code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module EXERCICIO1;
// ------------------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [3:0] c;
reg [3:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0031 - Jose Ferreira Reis Fonseca - 405808");
$display("Test number system");
a = 2... | 7.831328 |
module EXERCICIO2;
// ------------------------- definir dados
reg [5:0] a;
reg [5:0] b;
reg [3:0] c;
reg [9:0] d;
reg [5:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0032 - Jose Ferreira Reis Fonseca - 405808");
$display("Test number system");
a = 6... | 6.80266 |
module EXERCICIO3;
// ------------------------- definir dados
reg [5:0] a;
reg [5:0] b;
reg [3:0] c;
reg [4:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0033 - Jose Ferreira Reis Fonseca - 405808");
$display("Test number system");
a = 6... | 7.037054 |
module EXERCICIO4;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0034 - Jose Ferreira Reis Fonseca - 405808");
$display("Test number system");
a = 8... | 7.257924 |
module EXERCICIO5;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [3:0] e;
// ------------------------- parte principal
initial begin
$display("\nExercicio0035 - Jose Ferreira Reis Fonseca - 405808");
$display("Test number system");
a = 8... | 7.758722 |
module complemento2_2;
// -- definir bits dos registradores
reg [0:7] a;
reg [0:6] b;
reg [0:5] c;
reg [0:4] d;
reg [0:7] e;
// -- parte principal
initial begin : main
$display("Exercicio 004 - Débora Deslandes de Almeida Batista - 451549");
a = -('b101111);
b = -'d57;
c = -'d25;
... | 7.392663 |
module halfAdder (
s,
carryOut,
a,
b
);
//------- VARIVEIS --------
output s;
output carryOut;
input a, b;
//------- DESCRIO --------
xor xor1 (s, a, b);
and and1 (carryOut, a, b);
endmodule
| 7.256462 |
module fullAdder5b (
s,
carryOut,
a,
b,
carryIn
);
//------- VARIVEIS --------
output [4:0] s;
output carryOut;
input [4:0] a, b;
input carryIn;
wire co0, co1, co2, co3;
//------- DESCRIO --------
fullAdder FA1 (
s[0],
co0,
a[0],
b[0],
carryIn
);
ful... | 6.866137 |
module sinalAdd (
o,
men,
mai,
sa,
sb
);
//------- VARIVEIS --------
input men, mai, sa, sb;
output o;
wire aneg, apos;
and andneg (aneg, men, sb);
and andpos (apos, mai, sa);
or orout (o, aneg, apos);
endmodule
| 7.392043 |
module fa5bS (
sin,
s,
sinala,
a,
sinalb,
b
);
//------- VARIVEIS --------
input [4:0] a, b;
input sinala, sinalb;
output [4:0] s;
output sin;
wire [4:0] compa, compb, soma, compsom;
wire ig, men, mai, lost;
//------- DESCRIO --------
Compl26th ca (
compa,
a,
... | 7.855599 |
module test_fullAdder5bS;
// ------------------------- definir dados
reg [4:0] x, y;
reg sx, sy;
wire [4:0] saida, xi, yi;
wire ss, sxi, syi;
assign sxi = sx;
assign syi = sy;
assign xi = x;
assign yi = y;
// ------------------------- Operaes
fa5bS FA1 (
ss,
saida,
sxi,
... | 7.258892 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
reg carryI;
wire carryO;
wire [5:0] sub;
fullAdder modulo (
sub,
carryO,
x,
y,
carryI
);
// ------------------------- parte principal
initial begin
$display("Exercicio 0042... | 7.258892 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
wire [5:0] igual;
fullAdder modulo (
igual,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exercicio 0043 - Pedro Henrique A. M. de Carvalho - 427452");
... | 7.258892 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
wire [5:0] diferente;
fullAdder modulo (
diferente,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exercicio 0044 - Pedro Henrique A. M. de Carvalho - 42745... | 7.258892 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg y;
wire [5:0] c2;
fullAdder modulo (
c2,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exercicio 0045 - Pedro Henrique A. M. de Carvalho - 427452");
$display("Tes... | 7.258892 |
module halfAdder (
s,
carryOut,
a,
b
);
//------- VARIVEIS --------
output s;
output carryOut;
input a, b;
//------- DESCRIO --------
xor xor1 (s, a, b);
and and1 (carryOut, a, b);
endmodule
| 7.256462 |
module fullAdder5b (
s,
carryOut,
a,
b,
carryIn
);
//------- VARIVEIS --------
output [4:0] s;
output carryOut;
input [4:0] a, b;
input carryIn;
wire co0, co1, co2, co3;
//------- DESCRIO --------
fullAdder FA1 (
s[0],
co0,
a[0],
b[0],
carryIn
);
ful... | 6.866137 |
module sinalAdd (
o,
men,
mai,
sa,
sb
);
//------- VARIVEIS --------
input men, mai, a, b;
output o;
wire [4:0] xors, ands;
//------- DESCRIO --------
xor xor1 (xors[0], a[0], b[0]);
xor xor2 (xors[1], a[1], b[1]);
xor xor3 (xors[2], a[2], b[2]);
xor xor4 (xors[3], a[3], b[3]);
x... | 7.392043 |
module fa5bS (
sinal,
s,
a,
b
);
//------- VARIVEIS --------
input [4:0] a, b;
output [4:0] s;
output sinal;
wire [4:0] compa, compb;
//------- DESCRIO --------
Compl26th(
compa, a, sinal
);
endmodule
| 7.855599 |
module test_fullAdder5bS;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
reg carryIn = 0;
wire [5:0] soma;
wire [5:0] saida;
wire carryOut;
// ------------------------- Operaes
wire [5:0] xi;
wire [5:0] yi;
Compl26th c26b1 (
xi,
x
);
Compl26th c26b2 (
y... | 7.258892 |
module complemento2_3;
// -- definir bits dos registradores
reg [0:7] a;
reg [0:7] b;
reg [0:7] c;
reg [0:7] d;
reg [0:7] e;
// -- parte principal
initial begin : main
$display("Exercicio 005 - Débora Deslandes de Almeida Batista - 451549");
a = -('b101011 - 'b1001);
b = -('b10011 - 'o15)... | 7.392663 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
reg carryI;
wire carryO;
wire [5:0] soma;
fullAdder modulo (
soma,
carryO,
x,
y,
carryI
);
// ------------------------- parte principal
initial begin
$display("Exercicio 00... | 7.258892 |
module igualZero (
output r,
input [5:0] ent
);
assign r = (~(ent[0] || ent[1] || ent[2] || ent[3] || ent[4] || ent[5])); //recebe o sinal e pega qualquer sinal diferente de 0 depois nega
endmodule
| 8.024836 |
module test_fullAdder;
// ------------------------- definir dados
reg [5:0] x;
reg [5:0] y;
reg carryI;
wire carryO;
wire [5:0] soma;
wire zero;
fullAdder modulo (
soma,
carryO,
x,
y,
carryI
);
igualZero modulo (
zero,
soma
);
// ----------------------... | 7.258892 |
module pand (
output s,
input p,
input q,
input e,
input f
);
//cria vinculo
assign s = (p & q & e & f);
//terminar
endmodule
| 7.781159 |
module leftShift (
d,
clk
);
input d, clk;
wire q1, q2, q3, q4;
wire qnot1, qnot2, qnot3, qnot4;
dff flip1 (
q1,
qnot1,
d,
clk
);
dff flip2 (
q2,
qnot2,
q1,
clk
);
dff flip3 (
q3,
qnot3,
q2,
clk
);
dff flip4 (
q4,
... | 7.132145 |
module leftShift (
input d,
input clk,
input [3:0] preset,
input clear
);
wire q1, q2, q3, q4;
wire qnot1, qnot2, qnot3, qnot4;
dff2 flip1 (
q1,
qnot1,
d,
clk,
preset[0],
clear
);
dff2 flip2 (
q2,
qnot2,
q1,
clk,
preset[1],
... | 7.132145 |
module rightShift (
input d,
input clk,
input [3:0] preset,
input clear
);
wire w0, q1, q2, q3, q4;
wire qnot1, qnot2, qnot3, qnot4;
or or1 (w0, q4, d);
dff2 flip1 (
q1,
qnot1,
w0,
clk,
preset[0],
clear
);
dff2 flip2 (
q2,
qnot2,
q1,
... | 6.888079 |
module leftShift (
input d,
input clk,
input [3:0] preset,
input clear
);
wire w0, q1, q2, q3, q4;
wire qnot1, qnot2, qnot3, qnot4;
or or1 (w0, qnot4, d);
dff2 flip1 (
q1,
qnot1,
w0,
clk,
preset[0],
clear
);
dff2 flip2 (
q2,
qnot2,
q1,
... | 7.132145 |
module rightShift (
input d,
input clk,
input [3:0] preset,
input clear
);
wire w0, q1, q2, q3, q4;
wire qnot1, qnot2, qnot3, qnot4;
or or1 (w0, q4, d);
dff2 flip1 (
q1,
qnot1,
w0,
clk,
preset[0],
clear
);
dff2 flip2 (
q2,
qnot2,
q1,
... | 6.888079 |
module rightShift (
input d,
input clk,
input [3:0] preset,
input clear
);
wire w0, q1, q2, q3, q4;
wire qnot1, qnot2, qnot3, qnot4;
or or1 (w0, q4not, d);
dff2 flip1 (
q1,
qnot1,
w0,
clk,
preset[0],
clear
);
dff2 flip2 (
q2,
qnot2,
q1,
... | 6.888079 |
module pand (
output s,
input p,
input q
);
//cria vinculo
assign s = (p & q);
//terminar
endmodule
| 7.781159 |
module nandgate (
output s,
input p,
q
);
assign s = ~(p & q);
endmodule
| 7.298658 |
module test_base_01;
// ------------------------- definir dados
reg [4:0] a;
reg [4:0] b;
reg [4:0] c;
reg [4:0] d;
reg [4:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio01 - Adamo Ludwig - 473319");
a = 3 + 14;
b = 3 * 8;
c = 33 / 5;
d = 25 - 11;... | 6.932753 |
module por (
output s,
input p,
input q
);
//cria vinculo
assign s = (p | q);
//terminar
endmodule
| 7.223992 |
module ram2x4 (
output [3:0] s,
input [3:0] x,
input clk,
input readWrite,
input address,
input clear
);
reg demuxIn;
wire w0, w1;
wire [3:0] aux0;
wire [3:0] aux1;
dmx1bit dmx1 (
w0,
w1,
demuxIn,
address
);
ram1x4 ram1 (
aux0,
x,
clk,
... | 6.763999 |
module ram1x8 (
output [7:0] s,
input [7:0] x,
input clk,
input readWrite,
input address,
input clear
);
ram1x4 ram1 (
s[3:0],
x[3:0],
clk,
readWrite,
address,
clear
);
ram1x4 ram2 (
s[7:4],
x[7:4],
clk,
readWrite,
address,
... | 6.890243 |
module ram1x16 (
output [15:0] s,
input [15:0] x,
input clk,
input readWrite,
input address,
input clear
);
ram1x4 ram0 (
s[3:0],
x[3:0],
clk,
readWrite,
address,
clear
);
ram1x4 ram1 (
s[7:4],
x[7:4],
clk,
readWrite,
addres... | 6.860417 |
module ram4x8 (
output [7:0] s,
input [7:0] x,
input clk,
input readWrite,
input [1:0] address,
input clear
);
reg entradaDmx;
wire [3:0] w;
wire [7:0] aux0, aux1, aux2, aux3;
dmx2bits dmx1 (
w,
entradaDmx,
address
);
ram1x8 ram0 (
aux0,
x,
clk,... | 6.552052 |
module dff (
output q,
output qnot,
input d,
input clk,
input clear
);
reg q;
reg qnot;
always @(posedge clk) begin
q <= d;
qnot <= ~q;
end
endmodule
| 7.02102 |
module MEIASOMA (
saida,
carry,
a,
b
);
input a, b;
output saida, carry;
xor xor1 (saida, a, b);
and and1 (carry, a, b);
endmodule
| 7.555932 |
module SOMACOMPLETA (
soma,
carryout,
a,
b,
carryin
);
input a, b, carryin;
output soma, carryout;
wire temp2;
MEIASOMA MeiaSoma1 (
saida,
carry,
a,
b
);
MEIASOMA MeiaSoma2 (
soma,
temp2,
saida,
carryin
);
or OR1 (carryout, temp2, carr... | 6.785832 |
module SOMADOR4BITS (
saida,
carryout,
a,
b
);
input [3:0] a, b;
output [3:0] saida;
output carryout;
wire carryout1, carryout2, carryout3;
MEIASOMA MEIASOMA1 (
saida[0],
carryout1,
a[0],
b[0]
);
SOMACOMPLETA SOMACOMPLETA1 (
saida[1],
carryout2,
... | 7.135259 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR (s0, a, b);
and AND (s1, a, b);
endmodule
| 7.813544 |
module somacompleta (
s0,
s1,
a,
b,
c
);
output s0, s1;
input a, b, c;
meiasoma M0 (
s2,
s3,
a,
b
);
meiasoma M1 (
s0,
s4,
c,
s2
);
or OR0 (s1, s3, s4);
endmodule
| 7.045629 |
module // somaquatrobits
module ALU (s, comp, a, b);
input [3:0] a, b;
output [3:0] s;
output comp;
comparacao COMP0 ( comp, a, b );
somaquatrobits SC4 ( s, v, v0, a, b);
endmodule
| 6.519048 |
module testnorgate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
norgate NOR1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0; //atribuicao simultanea dos valores iniciais
end
//parte principal
initial be... | 6.695863 |
module test_base_01;
// ------------------------- definir dados
reg [6:0] a;
reg [9:0] b;
reg [3:0] c;
reg [6:0] d;
reg [9:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio02 - Adamo Ludwig - 473319");
a = 6'b100110 + 5'b11011;
b = 5'b11101 * 6'o25;
c =... | 6.932753 |
module testandgate;
// ------------------------- dados locais
reg a, b, c, d, e, f, g, h, i; // definir registradores
wire l, m, n, o, p, q, r, s, t1, t2, t3, t4, t5, t6, t7, t8; // definir conexao (fio)
// ------------------------- instancia
xor XOR1 (l, ~a, 1);
and AND1 (t1, ~a, 1);
xor XOR2 (m, ~... | 6.553783 |
module DIFERENCACOMPLETA (
diferenca,
sinal,
a,
b,
c
);
output diferenca, sinal;
input a, b, c;
wire temp1, temp2, temp3;
MEIADIFERENCA MEIADIFERENCA1 (
temp1,
temp2,
a,
b
);
MEIADIFERENCA MEIADIFERENCA2 (
diferenca,
temp3,
c,
temp1
);
... | 7.242596 |
module DIFERENCACOMPLETA3BITS (
diferenca,
sinal,
a,
b
);
output [2:0] diferenca;
output sinal;
input [2:0] a, b;
wire sinal1, sinal2;
MEIADIFERENCA MEIADIFERENCA1 (
diferenca[0],
sinal1,
a[0],
b[0]
);
DIFERENCACOMPLETA DIFERENCACOMPLETA1 (
diferenca[1],
... | 7.242596 |
module TESTESUBTRATOR;
reg [2:0] a, b;
wire [2:0] diferenca;
wire sinal;
integer i, j;
DIFERENCACOMPLETA3BITS DIFERENCACOMPLETA3BITS1 (
diferenca,
sinal,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
#1 $display(" Larissa Fernandes Leijot... | 6.580683 |
module meiadiferenca (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR (s0, a, b);
and AND (s1, ~a, b);
endmodule
| 7.462199 |
module xnorgate (
output s,
input p,
q
);
assign s = ~(p ^ q);
endmodule
| 6.74222 |
module testxnorgate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
xnorgate XNOR1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0; //atribuicao simultanea dos valores iniciais
end
//parte principal
initial... | 7.028584 |
module test_base_01;
// ------------------------- definir dados
reg [5:0] a;
reg [4:0] b;
reg [5:0] c;
reg [6:0] d;
reg [4:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio03 - Adamo Ludwig - 473319");
a = ~(6'b101010) + 1;
b = ~(6'o25) + 1;
c = ~(27) +... | 6.932753 |
module meiasoma (
s0,
s1,
a,
b
);
output s0, s1;
input a, b;
xor XOR (s0, a, b);
and AND (s1, a, b);
endmodule
| 7.813544 |
module somacompleta (
s0,
s1,
a,
b,
c
);
output s0, s1;
input a, b, c;
meiasoma M0 (
s2,
s3,
a,
b
);
meiasoma M1 (
s0,
s4,
c,
s2
);
or OR0 (s1, s3, s4);
endmodule
| 7.045629 |
module testnandmorgangate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
nandmorgangate NANDMORGAN1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0; //atribuicao simultanea dos valores iniciais
end
//parte pr... | 8.63586 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [7:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio04 - Adamo Ludwig - 473319");
a = ~(6'b101111) + 1;
b = ~(6'b111001) + 1;
c = ~(2... | 6.932753 |
module testnormorgangate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
normorgangate NORMORGAN1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0; //atribuicao simultanea dos valores iniciais
end
//parte princ... | 7.610532 |
module teste_Exercicio03;
// ------------------------- definir dados
reg [7:0] entrada;
reg clk;
reg addr;
reg rw;
reg clr;
wire [7:0] saida;
// ------------------------- instancia
Exercicio04 mod1 (
saida,
entrada,
clk,
addr,
rw,
clr
);
// --------------... | 6.977534 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
reg [6:0] b;
reg [5:0] c;
reg [4:0] d;
reg [7:0] e;
// ------------------------- parte principal
initial begin
$display("Exercicio05 - Adamo Ludwig - 473319");
a = 6'b101011 + (~(6'b001001) + 1);
b = 6'b10011 + (~(6... | 6.932753 |
module full_difference (
s,
fso1,
fsi0,
fsi1,
fsi2
);
output s, fso1;
input fsi0, fsi1, fsi2;
wire w0, w1, w2;
half_difference HALFSUB1 (
w0,
w1,
fsi0,
fsi1
);
half_difference HALFSUB2 (
fso0,
w2,
w0,
fsi2
);
or OR1 (fso1, w1, w2);
en... | 6.791438 |
module Exercicio0504;
reg [3:0] A, B;
wire [3:0] S;
wire [1:0] W;
fulladd FULLADD1 (
S[0],
W[0],
A[0],
B[0],
0
);
fulladd FULLADD2 (
S[1],
W[1],
A[1],
B[1],
W[0]
);
fulladd FULLADD3 (
S[2],
S[3],
A[2],
B[2],
W[1]... | 7.280671 |
module xorexpressiongate (
output s,
input p,
input q
);
assign s = (~p & q) | (p & ~q);
endmodule
| 8.114759 |
module testxorexpressiongate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
xorexpressiongate XOREXPRESSION1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0;
end
//parte principal
initial begin : main
$... | 8.249463 |
module xorgate (
output [0:3] s,
input [0:3] p,
input [0:3] q
);
assign s = (~p & q) + (p & ~q);
endmodule
| 7.421731 |
module testxorgate;
// ------------------------- dados locais
reg [0:3] a, b; // definir registrador
wire [0:3] s; // definir conexao (fio)
// ------------------------- instancia
xorgate XOR1 (
s,
a,
b
); // ------------------------- preparacao
initial begin : start
a = 4'b0011; ... | 6.716539 |
module fulladder (
a,
b,
cin,
s,
co
);
input a, b, cin;
output s, co;
wire t1, t2, t3;
xor xor_1 (s, a, b, cin);
and and_1 (t1, a, b), and_2 (t2, a, cin), and_3 (t3, b, cin);
or or_1 (co, t1, t2, t3);
endmodule
| 7.454465 |
module soma (
a,
b,
s,
cout,
ovr
);
output [3:0] s;
output cout, ovr;
input [3:0] a;
input [3:0] b;
wire c0, c1, c2, c_out, not_ovr;
halfadder HA (
a[0],
b[0],
s[0],
c0
);
fulladder FA1 (
a[1],
b[1],
c0,
s[1],
c1
);
fulladder ... | 7.220261 |
module comp1 (
output s,
input [1:0] a,
input [1:0] b
);
wire [1:0] s1;
// portas logicas
xor X1 (s1[0], a[0], b[0]);
xor X2 (s1[1], a[1], b[1]);
or O1 (s, s1[1], s1[0]);
endmodule
| 6.578325 |
module test_comp1;
// ------------------------- definir dados
reg [1:0] x;
reg [1:0] y;
wire z;
comp1 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exercicio06 - Willian Antonio dos Santos - 462020");
$display("Teste do comparador");
... | 6.804646 |
module xnorexpressiongate (
output s,
input p,
q
);
assign s = (p & q) | (~p & ~q);
endmodule
| 7.149412 |
module testxnorexpressiongate;
//dados locais
reg a, b; //definir registradores
wire s; //definir conexao (fio)
//instancia
xnorexpressiongate XNOREXPRESSION1 (
s,
a,
b
);
//preparacao
initial begin : start
a = 0;
b = 0; //atribuicao simultanea dos valores iniciais
end
... | 7.821234 |
module XNORgate (
output s,
input p,
q
);
assign s = (p & q) | (~p & ~q);
endmodule
| 6.59064 |
module testXNORgate;
// ------------------------- dados locais
reg a, b; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
XNORgate XNOR1 (
s,
a,
b
);
// ------------------------- preparacao
initial begin : start
// atribuicao simult... | 8.437605 |
module fulladder (
a,
b,
cin,
s,
co
);
input a, b, cin;
output s, co;
wire t1, t2, t3;
xor xor_1 (s, a, b, cin); // ISOLAR AS OPERACOES: COMPLEMENTO DE 1, 2 ...
and and_1 (t1, a, b), and_2 (t2, a, cin), and_3 (t3, b, cin);
or or_1 (co, t1, t2, t3);
endmodule
| 7.454465 |
module soma (
a,
b,
s,
cout,
ovr
);
output [3:0] s;
output cout, ovr;
input [3:0] a;
input [3:0] b;
wire c0, c1, c2, c_out, not_ovr;
halfadder HA (
a[0],
b[0],
s[0],
c0
);
fulladder FA1 (
a[1],
b[1],
c0,
s[1],
c1
);
fulladder ... | 7.220261 |
module comp2 (
output s,
input [1:0] a,
input [1:0] b
);
wire [1:0] s1;
wire [1:0] s2;
wire [1:0] s3;
wire s4;
wire [1:0] s5;
// Portas logicas
// Complemento de 1 e soma 1 ja inserido para fazer a subtracao 3 bits de a - b
// O ultimo bit e' o sinal e consequentemente indica qual numero e' ... | 6.712072 |
module test_comp2;
// ------------------------- definir dados
reg [1:0] x;
reg [1:0] y;
wire z;
comp2 modulo (
z,
x,
y
);
// ------------------------- parte principal
initial begin
$display("Exercicio07 - Willian Antonio dos Santos - 462020");
$display("Teste do comparador, mai... | 6.665683 |
module and3entradasgate (
output s,
input p,
input q,
input r
);
assign s = p & q & r;
endmodule
| 7.930345 |
module testand3entradasgate;
//dados locais
reg a, b, c; //definir registradores
wire s; //definir conexao (fio)
//instancia
and3entradasgate AND3ENTRADAS1 (
s,
a,
b,
c
);
//preparacao
initial begin : start
a = 0;
b = 0;
c = 0; //atribuicao simultanea dos valore... | 6.944285 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// atribuic... | 6.553783 |
module and3entradascompostogate (
output s,
input p,
input q,
input r
);
assign s = ((~p) | (~q)) & r;
endmodule
| 7.309675 |
module testand3entradascompostogate;
//dados locais
reg a, b, c; //definir registradores
wire s; //definir conexao (fio)
//instancia
and3entradascompostogate AND3ENTRADASCOMPOSTO1 (
s,
a,
b,
c
);
//preparacao
initial begin : start
a = 0;
b = 0;
c = 0; //atribuic... | 6.944285 |
module andgate1 (
output s1,
input p,
input q,
input r
);
wire temp1, st; // st uma variavel temporaria
andgate AND1 (
temp1,
p,
q
);
assign st = temp1 & r;
assign s1 = st;
endmodule
| 7.154508 |
module testandgate;
// ------------------------- dados locais
reg a, b, c; // definir registradores
wire s; // definir conexao (fio)
// ------------------------- instancia
andgate1 AND1 (
s,
a,
b,
c
);
// ------------------------- preparacao
initial begin : start
// atribui... | 6.553783 |
module nandgate (
output s,
input p,
input q
);
assign s = ~(p & q);
endmodule
| 7.298658 |
module or3entradasgate (
output s,
input p,
input q,
input r
);
assign s = p | ~((~p) & (~r));
endmodule
| 7.467002 |
module testor3entradasgate;
//dados locais
reg a, b, c; //definir registradores
wire s; //definir conexao (fio)
//instancia
or3entradasgate OR3ENTRADAS1 (
s,
a,
b,
c
);
//preparacao
initial begin : start
a = 0;
b = 0;
c = 0; //atribuicao simultanea dos valores i... | 7.642925 |
module orgate1 (
output s,
input p,
input q,
input r
);
wire temp1, st; // variaveis temporarias
orgate OR1 (
temp1,
p,
q
);
assign st = temp1 | r;
assign s = st;
endmodule
| 7.52022 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] n;
wire [3:0] q;
wire [3:0] qnot;
wire w;
and E (w, address, rw, clk);
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not ... | 6.842395 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] q;
wire [3:0] qnot;
wire [3:0] n;
wire w;
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not N2 (n[2], data[1]);
not N3 (n[... | 6.842395 |
module RAM2X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire add0;
wire add1;
wire [3:0] r1;
wire [3:0] r2;
seletor1in2out SA (
add0,
add1,
address,
1
);
RAM1X4 R1 (
... | 6.765373 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] q;
wire [3:0] qnot;
wire [3:0] n;
wire w;
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not N2 (n[2], data[1]);
not N3 (n[... | 6.842395 |
module RAM1X8 (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X4 R1 (
o[3:0],
data[3:0],
address,
rw,
clk,
clr
);
RAM1X4 R2 (
o[7:4],
data[7:4],
addre... | 7.029692 |
module RAM1X4 (
o,
data,
address,
rw,
clk,
clr
);
output [3:0] o;
input [3:0] data;
input address;
input rw;
input clk;
input clr;
wire [3:0] q;
wire [3:0] qnot;
wire [3:0] n;
wire w;
not N0 (n[0], data[3]);
not N1 (n[1], data[2]);
not N2 (n[2], data[1]);
not N3 (n[... | 6.842395 |
module RAM1X8 (
o,
data,
address,
rw,
clk,
clr
);
output [7:0] o;
input [7:0] data;
input address;
input rw;
input clk;
input clr;
RAM1X4 R1 (
o[3:0],
data[3:0],
address,
rw,
clk,
clr
);
RAM1X4 R2 (
o[7:4],
data[7:4],
addre... | 7.029692 |
module MUX8Bits (
s,
data0,
data1,
address
);
output [7:0] s;
input [7:0] data0;
input [7:0] data1;
input address;
reg [7:0] s;
always @(address or data1 or data0) begin
if (~address) begin
s = data0;
end else begin
s = data1;
end
end
endmodule
| 6.955345 |
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