code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module address_gen (
d_in,
addr
);
input [31:0] d_in;
output [10:0] addr;
wire [1:0] diff;
assign diff = d_in[18:16] - 3'd1;
assign addr = {diff, d_in[15:7]};
endmodule
| 6.808832 |
module prcess exponent matching in
* float add/sub operation.
*
* parameter
* EW: float exponent width
* MW: float mantisa width
* FW: float width
*
* ports:
* float0_i:
* float1_i: two input float data
* exp_o: exponent after exponent matching
* close_o: flag indicates exponen are same
* sgn_big_o: sg... | 8.515016 |
module exp_nine_picture (
clk,
reset,
VGA_R,
VGA_G,
VGA_B,
VGA_HS,
VGA_VS,
VGA_CLK,
VGA_SYNC_N,
VGA_BLANK_N
);
input clk;
input reset;
output [7:0] VGA_R;
output [7:0] VGA_G;
output [7:0] VGA_B;
output VGA_HS, VGA_VS;
output VGA_CLK;
output VGA_BLANK_N;
output V... | 6.509808 |
module exp_test ();
reg [15:0] x = 0;
reg clk = 1, rst = 1, start = 0;
wire done;
wire [1:0] integer_part;
wire [15:0] fractional_part;
exponential test (
.clk(clk),
.rst(rst),
.start(start),
.x(x),
.done(done),
.intpart(integer_part),
.fracpart(fractional_part)
... | 6.716077 |
module exp_unit (
exp_a,
exp_b,
exp_c,
shamt,
ab_req
);
//8 bit inputs exp_a, exp_b and exp_c for the three exponents
input [7:0] exp_a, exp_b, exp_c;
//outputs shamt and ab_req for returning shift amount and whether trivial or not
output [7:0] shamt;
output ab_req;
assign shamt = e... | 6.6031 |
module exp_wrapper (
input clk,
rst,
start,
input [15:0] frac,
input [1:0] ui,
input [3:0] n,
output done
);
wire en_shift, en_shift2, exp_start, f_read, f_write, ui_shift;
wire done_exp;
exp_wrapper_dp dp (
clk,
rst,
ui,
frac,
ui_shift,
done,
... | 6.996108 |
module exp_wrapper_dp (
input clk,
rst,
input [1:0] ui,
input [15:0] frac,
input ui_shift,
done,
en_shift,
en_shift2,
exp_start,
f_read,
f_write,
output done_exp
);
wire [ 1:0] intpart;
wire [15:0] fracpart;
wire [15:0] frac_shift;
wire [21:0] exp_out;
shifter ... | 6.505323 |
module exp_wrapper_TB ();
reg clk, rst, start;
wire done;
reg [3:0] n;
reg [1:0] ui;
reg [15:0] fracpart;
exp_wrapper wx_wrapper (
clk,
rst,
start,
fracpart,
ui,
n,
done
);
initial begin
clk = 1'b0;
rst = 1'b0;
ui = 2'b00;
//fracpart = 16'b000... | 6.508721 |
module xnorgate (
output s,
input a,
input b
);
assign s = ((a & b) | ((~a) & (~b)));
endmodule
| 6.74222 |
module testxnorgate;
//------------ dados locais
reg a, b;
wire s;
//----------- instancia
xnorgate XNOR1 (
s,
a,
b
);
//--------- preparacao
initial begin : start
a = 0;
b = 0;
end
//--------- parte principal
initial begin
$display("Exercicio07 - Ana Carolina - 44... | 7.028584 |
module exreg (
input wire clk,
input wire flush,
input wire alualtsrcin,
input wire [1:0] alusrcin,
input wire [1:0] regdstin,
input wire [2:0] aluopin,
output wire alualtsrcout,
output wire [1:0] alusrcout,
output wire [1:0] regdstout,
output wire [2:0] aluopout
);
// interna... | 7.534926 |
module exs (
input clk,
input rst,
input c_is_lw_in,
input c_mem_we_in,
input c_reg_data_in,
input c_reg_addr_in,
input c_reg_we_in,
input [13:0] ca_in,
input [ 1:0] c_alu_src_in,
input [31:0] rs_value_in,
input [31:... | 7.963916 |
module EXSegReg (
input wire clk,
input wire rst,
input wire en,
input wire clear,
//数据信号
input wire [31:0] PCD,
output reg [31:0] PCE,
input wire [31:0] BrPCD,
output reg [31:0] BrPCE,
input wire [31:0] ImmD,
output reg [31:0] ImmE,
input wire [4:0] RdD,
output reg [... | 6.863677 |
module EXT #(
parameter WIDTH = 16
) (
input [WIDTH-1:0] numb,
input isSign, //1зš0
//input ena,//Ч
output [31:0] res
);
reg [31:0] tmp = 32'b0;
assign res = tmp;
integer i;
always @(*) begin
if (isSign) begin
for (i = 31; i >= WIDTH; i = i - 1) tmp[i] = numb[WIDTH-1];
tmp[... | 7.969209 |
module EXT11_16 (
input [10:0] in,
output [15:0] out
);
assign out = {{(5) {in[10]}}, in};
endmodule
| 7.447677 |
module Ext16 (
input [15 : 0] imem15_0,
output [31 : 0] to_mux4
);
assign to_mux4 = {{(16) {1'b0}}, imem15_0};
endmodule
| 7.406638 |
module EXT16T32 (
X,
Se,
Y
);
input [15:0] X;
input Se;
output [31:0] Y;
wire [31:0] E0, E1;
wire [15:0] e = {16{X[15]}};
parameter z = 16'b0;
assign E0 = {z, X};
assign E1 = {e, X};
MUX2X32 i (
E0,
E1,
Se,
Y
);
endmodule
| 7.17123 |
module EXT5T32 (
X,
Y
);
input [4:0] X;
output [31:0] Y;
parameter z = 27'b0;
assign Y = {z, X};
endmodule
| 7.886355 |
module ext16_1 #(
parameter DEPTH = 16
) (
input [DEPTH-1:0] a,
output reg [31:0] b
);
always @(a) begin
b[31:0] = 32'h00000000;
b[31:DEPTH] = a[DEPTH-1:0];
end
endmodule
| 8.42203 |
module ext16_32 (
input [15:0] datai,
input sign,
output [31:0] datao
);
assign datao = (sign == 0 || datai[15] == 0) ? {16'h0000, datai} : {16'hffff, datai};
endmodule
| 8.408392 |
module Ext18 (
input [15 : 0] imem15_0_18,
output [31 : 0] to_mux4_18
);
assign to_mux4_18 = {{(14) {imem15_0_18[15]}}, imem15_0_18, 2'b00};
endmodule
| 6.65867 |
module ext24 #(
parameter depth = 8
) (
input [depth-1:0] a,
input sign_ext,
output reg [31:0] b
);
always @(a or sign_ext) begin
if (sign_ext == 1 && a[depth-1] == 1) begin
b[31:0] = 32'hffffffff;
b[depth-1:0] = a[depth-1:0];
end else begin
b[31:0] = 32'h00000000;
b[... | 8.977964 |
module Ext5 (
input [ 4 : 0] sa,
output [31 : 0] to_mux3
);
assign to_mux3 = {{(32 - 5) {1'b0}}, sa};
endmodule
| 7.760794 |
module ext532 (
input [4:0] datai,
input sign,
output [31:0] datao
);
assign datao = (sign == 0 || datai[4] == 0) ? {27'b0, datai} : {27'h7ffffff, datai};
endmodule
| 6.569301 |
module EXT5_16 (
input [ 4:0] in,
output [15:0] out
);
assign out = {{(11) {in[4]}}, in};
endmodule
| 7.600672 |
module EXT8_16 (
input [ 7:0] in,
output [15:0] out
);
assign out = {{(8) {in[7]}}, in};
endmodule
| 7.519923 |
module EXTdm (
input [31:0] dmout,
input [2:0] DMEXTop,
output reg [31:0] DMout
);
always @(*) begin
case (DMEXTop)
`DMEXT_LB: DMout = {{24{dmout[7]}}, dmout[7:0]};
`DMEXT_LH: DMout = {{16{dmout[15]}}, dmout[15:0]};
`DMEXT_LW: DMout = dmout;
`DMEXT_LBU: DMout = {24'b0, dmo... | 7.827646 |
module ext (
input [2:0] ext_switch,
input [4:0] iData_len5,
input [7:0] iData_len8,
input [15:0] iData_len16,
input [31:0] iData_len32,
output reg [31:0] oData
);
always @(*) begin
case (ext_switch)
`EXT5_Z: oData <= {27'b0, iData_len5};
`EXT16_SL2_S:
oData = iData_len... | 8.64485 |
module extend16 (
input [15:0] a,
input sign,
output [31:0] b
);
assign b = (sign == 0 || a[15] == 0) ? {16'b0, a} : {16'hffff, a};
endmodule
| 6.898263 |
module extend16to32 (
// input
input [15:0] extendee,
input ExtSel,
// output
output reg [31:0] result
);
integer i;
// assign result[15:0] = extendee[15:0];
// assign result[32:16] = 0;
always @(ExtSel or extendee) begin
for (i = 0; i < 16; i = i + 1) begin
result[i] <= extendee... | 7.163746 |
module extend5 (
input [ 4:0] a,
output [31:0] b
);
assign b = {27'b0, a};
endmodule
| 7.218732 |
module extendAddress (
toExtendAddress,
PCPlusFourAddress,
JumpAddress
);
input wire [25:0] toExtendAddress;
input wire [31:0] PCPlusFourAddress;
output wire [31:0] JumpAddress;
assign JumpAddress = {PCPlusFourAddress[31:28], toExtendAddress[25:0], {2{0}}};
//assign ExtendAddress = {pcPlusFour[31... | 7.228929 |
module extended #(
parameter half = 16
) (
input [half-1:0] in,
input ExtOp,
output reg [31:0] out
);
always @(in or ExtOp) out = (ExtOp) ? {{half{in[half-1]}}, in} : {{half{1'b0}}, in};
endmodule
| 7.062016 |
module Extender (
extendedImm,
imm,
immSrc
);
`include "../Parameters.vh"
input [XLEN - 8 : 0] imm; // [31..7] are the immediate number part of the instruction
input [1 : 0] immSrc; // Immediate number's width vary from different instruction types
output reg [XLEN - 1 : 0] extendedImm; // Extend... | 8.44234 |
module Extender21Bits (
in,
out
);
input [20:0] in;
output wire [31:0] out;
assign out = {{11{in[20]}}, in};
endmodule
| 7.443574 |
module extender_0 (
in,
out
);
parameter in_WIDTH = 12;
parameter out_WIDTH = 32;
input [in_WIDTH-1:0] in;
output reg [out_WIDTH-1:0] out;
always @(in) begin
out = {{(out_WIDTH - in_WIDTH) {1'b0}}, in};
end
endmodule
| 7.104602 |
module Extender_16_32 #(
parameter INPUT_SIZE = 16,
parameter OUTPUT_SIZE = 32
) (
input [(INPUT_SIZE-1):0] ext_input,
output reg [(OUTPUT_SIZE-1):0] ext_output
);
always @(*) begin
if (ext_input[15] == 1'b1) ext_output = {{16{1'b1}}, ext_input};
else ext_output = {{16{1'b0}}, ext_input};
... | 8.983239 |
module Extender_16_to_32 (
ExIn,
Neg,
ExOut
);
input [15:0] ExIn;
input Neg;
output reg [31:0] ExOut;
always @(*) begin
if (ExIn[15]) begin
if (Neg) ExOut <= {16'b1111111111111111, ExIn};
else ExOut <= {16'b0, ExIn};
end else ExOut <= {16'b0, ExIn};
end
endmodule
| 7.941829 |
module Extender_20090121 (
input [15:0] Imm,
input [1:0] Extop,
output reg [31:0] Ext_result
);
always @(*) begin
case (Extop)
2'b00: Ext_result <= {{16{1'b0}}, Imm}; // 零拓展
2'b01: Ext_result <= {{16{Imm[15]}}, Imm}; // 符号拓展
2'b10: Ext_result <= {Imm, {16{1'b0}}}; // lui拓展
e... | 7.610346 |
module Extender_26_32 #(
parameter INPUT_SIZE = 26,
parameter OUTPUT_SIZE = 32
) (
input [(INPUT_SIZE-1):0] ext_input,
output reg [(OUTPUT_SIZE-1):0] ext_output
);
always @(*) begin
if (ext_input[25] == 1'b1) ext_output = {{6{1'b1}}, ext_input};
else ext_output = {{6{1'b0}}, ext_input};
en... | 8.104877 |
module Extender_26_to_32 (
ExtenderIn,
ExtenderOut
);
input [25:0] ExtenderIn;
output reg [31:0] ExtenderOut;
always @(*) begin
if (ExtenderIn[25]) ExtenderOut <= {6'b111111, ExtenderIn};
else ExtenderOut <= {6'b0, ExtenderIn};
end
endmodule
| 7.56159 |
module Extender_8_to_16 (
ExIn,
ExOut
);
input [7:0] ExIn;
output reg [15:0] ExOut;
always @(*) begin
if (ExIn[7]) begin
ExOut <= {8'b11111111, ExIn};
end else ExOut <= {8'b0, ExIn};
end
endmodule
| 7.930669 |
module extender_j (
imm26,
d_out
);
input [25:0] imm26;
output reg [31:0] d_out;
wire [5:0] imm6_up;
assign imm6_up = {6{1'b0}};
always @* begin
d_out = {imm6_up, imm26};
end
endmodule
| 6.714673 |
module extender_next_pc (
imm16,
d_out
);
input [15:0] imm16;
output reg [31:0] d_out;
wire [15:0] imm15_up;
assign imm15_up = {16{1'b0}};
always @* begin
d_out = {imm15_up, imm16};
end
endmodule
| 6.840387 |
module extender_sign (
in,
out
);
parameter in_WIDTH = 12;
parameter out_WIDTH = 32;
input [in_WIDTH-1:0] in;
output reg [out_WIDTH-1:0] out;
always @(in) begin
out = {{(out_WIDTH - in_WIDTH) {in[in_WIDTH-1]}}, in};
end
endmodule
| 7.888736 |
module Extender_tb;
`include "../src/utils/Assert.vh"
`include "../src/Parameters.vh"
// Input stimulus
reg [XLEN - 1 : 0] instruction;
reg [6 : 0] opcode;
// Output
wire [XLEN - 1 : 0] extendedImm;
Extender DUT (
.extendedImm(extendedImm),
.imm(instruction[XLEN-1 : 7]),
.opcode(opco... | 6.514776 |
module ExtendRAM #(
parameter RTYPE = "ISPRAM", // RAMڲʵ
parameter ADDRW = 14, // RAMַ
parameter UNITW = 8, // RAMÿԪ
parameter GROUP = 4, // RAMÿ鵥Ԫ
parameter DEPTH = 2 ** 14 // RAM洢
) (
input CLK, // ʱ
input RST... | 7.72549 |
module ExtendSa (
input [ 4:0] sa,
output [31:0] extendedSa
);
assign extendedSa[31:5] = 0;
assign extendedSa[4:0] = sa;
endmodule
| 7.614874 |
module extend_16 (
input wire [10:0] Src,
output reg [15:0] Dest,
input wire [ 2:0] SrcGet
);
always @(*) begin
case (SrcGet)
// `IM0: begin
// Dest <= 0;
// end
`IM5: begin
Dest[4:0] <= Src[4:0];
Dest[15:5] <= (Src[4]) ? 11'b11111111111 : 11'b00000000000;
... | 7.349211 |
module extend_16_32 (
input [15:0] data_in,
input sign,
output [31:0] data_out
);
assign data_out = (sign == 0 || data_in[15] == 0) ? {16'b0, data_in} : {16'hffff, data_in};
endmodule
| 7.120758 |
module extend_sign_18_32 (
input [17:0] data_in,
output [31:0] data_out
);
assign data_out = (data_in[17] == 0) ? {14'b0, data_in} : {14'b11111111111111, data_in};
endmodule
| 7.413302 |
module extend_5_32 (
input [ 4:0] a,
output [31:0] b
);
assign b = {27'b0, a};
endmodule
| 6.894771 |
module extend_cut (
input [31:0] data_in,
input [2:0] EC_CS,
input SIGN_EC,
output [31:0] data_out
);
reg [31:0] temp;
always @(*) begin
case (EC_CS)
3'b001: temp <= {(SIGN_EC && data_in[15]) ? 16'hffff : 16'h0000, data_in[15:0]};
3'b010: temp <= {(SIGN_EC && data_in[7]) ? 24'hff... | 7.893301 |
module Extend_Imm (
input signed [19:0] In_Imm,
input Long_Imm,
output reg signed [31:0] Out_Imm
);
always @(In_Imm or Long_Imm) begin
if (Long_Imm) begin
Out_Imm <= {{12{In_Imm[19]}}, In_Imm};
end else begin
Out_Imm <= {{18{In_Imm[13]}}, In_Imm[13:0]};
end
end
endmodule
| 7.172863 |
module extend_rst (
input wire clk,
input wire clk_data,
output wire clk_data_reg
);
(* KEEP = "TRUE" *) reg clk_data_prev = 0;
always @(posedge clk) begin
clk_data_prev <= clk_data;
end
(* KEEP = "TRUE" *)reg [5:0] clk_data_count_reg = 0;
(* KEEP = "TRUE" *)reg [5:0] clk_data_count_next... | 6.925428 |
module extend_selector (
input [15:0] Instr,
input Extend_sel,
output reg [31:0] Ex_offset
);
always @(*) begin
if (Extend_sel == 1'b0) begin
Ex_offset[31:16] = 16'b0;
Ex_offset[15:0] = Instr[15:0];
end else begin
if (Instr[15] == 0) Ex_offset[31:16] = 16'b0;
else Ex_offse... | 7.876035 |
module extend_tb ();
reg [ 2:0] ImmSrc;
reg [31:0] Instruction;
wire [31:0] ExtImm;
extend UUT (
.ImmSrc(ImmSrc),
.Instr (Instruction[31:7]),
.ExtImm(ExtImm)
);
initial begin
ImmSrc <= 3'b000;
Instruction <= 32'h0FF00FF0;
#2 ImmSrc <= 3'b001;
Instruction <= 32'hFFFFFF8... | 6.762627 |
module extend_unit (
input [15:0] datain,
input ExtSel,
output reg [31:0] result
);
always @(datain or ExtSel) begin
result[15:0] <= datain[15:0]; //16λ
if (ExtSel == 1 && datain[15] == 1) result[31:16] <= 16'b1111_1111_1111_1111; //չȫΪ1
else result[31:16] = 0; //չȫΪ0
end
endmodule
| 6.708504 |
module extension (
imm16,
imm32,
extop
);
input [15:0] imm16;
input extop;
output [31:0] imm32;
reg [31:0] imm32;
always @(extop, imm16) begin
if (extop)//符号拓展
begin
if (imm16[15]) imm32 <= {16'hffff, imm16};
else imm32 <= {16'h0000, imm16};
end else imm32 <= {16'h000... | 8.026251 |
module extension_unit (
instruction,
immediate
);
// There are 5 flavors of extending immediates, which are used by various instructions:
// 5b zero extension,
// 5b sign extension,
// 8b zero extension,
// 8b sign extension,
// and 11b sign extension
input [15:0] instruction;
o... | 10.036226 |
module Extensor (
input [15:0] in,
output reg [31:0] out
);
always @(in) begin
out = {{15{1'b0}}, in};
end
endmodule
| 6.919099 |
module extensor16_32 (
entrada,
saida
);
// input
input [15:0] entrada;
// output
output [31:0] saida;
assign saida = {16'b0000000000000000, entrada};
endmodule
| 6.855165 |
module extensorSinal (
selectSize,
imm12,
imm16,
imm21,
imm9,
imm18,
out32
);
input [2:0] selectSize;
input [11:0] imm12;
input [15:0] imm16;
input [20:0] imm21;
input [8:0] imm9;
input [17:0] imm18;
output reg [31:0] out32;
parameter i16 = 3'b0, i21 = 3'b01, i9 = 3'b10, i18... | 7.606251 |
module extensorTeste;
//Inputs
reg [10:0] im_to_ext_i;
//Outputs
wire [10:0] ext_o; //Saída do mux
extensor DUT (
im_to_ext_i,
ext_o
);
initial begin
im_to_ext_i = 11'b1;
#5 im_to_ext_i = 11'b101;
#5 im_to_ext_i = 11'b101;
end
endmodule
| 6.783726 |
module extensor_tb;
parameter DATA_WIDTH = 32;
parameter IMM_WIDTH = 16;
//INPUTS
reg [DATA_WIDTH - 1:0] i_instruccion;
//OUTPUTS
wire [DATA_WIDTH - 1:0] o_branchoffset;
EXTENSOR extensorcito (
.i_instruccion (i_instruccion),
.o_branchoffset(o_branchoffset)
);
initial begin
i_instr... | 7.270438 |
module for the user design top level file. This module can be
// instantiated in the system and interconnect as shown in example design
//(example_top module).
// Revision History :
//*****************************************************************************
//`define SKIP_CALIB
`timescale 1ps/1ps
module Exte... | 8.702952 |
module for pmodAD2 that reads
// and translate measurments from U2 to bcd.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Revision 0.02 - Macro Created
// Additional Comments: using Verilog-2001 syntax.
//
// The `timescale directive specifies what the
// simulation time units are (1 ... | 6.898524 |
module External_CLK (
CLK,
RESET,
ADR_CLK_N,
ADR_CLK_P,
DATA_CLK_N,
DATA_CLK_P,
INC_CLK_N,
INC_CLK_P,
LATCH_CLK,
MAIN_CLK_N,
MAIN_CLK_P,
CLK_ENA,
OSC_ENA,
OSC_STABLE,
ASYNC_RESET,
SYNC_RESET
);
input CLK;
input RESET;
output ADR_CLK_N; // #DATA_VAL... | 6.512946 |
module DFFR_B (
clk,
nres,
d,
q,
nq
);
input clk;
input nres;
input d;
output q;
output nq;
reg val;
initial val = 1'bx;
always @(posedge clk) begin
if (clk) val <= d;
end
always @(*) begin
if (~nres) val <= 1'b0;
end
assign q = val;
assign nq = ~val;
endmodu... | 6.891278 |
module DR_LATCH (
ena,
nres,
d,
q,
nq
);
input ena;
input nres;
input d;
output q;
output nq;
reg val;
initial val = 1'b0;
always @(*) begin
if (ena) val = d;
if (~nres) val = 1'b0;
end
assign q = val;
assign nq = ~val;
endmodule
| 7.119516 |
module External_Mem (
clk,
rst,
Addr,
WriteData,
Read,
Write,
DataToCPU,
DataBus,
CS_RAM,
CS_Audio,
CS_Graphics,
CS_Spart,
CS_PS2,
switch
);
input clk, rst, Read, Write, switch;
input [3:0] Addr;
input [15:0] WriteData;
output [15:0] DataToCPU;
inout [15... | 7.183273 |
module
*
* Description: Treat the input as an IP header and compute the
* IP checksum. Compute the one's complement of the one's complement
* sum of the 16-bit words that compose the IP header.
*
* Completes in 3 cycles.
* Does not support IP options
*/
`timescale 1 ps / 1 ps
module @MODULE_NAME@
#(
pa... | 6.909746 |
module
*
* Description: split input data into RESULT_WIDTH size words and XOR all the words
* together to form the result. Essentially a very very simple hash function
*/
`timescale 1 ps / 1 ps
module @MODULE_NAME@
#(
parameter DATA_WIDTH = @DATA_WIDTH@,
parameter RESULT_WIDTH = @RESULT_WIDTH@
)
(
... | 6.909746 |
module @MODULE_NAME@
#(
parameter BITMASK_WIDTH = @BITMASK_WIDTH@,
parameter PKT_LEN_WIDTH = @PKT_LEN_WIDTH@
)
(
input clk_lookup,
input rst,
input tuple_in_@EXTERN_NAME@_input_VALID,
input [BITMASK_WIDTH+PKT_LEN_WIDTH:0] tuple_in_@EXTERN_NAME@_input_DATA,
... | 6.51334 |
module @MODULE_NAME@
#(
parameter LARGE_OP_WIDTH = @LARGE_OP_WIDTH@,
parameter SMALL_OP_WIDTH = @SMALL_OP_WIDTH@
)
(
// Data Path I/O
input clk_lookup,
input rst,
input tuple_in_@EXTERN_NAME@_... | 6.51334 |
module @MODULE_NAME@
#(
parameter TIMER_WIDTH = @TIMER_WIDTH@
)
(
// Data Path I/O
input clk_lookup,
input rst,
input tuple_in_@EXTERN_NAME@_input_VALID,
input [1:0] ... | 6.51334 |
module EXTImm (
input [2:0] IMEXTop,
input [31:0] instr,
output reg [31:0] IMM32
);
//以下译码出指令的立即数，不同指令类型由不同立即数编码形式
always @(*) begin
case (IMEXTop)
`ITYPE_IMM: IMM32 = {{20{instr[31]}}, instr[31:20]};
`STYPE_IMM: IMM32 = {{20{instr[31]}}, instr[31:25], instr[11:7]};
`BTYPE_IMM: I... | 8.746537 |
module extjtag (
sclk, // @negedge
pre_wen, // 1 cycle ahead of write data
di, // [31:0] data in (only some bits are used)
xpgmen, // enable programming mode for an external FPGA
xfpgaprog, // PROG_B to be sent to an external FPGA
xfpgatck, // TCK to be sent to an external FPGA
xfpgatm... | 7.08343 |
module EXTN (
input [31 : 0] dmem_data,
input [1 : 0] C_EXTN,
output reg [31 : 0] to_mux2
);
always @(*) begin
case (C_EXTN)
2'b00: to_mux2 = {{24{dmem_data[7]}}, dmem_data[7 : 0]}; //LB
2'b01: to_mux2 = {24'b0, dmem_data[7 : 0]}; //LBU
2'b10: to_mux2 = {{16{dmem_data[15]}}, ... | 7.995447 |
module ExToMem (
input clk,
reset,
input regwriteE,
input memtoregE,
input memwriteE,
output reg regwriteM,
output reg memtoregM,
output reg memwriteM,
input [4:0] rtE,
output reg [4:0] rtM,
input [31:0] alu_outE,
output reg [31:0] alu_outM,
input [31:0] write_dataE,
... | 6.804297 |
module questao1 (
output [3:0] s,
input addr,
input rw,
input clk,
input [3:0] i
);
memoria m1 (
s[0],
addr,
rw,
clk,
i[0]
);
memoria m2 (
s[1],
addr,
rw,
clk,
i[1]
);
memoria m3 (
s[2],
addr,
rw,
clk,
... | 6.77651 |
module questao2 (
output [3:0] s,
input addr,
input rw,
input clk,
input [3:0] i
);
wire [3:0] a0;
wire [3:0] a1;
questao1 q11 (
a0,
addr,
rw,
clk,
i
);
questao1 q12 (
a1,
~addr,
rw,
clk,
i
);
mux2x1 m (
s,
a0,
... | 7.414497 |
module buffer (
output s,
input a
);
assign s = a;
endmodule
| 6.861394 |
module mux2x8 (
output [7:0] s,
input [7:0] a0,
input [7:0] a1,
input c
);
reg [7:0] s = 8'b00000000;
always #1 begin
if (c) begin
s <= a0;
end else if (~c) begin
s <= a1;
end
end
endmodule
| 6.869828 |
module mux8x8 (
output [7:0] s,
input [7:0] s0,
input [7:0] s1,
input [7:0] s2,
input [7:0] s3,
input [7:0] s4,
input [7:0] s5,
input [7:0] s6,
input [7:0] s7,
input [2:0] addr
);
reg [7:0] s = 4'b0000;
always #1 begin
if (~addr[2] & ~addr[1] & ~addr[0]) begin
... | 7.056685 |
module questao1 (
output [3:0] s,
input addr,
input rw,
input clk,
input [3:0] i
);
memoria m1 (
s[0],
addr,
rw,
clk,
i[0]
);
memoria m2 (
s[1],
addr,
rw,
clk,
i[1]
);
memoria m3 (
s[2],
addr,
rw,
clk,
... | 6.77651 |
module questao2 (
output [3:0] s,
input addr,
input rw,
input clk,
input [3:0] i
);
wire [3:0] a0;
wire [3:0] a1;
questao1 q11 (
a0,
addr,
rw,
clk,
i
);
questao1 q12 (
a1,
~addr,
rw,
clk,
i
);
mux2x1 m (
s,
a0,
... | 7.414497 |
module buffer (
output s,
input a
);
assign s = a;
endmodule
| 6.861394 |
module mux2x8 (
output [7:0] s,
input [7:0] a0,
input [7:0] a1,
input c
);
reg [7:0] s = 8'b00000000;
always #1 begin
if (c) begin
s <= a0;
end else if (~c) begin
s <= a1;
end
end
endmodule
| 6.869828 |
module mux8x8 (
output [7:0] s,
input [7:0] s0,
input [7:0] s1,
input [7:0] s2,
input [7:0] s3,
input [7:0] s4,
input [7:0] s5,
input [7:0] s6,
input [7:0] s7,
input [2:0] addr
);
reg [7:0] s = 4'b0000;
always #1 begin
if (~addr[2] & ~addr[1] & ~addr[0]) begin
... | 7.056685 |
module dmx4x4 (
output s0,
output s1,
output s2,
output s3,
input [1:0] addr
);
reg s0 = 0, s1 = 0, s2 = 0, s3 = 0, s4 = 0, s5 = 0, s6 = 0, s7 = 0;
always #1 begin
if (~addr[1] & ~addr[0]) begin
s0 <= 1;
s1 <= 0;
s2 <= 0;
s3 <= 0;
end else if (~addr[1] & addr[0])... | 7.140371 |
module mux4x4 (
output [7:0] s,
input [7:0] s0,
input [7:0] s1,
input [7:0] s2,
input [7:0] s3,
input [1:0] addr
);
reg [7:0] s = 4'b0000;
always #1 begin
if (~addr[1] & ~addr[0]) begin
s <= s0;
end else if (~addr[1] & addr[0]) begin
s <= s1;
end else if (addr[1]... | 7.535358 |
module somadorAlgebrico (
output [2:0] s,
input [1:0] a,
input [1:0] b,
input carryIn
);
wire w[1:0];
wire carryOut[1:0];
xor xor1 (w[0], b[0], carryIn);
xor xor2 (w[1], b[1], carryIn);
fullAdder fa1 (
s[0],
carryOut[0],
a[0],
w[0],
carryIn
);
fullAdder fa2 (... | 7.642515 |
module comparador (
output s,
input [2:0] a,
input [2:0] b,
input key
);
wire [2:0] w;
wire w1;
xnor xnor1 (w[0], a[0], b[0]);
xnor xnor2 (w[1], a[1], b[1]);
xnor xnor3 (w[2], a[2], b[2]);
and and1 (w1, w[0], w[1], w[2]);
xor xor1 (s, key, w1);
endmodule
| 7.425908 |
module notgate (
output s,
input p,
input r
);
assign s = ~p & ~r; // criar vinculo permanente
// (dependencia)
endmodule
| 7.575943 |
module testnotgate;
// ------------------------- dados locais
reg a;
reg b; // definir registrador
// (variavel independente)
wire s; // definir conexao (fio)
// (variavel dependente )
// ------------------------- instancia
notgate NOT1 (
s,
a,
b
);
// --------------------... | 7.480879 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
// ------------------------- parte principal
initial begin
$display("Extra 0001 - Raphael Quintao - 445171");
a = 'b00000111;
$display("%8b = %8b", a, ~a);
end
endmodule
| 6.932753 |
module test_base_01;
// ------------------------- definir dados
reg [7:0] a;
reg [7:0] b;
// ------------------------- parte principal
initial begin
$display("Extra 0002 - Raphael Quintao - 445171");
a = 'b00000111;
b = ~a + 1;
$display("%8b = %8b", a, b);
end
endmodule
| 6.932753 |
module complement de 1
// -------------------------
module complement (output [7:0] s, input [7:0] p);
assign s = ~p;
endmodule
| 7.038672 |
module complement
// -------------------------
module test_complement;
// ------------------------- dados locais
reg [7:0] a;
wire [7:0] s1;
// ------------------------- instancia
complement C1 (s1, a);
// ------------------------- parte principal
initial begin
a = 0;
$display("Extra0003 - Ana Cristina - 4273... | 6.969189 |
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