code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module exu_edp_dp_inv_macro__stack_72c__width_1 (
din,
dout
);
input [0:0] din;
output [0:0] dout;
inv #(1) d0_0 (
.in (din[0:0]),
.out(dout[0:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_and_macro__dinv_16x__dnand_6x__ports_2__width_1 (
din0,
din1,
dout
);
input [0:0] din0;
input [0:0] din1;
output [0:0] dout;
and2 #(1) d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);
endmodule
| 6.728713 |
module exu_edp_dp_buff_macro__dbuff_48x__width_1 (
din,
dout
);
input [0:0] din;
output [0:0] dout;
buff #(1) d0_0 (
.in (din[0:0]),
.out(dout[0:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__stack_72c__width_71 (
din,
dout
);
input [70:0] din;
output [70:0] dout;
buff #(71) d0_0 (
.in (din[70:0]),
.out(dout[70:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_inv_macro__dinv_6x__width_3 (
din,
dout
);
input [2:0] din;
output [2:0] dout;
inv #(3) d0_0 (
.in (din[2:0]),
.out(dout[2:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_cla_macro__width_64 (
cin,
din0,
din1,
dout,
cout
);
input cin;
input [63:0] din0;
input [63:0] din1;
output [63:0] dout;
output cout;
cla #(64) m0_0 (
.cin (cin),
.in0 (din0[63:0]),
.in1 (din1[63:0]),
.out (dout[63:0]),
.cout(cout)
... | 6.980477 |
module exu_edp_dp_and_macro__ports_2__stack_72c__width_3 (
din0,
din1,
dout
);
input [2:0] din0;
input [2:0] din1;
output [2:0] dout;
and2 #(3) d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);
endmodule
| 6.728713 |
module exu_edp_dp_xor_macro__ports_2__stack_72c__width_3 (
din0,
din1,
dout
);
input [2:0] din0;
input [2:0] din1;
output [2:0] dout;
xor2 #(3) d0_0 (
.in0(din0[2:0]),
.in1(din1[2:0]),
.out(dout[2:0])
);
endmodule
| 6.902079 |
module exu_edp_dp_increment_macro__width_4 (
din,
cin,
dout,
cout
);
input [3:0] din;
input cin;
output [3:0] dout;
output cout;
incr #(4) m0_0 (
.cin (cin),
.in (din[3:0]),
.out (dout[3:0]),
.cout(cout)
);
endmodule
| 7.1393 |
module exu_edp_dp_buff_macro__stack_64c__width_64 (
din,
dout
);
input [63:0] din;
output [63:0] dout;
buff #(64) d0_0 (
.in (din[63:0]),
.out(dout[63:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_inv_macro__stack_72c__width_7 (
din,
dout
);
input [6:0] din;
output [6:0] dout;
inv #(7) d0_0 (
.in (din[6:0]),
.out(dout[6:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_zero_macro__width_8 (
din,
dout
);
input [7:0] din;
output dout;
zero #(8) m0_0 (
.in (din[7:0]),
.out(dout)
);
endmodule
| 7.768938 |
module exu_edp_dp_and_macro__ports_2__stack_72c__width_1 (
din0,
din1,
dout
);
input [0:0] din0;
input [0:0] din1;
output [0:0] dout;
and2 #(1) d0_0 (
.in0(din0[0:0]),
.in1(din1[0:0]),
.out(dout[0:0])
);
endmodule
| 6.728713 |
module exu_mdp_dp_buff_macro__width_2 (
din,
dout
);
input [1:0] din;
output [1:0] dout;
buff #(2) d0_0 (
.in (din[1:0]),
.out(dout[1:0])
);
endmodule
| 7.07001 |
module exu_mdp_dp_buff_macro__stack_72c__width_64 (
din,
dout
);
input [63:0] din;
output [63:0] dout;
buff #(64) d0_0 (
.in (din[63:0]),
.out(dout[63:0])
);
endmodule
| 7.07001 |
module exu_mdp_dp_buff_macro__stack_72c__width_32 (
din,
dout
);
input [31:0] din;
output [31:0] dout;
buff #(32) d0_0 (
.in (din[31:0]),
.out(dout[31:0])
);
endmodule
| 7.07001 |
module exu_mdp_dp_buff_macro__stack_72c__width_8 (
din,
dout
);
input [7:0] din;
output [7:0] dout;
buff #(8) d0_0 (
.in (din[7:0]),
.out(dout[7:0])
);
endmodule
| 7.07001 |
module exu_mdp_dp_buff_macro__stack_72c__width_36 (
din,
dout
);
input [35:0] din;
output [35:0] dout;
buff #(36) d0_0 (
.in (din[35:0]),
.out(dout[35:0])
);
endmodule
| 7.07001 |
module exu_mdp_dp_buff_macro__dbuff_48x__width_1 (
din,
dout
);
input [0:0] din;
output [0:0] dout;
buff #(1) d0_0 (
.in (din[0:0]),
.out(dout[0:0])
);
endmodule
| 7.07001 |
module mux64 (
I,
SEL,
Z
);
//ports
input [63:0] I;
input [5:0] SEL;
output Z;
//wires
wire [63:0] I;
wire [5:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux32 i_muxA (
.I ({I[31:0]}),
.SEL({SEL[4:0]}),
.Z (int1)
);
mux32 i_muxB (
.I ({I[63:32]... | 7.258785 |
module mux128 (
I,
SEL,
Z
);
//ports
input [127:0] I;
input [6:0] SEL;
output Z;
//wires
wire [127:0] I;
wire [6:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux64 i_muxA (
.I ({I[63:0]}),
.SEL({SEL[5:0]}),
.Z (int1)
);
mux64 i_muxB (
.I ({I[127... | 7.172217 |
module mux8 (
I,
SEL,
Z
);
//ports
input [7:0] I;
input [2:0] SEL;
output Z;
//wires
wire [7:0] I;
wire [2:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux4 i_muxA (
.I ({I[3:0]}),
.SEL({SEL[1:0]}),
.Z (int1)
);
mux4 i_muxB (
.I ({I[7:4]}),
... | 6.836068 |
module mux256 (
I,
SEL,
Z
);
//ports
input [255:0] I;
input [7:0] SEL;
output Z;
//wires
wire [255:0] I;
wire [7:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux128 i_muxA (
.I ({I[127:0]}),
.SEL({SEL[6:0]}),
.Z (int1)
);
mux128 i_muxB (
.I ({I[... | 6.728786 |
module mux2 (
I,
SEL,
Z
);
//ports
input [1:0] I;
input [0:0] SEL;
output Z;
//wires
wire [1:0] I;
wire [0:0] SEL;
wire Z;
endmodule
| 7.252603 |
module mux16 (
I,
SEL,
Z
);
//ports
input [15:0] I;
input [3:0] SEL;
output Z;
//wires
wire [15:0] I;
wire [3:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux8 i_muxA (
.I ({I[7:0]}),
.SEL({SEL[2:0]}),
.Z (int1)
);
mux8 i_muxB (
.I ({I[15:8]}),
... | 7.724809 |
module mux512 (
I,
SEL,
Z
);
//ports
input [511:0] I;
input [8:0] SEL;
output Z;
//wires
wire [511:0] I;
wire [8:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux256 i_muxA (
.I ({I[255:0]}),
.SEL({SEL[7:0]}),
.Z (int1)
);
mux256 i_muxB (
.I ({I[... | 6.846407 |
module mux32 (
I,
SEL,
Z
);
//ports
input [31:0] I;
input [4:0] SEL;
output Z;
//wires
wire [31:0] I;
wire [4:0] SEL;
wire Z;
wire int1;
wire int2;
//instances
mux16 i_muxA (
.I ({I[15:0]}),
.SEL({SEL[3:0]}),
.Z (int1)
);
mux16 i_muxB (
.I ({I[31:16]... | 7.71352 |
module halfAdder (
cout,
s,
a,
b
);
output cout, s;
input a, b;
xor XOR1 (s, a, b);
and AND1 (cout, a, b);
endmodule
| 7.256462 |
module fulladder_nor (
c0,
c1,
r,
s,
t
);
output c0, c1;
input r, s, t;
wire carry1, carry2, cout;
halfadder_nor HA1 (
cout,
carry1,
r,
s
);
halfadder_nor HA2 (
c0,
carry2,
cout,
t
);
or_nor OR1 (
c1,
carry1,
carry2
... | 7.305937 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module or_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1;
nor NOR1 (temp1, a, b);
nor NOR2 (s, temp1, temp1);
endmodule
| 7.031651 |
module test;
reg [3:0] a;
reg [3:0] b;
wire [4:0] c;
integer i, j;
// instancia
four_bits_fulladder_nor FBFA1 (
c,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Guia 05_01 - Alyson Deives - 416589");
$displ... | 6.635152 |
module halfAdder (
cout,
s,
a,
b
);
output cout, s;
input a, b;
xor XOR1 (s, a, b);
and AND1 (cout, a, b);
endmodule
| 7.256462 |
module fulladder_nor (
c0,
c1,
r,
s,
t
);
output c0, c1;
input r, s, t;
wire carry1, carry2, cout;
halfadder_nor HA1 (
cout,
carry1,
r,
s
);
halfadder_nor HA2 (
c1,
carry2,
cout,
t
);
or_nor OR1 (
c0,
carry1,
carry2
... | 7.305937 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module or_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1;
nor NOR1 (temp1, a, b);
nor NOR2 (s, temp1, temp1);
endmodule
| 7.031651 |
module fullsubtractor_nor (
c1,
c0,
r,
s,
t
);
output c0, c1;
input r, s, t;
halfsubtractor_nor HS1 (
cout,
carry1,
r,
s
);
halfsubtractor_nor HS2 (
c0,
carry2,
cout,
t
);
or_nor OR1 (
c1,
carry1,
carry2
);
endmodule... | 6.741456 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module or_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1;
nor NOR1 (temp1, a, b);
nor NOR2 (s, temp1, temp1);
endmodule
| 7.031651 |
module test;
reg [2:0] a;
reg [2:0] b;
wire [3:0] c;
integer i, j;
// instancia
three_bits_fullsubtractor_nor TBFS1 (
c,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Guia 05_02 - Alyson Deives - 416589");
... | 6.635152 |
module xor_nand (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4;
nand NAND1 (temp1, b, b);
nand NAND2 (temp3, a, a);
nand NAND3 (temp2, a, temp1);
nand NAND4 (temp4, b, temp3);
nand NAND5 (s, temp2, temp4);
endmodule
| 7.091488 |
module halfAdder (
cout,
s,
a,
b
);
output cout, s;
input a, b;
xor XOR1 (s, a, b);
and AND1 (cout, a, b);
endmodule
| 7.256462 |
module incrementar (
input [5:0] a,
output [5:0] s
);
xor xOr01 (s[0], a[0], 1);
xor xOr02 (s[1], a[1]);
xor xOr03 (s[2], a[2]);
xor xOr04 (s[3], a[3]);
xor xOr05 (s[4], a[4]);
xor xOr06 (s[5], a[5]);
endmodule
| 6.898062 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module or_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1;
nor NOR1 (temp1, a, b);
nor NOR2 (s, temp1, temp1);
endmodule
| 7.031651 |
module xor_nand (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4;
nand NAND1 (temp1, b, b);
nand NAND2 (temp3, a, a);
nand NAND3 (temp2, a, temp1);
nand NAND4 (temp4, b, temp3);
nand NAND5 (s, temp2, temp4);
endmodule
| 7.091488 |
module fulladder_nor (
c0,
c1,
r,
s,
t
);
output c0, c1;
input r, s, t;
wire carry1, carry2, cout;
halfadder_nor HA1 (
cout,
carry1,
r,
s
);
halfadder_nor HA2 (
c0,
carry2,
cout,
t
);
or_nor OR1 (
c1,
carry1,
carry2
... | 7.305937 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module or_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1;
nor NOR1 (temp1, a, b);
nor NOR2 (s, temp1, temp1);
endmodule
| 7.031651 |
module test;
reg [2:0] a;
reg [2:0] b;
wire [5:0] c;
integer i, j;
// instancia
three_bits_multiplier TBM1 (
c,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
// parte principal
initial begin : main
$display("Guia 05_03 - Alyson Deives - 416589");
$display(... | 6.635152 |
module halfAdder (
cout,
s,
a,
b
);
output cout, s;
input a, b;
xor XOR1 (s, a, b);
and AND1 (cout, a, b);
endmodule
| 7.256462 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module xor_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2, temp3, temp4, temp5, temp6;
nor NOR1 (temp1, b, b);
nor NOR2 (temp2, a, a);
nor NOR3 (temp3, a, temp1);
nor NOR4 (temp4, b, temp2);
nor NOR5 (temp5, temp3, temp4);
nor NOR6 (s, temp5, temp5);
endmodule
| 6.640232 |
module and_nor (
s,
a,
b
);
output s;
input a, b;
wire temp1, temp2;
nor NOR1 (temp1, a, a);
nor NOR2 (temp2, b, b);
nor NOR3 (s, temp1, temp2);
endmodule
| 6.962266 |
module Ex_16or8to32 (
input wire selector,
input wire [15:0] data_0,
input wire [7:0] data_1,
output wire [31:0] data_out
);
wire [31:0] aux_0, aux_1;
// Extenção do fio de 16-bits, mantendo o sinal (imediatos e offsets)
assign aux_0 = (data_0[15]) ? {{16{1'b1}}, data_0} : {{16{1'b0}}, data_0};
... | 8.474816 |
module Ex_1to32 (
input wire data_in,
output wire [31:0] data_out
);
// Extende 1 bit para 32-bits com 0s a esquerda(slt, slti)
assign data_out = {31'b0, data_in};
endmodule
| 8.244864 |
module ex_4_1 (
//////////// CLOCK //////////
input CLOCK2_50,
input CLOCK3_50,
input CLOCK4_50,
input CLOCK_50,
//////////// SW //////////
input [1:0] SW,
//////////// LED //////////
output [3:0] LEDR
);
//=======================================================
// REG/WIR... | 6.52345 |
module ex_advint (
//# {{clocks|Clocking}}
input clk,
input rst_n,
//# {{data|ALU Data}}
input [63:0] in1,
input [63:0] in2,
output reg [63:0] out,
output reg [63:0] out2,
//# {{control|Dispatch Control Signals}}
input ex_enable,
output ex_busy,
input [5:0] rd_in_rn,
... | 8.261069 |
module ex_agu #(
parameter CONFIG_AW = 0
) (
input ex_lsu_op,
input ex_epu_op,
output agu_en,
input [CONFIG_AW-1:0] add_sum,
output [CONFIG_AW-1:0] wb_lsa
);
assign agu_en = (ex_lsu_op | ex_epu_op);
assign wb_lsa = add_sum;
endmodule
| 7.239139 |
module ex_alu #(
parameter CONFIG_DW = 0,
//parameter CONFIG_ENABLE_MUL = 0,
//parameter CONFIG_ENABLE_DIV = 0,
//parameter CONFIG_ENABLE_DIVU = 0,
//parameter CONFIG_ENABLE_MOD = 0,
/... | 7.288514 |
module ex_ALU_cntrl (
input ALU_OP,
input instr,
output result
);
endmodule
| 6.575594 |
module ex_ALU_frwd (
input ctrl_mux4,
input ctrl_mux3,
input idex_regRS1,
input idex_regRS2,
output exmem_regRD,
output exmem_regWrite,
output memwb_regRD,
output memwb_regWrite
);
endmodule
| 6.774199 |
module ex_alu_s1 (
//# {{data|ALU Data}}
input [63:0] in1,
input [63:0] in2,
output [63:0] out,
//# {{control|Control Signals}}
input enable,
input [2:0] unit,
input [1:0] op
);
reg [63:0] out_pre;
assign out = out_pre;
always @(*) begin
out_pre = 64'h0;
if (enable)
... | 6.929269 |
module arithmetic_right (
shift_out,
shift_in,
shift_amount
);
output [15:0] shift_out;
input signed [15:0] shift_in;
input [3:0] shift_amount;
assign shift_out = shift_in >>> shift_amount;
endmodule
| 7.21874 |
module Ex_block_tb;
// Inputs
reg [15:0] data_in;
reg [15:0] A;
reg [15:0] B;
reg [5:0] op_dec;
reg clk;
reg reset;
// Outputs
wire [15:0] data_out;
wire [15:0] ans_ex;
wire [15:0] DM_data;
wire [1:0] flag_ex;
// Instantiate the Unit Under Test (UUT)
Ex_block uut (
.data_out(data_ou... | 7.158043 |
module ex_branch(
input wire `addr_t pc_in,
input wire `word_t offset_in,
input wire branch_busy_in,
input wire `sinst_t branch_op_in,
input wire `regtag_t branch_tagx_in,
input wire `regtag_t branch_tagy_in,
input wire `word_t branch_datax_in,
input wire `word_t branch_datay_in,
//... | 7.133714 |
module ex_bru #(
parameter CONFIG_DW = 0,
parameter CONFIG_AW = 0
) (
input ex_valid,
input [ `NCPU_BRU_IOPW-1:0] ex_bru_opc_bus,
input [ `PC_W-1:0] ex_pc,
input [CONFIG_AW-1:`NCPU_P_INSN_LEN] ex_imm,
input [ CONFIG... | 6.559428 |
module EX_BU (
input clk,
rst,
flush,
input [5:0] EX_Operation,
input [31:0] EX_imm,
EX_Src1,
EX_Src2,
EX_PC,
input [5:0] EX_Phydst,
input [3:0] EX_Commit_Window,
input EX_en,
output reg [3:0] WB_Commit_Window,
output reg [5:0] WB_Phydst,
output reg [31:0] WB_Res... | 6.941 |
module ex_case (
input wire rst_n,
input wire sclk,
output reg o_dv,
output reg [7:0] o_data,
input wire [9:0] i_data,
input wire [7:0] i_addr
);
reg [2:0] cnt_7;
always @(posedge sclk or negedge rst_n) begin
if (rst_n == 1'b0) cnt_7 <= 3'b000;
else cnt_7 <= c... | 7.863153 |
module ex_check (
sr1d,
ed,
mnd,
sr2,
ec,
mc,
st
);
input sr1d;
input [4:0] ed;
input [10:0] mnd;
output sr2;
output reg [4:0] ec;
output reg [9:0] mc;
output reg [1:0] st;
assign sr2 = sr1d;
//assign ec = ed;
//assign mc = mnd[9:0];
always @(ed or mnd) begin
if ... | 6.944535 |
module ex_cnt (
input wire sclk,
input wire rst_n,
output wire [9:0] cnt
);
reg [9:0] cnt_r;
assign cnt = cnt_r;
always @(posedge sclk or negedge rst_n) begin
if (rst_n == 1'b0) cnt_r <= 10'b00_0000_0000;
else cnt_r <= cnt_r + 10'b00_0000_0001;
end
endmodule
| 7.113252 |
module ex_dds (
input wire sclk,
input wire rst_n,
output wire [7:0] o_wave
);
parameter FRQ_W = 32'd85899346;
parameter FRQ_ADD = 32'd85899346 / 10;
parameter INIT_PHASE = 32'h8000_0000;
reg [31:0] addr;
reg [31:0] frq_word;
reg [ 6:0] div_cnt;
reg div_flag;
always @(posedge sclk ... | 6.749352 |
module ex_dds (
input wire sclk,
input wire rst_n,
output wire [15:0] o_wave
);
parameter FRQ_W_1K = 32'd85899;
parameter FRQ_W_10K = 32'd858993;
reg [31:0] addr_1K;
reg [31:0] addr_10K;
reg [22:0] sum;
reg [14:0] sum_cnt;
reg sum_flag;
wire [ 7:0] o_wave_1K;
wire [ 7:0] o_w... | 6.749352 |
module ex_decode (
// Input from IFU
opcode_1_op_r,
opcode_2_op_r,
// Input from decode8to256
decodeout_1,
decodeout_2,
// Output to ex_ctl
invalid_op_r,
illegal_op_r
);
// Input signals from IU
input [7:0] opcode_1_op_r; // 1st byte of the opcode
input [7:0] opcode_2_op_... | 6.774193 |
module D_FF (
c,
r,
d,
q
);
input c, r;
input d;
output reg q;
always @(posedge r or posedge c) begin
if (r) q <= 1'b0;
else q <= d;
end
endmodule
| 7.327167 |
module ex_dmem (
// ź
input rst_n_i,
input clk_i,
input [ 31:0] alu_c_i,
input [ 31:0] rD2_i,
input [ 31:0] pc4_i,
input [ 31:0] pcimm_i,
input [ 31:0] imm_i,
input [4 : 0] wR_i,
output reg [4 : 0] wR_o,
output reg [ 31:... | 6.608713 |
module EX_DU (
input clk,
rst,
flush,
input [5:0] EX_Operation,
input [31:0] EX_imm,
EX_Src1,
EX_Src2,
input [5:0] EX_PhyRdst,
input [3:0] EX_Commit_window,
input EX_en,
/*to memory*/
output reg [3:0] Memory_sel,
output reg [31:0] Memory_Address,
output reg [31:... | 7.481665 |
module EX_FF (
input wire clk,
input wire rst,
//info from execution stage
input wire [`REG_BUS128] ex_rt_e,
input wire [`REG_ADDR_BUS7] ex_rtaddr_e,
input wire ex_wreg_e,
input wire [0:2] ex_uid_e,
input wire [`REG_BUS128] ex_rt_o,
input wire [`REG_ADDR_BUS7] ex_rtaddr_o,
inp... | 7.309998 |
module ex_fifo (
input wire w_clk,
input wire r_clk,
input wire rst_n,
input wire w_en,
input wire [7:0] w_data,
output wire w_full,
input wire r_en,
output wire [7:0] r_data,
output wire r_empty
);
wire [8:0] r_gaddr;
wire [8:0] w_gaddr;
wire [7:0]... | 6.723556 |
module EX_Forward (
EX_MEM_Rd,
MEM_WB_Rd,
EX_MEM_RegWrite,
MEM_WB_RegWrite,
ID_EX_Rs,
ID_EX_Rt,
EX_Forward_1,
EX_Forward_2
);
input EX_MEM_RegWrite, MEM_WB_RegWrite;
input [4:0] EX_MEM_Rd, MEM_WB_Rd, ID_EX_Rs, ID_EX_Rt;
output [1:0] EX_Forward_1, EX_Forward_2;
assign EX_Forwar... | 6.854193 |
module ExForwardingHandler (
input [4:0] reg_read_addr_i, // Address of the register to be wrote back.
input [31:0] reg_read_data_i, // Data to be wrote.
input [4:0] reg_write_addr_from_ex_to_mem_i, // Previous register address.
input [31:0] reg_write_data_from_ex_to_mem_i, // Previous data to be WB... | 8.699583 |
module EX_Forwarding_Unit (
input MEM_RegWrite,
input WB_RegWrite,
input EX_MemWrite,
input [4:0] MEM_rd,
input [4:0] WB_rd,
input [4:0] EX_rs1,
input [4:0] EX_rs2,
input [2:0] EX_ALUOp,
output reg [1:0] EX_fwd_A,
output reg [1:0] EX_fwd_B,
output reg [1:0] EX_fwd_C
);
al... | 7.774623 |
module ex_fsm (
input wire sclk,
input wire rst_n,
input wire A,
output reg k1,
output reg k2
);
parameter IDLE = 4'b0001;
parameter START = 4'b0010;
parameter STOP = 4'b0100;
parameter CLEAR = 4'b1000;
reg [3:0] state;
//reg [3:0] next_state;
always @(posedge sclk or negedge r... | 8.003681 |
module EX_hazard_checker #(
parameter OP_IMME_ARITHMETIC = 7'b0010011,
parameter OP_ARITHMETIC = 7'b0110011,
parameter OP_CONDITIONAL_JMP = 7'b1100011,
parameter OP_UNCONDITIONAL_JMP = 7'b1101111,
parameter OP_MEMORY_LOAD = 7'b0000011,
parameter OP_MEMORY_STORE = 7'b0100011
) (
input wire [4... | 6.973501 |
module ex_home (
input wire clk,
input wire rst_n,
input wire cin,
output reg cout
);
reg [6:0] state;
reg [6:0] next_state;
parameter idle = 7'b0000001;
parameter s1 = 7'b0000010;
parameter s2 = 7'b0000100;
parameter s3 = 7'b0001000;
parameter s4 = 7'b0010000;
parameter s5 = 7'b01... | 7.92006 |
module ex_ipcore (
input wire clk,
output wire oclk1,
output wire oclk2,
output reg [1:0] cnt,
output wire [7:0] odata,
output wire locked
);
reg [7:0] raddr = 0;
always @(posedge oclk1 or negedge locked) begin
if (locked == 1'b0) raddr <= 8'h00;
else raddr <= raddr + 8'h01;
end
... | 7.017082 |
module ex_lsu1p (
input wire clk,
input wire rst,
input wire flush,
input wire exception_flush,
input wire stall,
input wire [ 31:0] ex_pc_o,
input wire [ 31:0] ex_alu_res_o,
input wire ex_in_delay_slot_o,
input wire ex_w_reg_ena_o,
input wire [4 : 0] ex_w_reg_ds... | 6.795477 |
module EX_M (
input clk,
input rst,
input [31:0] ALUResult_Ex,
output reg [31:0] ALUResult_M,
input [31:0] WriteData_Ex,
output reg [31:0] WriteData_M,
input [4:0] writereg_Ex,
output reg [4:0] writereg_M,
input RegWrite_Ex,
output reg RegWrite_M,
input MemtoReg_Ex,
outpu... | 7.541665 |
module ex_mem (
input wire rst,
input wire clk,
input wire [`StallBus] stall,
input wire flush,
input wire [`RegAddrBus] ex_wd,
input wire ex_wreg,
input wire [`WordBus] ex_wdata,
input wire ex_whilo,
input wire [`WordBus] ex_hi,
input wire [`WordBus] ex_lo,
input wire [`Alu... | 8.36239 |
module ex_mem(
input wire clk,
input wire rst,
//来自控制模块的信息
input wire[5:0] stall,
//来自执行的信息
input wire[·RegAddrBus] ex_wd,
input wire ex_wreg,
input wire[`RegBus] ex_wdata,
input wire[`RegBus] ex_hi,
input wire[`RegBus] ex_lo,
input wire ... | 6.615094 |
module EX_MemReg (
clk,
RegWrite,
MemtoReg,
MemWrite,
MemRead,
ALUresult,
writedata,
writeReg,
RegWriteOut,
MemtoRegOut,
MemWriteOut
, MemReadOut,
ALUresultOut,
writedataOut,
writeRegOut
);
input clk;
input RegWrite, MemtoReg;
input MemWrite, MemRead;
... | 8.257247 |
module EX_MEM_latch (
input clk,
input [15:0] DataAddress, //data path to RAM
output [15:0] o_DataAddress,
input ReadMem,
input WriteMem, //control signal to RAM
output o_ReadMem,
output o_WriteMem,
input [ 1:0] quarter, //data path... | 7.304072 |
module: EX_MEM_Pipeline_reg
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module EX_MEM_Pipeline_reg_test;
// Inputs
reg clk;
reg en;
reg branch_out_pipe_2;
reg memWrite_out_pipe_2;... | 6.502148 |
module ex_mem_pipe_reg (
clock,
wb_in,
wb_out,
m_in,
branch,
mem_write,
mem_read,
zero_flag_in,
zero_flag_out,
alu_result_in,
alu_result_out,
write_data_in,
write_data_out,
write_back_reg_in,
write_back_reg_out,
pc_add_in,
pc_add_out
);
input clock,... | 6.656074 |
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