code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module complement de 1
// -------------------------
module complement_2 (output [7:0] s, input [7:0] p);
assign s = (~p) + 1;
endmodule
| 7.038672 |
module complement
// -------------------------
module test_complement_2;
// ------------------------- dados locais
reg [7:0] a;
wire [7:0] s1;
// ------------------------- instancia
complement_2 C2 (s1, a);
// ------------------------- parte principal
initial begin
a = 0;
$display("Extra0004 - Ana Cristina - ... | 6.969189 |
module notgate (
output [7:0] s1,
input [7:0] b
);
assign s1 = ~b;
endmodule
| 7.575943 |
module pnot (
output [0:7] s,
input [0:7] p
);
// Associar a saida com a contrapositiva da entrada
assign s = ~p;
//terminar
endmodule
| 7.001038 |
module complement (
output [7:0] s,
input [7:0] a
);
assign s = ~a;
endmodule
| 7.736521 |
module test_complement;
//--------------definir dados
reg [7:0] a;
wire [7:0] b;
//instancia
complement comp1 (
b,
a
);
//parte principal
initial begin
a = 8'b00000000;
$display("Extra0011 - Thaise Souto Martins - 395504");
$display("Complemento de 1 - 1 byte");
$display(... | 6.590267 |
module complement (
output [7:0] s,
input [7:0] a
);
assign s = (~a) + 1'b1;
endmodule
| 7.736521 |
module test_complement;
//--------------definir dados
reg [7:0] a;
wire [7:0] b;
//instancia
complement comp1 (
b,
a
);
//parte principal
initial begin
a = 8'b00000000;
$display("Extra0012 - Thaise Souto Martins - 395504");
$display("Complemento de 2 - 1 byte");
$display(... | 6.590267 |
module xorgate (
output [0:7] s,
input [0:7] p,
input [0:7] q
);
assign s = p ^ q;
endmodule
| 7.421731 |
module testxorgate;
reg [0:7] a, b;
wire [0:7] s;
xorgate XOR1 (
s,
a,
b
);
initial begin : start
a = 8'b11111111;
b = 8'b11111111;
end
initial begin
$display("Extra02 Roger Rubens Machado - 430533");
$display("Test XOR gate");
$monitor("%b ^ %b = %b", a, b, s);
... | 6.716539 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
assign s = (p ^ q);
endmodule
| 7.421731 |
module testandogate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
// parte principal
initial begin
$display("Guia 01 - Jessica Luisa Betonico Andrade - 412748");
$display("Test XOR gate");
$display(" \n (a^b) = s \n");
a = 0;
b = 0;
#1 $display(... | 7.357723 |
module xorgate (
s,
p,
q
);
output s;
input p, q;
assign s = ~(p) & q | p & ~(q);
endmodule
| 7.421731 |
module testandogate;
reg a, b;
wire s;
// instancia
xorgate XOR1 (
s,
a,
b
);
// parte principal
initial begin
$display("Guia 01 - Jessica Luisa Betonico Andrade - 412748");
$display(" Teste XOR gate");
$display("\n ~(a)&b|a&~(b) = s \n");
a = 0;
b = 0;
#1 $... | 7.357723 |
module metodonandnor (
s4,
e1,
e2,
e3
);
output s4;
input e1, e2, e3;
assign s4 = (~(e1 & e2 & e3));
endmodule
| 7.112775 |
module testnandnor;
reg e1, e2, e3;
wire s1, s, s2, s3, s4;
metodonandnor NANDNOR1 (
s1,
e1,
e1,
e1
);
metodonandnor NANDNOR2 (
s,
e2,
e2,
e2
);
metodonandnor NANDNOR3 (
s2,
e3,
e3,
e3
);
metodonandnor NANDNOR4 (
s3,
... | 6.631345 |
module SOMACOMPLETANAND (
soma,
carry,
a,
b,
c
);
output soma, carry;
input a, b, c;
wire temp1, temp2, temp3, tmp4, temp5;
MEIASOMANAND MEIASOMA1 (
temp1,
temp2,
a,
b
);
MEIASOMANAND MEIASOMA2 (
soma,
temp3,
temp1,
c
);
nand NAND1 (t... | 7.288905 |
module SOMACOMPLETANAND3BITS (
soma,
carry,
a,
b
);
input [2:0] a, b;
output [2:0] soma;
output carry;
wire temp1, temp2;
MEIASOMANAND MEIASOMA1 (
soma[0],
temp1,
a[0],
b[0]
);
SOMACOMPLETANAND SOMACOMPLETA1 (
soma[1],
temp2,
a[1],
b[1],
... | 7.288905 |
module metodonornand (
s4,
e1,
e2,
e3
);
output s4;
input e1, e2, e3;
assign s4 = ~(e1 | e2 | e3);
endmodule
| 7.242622 |
module testnornand;
reg e1, e2, e3;
wire s1, s, s2, s3, s4;
metodonornand NORNAND1 (
s1,
e1,
e1,
e1
);
metodonornand NORNAND2 (
s,
e2,
e2,
e2
);
metodonornand NORNAND3 (
s2,
e3,
e3,
e3
);
metodonornand NORNAND4 (
s3,
... | 6.689244 |
module DIFERENCACOMPLETANOR (
diferenca,
sinal,
a,
b,
c
);
output diferenca, sinal;
input a, b, c;
wire temp1, temp2, temp3;
MEIADIFERENCANOR DIFERENCANOR1 (
temp1,
temp2,
a,
b
);
MEIADIFERENCANOR DIFERENCANOR2 (
diferenca,
temp3,
temp1,
... | 7.242596 |
module DIFERENCACOMPLETA3BITS (
diferenca,
sinal,
a,
b
);
input [2:0] a, b;
output [2:0] diferenca;
output sinal;
wire temp1, temp2;
MEIADIFERENCANOR MEIADIFERENCA1 (
diferenca[0],
temp1,
a[0],
b[0]
);
DIFERENCACOMPLETANOR DIFERENCACOMPLETA1 (
diferenca[1],
... | 7.242596 |
module TESTESUBTRATOR3BITS;
reg [2:0] a, b;
wire [2:0] diferenca;
wire sinal;
integer i, j;
DIFERENCACOMPLETA3BITS DIFERENCACOMPLETA1 (
diferenca,
sinal,
a,
b
);
initial begin : start
a = 0;
b = 0;
end
initial begin : main
$display(" Larissa Fernandes Leijoto ... | 6.580683 |
module norG8 (
output s,
input a,
input b,
input c,
input d,
input e,
input f,
input g,
input h
);
assign s = ~(a | b | c | d | e | f | g | h);
endmodule
| 7.184894 |
module exercicioextra;
// ------------------------- definir dados
reg [7:0] a;
wire [7:0] s;
Comp2byte comp1 (
s,
a
);
// ------------------------- parte principal
initial begin : main
$display("Extra1 - Mateus Cunha da Silva - 463624");
$display("Test number system");
$moni... | 7.123071 |
module testandgate;
reg [0:7] a, b;
wire [0:7] s;
andgate AND1 (
s,
a,
b
);
initial begin : start
a = 8'b00000000;
b = 8'b00000000;
end
initial begin
$display("Extra01 Roger Rubens Machado - 430533");
$display("Test AND gate");
$monitor("%b & %b = %b", a, b, s);
... | 6.553783 |
module andG8 (
output s,
input a,
input b,
input c,
input d,
input e,
input f,
input g,
input h
);
assign s = a & b & c & d & e & f & g & h;
endmodule
| 7.249555 |
module exercicioextra;
// ------------------------- definir dados
reg [7:0] a;
wire [7:0] s;
Comp2byte comp1 (
s,
a
);
// ------------------------- parte principal
initial begin : main
$display("Extra2 - Mateus Cunha da Silva - 463624");
$display("Test number system");
$moni... | 7.123071 |
module Extraction_add (
input [15:0] numA,
input [15:0] numB,
output reg sign_A,
sign_B,
output reg [4:0] Exp_Res,
output reg [10:0] mantissa_A,
output reg [10:0] mantissa_B
);
reg [10:0] mA;
reg [10:0] mB;
reg [ 4:0] ExpA;
reg [ 4:0] ExpB;
always @(numA, numB) begin
sign_A = ... | 7.96279 |
module Extraction_mul (
input [15:0] numA,
input [15:0] numB,
output reg sign_res,
output reg [4:0] exponent_res,
output reg [10:0] mantissa_A,
output reg [10:0] mantissa_B
);
reg [9:0] m1;
reg [9:0] m2;
always @(numA, numB) begin
m1 = numA[9:0];
m2 = numB[9:0];
if (numA ==... | 7.202392 |
module ram1x16 (
output [15:0] s,
input [15:0] x,
input addr,
input rw,
input clk,
input clear
);
ram1x4 ram0 (
s[3:0],
x[3:0],
addr,
rw,
clk,
clear
);
ram1x4 ram1 (
s[7:4],
x[7:4],
addr,
rw,
clk,
clear
);
ram1x4 r... | 6.860417 |
module ram4x8 (
output [7:0] s,
input [7:0] x,
input clk,
input readWrite,
input [1:0] address,
input clear
);
reg entradaDmx;
wire [3:0] w;
wire [7:0] aux0, aux1, aux2, aux3;
dmx2bits dmx1 (
w,
entradaDmx,
address
);
ram1x8 ram0 (
aux0,
x,
clk,... | 6.552052 |
module comp1 (
output [0:7] s,
input [0:7] p
);
assign s = ~p;
endmodule
| 6.578325 |
module comp2 (
output [0:7] s,
input [0:7] p
);
assign s = (~p) + 1'b1;
endmodule
| 6.712072 |
module extratorBranch #(
parameter ADDR_WIDTH = 16
) (
input [ADDR_WIDTH-1:0] instrucao,
output [10:0] offset
);
assign offset = instrucao[10:0];
endmodule
| 8.004905 |
module extratorImediato #(
parameter DATA_WIDTH = 16,
parameter ADDR_WIDTH = 16
) (
input [ADDR_WIDTH-1:0] instrucao,
output [DATA_WIDTH-1:0] imediato
);
assign imediato = instrucao;
endmodule
| 8.921599 |
module ExtremaDetection (
input iclk,
input irst_n,
input iDval,
input [7:0] iData_a,
input [7:0] iData_b0,
input [7:0] iData_b1,
input [7:0] iData_b2,
input [7:0] iData_b3,
input [7:0] iData_b4,
input [7:0] iDat... | 6.851899 |
module EXTS (
input [31 : 0] Rt,
input [1 : 0] C_EXTS,
output reg [31 : 0] to_dmem
);
always @(*) begin
case (C_EXTS)
2'b00: to_dmem = Rt;
2'b01: to_dmem = {16'b0, Rt[15 : 0]}; //SH
2'b10: to_dmem = {24'b0, Rt[7 : 0]}; //SB
default: to_dmem = 32'bz;
endcase
end
en... | 8.308739 |
module extsinal5p8 (
entrada,
saida
);
input [4:0] entrada;
output reg [7:0] saida;
always @(*) begin
saida[7:5] = 3'b000;
saida[4:0] = entrada;
end
endmodule
| 6.746191 |
module EXT_SLT (
input SLT_CLOCK, //from MSX Slot
input SLT_RESETn, //from MSX Slot
input SLT_SLTSL, //from MSX Slot
input SLT_WEn, //from MSX Slot
input SLT_RDn, //from MSX Slot
input [15:0] SLT_A, //from MSX Slot
inout [7:0] SLT_D, //from MSX Slot
input [1:0] EXT... | 7.041672 |
module ExtU (
input [15:0] ImmIn,
input [ 1:0] ExtOP,
output [31:0] ImmOut
);
assign ImmOut = (ExtOP == 0) ? {16'h0000,ImmIn[15:0]} :
(ExtOP == 1) ? {{16{ImmIn[15]}},ImmIn[15:0]} :
(ExtOP == 2) ? {16'h0000,ImmIn[15:0]}<<16 : 0;
endmodule
| 7.369977 |
module EXT_16_32 (
in16,
EXTOp,
out32
);
input [15:0] in16;
input EXTOp; //0: zero extension; 1: signed-extension
output [31:0] out32;
assign out32 = (EXTOp == `EXT_SIGNED) ? {{16{in16[15]}}, in16} //signed-extension
: {16'd0, in16}; //zero extension
endmodule
| 7.826071 |
module ext (
imm16,
ExtOp,
ext32
);
input [15:0] imm16;
input [1:0] ExtOp;
output reg [31:0] ext32;
always @(*) begin
case (ExtOp)
2'b00: begin
ext32 = {16'b0, imm16};
end
2'b01: begin
ext32 = {{16{imm16[15]}}, imm16};
end
2'b10: begin
ext... | 8.082905 |
module Ext_32 (
input [15:0] imm_16,
output [31:0] Imm_32
);
assign Imm_32 = {
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
imm_16[15],
im... | 7.843633 |
module EXT_5_32 (
shamt,
EXTOp,
out32
);
input [4:0] shamt; //5bit shamt
input EXTOp; //0: zero extension; 1: signed-extension
output [31:0] out32; //32bit operand for ALU
assign out32 = (EXTOp == `EXT_SIGNED) ? {{27{shamt[4]}}, shamt} //signed-extension
: {27'd0, shamt}; //zero extensi... | 9.189392 |
module EXT_8_32 (
in8,
EXTOp,
out32
);
input [7:0] in8;
input EXTOp; //0: zero extension; 1: signed-extension
output [31:0] out32;
assign out32 = (EXTOp == `EXT_SIGNED) ? {{24{in8[7]}}, in8} //signed-extension
: {24'd0, in8}; //zero extension
endmodule
| 8.079726 |
module ext_addrgen #(
parameter DATA_W = 32,
parameter EXT_ADDR_W = 10,
parameter EXT_PERIOD_W = 10,
parameter MEM_ADDR_W = 10
) (
input clk,
input rst,
// Control I/F
input run,
output reg done,
// Configuration
input [ `IO_ADDR_W-1:0] ext_addr,
... | 8.97177 |
module Ext_Branch (
input [15:0] id_imm,
output [31:0] id_bra_imm
);
assign id_bra_imm = (id_imm[15]==1'b1) ? {2'b11, 12'hfff, id_imm , 2'b00} : {14'd0, id_imm, 2'b00};
endmodule
| 6.977476 |
module ext_crc (
input wire rx_clk,
input wire [7:0] rx_data,
input wire rx_enable,
input wire sfd_wait,
output [7:0] rawdata,
output raw_en
);
wire en_exp = !sfd_wait && rx_enable;
reg [3:0] en_shift = 0;
reg [7:0] data_shift1, data_shift2, data_shift3, data_shift4;
reg en_rise = 0;
... | 6.921158 |
module EXT_CUT (
input [31:0] data_in,
input [2:0] E_C,
input SIGN_E,
output [31:0] data_out
);
assign data_out=(E_C==3'b010)?{((SIGN_E&&data_in[7])?24'b111111111111111111111111:24'b000000000000000000000000),data_in[7:0]}:((E_C==3'b001)?{((SIGN_E&&data_in[15])?16'b1111111111111111:16'b000000000000000... | 8.371419 |
module ext_D (
input [15:0] In,
input [ 1:0] EXTop,
output [31:0] Out
);
assign Out = (EXTop == 2'b00) ? {16'h0000,In} :
(EXTop == 2'b01) ? {{16{In[15]}},In} :
(EXTop == 2'b10) ? {In,16'h0000} :
32'b0;
endmodule
| 8.106831 |
module ext_de1_sram (
input clk,
// ram interface with openmsp430 core
input [ADDR_WIDTH-1:0] ram_addr,
input ram_cen,
input [ 1:0] ram_wen,
input [ 15:0] ram_din,
output reg [ 15:0] ram_dout,
// DE1's sram signals
i... | 8.435122 |
module ext_de_sinal (
input [15:0] unex,
output [31:0] ext
);
assign ext = {{16{unex[15]}}, unex};
endmodule
| 7.742269 |
module ext_de_sinal_tb;
reg [15:0] unex;
wire [31:0] ext;
ext_de_sinal dut (
.unex(unex),
.ext (ext)
);
initial begin
unex = 16'b0000000000000000;
display_comparator;
end
task display_comparator;
begin
unex = 16'b0000000011111111;
#1;
$display("unex: %b\t ex... | 6.994254 |
module ext_dm(
input [1:0] byte_addr,
input [2:0] ext_dm,
input [31:0] din,
output [31:0] dout
);
wire [7:0] byte;
wire [15:0] half_byte;
assign byte = (byte_addr == 2'b00) ? din[7:0]:
(byte_addr == 2'b01) ? din[15:8]:
(byte_addr == 2'b10) ? din[23:16]:
... | 7.36799 |
module ext_gpio_tb ();
reg clk = 0;
always #1 clk = !clk;
reg reset = 0;
wire [15:0] gpi = 16'hABCD;
wire [15:0] gpo;
reg [5:0] addr = 6'h3;
wire gpi_read, gpo_read;
reg gpo_write = 1'b1;
reg edit_gpo = 1'b0;
reflet_addressable_io #(
.number_of_io(16),
.addr_size(6)
) io (
.c... | 6.737999 |
module Ext_32 (
input [15:0] imm_16,
output [31:0] Imm_32
);
assign Imm_32 = {{16{imm_16[15]}}, imm_16}; //չΪ32λ
endmodule
| 7.843633 |
module ext_io_adc (
clock,
SCLK,
nCS,
MISO,
MOSI,
AIN1,
AIN2,
pk_detect_reset,
pk_detect_ack
);
input wire clock;
output reg SCLK;
output reg nCS;
input wire MISO;
output reg MOSI;
output reg [11:0] AIN1; //
output reg [11:0] AIN2; //
output reg pk_detect_ack; ... | 6.664698 |
module ext_mem_reader_cmd_translate (
input clk,
input rst_n,
output reg ext_mem_reader_cmd_ready,
input [71:0] ext_mem_reader_cmd_data,
input ext_mem_reader_cmd_valid,
output reg [31:0] ext_mem_reader_addr,
output ext_mem_reader_valid,
input ext_mem_reader_ready
);
parameter DataWid... | 7.829485 |
module EXT_module (
imm16_in,
imm32_out,
EXTop
);
input [15:0] imm16_in;
input [1:0] EXTop;
output [31:0] imm32_out;
reg [31:0] imm32_out;
always @(*)
case (EXTop)
2'b00: imm32_out = {{16'h0000}, imm16_in};
2'b01: imm32_out = {imm16_in, {16'h0000}};
2'b10: imm32_out = {... | 8.069469 |
module ext_preamble (
inout wire rx_clk,
// input wire reset,
input wire [7:0] rx_data,
input wire rx_enable,
//input wire rx_error,
output reg sfd_wait
);
// if 1: in preamble
// reg sfd_wait;
//assign rx_after_sfd = ~sfd_wait;
always @(posedge rx_clk) begin
if (rx_enable =... | 7.891173 |
module EXT_RAM #(
parameter DATA_WIDTH = 5,
parameter ADDR_WIDTH = 8,
parameter RAM_DEPTH = 1 << ADDR_WIDTH
) (
input logic clk, // Clock Input
input logic [ADDR_WIDTH-1:0] address, // Address Input
input logic we, // Write Enable
input logi... | 8.085076 |
module ext_ram_32 (
wr_clk,
rd_clk,
rd_clk_display,
wr,
wr_addr,
rd_addr,
rd_addr_display,
rd_addr_check,
data_in,
data_out,
data_out_display,
data_out_check,
start_of_frame,
end_of_frame,
pic_num
);
parameter BinMode = 0;
input wr_clk;
input rd_clk;
... | 6.516921 |
module ext_RAM_ctrl (
clk,
reset_n,
end_of_one_frame,
ref_frame_RAM_rd,
ref_frame_RAM_rd_addr,
dis_frame_RAM_wr,
dis_frame_RAM_wr_addr,
ref_frame_RAM_dout,
ext_frame_RAM0_cs_n,
ext_frame_RAM0_wr,
ext_frame_RAM0_addr,
ext_frame_RAM0_data,
ext_frame_RAM1_cs_n,
ext_f... | 7.057962 |
module ext_sign #(
parameter NB_IN = 16,
parameter NB_OUT = 32
) (
input [NB_IN-1:0] i_data,
output reg [NB_OUT-1:0] o_data
);
always @(*) begin
o_data[NB_IN-1:0] = i_data[NB_IN-1:0];
o_data[NB_OUT-1:NB_IN] = {NB_IN{i_data[NB_IN-1]}}; // se extiende el signo de i_data[15]
end
endmodu... | 8.819255 |
module Ext_Sinal (
entrada,
saida
);
input [15:0] entrada;
output [31:0] saida;
assign saida = (entrada[15] == 0) ? {16'b0000000000000000, entrada} : {16'b1111111111111111, entrada};
endmodule
| 7.742646 |
module: ext
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ext_tb;
// Inputs
reg [15:0] imm;
reg [1:0] EOp;
// Outputs
wire [31:0] ext;
// Instantiate the Unit Under Test (... | 7.228997 |
module signZeroExtend (
immediate,
ExtSel,
out
);
input [15:0] immediate;
input ExtSel;
output [31:0] out;
assign out[15:0] = immediate;
assign out[31:16] = ExtSel ? (immediate[15] ? 16'hffff : 16'h0000) : 16'h0000;
endmodule
| 6.791237 |
module
*/
/* verilator lint_off DECLFILENAME */
module arbiter #
(
parameter PORTS = 4,
// select round robin arbitration
parameter ARB_TYPE_ROUND_ROBIN = 0,
// blocking arbiter enable
parameter ARB_BLOCK = 0,
// block on acknowledge assert when nonzero, request deassert when 0
parameter A... | 7.852732 |
module
*/
/* verilator lint_off DECLFILENAME */
module priority_encoder #
(
parameter WIDTH = 4,
// LSB priority selection
parameter LSB_HIGH_PRIORITY = 0
)
(
input wire [WIDTH-1:0] input_unencoded,
output wire output_valid,
output wire [$clog2(WIDTH)-1:0] output_e... | 7.852732 |
module exunit_alu (
input wire clk,
input wire reset,
input wire [ `DATA_LEN-1:0] ex_src1,
input wire [ `DATA_LEN-1:0] ex_src2,
input wire [ `ADDR_LEN-1:0] pc,
input wire [ `DATA_LEN-1:0] imm,
input wire ... | 6.560374 |
module exunit_mul (
input wire clk,
input wire reset,
input wire [ `DATA_LEN-1:0] ex_src1,
input wire [ `DATA_LEN-1:0] ex_src2,
input wire dstval,
input wire [`SPECTAG_LEN-1:0] spectag,
input wire specbit,... | 6.583065 |
module EXU_ALU (
input wire i_clk,
input wire i_rstn,
input wire [`rfidxlen_def] i_alu_rdidx,
input wire [`decinfo_grplen_def] i_decinfo_grp,
input wire [`decinfolen_def] i_aluinfo,
//参数1
input wire [`xlen_def] i_alu_op1,
//参数2
input wire [`xlen_def] i_alu_op2,
//派遣指令，需要写入的rd... | 6.706745 |
module exu_alu_bjp (
input clk,
input rst_n,
input bjp_i_valid,
output bjp_i_ready,
input [`E203_XLEN-1:0] bjp_i_rs1,
input [`E203_XLEN-1:0] bjp_i_rs2,
input [`E203_XLEN-1:0] bjp_i_imm,
input [`E203_PC_SIZE-1:0] bjp_i_pc,
input [`E203_DECINFO_BJP_WIDTH-1:0] bjp_i_info,
//bjp... | 9.841289 |
module exu_alu_rglr (
input clk,
rst_n,
input alu_i_valid,
input [`E203_XLEN-1:0] alu_i_rs1,
input [`E203_XLEN-1:0] alu_i_rs2,
input [`E203_XLEN-1:0] alu_i_imm,
input [`E203_PC_SIZE-1:0] alu_i_pc,
input [`E203_DECINFO_ALU_WIDTH-1:0] alu_i_info,
output alu_i_ready,
//ALU写回/交付接口
... | 7.046632 |
module EXU_BJU (
input wire i_clk,
input wire i_rstn,
input wire [`rfidxlen_def] i_bju_rdidx,
input wire [`decinfo_grplen_def] i_decinfo_grp,
input wire [`decinfolen_def] i_bjuinfo,
//当前跳转指令的地址
input wire [`xlen_def] i_iaddr,
input wire [`xlen_def] i_imm,
input wire [`xlen_def] i_... | 8.544817 |
module exu_commit (
input wire clk,
input wire rst_n,
input wire req_muldiv_i,
input wire muldiv_reg_we_i,
input wire [4:0] muldiv_reg_waddr_i,
input wire [31:0] muldiv_reg_wdata_i,
input wire req_mem_i,
input wire mem_reg_we_i,
input wire [4:0] mem_reg_waddr_i,
input wire [31... | 6.59427 |
module exu_edp_dp_buff_macro__dbuff_32x__stack_none__width_4 (
din,
dout
);
input [3:0] din;
output [3:0] dout;
buff #(4) d0_0 (
.in (din[3:0]),
.out(dout[3:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_64 (
din,
dout
);
input [63:0] din;
output [63:0] dout;
buff #(64) d0_0 (
.in (din[63:0]),
.out(dout[63:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_72 (
din,
dout
);
input [71:0] din;
output [71:0] dout;
buff #(72) d0_0 (
.in (din[71:0]),
.out(dout[71:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_zero_macro__width_64 (
din,
dout
);
input [63:0] din;
output dout;
zero #(64) m0_0 (
.in (din[63:0]),
.out(dout)
);
endmodule
| 7.768938 |
module exu_edp_dp_inv_macro__dinv_12x__stack_72c__width_1 (
din,
dout
);
input [0:0] din;
output [0:0] dout;
inv #(1) d0_0 (
.in (din[0:0]),
.out(dout[0:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_buff_macro__stack_72c__width_1 (
din,
dout
);
input [0:0] din;
output [0:0] dout;
buff #(1) d0_0 (
.in (din[0:0]),
.out(dout[0:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__stack_72c__width_7 (
din,
dout
);
input [6:0] din;
output [6:0] dout;
buff #(7) d0_0 (
.in (din[6:0]),
.out(dout[6:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_xor_macro__ports_2__stack_72c__width_64 (
din0,
din1,
dout
);
input [63:0] din0;
input [63:0] din1;
output [63:0] dout;
xor2 #(64) d0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout[63:0])
);
endmodule
| 6.902079 |
module exu_edp_dp_buff_macro__stack_72c__width_64 (
din,
dout
);
input [63:0] din;
output [63:0] dout;
buff #(64) d0_0 (
.in (din[63:0]),
.out(dout[63:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_cmp_macro__width_32 (
din0,
din1,
dout
);
input [31:0] din0;
input [31:0] din1;
output dout;
cmp #(32) m0_0 (
.in0(din0[31:0]),
.in1(din1[31:0]),
.out(dout)
);
endmodule
| 6.714411 |
module exu_edp_dp_inv_macro__stack_72c__width_3 (
din,
dout
);
input [2:0] din;
output [2:0] dout;
inv #(3) d0_0 (
.in (din[2:0]),
.out(dout[2:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_cmp_macro__width_64 (
din0,
din1,
dout
);
input [63:0] din0;
input [63:0] din1;
output dout;
cmp #(64) m0_0 (
.in0(din0[63:0]),
.in1(din1[63:0]),
.out(dout)
);
endmodule
| 6.714411 |
module exu_edp_dp_cmp_macro__width_8 (
din0,
din1,
dout
);
input [7:0] din0;
input [7:0] din1;
output dout;
cmp #(8) m0_0 (
.in0(din0[7:0]),
.in1(din1[7:0]),
.out(dout)
);
endmodule
| 6.714411 |
module exu_edp_dp_buff_macro__dbuff_32x__stack_72c__width_2 (
din,
dout
);
input [1:0] din;
output [1:0] dout;
buff #(2) d0_0 (
.in (din[1:0]),
.out(dout[1:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__dbuff_32x__stack_72c__width_1 (
din,
dout
);
input [0:0] din;
output [0:0] dout;
buff #(1) d0_0 (
.in (din[0:0]),
.out(dout[0:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__dbuff_24x__stack_72c__width_65 (
din,
dout
);
input [64:0] din;
output [64:0] dout;
buff #(65) d0_0 (
.in (din[64:0]),
.out(dout[64:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__stack_72c__width_8 (
din,
dout
);
input [7:0] din;
output [7:0] dout;
buff #(8) d0_0 (
.in (din[7:0]),
.out(dout[7:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_inv_macro__stack_72c__width_64 (
din,
dout
);
input [63:0] din;
output [63:0] dout;
inv #(64) d0_0 (
.in (din[63:0]),
.out(dout[63:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_buff_macro__stack_72c__width_2 (
din,
dout
);
input [1:0] din;
output [1:0] dout;
buff #(2) d0_0 (
.in (din[1:0]),
.out(dout[1:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_zero_macro__width_32 (
din,
dout
);
input [31:0] din;
output dout;
zero #(32) m0_0 (
.in (din[31:0]),
.out(dout)
);
endmodule
| 7.768938 |
module exu_edp_dp_inv_macro__stack_72c__width_2 (
din,
dout
);
input [1:0] din;
output [1:0] dout;
inv #(2) d0_0 (
.in (din[1:0]),
.out(dout[1:0])
);
endmodule
| 7.1393 |
module exu_edp_dp_buff_macro__width_5 (
din,
dout
);
input [4:0] din;
output [4:0] dout;
buff #(5) d0_0 (
.in (din[4:0]),
.out(dout[4:0])
);
endmodule
| 7.301601 |
module exu_edp_dp_buff_macro__width_3 (
din,
dout
);
input [2:0] din;
output [2:0] dout;
buff #(3) d0_0 (
.in (din[2:0]),
.out(dout[2:0])
);
endmodule
| 7.301601 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.