code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module EX_Mem_PR #(
parameter ISIZE = 18,
DSIZE = 16
) (
input Clk,
Rst,
//input memWriteEnab, memEnab, // not registered
input sel_mem2Reg,
RFwriteEnab,
input [DSIZE-1:0] ALUresult,
input [2:0] RFdest_rd,
input [3:0] ALUstatus,
//output reg memWriteEnab_o, memEnab_o, /... | 8.630293 |
module ex_mem_reg (
input clk,
input rst,
input id_ex_memread,
input id_ex_memwrite,
input id_ex_mem_to_reg,
input id_ex_pc_src,
input [4:0] id_ex_rd,
input id_ex_regwrite,
input id_ex_ins_valid,
output reg ex_mem_memread,
output reg ex_mem_memwrite,
output reg ex_mem_m... | 7.653606 |
module EX_MEM_split (
clk,
rst,
en,
createdump_is,
write_mem_is,
read_mem_is,
mem_to_reg_is,
reg_w_en_is,
w_reg_is,
data_2_is,
ALU_out_is,
createdump_os,
write_mem_os,
read_mem_os,
mem_to_reg_os,
reg_w_en_os,
w_reg_os,
data_2_os,
ALU_out_os
);
... | 7.317375 |
module EX_MEM_stage (
input wire clk, // Clock
input wire rst_n, // Reset
input wire flush,
input wire [31:0] exPc,
input wire [31:0] exAluRes,
exRegData2,
input wire [ 4:0] exRd,
input wire [ 9:0] exCtrlSig,
output reg [31:0] memPc,
output reg [31:0] memAluRes,
memRegD... | 6.519401 |
module ex_mem_stage_reg (
ex_flush,
regwrite_in,
memtoreg_in,
regwrite_out,
memtoreg_out,
branch_in,
memread_in,
memwrite_in,
jump_in,
branch_out,
memrea_d_out,
memwrite_out,
jump_out,
jump_addr_in,
branch_addr_in,
jump_addr_out,
branch_addr_out,
a... | 8.497012 |
module ex_mem (
input clk,
input reset,
input [ 4:0] in_regWAddr, //写回寄存器的地址
input [31:0] in_regRData2, //读存储器的数据
input [ 1:0] ex_result_sel, //执行结果选择
input [31:0] id_ex_data_imm, //指令立即数
input [31:0] alu_result, //ALU运算结果
input [31:0] in_pc, ... | 8.36239 |
module ex_mm (
input wire rst,
input wire clk,
input wire [ 4:0] ex_wa,
input wire ex_we,
input wire [31:0] ex_wn,
output reg [ 4:0] mm_wa,
output reg mm_we,
output reg [31:0] mm_wn,
input wire [ 4:0] ex_mem_e,
input wire [31:0] ex_mem_n,
... | 7.637324 |
module ALU (
input wire i_clk,
input wire i_rst_n,
input wire i_add,
input wire i_sub,
input wire i_slt,
input wire i_sltu,
input wire i_xor,
input wire i_or,
input wire i_and,
input wire i_sll,
input wire i_srl,
input wire i_sra,
//alu使能
input wire i_en,
//... | 7.960621 |
module EX_MulDiv (
input clk,
input rst,
input MEM_exception,
input [ 7:0] MDop,
input [31:0] rs_data,
input [31:0] rt_data,
output [31:0] MD_data,
output EX_MD_stall
);
parameter state_wait = 5'b00001;
parameter state_mul = 5'b00010;
parameter state_div = 5'b00100;... | 6.985722 |
module ex_mux1 (
input ex_flush,
input id_ex_wb,
output ex_mem_wb
);
reg [1:0] zeros;
reg result;
wire sel;
assign sel = ex_flush;
assign ex_mem_wb = result;
always @(*) begin
case (sel)
1'b0: result = zeros[0];
1'b1: result = id_ex_wb;
endcase
end
endmodule
| 7.355403 |
module ex_mux2 (
input ex_flush,
input id_ex_m,
input [3:0] zeros,
input ex_mem_m
);
reg [3:0] zeros;
reg result;
wire sel;
assign sel = ex_flush;
assign ex_mem_m = result;
always @(*) begin
case (sel)
1'b0: result = zeros[0];
1'b1: result = id_ex_m;
endcase
end
endmodu... | 7.816858 |
module ex_mux3 (
input [ 1:0] ctrl,
input [31:0] id_exReadData1,
input [31:0] wbData,
input [31:0] ex_memData,
output [31:0] tempAluOp1
);
reg [31:0] result;
wire [ 1:0] sel;
assign tempAluOp1 = result;
assign sel = {ctrl};
always @(*) begin
case (sel)
2'b00: result = id_exR... | 7.120701 |
module ex_mux4 (
input [ 1:0] ctrl,
input [31:0] id_exReadData2,
input [31:0] wbData,
input [31:0] ex_memData,
output [31:0] tempAluOp2
);
reg [31:0] result;
wire [ 1:0] sel;
assign tempAluOp2 = result;
assign sel = {ctrl};
always @(*) begin
case (sel)
2'b00: result = id_exR... | 7.572523 |
module ex_mux5 (
input [ 1:0] aluSrc1,
input [31:0] tempAluOp1,
input [31:0] id_ex_pc,
output [31:0] aluOp1
);
reg [31:0] result;
wire [ 1:0] sel;
assign aluOp1 = result;
assign sel = {aluSrc1};
always @(*) begin
case (sel)
2'b00: result = tempAluOp1;
2'b01: result = id_ex_... | 6.592775 |
module ex_mux6 (
input [ 1:0] aluSrc2,
input [31:0] tempAluOp2,
input [31:0] id_ex_imm,
output [31:0] aluSrc2
);
reg [31:0] result;
wire [ 1:0] sel;
assign aluOp1 = result;
assign sel = {aluSrc2};
always @(*) begin
case (sel)
2'b00: result = tempAluOp2;
2'b01: result = id_e... | 6.821534 |
module EX_MWcontrol (
input [31:0] rt_data,
input [31:0] alu_result,
input [4 : 0] data_dtl,
output [ 31:0] data_wdata,
output [ 31:0] data_addr,
output [3 : 0] data_strb,
input in_en,
output out_en,
output AdES_exception,
input MEM_exception
);
wire [1:0] ea = alu_resul... | 7.245415 |
module implements the 21:1 32-bit mux
*
******************************************************************************/
module mux21_32(out,
in20,
in19,
in18,
in17,
in16,
in15,
in14,
in13,
in12,
in11,
in10,
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
in1,
in0,
sel);
input ... | 7.842559 |
module EX_reg_MEM (
input clk_EXMem, //寄存器时钟
input rst_EXMem, //寄存器复位
input en_EXMem, //寄存器使能
input NOP_EXMem, //
input [31:0] PC_in_EXMem, //PC输入
input [31:0] PC4_in_EXMem, //PC+4输入
input [4:0] Wt_addr_EXMem, //写目的寄存器地址输入
input zero_in_EXMem, //zero
input [31:0] ALU_in_EXM... | 6.911443 |
module ex_shift_reg (
input wire lvds_clk,
input wire rst_n,
input wire lvds_d,
output reg [7:0] o_lvds_d
);
reg [7:0] shift_reg;
reg [2:0] s_cnt;
reg s_flag;
reg s_flag_dly1;
reg s_flag_dly2;
always @(posedge lvds_clk or negedge rst_n) begin
if (rst_n == 1'b0) shift_... | 7.766889 |
module DataHanzardDetector (
input wire [4:0] EX_rs,
input wire [4:0] EX_rt,
input wire MEM_RegWrite,
input wire [4:0] MEM_WBAddr,
input wire WB_RegWrite,
input wire [4:0] WB_WBAddr,
output reg [1:0] datafwd_1,
output reg [1:0] datafwd_2
);
// design logic:
// first forward wb to... | 7.284278 |
module JrTempReg (
input wire clk,
input wire reset,
input wire [31:0] data_in,
output reg [31:0] data_out,
input wire is_jr,
output reg indicator
);
always @(posedge clk or posedge reset) begin
if (reset) begin
indicator <= 0;
end else indicator <= is_jr;
end
always @... | 7.147896 |
module EX_Stage_Module (
//inputs to main moduel:
input clk,
rst,
freeze,
input [`ADDRESS_LEN - 1:0] PC_in,
input wb_en_in,
mem_r_en_in,
mem_w_en_in,
status_w_en_in,
branch_taken_in,
input immd,
input [`EXECUTE_COMMAND_LEN - 1:0] exe_cmd,
input [`REGISTER_LEN - 1:0] v... | 6.90504 |
module EX_Stage_reg (
input clk,
input rst,
input Freeze,
input WB_en_in,
input MEM_R_EN_in,
input MEM_W_EN_in,
input [31:0] PC_in,
input [31:0] ALU_result_in,
input [31:0] ST_val_in,
input [4:0] Dest_in,
output reg WB_en,
output reg MEM_R_EN,
output reg MEM_W_EN,
... | 7.165092 |
module tb;
parameter word_size = 32;
parameter reg_size = 5;
parameter fun_size = 6;
wire zero;
wire [word_size-1:0] AddResult, alu_result;
wire [word_size-1:0] WriteData;
wire [2:0] mem_control_signals_out;
wire [1:0] wb_control_signals_out;
wire [reg_size -1:0] destination_reg;
reg [3:0] ex_cont... | 6.612288 |
module: EX_stage
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
`include "mips_16_defs.v"
module EX_stage_tb_0_v;
// Inputs
reg clk;
reg rst;
reg [56:0] pipeline_reg... | 7.906069 |
module ex_tb ();
wire [15:0] fractionalPart;
wire [1:0] integerPart;
wire done;
reg [15:0] x;
reg clk = 1'b0, rst = 1'b0, start = 1'b0;
exponential EXP (
.x(x),
.start(start),
.clk(clk),
.rst(rst),
.done(done),
.intpart(integerPart),
.fracpart(fractionalPart)
)... | 6.538355 |
module tb ();
reg clock;
reg reset;
wire [4:0] q;
RippleCarryCounter r1 (
clock,
reset,
q
);
initial clock = 1'b0;
always #5 clock = ~clock;
initial begin
reset = 1'b1;
#15 reset = 1'b0;
#500 reset = 1'b1;
end
initial $monitor("Time = ", $time, "---> Output = %d",... | 7.195167 |
module EX_to_MEM (
input clk,
rst_n,
flush,
input [31:0] pc_branch,
pc_add4, //calculated pc for branch instruction
input [31:0] data_in, // data for store_word instruction
input [31:0] alu_in, //result from alu
input [4:0] rd,
input branch,
memRW,
input RegW,
input [1... | 7.763793 |
module EX_WB (
input Clk,
Reset,
input RegWrite_ID_EX,
input [31:0] ALUresult,
input [4:0] Rd_ID_EX,
output reg RegWrite_EX_WB,
output reg [31:0] ALUresult_EX_WB,
output reg [4:0] Rd_EX_WB
);
always @(posedge Clk, negedge Reset) begin
if (Reset == 0) begin
RegWrite_EX_WB = 1... | 6.784916 |
module EX_WB_pipeline (
input clk,
rst,
input [7:0] pc_ID_EX,
aluResult,
immOut_ID_EX,
input branch_ID_EX,
regWrite_ID_EX,
immToReg_ID_EX,
input [2:0] rd_ID_EX,
input [1:0] opcode_ID_EX,
output reg [7:0] pc_EX_WB,
aluResult_EX_WB,
immOut_EX_WB,
output reg branch_... | 6.587174 |
module EX_WB_reg (
input [63:0] EX_alu_out,
input [4:0] EX_rD,
input [1:0] EX_WB_ctrl,
input [7:0] EX_PPP,
output reg [63:0] WB_alu_out,
output reg [4:0] WB_rD,
output reg [1:0] WB_WB_ctrl,
output reg [7:0] WB_PPP,
input clk,
input rst
);
always @(posedge clk) begin
if (rs... | 6.886303 |
module ex_wire (
input wire sel,
input wire a,
input wire b,
output wire c
);
assign c = sel ? a : b;
//assign c = (sel == 1'b1) ? a : b ;
/* always @(sel or a or b)
begin
if(sel == 1'b1)
c = a;
else
c = b;
end */
//at the same time , we should change the output wire c to o... | 7.301963 |
module Eyeriss_PE (
input [15:0] map,
filter,
input [15:0] Psum_from_GLB,
Psum_from_PE,
input getdata_fil,
getdata_map,
getdata_psum,
input [7:0] id_in,
input CLK,
clr,
input [25:0] conf_i,
input stall,
input psum_i_empty,
psum_i_full, //empty from back, full fr... | 6.572365 |
module PEController (
input clk,
input resetN,
input PEdone, //Signal from the PE when done
input [1:0] modeController, //mode from outController
input get_next_in, //signal from outside contorller for ACCUM modeController
input [3:0] num_of_ifmap,
input [3:0] num_... | 6.805335 |
module Eyeriss_PE_Core (
input [15:0] ifmapin,
filter,
input [15:0] inputPsum,
input [1:0] mode, // 0-idle 1-get data, 2-multiply, 3-output,
input CLK,
clr,
map_en,
fil_en,
psum_en,
p_en_delay,
regs_en,
rst_accm,
input [3:0] mult_bits,
input [3:0] filter_iterator... | 6.544115 |
module adder_16 (
a,
b,
c
);
input [15:0] a, b;
output [15:0] c;
assign c = b + a;
endmodule
| 7.110663 |
module Eyeriss_Row_PE //#(parameter ARRAY_ROW_NUM=2)
(
input [58:0] GLB_BUS,
input CLK,
clr,
input read,
input [78:0] conf, //input [25:0]conf [ARRAY_ROW_NUM-1:0],
input stall,
output ready_out,
output [15:0] psum_out,
output ready_for_input,
output_ready //empty to front, f... | 7.169951 |
module E_ALU (
input [31:0] A,
input [31:0] B,
input [4:0] shamt,
input [3:0] ALUop,
output reg [31:0] ALUresult
);
always @(*) begin
case (ALUop)
0: ALUresult = A + B;
1: ALUresult = A - B;
2: ALUresult = B << 16;
3: ALUresult = A | B;
default: ALUresult = 0;
... | 7.102552 |
module e_clock_mng (
rst,
sd_clk_2x,
sd_clock_en, // from sync
sdclk_disable, // from sync
sdio_on,
int_clock_en, // from sync
clock_div,
load_clock_div_p, //T flop Pulse from sync
sd_clkn,
sd_clk,
sd_clk_int
);
input rst;
input sd_clk_2x;
input sd_clock_en;
inp... | 6.560192 |
module E_CPU_IO_bot_ConfigMem (
FrameData,
FrameStrobe,
ConfigBits,
ConfigBits_N
);
parameter MaxFramesPerCol = 20;
parameter FrameBitsPerRow = 32;
parameter NoConfigBits = 20;
input [FrameBitsPerRow-1:0] FrameData;
input [MaxFramesPerCol-1:0] FrameStrobe;
output [NoConfigBits-1:0] ConfigBit... | 7.834857 |
module E_CPU_IO_ConfigMem (
FrameData,
FrameStrobe,
ConfigBits,
ConfigBits_N
);
parameter MaxFramesPerCol = 20;
parameter FrameBitsPerRow = 32;
parameter NoConfigBits = 20;
input [FrameBitsPerRow-1:0] FrameData;
input [MaxFramesPerCol-1:0] FrameStrobe;
output [NoConfigBits-1:0] ConfigBits;
... | 8.132202 |
module e_crc16 (
rst,
clk,
gen_en,
out_en,
din,
dout
);
input rst;
input clk;
input gen_en;
input out_en;
input din;
output dout;
wire rst;
wire clk;
wire gen_en;
wire out_en;
wire din;
wire dout;
reg [15:0] crc_reg;
assign dout = crc_reg[15];
always @(posedge ... | 7.018503 |
module e_dat0_line (
rst,
clk,
clkn,
high_speed,
crc_rst,
dat_width,
oe,
data_sel,
crc_check_en,
dat_phase,
xmit_data,
rcv_data,
crc_error,
dat_in,
dat
);
input rst;
input clk;
input clkn;
input high_speed;
input crc_rst;
input dat_width;
inp... | 7.076066 |
module E_M_Reg (
input [31:0] ALURstE,
input [31:0] WDE,
input [4:0] A3E,
input [31:0] InstrE,
input [31:0] PCplus8E,
input clk,
input reset,
output reg [31:0] ALURstM,
output reg [31:0] WDM,
output reg [4:0] A3M,
output reg [31:0] InstrM,
output reg [31:0] PCplus8M
);
... | 6.968299 |
module E_Piano (
input wire clk, //Basys2时钟，50MHz
input wire PS2C, //PS2接口的时钟
input wire PS2D, //PS2接口的数据
input wire [1:0] select,
output wire [7:0] led, //Basys2上的8个LED灯，用于跑马灯效果
output wire [6:0] seg, //七段数码管的显示
output wire [3:0] an, //七段数码管的... | 10.136921 |
module e_pipereg (
clk,
d_icode,
d_ifun,
d_rA,
d_rB,
d_valC,
d_valP,
d_valA,
d_valB,
e_icode,
e_ifun,
e_rA,
e_rB,
e_valC,
e_valP,
e_valA,
e_valB
);
parameter n = 64;
input clk;
input [3:0] d_icode, d_ifun;
input [3:0] d_rA;
input [3:0] d_rB;... | 6.956071 |
module e_ram (
aclr,
clock,
data,
rdaddress,
rden,
wraddress,
wren,
q
);
input aclr;
input clock;
input [31:0] data;
input [11:0] rdaddress;
input rden;
input [11:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
... | 6.530777 |
module E_REG (
input clk,
input reset,
input en,
input [31:0] instr_in,
input [31:0] PC_in,
input [31:0] rs_data_in,
input [31:0] rt_data_in,
input [31:0] EXT_in,
input flag_in,
output reg [31:0] instr_out,
output reg [31:0] PC_out,
output reg [31:0] rs_data_out,
ou... | 7.3967 |
module E_TABLE (
clk,
addr,
out
);
input wire clk;
input wire [7:0] addr;
output reg [7:0] out;
reg [7:0] rom[0:255];
initial begin
$readmemh("E_TABLE.txt", rom);
end
always @(posedge clk) begin
out <= rom[addr];
end
//assign out=out_reg;
endmodule
| 6.970503 |
module f-d
(
input wire clock,
input wire [31:0] instr_in,
input wire [31:0] pc,
input wire decode_enable_in,
input wire enable,
output reg [31:0] out_pc,
output reg [31:0] instr_out,
output reg decode_enable_out;
/*output wire [31:0] in_s1,
output wire [31:0] in_s2,
output wire [25:0] offset,
output... | 6.969247 |
module F_D (
input clk,
input rst,
input STALL,
input [31:0] PCIn,
input [31:0] instructionIn,
output reg [31:0] PC,
output reg [31:0] instruction
);
always @(posedge clk) begin
if (rst) begin
PC <= 0;
instruction <= 0;
end else begin
if (STALL) begin
//n... | 8.164926 |
module F0_F1 (
input [31:0] x,
input [31:0] round_key,
input selecao_f0_f1,
output [31:0] result
);
wire [31:0] x_xor_round;
wire [ 7:0] mux_a_temp;
wire [ 7:0] mux_b_temp;
wire [ 7:0] mux_c_temp;
wire [ 7:0] mux_d_temp;
wire [ 7:0] saida_sbox_a;
wire [ 7:0] saida_sbox_b;
wire [ 7:0] sa... | 7.343193 |
module f15_binmap #(
parameter integer BIN_WIDTH = 6,
parameter integer SCALE_FRAC_BITS = 8
) (
input wire [15:0] in_0,
input wire [15:0] offset_0, // unsigned
input wire [15:0] scale_0, // unsigned
output reg [BIN_WIDTH-1:0] bin_5, // bin number
output reg sat_ind_5, // saturation indic... | 7.271912 |
module f15_eoseq #(
parameter integer WIDTH = 16
) (
input wire [WIDTH-1:0] in_data,
input wire in_valid,
input wire in_last,
output reg [WIDTH-1:0] out_data,
output reg out_valid,
output reg out_last,
input wire clk,
input wire rst
);
// Signals
reg [WIDTH-1:0] buf_data;
reg ... | 7.634473 |
module f15_line_mem #(
parameter integer AWIDTH = 12,
parameter integer DWIDTH = 18
) (
input wire [AWIDTH-1:0] rd_addr,
output reg [DWIDTH-1:0] rd_data,
input wire rd_ena,
input wire [AWIDTH-1:0] wr_addr,
input wire [DWIDTH-1:0] wr_data,
input wire wr_ena,
input wire clk,
inpu... | 7.1749 |
module f15_maxhold #(
parameter integer WIDTH = 9
) (
input wire [WIDTH-1:0] yin_0,
input wire [WIDTH-1:0] x_0,
input wire [15:0] epsilon_0,
input wire clear_0,
output wire [WIDTH-1:0] yout_4,
input wire clk,
input wire rst
);
// Signals
reg [WIDTH-1:0] x_1;
reg [WIDTH : 0] y_1;
... | 7.409058 |
module f15_packetizer #(
parameter integer BIN_WIDTH = 6,
parameter integer DECIM_WIDTH = 10
) (
input wire [BIN_WIDTH-1:0] in_bin_addr,
input wire in_bin_last,
input wire [7:0] in_histo,
input wire [7:0] in_spectra_max,
input wire [7:0] in_spectra_avg,
input wire in_last,
input wi... | 6.980175 |
module f15_wf_agg #(
parameter integer Y_WIDTH = 12,
parameter integer X_WIDTH = 16,
parameter integer DECIM_WIDTH = 8
) (
input wire [Y_WIDTH-1:0] yin_0,
input wire [X_WIDTH-1:0] x_0,
input wire valid_0,
input wire last_0,
input wire [15:0] rng_0,
output wire [Y_WIDTH-1:0] yout_3,
... | 7.04589 |
module F16 (
inA,
Z
);
// Assigning ports as in/out
input [15:0] inA;
output Z;
wire [15:0] A;
alt_invert #(16) m (
inA,
A
);
wire Zn;
func16 m2 (
A,
Zn
);
assign Z = ~Zn;
endmodule
| 8.266999 |
module F2 (
inA,
Z
);
// Assigning ports as in/out
input [1:0] inA;
output Z;
assign Z = ~inA[1];
endmodule
| 8.23589 |
module f2i #(
parameter WID = 32
) (
input clk,
input ce,
input [WID-1:0] i,
output [WID-1:0] o,
output overflow
);
localparam MSB = WID - 1;
localparam EMSB = WID==80 ? 14 :
WID==64 ? 10 :
WID==52 ? 10 :
WID==48 ? 10 :
WID==44 ? 10 :
WID==42 ? 10 :
... | 6.647278 |
module f2m_inv #(
parameter M = 163, // degree of f(x)
parameter FX = 163'hc9 // binary representation of f(x)
) (
// System signals
input clk, // system clock
input rst_n, // system asynchronous reset, active low
input clr, // synchronous clear
// Data interface
input ... | 6.920953 |
module f2m_inv_dp #(
parameter M = 163, // degree of f(x)
parameter D_WIDTH = 9 // data width of counter d
) (
// Data interface
input [ M:0] r_i, // input polynomial r(x)
input [ M:0] s_i, // input polynomial s(x)
input [ M:0] u_i, // input poly... | 6.996082 |
module f2m_mul #(
parameter M = 163, // degree of f(x)
parameter FX = 163'hc9, // binary representation of f(x)
parameter NUM_SEG = 3 // number of segment with M, range [1, M]
) (
// System signals
input clk, // system clock
input rst_n, // system asynchronous reset,... | 6.536275 |
module f2m_sqr #(
parameter M = 163, // degree of f(x)
parameter FX = 163'hc9 // binary representation of f(x)
) (
// Data interface
input [M-1:0] a, // input polynomial a(x)
output reg [M-1:0] z // output a(x)^2 mod f(x)
);
// Local signals
wire [M-1:0] xpow[M-2:0]; // xpow(i) =... | 7.84591 |
module f2s_control (
input adat,
rst,
aclk,
bclk,
output reg bdat
);
reg adat1, bdat1, bdat2, bdat3, abdat1, abdat2;
//实例化慢时钟域同步器
always @(posedge bclk or negedge rst) begin
if (~rst) {bdat2, bdat1} <= 2'b00;
else {bdat2, bdat1} <= {bdat1, adat1};
end
//实例化快时钟域同步器
always @(p... | 7.69468 |
module f2s_control (
input adat,
rst,
aclk,
bclk,
output reg bdat
);
reg adat1, bdat1, bdat2, bdat3, abdat1, abdat2, stall;
wire aclk_gt;
//双向同步器
always @(posedge aclk or negedge rst) begin
if (~rst) {abdat2, abdat1} <= 2'b00;
else {abdat2, abdat1} <= {abdat1, bdat2};
end
al... | 7.69468 |
module F32 (
inA,
Z
);
// Assigning ports as in/out
input [31:0] inA;
output Z;
wire [31:0] A;
alt_invert #(32) m (
inA,
A
);
wire Zn;
func32 m2 (
A,
Zn
);
assign Z = ~Zn;
endmodule
| 7.858987 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f32m_sub (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_sub
s1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
s2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.641308 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f32m_add (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_add
a1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
a2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.84182 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f32m_sub (
a,
b,
c
);
input [`W2:0] a, b;
output [`W2:0] c;
f3m_sub
s1 (
a[`W2:`WIDTH+1],
b[`W2:`WIDTH+1],
c[`W2:`WIDTH+1]
),
s2 (
a[`WIDTH:0],
b[`WIDTH:0],
c[`WIDTH:0]
);
endmodule
| 6.641308 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module f33m_mux2 (
v1,
l1,
v2,
l2,
out
);
`define M 97 // M is the degree of the irreducible polynomial
`define WIDTH (2*`M-1) // width for a GF(3^M) element
`define W2 (4*`M-1) // width for a GF(3^{2*M}) element
`define W3 (6*`M-1) // width for a GF(3^{3*M}) element
`def... | 6.851428 |
module f33m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`W3:0] v1, v2, v3;
input l1, l2, l3;
output [`W3:0] out;
genvar i;
generate
for (i = 0; i <= `W3; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
endmodule
... | 6.701979 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module func4 (
A,
aa,
C
);
input [`WIDTH+2:0] A;
input [1:0] aa;
output [`WIDTH+2:0] C;
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_mult m (
A[i+1:i],
aa,
C[i+1:i]
);
end
endgenerate
endmodule
| 7.077584 |
module func2 (
A,
out
);
input [`WIDTH+2:0] A;
output [`WIDTH+2:0] out;
assign out = {A[`WIDTH:0], 2'd0};
endmodule
| 6.95158 |
module func1 (
S,
R,
q,
out
);
input [`WIDTH+2:0] S, R;
input [1:0] q;
output [`WIDTH+2:0] out;
wire [`WIDTH+2:0] t;
func4 f (
R,
q,
t
); // t == q*R
genvar i;
generate
for (i = 0; i <= `WIDTH + 2; i = i + 2) begin : label
f3_sub s1 (
S[i+1:i],
... | 7.258845 |
module f3m_sub (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_sub aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.073169 |
module f3m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`WIDTH:0] v1, v2, v3;
input l1, l2, l3;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
en... | 7.39398 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f33m_mux2 (
v1,
l1,
v2,
l2,
out
);
input [`W3:0] v1, v2;
input l1, l2;
output [`W3:0] out;
genvar i;
generate
for (i = 0; i <= `W3; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2);
end
endgenerate
endmodule
| 6.851428 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f3m_add (
A,
B,
C
);
input [`WIDTH : 0] A, B;
output [`WIDTH : 0] C;
genvar i;
generate
for (i = 0; i < `M; i = i + 1) begin : aa
f3_add aa (
A[(2*i+1) : 2*i],
B[(2*i+1) : 2*i],
C[(2*i+1) : 2*i]
);
end
endgenerate
endmodule
| 7.024046 |
module f3m_mux6 (
v0,
v1,
v2,
v3,
v4,
v5,
l0,
l1,
l2,
l3,
l4,
l5,
out
);
input l0, l1, l2, l3, l4, l5;
input [`WIDTH:0] v0, v1, v2, v3, v4, v5;
output [`WIDTH:0] out;
genvar i;
generate
for (i = 0; i <= `WIDTH; i = i + 1) begin : label
assign out[i... | 6.831576 |
module f33m_mux3 (
v1,
l1,
v2,
l2,
v3,
l3,
out
);
input [`W3:0] v1, v2, v3;
input l1, l2, l3;
output [`W3:0] out;
genvar i;
generate
for (i = 0; i <= `W3; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2) | (v3[i] & l3);
end
endgenerate
endmodule
... | 6.701979 |
module f33m_mux2 (
v1,
l1,
v2,
l2,
out
);
input [`W3:0] v1, v2;
input l1, l2;
output [`W3:0] out;
genvar i;
generate
for (i = 0; i <= `W3; i = i + 1) begin : label
assign out[i] = (v1[i] & l1) | (v2[i] & l2);
end
endgenerate
endmodule
| 6.851428 |
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