code stringlengths 35 6.69k | score float64 6.5 11.5 |
|---|---|
module feature_write_addr_gen_MuxAdd2i1u32u32u1_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001, asc002;
assign asc002 = +(in2) + (32'B00000000000000000000000000000001);
reg [31:0] asc001_tmp_0;
a... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u3u3u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc002;
assign asc002 = +(in2) + (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always ... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u3u3u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc002;
assign asc002 = +(in2) + (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always ... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u3u3u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc002;
assign asc002 = +(in2) + (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
alway... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u3u3u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc002;
assign asc002 = +(in2) + (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
alway... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u3u3u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc002;
assign asc002 = +(in2) + (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
alway... | 7.136373 |
module feature_write_addr_gen_MuxAdd2i1u3u3u1_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc002;
assign asc002 = +(in2) + (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
alway... | 7.136373 |
module feature_write_addr_gen_Muxi0u1u1_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 1'B0;
default: asc00... | 7.136373 |
module feature_write_addr_gen_Muxi0u1u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tmp_0 = 1'B0;
default: asc00... | 7.136373 |
module feature_write_addr_gen_Muxi0u32u1_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tm... | 7.136373 |
module feature_write_addr_gen_Muxi0u32u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tm... | 7.136373 |
module feature_write_addr_gen_Muxi0u32u1_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_Muxi0u32u1_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_Muxi0u32u1_4_2 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_Muxi0u32u1_4_3 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_MuxSubi1u3u3u1_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc003;
assign asc003 = +(in2) - (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @... | 7.136373 |
module feature_write_addr_gen_MuxSubi1u3u3u1_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc003;
assign asc003 = +(in2) - (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @... | 7.136373 |
module feature_write_addr_gen_MuxSubi1u3u3u1_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc003;
assign asc003 = +(in2) - (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always... | 7.136373 |
module feature_write_addr_gen_MuxSubi1u3u3u1_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc003;
assign asc003 = +(in2) - (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always... | 7.136373 |
module feature_write_addr_gen_MuxSubi1u3u3u1_4_2 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc003;
assign asc003 = +(in2) - (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always... | 7.136373 |
module feature_write_addr_gen_MuxSubi1u3u3u1_4_3 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001, asc003;
assign asc003 = +(in2) - (3'B001);
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always... | 7.136373 |
module feature_write_addr_gen_Muxu32i0u1_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_tm... | 7.136373 |
module feature_write_addr_gen_Muxu32i0u1_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_Muxu32i0u1_4_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_Muxu32i0u1_4_2 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: asc001_... | 7.136373 |
module feature_write_addr_gen_Nei7u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (&in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Nei7u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (&in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Nei7u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (&in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Nei7u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (&in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Nei7u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (&in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Nei7u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001, asc002;
assign asc002 = (&in1);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_NotEQ_3Ux3U_1U_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_NotEQ_3Ux3U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_NotEQ_3Ux3U_1U_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_NotEQ_3Ux3U_1U_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_NotEQ_3Ux3U_1U_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_NotEQ_3Ux3U_1U_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2, in1;
output out1;
wire asc001, asc002;
assign asc002 = (in1 == in2);
assign asc001 = ((~asc002));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Not_1U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input in1;
output out1;
wire asc001;
assign asc001 = ((~in1));
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_N_Muxb_1_2_23_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = i... | 7.136373 |
module feature_write_addr_gen_N_Muxb_1_2_23_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input in3, in2, ctrl1;
output out1;
wire asc001;
reg [0:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
1'B1: asc001_tmp_0 = i... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_10_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1:
... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_10_1_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in3, in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
ca... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_10_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1:
... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_10_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_10_4_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in3, in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
ca... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_18_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: ... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_18_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_19_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1:
... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_19_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_21_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1:
... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_22_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: ... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_9_1 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: a... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_9_4 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1: a... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_2_9_4_0 (
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in2;
input ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2) begin
case (ctrl1)
1'B1:... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_8_28_1 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in9, in8, in7, in6, in5, in4, in3, in2;
input [2:0] ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] as... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_8_28_4 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in9, in8, in7, in6, in5, in4, in3, in2;
input [2:0] ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] as... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_8_28_4_0 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in9, in8, in7, in6, in5, in4, in3, in2;
input [2:0] ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] ... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_8_28_4_1 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in9, in8, in7, in6, in5, in4, in3, in2;
input [2:0] ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] ... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_8_28_4_2 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in9, in8, in7, in6, in5, in4, in3, in2;
input [2:0] ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] ... | 7.136373 |
module feature_write_addr_gen_N_MuxB_320_8_31_4 (
in9,
in8,
in7,
in6,
in5,
in4,
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [319:0] in9, in8, in7, in6, in5, in4, in3, in2;
input [2:0] ctrl1;
output [319:0] out1;
wire [319:0] asc001;
reg [319:0] as... | 7.136373 |
module feature_write_addr_gen_N_Mux_32_2_18_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl... | 7.136373 |
module feature_write_addr_gen_N_Mux_32_2_27_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl... | 7.136373 |
module feature_write_addr_gen_N_Mux_32_2_27_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ct... | 7.136373 |
module feature_write_addr_gen_N_Mux_32_2_30_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [31:0] in3, in2;
input ctrl1;
output [31:0] out1;
wire [31:0] asc001;
reg [31:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl... | 7.136373 |
module feature_write_addr_gen_N_Mux_3_2_12_1 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001;
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.136373 |
module feature_write_addr_gen_N_Mux_3_2_12_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001;
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.136373 |
module feature_write_addr_gen_N_Mux_3_2_12_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001;
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.136373 |
module feature_write_addr_gen_N_Mux_3_2_21_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001;
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.136373 |
module feature_write_addr_gen_N_Mux_3_2_21_4_0 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001;
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.136373 |
module feature_write_addr_gen_N_Mux_3_2_24_4 (
in3,
in2,
ctrl1,
out1
); /* architecture "behavioural" */
input [2:0] in3, in2;
input ctrl1;
output [2:0] out1;
wire [2:0] asc001;
reg [2:0] asc001_tmp_0;
assign asc001 = asc001_tmp_0;
always @(ctrl1 or in2 or in3) begin
case (ctrl1)
... | 7.136373 |
module feature_write_addr_gen_OrReduction_3U_1U_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_OrReduction_3U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_OrReduction_3U_1U_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_OrReduction_3U_1U_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_OrReduction_3U_1U_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_OrReduction_3U_1U_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_OrReduction_4U_1U_4 (
in1,
out1
); /* architecture "behavioural" */
input [3:0] in1;
output out1;
wire asc001;
assign asc001 = (|in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Or_1Ux1U_1U_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input in2, in1;
output out1;
wire asc001;
assign asc001 = (in2) | (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Subi1u3_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) - (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Subi1u3_4 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) - (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Subi1u3_4_0 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) - (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Subi1u3_4_1 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) - (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Subi1u3_4_2 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) - (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Subi1u3_4_3 (
in1,
out1
); /* architecture "behavioural" */
input [2:0] in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in1) - (3'B001);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Sub_3Ux1U_3S_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Sub_3Ux1U_3S_4 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Sub_3Ux1U_3S_4_0 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Sub_3Ux1U_3S_4_1 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Sub_3Ux1U_3S_4_2 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module feature_write_addr_gen_Sub_3Ux1U_3S_4_3 (
in2,
in1,
out1
); /* architecture "behavioural" */
input [2:0] in2;
input in1;
output [2:0] out1;
wire [2:0] asc001;
assign asc001 = +(in2) - (in1);
assign out1 = asc001;
endmodule
| 7.136373 |
module for the feature_write_addr_gen module.
*
* This module contains the followng items:
* - A foreign module definition for use in instantiatin the type_wrapper module
* which contains the BEH module instance.
* - An instance of the type_wrapper foreign module.
* - alwyas blocks each type_wrapper output.
*
**... | 7.070109 |
module fec32 (
clk_6M,
rstz,
loadini_p,
shift_in,
shift_out,
datvalid_p,
fec32_datin,
fec32rem,
syndrome
);
input clk_6M, rstz;
input loadini_p, shift_in, shift_out, datvalid_p;
input fec32_datin;
output [4:0] fec32rem;
output [4:0] syndrome;
// fec32 encode
wire fec... | 7.008032 |
module fechDecodeRegTB ();
localparam N = 16;
localparam T = 100;
reg [N-1:0] in;
wire [N-1:0] out;
reg write_en;
reg clck;
reg reset;
fech_decode_reg #(N) FDTB (
.IR_in(in),
.write_en(write_en),
.IR_out(out),
.clk(clck),
.reset(reset)
);
initial begin
write_en = ... | 6.5318 |
module fec_buffer
#(parameter blk_width = 768)
(
input reset, clk,
input fec_out_bits,
input fec_out_valid,
output [blk_width - 1:0],
output blk_valid,
input advance);
endmodule
| 7.223374 |
module fec_gen (
input clk,
arst,
input [31:0] din,
input parity_sel, // the next tick's dout is to be the parity word
output reg [31:0] dout
);
`include "reverse_32.inc"
///////////////////////////
// parity workhorse
reg [31:0] parity;
wire [31:0] next_parity;
fec_parity fs (
... | 7.717534 |
module fec_rot_10 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[22] ^ c[31];
assign co[1] = c[23];
assign co[2] = c[22] ^ c[24] ^ c[31];
assign co[3] = c[23] ^ c[25];
assign co[4] = c[24] ^ c[26];
assign co[5] = c[25] ^ c[27];
assign co[6] = c[26] ^ c[28];
assign co[7] ... | 6.805309 |
module fec_rot_11 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[21] ^ c[30];
assign co[1] = c[22] ^ c[31];
assign co[2] = c[21] ^ c[23] ^ c[30];
assign co[3] = c[22] ^ c[24] ^ c[31];
assign co[4] = c[23] ^ c[25];
assign co[5] = c[24] ^ c[26];
assign co[6] = c[25] ^ c[27];
... | 6.673418 |
module fec_rot_12 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[20] ^ c[29] ^ c[31];
assign co[1] = c[21] ^ c[30];
assign co[2] = c[20] ^ c[22] ^ c[29];
assign co[3] = c[21] ^ c[23] ^ c[30];
assign co[4] = c[22] ^ c[24] ^ c[31];
assign co[5] = c[23] ^ c[25];
assign co[6] = ... | 7.045719 |
module fec_rot_13 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[19] ^ c[28] ^ c[30];
assign co[1] = c[20] ^ c[29] ^ c[31];
assign co[2] = c[19] ^ c[21] ^ c[28];
assign co[3] = c[20] ^ c[22] ^ c[29];
assign co[4] = c[21] ^ c[23] ^ c[30];
assign co[5] = c[22] ^ c[24] ^ c[31];
... | 6.926226 |
module fec_rot_14 (
input [31:0] c,
output [31:0] co
);
assign co[0] = c[18] ^ c[27] ^ c[29];
assign co[1] = c[19] ^ c[28] ^ c[30];
assign co[2] = c[18] ^ c[20] ^ c[27] ^ c[31];
assign co[3] = c[19] ^ c[21] ^ c[28];
assign co[4] = c[20] ^ c[22] ^ c[29];
assign co[5] = c[21] ^ c[23] ^ c[... | 7.42241 |
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