repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
glennchid/font5-firmware | src/verilog/synthesis/MuxModule.v | 2,023 | module MODULE1(
input VAR16,
input [1:0] sel,
input signed [12:0] VAR12,
input signed [12:0] VAR11,
input signed [12:0] VAR3,
input signed [12:0] VAR19,
input signed [12:0] VAR17,
input signed [12:0] VAR13,
output reg signed [16:0] VAR6,
output reg signed [16:0] VAR7,
output reg signed [16:0] VAR20,
output reg signed [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fahcin/sky130_fd_sc_hs__fahcin.functional.v | 2,648 | module MODULE1 (
VAR2,
VAR21 ,
VAR16 ,
VAR13 ,
VAR4 ,
VAR24,
VAR5
);
output VAR2;
output VAR21 ;
input VAR16 ;
input VAR13 ;
input VAR4 ;
input VAR24;
input VAR5;
wire VAR8 ;
wire VAR6 ;
wire VAR12 ;
wire VAR1 ;
wire VAR10 ;
wire VAR26 ;
wire VAR11 ;
wire VAR22;
not VAR17 (VAR8 , VAR4 );
xor VAR3 (VAR6 , VAR16, VAR13, ... | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_ddr_dma_controller.v | 11,857 | module MODULE1(
input VAR9,
input VAR61,
input VAR66,
input VAR36,
output reg VAR30,
input VAR6,
input [31:0] VAR75,
input [31:0] VAR62,
output reg VAR43,
input VAR87,
output reg [11:0] VAR10,
output reg [31:0] VAR99,
output reg [7:0] VAR77,
input [7:0] VAR90,
input VAR52,
input [63:0] VAR92,
input VAR24,
output reg VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxbp/sky130_fd_sc_ms__dfxbp.symbol.v | 1,338 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR3,
input VAR1
);
supply1 VAR4;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.behavioral.pp.v | 1,895 | module MODULE1 (
VAR5,
VAR6,
VAR9 ,
VAR4 ,
VAR11 ,
VAR1 ,
VAR10
);
input VAR5;
input VAR6;
output VAR9 ;
input VAR4 ;
input VAR11 ;
input VAR1 ;
input VAR10 ;
wire VAR10 VAR7 ;
wire VAR13 ;
wire VAR3;
not VAR14 (VAR7 , VAR4 );
nand VAR15 (VAR13 , VAR10, VAR1, VAR11, VAR7 );
VAR12 VAR8 (VAR3, VAR13, VAR5, VAR6);
buf VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.pp.symbol.v | 1,367 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR2 ,
input VAR5 ,
input VAR8 ,
output VAR6 ,
input VAR7,
input VAR4
);
endmodule | apache-2.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_rp/bg_rp_stub.v | 1,258 | module MODULE1(VAR5, VAR4, VAR3, VAR2, VAR1)
;
input VAR5;
input [0:0]VAR4;
input [7:0]VAR3;
input [11:0]VAR2;
output [11:0]VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn_2.v | 2,312 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR10 ,
VAR9,
VAR5 ,
VAR7 ,
VAR4 ,
VAR2
);
output VAR6 ;
output VAR1 ;
input VAR10 ;
input VAR9;
input VAR5 ;
input VAR7 ;
input VAR4 ;
input VAR2 ;
VAR8 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MOD... | apache-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_dds_2.v | 5,250 | module MODULE1 #(
parameter VAR16 = 16,
parameter VAR10 = 16,
parameter VAR2 = 1,
parameter VAR28 = 16,
parameter VAR23 = 16) (
input clk,
input VAR14,
input [VAR10-1:0] VAR6,
input [ 15:0] VAR5,
input [VAR10-1:0] VAR9,
input [ 15:0] VAR4,
output [ VAR16-1:0] VAR31);
localparam VAR29 = 1;
localparam VAR18 = 2;
localpar... | mit |
oceanborn-mx/sirius | src.verilog/Multiplicacion_Matricial_2DMesh/Multiplicacion_Matricial_2DMesh/src/arreglo_2dmesh.v | 1,028 | module MODULE1 (
input VAR16, input VAR1, input[3:0] VAR30,VAR31, input[3:0] VAR10,VAR8, input VAR21, input VAR24, input[3:0] VAR12, input[3:0] VAR18, output[7:0] VAR4,VAR29, output[7:0] VAR25,VAR27
);
wire[3:0] VAR17,VAR19,VAR9;
wire[3:0] VAR3,VAR32,VAR11;
VAR5 VAR6(VAR16,VAR1,VAR12[0],VAR18[0],VAR30,VAR10,VAR4);
VAR7... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.pp.symbol.v | 1,368 | module MODULE1 (
input VAR7 ,
input VAR9 ,
input VAR5 ,
input VAR3 ,
output VAR2 ,
input VAR1 ,
input VAR4,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
em15-10122510310-dongxinyue/Em15_310_dongxinyue_lab1 | lab1/lab1/lab1.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_regc.v | 2,173 | module MODULE1(
VAR18,
VAR10,
VAR27,
VAR37,
VAR16,
VAR39,
VAR12,
VAR3,
VAR26,
VAR42,
VAR31,
VAR9,
VAR4,
VAR23
);
input VAR18;
input VAR10;
input VAR27;
output VAR37;
input[31:0] VAR16;
output[1023:0] VAR39;
input[7:0] VAR12;
input [3:0] VAR3;
input VAR26;
output VAR42;
input[31:0] VAR31;
output[1023:0] VAR9;
input[7:0]... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/wb_altera_ddr_wrapper/bench/ddr_ctrl_ip/alt_mem_ddrx_lpddr2_addr_cmd.v | 16,892 | module MODULE1
VAR27 = 1,
VAR23 = 1,
VAR16 = 1, VAR40 = 20,
VAR48 = 15, VAR17 = 12, VAR49 = 3, VAR26 = 2
)
(
VAR28,
VAR29,
VAR1,
VAR25,
VAR36,
VAR20,
VAR9,
VAR51,
VAR44,
VAR15,
VAR53,
VAR19,
VAR8,
VAR7,
VAR52,
VAR38, VAR47, VAR55, VAR24,
VAR43, VAR12,
VAR2,
VAR45,
VAR42,
VAR21,
VAR13,
VAR4,
VAR37,
VAR32
);
input VAR28;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.symbol.v | 1,370 | module MODULE1 (
input VAR6,
output VAR1
);
supply1 VAR2;
supply1 VAR5 ;
supply0 VAR4 ;
supply1 VAR3 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_hdmi_tx.v | 12,771 | module MODULE1 (
VAR84,
VAR85,
VAR63,
VAR41,
VAR1,
VAR14,
VAR32,
VAR49,
VAR18,
VAR86,
VAR56,
VAR69,
VAR33,
VAR8,
VAR39,
VAR15,
VAR19,
VAR50,
VAR35,
VAR12,
VAR4,
VAR45,
VAR24,
VAR38,
VAR25,
VAR81,
VAR22,
VAR70,
VAR48,
VAR57,
VAR87,
VAR3,
VAR51,
VAR76,
VAR68);
localparam VAR78 = 32'h00040063;
parameter VAR17 = 0;
input V... | gpl-3.0 |
joaocarlos/udlx-verilog | rtl/decode/signal_extend.v | 1,816 | module MODULE1
parameter VAR2 = 32,
parameter VAR3 = 16
)(
input [VAR3-1:0] VAR1,
output [VAR2-1:0] VAR4
);
assign VAR4 = {{(VAR2-VAR3){VAR1[VAR3-1]}},VAR1};
endmodule | lgpl-3.0 |
Team-Jared/tera-computer | src/registers.v | 2,368 | module MODULE1 (VAR24, VAR4, VAR3, VAR25, VAR8, VAR2, VAR23, VAR6);
output [7:0] VAR24, VAR4;
input [7:0] VAR3, VAR25;
input [3:0] VAR8;
input VAR2, VAR23, VAR6;
reg [7:0] VAR15 [0:15];
wire [7:0] VAR16, VAR5, VAR21, VAR10, VAR1, VAR9, VAR19, VAR18, VAR7, VAR20, VAR11, VAR17, VAR12, VAR22, VAR13;
assign VAR16 = VAR15[1... | mit |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_fp_custom_add_double_ll.v | 1,515 | module MODULE1 (
VAR1,
VAR6,
VAR10,
VAR9,
VAR11,
enable);
input enable;
input VAR1, VAR6;
input [63:0] VAR10;
input [63:0] VAR9;
output [63:0] VAR11;
VAR14 VAR8(
.VAR1(VAR1),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR13(),
.VAR3(),
.VAR7(),
.VAR15(),
.enable(enable));
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi_0.v | 2,332 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR7,
VAR9,
VAR2,
VAR5 ,
VAR10
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR7;
input VAR9;
input VAR2;
input VAR5 ;
input VAR10 ;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.blackbox.v | 1,303 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR4 ,
VAR2
);
output VAR3 ;
output VAR6 ;
input VAR4 ;
input VAR2;
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
hakehuang/pycpld | ips/ip/spi_master/spi_master.v | 5,939 | module MODULE1(
clk,VAR22,
VAR3,VAR17,VAR6,
VAR1,VAR5,VAR15,VAR9,VAR21,VAR4
);
input clk;
input VAR22;
input VAR3;
output VAR17;
output VAR6;
input VAR1;
output VAR15;
output VAR4;
input VAR5;
input VAR9;
input VAR21;
reg[7:0] VAR18;
reg[7:0] VAR19;
reg[7:0] VAR13;
reg[4:0] VAR7;
reg VAR11;
reg VAR10;
reg VAR20;
reg VA... | mit |
VCTLabs/DE1_SOC_Linux_FB | soc_system/submodules/hps_sdram_p0_altdqdqs.v | 6,964 | module MODULE1 (
VAR26,
VAR29,
VAR12,
VAR73,
VAR67,
VAR79,
VAR71,
VAR32,
VAR51,
VAR21,
VAR92,
VAR49,
VAR37,
VAR36,
VAR63,
VAR60,
VAR6,
VAR19,
VAR39,
VAR15,
VAR34,
VAR53,
VAR24,
VAR48,
VAR11,
VAR16,
VAR20,
VAR70,
VAR42,
VAR50,
VAR38,
VAR66,
VAR90,
VAR91,
VAR1,
VAR89,
VAR93,
VAR25
);
input [7-1:0] VAR25;
input VAR26;
inp... | epl-1.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/parser.v | 7,494 | module MODULE1(
input clk,
input VAR24,
input VAR11,
input [133:0] VAR21,
input VAR18,
input VAR16,
output VAR20,
output reg VAR23,
output [287:0] VAR22,
output VAR6,
output [133:0] VAR5,
input VAR10
);
reg [7:0] VAR25,VAR19;
reg [7:0] VAR3;
reg [47:0] VAR15;
reg [47:0] VAR13;
reg [15:0] VAR9;
reg [7:0] VAR7;
reg [31:0... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o_1.v | 2,463 | module MODULE2 (
VAR3 ,
VAR10,
VAR9,
VAR7 ,
VAR4 ,
VAR1,
VAR6,
VAR5 ,
VAR2
);
output VAR3 ;
input VAR10;
input VAR9;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR5 ;
input VAR2 ;
VAR8 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR2(VA... | apache-2.0 |
qmn/riscv-invicta | hardware/src/regfile.v | 1,829 | module MODULE1 (
input clk,
input reset,
output [31:0] VAR6,
output [31:0] VAR7,
input [4:0] VAR3,
input [4:0] VAR8,
input [4:0] VAR2,
input [31:0] VAR9,
input VAR5,
input VAR4);
reg [31:0] VAR1[31:0];
always @ (posedge clk) begin
if (VAR5 & !VAR4 & VAR2 != 0)
VAR1[VAR2] <= VAR9;
end
assign VAR6 = VAR3 == 0 ? 32'b0 : V... | bsd-2-clause |
anderson1008/NOCulator | hring/hw/buffered/src/c_regfile.v | 8,979 | module MODULE1
(clk, VAR43, VAR9, VAR13, VAR8, VAR34);
parameter VAR17 = 8;
parameter VAR30 = 64;
parameter VAR36 = 1;
parameter VAR15 = VAR38;
localparam VAR31 = VAR32(VAR17);
input clk;
input VAR43;
input [0:VAR31-1] VAR9;
input [0:VAR30-1] VAR13;
input [0:VAR36*VAR31-1] VAR8;
output [0:VAR36*VAR30-1] VAR34;
wire [0:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.pp.blackbox.v | 1,307 | module MODULE1 (
VAR6,
VAR3 ,
VAR5,
VAR7 ,
VAR2,
VAR1,
VAR8 ,
VAR4
);
output VAR6;
input VAR3 ;
input VAR5;
input VAR7 ;
input VAR2;
input VAR1;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
davidjabon/AXI-Peripheral-Library | Eight_Digit_Seven_Segment_Display_2.0/hdl/Eight_Digit_Seven_Segment_Display_v2_0.v | 2,479 | module MODULE1 #
(
parameter integer VAR22 = 32,
parameter integer VAR23 = 4
)
(
output wire [6:0] VAR3,
output wire VAR34,
output wire [7:0] VAR19,
input wire VAR13,
input wire VAR16,
input wire [VAR23-1 : 0] VAR45,
input wire [2 : 0] VAR51,
input wire VAR39,
output wire VAR24,
input wire [VAR22-1 : 0] VAR40,
input wi... | gpl-2.0 |
alexforencich/verilog-ethernet | rtl/eth_mac_phy_10g.v | 7,046 | module MODULE1 #
(
parameter VAR16 = 64,
parameter VAR17 = (VAR16/8),
parameter VAR81 = (VAR16/32),
parameter VAR46 = 1,
parameter VAR7 = 1,
parameter VAR79 = 64,
parameter VAR74 = 4'h6,
parameter VAR9 = 16'h6666,
parameter VAR55 = 0,
parameter VAR36 = 96,
parameter VAR66 = VAR55,
parameter VAR63 = 16,
parameter VAR20 ... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_ic_ram.v | 7,442 | module MODULE1(
clk, rst,
VAR19, VAR4, VAR2,
addr, en, VAR10, VAR7, VAR15
);
parameter VAR3 = VAR1;
parameter VAR14 = VAR18;
input clk;
input rst;
input [VAR14-1:0] addr;
input en;
input [3:0] VAR10;
input [VAR3-1:0] VAR7;
output [VAR3-1:0] VAR15;
input VAR19;
input [VAR12 - 1:0] VAR2;
output VAR4;
assign VAR15 = {VAR3... | gpl-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/serdes_n_to_1_s16_diff.v | 10,452 | module MODULE1 (VAR44, VAR79, reset, VAR52, VAR9, VAR77, VAR40, VAR64, VAR33, VAR66, VAR3) ;
parameter integer VAR12 = 10 ; parameter integer VAR35 = 16 ;
input VAR44 ; input VAR79 ; input reset ; input VAR52 ; input VAR9 ; input [(VAR35*VAR12)-1:0] VAR77 ; input [VAR12-1:0] VAR40 ; output [VAR35-1:0] VAR64 ; output [V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2b/sky130_fd_sc_hd__and2b.functional.pp.v | 1,934 | module MODULE1 (
VAR13 ,
VAR14 ,
VAR5 ,
VAR9,
VAR6,
VAR2 ,
VAR7
);
output VAR13 ;
input VAR14 ;
input VAR5 ;
input VAR9;
input VAR6;
input VAR2 ;
input VAR7 ;
wire VAR15 ;
wire VAR4 ;
wire VAR12;
not VAR3 (VAR15 , VAR14 );
and VAR1 (VAR4 , VAR15, VAR5 );
VAR8 VAR11 (VAR12, VAR4, VAR9, VAR6);
buf VAR10 (VAR13 , VAR12 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.pp.blackbox.v | 1,307 | module MODULE1 (
VAR2,
VAR8 ,
VAR5,
VAR4 ,
VAR6,
VAR1,
VAR3 ,
VAR7
);
output VAR2;
input VAR8 ;
input VAR5;
input VAR4 ;
input VAR6;
input VAR1;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
hightoon/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_STATUS_IN.v | 5,843 | module MODULE1(
input VAR2,
input VAR9,
output reg VAR14, output reg VAR4, output reg VAR7, input VAR10,
output reg VAR13 );
reg VAR15;
reg VAR11;
reg VAR12; reg [2:0] VAR5;
reg [7:0] VAR1;
parameter VAR17 = 2'b00;
parameter VAR16 = 2'b01;
parameter VAR3 = 2'b10;
parameter VAR8 = 2'b11;
reg [1:0] VAR6;
always @ ( neged... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4.functional.pp.v | 1,837 | module MODULE1 (
VAR13 ,
VAR3 ,
VAR8 ,
VAR14 ,
VAR5 ,
VAR6,
VAR2,
VAR9 ,
VAR4
);
output VAR13 ;
input VAR3 ;
input VAR8 ;
input VAR14 ;
input VAR5 ;
input VAR6;
input VAR2;
input VAR9 ;
input VAR4 ;
wire VAR10 ;
wire VAR11;
and VAR15 (VAR10 , VAR3, VAR8, VAR14, VAR5 );
VAR7 VAR1 (VAR11, VAR10, VAR6, VAR2);
buf VAR12 (V... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/duc_chain.v | 6,362 | module MODULE1
parameter VAR78 = 0,
parameter VAR42 = 0,
parameter VAR109 = 24
)
(input clk, input rst, input VAR52,
input VAR11, input [7:0] VAR72, input [31:0] VAR65,
input VAR40, input [7:0] VAR95, input [31:0] VAR7,
output [VAR109-1:0] VAR69,
output [VAR109-1:0] VAR26,
input [31:0] VAR67,
input VAR107,
output VAR62... | gpl-2.0 |
SymbiFlow/yosys-f4pga-plugins | ql-qlf-plugin/pp3/abc9_map.v | 1,409 | module MODULE1 (
output VAR10,
input VAR13,
input VAR11,
input VAR14,
input VAR4,
input VAR5
);
parameter VAR1 = 1'b0;
parameter VAR2 = 1'b0;
parameter VAR8 = 1'b0;
parameter VAR6 = 1'b0;
parameter VAR9 = 1'b0;
if (VAR2 != 1'b0 && VAR8 != 1'b0 && VAR6 == 1'b0 && VAR9 == 1'b0)
VAR12 VAR3 (.VAR10(VAR10), .VAR13(VAR13), .... | apache-2.0 |
migajv/mips_pipeline | verilog/regm.v | 2,281 | module MODULE1(
input wire clk,
input wire rst,
input wire [4:0] VAR3, VAR4,
output wire [31:0] VAR8, VAR2,
input wire VAR7,
input wire [4:0] VAR9,
input wire [31:0] VAR1);
reg [31:0] VAR6 [0:31];
reg [31:0] VAR8, VAR2;
integer VAR5; | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxbn/sky130_fd_sc_ms__dlxbn.symbol.v | 1,368 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR8 ,
input VAR3
);
supply1 VAR7;
supply0 VAR1;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
bluespec/Flute | builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkCSR_MIE.v | 3,367 | module MODULE1(VAR15,
VAR3,
VAR19,
VAR6,
VAR24,
VAR16,
VAR21,
VAR20);
input VAR15;
input VAR3;
input VAR19;
output [31 : 0] VAR6;
input [27 : 0] VAR24;
input [31 : 0] VAR16;
input VAR21;
output [31 : 0] VAR20;
wire [31 : 0] VAR20, VAR6;
reg [11 : 0] VAR17;
wire [11 : 0] VAR12;
wire VAR1;
wire VAR18,
VAR10,
VAR8,
VAR7;
... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_port_lookup/cam_router/src/ip_arp.v | 8,745 | module MODULE1
parameter VAR67 = VAR29,
parameter VAR4 = VAR7(VAR67)
)
( input [31:0] VAR50,
input [VAR61-1:0] VAR41,
input VAR51,
input VAR20,
output [47:0] VAR52,
output [VAR61-1:0] VAR13,
output VAR32,
output VAR6,
output VAR46,
input VAR44,
input [VAR4-1:0] VAR14, input VAR83, output [47:0] VAR77, output [31:0] VAR... | mit |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/rng.v | 1,925 | module MODULE1(reset, VAR10, VAR5, VAR7, VAR6, VAR3, VAR1, VAR9);
input reset, VAR10, VAR6;
input VAR5, VAR7;
output VAR3, VAR1;
output [15:0] VAR9;
reg [15:0] VAR8;
reg [3:0] VAR4;
assign VAR9[15:0] = VAR8[15:0];
assign VAR3 = VAR8[VAR4];
assign VAR1 = (VAR4 == 0);
reg VAR2;
always @ (posedge VAR6 or posedge reset) be... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/inv/sky130_fd_sc_ls__inv_8.v | 1,995 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR1,
VAR3,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR1;
input VAR3;
input VAR5 ;
input VAR4 ;
VAR8 VAR2 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR7,
VAR6
);
output VAR7;
input VAR6;
supply1 VAR1;
supply0 VAR3;... | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/cheat.v | 12,539 | module MODULE1(
input clk,
input [7:0] VAR31,
input [23:0] VAR59,
input [7:0] VAR7,
input VAR55,
input VAR4,
input VAR61,
input VAR23,
input VAR41,
input VAR11,
input VAR39,
input VAR44,
input VAR66,
input VAR40,
input VAR50,
input VAR37,
input [2:0] VAR42,
input VAR16,
input [31:0] VAR28,
output [7:0] VAR20,
output VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.pp.symbol.v | 1,474 | module MODULE1 (
input VAR6 ,
output VAR8 ,
output VAR2 ,
input VAR3,
input VAR7 ,
input VAR1 ,
input VAR10 ,
input VAR4 ,
input VAR5 ,
input VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32ai/sky130_fd_sc_ms__o32ai.symbol.v | 1,391 | module MODULE1 (
input VAR10,
input VAR8,
input VAR3,
input VAR4,
input VAR1,
output VAR2
);
supply1 VAR9;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/Video_System/submodules/altera_up_video_camera_decoder.v | 7,480 | module MODULE1 (
clk,
reset,
VAR14,
VAR2,
VAR4,
ready,
VAR1,
VAR10,
VAR15,
valid
);
parameter VAR12 = 9;
input clk;
input reset;
input [VAR12: 0] VAR14;
input VAR2;
input VAR4;
input ready;
output reg [VAR12: 0] VAR1;
output reg VAR10;
output reg VAR15;
output reg valid;
wire VAR9;
reg [VAR12: 0] VAR13;
reg VAR8;
reg V... | gpl-2.0 |
jmahler/EECE344-Digital_System_Design | lab02/CPLD/main.v | 2,330 | module MODULE1(
input wire VAR15,
input wire VAR10,
input wire VAR12,
input wire VAR13,
output wire VAR4,
output wire [7:0] VAR6,
input wire [7:0] VAR3
);
VAR7 VAR1(.VAR7(VAR15));
parameter VAR9=7;
wire [VAR9:0] VAR5; assign VAR5 = ~(VAR3);
reg [VAR9:0] VAR8;
wire [VAR9:0] VAR2;
reg [VAR9:0] VAR14;
assign VAR6 = ~(VAR1... | gpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_freeze.v | 8,060 | module MODULE1(
clk, rst,
VAR18, VAR15, VAR19, VAR5, VAR20,
VAR16, VAR1, VAR3,
VAR21, VAR10,
VAR7, VAR2, VAR8, VAR17, VAR12,
VAR6, VAR11
);
input clk;
input rst;
input [VAR14-1:0] VAR18;
input VAR15;
input VAR19;
input VAR5;
input VAR20;
input VAR16;
input VAR21;
input VAR10;
input VAR1;
input VAR3;
output VAR7;
output... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/einvn/sky130_fd_sc_hd__einvn.functional.pp.v | 1,872 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR8,
VAR1,
VAR13,
VAR10 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR8;
input VAR1;
input VAR13;
input VAR10 ;
input VAR7 ;
wire VAR4 ;
wire VAR6;
VAR9 VAR2 (VAR4 , VAR3, VAR1, VAR13 );
VAR9 VAR11 (VAR6, VAR8, VAR1, VAR13 );
notif0 VAR12 (VAR5 , VAR4, VAR6);
endmodule | apache-2.0 |
parallella/oh | parallella/hdl/pi2c.v | 1,410 | module MODULE1 (
VAR4, VAR9,
VAR2, VAR12,
VAR11, VAR18, VAR1, VAR10
);
parameter VAR22 = 0;
input VAR11;
input VAR18;
output VAR4;
input VAR1;
input VAR10;
output VAR9;
inout VAR2;
inout VAR12;
generate
if(VAR22==1) begin
wire VAR2 = VAR18 ? 1'VAR6: VAR11;
wire VAR4 = VAR2;
wire VAR12 = VAR10 ? 1'VAR6 : VAR1;
wire VAR9... | mit |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/Raster_Laser_Projector_Video_In_avalon_st_adapter.v | 6,847 | module MODULE1 #(
parameter VAR24 = 8,
parameter VAR6 = 1,
parameter VAR20 = 8,
parameter VAR27 = 1,
parameter VAR2 = 0,
parameter VAR29 = 0,
parameter VAR25 = 1,
parameter VAR21 = 1,
parameter VAR16 = 0,
parameter VAR13 = 8,
parameter VAR11 = 0,
parameter VAR14 = 0,
parameter VAR28 = 0,
parameter VAR23 = 1,
parameter ... | gpl-3.0 |
BigEd/beeb816 | pcb/bufboard.v | 3,033 | module MODULE1();
supply0 VAR72;
supply1 VAR85;
supply1 VAR74;
wire VAR7, VAR55, VAR82, VAR46, VAR73, VAR64, VAR6, VAR2;
wire VAR36, VAR68, VAR61, VAR21, VAR71, VAR59, VAR15, VAR79;
wire VAR33, VAR93, VAR84, VAR69, VAR5, VAR88, VAR11, VAR98;
wire VAR90, VAR103, VAR75, VAR76, VAR101, VAR4, VAR9 ;
wire VAR99, VAR27, VAR7... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sedfxtp/sky130_fd_sc_hd__sedfxtp.symbol.v | 1,493 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR7 ,
input VAR3,
input VAR1,
input VAR10
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_us_1/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_rd_cmd_fsm.v | 4,197 | module MODULE1 (
input wire clk ,
input wire reset ,
output wire VAR13 ,
input wire VAR9 ,
input wire [7:0] VAR6 ,
output wire VAR12 ,
input wire VAR3 ,
output wire VAR17 ,
input wire VAR16 ,
input wire VAR11 ,
output wire VAR1 ,
output wire VAR7
);
localparam VAR10 = 2'b00;
localparam VAR14 = 2'b01;
localparam VAR4 = ... | mit |
perillamint/humbleverilogcalc | sixbitdiv.v | 2,242 | module MODULE1 (VAR14, VAR25, VAR1, VAR20, VAR2);
input[5:0] VAR14;
input[5:0] VAR25;
output[5:0] VAR1;
output[5:0] VAR20;
output VAR2;
wire[5:0] VAR6;
wire[5:0] VAR13;
wire[5:0] VAR5;
wire[5:0] VAR12;
wire[5:0] VAR23;
wire[5:0] VAR21;
wire[5:0] VAR10;
wire[5:0] VAR11;
wire[5:0] VAR3;
wire[5:0] VAR22;
wire[5:0] VAR26;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso0p/sky130_fd_sc_lp__iso0p.behavioral.pp.v | 2,034 | module MODULE1 (
VAR7 ,
VAR13 ,
VAR15,
VAR12,
VAR2 ,
VAR9 ,
VAR4
);
output VAR7 ;
input VAR13 ;
input VAR15;
input VAR12;
input VAR2 ;
input VAR9 ;
input VAR4 ;
wire VAR6 ;
wire VAR1 ;
wire VAR5;
not VAR11 (VAR6 , VAR15 );
VAR3 VAR14 (VAR1 , VAR13, VAR12, VAR2 );
VAR3 VAR10 (VAR5, VAR6, VAR12, VAR2 );
and VAR8 (VAR7 , ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxtp/sky130_fd_sc_hs__sdfxtp.pp.blackbox.v | 1,310 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR6,
VAR1
);
input VAR3 ;
input VAR2 ;
output VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR6;
input VAR1;
endmodule | apache-2.0 |
aabdelfattah/alhaitham-hardware | v/rgb2hsv.v | 15,713 | module MODULE1(
clk,
VAR14,
rst,
VAR4,
VAR7
);
input clk, rst;
input[31:0] VAR4 ;output[31:0] VAR7;
input VAR14 ;
reg[31:0] VAR7 ;
reg[7:0] VAR13[2:0]; reg[19:0] VAR10 ;
wire[7:0] VAR16;
reg[31:0] VAR8 ;
reg signed [9:0] VAR11;reg[15:0] VAR18, VAR1;
reg[15:0] VAR12, VAR5;
wire[15:0] VAR20, VAR17;
reg[2:0] VAR9;
reg[2:0... | gpl-3.0 |
fbalakirev/red-pitaya-notes | cores/axis_accumulator_v1_0/axis_accumulator.v | 3,912 | module MODULE1 #
(
parameter integer VAR23 = 16,
parameter integer VAR16 = 32,
parameter integer VAR1 = 16,
parameter VAR32 = "VAR7",
parameter VAR14 = "VAR7"
)
(
input wire VAR21,
input wire VAR28,
input wire [VAR1-1:0] VAR2,
output wire VAR26,
input wire [VAR23-1:0] VAR3,
input wire VAR15,
input wire VAR19,
output wi... | mit |
Madh93/scpu | modules/vga.v | 1,419 | module MODULE1(
input reset, VAR10,
input wire VAR9,
input wire [7:0] VAR6,
input wire [6:0] VAR8,
input wire [7:0] pos,
input VAR11,
output [3:0] VAR1, VAR16, VAR2,
output VAR14, VAR4, VAR7, VAR5, VAR15);
wire [7:0] VAR6;
wire [6:0] VAR8;
wire [2:0] VAR9;
assign VAR6 = VAR6 + 10 + ((pos%5)*8'b00000101); assign VAR8 = ... | mit |
AnttiLukats/orp | hardware/mselSoC/src/systems/geophyte/rtl/verilog/crypto_sha256/rtl/verilog/wb_sha256_ctrl.v | 5,640 | module MODULE1 (
input VAR25,
input VAR15,
input [6:0] VAR28,
input [31:0] VAR18,
input [3:0] VAR22,
input VAR14,
input [1:0] VAR30,
input [2:0] VAR5,
input VAR6,
input VAR20,
output reg VAR13,
output VAR24,
output VAR8,
output reg [31:0] VAR19,
output reg VAR27,
output reg [255:0] VAR31,
output reg [511:0] VAR7,
input... | apache-2.0 |
slongfield/StereoCensus | verilog/census/census.v | 2,493 | module MODULE1#(
parameter VAR12=1,
parameter VAR10=2,
parameter VAR4=2
) (
input wire clk,
input wire rst,
input wire [VAR12*VAR10*VAR4-1:0] VAR11,
output wire [VAR10*VAR4-1:0] VAR3
);
localparam VAR5 = VAR12*VAR10*VAR4;
localparam VAR1 = (VAR10*VAR4-1)/2;
wire [VAR10*VAR4-1:0] VAR9;
wire [VAR12-1:0] word[VAR10*VAR4];... | gpl-3.0 |
rfotino/consolite-hardware | proj/ipcore_dir/s6_lpddr_ram/user_design/rtl/infrastructure.v | 10,479 | module MODULE1 #
(
parameter VAR32 = 2500,
parameter VAR116 = 1,
parameter VAR78 = "VAR114",
parameter VAR61 = 1,
parameter VAR69 = 1,
parameter VAR90 = 16,
parameter VAR7 = 8,
parameter VAR18 = 2,
parameter VAR63 = 1
)
(
input VAR104,
input VAR110,
input VAR1,
input VAR72,
output VAR67,
output VAR50,
output VAR2,
outp... | mit |
eda-globetrotter/MarcheProcessor | processor/reading/myAddSub.v | 2,319 | module MODULE1(VAR20,VAR25,VAR6,VAR28,VAR40,VAR12,VAR7,VAR1);
input [7:0] VAR20;
input [7:0] VAR25;
input VAR6;
input VAR28;
input VAR40;
output [7:0] VAR12;
output VAR7;
output VAR1;
reg[7:0] VAR42;
wire [7:0] VAR12;
wire VAR43,VAR39,VAR13,VAR46,VAR36,VAR17,VAR15;
wire VAR19;
always @(VAR20 or VAR25 or VAR6 or VAR28 o... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/up_gt.v | 25,310 | module MODULE1 (
VAR8,
VAR47,
VAR33,
VAR50,
VAR66,
VAR93,
VAR103,
VAR95,
VAR77,
VAR52,
VAR24,
VAR142,
VAR84,
VAR111,
VAR105,
VAR102,
VAR9,
VAR48,
VAR81,
VAR113,
VAR35,
VAR112,
VAR92,
VAR136,
VAR65,
VAR88,
VAR5,
VAR100,
VAR28,
VAR144,
VAR83,
VAR133,
VAR57,
VAR147,
VAR21,
VAR62,
VAR119,
VAR131,
VAR15,
VAR126,
VAR150,
VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.functional.v | 1,434 | module MODULE1 (
VAR8 ,
VAR5,
VAR2,
VAR7
);
output VAR8 ;
input VAR5;
input VAR2;
input VAR7;
wire VAR9 ;
wire VAR1;
or VAR4 (VAR9 , VAR2, VAR5 );
nand VAR6 (VAR1, VAR7, VAR9 );
buf VAR3 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp.symbol.v | 1,351 | module MODULE1 (
input VAR2 ,
output VAR6 ,
input VAR5,
input VAR1
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b_2.v | 2,173 | module MODULE1 (
VAR3 ,
VAR6 ,
VAR9 ,
VAR8,
VAR7,
VAR2 ,
VAR1
);
output VAR3 ;
input VAR6 ;
input VAR9 ;
input VAR8;
input VAR7;
input VAR2 ;
input VAR1 ;
VAR5 VAR4 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR6 ,
VAR9
);
output VAR3... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/master_0/altera_avalon_sc_fifo/altera_avalon_sc_fifo.v | 32,228 | module MODULE1
parameter VAR48 = 1,
parameter VAR2 = 8,
parameter VAR91 = 16,
parameter VAR44 = 0,
parameter VAR84 = 0,
parameter VAR70 = 0,
parameter VAR96 = 0,
parameter VAR59 = 0,
parameter VAR80 = 0,
parameter VAR78 = 0,
parameter VAR88 = 3,
parameter VAR98 = 1,
parameter VAR37 = VAR48 * VAR2,
parameter VAR23 = VAR... | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cmn/block_ram/dual_port_ram_sync.v | 2,515 | module MODULE1
parameter VAR5 = 6,
parameter VAR7 = 8
)
(
input wire clk,
input wire VAR11,
input wire [VAR5-1:0] VAR4,
input wire [VAR5-1:0] VAR8,
input wire [VAR7-1:0] VAR3,
output wire [VAR7-1:0] VAR2,
output wire [VAR7-1:0] VAR10
);
reg [VAR7-1:0] VAR9 [2**VAR5-1:0];
reg [VAR5-1:0] VAR6;
reg [VAR5-1:0] VAR1;
always... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu9t5v0__dlyb_4.behavioral.v | 1,098 | module MODULE1( VAR4, VAR5 );
input VAR4;
output VAR5;
VAR1 VAR3(.VAR4(VAR4),.VAR5(VAR5));
VAR1 VAR2(.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
ace8957/EECE6017C | proc.v | 8,406 | module MODULE1 (VAR56, VAR55, VAR21, VAR50, VAR47, VAR48, VAR12, VAR60);
input [8:0] VAR56;
input VAR55, VAR21, VAR50;
output reg VAR47, VAR60;
output reg [8:0] VAR48, VAR12;
parameter VAR25 = 3'b000, VAR19 = 3'b001, VAR2 = 3'b010, VAR29 = 3'b011, VAR52 = 3'b100;
parameter VAR15 = 3'b000, VAR13 = 3'b001, VAR4 = 3'b010,... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_2.behavioral.v | 1,802 | module MODULE1( VAR4, VAR5, VAR2, VAR7, VAR3 );
input VAR2, VAR4, VAR7, VAR3;
output VAR5;
VAR1 VAR8(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3));
VAR1 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7),.VAR3(VAR3)); | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/bsv/ResetToBool.v | 1,552 | module MODULE1( VAR3, VAR1);
input VAR3;
output VAR1;
assign VAR1 = (VAR3 == VAR2);
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.pp.blackbox.v | 1,363 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR6 ,
VAR4 ,
VAR3,
VAR7,
VAR2 ,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR6 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
cafe-alpha/wasca | fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter.v | 6,149 | module MODULE1 #(
parameter VAR15 = 18,
parameter VAR14 = 0,
parameter VAR19 = 18,
parameter VAR24 = 0,
parameter VAR17 = 0,
parameter VAR4 = 0,
parameter VAR25 = 1,
parameter VAR20 = 1,
parameter VAR6 = 0,
parameter VAR8 = 18,
parameter VAR9 = 0,
parameter VAR23 = 1,
parameter VAR5 = 0,
parameter VAR1 = 1,
parameter V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a_2.v | 2,321 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR1 ,
VAR4 ,
VAR2 ,
VAR6 ,
VAR7,
VAR9
);
output VAR3 ;
input VAR10 ;
input VAR1 ;
input VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR7;
input VAR9;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODUL... | apache-2.0 |
vadixidav/vga-controller | vga.v | 2,743 | module MODULE1(
clk,
reset,
VAR8,
VAR3,
VAR20,
VAR1,
VAR10
);
parameter VAR12 = 1'b0;
parameter VAR2 = 640;
parameter VAR19 = 16;
parameter VAR7 = 96;
parameter VAR6 = 48;
parameter VAR16 =
VAR2 +
VAR19 +
VAR7 +
VAR6;
parameter VAR21 = 1'b0;
parameter VAR14 = 480;
parameter VAR13 = 10;
parameter VAR9 = 2;
parameter VAR... | mpl-2.0 |
promach/internal_logic_analyzer | rtl/stop.v | 1,034 | module MODULE1 (clk, reset, VAR1, VAR2, VAR6, VAR5);
input clk, reset, VAR1, VAR2;
input [(VAR7-1) : 0] VAR6;
output reg VAR5 = 0;
reg VAR4 = 0;
reg [(VAR7-1) : 0] VAR3 = 0;
always @(posedge clk)
begin
if (reset)
VAR4 <= 1'b0;
end
else if ((VAR2) && (VAR1))
VAR4 <= 1'b1; end
always @(posedge clk)
begin
if (reset)
VAR3 ... | gpl-3.0 |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/hazard_detection.v | 7,181 | module MODULE1(VAR2,VAR42,VAR40,clk,VAR32,VAR6,VAR30,VAR14,VAR29,VAR19,VAR13,VAR31,VAR18,VAR39,VAR43);
parameter VAR10 = 6'b000000;
parameter VAR23 = 6'b001000;
parameter VAR26 = 6'b000010;
parameter VAR12 = 6'b000001;
parameter VAR5 = 4'b0001;
parameter VAR4 = 6'b001010;
parameter VAR22 = 6'b001001;
parameter VAR25 = ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decap/sky130_fd_sc_ls__decap.functional.v | 1,039 | module MODULE1 ();
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | rtl/xgmii_interleave.v | 2,161 | module MODULE1
(
input wire [63:0] VAR3,
input wire [7:0] VAR1,
output wire [72:0] VAR2
);
assign VAR2[7:0] = VAR3[7:0];
assign VAR2[8] = VAR1[0];
assign VAR2[16:9] = VAR3[15:8];
assign VAR2[17] = VAR1[1];
assign VAR2[25:18] = VAR3[23:16];
assign VAR2[26] = VAR1[2];
assign VAR2[34:27] = VAR3[31:24];
assign VAR2[35] = V... | mit |
cr88192/bgbtech_bjx1core | srvcore/ExUop.v | 19,087 | parameter[7:0] VAR66 = 8'h00; parameter[7:0] VAR17 = 8'h01;
parameter[7:0] VAR20 = 8'h02;
parameter[7:0] VAR59 = 8'h03;
parameter[7:0] VAR137 = 8'h04;
parameter[7:0] VAR46 = 8'h05;
parameter[7:0] VAR107 = 8'h06;
parameter[7:0] VAR86 = 8'h07;
parameter[7:0] VAR85 = 8'h08;
parameter[7:0] VAR172 = 8'h09;
parameter[7:0] VA... | mit |
combinatorylogic/soc | backends/c2/hw/blackice/vga640x480ice.v | 4,647 | module MODULE1(input clk, input VAR12,
input rst,
input [15:0] VAR26,
output [17:0] VAR32,
output reg VAR36,
input VAR27,
output VAR34,
output VAR13,
output [2:0] VAR10 );
reg VAR28;
reg VAR23;
wire [15:0] VAR30;
wire VAR37;
wire [15:0] VAR18;
wire VAR38;
reg [17:0] VAR31;
assign VAR32 = VAR31[17:0];
assign VAR30 = VAR... | mit |
zhaishaomin/ring_network-based-multicore- | core/core_if_id.v | 2,354 | module MODULE1( clk,
rst,
VAR15,
VAR10,
VAR1,
VAR13,
VAR6,
VAR16,
VAR4,
VAR12,
VAR14,
VAR2,
VAR17,
VAR3,
VAR8,
VAR11,
VAR7,
VAR9,
VAR5,
VAR18
);
input clk;
input rst;
input [31:0] VAR1;
input [31:0] VAR13;
input [31:0] VAR6;
input [31:0] VAR16;
input [1:0] VAR4;
input [2:0] VAR12;
input [1:0] VAR14;
input VAR2;
input V... | apache-2.0 |
mwswartwout/EECS318 | hw1/problem3/problem3.v | 1,941 | module MODULE1(out, VAR50, VAR23);
output [9:0] out;
input [4:0] VAR50, VAR23;
wire [4:0] VAR62, VAR46, VAR13, VAR52, VAR55;
wire VAR33, VAR59, VAR2, VAR39, VAR26, VAR25, VAR66, VAR48, VAR31, VAR51, VAR12, VAR6, VAR57, VAR67, VAR49, VAR7, VAR74, VAR64, VAR38, VAR15, VAR20, VAR43, VAR56, VAR10, VAR30, VAR11;
wire VAR28,... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_ic_filter.v | 1,168 | module MODULE1(
VAR3,
VAR1,
VAR2 );
output VAR3;
input VAR1;
input VAR2;
assign VAR3 = VAR1 ;
endmodule | gpl-2.0 |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/udp/ethernet_parser_64bit.v | 3,629 | module MODULE1
parameter VAR20=VAR8/8,
parameter VAR6 = 3,
parameter VAR19 = 2
)
( input [VAR8-1:0] VAR7,
input [VAR20-1:0] VAR14,
input VAR16,
output reg [47:0] VAR3,
output reg [47:0] VAR17,
output reg [15:0] VAR13,
output reg VAR10,
output reg [VAR6-1:0] VAR23,
input reset,
input clk
);
parameter VAR21 = 3;
paramete... | lgpl-2.1 |
binderclip/BCOpenMIPS | cpu-code/div.v | 3,404 | module MODULE1 (
input wire clk,
input wire rst,
input wire VAR13,
input wire[VAR23] VAR16, input wire[VAR23] VAR12, input wire VAR6,
input wire VAR22,
output reg[VAR11] VAR14,
output reg VAR26
);
wire[32:0] VAR17;
reg[5:0] VAR9;
reg[VAR11] VAR5;
reg[1:0] state; reg[VAR23] VAR4;
wire[VAR23] VAR3;
wire[VAR23] VAR19;
ass... | mit |
Beck-Sisyphus/EE471 | Lab4/sourceCode/DE1_SoCPhaseII.v | 6,562 | module MODULE1 (VAR49, VAR1, VAR19, VAR11);
input VAR49; output [9:0] VAR1;
input [9:0] VAR19;
input [3:0] VAR11;
reg [2:0] VAR37, VAR29;
wire [15:0] VAR30;
reg [7:0] VAR34; reg VAR33, VAR7;
reg [10:0] VAR28;
reg [15:0] VAR51;
reg [2:0] VAR38;
wire rst, VAR4;
reg [4:0] VAR20, VAR8, VAR43;
reg [31:0] VAR13;
wire [31:0] ... | mit |
trander1/Generic-Cache-Block | Verilog Files/multilevel_cache_top.v | 6,890 | module MODULE1(
VAR3, VAR28,
VAR22, clk
);
parameter VAR39 = 4; parameter VAR34 = 4;
parameter VAR4 = 1; parameter VAR19 = 16;
parameter VAR35 = 2;
parameter VAR16 = VAR39+VAR34+VAR35;
parameter VAR37 = VAR8(VAR4); parameter VAR27 = VAR8(VAR19); output reg [VAR34-1:0]VAR3;output reg VAR28; input [VAR16-1:0]VAR22; input... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/ram16_2port.v | 1,205 | module MODULE1 (input VAR3, input write,
input [3:0] VAR6, input [15:0] VAR4,
input [3:0] VAR5, output reg [15:0] VAR1,
input [3:0] VAR2, output reg [15:0] VAR7);
reg [15:0] VAR8 [0:31];
always @(posedge VAR3)
VAR1 <= VAR8[VAR5];
always @(posedge VAR3)
VAR7 <= VAR8[VAR2];
always @(posedge VAR3)
if(write)
VAR8[VAR6] <= ... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/shd_fifo/shd_fifo_stub.v | 1,365 | module MODULE1(rst, VAR5, VAR3, din, VAR6, VAR1, dout, VAR4, VAR2)
;
input rst;
input VAR5;
input VAR3;
input [255:0]din;
input VAR6;
input VAR1;
output [255:0]dout;
output VAR4;
output VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp.functional.pp.v | 1,840 | module MODULE1 (
VAR4,
VAR3,
VAR16 ,
VAR9,
VAR6,
VAR11 ,
VAR14
);
output VAR4;
input VAR3;
input VAR16 ;
input VAR9;
input VAR6;
input VAR11 ;
input VAR14 ;
wire VAR10 ;
wire VAR2 ;
wire VAR13 ;
wire VAR5;
not VAR8 (VAR2 , VAR16 );
VAR12 VAR15 VAR7 (VAR10 , VAR3, VAR2, , VAR9, VAR6);
and VAR1 (VAR4 , VAR10, VAR16 );
en... | apache-2.0 |
Seeed-Studio/DSOQuad_SourceCode | FPGA_V2.5/Signal.v | 8,476 | module MODULE1( VAR31, VAR34, VAR9, VAR39, VAR49, VAR7,
VAR38, VAR23,
VAR45, VAR4, VAR26,
VAR28, VAR42, VAR24, VAR27, VAR30, VAR18,
VAR22, VAR2, VAR10, VAR47, VAR17, VAR29, );
input VAR31; input VAR34; input [ 7:0]VAR9; input [ 7:0]VAR39; input [15:0]VAR49; input [17:0]VAR7; input VAR38;
input [ 7:0]VAR23;
output VAR45... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/invlp/sky130_fd_sc_lp__invlp.behavioral.v | 1,341 | module MODULE1 (
VAR9,
VAR3
);
output VAR9;
input VAR3;
supply1 VAR8;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR2 ;
wire VAR5;
not VAR1 (VAR5, VAR3 );
buf VAR7 (VAR9 , VAR5 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_gpio_sysfs/zybo_petalinux_1.srcs/sources_1/bd/block_design/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_nto1_mux.v | 4,820 | module MODULE1 #
(
parameter integer VAR6 = 1, parameter integer VAR12 = 1, parameter integer VAR8 = 1, parameter integer VAR14 = 0 )
(
input wire [VAR6-1:0] VAR5, input wire [VAR12-1:0] VAR2, input wire [VAR6*VAR8-1:0] VAR1, output wire [VAR8-1:0] VAR4 );
wire [VAR8*VAR6-1:0] VAR9;
genvar VAR3;
generate
if (VAR14 == 0... | gpl-3.0 |
MiddleMan5/233 | Experiments/Experiment7-Its_Alive/IPI-BD/RAT/ip/RAT_slice_1_0_0/RAT_slice_1_0_0_stub.v | 1,218 | module MODULE1(VAR1, VAR2)
;
input [17:0]VAR1;
output [7:0]VAR2;
endmodule | mit |
thucoldwind/ucore_mips | CPU32/thinpad_top/thinpad_top.srcs/sources_1/new/vga.v | 1,403 | module MODULE1
(
input clk,
output wire VAR1,
output wire VAR6,
output reg [VAR3 - 1:0] VAR4,
output reg [VAR3 - 1:0] VAR2,
output wire VAR5
);
begin
end
begin
begin
end | unlicense |
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