repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_2.behavioral.v | 1,116 | module MODULE1( VAR3, VAR2 );
input VAR3;
output VAR2;
VAR5 VAR4(.VAR3(VAR3),.VAR2(VAR2));
VAR5 VAR1(.VAR3(VAR3),.VAR2(VAR2)); | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_nios2_gen2_0_cpu_debug_slave_tck.v | 8,323 | module MODULE1 (
VAR13,
VAR7,
VAR10,
VAR6,
VAR34,
VAR8,
VAR21,
VAR5,
VAR25,
VAR33,
VAR12,
VAR38,
VAR28,
VAR37,
VAR15,
VAR18,
VAR40,
VAR9,
VAR32,
VAR31,
VAR4,
VAR27,
VAR14,
VAR35,
VAR23,
VAR3,
VAR30,
VAR20,
VAR17,
VAR26,
VAR16
)
;
output [ 1: 0] VAR30;
output VAR20;
output [ 37: 0] VAR17;
output VAR26;
output VAR16;
inp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21o/sky130_fd_sc_lp__a21o.behavioral.v | 1,502 | module MODULE1 (
VAR12 ,
VAR8,
VAR2,
VAR6
);
output VAR12 ;
input VAR8;
input VAR2;
input VAR6;
supply1 VAR7;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR4 ;
wire VAR10 ;
wire VAR3;
and VAR1 (VAR10 , VAR8, VAR2 );
or VAR13 (VAR3, VAR10, VAR6 );
buf VAR5 (VAR12 , VAR3 );
endmodule | apache-2.0 |
gajjanag/6111_Project | src/perspective_params.v | 8,949 | module MODULE1(input clk,
input[9:0] VAR46,
input[8:0] VAR27,
input[9:0] VAR5,
input[8:0] VAR75,
input[9:0] VAR30,
input[8:0] VAR43,
input[9:0] VAR44,
input[8:0] VAR52,
output reg signed[67:0] VAR69,
output reg signed[68:0] VAR64,
output reg signed[78:0] VAR38,
output reg signed[67:0] VAR45,
output reg signed[68:0] VAR... | gpl-3.0 |
KorotkiyEugene/LAG_sv_syn_quartus | unary_select_pair.v | 1,720 | module MODULE1 (VAR7, VAR3, VAR8, VAR9);
parameter VAR11 = 0; parameter VAR10 = 4;
parameter VAR12 = 4;
input [VAR10-1:0] VAR7;
input [VAR12-1:0] VAR3;
input [VAR10*VAR12-1:0] VAR8;
output VAR9;
genvar VAR1,VAR13;
wire [VAR10*VAR12-1:0] VAR5;
generate
for (VAR1=0; VAR1<VAR10; VAR1=VAR1+1) begin:VAR2
for (VAR13=0; VAR13... | gpl-2.0 |
ShepardSiegel/ocpi | coregen/temac_v6/example_design/client/fifo/eth_fifo_8.v | 8,181 | module MODULE1 (
VAR20, VAR29, VAR17, VAR14, VAR40, VAR21, VAR46, VAR11, VAR42,
VAR41, VAR5, VAR6, VAR13, VAR43, VAR44, VAR51, VAR45, VAR15,
VAR26, VAR24, VAR37, VAR38, VAR52, VAR18, VAR32, VAR56,
VAR31, VAR27, VAR54, VAR2, VAR55, VAR19, VAR10, VAR12 );
parameter VAR16 = 0;
input VAR20;
input VAR29;
input VAR17;
output... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.functional.pp.v | 2,163 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR16 ,
VAR7 ,
VAR13 ,
VAR20,
VAR3 ,
VAR8 ,
VAR15 ,
VAR11
);
output VAR5 ;
input VAR2 ;
input VAR16 ;
input VAR7 ;
input VAR13 ;
input VAR20;
input VAR3 ;
input VAR8 ;
input VAR15 ;
input VAR11 ;
wire VAR10 ;
wire VAR4 ;
wire VAR12;
not VAR9 (VAR4 , VAR20 );
VAR19 VAR18 (VAR12, VAR16, VAR... | apache-2.0 |
cambridgehackers/connectal | verilog/CONNECTNET.v | 1,214 | module MODULE1(VAR1, VAR2);
output VAR2;
input VAR1;
assign VAR2 = VAR1;
endmodule | mit |
minosys-jp/FPGA | Zybo/fillbox/HDL/fillbox_v1_0.v | 7,198 | module MODULE1 #
(
parameter VAR37 = 32'h10000000,
parameter integer VAR108 = 16,
parameter integer VAR105 = 1,
parameter integer VAR148 = 32,
parameter integer VAR68 = 32,
parameter integer VAR157 = 0,
parameter integer VAR46 = 0,
parameter integer VAR11 = 0,
parameter integer VAR129 = 0,
parameter integer VAR33 = 0,
... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nand4/sky130_fd_sc_hd__nand4.symbol.v | 1,294 | module MODULE1 (
input VAR9,
input VAR6,
input VAR4,
input VAR7,
output VAR8
);
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and3b/sky130_fd_sc_ms__and3b_1.v | 2,218 | module MODULE2 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR10 ,
VAR7,
VAR4,
VAR6 ,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR7;
input VAR4;
input VAR6 ;
input VAR8 ;
VAR9 VAR1 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_028.v | 1,522 | module MODULE1 (
VAR10,
VAR2
);
input [31:0] VAR10;
output [31:0]
VAR2;
wire [31:0]
VAR11,
VAR13,
VAR6,
VAR7,
VAR3,
VAR14,
VAR1,
VAR5,
VAR12;
assign VAR11 = VAR10;
assign VAR14 = VAR6 << 3;
assign VAR13 = VAR11 << 7;
assign VAR6 = VAR11 + VAR13;
assign VAR12 = VAR1 - VAR5;
assign VAR1 = VAR3 - VAR14;
assign VAR5 = VAR1... | mit |
benreynwar/fpga-sdrlib | verilog/fft/mstore.v | 1,791 | module MODULE1
parameter VAR13 = 0,
parameter VAR14 = 1
)
(
input wire clk,
input wire VAR7,
input wire VAR8,
input wire [VAR14-1:0] VAR6,
input wire VAR1,
output wire [VAR14-1:0] VAR12,
output reg VAR5
);
function integer VAR2;
input integer VAR3;
begin
VAR3 = VAR3-1;
for (VAR2=0; VAR3>0; VAR2=VAR2+1)
VAR3 = VAR3>>1;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fill/sky130_fd_sc_hs__fill.pp.blackbox.v | 1,173 | module MODULE1 (
VAR4,
VAR2,
VAR3 ,
VAR1
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_banked.v | 3,927 | module MODULE1
, parameter VAR29(VAR42)
, parameter VAR14=0
, parameter VAR34=1
, parameter VAR26=1
, parameter VAR32=VAR18(VAR42)
, parameter VAR17=(VAR42/VAR26)
, parameter VAR11=VAR18(VAR17)
, parameter VAR3=VAR18(VAR26)
, parameter VAR23=(VAR5/VAR34)
)
(
input VAR28
, input VAR25
, input VAR1
, input VAR27
, input ... | bsd-3-clause |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_LOALPL6_syn.v | 5,599 | module MODULE1 ( VAR213, VAR67, VAR163, VAR188 );
input [15:0] VAR67;
input [15:0] VAR163;
output [16:0] VAR188;
input VAR213;
wire VAR132, VAR183, VAR93, VAR135, VAR16, VAR107, VAR157, VAR91, VAR160, VAR75, VAR126, VAR103, VAR224, VAR48,
VAR175, VAR85, VAR35, VAR196, VAR202, VAR5, VAR146, VAR59, VAR179, VAR168, VAR30,... | apache-2.0 |
kulp/tenyr | hw/verilog/gpio.v | 1,197 | module MODULE1(clk, VAR6, VAR13, reset, addr, VAR12, VAR4, VAR15);
parameter VAR1 = 32;
localparam VAR3 = 4;
input wire clk, VAR6, VAR13, reset;
input wire[31:0] addr, VAR12;
output reg [31:0] VAR4;
inout wire[VAR1-1:0] VAR15;
localparam VAR10 = 0, VAR8 = 1, VAR14 = 2, VAR11 = 3;
reg [VAR1-1:0] state[VAR3-1:0];
integer... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.symbol.v | 1,257 | module MODULE1 (
input VAR1,
input VAR2,
output VAR3 ,
input VAR4
);
endmodule | apache-2.0 |
bluespec/Flute | builds/RV32ACDFIMSU_Flute_iverilog/Verilog_RTL/mkNear_Mem.v | 64,052 | module MODULE1(VAR157,
VAR395,
VAR223,
VAR190,
VAR212,
VAR457,
VAR412,
VAR267,
VAR465,
VAR300,
VAR44,
VAR265,
VAR195,
VAR106,
VAR419,
VAR270,
VAR128,
VAR126,
VAR407,
VAR227,
VAR197,
VAR160,
VAR320,
VAR369,
VAR149,
VAR48,
VAR191,
VAR359,
VAR268,
VAR427,
VAR175,
VAR453,
VAR461,
VAR168,
VAR353,
VAR185,
VAR34,
VAR383,
VAR1... | apache-2.0 |
MegaShow/college-programming | Homework/Computer Organization and Interfacing/Single Cycle CPU/Single Cycle CPU.srcs/sources_1/new/CPU.v | 3,907 | module MODULE1(
input clk,
input reset,
output wire [31:0] VAR73,
output wire [31:0] VAR76,
output wire [31:0] VAR69,
output wire [31:0] VAR38,
output wire [31:0] VAR82,
output wire [31:0] VAR20,
output wire [31:0] VAR43,
output wire [31:0] VAR80
);
reg VAR15;
wire [31:0] VAR35;
wire [31:0] VAR1, VAR31;
wire [31:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4b/sky130_fd_sc_hd__or4b.behavioral.v | 1,498 | module MODULE1 (
VAR12 ,
VAR10 ,
VAR9 ,
VAR11 ,
VAR2
);
output VAR12 ;
input VAR10 ;
input VAR9 ;
input VAR11 ;
input VAR2;
supply1 VAR1;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR8 ;
wire VAR14;
not VAR13 (VAR8 , VAR2 );
or VAR6 (VAR14, VAR8, VAR11, VAR9, VAR10);
buf VAR7 (VAR12 , VAR14 );
endmodule | apache-2.0 |
ssabogal/nocturnal | noc_dev/noc_dev.ip_user_files/ipstatic/axis_infrastructure_v1_1_0/hdl/verilog/axis_infrastructure_v1_1_clock_synchronizer.v | 4,083 | module MODULE1 # (
parameter integer VAR8 = 4
)
(
input wire clk,
input wire VAR10 ,
output wire VAR12
);
VAR2 #(
.VAR3 ( VAR8 ) ,
.VAR7 ( 0 ) ,
.VAR6 ( 0 )
)
VAR1 (
.VAR9 ( 1'b0 ) ,
.VAR4 ( VAR10 ) ,
.VAR5 ( VAR12 ) ,
.VAR11 ( clk )
);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.functional.pp.v | 1,828 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR12 ,
VAR7 ,
VAR5 ,
VAR15,
VAR13,
VAR11 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR12 ;
input VAR7 ;
input VAR5 ;
input VAR15;
input VAR13;
input VAR11 ;
input VAR3 ;
wire VAR8 ;
wire VAR10;
or VAR6 (VAR8 , VAR5, VAR7, VAR12, VAR2 );
VAR9 VAR14 (VAR10, VAR8, VAR15, VAR13);
buf VAR4 (... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_2.behavioral.pp.v | 1,254 | module MODULE1( VAR3, VAR2, VAR1, VAR4, VAR6 );
input VAR1, VAR3;
inout VAR4, VAR6;
output VAR2;
VAR7 VAR8(.VAR3(VAR3),.VAR2(VAR2),.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6));
VAR7 VAR5(.VAR3(VAR3),.VAR2(VAR2),.VAR1(VAR1),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
juan199/Lab_Digitales | exp1/Prueba_SUB.v | 1,234 | module MODULE1
(
input wire[15:0] VAR6,
output reg [27:0] VAR10
);
always @ ( VAR6 )
begin
case (VAR6)
0: VAR10 = { VAR11 ,24'd4009 };
1: VAR10 = { VAR3 , VAR14,16'b0001 };
2: VAR10 = { VAR3 ,VAR13,16'h1 };
3: VAR10 = { VAR3, VAR9,16'd1}; 4: VAR10 = { VAR3, VAR15,16'd0 };
5: VAR10 = { VAR12 ,8'b0,VAR14,8'b0 }; 6: VAR10... | lgpl-3.0 |
Elphel/x353 | control/rtc353.v | 11,536 | module MODULE2 (VAR10, VAR40, VAR45, VAR41, VAR29, VAR65, VAR31, VAR61, VAR9, VAR14, VAR68, VAR5, VAR2); input VAR10;
input VAR40;
input [ 1:0] VAR45;
input [15:0] VAR41;
output [19:0] VAR29;
output [31:0] VAR65;
input VAR31;
input VAR61;
input VAR9;
output [19:0] VAR14;
output [31:0] VAR68;
output [19:0] VAR5;
output ... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_mbist.v | 25,093 | module MODULE1(
VAR18,
VAR108,
VAR52,
VAR9,
VAR37,
VAR45,
VAR77,
VAR145,
VAR124,
VAR146,
VAR11,
VAR70,
VAR16,
VAR23,
VAR28,
VAR78,
VAR90,
VAR133,
VAR58,
VAR150,
VAR125,
VAR66,
VAR97,
VAR12,
VAR39,
VAR83,
VAR29,
VAR128,
VAR103,
VAR106,
VAR54
);
output VAR18;
output VAR108;
output VAR52;
output[6:0] VAR9;
output[1:0] VAR... | gpl-2.0 |
bluespec/Flute | src_bsc_lib_RTL/BRAM2BE.v | 6,821 | module MODULE1(VAR23,
VAR16,
VAR20,
VAR4,
VAR8,
VAR2,
VAR6,
VAR7,
VAR18,
VAR12,
VAR10,
VAR15
);
parameter VAR21 = 0;
parameter VAR14 = 1;
parameter VAR5 = 1;
parameter VAR3 = 1;
parameter VAR11 = 1;
parameter VAR13 = 1;
input VAR23;
input VAR16;
input [VAR11-1:0] VAR20;
input [VAR14-1:0] VAR4;
input [VAR5-1:0] VAR8;
ou... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_sync.v | 27,176 | module MODULE1 #
(
parameter VAR105 = "VAR100", parameter VAR31 = "VAR9", parameter VAR58 = "VAR19", parameter VAR57 = 0, parameter VAR71 = 0, parameter VAR69 = 1, parameter VAR73 = 3, parameter VAR66 = 0, parameter VAR39 = 0
)
(
input VAR94,
input VAR74,
input VAR25,
input VAR87,
input VAR20,
input VAR42,
input VAR11,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.functional.v | 1,254 | module MODULE1 (
VAR1,
VAR3,
VAR6
);
output VAR1;
input VAR3;
input VAR6;
wire VAR5;
and VAR4 (VAR5, VAR3, VAR6 );
buf VAR2 (VAR1 , VAR5 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/async_fifo.v | 16,994 | module MODULE1 #(
parameter VAR6 = "7SERIES", VAR4 = 144, VAR13 = 12, VAR33 = "VAR10",
VAR71 = 9'd32,
VAR65 = 9'd121,
VAR25 = "VAR10", VAR27 = "VAR88", VAR22 = "VAR19")
( input [VAR4-1:0] din,
input VAR36,
input VAR44,
input rst,
input VAR23,
input VAR35,
output [VAR4-1:0] dout,
output VAR40,
output VAR24,
output reg V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_io | cells/top_xres4v2/sky130_fd_io__top_xres4v2.behavioral.v | 7,606 | module MODULE1 ( VAR23, VAR13, VAR36, VAR7,
VAR5, VAR21, VAR42, VAR1, VAR8, VAR32, VAR41, VAR16,
VAR35, VAR2, VAR9
);
wire VAR4;
output VAR13;
inout VAR5;
inout VAR21;
inout VAR42;
input VAR35;
input VAR8;
input VAR32;
input VAR41;
input VAR16;
inout VAR2;
input VAR9;
supply1 VAR37;
supply1 VAR19;
supply1 VAR12;
supply... | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_ic_fsm.v | 9,689 | module MODULE1(
clk, rst,
VAR13, VAR9, VAR4,
VAR11, VAR8, VAR2, VAR17, VAR20,
VAR24, VAR5, VAR10, VAR21, VAR22,
VAR3, VAR19
);
input clk;
input rst;
input VAR13;
input VAR9;
input VAR4;
input VAR11;
input VAR8;
input VAR2;
input [31:0] VAR17;
output [31:0] VAR20;
output [3:0] VAR24;
output VAR5;
output VAR10;
output VA... | gpl-3.0 |
kactus2/ipxactexamplelib | tut.fi/communication.bridge/wb_slave_spi_master/1.0/wb_slave_spi_master.v | 9,387 | module MODULE1 #(
parameter VAR16 = 16, parameter VAR33 = 16, parameter VAR30 = 32, parameter VAR34 = 'h0F00, parameter VAR32 = VAR27(VAR16), parameter VAR2 = 1, parameter VAR20 = 1 ) (
input VAR7,
output VAR17,
output reg VAR5,
output reg VAR40,
input [VAR33-1:0] VAR38, input VAR14, input [VAR30-1:0] VAR13, input VAR2... | mit |
ShepardSiegel/ocpi | rtl/mkTLPServerNode.v | 5,179 | module MODULE1(VAR39,
VAR38,
VAR10,
VAR3,
VAR4,
VAR52,
VAR41,
VAR12,
VAR49,
VAR29,
VAR19,
VAR26,
VAR25,
VAR31,
VAR35);
input [13 : 0] VAR39;
input VAR38;
input VAR10;
input VAR3;
output [152 : 0] VAR4;
output VAR52;
input [152 : 0] VAR41;
input VAR12;
output VAR49;
input [152 : 0] VAR29;
input VAR19;
output VAR26;
inpu... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfbbp/sky130_fd_sc_hs__dfbbp.pp.blackbox.v | 1,400 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR7 ,
VAR8,
VAR3 ,
VAR1
);
output VAR2 ;
output VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR7 ;
input VAR8;
input VAR3 ;
input VAR1 ;
endmodule | apache-2.0 |
binderclip/BCOpenMIPS | cpu-code/cp0_reg.v | 5,955 | module MODULE1 (
input wire clk,
input wire rst,
input wire[VAR19] VAR9,
input wire[VAR3] VAR24,
input wire[VAR19] VAR34,
input wire VAR14,
input wire[5:0] VAR7,
input wire[VAR3] VAR1,
input wire[VAR3] VAR32,
input wire VAR12,
input wire VAR23,
input wire[VAR3] VAR17,
input wire VAR25,
input wire VAR36,
input wire[VAR3... | mit |
alexforencich/verilog-axis | rtl/priority_encoder.v | 3,253 | module MODULE1 #
(
parameter VAR5 = 4,
parameter VAR13 = 0
)
(
input wire [VAR5-1:0] VAR7,
output wire VAR12,
output wire [VAR8(VAR5)-1:0] VAR9,
output wire [VAR5-1:0] VAR15
);
parameter VAR2 = VAR5 > 2 ? VAR8(VAR5) : 1;
parameter VAR10 = 2**VAR2;
wire [VAR10-1:0] VAR11 = {{VAR10-VAR5{1'b0}}, VAR7};
wire [VAR10/2-1:0] ... | mit |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_timer_0.v | 6,733 | module MODULE1 (
address,
VAR29,
clk,
VAR14,
VAR19,
VAR20,
irq,
VAR5
)
;
output irq;
output [ 15: 0] VAR5;
input [ 2: 0] address;
input VAR29;
input clk;
input VAR14;
input VAR19;
input [ 15: 0] VAR20;
wire VAR30;
wire VAR26;
wire VAR31;
reg [ 3: 0] VAR21;
wire VAR32;
reg VAR25;
wire VAR24;
wire [ 31: 0] VAR18;
reg [ 3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50.functional.pp.v | 1,866 | module MODULE1 (
VAR1 ,
VAR9 ,
VAR8,
VAR3,
VAR5 ,
VAR7
);
output VAR1 ;
input VAR9 ;
input VAR8;
input VAR3;
input VAR5 ;
input VAR7 ;
wire VAR6 ;
wire VAR12;
buf VAR11 (VAR6 , VAR9 );
VAR4 VAR2 (VAR12, VAR6, VAR8, VAR3);
buf VAR10 (VAR1 , VAR12 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_rndrob.v | 2,864 | module MODULE1(
VAR2,
clk, reset, VAR5, VAR11, VAR7
);
input clk, reset, VAR5;
input [3:0] VAR11;
input VAR7;
output [3:0] VAR2;
wire [3:0] VAR8,
VAR3,
VAR12;
assign VAR3 = VAR7 ? VAR2 : VAR12;
VAR9 VAR4(.din (VAR3[3:0]),
.clk (clk),
.VAR6 (VAR8[3:0]),
.rst (reset),
.VAR5 (VAR5), .VAR10(), .VAR1());
assign VAR12 = VAR8... | gpl-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/whr_op_ctrl_mac.v | 9,613 | module MODULE1
(clk, reset, VAR50, VAR1, VAR43, VAR19,
VAR83, VAR14, VAR54, VAR42, VAR77);
parameter VAR46 = 8;
parameter VAR4 = 4;
parameter VAR6 = 5;
parameter VAR44 = VAR84;
parameter VAR23 = VAR66;
parameter VAR82 = 1;
localparam VAR80
= (VAR23 == VAR66) ? 1 :
-1;
parameter VAR9 = VAR53;
localparam VAR71
= VAR82 &&... | gpl-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_auto_us_1/synth/design_1_auto_us_1.v | 10,500 | module MODULE1 (
VAR53,
VAR65,
VAR24,
VAR89,
VAR51,
VAR48,
VAR66,
VAR26,
VAR5,
VAR13,
VAR77,
VAR9,
VAR88,
VAR43,
VAR28,
VAR19,
VAR2,
VAR25,
VAR50,
VAR20,
VAR49,
VAR79,
VAR34,
VAR39,
VAR36,
VAR93,
VAR17,
VAR58,
VAR27,
VAR73,
VAR68,
VAR102,
VAR80,
VAR21,
VAR31,
VAR69,
VAR57,
VAR52,
VAR40,
VAR85
);
input wire VAR53;
input... | gpl-3.0 |
plindstroem/oh | memory/hdl/fifo_sync.v | 2,915 | module MODULE1
parameter VAR12 = 5,
parameter VAR13 = 16
)
(
input clk,
input reset,
input [VAR13-1:0] VAR5,
input VAR6,
input VAR11,
output wire [VAR13-1:0] VAR8,
output reg VAR14,
output reg VAR2
);
reg [VAR12-1:0] VAR7;
reg [VAR12-1:0] VAR4;
reg [VAR12-1:0] VAR3;
always @ ( posedge clk or posedge reset ) begin
if( r... | gpl-3.0 |
manasks/ece_510_pre_si_val | Lab2/alu_datapath.v | 3,089 | module MODULE1(clk, VAR44, VAR35, VAR34, VAR19, VAR51, VAR30, VAR25, VAR20);
input clk;
input VAR44;
input VAR35;
input VAR34;
input VAR19;
input VAR51;
output VAR30;
output VAR25;
output VAR20;
reg VAR20;
logic clk;
logic [VAR40-1:0] VAR44;
VAR7 VAR35;
logic VAR34;
logic VAR19;
logic VAR51;
logic VAR30;
logic VAR36;
l... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb.functional.v | 1,886 | module MODULE1 (
VAR1,
VAR3,
VAR4 ,
VAR15 ,
VAR13 ,
VAR8 ,
VAR9
);
input VAR1;
input VAR3;
output VAR4 ;
input VAR15 ;
input VAR13 ;
input VAR8 ;
input VAR9 ;
wire VAR9 VAR11 ;
wire VAR7 ;
wire VAR5;
nor VAR12 (VAR11 , VAR15, VAR13 );
and VAR10 (VAR7 , VAR11, VAR8, VAR9 );
VAR6 VAR2 (VAR5, VAR7, VAR1, VAR3);
buf VAR14 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.behavioral.pp.v | 2,164 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR1 ,
VAR17 ,
VAR13 ,
VAR16,
VAR9,
VAR5 ,
VAR3
);
output VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR17 ;
input VAR13 ;
input VAR16;
input VAR9;
input VAR5 ;
input VAR3 ;
wire VAR10 ;
wire VAR11 ;
wire VAR2 ;
wire VAR19;
nand VAR15 (VAR10 , VAR1, VAR7 );
nand VAR14 (VAR11 , VAR13, VAR17 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.behavioral.pp.v | 2,006 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR7 ,
VAR4 ,
VAR12,
VAR13,
VAR1 ,
VAR2
);
output VAR9 ;
input VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR12;
input VAR13;
input VAR1 ;
input VAR2 ;
wire VAR10 ;
wire VAR15 ;
wire VAR11;
and VAR14 (VAR10 , VAR3, VAR7 );
nor VAR6 (VAR15 , VAR4, VAR10 );
VAR8 VAR16 (VAR11, VAR15, VAR12, VAR1... | apache-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu.v | 25,353 | module MODULE1 (
VAR126,
VAR193,
VAR115,
VAR89,
VAR10,
VAR6,
VAR5,
VAR33,
VAR2,
VAR40,
VAR132,
VAR48,
VAR46,
VAR1,
VAR213,
VAR55
);
input VAR126; input [123:0] VAR193; input VAR115; input VAR89; input VAR10; input VAR6;
output [7:0] VAR5; output [144:0] VAR33;
input VAR2;
input VAR40;
input VAR132;
input VAR48;
input V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2b/sky130_fd_sc_lp__nor2b_lp.v | 2,181 | module MODULE2 (
VAR5 ,
VAR8 ,
VAR2 ,
VAR7,
VAR6,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR8 ;
input VAR2 ;
input VAR7;
input VAR6;
input VAR1 ;
input VAR3 ;
VAR9 VAR4 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR5 ,
VAR8 ,
VAR2
);
output VAR5... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/terasic/src/EXT_PLL_CTRL.v | 6,808 | module MODULE1
(
VAR18,
VAR14,
VAR5,
VAR21,
VAR8,
VAR11,
VAR16,
VAR20,
VAR25, VAR29, VAR6, VAR12,
VAR28
);
input VAR18;
input VAR14;
input [3:0] VAR5;
output [3:0] VAR21;
input [3:0] VAR8;
output [3:0] VAR11;
input [3:0] VAR16;
output [3:0] VAR20;
input VAR25;
input VAR29;
output VAR6;
output VAR12;
inout VAR28;
reg [2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.v | 2,163 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR4,
VAR6,
VAR8 ,
VAR2
);
output VAR3 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR8 ;
input VAR2 ;
VAR7 VAR1 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
supply1 VAR4;
supply0 VAR6;... | apache-2.0 |
leopard1/Digit-Recognize-FPGA | src/plugin/PLL_bb.v | 11,313 | module MODULE1 (
VAR2,
VAR4,
VAR1,
VAR3);
input VAR2;
input VAR4;
output VAR1;
output VAR3;
tri0 VAR2;
endmodule | mit |
rkrajnc/minimig-mist | rtl/soc/minimig_mist_top.v | 20,232 | module MODULE1 (
input wire [ 2-1:0] VAR120, input wire [ 2-1:0] VAR151, input wire [ 2-1:0] VAR8, output wire VAR24, output wire VAR112, input wire VAR207, output wire VAR164, output wire VAR67, output wire [ 6-1:0] VAR237, output wire [ 6-1:0] VAR213, output wire [ 6-1:0] VAR13, inout wire [ 16-1:0] VAR15, output wir... | gpl-3.0 |
zhaishaomin/ring_network-based-multicore- | communication_assist/arbiter_for_OUT_rep.v | 3,756 | module MODULE1( clk,
rst,
VAR5,
VAR9,
VAR1,
VAR4,
VAR7,
VAR3,
VAR13,
VAR15,
VAR8,
VAR14,
select );
input clk;
input rst;
input VAR5;
input VAR9;
input VAR1;
input [15:0] VAR4;
input [15:0] VAR7;
input [1:0] VAR3;
input [1:0] VAR13;
output VAR15;
output VAR8;
output VAR14;
output [1:0] select; parameter VAR6=3'b001;
par... | apache-2.0 |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/RAM40x7bits.v | 1,413 | module MODULE1(VAR15, VAR10, VAR16, VAR13, VAR1, VAR8);
input [5:0] VAR15;
input [6:0] VAR10;
input VAR13;
input VAR16, VAR1;
output [6:0] VAR8;
reg [6:0] VAR5 [39:0];
always@(posedge VAR16 or posedge VAR13)
if (VAR13 == 1) begin VAR5[0] <= "VAR23"; VAR5[1] <= "VAR20";
VAR5[2] <= "VAR23";
VAR5[3] <= "3";
VAR5[4] <= "3"... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_1c_2p_v1_00_a/hdl/verilog/cf_dds_top.v | 9,089 | module MODULE1 (
VAR7,
VAR39,
VAR56,
VAR11,
VAR18,
VAR24,
VAR37,
VAR43,
VAR51,
VAR41,
VAR62,
VAR16,
VAR5,
VAR52,
VAR21,
VAR26,
VAR8,
VAR54,
VAR22,
VAR33, VAR36, VAR47, VAR15, VAR30, VAR17,
VAR9,
VAR48,
VAR49,
VAR27);
input VAR7;
input VAR39;
input [63:0] VAR56;
output VAR11;
output VAR18;
output VAR24;
input VAR37;
out... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_rank_cntrl.v | 22,688 | module MODULE1 #
(
parameter VAR14 = 100, parameter VAR90 = "8", parameter VAR76 = 2, parameter VAR22 = 5, parameter VAR65 = 5, parameter VAR29 = 0, parameter VAR62 = 4, parameter VAR9 = 2, parameter VAR100 = 30, parameter VAR87 = 8, parameter VAR24 = 4, parameter VAR41 = 4, parameter VAR20 = 20, parameter VAR50 = 16, ... | mit |
SI-RISCV/e200_opensource | rtl/e203/perips/sirv_qspi_physical_1.v | 19,612 | module MODULE1(
input VAR104,
input reset,
output VAR92,
input VAR208,
output VAR252,
output VAR30,
input VAR106,
output VAR6,
output VAR167,
input VAR95,
output VAR212,
output VAR32,
input VAR176,
output VAR33,
output VAR38,
output VAR240,
output VAR132,
output VAR157,
output VAR12,
input [11:0] VAR188,
input VAR180,
... | apache-2.0 |
BoolLi/Pollard-s-p-1-algorithm | factorFinder.v | 1,191 | module MODULE1(
input [0:31] VAR2,
input clk,
output reg [0:15] VAR9,
output reg [0:15] VAR7,
output reg VAR5
);
reg [0:15] VAR3;
reg reset;
reg VAR1;
reg VAR11;
VAR12 VAR10 (
.VAR8(VAR2),
.VAR4(VAR9),
.clk(clk),
.reset(reset),
.VAR6(VAR7),
.VAR11(VAR11),
.VAR5(VAR5)
); | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai.pp.blackbox.v | 1,408 | module MODULE1 (
VAR5 ,
VAR1,
VAR2,
VAR9 ,
VAR3 ,
VAR8,
VAR6,
VAR7 ,
VAR4
);
output VAR5 ;
input VAR1;
input VAR2;
input VAR9 ;
input VAR3 ;
input VAR8;
input VAR6;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
petrmikheev/miksys | verilog/RAM4096x64_2RW_bb.v | 9,052 | module MODULE1 (
VAR5,
VAR6,
VAR4,
VAR7,
VAR8,
VAR1,
VAR2,
VAR10,
VAR11,
VAR9,
VAR3);
input [11:0] VAR5;
input [11:0] VAR6;
input [7:0] VAR4;
input [7:0] VAR7;
input VAR8;
input [63:0] VAR1;
input [63:0] VAR2;
input VAR10;
input VAR11;
output [63:0] VAR9;
output [63:0] VAR3;
tri1 [7:0] VAR4;
tri1 [7:0] VAR7;
tri1 VAR8;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sedfxtp/sky130_fd_sc_hs__sedfxtp.pp.blackbox.v | 1,367 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR3 ,
VAR1 ,
VAR6 ,
VAR8 ,
VAR2,
VAR4
);
output VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
input VAR2;
input VAR4;
endmodule | apache-2.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_emif_hps/synth/ghrd_10as066n2_emif_hps.v | 4,147 | module MODULE1 (
input wire VAR11, input wire [4095:0] VAR9, output wire [4095:0] VAR25, input wire [1:0] VAR18, output wire [0:0] VAR17, output wire [0:0] VAR5, output wire [0:0] VAR21, output wire [16:0] VAR7, output wire [0:0] VAR3, output wire [1:0] VAR14, output wire [0:0] VAR24, output wire [0:0] VAR16, output wi... | mit |
kactus2/ipxactexamplelib | tut.fi/communication.bus/wishbone/1.0/wishbone_bus.v | 5,966 | module MODULE1 #(
parameter VAR23 = 32,
parameter VAR44 = 32,
parameter VAR14 = 'h0100,
parameter VAR40 = 'h0200,
parameter VAR32 = 'h0300,
parameter VAR7 = 'h0400,
parameter VAR36 = 'h0040
) (
input [VAR23-1:0] VAR1,
input VAR9,
input [VAR44-1:0] VAR26,
input VAR48,
input VAR47,
output reg VAR4,
output reg [VAR44-1:0]... | mit |
phasza/axi_spi_if | fifo2spi.v | 8,557 | module MODULE1 (
input VAR23, input VAR9,
input [31:0] VAR11,
input [31:0] VAR55,
input [31:0] VAR33,
output VAR45,
output [31:0] VAR54,
output VAR37,
output [1:0] VAR50,
input VAR34,
input [1:0] VAR20,
output VAR24,
input VAR4,
input [35:0] VAR49,
output VAR21,
input VAR39,
output [1:0] VAR26,
output VAR1,
input VAR19... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.functional.v | 1,950 | module MODULE1 (
VAR4,
VAR16,
VAR6
);
output VAR4;
input [15:0] VAR16;
input [15:0] VAR6;
bufif1 VAR7 (VAR4 , !VAR16[0], VAR6[0] );
bufif1 VAR17 (VAR4 , !VAR16[1], VAR6[1] );
bufif1 VAR13 (VAR4 , !VAR16[2], VAR6[2] );
bufif1 VAR18 (VAR4 , !VAR16[3], VAR6[3] );
bufif1 VAR9 (VAR4 , !VAR16[4], VAR6[4] );
bufif1 VAR14 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_1.v | 2,278 | module MODULE1 (
VAR4,
VAR7 ,
VAR2,
VAR8 ,
VAR1,
VAR10,
VAR3 ,
VAR9
);
output VAR4;
input VAR7 ;
input VAR2;
input VAR8 ;
input VAR1;
input VAR10;
input VAR3 ;
input VAR9 ;
VAR5 VAR6 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_2c_v1_00_a/hdl/verilog/cf_pnmon.v | 10,264 | module MODULE1 (
VAR6,
VAR14,
VAR11,
VAR13,
VAR10);
input VAR6;
input [13:0] VAR14;
output VAR11;
output VAR13;
input VAR10;
reg VAR7 = 'd0;
reg VAR27 = 'd0;
reg VAR15 = 'd0;
reg VAR22 = 'd0;
reg [13:0] VAR1 = 'd0;
reg [13:0] VAR25 = 'd0;
reg [29:0] VAR19 = 'd0;
reg VAR17 = 'd0;
reg VAR20 = 'd0;
reg VAR5 = 'd0;
reg VAR... | mit |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/DCM/DCM_FRL.v | 4,514 | module MODULE1(VAR63,
VAR41,
VAR51,
VAR9,
VAR44);
input VAR63;
input VAR41;
output VAR51;
output VAR9;
output VAR44;
wire VAR14;
wire VAR1;
wire VAR62;
wire VAR40;
wire [6:0] VAR54;
wire [15:0] VAR15;
assign VAR40 = 0;
assign VAR54 = 7'b0000000;
assign VAR15 = 16'b0000000000000000;
assign VAR9 = VAR1;
VAR11 VAR64 (.VAR... | bsd-2-clause |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/ipi_proj/srcs/ip/xilinx_com_hls_image_filter_1_0/hdl/verilog/FIFO_image_filter_src1_rows_V.v | 2,983 | module MODULE1 (
clk,
VAR6,
VAR23,
VAR22,
VAR1);
parameter VAR27 = 32'd12;
parameter VAR17 = 32'd2;
parameter VAR19 = 32'd3;
input clk;
input [VAR27-1:0] VAR6;
input VAR23;
input [VAR17-1:0] VAR22;
output [VAR27-1:0] VAR1;
reg[VAR27-1:0] VAR25 [0:VAR19-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR23)
begin
fo... | gpl-3.0 |
YoelRP/PROYECTO | bin/example/example_code.v | 2,714 | module MODULE1 (
VAR8 , reset , VAR4 , VAR11 , VAR17 , VAR7
);
input VAR8,reset,VAR4,VAR11;
output VAR17,VAR7;
wire VAR8,reset,VAR4,VAR11;
reg VAR17,VAR7;
parameter VAR10 = 3 ;
parameter VAR5 = 3'b001,VAR12 = 3'b010,VAR3 = 3'b100 ;
reg [VAR10-1:0] state ;reg [VAR10-1:0] VAR1 ;always @ (state or VAR4 or VAR11)
begin : V... | gpl-3.0 |
d16-processor/d16 | verilog/src/dma_controller.v | 5,260 | module MODULE1(
input clk,
input rst,
input en,
output VAR9,
input [15:0] addr,
input [15:0] VAR26,
input VAR14,
output reg [15:0] VAR8,
output reg [15:0] VAR43,
output reg VAR2,
input [15:0] VAR37,
output reg [23:0] VAR22,
output reg [31:0] VAR3,
output reg VAR31,
output reg VAR42,
input [31:0] VAR19,
input VAR32,
inp... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/c47de30114c88d53/ip_design_rst_ps7_0_100M_0_stub.v | 1,837 | module MODULE1(VAR10, VAR3, VAR7,
VAR2, VAR5, VAR9, VAR1, VAR4,
VAR6, VAR8)
;
input VAR10;
input VAR3;
input VAR7;
input VAR2;
input VAR5;
output VAR9;
output [0:0]VAR1;
output [0:0]VAR4;
output [0:0]VAR6;
output [0:0]VAR8;
endmodule | mit |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/02 verilog/ProyectoDigital1/FIFO/fifo.v | 2,256 | module MODULE1
parameter VAR9 = 4,
parameter VAR3 = 8
)
(
input clk, reset,
input rd, wr,
input [VAR3-1:0] VAR17,
output [VAR3-1:0] VAR12,
output VAR4,
output VAR10
);
parameter VAR2 = (1 << VAR9);
reg [VAR3-1:0] VAR6 [VAR2-1:0];
reg [VAR9-1:0] VAR7, VAR1;
reg [VAR9-1:0] VAR11, VAR15;
reg VAR8, VAR5, VAR16, VAR13;
wire... | gpl-3.0 |
horia141/mv-parser | projects/VGAVideo/VGAVideo.v | 10,774 | module MODULE10(VAR34,reset,VAR41,VAR50);
parameter VAR64 = 8;
input wire [('b1) - ('b1):0] VAR34;
input wire [('b1) - ('b1):0] reset;
input wire [('b1) - ('b1):0] VAR41;
output reg [(VAR64) - ('b1):0] VAR50;
always @ (posedge VAR34) begin
if (reset) begin
VAR50 <= {VAR64{1'b0}};
end
else begin
if (VAR41) begin
VAR50 <... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2b/sky130_fd_sc_ms__nor2b.functional.v | 1,393 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR8;
wire VAR1 ;
wire VAR4;
not VAR7 (VAR1 , VAR2 );
and VAR6 (VAR4, VAR1, VAR8 );
buf VAR5 (VAR3 , VAR4 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/tlu/rtl/tlu_incr64.v | 1,766 | module MODULE1 ( in, out );
input [63:0] in;
output [63:0] out;
assign out = in + 64'h01;
endmodule | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_ctr5.v | 2,003 | module MODULE1(
VAR9, VAR2,
clk, VAR1, VAR8, VAR3
);
input clk;
input VAR1, VAR8;
input VAR3;
output VAR9;
output VAR2;
wire [4:0] VAR10,
VAR7,
sum;
assign sum[0] = ~VAR10[0];
assign sum[1] = VAR10[1] ^ VAR10[0];
assign sum[2] = VAR10[2] ^ (VAR10[1] & VAR10[0]);
assign sum[3] = VAR10[3] ^ (VAR10[2] & VAR10[1] & VAR10[0... | gpl-2.0 |
PeterMagnusson/modexp | src/rtl/blockmem_rw32_r64.v | 3,936 | module MODULE1(
input wire clk,
input wire VAR2,
input wire [07 : 0] VAR11,
input wire [31 : 0] VAR9,
output wire [31 : 0] VAR4,
input wire [06 : 0] VAR6,
output wire [63 : 0] VAR13
);
reg [31 : 0] VAR3 [0 : 127];
reg [31 : 0] VAR8 [0 : 127];
wire VAR10;
wire VAR14;
reg [31 : 0] VAR7;
reg [31 : 0] VAR16;
reg [31 : 0] V... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/cmd_prbs_gen.v | 10,476 | module MODULE1 #
(
parameter VAR6 = 100,
parameter VAR26 = "VAR14",
parameter VAR25 = 8,
parameter VAR13 = 29,
parameter VAR24 = 32,
parameter VAR27 = "VAR15", parameter VAR7 = 64, parameter VAR5 = 32,
parameter VAR8 = 32'hFFFFD000,
parameter VAR1 = 32'h00002000,
parameter VAR3 = 32'h00002000,
parameter VAR21 = 32'h000... | lgpl-3.0 |
puroh/Procesador_monociclo | bankregister.v | 1,775 | module MODULE1(
input [4:0] VAR5,
input [4:0] VAR7,
input [4:0] VAR1,
input VAR3,
input clk,
input [31:0] VAR6,
output wire [31:0] VAR2,
output wire [31:0] VAR8,
input reset
);
reg [31:0] register [31:0];
wire [31:0] VAR4;
assign VAR2 = register[VAR5];
assign VAR8 = register[VAR7];
always @(posedge clk )
begin
if(reset... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_freeze.v | 9,986 | module MODULE1(
clk, rst,
VAR19, VAR10, VAR18, VAR4, VAR17,
VAR15, VAR12, VAR5,
VAR9, VAR14,
VAR13, VAR16, VAR21, VAR8, VAR20,
VAR7, VAR2
);
input clk;
input rst;
input [VAR1-1:0] VAR19;
input VAR10;
input VAR18;
input VAR4;
input VAR17;
input VAR15;
input VAR9;
input VAR14;
input VAR12;
input VAR5;
output VAR13;
outpu... | gpl-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/06PCM-AUDIO-MICROFONO/Version_02/02 verilog/proyecto directo/Microfono/Microfono.v | 1,056 | module MODULE1(VAR23,VAR11,VAR18,VAR14,VAR19,VAR6,VAR21,VAR8, VAR9);
input wire VAR23;
input wire VAR11;
input wire VAR18;
input wire VAR14;
output wire VAR19;
output wire VAR6;
output wire [17:0] VAR21;
output wire VAR8;
output wire VAR9;
wire VAR17;
wire VAR2;
wire VAR25;
wire VAR3;
wire [5:0] VAR10;
wire [17:0] VAR1... | gpl-3.0 |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir/qmfir_uart/qmfir_240MHz/ISE_project/firdecim_m5_n15.v | 13,054 | module MODULE1
(
VAR41, VAR40,
VAR42, VAR24, VAR31, VAR37
);
parameter VAR7 = 16;
parameter VAR18 = 32;
parameter VAR10 = 32;
output reg signed [(VAR18-1):0] VAR41;
output reg VAR40;
input VAR42; input VAR24;
input VAR31;
input signed [(VAR7-1):0] VAR37;
reg signed [15:0] VAR13;
reg signed [15:0] VAR2;
reg signed [15:0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b_2.v | 2,184 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR5 ,
VAR3 ,
VAR7 ,
VAR1,
VAR6
);
output VAR8 ;
input VAR9 ;
input VAR5 ;
input VAR3 ;
input VAR7 ;
input VAR1;
input VAR6;
VAR2 VAR4 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8 ,
VAR9,
VAR5 ,
VAR3 ,
VAR7
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai211/gf180mcu_fd_sc_mcu7t5v0__oai211_4.behavioral.pp.v | 1,868 | module MODULE1( VAR6, VAR7, VAR9, VAR3, VAR5, VAR1, VAR8 );
input VAR9, VAR6, VAR3, VAR5;
inout VAR1, VAR8;
output VAR7;
VAR10 VAR4(.VAR6(VAR6),.VAR7(VAR7),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8));
VAR10 VAR2(.VAR6(VAR6),.VAR7(VAR7),.VAR9(VAR9),.VAR3(VAR3),.VAR5(VAR5),.VAR1(VAR1),.VAR8(VAR8)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux2/sky130_fd_sc_hvl__mux2.functional.pp.v | 1,912 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR12 ,
VAR4 ,
VAR9,
VAR11,
VAR8 ,
VAR6
);
output VAR7 ;
input VAR3 ;
input VAR12 ;
input VAR4 ;
input VAR9;
input VAR11;
input VAR8 ;
input VAR6 ;
wire VAR15 ;
wire VAR14;
VAR1 VAR13 (VAR15 , VAR3, VAR12, VAR4 );
VAR2 VAR5 (VAR14, VAR15, VAR9, VAR11);
buf VAR10 (VAR7 , VAR14 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latrsnq/gf180mcu_fd_sc_mcu7t5v0__latrsnq_2.behavioral.v | 6,154 | module MODULE1( VAR53, VAR39, VAR23, VAR35, VAR6 );
input VAR39, VAR53, VAR23, VAR35;
output VAR6;
reg VAR29;
VAR63 VAR42(.VAR53(VAR53),.VAR39(VAR39),.VAR23(VAR23),.VAR35(VAR35),.VAR6(VAR6),.VAR29(VAR29));
VAR63 VAR41(.VAR53(VAR53),.VAR39(VAR39),.VAR23(VAR23),.VAR35(VAR35),.VAR6(VAR6),.VAR29(VAR29));
and VAR28(VAR25,VA... | apache-2.0 |
alexforencich/xfcp | lib/eth/example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v | 2,561 | module MODULE1 #(
parameter VAR1=1, parameter VAR2=3, parameter VAR3=125000 )(
input wire clk,
input wire rst,
input wire [VAR1-1:0] in,
output wire [VAR1-1:0] out
);
reg [23:0] VAR5 = 24'd0;
reg [VAR2-1:0] VAR4[VAR1-1:0];
reg [VAR1-1:0] state;
assign out = state;
integer VAR6;
always @(posedge clk) begin
if (rst) begi... | mit |
eda-globetrotter/PicenoDecoders | andy/design/cencoder.v | 1,441 | module MODULE1 (output [1:0] VAR3, input VAR2, input clk, input reset);
reg [1:0] VAR3;
reg VAR1, VAR4;
always @ (posedge clk)
begin
if (reset)
begin
VAR1 <= 1'b0;
end
else
begin
VAR1 <= VAR2;
end
end
always @ (posedge clk)
begin
if (reset)
begin
VAR4 <= 1'b0;
end
else
begin
VAR4 <= VAR1;
end
end
always @ (VAR1 or VAR4... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu7t5v0__sdffq_1.functional.pp.v | 1,681 | module MODULE1( VAR1, VAR24, VAR6, VAR25, VAR10, VAR19, VAR18, VAR14 );
input VAR25, VAR6, VAR1, VAR24, VAR19, VAR18, VAR14;
output VAR10;
wire VAR21;
not VAR5( VAR21, VAR6 );
wire VAR15;
not VAR4( VAR15, VAR1 );
wire VAR2;
and VAR12( VAR2, VAR21, VAR15 );
wire VAR23;
not VAR9( VAR23, VAR24 );
wire VAR17;
and VAR16( VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Transform_ABC_to_dq.v | 2,881 | module MODULE1
(
VAR14,
VAR16,
VAR7,
VAR3,
VAR6,
VAR13
);
input signed [17:0] VAR14; input signed [17:0] VAR16; input signed [17:0] VAR7; input signed [17:0] VAR3; output signed [17:0] VAR6; output signed [17:0] VAR13;
wire signed [17:0] VAR5; wire signed [17:0] VAR17; wire signed [17:0] VAR15; wire signed [17:0] VAR11... | gpl-3.0 |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0_stub.v | 4,795 | module MODULE1(VAR39, VAR54, VAR24, VAR48,
VAR34, VAR68, VAR69, VAR27, VAR23, VAR5, VAR26, VAR56,
VAR22, VAR49, VAR45, VAR43, VAR32, VAR29, VAR33, VAR40,
VAR14, VAR62, VAR15, VAR42, VAR21, VAR35,
VAR57, VAR53, VAR58, VAR1, VAR28, VAR8, VAR4,
VAR30, VAR19, VAR38, VAR17, VAR50, VAR31,
VAR20, VAR46, VAR6, VAR55, VAR44, VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/diode/sky130_fd_sc_lp__diode.behavioral.v | 1,177 | module MODULE1 (
VAR3
);
input VAR3;
supply1 VAR4;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp.behavioral.pp.v | 1,788 | module MODULE1 (
VAR13 ,
VAR11 ,
VAR8 ,
VAR10,
VAR6,
VAR3 ,
VAR15
);
output VAR13 ;
input VAR11 ;
input VAR8 ;
input VAR10;
input VAR6;
input VAR3 ;
input VAR15 ;
wire VAR5 ;
reg VAR7 ;
wire VAR12 ;
wire VAR9;
wire VAR14 ;
VAR2 VAR1 (VAR5 , VAR12, VAR9, VAR7, VAR10, VAR6);
assign VAR14 = ( VAR10 === 1'b1 );
buf VAR4 (V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.v | 2,411 | module MODULE2 (
VAR4 ,
VAR2,
VAR11,
VAR8 ,
VAR10 ,
VAR7,
VAR1,
VAR9 ,
VAR5
);
output VAR4 ;
input VAR2;
input VAR11;
input VAR8 ;
input VAR10 ;
input VAR7;
input VAR1;
input VAR9 ;
input VAR5 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5... | apache-2.0 |
aap/pdp6 | verilog/fast162_dp.v | 7,406 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR66,
input wire VAR23,
input wire VAR86,
input wire VAR6,
input wire VAR131,
input wire VAR89,
input wire VAR37,
input wire [21:35] VAR116,
input wire [18:21] VAR125,
input wire VAR46,
input wire [0:35] VAR88,
output wire VAR26,
output wire VAR53,
output wi... | mit |
KestrelComputer/gpia3 | rtl/verilog/GPIA_DWORD_IN.v | 1,259 | module MODULE1(
input [63:0] VAR3,
input [63:0] VAR11,
input [63:0] VAR1,
input [7:0] VAR10,
output [63:0] VAR2
);
VAR14 VAR6(
.VAR3(VAR3[7:0]),
.VAR11(VAR11[7:0]),
.VAR1(VAR1[7:0]),
.VAR10(VAR10[0]),
.VAR2(VAR2[7:0])
);
VAR14 VAR4(
.VAR3(VAR3[15:8]),
.VAR11(VAR11[15:8]),
.VAR1(VAR1[15:8]),
.VAR10(VAR10[1]),
.VAR2(VAR2... | mpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v | 1,713 | module MODULE1 #(
parameter VAR4(VAR15)
, parameter VAR4(VAR34)
, parameter VAR18=0
, parameter VAR29=0
, parameter VAR10=VAR25(VAR34)
) (input VAR6
, input VAR5
, input [VAR9(VAR15, 1):0] VAR22
, input [VAR10-1:0] VAR1
, input VAR27
, input [VAR9(VAR15, 1):0] VAR11
, input VAR30
, output [VAR9(VAR15, 1):0] VAR2
);
wir... | bsd-3-clause |
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