repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
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ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtp_x8_125/example_design/PIO_64_TX_ENGINE.v | 11,925 | module MODULE1 (
clk,
VAR17,
VAR23,
VAR28,
VAR22,
VAR13,
VAR8,
VAR30,
VAR20,
VAR18,
VAR27,
VAR10,
VAR37,
VAR36,
VAR3,
VAR29,
VAR14,
VAR5,
VAR24,
VAR21,
VAR1,
VAR34,
VAR11,
VAR38,
VAR2,
VAR12,
VAR25
);
input clk;
input VAR17;
output [63:0] VAR23;
output [7:0] VAR28;
output VAR22;
output VAR13;
output VAR8;
output VAR30;... | lgpl-3.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/openmsp430/periph/omsp_gpio.v | 35,147 | module MODULE1 (
VAR211, VAR89, VAR86, VAR38, VAR239, VAR235, VAR140, VAR279, VAR175, VAR274, VAR63, VAR134, VAR207, VAR154, VAR257, VAR258, VAR215, VAR60, VAR243, VAR90, VAR95,
VAR219, VAR223, VAR18, VAR48, VAR166, VAR59, VAR183, VAR270, VAR234, VAR4, VAR165, VAR181 );
parameter VAR246 = 1'b1; parameter VAR259 = 1'b1;... | bsd-3-clause |
csail-csg/riscy-OOO | procs/asic/bluespec_verilog/RegFileLoad.v | 4,211 | module MODULE1(VAR13,
VAR6, VAR5, VAR16,
VAR20, VAR21,
VAR15, VAR4,
VAR8, VAR10,
VAR14, VAR19,
VAR7, VAR1
);
parameter VAR2 = "";
parameter VAR17 = 1;
parameter VAR3 = 1;
parameter VAR11 = 0;
parameter VAR9 = 1;
parameter VAR12 = 0;
input VAR13;
input [VAR17 - 1 : 0] VAR6;
input [VAR3 - 1 : 0] VAR5;
input VAR16;
input ... | mit |
vad-rulezz/megabot | minsoc/rtl/verilog/minsoc_xilinx_internal_jtag.v | 17,575 | module MODULE1 (
VAR20,
VAR30,
VAR15,
VAR9,
VAR48,
VAR33,
VAR4,
VAR27,
VAR35,
VAR39
);
parameter VAR37 = 1;
input VAR30;
output VAR20;
output VAR15;
output VAR9;
output VAR48;
output VAR33;
output VAR4;
output VAR27;
output VAR35;
output VAR39;
wire VAR30;
wire VAR20;
wire VAR45;
wire VAR15;
wire VAR9;
wire VAR48;
wire... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_jbus_common/rtl/bw_io_impctl_dtl_clkgen.v | 2,144 | module MODULE1(VAR14 ,VAR6 ,clk ,VAR15 ,VAR3 ,
VAR17 ,VAR5 ,VAR9 ,VAR13 ,VAR18
,VAR10 ,VAR19 );
output VAR6 ;
output VAR15 ;
output VAR5 ;
output VAR9 ;
output VAR13 ;
output VAR10 ;
input VAR14 ;
input clk ;
input VAR3 ;
input VAR17 ;
input VAR18 ;
input VAR19 ;
wire VAR7 ;
wire VAR11 ;
VAR1 VAR4 (
.VAR12 (clk ),
.VAR... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/de1/bench/uart_decoder.v | 4,088 | module MODULE1(clk, VAR4);
input clk;
input VAR4;
parameter VAR1 = 8680;
always @(posedge clk)
MODULE1;
task MODULE1;
reg [7:0] VAR2;
begin
while (VAR4 !== 1'b1)
@(VAR4);
while (VAR4 !== 1'b0)
@(VAR4);
VAR2[0] = VAR4;
VAR2[1] = VAR4;
VAR2[2] = VAR4;
VAR2[3] = VAR4;
VAR2[4] = VAR4;
VAR2[5] = VAR4;
VAR2[6] = VAR4;
VAR2[7... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3/sky130_fd_sc_hdll__nand3_4.v | 2,191 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR10 ,
VAR1 ,
VAR8,
VAR2,
VAR3 ,
VAR7
);
output VAR9 ;
input VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR8;
input VAR2;
input VAR3 ;
input VAR7 ;
VAR5 VAR6 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
anderson1008/NOCulator | hring/hw/bless_mc/permutationNetwork.v | 4,294 | module MODULE2 (
VAR13,
VAR29,
VAR14,
VAR26,
VAR31,
VAR19,
VAR25,
VAR20,
VAR30,
VAR27,
VAR5,
VAR24,
VAR10,
VAR8,
VAR11,
VAR17
);
output [1:0] VAR30, VAR27, VAR5, VAR24;
input [VAR32-1:0] VAR13, VAR29, VAR14, VAR26;
input [VAR34-2:0] VAR31, VAR19, VAR25, VAR20;
output [VAR34-2:0] VAR10, VAR8, VAR11, VAR17;
wire [VAR7-1:... | mit |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_V2NFC100DDR_0_0/synth/OpenSSD2_V2NFC100DDR_0_0.v | 6,166 | module MODULE1 (
VAR35,
VAR25,
VAR33,
VAR29,
VAR17,
VAR30,
VAR7,
VAR11,
VAR18,
VAR34,
VAR28,
VAR13,
VAR36,
VAR12,
VAR27,
VAR31,
VAR22,
VAR3,
VAR10,
VAR6,
VAR24,
VAR26,
VAR15,
VAR23,
VAR5,
VAR1,
VAR4,
VAR9,
VAR20,
VAR19,
VAR21
);
input wire VAR35;
input wire VAR25;
input wire VAR33;
input wire VAR29;
input wire [5 : 0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv.functional.pp.v | 1,774 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR2,
VAR1,
VAR10 ,
VAR4
);
output VAR7 ;
input VAR8 ;
input VAR2;
input VAR1;
input VAR10 ;
input VAR4 ;
wire VAR12 ;
wire VAR11;
not VAR9 (VAR12 , VAR8 );
VAR3 VAR5 (VAR11, VAR12, VAR2, VAR1);
buf VAR6 (VAR7 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ebufn/sky130_fd_sc_hd__ebufn_1.v | 2,148 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR8,
VAR1,
VAR5,
VAR6 ,
VAR4
);
output VAR7 ;
input VAR9 ;
input VAR8;
input VAR1;
input VAR5;
input VAR6 ;
input VAR4 ;
VAR3 VAR2 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR7 ,
VAR9 ,
VAR8
);
output VAR7 ;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/mux4/sky130_fd_sc_hvl__mux4.symbol.v | 1,372 | module MODULE1 (
input VAR4,
input VAR8,
input VAR6,
input VAR5,
output VAR9 ,
input VAR10,
input VAR1
);
supply1 VAR11;
supply0 VAR3;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s.behavioral.v | 1,438 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR4;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR7 ;
wire VAR1;
buf VAR9 (VAR1, VAR6 );
buf VAR5 (VAR2 , VAR1 );
endmodule | apache-2.0 |
yaqwsx/MandelbrotFPGA | VGA_Controller/VGA_Controller.v | 4,940 | module MODULE1( VAR9,
VAR30,
VAR27,
VAR13,
VAR41,
VAR2,
VAR42,
VAR36,
VAR39,
VAR6,
VAR14,
VAR3,
VAR4,
VAR33,
VAR7,
VAR15,
VAR23,
VAR29,
VAR38,
VAR24,
VAR37,
VAR34 );
output reg [19:0] VAR6;
output reg [9:0] VAR14;
output reg [9:0] VAR3;
input [3:0] VAR9;
input [9:0] VAR30;
input [9:0] VAR27;
input [9:0] VAR13;
input [9... | mit |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/MULT_PEAK/MULT_PEAK_bb.v | 3,776 | module MODULE1 (
VAR1,
VAR2,
VAR3);
input [59:0] VAR1;
input [49:0] VAR2;
output [109:0] VAR3;
endmodule | gpl-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/cdp/output_ctrl.v | 21,671 | module MODULE1(
clk,
reset,
VAR4, VAR24,
VAR39,
VAR16, VAR1,
VAR40,
VAR6, VAR27,
VAR10,
VAR14, VAR31, VAR7, VAR34,
VAR35
);
input clk;
input reset;
input VAR4;
input [138:0]VAR24;
output [7:0]VAR39;
input [29:0]VAR16;
output VAR6;
input VAR27;
input [138:0]VAR10;
output VAR14;
output [18:0]VAR31;
output VAR7;
output [1... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/clk_gen/clk_gen_clk_wiz.v | 6,435 | module MODULE1
( input VAR75,
output VAR24,
input reset
);
VAR30 VAR49
(.VAR7 (VAR1),
.VAR67 (VAR75));
wire [15:0] VAR64;
wire VAR52;
wire VAR20;
wire VAR54;
wire VAR8;
wire VAR11;
wire VAR76;
wire VAR35;
wire VAR63;
wire VAR78;
wire VAR2;
wire VAR60;
wire VAR71;
wire VAR31;
wire VAR51;
wire VAR4;
wire VAR72;
wire VAR2... | gpl-3.0 |
egyp7/mor1kx | rtl/verilog/mor1kx.v | 21,556 | module MODULE1
parameter VAR192 = 32,
parameter VAR78 = "VAR20",
parameter VAR63 = "VAR28",
parameter VAR80 = 5,
parameter VAR15 = 9,
parameter VAR135 = 2,
parameter VAR149 = 32,
parameter VAR170 = "VAR28",
parameter VAR93 = "VAR28",
parameter VAR23 = "VAR28",
parameter VAR5 = 6,
parameter VAR172 = 1,
parameter VAR182 ... | mpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/ethernet_port_interface_0.v | 3,689 | module MODULE1 (
input wire clk, input wire reset, input wire [26:0] VAR18, input wire VAR3, output wire [31:0] VAR2, input wire VAR7, input wire [31:0] VAR11, output wire VAR10, input wire [7:0] VAR12, output wire VAR20, input wire VAR8, input wire [5:0] VAR16, input wire VAR17, input wire VAR9, output wire [7:0] VAR4... | apache-2.0 |
dengjeffrey/BirthdayClockVerilog | ps2lab1.v | 1,790 | module MODULE1(
input VAR38,
input [3:0] VAR15,
input [17:0] VAR27,
output [6:0] VAR9, VAR19, VAR1, VAR16, VAR10, VAR2, VAR11, VAR39,
output [8:0] VAR7, output [17:0] VAR34, input VAR22,
input VAR35,
inout [35:0] VAR4, VAR25
);
assign VAR4 = 36'VAR5;
assign VAR25 = 36'VAR5;
wire VAR13;
assign VAR13 = VAR15[0];
assign V... | mit |
sarchar/uart_de0_nano | uart_fifo_dual_port_ram_bb.v | 7,871 | module MODULE1 (
VAR6,
VAR5,
VAR4,
VAR2,
VAR1,
VAR3);
input VAR6;
input [7:0] VAR5;
input [9:0] VAR4;
input [9:0] VAR2;
input VAR1;
output [7:0] VAR3;
tri1 VAR6;
tri0 VAR1;
endmodule | mit |
chriz2600/DreamcastHDMI | Core/source/filter/ram2video_f.v | 19,213 | module MODULE1(
input VAR68,
input reset,
input VAR97,
input VAR62,
output reg VAR36,
input VAR74 VAR6,
output [VAR143-1:0] VAR19 ,
input [23:0] VAR54,
output [9:0] VAR94 ,
input [7:0] VAR96,
input VAR59,
input [7:0] VAR1,
input VAR50 VAR137 ,
output [23:0] VAR16,
output VAR160,
output VAR144,
output VAR135
);
localpar... | mit |
hwstar/Timestamper-FPGA | utx.v | 6,309 | module MODULE2(clk, VAR22, VAR4, VAR13);
input clk;
input VAR22;
input VAR4;
output reg VAR13;
reg [10:0] VAR6;
always @ begin
VAR25 <= 1;
VAR11 <= 0;
VAR19 <= 0;
VAR2 <= 1;
VAR9 <= VAR13;
case(VAR10)
if(VAR27) begin
VAR8 <= VAR29;
VAR2 <= 0; end else begin
VAR25 <= 0; VAR9 <= 0; VAR8 <= VAR32; end
if(VAR13) begin
VAR8... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2b/sky130_fd_sc_ls__nor2b.pp.blackbox.v | 1,322 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR3 ,
VAR4,
VAR5,
VAR2 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR4;
input VAR5;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/Sdram_Controller/control_interface.v | 6,560 | module MODULE1(
VAR10,
VAR2,
VAR20,
VAR15,
VAR5,
VAR17,
VAR22,
VAR8,
VAR6,
VAR19,
VAR18,
VAR1,
VAR11,
VAR9,
VAR14,
VAR13,
VAR7
);
input VAR10; input VAR2; input [2:0] VAR20; input [VAR16-1:0] VAR15; input VAR5; input VAR17; input VAR22; output VAR8; output VAR6; output VAR19; output VAR18; output VAR1; output VAR11; ou... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/example_design/rtl/traffic_gen/data_prbs_gen.v | 4,666 | module MODULE1 #
(
parameter VAR8 = 100,
parameter VAR4 = "VAR1",
parameter VAR2 = 32, parameter VAR7 = 32
)
(
input VAR5,
input VAR14,
input VAR13,
input VAR11, input [VAR2 - 1:0] VAR3,
output [VAR2 - 1:0] VAR10 );
reg [VAR2 - 1 :0] VAR12;
reg [VAR2 :1] VAR6;
integer VAR9;
always @ (posedge VAR5)
begin
if (VAR11 && VA... | lgpl-3.0 |
asicguy/gplgpu | hdl/altera_project/fifo_128x128a/fifo_128x128a_bb.v | 5,878 | module MODULE1 (
VAR7,
VAR6,
VAR2,
VAR9,
VAR5,
VAR3,
VAR8,
VAR4,
VAR10,
VAR1);
input VAR7;
input [127:0] VAR6;
input VAR2;
input VAR9;
input VAR5;
input VAR3;
output [127:0] VAR8;
output VAR4;
output VAR10;
output [6:0] VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf.behavioral.v | 1,345 | module MODULE1 (
VAR9,
VAR5
);
output VAR9;
input VAR5;
supply1 VAR8;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
wire VAR6;
buf VAR7 (VAR6, VAR5 );
buf VAR2 (VAR9 , VAR6 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_alu.v | 8,743 | module MODULE1
(
VAR50, VAR13, VAR47, VAR54,
VAR28, VAR19, VAR55,
VAR36, VAR39, VAR80,
VAR69, VAR34, VAR38, VAR52,
VAR20, VAR23,
VAR57, VAR73, VAR12,
VAR22,
VAR21, VAR24, VAR48, VAR8, VAR11,
VAR37, VAR30, VAR64,
VAR17, VAR26, VAR67,
VAR1, VAR3,
VAR60, VAR56,
VAR65, VAR59,
VAR16, VAR42, VAR7
);
input VAR21;
input VAR24;... | gpl-2.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/Dc2Tile.v | 8,117 | module MODULE1(
VAR29, reset,
VAR28, VAR7,
VAR10, VAR50,
VAR39, VAR4,
VAR55,
VAR40, VAR37, VAR49,
VAR13, VAR32, VAR51,
VAR27, VAR14, VAR2,
VAR23, VAR47, VAR25
);
input VAR29; input reset; input[31:0] VAR28; input[127:0] VAR7; input VAR39; input VAR4; input[4:0] VAR55;
output[127:0] VAR10; output[1:0] VAR50;
input[127:0... | mit |
TheMadSocrates/vercpu-project | rtl/fpga/progmem.v | 1,775 | module MODULE1(
input wire [ 7 : 0] VAR1,
output reg [15 : 0] VAR2
);
always @(VAR1) begin
case(VAR1)
8'h00: VAR2 = 16'h7f00;
8'h01: VAR2 = 16'h0100;
8'h02: VAR2 = 16'h0101;
8'h03: VAR2 = 16'h7200;
8'h04: VAR2 = 16'h74ff;
8'h05: VAR2 = 16'h0a0c;
8'h06: VAR2 = 16'h0101;
8'h07: VAR2 = 16'h0000;
8'h08: VAR2 = 16'h0100;
8'... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/lsu/rtl/lsu_dc_parity_gen.v | 1,791 | module MODULE1 (VAR5, VAR3);
parameter VAR2 = 8 ;
parameter VAR6 = 16 ;
input [VAR2 * VAR6 - 1 : 0] VAR3 ;
output [VAR6 - 1 : 0] VAR5 ; reg [VAR6 - 1 : 0] VAR1 ;
integer VAR7 ;
integer VAR4 ;
always @(VAR3)
for (VAR7 = 0; VAR7 <= VAR6 - 1 ; VAR7 = VAR7 + 1) begin
VAR1[VAR7] = 1'b0 ;
for (VAR4 = VAR2 * VAR7; VAR4 <= VAR... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_RX_EMPTY.v | 1,877 | module MODULE1 (
address,
clk,
VAR2,
VAR3,
VAR6
)
;
output [ 31: 0] VAR6;
input [ 1: 0] address;
input clk;
input VAR2;
input VAR3;
wire VAR4;
wire VAR5;
wire VAR1;
reg [ 31: 0] VAR6;
assign VAR4 = 1;
assign VAR1 = {1 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR3)
begin
if (VAR3 == 0)
VAR6 <= 0;
end
el... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp_m.v | 2,127 | module MODULE2 (
VAR9 ,
VAR5 ,
VAR6 ,
VAR8,
VAR3,
VAR4 ,
VAR2
);
output VAR9 ;
input VAR5 ;
input VAR6 ;
input VAR8;
input VAR3;
input VAR4 ;
input VAR2 ;
VAR7 VAR1 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR9 ,
VAR5 ,
VAR6
);
output VAR9... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/vga_timing.v | 4,730 | module MODULE1 (
input wire VAR5,
input wire rst,
output reg [9:0] VAR17,
output reg VAR9,
output reg [9:0] VAR21,
output reg VAR3,
output reg VAR4
);
localparam VAR20 = 800;
localparam VAR14 = 640;
localparam VAR22 = 656;
localparam VAR7 = 96;
localparam VAR15 = 0;
localparam VAR19 = 525;
localparam VAR18 = 480;
local... | mit |
spesialstyrker/boula | gen/FIFO.v | 14,170 | module MODULE1(
VAR399,
VAR425,
VAR238,
VAR208,
VAR223,
VAR188,
VAR275,
VAR37,
VAR163,
VAR262,
VAR164,
VAR352,
VAR246,
VAR340,
VAR222
);
input VAR399;
input VAR425;
input VAR238;
input VAR208;
output VAR223;
input [63 : 0] VAR188;
input [7 : 0] VAR275;
input VAR37;
output VAR163;
input VAR262;
output [63 : 0] VAR164;
o... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_Video_Clipper.v | 9,894 | module MODULE1 (
clk,
reset,
VAR14,
VAR23,
VAR37,
VAR42,
VAR31,
VAR10,
VAR41,
VAR20,
VAR39,
VAR13,
VAR9,
VAR3
);
parameter VAR17 = 15; parameter VAR40 = 0;
parameter VAR19 = 720; parameter VAR27 = 244; parameter VAR2 = 9; parameter VAR21 = 7;
parameter VAR30 = 40;
parameter VAR44 = 40;
parameter VAR35 = 2;
parameter VA... | gpl-2.0 |
csail-csg/recycle-bsv-lib | src/v/EHR_3.v | 2,399 | module MODULE1 (
VAR11,
VAR8,
VAR15,
VAR17,
VAR6,
VAR5,
VAR12,
VAR7,
VAR1,
VAR2,
VAR9
);
parameter VAR10 = 1;
parameter VAR13 = 0;
input VAR11;
input VAR8;
output [VAR10-1:0] VAR15;
input [VAR10-1:0] VAR17;
input VAR6;
output [VAR10-1:0] VAR5;
input [VAR10-1:0] VAR12;
input VAR7;
output [VAR10-1:0] VAR1;
input [VAR10-1... | mit |
omicronns/studies-sys-rek | lab4/zlozony/src/delay_line/delay_line.v | 1,204 | module MODULE1 #(
parameter VAR5 = 0,
parameter VAR4 = 1
)(
input VAR6,
input rst,
input clk,
input [VAR4 - 1:0] in,
output [VAR4 - 1:0] out
);
wire [VAR4 - 1:0] VAR7 [VAR5:0];
assign VAR7[0] = in;
assign out = VAR7[VAR5];
generate
genvar VAR3;
for(VAR3 = 0; VAR3 < VAR5; VAR3 = VAR3 + 1)
VAR2 #(
.VAR4(VAR4)
)
VAR1 (
.V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/einvn/sky130_fd_sc_hs__einvn.pp.blackbox.v | 1,236 | module MODULE1 (
VAR2 ,
VAR1,
VAR3 ,
VAR4,
VAR5
);
input VAR2 ;
input VAR1;
output VAR3 ;
input VAR4;
input VAR5;
endmodule | apache-2.0 |
plindstroem/oh | elink/hdl/etx_protocol.v | 5,608 | module MODULE1 (
VAR46, VAR48, VAR24, VAR26, VAR42,
reset, clk, VAR47, VAR39, VAR21, VAR45,
VAR16, VAR44, VAR31, VAR9
);
parameter VAR49 = 104;
parameter VAR36 = 32;
parameter VAR20 = 32;
parameter VAR14 = 12'h000;
input reset;
input clk;
input VAR47;
input [VAR49-1:0] VAR39;
output VAR46;
output VAR48;
input VAR21; in... | gpl-3.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_tx_stuff.v | 2,156 | module MODULE1
(input VAR2,
input VAR8,
input VAR5,
output VAR25,
output VAR18,
input VAR23,
output VAR19);
localparam VAR17 = 4'd0;
localparam VAR15 = 4'd1;
localparam VAR14 = 4'd2;
localparam VAR16 = 4'd3;
localparam VAR7=4, VAR3=5;
reg [VAR3+VAR7-1:0] VAR20;
wire [VAR7-1:0] state;
wire [VAR7-1:0] VAR22 = VAR20[VAR7+... | apache-2.0 |
olofk/wb_streamer | rtl/verilog/wb_stream_reader.v | 3,460 | module MODULE1
parameter VAR33 = 32,
parameter VAR41 = 0,
parameter VAR43 = 2**VAR41)
(input clk,
input rst,
output [VAR33-1:0] VAR2,
output [VAR5-1:0] VAR23,
output [VAR5/8-1:0] VAR11,
output VAR29 ,
output VAR55,
output VAR52,
output [2:0] VAR63,
output [1:0] VAR8,
input [VAR5-1:0] VAR59,
input VAR36,
input VAR56,
in... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s.blackbox.v | 1,324 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
input VAR6;
supply1 VAR3;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb_4.v | 2,323 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR5 ,
VAR2 ,
VAR11 ,
VAR4,
VAR6,
VAR9 ,
VAR7
);
output VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR2 ;
input VAR11 ;
input VAR4;
input VAR6;
input VAR9 ;
input VAR7 ;
VAR10 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai_4.v | 2,352 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR10 ,
VAR6 ,
VAR3,
VAR11,
VAR9 ,
VAR4
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR6 ;
input VAR3;
input VAR11;
input VAR9 ;
input VAR4 ;
VAR1 VAR7 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR9(VAR9),
.... | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/fx2_to_bus.v | 1,091 | module MODULE1 #(
parameter VAR5 = 16 ) (
input wire [VAR5-1:0] VAR10,
input wire VAR7, input wire VAR6,
input wire VAR9, output wire [VAR5-1:0] VAR4,
output wire VAR8,
output wire VAR1,
output wire VAR3
);
assign VAR4 = VAR10 - 16'h4000;
assign VAR3 = ~VAR10[15] & VAR10[14];
reg VAR2;
always @(posedge VAR9) begin
VAR2... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi_2.v | 2,450 | module MODULE2 (
VAR12 ,
VAR5 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR6 ,
VAR8,
VAR7,
VAR3 ,
VAR11
);
output VAR12 ;
input VAR5 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR6 ;
input VAR8;
input VAR7;
input VAR3 ;
input VAR11 ;
VAR10 VAR1 (
.VAR12(VAR12),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR8(VA... | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_protocol.v | 14,577 | module MODULE1 (
input wire VAR9,
input wire VAR171,
input wire VAR168,
input wire VAR32,
input wire [4:0] VAR3,
input wire VAR185,
input wire VAR158,
input wire VAR62,
input wire VAR138,
input wire [3:0] VAR51,
input wire [3:0] VAR86,
input wire [4:0] VAR40,
input wire [4:0] VAR25,
input wire [15:0] VAR189,
input wire... | isc |
kyflores/ice-mc | rtl/commutation.v | 1,217 | module MODULE1(
clk,
VAR5,
VAR7,
VAR6,
VAR4,
VAR8,
VAR9,
VAR3
);
input wire clk, VAR5, VAR7, VAR6, VAR4, VAR8, VAR9;
reg[2:0] VAR1;
output wire[3:0] VAR3;
reg[3:0] VAR2[7:0];
always @(posedge clk) begin
if (VAR7) begin
VAR1 <= 0;
VAR2[0] <= 4'b0110;
VAR2[1] <= 4'b0100;
VAR2[2] <= 4'b1100;
VAR2[3] <= 4'b1000;
VAR2[4] <=... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pcie_pipe_misc.v | 8,397 | module MODULE1 #
(
parameter VAR1 = 0 )
(
input wire VAR12 , input wire VAR23 , input wire VAR10 , input wire VAR28 , input wire [2:0] VAR9 , input wire VAR4 ,
output wire VAR19 , output wire VAR25 , output wire VAR26 , output wire VAR2 , output wire [2:0] VAR29 , output wire VAR30 ,
input wire VAR22 , input wire VAR21... | mit |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ip/design_1_axis_broadcaster_0_0/synth/design_1_axis_broadcaster_0_0.v | 5,701 | module MODULE1 (
VAR15,
VAR16,
VAR18,
VAR29,
VAR20,
VAR12,
VAR32,
VAR22,
VAR7,
VAR27,
VAR3,
VAR2
);
input wire VAR15;
input wire VAR16;
input wire VAR18;
output wire VAR29;
input wire [7 : 0] VAR20;
input wire [0 : 0] VAR12;
input wire VAR32;
output wire [1 : 0] VAR22;
input wire [1 : 0] VAR7;
output wire [15 : 0] VAR2... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpu/integracion_fisica/front_end/source/RecursiveKOA_1c.v | 5,749 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR18,
input wire [VAR15-1:0] VAR5,
input wire [VAR15-1:0] VAR31,
output wire [2*VAR15-1:0] VAR27
);
wire [1:0] VAR28;
wire [3:0] VAR3;
assign VAR28 = 2'b00;
assign VAR3 = 4'b0000;
wire [VAR15/2-1:0] VAR36;
wire [VAR15/2:0] VAR20;
wire [VAR15/2-3:0] VAR16;
wir... | gpl-3.0 |
trander1/Dual-Core-Processor | FinalProjectV3/Modules/fifo.v | 4,131 | (VAR19<=4)?2:\
-1
module MODULE1(
VAR23, VAR13, VAR31,
VAR29, reset, clk
);
parameter VAR8 = 4;
parameter VAR22 = 2;
parameter VAR21 = 2;
parameter VAR10 = 1;
parameter VAR20 = VAR8+VAR21+VAR10; parameter VAR3 = 'b0;
parameter VAR7 = VAR6(VAR22);
parameter VAR1 = 2'b01;
parameter VAR28 = 2'b10;
parameter VAR9 = 2'b00;
... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/Multipliers/26bit/BinaryKOA/ks8.v | 1,280 | module MODULE1(VAR2, VAR4, VAR10);
input wire [7:0] VAR2;
input wire [7:0] VAR4;
output wire [14:0] VAR10;
wire [6:0] VAR3;
wire [6:0] VAR6;
wire [6:0] VAR1;
wire [3:0] VAR5;
wire [3:0] VAR9;
VAR12 VAR11(VAR2[3:0], VAR4[3:0], VAR6);
VAR12 VAR8(VAR2[7:4], VAR4[7:4], VAR3);
assign VAR5[3:0] = VAR2[7:4] ^ VAR2[3:0];
assig... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.pp.blackbox.v | 1,269 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR2 ,
VAR3 ,
VAR4,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR3 ;
input VAR4;
input VAR5;
endmodule | apache-2.0 |
freecores/orsoc_graphics_accelerator | rtl/verilog/gfx/gfx_fragment_processor.v | 7,364 | module MODULE1(VAR31, VAR49,
VAR28,
VAR17, VAR16, VAR36, VAR44, VAR41, VAR24, VAR8, VAR50, VAR26, VAR48, VAR7, VAR40, VAR9, VAR46, VAR38, VAR15, VAR43, VAR30, VAR10, VAR1, VAR35, VAR6, VAR32, VAR11, VAR45, VAR25, VAR37, VAR29, VAR12, VAR14, VAR19 );
parameter VAR27 = 16;
input VAR31;
input VAR49;
input [7:0] VAR28;
inp... | gpl-3.0 |
ueliem/literate-broccoli | bidir/bidir_switch_block.v | 4,084 | module MODULE1(
input [VAR6*VAR6*12-1:0] select,
inout [VAR6-1:0] VAR5,
inout [VAR6-1:0] VAR8,
inout [VAR6-1:0] VAR4
);
parameter VAR6 = 3;
wire [VAR6-1:0] VAR3;
genvar VAR7, VAR9;
wire VAR11[VAR6:0][VAR6:0];
generate
for(VAR9 = 0; VAR9 < VAR6; VAR9 = VAR9 + 1) begin
for (VAR7 = 0; VAR7 < VAR6; VAR7 = VAR7 + 1) begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.functional.v | 1,435 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR7 ,
VAR3,
VAR10
);
output VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR3;
input VAR10;
wire VAR4 ;
wire VAR2;
nor VAR6 (VAR4 , VAR1, VAR7 );
and VAR5 (VAR2, VAR4, VAR3, VAR10);
buf VAR8 (VAR9 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.v | 2,068 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR7,
VAR1,
VAR3 ,
VAR2
);
output VAR8 ;
input VAR5 ;
input VAR7;
input VAR1;
input VAR3 ;
input VAR2 ;
VAR4 VAR6 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8,
VAR5
);
output VAR8;
input VAR5;
supply1 VAR7;
supply0 VAR1;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221a/sky130_fd_sc_ls__o221a.blackbox.v | 1,395 | module MODULE1 (
VAR4 ,
VAR2,
VAR6,
VAR9,
VAR10,
VAR3
);
output VAR4 ;
input VAR2;
input VAR6;
input VAR9;
input VAR10;
input VAR3;
supply1 VAR7;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_2.behavioral.v | 1,718 | module MODULE1( VAR6, VAR5, VAR8 );
input VAR5, VAR6;
output VAR8;
reg VAR4;
VAR3 VAR9(.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR4(VAR4));
VAR3 VAR11(.VAR6(VAR6),.VAR5(VAR5),.VAR8(VAR8),.VAR4(VAR4));
not VAR2(VAR7,VAR5);
buf VAR10(VAR1,VAR5); | apache-2.0 |
asicguy/gplgpu | hdl/vga/serializer_a.v | 14,101 | module MODULE1
(
input VAR35,
input VAR65, input VAR40, input VAR75, input VAR7, input VAR55, input VAR79, input VAR66, input VAR21, input VAR77,
input [3:0] VAR59,
input [36:0] VAR83, input VAR41, input VAR50, input VAR47,
input VAR63,
input VAR43,
input VAR29,
input [3:0] VAR36,
input [3:0] VAR38,
input VAR72,
input ... | gpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/xilinx_ddr2.v | 6,361 | module MODULE1
(
input [31:0] VAR2,
input [1:0] VAR40,
input [2:0] VAR54,
input VAR84,
input [31:0] VAR62,
input [3:0] VAR52,
input VAR11,
input VAR82,
output VAR17,
output VAR72,
output VAR65,
output [31:0] VAR33,
input [31:0] VAR83,
input [1:0] VAR76,
input [2:0] VAR34,
input VAR47,
input [31:0] VAR3,
input [3:0] VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfxbp/sky130_fd_sc_hs__sdfxbp.behavioral.pp.v | 2,396 | module MODULE1 (
VAR8,
VAR7,
VAR20 ,
VAR14 ,
VAR4 ,
VAR5 ,
VAR17 ,
VAR21
);
input VAR8;
input VAR7;
output VAR20 ;
output VAR14 ;
input VAR4 ;
input VAR5 ;
input VAR17 ;
input VAR21 ;
wire VAR2 ;
wire VAR23 ;
reg VAR3 ;
wire VAR16 ;
wire VAR6;
wire VAR15;
wire VAR13;
wire VAR12 ;
wire VAR22 ;
wire VAR11 ;
wire VAR19 ;
... | apache-2.0 |
moizumi99/brainf__k_CPU | hdl/lcdcontrol.v | 2,041 | module MODULE1 (
input VAR8, VAR16,
input VAR9,
input [8:0] VAR17,
output reg VAR6,
output VAR5, output VAR14, output VAR2, output VAR12, inout [7:0] VAR1 );
reg [8:0] VAR10;
reg [4:0] VAR11;
reg [17:0] VAR13;
wire VAR7;
wire VAR4;
reg VAR15;
reg [19:0] VAR3;
assign VAR14 = 1'b0; assign VAR5 = 1'b1; assign VAR12 = VAR1... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3.functional.pp.v | 1,733 | module MODULE1 (
VAR9 ,
VAR2 ,
VAR5,
VAR8
);
output VAR9 ;
input VAR2 ;
input VAR5;
input VAR8;
wire VAR6 ;
wire VAR3;
buf VAR10 (VAR6 , VAR2 );
VAR1 VAR4 (VAR3, VAR6, VAR5, VAR8);
buf VAR7 (VAR9 , VAR3 );
endmodule | apache-2.0 |
Candyroot/Floating-Point-Addition | Control.v | 2,271 | module MODULE1(clk,VAR1,VAR7,VAR11,
VAR10,VAR6,
VAR18,VAR4,VAR19,VAR5,
VAR3,VAR9,VAR17,VAR2,VAR8,VAR13,VAR14,VAR16,VAR15);
integer VAR20;
reg [7:0] VAR12=0;
input clk,VAR1;
input [8:0] VAR7;
input [27:0] VAR11,VAR10;
output reg VAR4,VAR19,VAR17,VAR2;
output reg VAR8,VAR13,VAR14,VAR16,VAR15;
output reg [7:0] VAR5,VAR6;
... | gpl-3.0 |
cornell-zhang/datuner | designs/vtr/spree.v | 72,567 | module MODULE6 (
clk,
VAR30,
VAR265,
VAR79,
VAR224,
VAR43,
VAR106,
VAR137,
VAR268
);
input clk;
input VAR30;
input [31:0] VAR265;
input [31:0] VAR79;
input VAR224;
input [31:0] VAR43;
input [31:0] VAR106;
input VAR137;
output [31:0] VAR268;
wire VAR163;
wire VAR237;
wire VAR323;
wire VAR20;
wire VAR119;
wire VAR67;
wir... | bsd-3-clause |
peteasa/oh | src/mio/hdl/mio_regs.v | 7,745 | module MODULE1 #(parameter VAR59 = 8, parameter VAR67 = 32, parameter VAR62 = 104, parameter VAR30 = 0, parameter VAR24 = 0 )
(
input clk,
input VAR49,
input VAR46, input [VAR62-1:0] VAR29, output VAR6,
output VAR20, output [VAR62-1:0] VAR52, input VAR48,
output VAR65, output VAR51, output VAR43, output VAR64, output V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbp/sky130_fd_sc_hd__dlrbp.symbol.v | 1,456 | module MODULE1 (
input VAR5 ,
output VAR1 ,
output VAR3 ,
input VAR4,
input VAR8
);
supply1 VAR6;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
alexforencich/verilog-i2c | rtl/i2c_slave_axil_master.v | 17,501 | module MODULE1 #
(
parameter VAR25 = 4,
parameter VAR11 = 32, parameter VAR24 = 16, parameter VAR9 = (VAR11/8)
)
(
input wire clk,
input wire rst,
input wire VAR2,
output wire VAR40,
output wire VAR15,
input wire VAR37,
output wire VAR12,
output wire VAR28,
output wire [VAR24-1:0] VAR10,
output wire [2:0] VAR23,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.blackbox.v | 1,397 | module MODULE1 (
VAR1 ,
VAR7,
VAR5,
VAR9 ,
VAR2
);
output VAR1 ;
input VAR7;
input VAR5;
input VAR9 ;
input VAR2 ;
supply1 VAR3;
supply0 VAR4;
supply1 VAR8 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai.functional.pp.v | 2,065 | module MODULE1 (
VAR18 ,
VAR9 ,
VAR15 ,
VAR6 ,
VAR8 ,
VAR13 ,
VAR1,
VAR14,
VAR12 ,
VAR3
);
output VAR18 ;
input VAR9 ;
input VAR15 ;
input VAR6 ;
input VAR8 ;
input VAR13 ;
input VAR1;
input VAR14;
input VAR12 ;
input VAR3 ;
wire VAR4 ;
wire VAR5 ;
wire VAR17;
or VAR2 (VAR4 , VAR15, VAR9, VAR6 );
nand VAR10 (VAR5 , VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_hs__udp_dlatch_pr_pp_pkg_s.blackbox.v | 1,490 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR2,
VAR7 ,
VAR8 ,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR2;
input VAR7 ;
input VAR8 ;
input VAR5 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu9t5v0__xnor3_2.behavioral.pp.v | 2,623 | module MODULE1( VAR1, VAR2, VAR3, VAR6, VAR4, VAR8 );
input VAR2, VAR1, VAR3;
inout VAR4, VAR8;
output VAR6;
VAR7 VAR5(.VAR1(VAR1),.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8));
VAR7 VAR9(.VAR1(VAR1),.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR4(VAR4),.VAR8(VAR8)); | apache-2.0 |
jhol/butterflylogic | rtl/rle_enc.v | 6,818 | module MODULE1 #(
parameter integer VAR24 = 32
)(
input wire clk,
input wire rst,
input wire enable,
input wire VAR30,
input wire [1:0] VAR18,
input wire [3:0] VAR10,
input wire [VAR24-1:0] VAR9,
input wire VAR33,
output reg [VAR24-1:0] VAR19,
output reg VAR15 = 0
);
localparam VAR22 = 1'b1;
reg VAR23 = 0, VAR16;
reg V... | gpl-2.0 |
meteorcloudy/CPU_verilog | shift.v | 1,662 | module MODULE1(VAR34,VAR24,VAR35,VAR8,VAR17
);
input [31:0] VAR34;
input [4:0] VAR24;
input VAR35,VAR8;
output [31:0] VAR17;
wire [31:0] VAR16,VAR13,VAR15,VAR18,VAR3,VAR25,VAR7,VAR26,VAR11;
wire VAR1=VAR34[31]&VAR8;
wire [15:0] VAR32={16{VAR1}};
parameter VAR37=16'b0;
wire [31:0] VAR33,VAR20,VAR29,VAR12,VAR6,VAR9,VAR4,... | mit |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_arb_hp0_1.v | 3,359 | module MODULE1(
VAR13,
VAR26,
VAR28,
VAR52,
VAR9,
VAR27,
VAR22,
VAR32,
VAR65,
VAR54,
VAR41,
VAR3,
VAR31,
VAR29,
VAR34,
VAR55,
VAR23,
VAR49,
VAR46,
VAR21,
VAR62,
VAR33,
VAR39,
VAR7,
VAR25,
VAR11,
VAR43,
VAR59,
VAR14,
VAR12,
VAR51,
VAR66,
VAR4,
VAR17,
VAR64,
VAR36,
VAR6,
VAR38
);
input VAR13;
input VAR26;
input [VAR19-1:... | gpl-3.0 |
horia141/bachelor-thesis | prj/components/Alu/Alu.v | 7,036 | module MODULE1(VAR25,reset,VAR12,VAR36,VAR27);
input wire VAR25;
input wire reset;
input wire [11:0] VAR12;
input wire VAR36;
output wire [7:0] VAR27;
reg [1:0] VAR30;
reg [7:0] VAR22;
wire [3:0] VAR32;
wire [7:0] VAR31;
reg [256*8-1:0] VAR10;
reg [256*8-1:0] VAR4;
assign VAR27 = VAR22;
assign VAR32 = VAR12[11:8];
assi... | mit |
AngelTerrones/MUSB | Hardware/musb/musb_idex_register.v | 7,818 | module MODULE1(
input clk, input rst, input [4:0] VAR48, input [31:0] VAR32, input [31:0] VAR53, input VAR26, input VAR42, input VAR35, input [1:0] VAR50, input [1:0] VAR33, input [1:0] VAR39, input VAR6, input VAR20, input VAR8, input [4:0] VAR10, input [4:0] VAR18, input VAR57, input [15:0] VAR31, input [31:0] VAR19,... | mit |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/verilog/ANN_ST_uOut.v | 1,990 | module MODULE1 (VAR5, VAR14, VAR7, VAR8, VAR1, VAR12, VAR10, VAR11, VAR4, VAR13, clk);
parameter VAR9 = 32;
parameter VAR6 = 8;
parameter VAR2 = 160;
input[VAR6-1:0] VAR5;
input VAR14;
input[VAR9-1:0] VAR7;
input VAR8;
output reg[VAR9-1:0] VAR1;
input[VAR6-1:0] VAR12;
input VAR10;
input[VAR9-1:0] VAR11;
input VAR4;
out... | gpl-3.0 |
jmesmon/trifles | verilog/hw6/p18.v | 2,207 | module MODULE1(output reg VAR16, VAR9, VAR17, VAR7, VAR6,
input VAR10, VAR15, VAR8, VAR5, clk);
always @(posedge clk) begin
if (VAR15) begin
VAR9 = 1;
VAR7 = 0;
VAR17 = 0;
VAR6 = 0;
VAR16 = 0;
end else begin
if (VAR8) begin
VAR9 = 0;
VAR7 = 1;
VAR17 = 0;
VAR6 = 0;
VAR16 = 1;
end else if (VAR5) begin
VAR9 = 0;
VAR7 = 0;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3b/sky130_fd_sc_ls__and3b.pp.symbol.v | 1,307 | module MODULE1 (
input VAR3 ,
input VAR6 ,
input VAR1 ,
output VAR7 ,
input VAR4 ,
input VAR2,
input VAR8,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xnor2/sky130_fd_sc_ls__xnor2.behavioral.v | 1,401 | module MODULE1 (
VAR8,
VAR6,
VAR1
);
output VAR8;
input VAR6;
input VAR1;
supply1 VAR7;
supply0 VAR9;
supply1 VAR5 ;
supply0 VAR3 ;
wire VAR4;
xnor VAR10 (VAR4, VAR6, VAR1 );
buf VAR2 (VAR8 , VAR4 );
endmodule | apache-2.0 |
jas0n1ee/THU-DSD | FB/cpu_jtag_debug_module_tck.v | 7,765 | module MODULE1 (
VAR11,
VAR34,
VAR37,
VAR22,
VAR3,
VAR38,
VAR5,
VAR35,
VAR31,
VAR23,
VAR13,
VAR24,
VAR40,
VAR17,
VAR33,
VAR6,
VAR15,
VAR32,
VAR20,
VAR7,
VAR21,
VAR8,
VAR36,
VAR30,
VAR28,
VAR10,
VAR1,
VAR25,
VAR14,
VAR27,
VAR16
)
;
output [ 1: 0] VAR1;
output VAR25;
output [ 37: 0] VAR14;
output VAR27;
output VAR16;
inp... | mit |
queq/uart_tx-v3 | dataSend.v | 1,632 | module MODULE1
parameter VAR6 = 8
)
(
input wire clk, rst, enable,
input wire [13:0] VAR18,
input wire [7:0] VAR12,
output reg VAR2,
output wire VAR9
);
localparam [1:0]
VAR10 = 2'b00,
VAR14 = 2'b01,
VAR1 = 2'b10,
VAR7 = 2'b11;
reg [1:0] VAR4, VAR16;
reg [2:0] VAR15, VAR11;
reg [7:0] VAR8, VAR17;
reg VAR13, VAR3, VAR5;... | mit |
GSejas/Karatsuba_FPU | FPGA_FLOW/Add_Sub/ADD_SUB_PIPELINED/ADD_SUB_FUNCIONAL_v1.srcs/sources_1/imports/Proyecto_De_Graduacion/FPU_FLM/RTL/Add-Subt/Round_Sgf_Dec.v | 1,910 | module MODULE1(
input wire [1:0] VAR1,
input wire [1:0] VAR3,
input wire VAR2,
output reg VAR4
);
always @*
case ({VAR2,VAR3,VAR1})
5'b10101: VAR4 <=1;
5'b10110: VAR4 <=1;
5'b10111: VAR4 <=1;
5'b01001: VAR4 <=1;
5'b01010: VAR4 <=1;
5'b01011: VAR4 <=1;
default: VAR4 <=0;
endcase
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/xor2/sky130_fd_sc_ls__xor2.functional.v | 1,285 | module MODULE1 (
VAR2,
VAR4,
VAR5
);
output VAR2;
input VAR4;
input VAR5;
wire VAR6;
xor VAR3 (VAR6, VAR5, VAR4 );
buf VAR1 (VAR2 , VAR6 );
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_2/zqynq_lab_1_design_auto_pc_2_stub.v | 4,404 | module MODULE1(VAR3, VAR25, VAR4, VAR28,
VAR47, VAR19, VAR33, VAR43, VAR20, VAR37,
VAR24, VAR26, VAR40, VAR39, VAR50, VAR30,
VAR55, VAR13, VAR22, VAR49, VAR51, VAR29,
VAR9, VAR16, VAR41, VAR8, VAR14, VAR23,
VAR17, VAR6, VAR32, VAR27, VAR42, VAR56,
VAR54, VAR2, VAR36, VAR18, VAR5, VAR31,
VAR34, VAR53, VAR1, VAR38, VAR35... | mit |
Dennis-Chhun/Pong-Game | src/VGAInterface.v | 9,682 | module MODULE1(
VAR2,
VAR34,
VAR38,
VAR45,
VAR48,
VAR13,
VAR6,
VAR30,
VAR49,
VAR51,
VAR14,
VAR9,
VAR4,
VAR22,
VAR33,
VAR16,
VAR42,
VAR31,
VAR41,
VAR27,
VAR19,
VAR20,
VAR10
);
input VAR2;
input VAR34;
input VAR38;
output [8:0] VAR45;
output [17:0] VAR48;
input [3:0] VAR13;
input [17:0] VAR6;
output [6:0] VAR30;
output [... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/Aurora_MGT/Pcore/mgt_fifo1_v1_00_a/hdl/verilog/tx_stream.v | 6,151 | module MODULE1
(
VAR16,
VAR1,
VAR9,
VAR8,
VAR14,
VAR18,
VAR11,
VAR20,
VAR19,
VAR3,
VAR10,
VAR12,
VAR6
);
input [0:31] VAR16;
input VAR1;
output VAR9;
input VAR8;
input VAR14;
input VAR18;
output VAR11;
output VAR20;
output [0:1] VAR19;
output [0:1] VAR3;
output [0:31] VAR10;
output VAR12;
input VAR6;
reg VAR12;
reg VAR... | bsd-2-clause |
hanw/sonic-lite | hw/verilog/traffic_controller/avalon_st_mon.v | 14,070 | module MODULE1
(
input clk
,input reset
,input [7:0] VAR32
,input VAR46
,input VAR15
,output wire VAR37
,input [31:0] VAR48
,output reg[31:0] VAR39
,input VAR7
,input VAR14
,input [39:0] VAR42
,input [63:0] VAR61
,input VAR21
,input VAR29
,input VAR24
,input [2:0] VAR52
,input [5:0] VAR50
,output reg VAR4
,input wire V... | mit |
alexforencich/xfcp | lib/eth/rtl/eth_mac_10g.v | 7,533 | module MODULE1 #
(
parameter VAR30 = 64,
parameter VAR7 = (VAR30/8),
parameter VAR4 = (VAR30/8),
parameter VAR1 = 1,
parameter VAR42 = 1,
parameter VAR31 = 64,
parameter VAR2 = 4'h6,
parameter VAR21 = 16'h6666,
parameter VAR28 = 0,
parameter VAR44 = 96,
parameter VAR32 = VAR28,
parameter VAR45 = 16,
parameter VAR43 = 0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand4b/sky130_fd_sc_hs__nand4b.blackbox.v | 1,290 | module MODULE1 (
VAR1 ,
VAR5,
VAR3 ,
VAR7 ,
VAR4
);
output VAR1 ;
input VAR5;
input VAR3 ;
input VAR7 ;
input VAR4 ;
supply1 VAR2;
supply0 VAR6;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_io | cells/in_c/gf180mcu_fd_io__in_c.v | 1,027 | module MODULE1 (VAR1, VAR3, VAR6, VAR7, VAR4, VAR8, VAR2, VAR5);
input VAR1;
input VAR3;
input VAR6;
output VAR7;
inout VAR4;
inout VAR8;
inout VAR2;
inout VAR5;
buf (VAR7, VAR6); | apache-2.0 |
jakubfi/mera400f | src/awp.v | 6,034 | module MODULE1(
input VAR54,
input [0:15] VAR88,
input VAR40,
input VAR3,
input VAR19,
input [7:9] VAR134,
input VAR38,
input VAR132,
input VAR69,
input VAR73,
input VAR45,
input VAR89,
input VAR118,
input VAR110,
input VAR96,
output [0:15] VAR87, output VAR66, output VAR30, output VAR10, output VAR36, output VAR64, ou... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu9t5v0__clkinv_1.behavioral.pp.v | 1,182 | module MODULE1( VAR2, VAR3, VAR1, VAR4 );
input VAR2;
inout VAR1, VAR4;
output VAR3;
VAR7 VAR5(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4));
VAR7 VAR6(.VAR2(VAR2),.VAR3(VAR3),.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
rad-/65C816_SoftCore | 65816_Interface_System.srcs/sources_1/bd/Interface_Master_BD/ip/Interface_Master_BD_xbar_0/synth/Interface_Master_BD_xbar_0.v | 13,323 | module MODULE1 (
VAR11,
VAR109,
VAR58,
VAR91,
VAR32,
VAR76,
VAR12,
VAR40,
VAR112,
VAR61,
VAR82,
VAR97,
VAR123,
VAR98,
VAR30,
VAR75,
VAR96,
VAR1,
VAR48,
VAR62,
VAR125,
VAR13,
VAR128,
VAR60,
VAR108,
VAR103,
VAR53,
VAR4,
VAR39,
VAR119,
VAR117,
VAR92,
VAR7,
VAR107,
VAR115,
VAR36,
VAR66,
VAR100,
VAR68,
VAR37
);
input wire V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlygate4sd3/sky130_fd_sc_ms__dlygate4sd3.behavioral.pp.v | 1,832 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR11,
VAR12,
VAR10 ,
VAR2
);
output VAR1 ;
input VAR5 ;
input VAR11;
input VAR12;
input VAR10 ;
input VAR2 ;
wire VAR3 ;
wire VAR6;
buf VAR7 (VAR3 , VAR5 );
VAR9 VAR8 (VAR6, VAR3, VAR11, VAR12);
buf VAR4 (VAR1 , VAR6 );
endmodule | apache-2.0 |
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