repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
katherinejlu/ece3400 | code dump/Lab3_team1/sin_rom.v | 5,904 | module MODULE1
(
input [7:0] addr,
input clk,
output reg [7:0] VAR2
);
reg [7:0] VAR1[255:0];
begin
begin | mit |
nliu96/openHMC_Altera | src/crc_128_init.v | 25,717 | module MODULE1 (
input wire clk ,
input wire VAR1 ,
input wire [127:0] VAR2 ,
output reg [31:0] VAR3
);
always @(posedge clk or negedge VAR1) else
always @(posedge clk) VAR4
begin
if (!VAR1) begin
VAR3 <= 32'h0;
end
else begin
VAR3[31] <= VAR2[2]^VAR2[5]^VAR2[10]^VAR2[12]^VAR2[13]^VAR2[14]^VAR2[16]^VAR2[17]^VAR2[20]^VA... | lgpl-3.0 |
SymbiFlow/prjxray-experiments-archive-2017 | clb_lut5/top.v | 2,088 | module MODULE2(input clk, VAR14, VAR21, output do);
localparam integer VAR10 = 6;
localparam integer VAR23 = VAR17;
reg [VAR10-1:0] din;
wire [VAR23-1:0] dout;
reg [VAR10-1:0] VAR2;
reg [VAR23-1:0] VAR11;
always @(posedge clk) begin
VAR2 <= {VAR2, VAR21};
VAR11 <= {VAR11, VAR2[VAR10-1]};
if (VAR14) begin
din <= VAR2;
V... | isc |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_uart/rtl/wb_uart.v | 18,980 | module MODULE1 (
input clk,
input rst,
input VAR74,
input VAR48,
input [3:0] VAR4,
input [31:0] VAR46,
input VAR23,
output reg VAR56,
output reg [31:0] VAR34,
input [31:0] VAR57,
output VAR28,
input VAR61,
input VAR51,
output VAR64,
input VAR30,
output VAR53,
output reg VAR81
);
localparam VAR2 = 32'h00000000;
localpar... | mit |
AleCher/ipstack | implementation/ethmac_block.v | 13,509 | module MODULE1
(
VAR66,
VAR77,
VAR51,
VAR45,
VAR6,
VAR3,
VAR69,
VAR27,
VAR47,
VAR34,
VAR32,
VAR73,
VAR38,
VAR40,
VAR17,
VAR55,
VAR65,
VAR42,
VAR35,
VAR53,
VAR71,
VAR59,
VAR64,
VAR2,
VAR72,
VAR56,
VAR4,
VAR46,
VAR22,
VAR7,
VAR54,
VAR15 ,
VAR70
);
output VAR66;
input VAR77;
output [7:0] VAR51;
output VAR45;
output VAR6;
... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/bench/verilog/tst_bench_top.v | 14,591 | module MODULE1();
reg clk;
reg VAR66;
wire [31:0] VAR49;
wire [ 7:0] VAR16, VAR19, VAR53, VAR11;
wire VAR9;
wire VAR59;
wire VAR52;
wire ack;
wire VAR64;
reg [7:0] VAR7, VAR5;
wire VAR1, VAR41, VAR28, VAR3, VAR14;
wire VAR47, VAR27, VAR68, VAR42, VAR51;
parameter VAR60 = 3'b000;
parameter VAR56 = 3'b001;
parameter VAR6... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.behavioral.v | 1,759 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR3,
VAR2
);
output VAR9 ;
input VAR8 ;
input VAR3;
input VAR2;
wire VAR4 ;
wire VAR10;
not VAR6 (VAR4 , VAR8 );
VAR1 VAR5 (VAR10, VAR4, VAR3, VAR2);
buf VAR7 (VAR9 , VAR10 );
endmodule | apache-2.0 |
alexforencich/verilog-ethernet | lib/axis/rtl/axis_rate_limit.v | 8,801 | module MODULE1 #
(
parameter VAR27 = 8,
parameter VAR31 = (VAR27>8),
parameter VAR8 = ((VAR27+7)/8),
parameter VAR14 = 1,
parameter VAR42 = 0,
parameter VAR59 = 8,
parameter VAR36 = 0,
parameter VAR12 = 8,
parameter VAR56 = 1,
parameter VAR45 = 1
)
(
input wire clk,
input wire rst,
input wire [VAR27-1:0] VAR52,
input w... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o.symbol.v | 1,367 | module MODULE1 (
input VAR4,
input VAR5,
input VAR2,
input VAR6,
output VAR9
);
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms1/kc705/system_top.v | 10,892 | module MODULE1 (
VAR113,
VAR27,
VAR73,
VAR97,
VAR94,
VAR18,
VAR50,
VAR56,
VAR11,
VAR93,
VAR130,
VAR22,
VAR46,
VAR17,
VAR8,
VAR41,
VAR138,
VAR61,
VAR78,
VAR40,
VAR125,
VAR10,
VAR51,
VAR108,
VAR60,
VAR104,
VAR6,
VAR135,
VAR88,
VAR76,
VAR75,
VAR12,
VAR131,
VAR140,
VAR44,
VAR13,
VAR123,
VAR128,
VAR32,
VAR62,
VAR54,
VAR48,
... | gpl-3.0 |
zhaishaomin/ring_network-based-multicore- | core/core_ex_mem.v | 3,126 | module MODULE1( clk,
rst,
VAR8,
VAR20,
VAR6,
VAR13,
VAR21,
VAR10,
VAR4,
VAR14,
VAR3,
VAR18,
VAR2,
VAR17,
VAR1,
VAR12,
VAR9,
VAR15,
VAR5,
VAR19,
VAR16,
VAR11,
VAR22,
VAR7
);
input clk;
input rst;
input VAR8;
input VAR20;
input VAR6;
input VAR13;
input VAR21;
input VAR10;
input VAR4;
input VAR14;
input [31:0] VAR3;
input... | apache-2.0 |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/syn/verilog/ANN_fdiv_32ns_32ns_32_16.v | 1,903 | module MODULE1
VAR27 = 2,
VAR18 = 16,
VAR16 = 32,
VAR10 = 32,
VAR3 = 32
)(
input wire clk,
input wire reset,
input wire VAR1,
input wire [VAR16-1:0] VAR6,
input wire [VAR10-1:0] VAR19,
output wire [VAR3-1:0] dout
);
wire VAR13;
wire VAR17;
wire VAR23;
wire [31:0] VAR25;
wire VAR11;
wire [31:0] VAR12;
wire VAR14;
wire [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb_1.v | 2,325 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR5 ,
VAR10 ,
VAR9 ,
VAR3,
VAR11,
VAR2 ,
VAR6
);
output VAR7 ;
input VAR1 ;
input VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR3;
input VAR11;
input VAR2 ;
input VAR6 ;
VAR8 VAR4 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR2(VAR2),
.... | apache-2.0 |
genkilife/miaow | src/verilog/rtl/decode/decode.v | 12,979 | module MODULE1(
VAR106,
VAR93,
VAR91,
VAR18,
VAR137,
VAR35,
VAR14,
VAR78,
VAR38,
VAR58,
VAR120,
VAR163,
VAR88,
VAR72,
VAR54,
VAR65,
VAR124,
VAR152,
VAR7,
VAR56,
VAR103,
VAR6,
VAR76,
VAR25,
VAR151,
VAR111,
VAR162,
VAR3,
VAR145,
VAR127,
VAR67,
VAR26,
VAR148,
VAR147,
VAR171,
VAR28,
VAR157,
clk,
rst
);
input clk;
input rst... | bsd-3-clause |
olajep/oh | src/adi/hdl/library/axi_dmac/dest_fifo_inf.v | 3,910 | module MODULE1 #(
parameter VAR4 = 3,
parameter VAR7 = 64,
parameter VAR23 = 4)(
input clk,
input VAR33,
input enable,
output VAR17,
input VAR21,
output VAR11,
output [VAR4-1:0] VAR29,
output reg [VAR4-1:0] VAR19 = 'h0,
input VAR25,
input VAR13,
input en,
output reg [VAR7-1:0] dout,
output reg valid,
output reg VAR5,
o... | mit |
GSejas/Aproximate-Arithmetic-Operators | add_approx_flow/integracion_fisica/front_end/db/SINGLE/Approx_adder_GeArN8R4P1_syn.v | 7,066 | module MODULE1 ( VAR133, VAR201, VAR150, VAR185 );
input [15:0] VAR201;
input [15:0] VAR150;
output [16:0] VAR185;
input VAR133;
wire VAR242, VAR153, VAR240, VAR194, VAR39, VAR172, VAR94, VAR63,
VAR128, VAR36, VAR171, VAR105, VAR35, VAR79, VAR54, VAR33, VAR7, VAR217,
VAR67, VAR10, VAR117, VAR137, VAR18, VAR167, VAR237,... | apache-2.0 |
Apo45ty/ArquiCourseCPUVerilog | VerilogSource/EmbededSystem/ARM_ALU.v | 2,363 | module MODULE1(input wire [31:0] VAR8,VAR2,input wire[4:0] VAR5,input wire [3:0] VAR3,output wire [31:0] VAR4,output wire [3:0] VAR9, input wire VAR11,VAR1);
parameter VAR6 = 32'VAR7;
reg [31:0] buffer,VAR8,VAR2;
reg [3:0] VAR10;
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin
begin | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.behavioral.v | 1,676 | module MODULE1 (
VAR9 ,
VAR11,
VAR14,
VAR4,
VAR15,
VAR13
);
output VAR9 ;
input VAR11;
input VAR14;
input VAR4;
input VAR15;
input VAR13;
supply1 VAR1;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR10 ;
wire VAR17 ;
wire VAR5 ;
wire VAR12;
and VAR7 (VAR17 , VAR4, VAR11, VAR14 );
and VAR3 (VAR5 , VAR15, VAR13 );
or VAR16 (VAR... | apache-2.0 |
housq/lc3 | LC3_RAMblock.v | 1,687 | module MODULE1(
input [15 : 0] VAR4,
input [15 : 0] VAR6,
input clk,
input VAR5,
output [15 : 0] VAR1
);
reg [15:0] VAR2 [65535:0];
VAR3 VAR2[16'h002]=16'h700;
VAR3 VAR2[16'h180]=16'h200;
VAR3 VAR2[16'h200]=16'b0010000000000001; VAR3 VAR2[16'h201]=16'b1100000000000000; VAR3 VAR2[16'h202]=16'h203;
VAR3 VAR2[16'h203]=16'... | gpl-2.0 |
HighlandersFRC/fpga | oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_ddrc.v | 6,230 | module MODULE1(
VAR100,
VAR26,
VAR87,
VAR16,
VAR76,
VAR69,
VAR8,
VAR89,
VAR66,
VAR106,
VAR77,
VAR70,
VAR107,
VAR85,
VAR13,
VAR63,
VAR84,
VAR18,
VAR68,
VAR27,
VAR44,
VAR91,
VAR24,
VAR52,
VAR103,
VAR88,
VAR102,
VAR11,
VAR14,
VAR49,
VAR81,
VAR41,
VAR93,
VAR23,
VAR96,
VAR108,
VAR58,
VAR35,
VAR38,
VAR109,
VAR104,
VAR72,
VAR... | mit |
alan4186/ParCNN | DE2_115_CAMERA/v/Reset_Delay.v | 2,411 | module MODULE1(VAR1,VAR5,VAR6,VAR2,VAR7,VAR8,VAR3);
input VAR1;
input VAR5;
output reg VAR6;
output reg VAR2;
output reg VAR7;
output reg VAR8;
output reg VAR3;
reg [31:0] VAR4;
always@(posedge VAR1 or negedge VAR5)
begin
if(!VAR5)
begin
VAR4 <= 0;
VAR6 <= 0;
VAR2 <= 0;
VAR7 <= 0;
VAR8 <= 0;
VAR3 <= 0;
end
else
begin
i... | mit |
dachdecker2/icoboard_ws2812b_display | ws2812b_out.v | 3,830 | module MODULE1 (
input clk,
input VAR7,
input VAR6,
input [23:0] VAR14,
output reg VAR13,
output reg VAR4,
output reg [3:0] VAR8
);
parameter VAR3 = 3; parameter VAR1 = 5; parameter VAR9 = 450;
localparam VAR2 = VAR5(VAR9 > VAR1 ? VAR9
: VAR1);
reg [4:0] VAR11 = 0; reg [VAR2-1:0] counter = 0; reg [23:0] VAR10;
reg [0:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21ba/sky130_fd_sc_hs__o21ba_4.v | 2,189 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR4 ,
VAR1,
VAR2,
VAR6
);
output VAR3 ;
input VAR7 ;
input VAR4 ;
input VAR1;
input VAR2;
input VAR6;
VAR5 VAR8 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR3 ,
VAR7 ,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR4 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211a/sky130_fd_sc_ls__o211a.pp.symbol.v | 1,372 | module MODULE1 (
input VAR6 ,
input VAR8 ,
input VAR1 ,
input VAR7 ,
output VAR4 ,
input VAR9 ,
input VAR3,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu9t5v0__dlyd_2.behavioral.v | 1,098 | module MODULE1( VAR3, VAR1 );
input VAR3;
output VAR1;
VAR5 VAR4(.VAR3(VAR3),.VAR1(VAR1));
VAR5 VAR2(.VAR3(VAR3),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi_1.v | 2,542 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR6 ,
VAR13 ,
VAR7 ,
VAR10 ,
VAR9 ,
VAR2,
VAR12,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR4 ;
input VAR6 ;
input VAR13 ;
input VAR7 ;
input VAR10 ;
input VAR9 ;
input VAR2;
input VAR12;
input VAR5 ;
input VAR3 ;
VAR8 VAR11 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR13(VAR13),
.VAR7(VAR7),... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffsnq/gf180mcu_fd_sc_mcu7t5v0__dffsnq_1.behavioral.pp.v | 3,792 | module MODULE1( VAR25, VAR26, VAR32, VAR31, VAR5, VAR15 );
input VAR25, VAR26, VAR32;
inout VAR5, VAR15;
output VAR31;
reg VAR14;
VAR17 VAR4(.VAR25(VAR25),.VAR26(VAR26),.VAR32(VAR32),.VAR31(VAR31),.VAR5(VAR5),.VAR15(VAR15),.VAR14(VAR14));
VAR17 VAR7(.VAR25(VAR25),.VAR26(VAR26),.VAR32(VAR32),.VAR31(VAR31),.VAR5(VAR5),.V... | apache-2.0 |
walkthetalk/fsref | ip/intr_filter/src/intr_filter.v | 2,082 | module MODULE1 #
(
parameter integer VAR10 = 8,
parameter integer VAR22 = 8
) (
input clk,
input VAR18,
input wire VAR15,
input wire VAR6,
input wire VAR5,
input wire VAR20,
input wire VAR9,
input wire VAR21,
input wire VAR19,
input wire VAR2,
output wire VAR1,
output wire VAR12,
output wire VAR8,
output wire VAR14,
ou... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/sequencer_scc_sv_phase_decode.v | 3,939 | module MODULE1
VAR5 = 32,
VAR1 = 6
)
(
VAR7,
VAR3,
VAR6,
VAR2,
VAR4
);
input [VAR5 - 1:0] VAR7;
output [2:0] VAR3;
output [6:0] VAR6;
output [6:0] VAR2;
output [5:0] VAR4;
reg [2:0] VAR3;
reg [6:0] VAR6;
reg [6:0] VAR2;
reg [5:0] VAR4;
always @ (*) begin
VAR3 = 3'b010;
VAR6 = 7'b1110110;
VAR2 = 7'b0110100;
VAR4 = 6'b00... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand4b/sky130_fd_sc_ms__nand4b_4.v | 2,311 | module MODULE2 (
VAR1 ,
VAR10 ,
VAR2 ,
VAR3 ,
VAR4 ,
VAR8,
VAR9,
VAR5 ,
VAR11
);
output VAR1 ;
input VAR10 ;
input VAR2 ;
input VAR3 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR5 ;
input VAR11 ;
VAR6 VAR7 (
.VAR1(VAR1),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR5(VAR5),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi_4.v | 2,361 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR1 ,
VAR9 ,
VAR7 ,
VAR8,
VAR2,
VAR6 ,
VAR3
);
output VAR4 ;
input VAR5 ;
input VAR1 ;
input VAR9 ;
input VAR7 ;
input VAR8;
input VAR2;
input VAR6 ;
input VAR3 ;
VAR11 VAR10 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR3(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3/sky130_fd_sc_ls__nor3.pp.blackbox.v | 1,321 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR1 ,
VAR8,
VAR4,
VAR2 ,
VAR7
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR1 ;
input VAR8;
input VAR4;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtp/sky130_fd_sc_hs__dlrtp_1.v | 2,220 | module MODULE2 (
VAR2,
VAR6 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR5
);
input VAR2;
input VAR6 ;
input VAR4 ;
output VAR1 ;
input VAR3 ;
input VAR5 ;
VAR7 VAR8 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR2,
VAR6 ,
VAR4 ,
VAR1
);
input VAR2;
input VAR6 ;
input VAR4 ... | apache-2.0 |
olgirard/openmsp430 | core/synthesis/actel/src/omsp_mem_backbone.v | 11,019 | module MODULE1 (
VAR1, VAR13, VAR29, VAR32, VAR49, VAR21, VAR28, VAR17, VAR26, VAR48, VAR56, VAR25, VAR40, VAR5, VAR18, VAR31,
VAR15, VAR20, VAR14, VAR38, VAR27, VAR52, VAR3, VAR16, VAR57, VAR53, VAR11, VAR8, VAR6, VAR43, VAR10, VAR7 );
output [15:0] VAR1; output [VAR37:0] VAR13; output VAR29; output [15:0] VAR32; outp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv5sd1/sky130_fd_sc_ms__clkdlyinv5sd1.pp.blackbox.v | 1,344 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR1,
VAR4,
VAR3 ,
VAR5
);
output VAR6 ;
input VAR2 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_auto_pc_0/synth/led_controller_design_auto_pc_0.v | 14,732 | module MODULE1 (
VAR28,
VAR5,
VAR37,
VAR93,
VAR21,
VAR40,
VAR16,
VAR24,
VAR114,
VAR98,
VAR49,
VAR8,
VAR96,
VAR45,
VAR58,
VAR104,
VAR43,
VAR68,
VAR31,
VAR94,
VAR42,
VAR79,
VAR18,
VAR20,
VAR71,
VAR72,
VAR50,
VAR76,
VAR108,
VAR53,
VAR54,
VAR2,
VAR78,
VAR6,
VAR47,
VAR84,
VAR102,
VAR26,
VAR44,
VAR10,
VAR4,
VAR67,
VAR3,
VAR9... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22o/sky130_fd_sc_lp__a22o_4.v | 2,339 | module MODULE2 (
VAR9 ,
VAR2 ,
VAR7 ,
VAR6 ,
VAR1 ,
VAR5,
VAR11,
VAR3 ,
VAR8
);
output VAR9 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR1 ;
input VAR5;
input VAR11;
input VAR3 ;
input VAR8 ;
VAR10 VAR4 (
.VAR9(VAR9),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR... | apache-2.0 |
gitpan/Verilog-Perl | verilog/parser_sv.v | 9,415 | package VAR10;
bit [7:0] VAR30;
bit [7:0] VAR35;
endpackage
module MODULE7 ();
VAR14 VAR42;
VAR38 VAR42 = 33ns; endmodule : MODULE7
interface VAR33 #(parameter VAR43 = 0);
logic VAR32;
logic [7:0] addr, VAR26[9];
modport VAR1(input VAR26, VAR21, output addr);
endinterface : VAR33
module MODULE8 (
VAR33 VAR13,
VAR33.MOD... | artistic-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp.behavioral.pp.v | 2,529 | module MODULE1 (
VAR25,
VAR15 ,
VAR19,
VAR11 ,
VAR14,
VAR21,
VAR10 ,
VAR4
);
output VAR25;
input VAR15 ;
input VAR19;
input VAR11 ;
input VAR14;
input VAR21;
input VAR10 ;
input VAR4 ;
wire VAR13 ;
wire VAR7 ;
wire VAR23 ;
wire VAR17 ;
wire VAR16 ;
wire VAR18 ;
wire VAR6;
reg VAR1 ;
wire VAR22 ;
wire VAR8 ;
wire VAR9 ;... | apache-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/Key_Synchronizer_Module.v | 2,689 | module MODULE1
parameter VAR17 = 50000000, parameter VAR10 = 800000000 )
(
input VAR6,
output reg VAR5,
input VAR12
);
wire VAR13;
VAR9
.VAR2( 2 )
)
VAR11
(
.VAR14( ~VAR6 ),
.VAR3( VAR13 ),
.VAR12( VAR12 )
);
localparam VAR15 = (1.0 * VAR10) / (1000000000.0 / VAR17);
localparam VAR8 = VAR7(VAR15);
localparam [VAR8:0] V... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_Electrical_Velocity_To_Position.v | 2,682 | module MODULE1
(
VAR10,
reset,
VAR16,
VAR4,
VAR3,
VAR7
);
input VAR10;
input reset;
input VAR16;
input VAR4;
input signed [17:0] VAR3; output signed [17:0] VAR7;
wire signed [35:0] VAR2; wire signed [31:0] VAR11; wire signed [31:0] VAR18; wire signed [31:0] VAR12; wire signed [31:0] VAR14; wire signed [17:0] VAR17;
ass... | gpl-3.0 |
hoglet67/CoPro6502 | src/LX9Co_CoPro32016.v | 12,835 | module MODULE1 (
input VAR67,
input [3:0] VAR50,
input VAR102,
input [2:0] VAR95,
inout [7:0] VAR8,
input VAR59,
input VAR45,
input VAR38,
output VAR75,
output reg VAR40,
output reg VAR56,
output reg VAR10,
output reg VAR96,
output reg VAR89,
output reg [18:0] VAR86,
inout [31:0] VAR3
);
wire clk;
wire VAR20;
reg VAR5... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32o/sky130_fd_sc_ls__a32o.symbol.v | 1,424 | module MODULE1 (
input VAR7,
input VAR9,
input VAR3,
input VAR4,
input VAR10,
output VAR2
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21bai/sky130_fd_sc_hs__o21bai.pp.blackbox.v | 1,345 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR2,
VAR1,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR2;
input VAR1;
input VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/inv/sky130_fd_sc_hdll__inv.blackbox.v | 1,212 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR5;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_tt.v | 7,571 | module MODULE1(
clk, rst, VAR10,
VAR14, VAR2, VAR7, VAR21, VAR16,
VAR18
);
input clk; input rst; input VAR10; input VAR14; input VAR2; input [31:0] VAR7; input [31:0] VAR21; output [31:0] VAR16; output VAR18;
reg [31:0] VAR17; else
wire [31:0] VAR17; VAR19
reg [31:0] VAR6; else
wire [31:0] VAR6; VAR19
wire VAR9; wire V... | gpl-3.0 |
rkrajnc/minimig-mist | rtl/minimig/cia_timera.v | 3,204 | module MODULE1
(
input clk, input VAR6,
input wr, input reset, input VAR1, input VAR15, input VAR14, input [7:0] VAR11, output [7:0] VAR2, input VAR21, output VAR5, output VAR18, output irq );
reg [15:0] VAR4; reg [7:0] VAR17; reg [7:0] VAR3; reg [6:0] VAR9; reg VAR8; wire VAR7; wire VAR16; reg VAR13; wire VAR12; wire ... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAM16_s36_s36_altera.v | 10,991 | module MODULE1 (
VAR35,
VAR30,
VAR49,
VAR4,
VAR58,
VAR36,
VAR14,
VAR18,
VAR52,
VAR1);
input [9:0] VAR35;
input [9:0] VAR30;
input VAR49;
input VAR4;
input [31:0] VAR58;
input [31:0] VAR36;
input VAR14;
input VAR18;
output [31:0] VAR52;
output [31:0] VAR1;
tri1 VAR49;
tri0 VAR14;
tri0 VAR18;
wire [31:0] VAR5;
wire [31:0... | mit |
shailcoolboy/Warp-Trinity | PlatformSupport/CustomPeripherals/pcores/radio_controller_v1_21_a/hdl/verilog/user_logic.v | 37,011 | module MODULE1
(
VAR16,
VAR72,
VAR17,
VAR195,
VAR191,
VAR105,
VAR154,
VAR217,
VAR221,
VAR65,
VAR187,
VAR88,
VAR80,
VAR197,
VAR110,
VAR24,
VAR140,
VAR61,
VAR168,
VAR38,
VAR229,
VAR18,
VAR206,
VAR172,
VAR131,
VAR115,
VAR78,
VAR212,
VAR26,
VAR146,
VAR145,
VAR35,
VAR133,
VAR83,
VAR139,
VAR52,
VAR22,
VAR188,
VAR164,
VAR122,... | bsd-2-clause |
CospanDesign/nysa-verilog | verilog/wishbone/slave/wb_fpga_nes/rtl/cpu/cpu.v | 85,520 | module MODULE1 (
input wire VAR275, input wire VAR332, input wire VAR50,
input wire VAR346, input wire VAR286, input wire VAR109,
input wire [ 7:0] din, output wire [ 7:0] dout, output wire [15:0] VAR226, output reg VAR290,
input wire [ 3:0] VAR129, input wire [ 7:0] VAR221, input wire VAR203, output reg [ 7:0] VAR187,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlclkp/sky130_fd_sc_lp__dlclkp.pp.symbol.v | 1,270 | module MODULE1 (
input VAR6 ,
input VAR7,
output VAR4,
input VAR5 ,
input VAR3,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xnor2/sky130_fd_sc_lp__xnor2.functional.pp.v | 1,827 | module MODULE1 (
VAR5 ,
VAR12 ,
VAR13 ,
VAR1,
VAR4,
VAR10 ,
VAR7
);
output VAR5 ;
input VAR12 ;
input VAR13 ;
input VAR1;
input VAR4;
input VAR10 ;
input VAR7 ;
wire VAR6 ;
wire VAR8;
xnor VAR9 (VAR6 , VAR12, VAR13 );
VAR3 VAR11 (VAR8, VAR6, VAR1, VAR4);
buf VAR2 (VAR5 , VAR8 );
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/ddr3_s4_amphy_ex_lfsr8.v | 1,402 | module MODULE1 (
clk, VAR4, enable, VAR3, VAR6, VAR7, VAR1);
parameter VAR5 = 32;
input clk;
input VAR4;
input enable;
input VAR3;
input VAR6;
output[8 - 1:0] VAR7;
wire[8 - 1:0] VAR7;
input[8 - 1:0] VAR1;
reg[8 - 1:0] VAR2;
assign VAR7 = VAR2 ;
always @(posedge clk or negedge VAR4)
begin
if (!VAR4)
begin
VAR2 <= VAR5[... | lgpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/bench/verilog/dbg_comm.v | 6,171 | module MODULE1(VAR9, VAR4, VAR1, VAR10, VAR2);
parameter VAR3 = 1;
output VAR9;
output VAR4;
output VAR1;
output VAR10;
input VAR2;
integer VAR13, VAR12;
reg [4:0] memory[0:0];
reg VAR15;
reg VAR7;
reg VAR6;
reg VAR8;
wire VAR4;
wire VAR1;
wire VAR10;
wire VAR9;
wire VAR2;
reg [3:0] VAR11;
wire [4:0] VAR5;
wire [3:0] V... | gpl-3.0 |
comododragon/SHA256_FPGA | Full/Quartus/TOP.v | 4,177 | module MODULE1(
VAR41,
VAR40,
VAR24,
VAR34,
VAR7,
VAR36
);
input VAR41;
input [4:1] VAR40;
output [8:1] VAR24;
input VAR34;
input VAR7;
output VAR36;
wire [255:0] VAR46;
wire [255:0] VAR16;
wire VAR12;
wire VAR14;
wire VAR6;
wire VAR20;
wire VAR38;
wire [511:0] VAR37;
wire [255:0] VAR2;
wire [1:0] VAR43;
assign VAR24 =... | mit |
osrf/wandrr | firmware/motor_controller/fpga/usb_rx_nrzi.v | 3,002 | module MODULE1
(input VAR34,
input VAR1,
input VAR28,
input VAR27,
output VAR5,
output VAR14,
output VAR23);
localparam VAR3 = 2'b10;
localparam VAR17 = 2'b01;
localparam VAR25 = 2'b00;
wire [1:0] VAR10;
sync #(2) VAR22(.in({VAR1, VAR28}), .clk(VAR34), .out(VAR10));
localparam VAR26 = 4'd0;
localparam VAR24 = 4'd1;
loc... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor4bb/sky130_fd_sc_hdll__nor4bb.behavioral.v | 1,531 | module MODULE1 (
VAR3 ,
VAR9 ,
VAR5 ,
VAR10,
VAR13
);
output VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR10;
input VAR13;
supply1 VAR7;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR11 ;
wire VAR2 ;
wire VAR14;
nor VAR12 (VAR2 , VAR9, VAR5 );
and VAR8 (VAR14, VAR2, VAR10, VAR13);
buf VAR6 (VAR3 , VAR14 );
endmodule | apache-2.0 |
olgirard/opengfx430 | core/rtl/verilog/ogfx_gpu_reg.v | 29,923 | module MODULE1 (
VAR16, VAR73, VAR7, VAR86, VAR57, VAR107, VAR52, VAR131, VAR62, VAR69, VAR18, VAR17, VAR99,
VAR116, VAR105, VAR123,
VAR88, VAR23, VAR28, VAR33,
VAR97, VAR24,
VAR98, VAR41, VAR49, VAR56,
VAR83 );
output [VAR36:0] VAR16; output VAR73; output VAR7; output VAR86; output [15:0] VAR57; output [3:0] VAR107; o... | bsd-3-clause |
rhalstea/cidr_15_fpga_join | probe_engine/verilog/hash_function.v | 1,424 | module MODULE1 (
input clk,
input rst,
input VAR2,
input [63:0] VAR10,
output VAR3,
output [63:0] VAR9
);
wire [47:0] VAR12 = 48'h00001E698F65;
wire [47:0] VAR16 = 48'h000024820C8D;
wire [47:0] VAR14;
wire [47:0] VAR1;
wire [47:0] VAR5;
wire [47:0] VAR15;
wire [47:0] VAR11;
reg VAR18;
assign VAR14 = {16'd0, VAR10[63:32... | bsd-3-clause |
P3Stor/P3Stor | pcie/core/sync_fifo.v | 8,446 | module MODULE1
parameter VAR12 = 32,
parameter VAR3 = 16,
parameter VAR17 = "VAR6", parameter VAR15 = VAR3-1,
parameter VAR14 = 1,
parameter VAR2 = (VAR3<=2) ? 1:
(VAR3<=4) ? 2:
(VAR3<=8) ? 3:
(VAR3<=16) ? 4:
(VAR3<=32) ? 5:
(VAR3<=64) ? 6:
(VAR3<=128) ? 7:
(VAR3<=256) ? 8:
(VAR3<=512) ? 9:
(VAR3<=1024) ?10:
(VAR3<=204... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/sdlxtp/sky130_fd_sc_hvl__sdlxtp_1.v | 2,321 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR5 ,
VAR11 ,
VAR9,
VAR10,
VAR8,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR7 ;
input VAR5 ;
input VAR11 ;
input VAR9;
input VAR10;
input VAR8;
input VAR4 ;
input VAR1 ;
VAR6 VAR2 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR4(VAR4),
.VA... | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/radio_controller_v1_00_a/hdl/verilog/user_logic.v | 10,524 | module MODULE1
(
VAR37, VAR2, VAR15, VAR19, VAR11, VAR21, VAR25, VAR7, VAR39, VAR13, VAR22, VAR24, VAR33,
VAR4,
VAR30,
VAR3,
VAR8, VAR29, VAR5, VAR35, VAR17, VAR1, VAR14, VAR31, VAR26, VAR28, VAR27 );
parameter VAR16 = 32;
parameter VAR9 = 1;
output VAR37;
output VAR2;
output VAR15;
output VAR19;
output VAR11;
output V... | bsd-2-clause |
laoreja/MineSweeperM | code/vga_bsprite.v | 2,312 | module MODULE1(
input wire VAR22,
input wire [9:0]hc,
input wire [9:0]VAR18,
input wire [7:0]VAR17,
input wire [3:0]VAR11,
input wire [3:0]VAR7,
input wire [7:0]VAR12,
output wire [9:0]VAR13,
output wire [7:0]VAR24,
output reg[2:0]VAR19,
output reg[2:0]VAR14,
output reg[1:0]VAR21,
output wire [3:0]VAR23,
output wire [3... | gpl-3.0 |
ncos/Xilinx-Verilog | Donov-I/toplevel_pl.v | 1,490 | module MODULE1(
output reg [7:0] VAR19,
output reg [7:0] VAR18,
inout [7:0] VAR7,
inout [7:0] VAR5,
output reg [7:0] VAR3,
input [7:0] VAR12,
input VAR13,
input VAR8,
input VAR23,
input VAR9,
input VAR17,
input VAR24
);
wire clk;
VAR10 VAR20 (
.VAR15(VAR24),
.VAR21(clk),
.VAR22(8'd15)
);
reg [7:0] VAR1;
wire [7:0] VAR1... | mit |
iori-yja/ball_detector | sram_bb.v | 7,454 | module MODULE1 (
VAR1,
VAR4,
VAR3,
VAR6,
VAR2,
VAR5);
input VAR1;
input [15:0] VAR4;
input [11:0] VAR3;
input [11:0] VAR6;
input VAR2;
output [15:0] VAR5;
tri1 VAR1;
tri0 VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp.functional.v | 2,054 | module MODULE1 (
VAR14 ,
VAR10 ,
VAR17 ,
VAR9 ,
VAR5 ,
VAR13 ,
VAR7 ,
VAR4
);
input VAR14 ;
input VAR10 ;
output VAR17 ;
input VAR9 ;
input VAR5 ;
input VAR13 ;
input VAR7 ;
input VAR4;
wire VAR16 ;
wire VAR12 ;
wire VAR11;
not VAR18 (VAR12 , VAR4 );
VAR1 VAR8 (VAR11, VAR5, VAR13, VAR7 );
VAR3 VAR6 VAR2 (VAR16 , VAR11,... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/ad9265_fmc/common/ad9265_spi.v | 3,579 | module MODULE1 (
VAR6,
VAR2,
VAR10,
VAR9,
VAR5);
input [ 1:0] VAR6;
input VAR2;
input VAR10;
output VAR9;
inout VAR5;
reg [ 5:0] VAR8 = 'd0;
reg VAR1 = 'd0;
reg VAR11 = 'd0;
wire VAR4;
wire VAR7;
assign VAR4 = & VAR6;
assign VAR7 = VAR11 & ~VAR4;
always @(posedge VAR2 or posedge VAR4) begin
if (VAR4 == 1'b1) begin
VAR8... | gpl-3.0 |
ruishihan/R7-with-notes | src/rtl/AXI2S.v | 4,911 | module MODULE1
(
rst,
VAR76,
VAR16,
VAR78,
VAR35,
VAR12,
sync,
VAR44,
VAR42,
VAR52,
VAR49,
VAR63,
VAR55,
VAR30,
VAR15,
VAR31,
VAR69,
VAR56,
VAR29,
VAR67,
VAR48,
VAR62,
VAR39,
VAR20,
VAR19,
VAR8,
VAR43,
VAR37,
VAR27,
VAR25,
VAR45,
VAR11,
VAR50,
VAR71,
VAR3,
VAR36,
VAR46,
VAR22,
VAR7,
VAR68,
VAR79,
VAR23,
VAR13,
VAR2,
VA... | apache-2.0 |
wyvernSemi/lm32fpga | HDL/rtl/Sdram_Controller/Sdram_Controller.v | 8,864 | module MODULE1(
VAR25,
VAR16,
VAR58,
VAR59,
VAR74,
VAR13,
VAR38,
VAR14,
VAR68,
VAR29,
VAR55,
VAR56,
VAR22,
VAR19,
VAR1,
VAR65,
VAR44,
VAR54,
VAR67,
VAR10,
VAR61,
VAR47,
VAR5
);
input VAR25; input VAR16; input VAR58; input [VAR34-1:0] VAR59; input VAR74; input VAR13; input [7:0] VAR38; output VAR14; output VAR68; input ... | gpl-3.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/xilinx_ddr2/xilinx_ddr2.v | 10,666 | module MODULE1
(
input [31:0] VAR126,
input [1:0] VAR33,
input [2:0] VAR49,
input VAR167,
input [31:0] VAR149,
input [3:0] VAR47,
input VAR12,
input VAR2,
output VAR76,
output VAR101,
output VAR93,
output [31:0] VAR29,
input [31:0] VAR130,
input [1:0] VAR151,
input [2:0] VAR98,
input VAR118,
input [31:0] VAR67,
input [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd2/sky130_fd_sc_hd__tapvgnd2.blackbox.v | 1,256 | module MODULE1 ();
supply1 VAR1;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi211/gf180mcu_fd_sc_mcu9t5v0__aoi211_4.behavioral.pp.v | 1,868 | module MODULE1( VAR10, VAR8, VAR3, VAR1, VAR9, VAR6, VAR5 );
input VAR3, VAR8, VAR1, VAR9;
inout VAR6, VAR5;
output VAR10;
VAR4 VAR7(.VAR10(VAR10),.VAR8(VAR8),.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR6(VAR6),.VAR5(VAR5));
VAR4 VAR2(.VAR10(VAR10),.VAR8(VAR8),.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR6(VAR6),.VAR5(VAR5)); | apache-2.0 |
asicguy/gplgpu | hdl/vga/ram_32x32_dp.v | 2,315 | module MODULE1
(
input VAR1,
input VAR6,
input [4:0] VAR5,
input [31:0] VAR7,
input VAR4,
input [4:0] VAR8,
output reg [31:0] VAR2
);
reg [31:0] VAR3 [0:31];
always @(posedge VAR1) if(VAR6) VAR3[VAR5] <= VAR7;
always @(posedge VAR4) VAR2 <= VAR3[VAR8];
endmodule | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_v6_gtx_x4_250/source/pcie_brams_v6.v | 8,424 | module MODULE1
parameter VAR14 = 0,
parameter VAR2 = 1,
parameter VAR12 = 1,
parameter VAR1 = 1,
parameter VAR3 = 1
)
(
input VAR13,
input VAR11,
input VAR10,
input [12:0] VAR5,
input [71:0] VAR16,
input VAR4,
input VAR9,
input [12:0] VAR15,
output [71:0] VAR8
);
localparam VAR7 = (VAR12 > 1) ? 1 : 0;
localparam [6:0] ... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211a/sky130_fd_sc_hdll__o211a.behavioral.v | 1,550 | module MODULE1 (
VAR13 ,
VAR3,
VAR8,
VAR4,
VAR1
);
output VAR13 ;
input VAR3;
input VAR8;
input VAR4;
input VAR1;
supply1 VAR5;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR14 ;
wire VAR7 ;
wire VAR10;
or VAR6 (VAR7 , VAR8, VAR3 );
and VAR11 (VAR10, VAR7, VAR4, VAR1);
buf VAR12 (VAR13 , VAR10 );
endmodule | apache-2.0 |
azonenberg/antikernel-ipcores | clock/crossing/SwitchDebouncerBlock.v | 3,996 | module MODULE1 #(
parameter VAR4 = 4,
parameter VAR5 = 0
) (
input wire clk,
input wire[VAR4-1:0] din,
output wire[VAR4-1:0] dout,
output wire[VAR4-1:0] VAR3,
output wire[VAR4-1:0] VAR2
);
genvar VAR6;
generate
for(VAR6=0; VAR6<VAR4; VAR6 = VAR6+1) begin: VAR8
VAR7 #(
.VAR5(VAR5[VAR6])
) VAR1 (
.clk(clk),
.din(din[VAR6... | bsd-3-clause |
Blunk-electronic/M-1 | HW/ise/executor_mini/src/executor.v | 132,671 | module MODULE1(
VAR73, clk, VAR103,
VAR223, VAR169, VAR74,
VAR65, VAR108,
VAR174,
VAR62,
VAR128, VAR186,
VAR236,
VAR122, VAR252, VAR216, VAR143, VAR68,
VAR3, VAR12,
VAR59, VAR209, VAR145,
VAR144, VAR241, VAR63, VAR58,
VAR99, VAR228, VAR26, VAR155, VAR201,
VAR135, VAR166, VAR78,
VAR117, VAR191, VAR150, VAR230, VAR162,
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a222oi/sky130_fd_sc_ls__a222oi.functional.pp.v | 2,413 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR15 ,
VAR17 ,
VAR23 ,
VAR11 ,
VAR19 ,
VAR5,
VAR13,
VAR4 ,
VAR14
);
output VAR2 ;
input VAR1 ;
input VAR15 ;
input VAR17 ;
input VAR23 ;
input VAR11 ;
input VAR19 ;
input VAR5;
input VAR13;
input VAR4 ;
input VAR14 ;
wire VAR8 ;
wire VAR6 ;
wire VAR10 ;
wire VAR22 ;
wire VAR21;
nand VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21o/sky130_fd_sc_ms__a21o.symbol.v | 1,341 | module MODULE1 (
input VAR3,
input VAR6,
input VAR5,
output VAR4
);
supply1 VAR1;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buflp/sky130_fd_sc_lp__buflp_1.v | 2,024 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR1,
VAR5,
VAR7 ,
VAR6
);
output VAR3 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR7 ;
input VAR6 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR1;
supply0 VAR5;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb_1.v | 1,915 | module MODULE2 (
VAR5 ,
VAR2 ,
VAR4,
VAR3
);
output VAR5 ;
output VAR2 ;
input VAR4;
input VAR3;
VAR1 VAR6 (
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR5,
VAR2
);
output VAR5;
output VAR2;
supply1 VAR4;
supply0 VAR3;
VAR1 VAR6 (
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/dac_spi_if.v | 9,654 | module MODULE1 (
VAR29, VAR38, din, VAR33, VAR44, VAR3,
VAR34, VAR23, VAR17, VAR37, VAR27, VAR26 );
parameter VAR30 = 0; parameter VAR48 = 9'h190;
output [3:0] VAR29; output [3:0] VAR38; output din; output [15:0] VAR33; output VAR44; output VAR3;
input VAR34; input [13:0] VAR23; input [15:0] VAR17; input VAR37; input [... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_1.functional.pp.v | 1,462 | module MODULE1( VAR3, VAR15, VAR6, VAR4, VAR9, VAR2, VAR18 );
input VAR6, VAR4, VAR9, VAR3;
inout VAR2, VAR18;
output VAR15;
wire VAR12;
not VAR16( VAR12, VAR6 );
wire VAR5;
not VAR11( VAR5, VAR4 );
wire VAR10;
not VAR14( VAR10, VAR9 );
wire VAR7;
and VAR8( VAR7, VAR12, VAR5, VAR10 );
wire VAR1;
not VAR17( VAR1, VAR3 )... | apache-2.0 |
johan92/altera_opencl_sandbox | vector_add/bin_vector_add/iface/ip/mem_splitter/acl_iface_ll_fifo.v | 3,461 | module MODULE1(clk, reset, VAR6, write, VAR11, read, VAR14, VAR16);
parameter VAR8 = 32;
parameter VAR10 = 32;
input clk;
input reset;
input [VAR8-1:0] VAR6;
input write;
output [VAR8-1:0] VAR11;
input read;
output VAR14;
output VAR16;
reg [VAR10:0] VAR15;
reg [VAR10:0] VAR7 ;
reg [VAR10-1:0][VAR8-1:0] VAR3;
wire VAR4;... | mit |
SoCdesign/audiomixer | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_hdmi_tx_16b_v1_00_a/hdl/verilog/user_logic.v | 7,766 | module MODULE1 (
VAR15,
VAR50,
VAR44,
VAR55,
VAR23,
VAR24,
VAR25,
VAR39,
VAR6,
VAR22,
VAR9,
VAR14,
VAR56,
VAR3,
VAR8,
VAR16,
VAR20,
VAR31,
VAR19,
VAR21,
VAR18,
VAR36,
VAR32,
VAR58,
VAR40,
VAR49,
VAR10,
VAR29,
VAR27);
parameter VAR33 = 32;
parameter VAR43 = 32;
input VAR15;
output VAR50;
output VAR44;
output VAR55;
outp... | mit |
olajep/oh | src/mio/hdl/mio.v | 6,861 | module MODULE1 #( parameter VAR10 = 64, parameter VAR41 = 32, parameter VAR13 = 104, parameter VAR7 = 18'h0010, parameter VAR58 = 7, parameter VAR14 = "VAR55" )
( input clk, input VAR42, output VAR57, output VAR36, output [VAR10-1:0] VAR15, input VAR38, input VAR53, input VAR24, input [VAR10-1:0] VAR31, output VAR61, i... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlxbn/sky130_fd_sc_hd__dlxbn.functional.pp.v | 1,959 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR11 ,
VAR1,
VAR6 ,
VAR9 ,
VAR15 ,
VAR2
);
output VAR12 ;
output VAR3 ;
input VAR11 ;
input VAR1;
input VAR6 ;
input VAR9 ;
input VAR15 ;
input VAR2 ;
wire VAR14 ;
wire VAR16;
not VAR5 (VAR14 , VAR1 );
VAR4 VAR8 VAR7 (VAR16 , VAR11, VAR14, , VAR6, VAR9);
buf VAR13 (VAR12 , VAR16 );
not ... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch2/CORDIC_Arch2.v | 20,671 | module MODULE1 #(parameter VAR121 = 32, parameter VAR58 = 8, parameter VAR126 = 23, parameter VAR106=26, parameter VAR131 = 5)/*#(parameter VAR121 = 64, parameter VAR58 = 11, parameter VAR126 = 52, parameter VAR106 = 55, parameter VAR131 = 6) (
input wire clk, input wire rst, input wire VAR75, input wire VAR67, input w... | gpl-3.0 |
terriblefire/tf328 | rtl/ramcpld.v | 4,687 | module MODULE1(
input VAR34,
input VAR58,
input [23:0] VAR45,
inout [7:0] VAR33,
input [1:0] VAR40,
input VAR61,
output VAR28,
input VAR1,
input VAR29,
input VAR39,
output VAR48,
output VAR64,
output [3:0] VAR35,
output [1:0] VAR47,
output [1:0] VAR12,
output [1:0] VAR57,
output VAR54,
output VAR20,
output VAR51,
outpu... | gpl-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pwm/db/ip/niosii/submodules/altera_avalon_st_clock_crosser.v | 4,885 | module MODULE1(
VAR21,
VAR1,
VAR27,
VAR14,
VAR12,
VAR18,
VAR25,
VAR6,
VAR11,
VAR5
);
parameter VAR17 = 1;
parameter VAR30 = 8;
parameter VAR13 = 2;
parameter VAR32 = 2;
parameter VAR26 = 1;
localparam VAR22 = VAR17 * VAR30;
input VAR21;
input VAR1;
output VAR27;
input VAR14;
input [VAR22-1:0] VAR12;
input VAR18;
input ... | mit |
phasza/axi_spi_if | apb_reg_if.v | 4,299 | module MODULE1 (
parameter VAR11 = 8,
localparam VAR24 = 32;
localparam VAR13 = VAR4(VAR24)
) (
input VAR16, input VAR6,
input [VAR11-1:0] VAR2,
input [2:0] VAR32,
input VAR3,
input VAR14,
input VAR21,
input [VAR24-1:0] VAR35,
input [VAR13-1:0] VAR8,
output VAR18,
output [VAR24-1:0] VAR34,
output VAR15,
input [VAR24-1:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn.pp.symbol.v | 1,335 | module MODULE1 (
input VAR5 ,
output VAR7 ,
input VAR4,
input VAR1 ,
input VAR6,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_060.v | 1,613 | module MODULE2 (
VAR14,
VAR16
);
input [31:0] VAR14;
output [31:0]
VAR16;
wire [31:0]
VAR11,
VAR5,
VAR1,
VAR12,
VAR7,
VAR10,
VAR15,
VAR6,
VAR13,
VAR8,
VAR9;
assign VAR11 = VAR14;
assign VAR9 = VAR13 - VAR8;
assign VAR15 = VAR10 - VAR7;
assign VAR13 = VAR15 + VAR6;
assign VAR8 = VAR11 << 7;
assign VAR10 = VAR7 << 2;
ass... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp.functional.v | 2,101 | module MODULE1 (
VAR15 ,
VAR14 ,
VAR12 ,
VAR11 ,
VAR18 ,
VAR7 ,
VAR3
);
output VAR15 ;
output VAR14 ;
input VAR12 ;
input VAR11 ;
input VAR18 ;
input VAR7 ;
input VAR3;
wire VAR10 ;
wire VAR5 ;
wire VAR2;
not VAR1 (VAR5 , VAR3 );
VAR8 VAR16 (VAR2, VAR11, VAR18, VAR7 );
VAR6 VAR17 VAR4 (VAR10 , VAR2, VAR12, VAR5);
buf V... | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/ddr2/ddr2_phy_dq_iob.v | 21,882 | module MODULE1 #
(
parameter VAR12 = "VAR32",
parameter VAR62 = "VAR18",
parameter VAR43 = 2
)
(
input VAR30,
input VAR42,
input VAR38,
input VAR68,
input VAR29,
input VAR79,
input VAR66,
input [1:0] VAR41,
input VAR83,
input VAR67,
input VAR24,
input VAR77,
input VAR8,
output VAR57,
output VAR76,
inout VAR4
);
wire VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s6s/sky130_fd_sc_hd__dlymetal6s6s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5,
VAR6,
VAR2 ,
VAR3
);
output VAR4 ;
input VAR1 ;
input VAR5;
input VAR6;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
Gifts/descrypt-ztex-bruteforcer | user_cores/des/src/descrypt_salt.v | 4,172 | module MODULE1(
input [63:0] VAR45,
input [63:0] VAR46,
input [11:0] VAR32,
output [67:0] VAR36,
input VAR26,
output [31:0] VAR43,
output [31:0] VAR2
);
wire [31:0] VAR40;
wire [31:0] VAR29;
wire [63:0] VAR6;
wire [31:0] VAR21 [23:0];
wire [31:0] VAR28 [23:0];
wire [67:0] VAR16 [23:0];
wire [55:0] VAR19;
VAR8 VAR42(VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2.symbol.v | 1,330 | module MODULE1 (
input VAR5,
output VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/aab3c8dbff810ca5/design_1_xbar_0_stub.v | 3,577 | module MODULE1(VAR35, VAR24, VAR14, VAR9,
VAR20, VAR16, VAR22, VAR34, VAR21, VAR37,
VAR23, VAR2, VAR10, VAR38, VAR28, VAR8,
VAR17, VAR25, VAR31, VAR13, VAR12, VAR15,
VAR30, VAR19, VAR40, VAR33, VAR1, VAR27,
VAR36, VAR6, VAR39, VAR29, VAR32, VAR5,
VAR7, VAR4, VAR26, VAR3, VAR18, VAR11)
;
input VAR35;
input VAR24;
input ... | mit |
OpenSoCPlus/hight_crypto_core | rtl/CONTROL.v | 15,385 | module MODULE1(
VAR46 ,
clk ,
VAR11 ,
VAR23 ,
VAR6 ,
VAR7 ,
VAR35 ,
VAR40 ,
VAR37 ,
VAR22 ,
VAR19 ,
VAR32
);
localparam VAR33 = 6'b110000;
localparam VAR4 = 6'b100000;
localparam VAR12 = 6'b000000;
localparam VAR31 = 6'b000001;
localparam VAR48 = 6'b000010;
localparam VAR14 = 6'b000011;
localparam VAR2 = 6'b000100;
loc... | lgpl-2.1 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.