repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
bargei/NoC264 | NoC264_2x2/mkRouterInputArbitersStatic.v | 11,654 | module MODULE1(VAR10,
VAR11,
VAR7,
VAR9,
VAR2,
VAR4,
VAR3,
VAR12,
VAR8,
VAR5,
VAR15,
VAR17,
VAR13,
VAR14,
VAR16,
VAR6,
VAR1);
input VAR10;
input VAR11;
input [4 : 0] VAR7;
output [4 : 0] VAR9;
input VAR2;
input [4 : 0] VAR4;
output [4 : 0] VAR3;
input VAR12;
input [4 : 0] VAR8;
output [4 : 0] VAR5;
input VAR15;
input [... | mit |
chebykinn/university | io/lab3/v-src/FIFO.v | 3,353 | module MODULE1(VAR26,VAR28,VAR18,VAR23,VAR15,VAR1,VAR2,VAR5,VAR13,VAR27,VAR8,VAR17,VAR20,VAR4,VAR3);
input [31:0] VAR26;
input [31:0] VAR28;
output VAR18;
output VAR23;
input [1:0] VAR15;
output [31:0] VAR1;
input [31:0] VAR2;
input VAR5;
input VAR13;
input VAR27;
output [31:0] VAR8;
input [31:0] VAR17;
input [12:0] VA... | mit |
teknohog/rautanoppa | common_hdl/hwrandom_core.v | 2,752 | module MODULE1(clk, VAR12, reset, VAR4);
module MODULE1(clk, VAR12, reset);
parameter VAR15 = 1;
parameter VAR6 = 241;
wire [VAR6-1:0] VAR3;
input clk;
input reset;
generate
genvar VAR25;
for (VAR25 = 0; VAR25 < VAR6; VAR25 = VAR25 + 1)
begin: VAR22
VAR24 #(.VAR17(VAR25 + 1)) VAR2 (.reset(reset), .VAR14(VAR3[VAR25]));
... | gpl-3.0 |
jeffkub/n64-cart-reader | old/n64cartridge/src/sdram/lfsr_count255.v | 2,370 | module MODULE1(
input VAR3,
input VAR4,
output reg VAR2);
reg [7:0] VAR5;
wire VAR1,VAR6;
xnor(VAR1,VAR5[7],VAR5[5],VAR5[4],VAR5[3]);
assign VAR6 = (VAR5 == 8'h80);
always @(posedge VAR3,posedge VAR4) begin
if(VAR4) begin
VAR5 <= 0;
VAR2 <= 0;
end
else begin
VAR5 <= VAR6 ? 8'h0 : {VAR5[6:0],VAR1};
VAR2 <= VAR6;
end
end... | mit |
ehab93/MIPS-Processor | lib/mux_32to1.v | 2,626 | module MODULE1 (
input [4:0] VAR26,
input VAR65, VAR13, VAR70, VAR58, VAR30, VAR23, VAR19, VAR64, VAR51,VAR71, VAR50, VAR40, VAR66, VAR44, VAR56, VAR52,
input VAR59, VAR7, VAR39, VAR29, VAR12, VAR2, VAR45, VAR60, VAR63,VAR20, VAR49, VAR5, VAR8, VAR37, VAR10, VAR18,
output VAR4);
wire VAR33 , VAR25 , VAR46 , VAR48 , VAR... | mit |
ptracton/wb_soc_template | rtl/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v | 29,036 | module MODULE1 (
VAR91,
VAR96,
VAR66,
VAR93,
VAR14,
VAR44,
VAR19, VAR100,
VAR109,
VAR69,
VAR26,
VAR88,
VAR80,
VAR11,
VAR106,
VAR38,
VAR94,
VAR70,
VAR18,
VAR65
);
input VAR91;
output VAR96;
input VAR66;
input VAR93;
input VAR14;
input VAR44;
input [52:0] VAR19;
input VAR100;
output VAR109;
input VAR69;
input VAR26; outp... | mit |
Aetas/nbit-comparator | Quartus 2 proj/seg7.v | 2,342 | module MODULE1(VAR1, VAR2);
input [3:0] VAR1; output reg [0:6] VAR2; always @(VAR1)
case(VAR1)
0: VAR2 = 7'b0000001; 1: VAR2 = 7'b1001111; 2: VAR2 = 7'b0010010; 3: VAR2 = 7'b0000110; 4: VAR2 = 7'b1001100; 5: VAR2 = 7'b0100100; 6: VAR2 = 7'b0100000; 7: VAR2 = 7'b0001111; 8: VAR2 = 7'b0000000; 9: VAR2 = 7'b0000100; 10: V... | mit |
asicguy/gplgpu | hdl/altera_project/spll_pll/spll_pll.v | 16,055 | module MODULE1 (
VAR8,
VAR81,
VAR102,
VAR57,
VAR74,
VAR86);
input VAR8;
input VAR81;
input VAR102;
output VAR57;
output VAR74;
output VAR86;
wire [5:0] VAR89;
wire VAR15;
wire [0:0] VAR77 = 1'h0;
wire [1:1] VAR59 = VAR89[1:1];
wire [0:0] VAR91 = VAR89[0:0];
wire VAR57 = VAR91;
wire VAR74 = VAR59;
wire VAR86 = VAR15;
wi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.behavioral.v | 1,371 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR4
);
output VAR9 ;
input VAR5 ;
input VAR4;
supply1 VAR3 ;
supply0 VAR8;
supply1 VAR7 ;
supply0 VAR6 ;
wire VAR1;
not VAR10 (VAR1 , VAR4 );
or VAR2 (VAR9 , VAR5, VAR1 );
endmodule | apache-2.0 |
victor1994y/BipedRobot_byFPGA | Project_BipedRobot.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1_clk_wiz.v | 7,154 | module MODULE1
( output VAR44,
output VAR52,
input VAR83,
output VAR78,
input VAR37
);
wire VAR2;
wire VAR89;
VAR15 VAR69
(.VAR1 (VAR2),
.VAR93 (VAR37));
wire VAR42;
wire VAR18;
wire VAR77;
wire VAR80;
wire VAR88;
wire VAR72;
wire VAR65;
wire [15:0] VAR86;
wire VAR10;
wire VAR12;
wire VAR40;
wire VAR85;
wire VAR7;
wire... | gpl-3.0 |
chiragsakhuja/gpu | pll/pll_0002.v | 2,069 | module MODULE1(
input wire VAR28,
input wire rst,
output wire VAR25,
output wire VAR1
);
VAR68 #(
.VAR42("false"),
.VAR65("50.0 VAR19"),
.VAR69("VAR22"),
.VAR34(1),
.VAR35("25.000000 VAR19"),
.VAR43("0 VAR64"),
.VAR39(50),
.VAR41("0 VAR19"),
.VAR63("0 VAR64"),
.VAR48(50),
.VAR38("0 VAR19"),
.VAR66("0 VAR64"),
.VAR58(50... | gpl-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_Leds/picoblze/uart_rx.v | 4,290 | module MODULE1
( VAR7,
VAR11,
VAR6,
VAR12,
VAR18,
VAR10,
VAR5,
VAR2,
clk);
input VAR7;
output[7:0] VAR11;
input VAR6;
input VAR12;
input VAR18;
output VAR10;
output VAR5;
output VAR2;
input clk;
wire VAR7;
wire [7:0] VAR11;
wire VAR6;
wire VAR12;
wire VAR18;
wire VAR10;
wire VAR5;
wire VAR2;
wire clk;
wire [7:0] VAR17;... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_intr_wr_mem.v | 2,773 | module MODULE1(
VAR26,
VAR34,
VAR22,
VAR9,
VAR24,
VAR4,
VAR19,
VAR18,
VAR3,
VAR30,
VAR17
);
input VAR26, VAR34;
output VAR22;
input VAR24, VAR9;
output reg VAR17, VAR30;
output reg [VAR10-1:0] VAR19;
output reg [VAR23-1:0] VAR4;
output reg [VAR11:0] VAR18;
output reg [VAR2-1:0] VAR3;
reg [VAR25-1:0] VAR27 = 0, VAR16 = ... | gpl-3.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/sv_mult27.v | 26,005 | module MODULE2
(
VAR225,
VAR83,
VAR92,
VAR257,
VAR240) ;
input VAR225;
input VAR83;
input [26:0] VAR92;
input [26:0] VAR257;
output [53:0] VAR240;
tri1 VAR225;
tri0 [26:0] VAR92;
tri0 [26:0] VAR257;
wire [53:0] VAR132;
wire VAR61;
wire VAR263;
wire VAR69;
VAR188 VAR14
(
.VAR82(),
.VAR225(VAR225),
.VAR92(VAR92),
.VAR257... | mit |
glennchid/font5-firmware | src/verilog/synthesis/bench.v | 2,388 | module MODULE1(
input clk,
output reg VAR15 = 0,
output reg VAR4 = 0
);
parameter VAR13 = 21'd1402596; parameter VAR11 = 8'd82;
parameter VAR5 = 8'd27;
parameter VAR9 = 10'd1000;
reg [20:0] VAR2 =21'd0;
reg [9:0] VAR12 = 10'd0;
reg [7:0] VAR16 = 8'd0;
reg VAR8 = 0, VAR10 = 0, VAR1 = 0, VAR3 = 0, VAR7 = 0, VAR6 = 0;
wir... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrsnq/gf180mcu_fd_sc_mcu9t5v0__sdffrsnq_1.functional.pp.v | 1,804 | module MODULE1( VAR31, VAR17, VAR21, VAR13, VAR24, VAR14, VAR1, VAR10, VAR29, VAR7 );
input VAR13, VAR21, VAR14, VAR31, VAR24, VAR17, VAR10, VAR29, VAR7;
output VAR1;
not VAR22( VAR20, VAR14 );
not VAR25( VAR5, VAR24 );
wire VAR2;
not VAR8( VAR2, VAR21 );
wire VAR6;
not VAR27( VAR6, VAR31 );
wire VAR26;
and VAR3( VAR26... | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v | 1,786 | module MODULE1 #(
parameter VAR5( VAR10 )
,parameter VAR2 = 1
)
(
input VAR1
,input [VAR10-1:0] VAR7
,output[VAR10-1:0] VAR3
);
if( VAR2 == 0) begin:VAR12
assign VAR3 = VAR7;
end:VAR12
else begin:VAR4
logic [VAR2:0][VAR10-1:0] VAR11;
assign VAR11[0] = VAR7 ;
assign VAR3 = VAR11[VAR2] ;
genvar VAR9;
for(VAR9=1; VAR9<= V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufbuf/sky130_fd_sc_lp__bufbuf.behavioral.v | 1,341 | module MODULE1 (
VAR8,
VAR6
);
output VAR8;
input VAR6;
supply1 VAR4;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR7 ;
wire VAR2;
buf VAR5 (VAR2, VAR6 );
buf VAR3 (VAR8 , VAR2 );
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_sof.v | 2,904 | module MODULE2
(input VAR35,
input VAR39,
input VAR42,
output VAR23,
inout VAR44,
inout VAR24);
wire [4:0] VAR15;
wire [31:0] VAR43 = { VAR15,
VAR17,
8'b10100101, 8'b11010101 };
wire [10:0] VAR2 =
{ VAR17[0], VAR17[1], VAR17[2], VAR17[3],
VAR17[4], VAR17[5], VAR17[6], VAR17[7],
VAR17[8], VAR17[9], VAR17[10] };
wire VAR... | apache-2.0 |
vr3d/miaow | src/verilog/rtl/issue/alu_issue_logic.v | 6,663 | module MODULE1
(
VAR22, VAR28, VAR19,
VAR15, VAR31, VAR8,
VAR26, VAR3, VAR18,
VAR37, VAR33, VAR36,
clk, rst, VAR35, VAR27, VAR38,
VAR12, VAR23, VAR5,
VAR41, VAR9, VAR7,
VAR11, VAR24, VAR4, VAR1,
VAR20, VAR30, VAR13, VAR39,
VAR6
);
input clk,rst;
input VAR35, VAR27,
VAR38,VAR12,
VAR23,VAR5,
VAR41,VAR9,
VAR7,VAR11;
input... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/pcie_blk_cf_mgmt.v | 28,285 | module MODULE1
(
input wire clk,
input wire VAR20,
input wire [12:0] VAR84,
output reg [10:0] VAR45 = 11'h047,
output reg VAR3 = 0,
output reg VAR58 = 0,
output reg [31:0] VAR61 = 0,
output reg [3:0] VAR10 = 4'hF,
input wire [31:0] VAR40,
input wire [16:0] VAR38,
input wire [63:0] VAR11,
output reg [31:0] VAR83 = 0,
ou... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.pp.blackbox.v | 1,435 | module MODULE1 (
VAR6 ,
VAR10 ,
VAR2 ,
VAR4 ,
VAR1 ,
VAR3 ,
VAR9,
VAR8,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/ucore/mem_ctrl.v | 6,787 | module MODULE1
(
VAR4,
VAR1,VAR10,
VAR22,
VAR7,VAR12,VAR19,VAR25,VAR15,
VAR13,
VAR21,VAR8,VAR2,VAR9,VAR26,VAR18,VAR3,VAR11,VAR17,
VAR14, VAR23, VAR28, VAR24, VAR20,
VAR5,VAR16
);
input VAR4;
input VAR10;
input [31:0] VAR1; output [31:0] VAR22;
output VAR14;
output VAR23;
output [31:0] VAR28;
input VAR24;
input [31:0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b.pp.symbol.v | 1,307 | module MODULE1 (
input VAR1 ,
input VAR4 ,
input VAR6 ,
output VAR8 ,
input VAR3 ,
input VAR2,
input VAR5,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf.pp.symbol.v | 1,236 | module MODULE1 (
input VAR3 ,
output VAR4 ,
input VAR1 ,
input VAR6,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/OPED.v | 7,831 | module MODULE1 #
( parameter VAR36 = 32,
parameter VAR21 = 32,
parameter VAR5 = 128,
parameter VAR39 = 128,
parameter VAR15 = 0)
( input VAR4, input VAR37,
input VAR44,
input [7:0] VAR29,
input [7:0] VAR32,
output [7:0] VAR41,
output [7:0] VAR7,
output VAR46, output VAR23,
output [31:0] VAR9, output [2:0] VAR26,
output... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi.symbol.v | 1,383 | module MODULE1 (
input VAR6,
input VAR2,
input VAR7,
input VAR4,
output VAR5
);
supply1 VAR8;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi.functional.v | 1,545 | module MODULE1 (
VAR5 ,
VAR6,
VAR11,
VAR2,
VAR3
);
output VAR5 ;
input VAR6;
input VAR11;
input VAR2;
input VAR3;
wire VAR7 ;
wire VAR4 ;
wire VAR8;
nand VAR9 (VAR7 , VAR11, VAR6 );
nand VAR12 (VAR4 , VAR3, VAR2 );
and VAR10 (VAR8, VAR7, VAR4);
buf VAR1 (VAR5 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3b/sky130_fd_sc_lp__nand3b.behavioral.v | 1,497 | module MODULE1 (
VAR13 ,
VAR2,
VAR9 ,
VAR12
);
output VAR13 ;
input VAR2;
input VAR9 ;
input VAR12 ;
supply1 VAR1;
supply0 VAR11;
supply1 VAR4 ;
supply0 VAR7 ;
wire VAR6 ;
wire VAR8;
not VAR10 (VAR6 , VAR2 );
nand VAR3 (VAR8, VAR9, VAR6, VAR12 );
buf VAR5 (VAR13 , VAR8 );
endmodule | apache-2.0 |
LSaldyt/qnp | output/vs/var20_multi.v | 1,558 | module MODULE1 (VAR10, VAR17, VAR3, VAR26, VAR21, VAR12, VAR15, VAR6, VAR23, VAR19, VAR24, VAR7, VAR14, VAR25, VAR9, VAR18, VAR16, VAR11, VAR13, VAR4, valid);
input VAR10, VAR17, VAR3, VAR26, VAR21, VAR12, VAR15, VAR6, VAR23, VAR19, VAR24, VAR7, VAR14, VAR25, VAR9, VAR18, VAR16, VAR11, VAR13, VAR4;
output valid;
wire [... | mit |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_miim.v | 16,494 | module MODULE1
(
VAR22,
VAR48,
VAR56,
VAR27,
VAR7,
VAR33,
VAR52,
VAR45,
VAR15,
VAR37,
VAR51,
VAR34,
VAR2,
VAR23,
VAR55,
VAR46,
VAR25,
VAR31,
VAR16,
VAR38,
VAR8
);
input VAR22; input VAR48; input [7:0] VAR56; input [15:0] VAR7; input [4:0] VAR33; input [4:0] VAR52; input VAR27; input VAR45; input VAR15; input VAR37; inp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.symbol.v | 1,374 | module MODULE1 (
input VAR3,
input VAR10,
input VAR4,
input VAR7,
input VAR8,
output VAR1
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_dmmu_top.v | 8,135 | module MODULE1(
clk, rst,
VAR17, VAR12, VAR31, VAR34, VAR24, VAR7,
VAR39, VAR29,
VAR54, VAR46, VAR10, VAR23, VAR8,
VAR30, VAR36, VAR49,
VAR18, VAR38, VAR44, VAR11, VAR13
);
parameter VAR51 = VAR53;
parameter VAR14 = VAR53;
input clk;
input rst;
input VAR17;
input VAR12;
input VAR31;
input [VAR14-1:0] VAR34;
input VAR24... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fahcin/sky130_fd_sc_ms__fahcin.blackbox.v | 1,332 | module MODULE1 (
VAR4,
VAR5 ,
VAR7 ,
VAR3 ,
VAR2
);
output VAR4;
output VAR5 ;
input VAR7 ;
input VAR3 ;
input VAR2 ;
supply1 VAR9;
supply0 VAR8;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ptracton/pmodacl2 | soc/display/timer.v | 2,486 | module MODULE1(
VAR5, VAR3,
clk, reset, VAR4, VAR2, VAR6
);
input clk;
input reset;
input [31:0] VAR4;
input VAR2;
input VAR6;
output VAR5;
output [31:0] VAR3;
reg [31:0] VAR3;
reg VAR5;
wire VAR1 = VAR2 & (VAR3 >= (VAR4-1));
always @(posedge clk)
if (reset) begin
VAR3 <= 16'b0;
end else if (VAR1) begin
VAR3 <= 16'b0;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.functional.v | 1,434 | module MODULE1 (
VAR5 ,
VAR4,
VAR8,
VAR1
);
output VAR5 ;
input VAR4;
input VAR8;
input VAR1;
wire VAR7 ;
wire VAR2;
or VAR3 (VAR7 , VAR8, VAR4 );
nand VAR6 (VAR2, VAR1, VAR7 );
buf VAR9 (VAR5 , VAR2 );
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/ip_pcie/source/PCIeGen2x8If128_pcie_bram_top_7x.v | 8,653 | module MODULE1
parameter VAR2 = "VAR15", parameter VAR23 = 0, parameter [3:0] VAR35 = 4'h1, parameter [5:0] VAR31 = 6'h08,
parameter VAR30 = 31, parameter VAR1 = 24, parameter VAR24 = 1, parameter VAR6 = 2, parameter VAR8 = 1,
parameter VAR17 = 'h1FFF, parameter VAR19 = 1, parameter VAR29 = 2, parameter VAR9 = 1 )
(
in... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/atlys/rtl/verilog/xilinx_ddr2/infrastructure.v | 10,450 | module MODULE1 #
(
parameter VAR60 = 2500,
parameter VAR81 = 1,
parameter VAR33 = "VAR41",
parameter VAR106 = 1,
parameter VAR30 = 1,
parameter VAR93 = 16,
parameter VAR92 = 8,
parameter VAR117 = 2,
parameter VAR90 = 1
)
(
input VAR2,
input VAR3,
input VAR16,
input VAR100,
output VAR32,
output VAR71,
output VAR69,
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p.behavioral.pp.v | 2,304 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR5 ,
VAR3,
VAR13 ,
VAR17 ,
VAR12,
VAR6 ,
VAR7
);
output VAR9 ;
input VAR10 ;
input VAR5 ;
input VAR3;
input VAR13 ;
input VAR17 ;
input VAR12;
input VAR6 ;
input VAR7 ;
wire VAR18 ;
wire VAR15 ;
wire VAR11;
wire VAR19 ;
not VAR8 (VAR18 , VAR10 );
VAR2 VAR14 (VAR15 , VAR5, VAR13, VAR17 ... | apache-2.0 |
zhaishaomin/ring_network-based-multicore- | reg.v | 7,077 | module MODULE2(VAR5, clk, reset, VAR4);
parameter VAR2 = 63;
output [VAR2:0] VAR5;
input clk;
input reset;
input [VAR2:0] VAR4;
reg [VAR2:0] VAR3;
assign VAR5 = VAR3;
always @(posedge clk)
begin
VAR3 <= VAR4;
end
always @(posedge reset)
begin
VAR3 = 'b0;
end
endmodule
module MODULE4(VAR5, clk, reset, VAR6, VAR4);
param... | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac_burst_memory.v | 14,659 | module MODULE1 #(
parameter VAR50 = 64,
parameter VAR10 = 64,
parameter VAR100 = 3,
parameter VAR12 = 128,
parameter VAR40 = 1,
parameter VAR68 = VAR64(VAR50/8),
parameter VAR15 = VAR64(VAR12),
parameter VAR9 = 0
) (
input VAR8,
input VAR22,
input VAR89,
input [VAR50-1:0] VAR99,
input VAR96,
input [VAR68-1:0] VAR55,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.v | 2,163 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR4,
VAR7,
VAR5 ,
VAR8
);
output VAR6 ;
input VAR1 ;
input VAR4;
input VAR7;
input VAR5 ;
input VAR8 ;
VAR3 VAR2 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR4;
supply0 VAR7;... | apache-2.0 |
skyfex/svo-raycaster | raycaster1/raycaster.v | 13,297 | module MODULE1(
VAR63,
VAR124,
VAR33, VAR25,
VAR61, VAR30, VAR164,
VAR157, VAR67,
VAR169, VAR177, VAR154, VAR141,
VAR39, VAR50, VAR127,
VAR75, VAR172, VAR167,
VAR38, VAR160, VAR214,
VAR62, VAR43,
VAR113
);
input VAR63;
input VAR124;
input [7:0] VAR33;
input [7:0] VAR25;
input VAR61;
input VAR30;
input VAR164;
input [2:... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfstp/sky130_fd_sc_hs__dfstp_2.v | 2,142 | module MODULE1 (
VAR4 ,
VAR5 ,
VAR1 ,
VAR7,
VAR8 ,
VAR6
);
input VAR4 ;
input VAR5 ;
output VAR1 ;
input VAR7;
input VAR8 ;
input VAR6 ;
VAR2 VAR3 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR4 ,
VAR5 ,
VAR1 ,
VAR7
);
input VAR4 ;
input VAR5 ;
output VA... | apache-2.0 |
cpulabs/mist1032sa | src/core/execute/old_execute/shift.v | 13,078 | module MODULE1
parameter VAR14 = 32
)
(
input [2:0] VAR11,
input [VAR14-1:0] VAR16,
input [VAR14-1:0] VAR7,
output [VAR14-1:0] VAR1,
output VAR23,
output VAR5,
output VAR21,
output VAR9,
output VAR22
);
genvar VAR6;
wire [31:0] VAR24;
assign VAR24 = VAR16;
wire [31:0] VAR3[0:63];
generate
for(VAR6 = 0; VAR6 < 64; VAR6 ... | bsd-2-clause |
theapi/nand2tetris_fpga | hack/DE1_SOC/DE1_SOC.v | 2,319 | module MODULE1(
input VAR1,
input VAR51,
input VAR11,
input VAR37,
output [12:0] VAR22,
output [1:0] VAR38,
output VAR39,
output VAR27,
output VAR5,
output VAR10,
inout [15:0] VAR23,
output VAR46,
output VAR6,
output VAR36,
output VAR24,
output [6:0] VAR44,
output [6:0] VAR29,
output [6:0] VAR3,
output [6:0] VAR48,
out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_mux_4to2/sky130_fd_sc_hs__udp_mux_4to2.blackbox.v | 1,298 | module MODULE1 (
VAR5 ,
VAR7,
VAR2,
VAR3,
VAR1,
VAR6,
VAR4
);
output VAR5 ;
input VAR7;
input VAR2;
input VAR3;
input VAR1;
input VAR6;
input VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a_2.v | 2,248 | module MODULE2 (
VAR9 ,
VAR4 ,
VAR10 ,
VAR3 ,
VAR6,
VAR5,
VAR8 ,
VAR7
);
output VAR9 ;
input VAR4 ;
input VAR10 ;
input VAR3 ;
input VAR6;
input VAR5;
input VAR8 ;
input VAR7 ;
VAR1 VAR2 (
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2.symbol.v | 1,254 | module MODULE1 (
input VAR7,
input VAR6,
output VAR3
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_jesd_gt/axi_jesd_gt.v | 34,241 | module MODULE1 (
VAR90,
VAR221,
VAR298,
VAR271,
VAR45,
VAR1,
VAR194,
VAR135,
VAR186,
VAR197,
VAR310,
VAR20,
VAR278,
VAR33,
VAR29,
VAR14,
VAR335,
VAR201,
VAR295,
VAR193,
VAR106,
VAR351,
VAR289,
VAR152,
VAR77,
VAR290,
VAR244,
VAR320,
VAR55,
VAR229,
VAR40,
VAR18,
VAR207,
VAR288,
VAR179,
VAR79,
VAR100,
VAR321,
VAR261,
VAR2... | gpl-3.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/General_Purpose_Regs.v | 1,960 | module MODULE1(
input[31:0] din, output[31:0] VAR2, output[31:0] VAR5,
input[4:0] VAR4,
input[4:0] VAR1,
input[1:0] VAR10, input VAR14, input clk );
reg [3:0] VAR11;
wire [31:0] VAR12;
wire [31:0] VAR13;
VAR7 VAR6(
.VAR8(din), .VAR2(VAR12),
.VAR5(VAR13),
.VAR4(VAR4), .VAR1(VAR1),
.VAR14(VAR14), .clk(clk), .sel(VAR11[0]... | gpl-3.0 |
monotone-RK/FACE | CQ/src/riffa/tx_engine_selector.v | 5,012 | module MODULE1
parameter VAR4 = 4'd12
)
(
input VAR7,
input VAR9,
input [VAR4-1:0] VAR8,
output VAR3, output [3:0] VAR13 );
reg [3:0] VAR1=0, VAR1=0;
reg [3:0] VAR11=0, VAR11=0;
reg VAR14=0, VAR14=0;
reg [3:0] VAR10=0, VAR10=0;
reg [3:0] VAR6=0, VAR6=0;
reg VAR15=0, VAR15=0;
reg VAR16=0, VAR16=0;
wire VAR12;
reg VAR17=... | mit |
nextseto/Verilog-Projects | Project 2 – Combinational Logic/dec_4_to_16/dec_4_to_16.v | 1,330 | module MODULE1
(
input [3:0] VAR2,
output [15:0] VAR1
);
assign VAR1[0] = ~VAR2[0] & ~VAR2[1] & ~VAR2[2] & ~VAR2[3];
assign VAR1[1] = ~VAR2[0] & ~VAR2[1] & ~VAR2[2] & VAR2[3];
assign VAR1[2] = ~VAR2[0] & ~VAR2[1] & VAR2[2] & ~VAR2[3];
assign VAR1[3] = ~VAR2[0] & ~VAR2[1] & VAR2[2] & VAR2[3];
assign VAR1[4] = ~VAR2[0] &... | mit |
unihd-cag/openhmc | rtl/building_blocks/counter/openhmc_counter48_wrapper_xilinx.v | 8,798 | module MODULE1 #(
parameter VAR2 = 48, parameter VAR6 = 1, parameter VAR1 = 1
) (
input wire clk,
input wire VAR4,
input wire [VAR6-1:0] VAR3,
output wire [VAR2-1:0] VAR5
);
begin
begin | lgpl-3.0 |
zuloloxi/mecrisp-ice | hx1k/icestorm/j1.v | 5,964 | module MODULE1(
input wire clk,
input wire VAR26,
output wire VAR46,
output wire VAR12,
output wire [15:0] VAR28,
output wire VAR5,
output wire [15:0] dout,
input wire [15:0] VAR47,
output wire [12:0] VAR39,
input wire [15:0] VAR41,
input wire VAR21
);
reg VAR2 = 0;
wire interrupt = VAR21 & VAR2;
reg [4:0] VAR9, VAR43;... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor3/sky130_fd_sc_lp__nor3_m.v | 2,195 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR10,
VAR7,
VAR6 ,
VAR8
);
output VAR1 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR10;
input VAR7;
input VAR6 ;
input VAR8 ;
VAR5 VAR3 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi.functional.pp.v | 2,082 | module MODULE1 (
VAR11 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR7 ,
VAR14 ,
VAR10,
VAR1,
VAR12 ,
VAR2
);
output VAR11 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR7 ;
input VAR14 ;
input VAR10;
input VAR1;
input VAR12 ;
input VAR2 ;
wire VAR4 ;
wire VAR16 ;
wire VAR17;
and VAR5 (VAR4 , VAR3, VAR9 );
nor VAR13 (VAR16 , VAR8, VAR7... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/memc_flow_vcontrol.v | 20,928 | module MODULE1 #
(
parameter VAR53 = 100,
parameter VAR21 = 4,
parameter VAR15 = 32,
parameter VAR24 = 6,
parameter VAR77 = 4,
parameter VAR31 = "VAR39",
parameter VAR22 = "VAR29"
)
(
input VAR49,
input [9:0] VAR28,
input [3:0] VAR9,
input [5:0] VAR27,
output reg VAR5,
input VAR36,
input [2:0] VAR71,
input [31:0] VAR48... | lgpl-3.0 |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/WROM256.v | 25,645 | module MODULE1 ( VAR6 ,VAR3 ,VAR9 );
input [7:0] VAR9 ;
wire [7:0] VAR9 ;
output [VAR1-1:0] VAR6 ;
wire [VAR1-1:0] VAR6 ;
output [VAR1-1:0] VAR3 ;
wire [VAR1-1:0] VAR3 ;
wire [15:0] VAR4[0:255];
assign VAR4[0]=16'h7FFF; assign VAR4[1]=16'h7FFF; assign VAR4[2]=16'h7FFF; assign VAR4[3]=16'h7FFF; assign VAR4[4]=16'h7FFF; ... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/8-way_4-parallel/ise/ipcore_dir/dram/user_design/rtl/controller/mig_7series_v1_9_bank_cntrl.v | 25,941 | module MODULE1 #
(
parameter VAR97 = 100,
parameter VAR79 = "1T",
parameter VAR102 = 3,
parameter VAR138 = 2,
parameter VAR104 = "8",
parameter VAR95 = 12,
parameter VAR77 = 5,
parameter VAR132 = 8,
parameter VAR58 = "VAR25",
parameter VAR52 = "VAR109",
parameter VAR93 = 4,
parameter VAR15 = 4,
parameter VAR130 = 2,
pa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand4/sky130_fd_sc_lp__nand4_0.v | 2,253 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR7 ,
VAR6 ,
VAR10 ,
VAR1,
VAR9,
VAR3 ,
VAR11
);
output VAR8 ;
input VAR2 ;
input VAR7 ;
input VAR6 ;
input VAR10 ;
input VAR1;
input VAR9;
input VAR3 ;
input VAR11 ;
VAR5 VAR4 (
.VAR8(VAR8),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR3(VAR3),
.VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.v | 2,242 | module MODULE1 (
VAR6 ,
VAR8,
VAR7 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR4
);
output VAR6 ;
input VAR8;
input VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR4 ;
VAR9 VAR3 (
.VAR6(VAR6),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR6 ,
VAR8,
VAR7
);
output VAR... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_prc_read_master.v | 4,141 | module MODULE1
( VAR4,
reset,
VAR48,
VAR24,
VAR6,
VAR31,
VAR9,
VAR21, VAR33,
VAR42,
read,
VAR39,
VAR49,
VAR58,
VAR19,
VAR38,
VAR64,
VAR27,
VAR52,
VAR54,
VAR36,
VAR47,
);
parameter VAR32 = 16;
parameter VAR16 = 16;
parameter VAR40 = 11;
parameter VAR45 = 1;
parameter VAR53 = 8;
parameter VAR28 = 8;
parameter VAR18 = 5;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr_8.v | 2,265 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR4,
VAR5 ,
VAR9 ,
VAR1 ,
VAR2
);
output VAR7 ;
input VAR6 ;
input VAR4;
input VAR5 ;
input VAR9 ;
input VAR1 ;
input VAR2 ;
VAR8 VAR3 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR7,
VAR6
);
output VAR7;
inpu... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_ddrx_decoder.v | 2,454 | module MODULE1 #
( parameter
VAR6 = 72,
VAR11 = 64
)
(
VAR15,
VAR8,
VAR14,
VAR3,
VAR9,
VAR5
);
input VAR15;
input [VAR6 - 1 : 0] VAR8;
output [VAR11 - 1 : 0] VAR5;
output VAR14;
output VAR3;
output VAR9;
wire [VAR11 - 1 : 0] VAR5;
wire VAR14;
wire VAR3;
wire VAR9;
generate
if (VAR6 == 40)
begin
VAR2 VAR1
(
.VAR10 (VAR1... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu7t5v0__aoi21_4.functional.v | 1,360 | module MODULE1( VAR2, VAR6, VAR9, VAR4 );
input VAR6, VAR2, VAR4;
output VAR9;
wire VAR15;
not VAR10( VAR15, VAR6 );
wire VAR8;
not VAR5( VAR8, VAR4 );
wire VAR11;
and VAR1( VAR11, VAR15, VAR8 );
wire VAR3;
not VAR13( VAR3, VAR2 );
wire VAR7;
and VAR14( VAR7, VAR3, VAR8 );
or VAR12( VAR9, VAR11, VAR7 );
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/uart16550/rtl/verilog/raminfr.v | 5,764 | module MODULE1
(clk, VAR3, VAR1, VAR7, VAR2, VAR4);
parameter VAR8 = 4;
parameter VAR6 = 8;
parameter VAR9 = 16;
input clk;
input VAR3;
input [VAR8-1:0] VAR1;
input [VAR8-1:0] VAR7;
input [VAR6-1:0] VAR2;
output [VAR6-1:0] VAR4;
reg [VAR6-1:0] VAR5 [VAR9-1:0];
wire [VAR6-1:0] VAR4;
wire [VAR6-1:0] VAR2;
wire [VAR8-1:0]... | mit |
asicguy/gplgpu | hdl/de_temp/der_reg_2.v | 7,304 | module MODULE1
(
input VAR19, input VAR27, input VAR2, input VAR17, input [12:0] VAR10, input [31:0] VAR15, input [31:0] VAR33, input [11:0] VAR20, input [11:0] VAR4, input [3:0] VAR23, input [3:0] VAR44, input [4:0] VAR30, input VAR38, input [1:0] VAR12, input [2:0] VAR11, input [31:0] VAR26, input [31:0] VAR42, input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2/sky130_fd_sc_ls__or2_1.v | 2,075 | module MODULE2 (
VAR7 ,
VAR6 ,
VAR4 ,
VAR8,
VAR2,
VAR3 ,
VAR9
);
output VAR7 ;
input VAR6 ;
input VAR4 ;
input VAR8;
input VAR2;
input VAR3 ;
input VAR9 ;
VAR1 VAR5 (
.VAR7(VAR7),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR7,
VAR6,
VAR4
);
output VAR7;
... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_axi_basic_tx_pipeline.v | 22,383 | module MODULE1 #(
parameter VAR14 = 128, parameter VAR39 = "VAR45", parameter VAR59 = 1,
parameter VAR23 = (VAR14 == 128) ? 2 : 1, parameter VAR37 = VAR14 / 8 ) (
input [VAR14-1:0] VAR13, input VAR19, output VAR2, input [VAR37-1:0] VAR30, input VAR36, input [3:0] VAR58,
output [VAR14-1:0] VAR61, output VAR35, output VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.functional.pp.v | 2,015 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR2 ,
VAR16 ,
VAR10 ,
VAR3,
VAR12,
VAR6 ,
VAR14
);
output VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR16 ;
input VAR10 ;
input VAR3;
input VAR12;
input VAR6 ;
input VAR14 ;
wire VAR4 ;
wire VAR9 ;
wire VAR17;
or VAR1 (VAR4 , VAR2, VAR5, VAR16 );
and VAR7 (VAR9 , VAR4, VAR10 );
VAR11 VAR15 ... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_current_monitor/ad7401.v | 7,447 | module MODULE1
(
input VAR19, input VAR17, input VAR12,
output reg [15:0] VAR8, output reg VAR1, output reg VAR15,
input VAR13 );
wire VAR2;
wire [15:0] VAR6 ;
reg [3:0] VAR20;
reg [3:0] VAR10;
reg VAR3;
reg VAR18;
localparam VAR21 = 4'b0001;
localparam VAR14 = 4'b0010;
localparam VAR22 = 4'b0100;
localparam VAR7 = 4'b... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/ad_gtv6_channel_1.v | 16,607 | module MODULE1 (
rst,
VAR20,
VAR367,
VAR277,
VAR274,
VAR296,
VAR163,
VAR129,
VAR214,
VAR67,
VAR146,
VAR303,
VAR120,
VAR137,
VAR77,
VAR138,
VAR88,
VAR73,
VAR258,
VAR359,
VAR309,
VAR221,
VAR295,
VAR58,
VAR315,
VAR314,
VAR7,
VAR9,
VAR131,
VAR173,
VAR100,
VAR144,
VAR147,
VAR4);
input rst;
input VAR20;
input VAR367;
input V... | mit |
monotone-RK/FACE | MCSoC-15/8-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/ui/mig_7series_v1_9_ui_top.v | 14,966 | module MODULE1 #
(
parameter VAR32 = 100,
parameter VAR2 = 256,
parameter VAR18 = 32,
parameter VAR35 = 3,
parameter VAR29 = 12,
parameter VAR67 = 5,
parameter VAR73 = 5,
parameter VAR74 = "VAR23",
parameter VAR55 = "VAR23",
parameter VAR72 = "VAR47",
parameter VAR63 = 2,
parameter VAR57 = 4,
parameter VAR80 = "VAR19",... | mit |
shaform/ArkanoidOnVerilog | gift_control.v | 1,757 | module MODULE1(
input VAR10, reset, enable, VAR27,
input [9:0] VAR3, VAR22,
output reg [2:0] VAR32,
output reg [9:0] VAR29, VAR31,
output reg VAR14,
output reg VAR16, VAR24, VAR19, VAR5, VAR12, VAR25, VAR23, VAR20
);
localparam VAR21 = 3'b000; localparam VAR7 = 3'b001; localparam VAR26 = 3'b010; localparam VAR9 = 3'b01... | gpl-3.0 |
asicguy/gplgpu | hdl/mc_graph/mc_mff.v | 8,946 | module MODULE1
)
(
input VAR70,
input VAR28,
input [(VAR37*8)-1:0] VAR9,
input [(VAR37*4)-1:0] VAR13,
input [(VAR37*8)-1:0] VAR66,
input [VAR37-1:0] VAR20,
input VAR40,
input VAR17,
input VAR48,
input VAR67,
input VAR12,
input VAR14,
input VAR79,
input VAR51,
input VAR44,
input [(VAR37*8)-1:0] VAR56,
input [2:0] VAR33,... | gpl-3.0 |
nliu96/openHMC_Altera | src/counter48.v | 3,280 | module MODULE1 #(
parameter VAR7 = 16 ) (
input wire clk,
input wire VAR8,
input wire VAR4,
input wire [VAR7-1:0] VAR3,
input wire VAR9,
output wire [VAR7-1:0] VAR2
);
reg [VAR7-1:0] VAR5;
reg VAR6;
assign VAR2 = VAR5;
always @(posedge clk or negedge VAR8) else
always @(posedge clk) VAR1
begin
if (!VAR8)
begin
VAR5 <= ... | lgpl-3.0 |
alankarkotwal/lc-3b-processor | controller.v | 7,436 | module MODULE1(clk, VAR5, VAR1, VAR2, VAR23, VAR4, VAR6, VAR19, VAR13, VAR12, VAR15, VAR3, VAR9, VAR7, VAR16, VAR18, VAR10, VAR24, VAR20, VAR21, VAR11, VAR17);
input [15:0] VAR5;
input clk, VAR1, VAR2, VAR23;
output reg [4:0] VAR4;
output reg VAR6;
output reg [1:0] VAR19;
output reg [2:0] VAR13;
output reg [1:0] VAR12;... | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_base/bsx.v | 8,868 | module MODULE1(
input VAR56,
input VAR3,
input VAR15,
input VAR43,
input [23:0] VAR44,
input [7:0] VAR35,
output [7:0] VAR7,
input [7:0] VAR13,
input [7:0] VAR38,
output [14:0] VAR51,
input VAR30,
input VAR16,
output VAR25,
output VAR9,
input [59:0] VAR36,
output [9:0] VAR53, output VAR1,
output [8:0] VAR58,
input VAR2... | gpl-2.0 |
Elphel/x393_sata | wrapper/clock_inverter.v | 2,692 | module MODULE1(
input rst, input VAR14,
input VAR16,
output VAR30
);
VAR22 #(
.VAR29 (0),
.VAR19 (1'b0),
.VAR25 (1'b0),
.VAR17 (1'b1),
.VAR7 (1'b0),
.VAR1 (1'b0),
.VAR6 (1'b0),
.VAR21 (1'b1),
.VAR11 (1'b0),
.VAR8 ("VAR15"),
.VAR3 ("VAR26")
) VAR4 (
.VAR10 (VAR30), .VAR2 (1'b1), .VAR13 (1'b1), .VAR28 (VAR14), .VAR9 (VAR... | gpl-3.0 |
zhangly/azpr_cpu | rtl/io/uart/rtl/uart.v | 3,435 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR8, input wire VAR11, input wire VAR2, input wire [VAR13] addr, input wire [VAR5] VAR3, output wire [VAR5] VAR9, output wire VAR14,
output wire VAR1, output wire VAR16,
input wire VAR20, output wire VAR22 );
wire VAR10; wire VAR12; wire [VAR19] VAR21; wire... | mit |
devinacker/sd2snes | verilog/sd2snes_obc1/mcu_cmd.v | 12,606 | module MODULE1(
input clk,
input VAR51,
input VAR36,
input [7:0] VAR48,
input [7:0] VAR35,
output [2:0] VAR46,
output VAR2,
output VAR29,
output VAR21,
input VAR4,
output [7:0] VAR50,
input [7:0] VAR25,
output [7:0] VAR55,
input [31:0] VAR53,
input [2:0] VAR11,
output [23:0] VAR3,
output [23:0] VAR8,
output [23:0] VAR2... | gpl-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N8_R1_P1_syn.v | 1,692 | module MODULE1 ( VAR33, VAR20, VAR44 );
input [7:0] VAR33;
input [7:0] VAR20;
output [8:0] VAR44;
wire VAR56, VAR27, VAR9, VAR49, VAR43, VAR21, VAR54, VAR55, VAR22, VAR26, VAR46, VAR48, VAR40;
VAR12 VAR7 ( .VAR58(VAR33[6]), .VAR10(VAR20[6]), .VAR8(VAR56) );
VAR51 VAR37 ( .VAR35(VAR20[2]), .VAR2(VAR33[2]), .VAR47(VAR22)... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai31/gf180mcu_fd_sc_mcu9t5v0__oai31_4.behavioral.v | 1,964 | module MODULE1( VAR4, VAR3, VAR7, VAR8, VAR2 );
input VAR8, VAR7, VAR4, VAR2;
output VAR3;
VAR5 VAR1(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2));
VAR5 VAR6(.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7),.VAR8(VAR8),.VAR2(VAR2)); | apache-2.0 |
iori-yja/ball_detector | hsvconv.v | 3,128 | module MODULE1 (
input clk,
input VAR38,
input read,
input [15:0] VAR45,
output [4:0] VAR10,
output [4:0] VAR49,
output [8:0] VAR3,
output reg VAR15,
output reg VAR48
);
parameter VAR40 = 4'h8;
parameter VAR44 = 3'h0,
VAR1 = 3'h1,
VAR32 = 3'h2,
VAR35 = 3'h3,
VAR16 = 3'h4;
wire [4:0] VAR31;
wire [4:0] VAR12;
wire [4:0] ... | mit |
bluespec/Flute | builds/RV32ACIMU_Flute_verilator/Verilog_RTL/mkCSR_MIP.v | 7,574 | module MODULE1(VAR38,
VAR43,
VAR31,
VAR24,
VAR34,
VAR46,
VAR36,
VAR47,
VAR60,
VAR20,
VAR17,
VAR41);
input VAR38;
input VAR43;
input VAR31;
output [31 : 0] VAR24;
input [27 : 0] VAR34;
input [31 : 0] VAR46;
input VAR36;
output [31 : 0] VAR47;
input VAR60;
input VAR20;
input VAR17;
input VAR41;
wire [31 : 0] VAR47, VAR24... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o311ai/sky130_fd_sc_ms__o311ai_1.v | 2,435 | module MODULE1 (
VAR10 ,
VAR2 ,
VAR8 ,
VAR1 ,
VAR7 ,
VAR6 ,
VAR3,
VAR4,
VAR11 ,
VAR12
);
output VAR10 ;
input VAR2 ;
input VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR3;
input VAR4;
input VAR11 ;
input VAR12 ;
VAR5 VAR9 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR3(V... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_contrast_adj/solution1/impl/verilog/doHistStretch_fmul_32ns_32ns_32_4_max_dsp.v | 1,897 | module MODULE1
VAR24 = 1,
VAR6 = 4,
VAR20 = 32,
VAR19 = 32,
VAR16 = 32
)(
input wire clk,
input wire reset,
input wire VAR26,
input wire [VAR20-1:0] VAR25,
input wire [VAR19-1:0] VAR12,
output wire [VAR16-1:0] dout
);
wire VAR2;
wire VAR8;
wire VAR5;
wire [31:0] VAR17;
wire VAR15;
wire [31:0] VAR7;
wire VAR4;
wire [31:... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.symbol.v | 1,389 | module MODULE1 (
input VAR4,
input VAR7,
input VAR1,
input VAR8,
input VAR2,
output VAR9
);
supply1 VAR10;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
SymbiFlow/fpga-tool-perf | third_party/ibex/ibex_load_store_unit.v | 9,412 | module MODULE1 (
VAR61,
VAR17,
VAR62,
VAR26,
VAR24,
VAR21,
VAR42,
VAR1,
VAR47,
VAR56,
VAR2,
VAR53,
VAR27,
VAR58,
VAR38,
VAR63,
VAR28,
VAR46,
VAR43,
VAR50,
VAR48,
VAR34,
VAR11,
VAR13,
VAR22,
VAR9,
VAR33
);
localparam [2:0] VAR52 = 0;
localparam [2:0] VAR39 = 1;
localparam [2:0] VAR45 = 2;
localparam [2:0] VAR16 = 3;
loc... | isc |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/common/rtl/ctu_lib.v | 10,343 | module MODULE9(
VAR61,
VAR80, VAR33
);
parameter VAR38 = 1;
input VAR80;
input [VAR38-1:0] VAR33;
output [VAR38-1:0] VAR61;
wire [VAR38-1:0] VAR5;
VAR65 VAR22 [VAR38-1:0]
(.VAR75 (VAR33[VAR38-1:0]),
.VAR73 (VAR80),
.VAR81 (VAR61[VAR38-1:0])
);
endmodule
module MODULE12(
VAR61,
VAR21, VAR33
);
parameter VAR38 = 1;
input... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4bb/sky130_fd_sc_hdll__or4bb_4.v | 2,330 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR3,
VAR9,
VAR11 ,
VAR1
);
output VAR2 ;
input VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR3;
input VAR9;
input VAR11 ;
input VAR1 ;
VAR8 VAR6 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR11(VAR11),
.... | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/axi_dmac_resize_src.v | 3,303 | module MODULE1 #(
parameter VAR6 = 64,
parameter VAR3 = 64
) (
input clk,
input reset,
input VAR10,
input [VAR6-1:0] VAR9,
input VAR13,
output VAR2,
output [VAR3-1:0] VAR8,
output VAR11
);
generate if (VAR6 == VAR3) begin
assign VAR2 = VAR10;
assign VAR8 = VAR9;
assign VAR11 = VAR13;
end else begin
localparam VAR12 = V... | mit |
DreamSourceLab/DSLogic-hdl | src/dwrite.v | 5,810 | module MODULE1(
input VAR9,
input VAR32,
input VAR39,
input VAR3,
output VAR2,
input VAR8,
input VAR33,
input [31:0] VAR42,
input VAR13,
input VAR30,
input [15:0] VAR45,
output reg VAR43,
input VAR25,
output VAR44,
output reg [31:0] VAR1,
output [15:0] VAR18
);
wire VAR17;
wire [9:0] VAR36;
wire VAR40;
wire VAR14;
wire... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkinv/sky130_fd_sc_hs__clkinv_8.v | 1,909 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR4,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR4;
input VAR3;
VAR5 VAR6 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR4;
supply0 VAR3;
VAR5 VAR6 (
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi.pp.blackbox.v | 1,435 | module MODULE1 (
VAR7 ,
VAR10 ,
VAR4 ,
VAR6 ,
VAR8 ,
VAR3 ,
VAR5,
VAR1,
VAR9 ,
VAR2
);
output VAR7 ;
input VAR10 ;
input VAR4 ;
input VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR9 ;
input VAR2 ;
endmodule | apache-2.0 |
adbrant/zuma-fpga | verilog/generic/config_controller.v | 1,584 | module MODULE1
parameter VAR10 = 40,
parameter VAR4 = 16,
parameter VAR12 = 6
)
(
clk,
reset,
VAR18,
VAR5,
VAR22,
VAR3,
VAR7,
VAR17
);
input clk;
input reset;
input VAR18;
output [ VAR4-1:0] VAR5;
output [ VAR12-1:0] VAR3;
input [31:0] VAR22;
output VAR17;
output [15:0] VAR7;
wire VAR1;
reg [ VAR12-1:0] VAR20;
reg [15:... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221ai/sky130_fd_sc_hdll__o221ai.pp.blackbox.v | 1,444 | module MODULE1 (
VAR3 ,
VAR10 ,
VAR8 ,
VAR2 ,
VAR9 ,
VAR4 ,
VAR1,
VAR6,
VAR7 ,
VAR5
);
output VAR3 ;
input VAR10 ;
input VAR8 ;
input VAR2 ;
input VAR9 ;
input VAR4 ;
input VAR1;
input VAR6;
input VAR7 ;
input VAR5 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dmac_v1_00_a/hdl/verilog/src_fifo_inf.v | 4,348 | module MODULE1 (
input clk,
input VAR10,
input enable,
output VAR11,
input VAR30,
output VAR12,
input [VAR6-1:0] VAR19,
output [VAR6-1:0] VAR20,
input VAR26,
input en,
input [VAR1-1:0] din,
output reg VAR28,
input sync,
input VAR29,
output VAR3,
output [VAR1-1:0] VAR15,
input VAR31,
output VAR24,
input [3:0] VAR14,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb.behavioral.v | 1,882 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR1 ,
VAR15 ,
VAR2 ,
VAR13,
VAR14
);
output VAR12 ;
input VAR7 ;
input VAR1 ;
input VAR15 ;
input VAR2 ;
input VAR13;
input VAR14;
wire VAR2 VAR8 ;
wire VAR4 ;
wire VAR9;
nand VAR3 (VAR8 , VAR2, VAR15 );
or VAR11 (VAR4 , VAR1, VAR7, VAR8 );
VAR10 VAR6 (VAR9, VAR4, VAR13, VAR14);
buf VAR... | apache-2.0 |
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