repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb.functional.v | 1,427 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR2 ,
VAR5,
VAR9
);
output VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR5;
input VAR9;
wire VAR7 ;
wire VAR4;
nor VAR3 (VAR7 , VAR1, VAR2 );
and VAR6 (VAR4, VAR7, VAR5, VAR9);
buf VAR10 (VAR8 , VAR4 );
endmodule | apache-2.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/ogfx_reg_vram_if.v | 22,907 | module MODULE1 (
VAR8, VAR17, VAR31 VAR67
VAR81, VAR80
VAR49, VAR24,
VAR48, VAR7, VAR26, VAR86, VAR33,
VAR18, VAR25,
VAR19, VAR23, VAR9, VAR34, VAR63, VAR28,
VAR64, VAR71, VAR4, VAR53, VAR47, VAR11, VAR38,
VAR13, VAR12, VAR41 );
output [15:0] VAR8; output [15:0] VAR17; VAR31 VAR67
output [15:0] VAR81; VAR80
output [15:... | bsd-3-clause |
ptracton/wb_soc_template | rtl/MOR1KX/rtl/verilog/mor1kx_true_dpram_sclk.v | 1,424 | module MODULE1
parameter VAR11 = 32,
parameter VAR6 = 32
)
(
input clk,
input [VAR11-1:0] VAR4,
input VAR12,
input [VAR6-1:0] VAR13,
output [VAR6-1:0] VAR9,
input [VAR11-1:0] VAR3,
input VAR7,
input [VAR6-1:0] VAR1,
output [VAR6-1:0] VAR10
);
reg [VAR6-1:0] VAR5[(1<<VAR11)-1:0];
reg [VAR6-1:0] VAR2;
reg [VAR6-1:0] VAR8... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/ha/sky130_fd_sc_hd__ha.symbol.v | 1,274 | module MODULE1 (
input VAR8 ,
input VAR7 ,
output VAR5,
output VAR6
);
supply1 VAR2;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T26-rom/romleds2.v | 1,203 | module MODULE1 (input wire clk,
output wire [3:0] VAR11);
parameter VAR15 = VAR1;
parameter VAR12 = "VAR7.VAR10";
reg [3:0] addr;
reg VAR2 = 0;
wire VAR5;
VAR6 #(VAR12)
VAR4 (
.clk(clk),
.addr(addr),
.VAR8(VAR11)
);
always @(negedge clk)
if (VAR2 == 0)
addr <= 0;
else if (VAR5)
addr <= addr + 1;
VAR9 #(.VAR13(VAR15))
V... | gpl-2.0 |
revaldinho/opc | opc5/opc5system/uart.v | 1,983 | module MODULE1 ( input[15:0] din, output[15:0] dout, input VAR10, input VAR1, input clk, input VAR14, input VAR13, input VAR12, output VAR2);
parameter VAR17 = 32000000;
parameter VAR6 = 115200;
parameter VAR8 = VAR17 / VAR6;
reg [15:0] VAR15;
reg [15:0] VAR3;
reg [10:0] VAR18;
reg [9:0] VAR4;
reg VAR16;
reg VAR7;
assi... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21oi/sky130_fd_sc_hd__a21oi.pp.blackbox.v | 1,359 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR1 ,
VAR5 ,
VAR3,
VAR4,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR8 ;
input VAR1 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR6 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfstp/sky130_fd_sc_ms__sdfstp.blackbox.v | 1,418 | module MODULE1 (
VAR3 ,
VAR7 ,
VAR9 ,
VAR2 ,
VAR8 ,
VAR4
);
output VAR3 ;
input VAR7 ;
input VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR4;
supply1 VAR6;
supply0 VAR5;
supply1 VAR10 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/mem_ctrl.v | 16,409 | module MODULE1(
input VAR34, input VAR1, input [31:0] VAR18, input VAR57, output reg VAR2, input VAR60, output reg VAR44, input [31:0] VAR11, output reg [31:0] VAR51, input VAR42, output reg VAR41, input [31:0] VAR7, input [31:0] VAR47, input [31:0] VAR53, input [31:0] VAR37, input VAR17, input [255:0] VAR21, output re... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_cu_binari_tree.v | 40,796 | module MODULE1(
clk ,
VAR49 ,
VAR16 ,
VAR54 ,
VAR69 ,
VAR8 ,
VAR10 ,
VAR96 ,
VAR75 ,
VAR12 ,
VAR86 ,
VAR33 ,
VAR56 ,
VAR9 ,
VAR94 ,
VAR90 ,
VAR48 ,
VAR107 ,
VAR2 ,
VAR3 ,
VAR98 ,
VAR118 ,
VAR99 ,
VAR59 ,
VAR105 ,
VAR89
);
input clk ;
input VAR49 ;
input [6:0] VAR16 ;
input VAR54 ;
input [ 1:0 ] VAR69 ;
input VAR8 ; inp... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_jp_sstl_dq_bscan.v | 2,696 | module MODULE1(VAR39 ,VAR32 ,VAR16 ,VAR17 ,in
,VAR21 ,VAR1 ,VAR20 ,out ,VAR29 ,VAR11 ,VAR25 ,
VAR2 );
output VAR1 ;
output out ;
output VAR29 ;
input VAR39 ;
input VAR32 ;
input VAR16 ;
input VAR17 ;
input in ;
input VAR21 ;
input VAR20 ;
input VAR11 ;
input VAR25 ;
input VAR2 ;
wire VAR24 ;
wire VAR22 ;
wire VAR38 ;
w... | gpl-2.0 |
benreynwar/fpga-sdrlib | verilog/message/qa_debug.v | 1,645 | module MODULE1
parameter VAR6 = 32,
parameter VAR14 = 1
)
(
input wire clk,
input wire VAR20,
input wire [VAR6-1:0] VAR1,
input wire VAR4,
input wire [VAR14-1:0] VAR9,
input wire [VAR18-1:0] VAR7,
input wire VAR16,
output wire [VAR6-1:0] VAR2,
output wire VAR11,
output wire [VAR14-1:0] VAR21,
output wire [VAR18-1:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd3/sky130_fd_sc_ls__clkdlyinv5sd3.functional.pp.v | 1,867 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR8,
VAR2,
VAR3 ,
VAR11
);
output VAR5 ;
input VAR7 ;
input VAR8;
input VAR2;
input VAR3 ;
input VAR11 ;
wire VAR4 ;
wire VAR6;
not VAR1 (VAR4 , VAR7 );
VAR9 VAR10 (VAR6, VAR4, VAR8, VAR2);
buf VAR12 (VAR5 , VAR6 );
endmodule | apache-2.0 |
laanwj/yosys-ice-experiments | pmodoled2/uart.v | 4,704 | module MODULE2(
input wire clk,
input wire VAR29,
input wire [31:0] VAR21,
input wire VAR12,
output wire VAR19);
parameter VAR8 = 1000000;
parameter VAR23 = 25;
wire [VAR23-1:0] VAR15 = VAR8;
reg [VAR23-1:0] VAR25;
wire [VAR23-1:0] VAR26 = VAR25[VAR23-1] ? ({4'd0, VAR21}) : (({4'd0, VAR21}) - VAR15);
wire [VAR23-1:0] V... | mit |
mmicko/grom8 | grom_cpu.v | 20,856 | module MODULE1(
input clk,
input reset,
output reg [11:0] addr,
input [7:0] VAR24,
output reg [7:0] VAR10,
output reg VAR9,
output reg VAR39,
output reg VAR44
);
reg[11:0] VAR4 ; reg[7:0] VAR30 ; reg[7:0] VAR40 ; reg[3:0] VAR12 ; reg[3:0] VAR32 ; reg[11:0] VAR43 ; reg[7:0] VAR47[0:3] ; reg[11:0] VAR8 ;
localparam VAR33... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2.pp.symbol.v | 1,224 | module MODULE1 (
input VAR3 ,
input VAR5 ,
output VAR1 ,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
velizarefremov/Rijndael | aesmodule.v | 1,074 | module MODULE1(
output [127:0] out,
output ready,
input [127:0] in,
input VAR7,
input clk,
input reset
);
wire [3:0] VAR4;
wire [127:0] VAR5;
VAR1 VAR9( .out(out), .ready(ready), .VAR4(VAR4), .in(in), .VAR5(VAR5), .VAR7(VAR7), .clk(clk), .reset(reset));
VAR2 VAR3(.dout(VAR5), .VAR6(VAR4), .VAR8(clk), .en(1'b1));
endmod... | gpl-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_crc.v | 7,336 | module MODULE1 (VAR3, VAR7, VAR6, VAR2, VAR8, VAR4, VAR9);
parameter VAR5 = 1;
input VAR3;
input VAR7;
input [3:0] VAR6;
input VAR2;
input VAR8;
output [31:0] VAR4;
output VAR9;
reg [31:0] VAR4;
wire [31:0] VAR1;
assign VAR1[0] = VAR2 & (VAR6[0] ^ VAR4[28]);
assign VAR1[1] = VAR2 & (VAR6[1] ^ VAR6[0] ^ VAR4[28] ^ VAR4[... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a.blackbox.v | 1,389 | module MODULE1 (
VAR6 ,
VAR3,
VAR2,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR3;
input VAR2;
input VAR1 ;
input VAR4 ;
supply1 VAR8;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or2/sky130_fd_sc_hvl__or2.behavioral.pp.v | 1,783 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR13 ,
VAR10,
VAR2,
VAR1 ,
VAR5
);
output VAR7 ;
input VAR9 ;
input VAR13 ;
input VAR10;
input VAR2;
input VAR1 ;
input VAR5 ;
wire VAR6 ;
wire VAR11;
or VAR12 (VAR6 , VAR13, VAR9 );
VAR8 VAR4 (VAR11, VAR6, VAR10, VAR2);
buf VAR3 (VAR7 , VAR11 );
endmodule | apache-2.0 |
ncos/Xilinx-Verilog | GYRACC/src/GYRO/data_formatter.v | 2,975 | module MODULE1
(
input wire VAR6,
input wire VAR12,
input wire VAR16,
input wire [7:0] VAR27,
input wire [15:0] VAR21,
input wire [15:0] VAR25,
input wire [15:0] VAR3,
output wire [15:0] VAR13,
output wire [15:0] VAR2,
output wire [15:0] VAR29,
output wire [15:0] VAR23,
output wire [15:0] VAR15,
output wire [15:0] VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b_1.v | 2,147 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR4 ,
VAR9,
VAR2,
VAR3 ,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR2;
input VAR3 ;
input VAR6 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR7 ,
VAR5,
VAR4
);
output VAR7 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/decap/sky130_fd_sc_hs__decap_4.v | 1,745 | module MODULE1 (
VAR2,
VAR4
);
input VAR2;
input VAR4;
VAR3 VAR1 (
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR2;
supply0 VAR4;
VAR3 VAR1 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a311o/sky130_fd_sc_lp__a311o_4.v | 2,437 | module MODULE2 (
VAR2 ,
VAR9 ,
VAR7 ,
VAR3 ,
VAR8 ,
VAR11 ,
VAR10,
VAR6,
VAR1 ,
VAR12
);
output VAR2 ;
input VAR9 ;
input VAR7 ;
input VAR3 ;
input VAR8 ;
input VAR11 ;
input VAR10;
input VAR6;
input VAR1 ;
input VAR12 ;
VAR4 VAR5 (
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR10(... | apache-2.0 |
kylemsguy/FPGA-Litecoin-Miner | ICARUS-LX150/serial_hub.v | 1,178 | module MODULE1 # (
parameter VAR7 = 100000000,
parameter VAR9 = 115200
) (clk, VAR3, VAR10, VAR5);
input clk;
input VAR3;
wire VAR1;
wire [7:0] VAR13;
VAR6 #(.VAR7(VAR7), .VAR9(VAR9)) VAR4 (.clk(clk), .VAR2(VAR3), .VAR12(VAR1), .VAR8(VAR13));
output reg VAR5 = 0;
reg [31:0] VAR11;
output reg [31:0] VAR10 = 0;
reg [2:0]... | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ecc/mig_7series_v2_0_ecc_buf.v | 6,293 | module MODULE1
parameter VAR4 = 100,
parameter VAR35 = 64,
parameter VAR8 = 4,
parameter VAR37 = 1,
parameter VAR2 = 64,
parameter VAR26 = 4
)
(
VAR45,
clk, rst, VAR33, VAR24, VAR36,
VAR15, VAR31, VAR29
);
input clk;
input rst;
input [VAR8-1:0] VAR33;
input [VAR37-1:0] VAR24;
wire [4:0] VAR34;
input [VAR8-1:0] VAR36;
i... | bsd-2-clause |
jotego/jt12 | hdl/mixer/jt12_fm_uprate.v | 2,528 | module MODULE1(
input rst,
input clk,
input signed [15:0] VAR1,
input signed [11:0] VAR23,
input VAR12, input VAR13,
input VAR24,
input VAR10,
input VAR15,
output signed [15:0] VAR14 );
wire signed [15:0] VAR7,VAR3,VAR20;
reg [15:0] VAR19;
always @(posedge clk)
VAR19 <= (VAR12?VAR1:16'd0) + {{1{VAR23[11]}},VAR23,3'b0};... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fa/sky130_fd_sc_ls__fa.pp.symbol.v | 1,286 | module MODULE1 (
input VAR7 ,
input VAR2 ,
input VAR6 ,
output VAR9,
output VAR5 ,
input VAR1 ,
input VAR4,
input VAR8,
input VAR3
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/packet_verifier.v | 2,187 | module MODULE1
(input clk, input reset, input VAR21,
input [7:0] VAR1, input VAR17, input VAR12, input VAR4, output VAR25,
output reg [31:0] VAR7,
output reg [31:0] VAR3,
output reg [31:0] VAR19,
output reg [31:0] VAR2);
reg [31:0] VAR24;
reg [31:0] VAR22;
wire VAR16, VAR8;
reg VAR6, VAR15;
wire VAR5;
wire VAR9 = VAR4 ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.behavioral.v | 1,516 | module MODULE1 (
VAR1 ,
VAR8,
VAR13,
VAR10
);
output VAR1 ;
input VAR8;
input VAR13;
input VAR10;
supply1 VAR12;
supply0 VAR7;
supply1 VAR4 ;
supply0 VAR3 ;
wire VAR6 ;
wire VAR11;
and VAR2 (VAR6 , VAR8, VAR13 );
nor VAR5 (VAR11, VAR10, VAR6 );
buf VAR9 (VAR1 , VAR11 );
endmodule | apache-2.0 |
p4fpga/p4fpga | src/bsv/library/AsymmetricBRAM/AsymmetricBRAM_Xilinx.v | 1,461 | module MODULE1(
VAR31,
VAR7,
VAR22,
VAR15,
VAR30,
VAR29,
VAR10
);
parameter VAR5 = 'VAR11 0;
parameter VAR20 = 'VAR11 0;
parameter VAR13 = 'VAR11 0;
parameter VAR32 = 'VAR11 0;
parameter VAR19 = 'VAR11 0;
parameter VAR17 = 'VAR11 0;
parameter VAR25 = 'VAR11 1;
parameter VAR18 = (VAR5 == 0) ? "VAR27":"VAR8";
input VAR31... | bsd-2-clause |
eda-globetrotter/PicenoDecoders | zhiyang_and_andrew/syn/src/z.v | 2,084 | module MODULE1();
integer VAR2;
reg clk;
reg VAR1[0:13];
always begin
clk = 0;
clk = 1; end
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd1/sky130_fd_sc_hdll__dlygate4sd1.blackbox.v | 1,296 | module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR4;
supply0 VAR2;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
antmicro/yosys | techlibs/common/cmp2lcu.v | 5,260 | module 80lcucmp (VAR16, VAR17, VAR30);
parameter VAR19 = 0;
parameter VAR8 = 0;
parameter VAR2 = 0;
parameter VAR26 = 0;
parameter VAR28 = 0;
input [VAR2-1:0] VAR16;
input [VAR26-1:0] VAR17;
output [VAR28-1:0] VAR30;
parameter VAR14 = "";
generate
if (VAR14 == "" || VAR20 < 2)
wire VAR9 = 1;
else if (VAR14 == "VAR23") ... | isc |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/FIFO_image_filter_p_src_cols_V_channel1.v | 3,023 | module MODULE1 (
clk,
VAR16,
VAR26,
VAR12,
VAR10);
parameter VAR23 = 32'd12;
parameter VAR24 = 32'd2;
parameter VAR15 = 32'd3;
input clk;
input [VAR23-1:0] VAR16;
input VAR26;
input [VAR24-1:0] VAR12;
output [VAR23-1:0] VAR10;
reg[VAR23-1:0] VAR1 [0:VAR15-1];
integer VAR6;
always @ (posedge clk)
begin
if (VAR26)
begin
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/xor2/sky130_fd_sc_hvl__xor2.behavioral.pp.v | 1,823 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR12 ,
VAR9,
VAR10,
VAR4 ,
VAR13
);
output VAR1 ;
input VAR5 ;
input VAR12 ;
input VAR9;
input VAR10;
input VAR4 ;
input VAR13 ;
wire VAR8 ;
wire VAR6;
xor VAR3 (VAR8 , VAR12, VAR5 );
VAR2 VAR7 (VAR6, VAR8, VAR9, VAR10);
buf VAR11 (VAR1 , VAR6 );
endmodule | apache-2.0 |
jkanasu/utl | lab14eve16/fpga/j07b_asynchronouscounter.v | 1,103 | module MODULE1(VAR5,VAR9,clk,rst,VAR1);
output reg VAR5;
output VAR9;
input clk, rst;
input VAR1;
assign VAR9 = ~VAR5;
always @(posedge clk, posedge rst)
begin
if (rst)
VAR5 <= 0;
end
else
VAR5 <= VAR1;
end
endmodule
module MODULE2(VAR6,VAR8,clk,rst);
input clk, rst;
output [3:0] VAR6, VAR8;
MODULE1 MODULE4(VAR6[0],VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4bb/sky130_fd_sc_hd__nor4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR5 ,
input VAR4 ,
input VAR7 ,
input VAR2 ,
output VAR1 ,
input VAR3 ,
input VAR9,
input VAR8,
input VAR6
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_nonsynth_mem_1rw_sync_mask_write_byte_assoc.v | 1,145 | module MODULE1
, parameter VAR9(VAR8)
, parameter VAR6=(VAR2>>3)
)
(
input VAR13
, input VAR4
, input VAR5
, input VAR14
, input [VAR8-1:0] VAR15
, input [VAR2-1:0] VAR17
, input [VAR6-1:0] VAR1
, output [VAR2-1:0] VAR12
);
for (genvar VAR10 = 0; VAR10 < VAR6; VAR10++) begin: VAR16
VAR3 #(
.VAR8(VAR8)
,.VAR7(8)
) VAR11... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4bb/sky130_fd_sc_lp__nor4bb.behavioral.v | 1,523 | module MODULE1 (
VAR11 ,
VAR8 ,
VAR10 ,
VAR14,
VAR9
);
output VAR11 ;
input VAR8 ;
input VAR10 ;
input VAR14;
input VAR9;
supply1 VAR5;
supply0 VAR7;
supply1 VAR12 ;
supply0 VAR13 ;
wire VAR6 ;
wire VAR2;
nor VAR1 (VAR6 , VAR8, VAR10 );
and VAR3 (VAR2, VAR6, VAR14, VAR9);
buf VAR4 (VAR11 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_isobufsrc/sky130_fd_sc_hd__lpflow_isobufsrc.symbol.v | 1,421 | module MODULE1 (
input VAR1 ,
output VAR2 ,
input VAR7
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.behavioral.pp.v | 1,940 | module MODULE1 (
VAR5 ,
VAR7 ,
VAR11 ,
VAR13 ,
VAR4,
VAR10 ,
VAR3
);
output VAR5 ;
input VAR7 ;
input VAR11 ;
input VAR13 ;
input VAR4;
input VAR10 ;
input VAR3 ;
wire VAR8 ;
wire VAR12;
buf VAR2 (VAR8 , VAR7 );
VAR6 VAR1 (VAR12, VAR8, VAR4, VAR13);
buf VAR9 (VAR5 , VAR12 );
endmodule | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/NIOS_Sys/synthesis/submodules/NIOS_Sys_timer.v | 6,907 | module MODULE1 (
address,
VAR19,
clk,
VAR20,
VAR8,
VAR14,
irq,
VAR1
)
;
output irq;
output [ 15: 0] VAR1;
input [ 2: 0] address;
input VAR19;
input clk;
input VAR20;
input VAR8;
input [ 15: 0] VAR14;
wire VAR13;
wire VAR32;
wire VAR17;
reg [ 3: 0] VAR16;
wire VAR2;
reg VAR15;
wire VAR27;
wire [ 31: 0] VAR12;
reg [ 31: ... | gpl-2.0 |
mithro/soft-utmi | hdl/third_party/XAPP1064-serdes-macros/Verilog_Source/Macros/serdes_n_to_1_ddr_s8_diff.v | 8,930 | module MODULE1 (VAR61, VAR19, VAR63, reset, VAR22, VAR60, VAR34, VAR52) ;
parameter integer VAR53 = 8 ; parameter integer VAR1 = 16 ;
input VAR61 ; input VAR19 ; input VAR63 ; input reset ; input VAR22 ; input [(VAR1*VAR53)-1:0] VAR60 ; output [VAR1-1:0] VAR34 ; output [VAR1-1:0] VAR52 ;
wire [VAR1:0] VAR7 ; wire [VAR1... | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/example_design/PIO_EP.v | 8,636 | module MODULE1 #(
parameter VAR35 = 64,
parameter VAR4 = VAR35 / 8, parameter VAR7 = 1
) (
input clk,
input VAR46,
input VAR18,
output [VAR35-1:0] VAR40,
output [VAR4-1:0] VAR20,
output VAR33,
output VAR25,
output VAR28,
input [VAR35-1:0] VAR13,
input [VAR4-1:0] VAR3,
input VAR10,
input VAR1,
output VAR14,
input [21:0]... | lgpl-3.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/dependencies/uart_controller.v | 6,643 | module MODULE1 #(
parameter VAR32 = 115200
)(
input clk,
input rst,
input VAR48,
output VAR9,
output reg VAR45,
input VAR15,
input VAR20,
input VAR53,
output [31:0] VAR30,
input VAR55,
input [31:0] VAR21,
output [31:0] VAR18,
input VAR22,
input [7:0] VAR50,
output VAR8,
output [31:0] VAR31,
output wire [31:0] VAR41,
ou... | mit |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_axi_basic_rx.v | 8,271 | module MODULE1 #(
parameter VAR34 = 128, parameter VAR1 = "VAR19", parameter VAR17 = "VAR15", parameter VAR5 = "VAR15", parameter VAR16 = 1,
parameter VAR27 = (VAR34 == 128) ? 2 : 1, parameter VAR2 = VAR34 / 8 ) (
output [VAR34-1:0] VAR25, output VAR37, input VAR11, output [VAR2-1:0] VAR35, output VAR22, output [21:0] ... | mit |
mballance/oc_wb_ip | rtl/wb_dma/rtl/verilog/wb_dma_de.v | 20,583 | module MODULE1(clk, rst,
VAR97, VAR12, VAR29, VAR96, VAR13,
VAR24, VAR74, VAR58, VAR78,
VAR85, VAR34, VAR38, VAR70, VAR15,
VAR31, VAR20, VAR55, VAR93,
VAR21, VAR99, VAR43, VAR22, VAR66, VAR61,
VAR62, VAR33, VAR82, VAR48,
VAR40, VAR19, VAR76, VAR10, VAR87,
VAR8, VAR80, VAR86, VAR101, VAR42,
VAR92, VAR32,
VAR84, VAR7,
VA... | apache-2.0 |
johan92/yafpgatetris | ip_cores/ps2_keyboard/Altera_UP_PS2_Data_In.v | 5,868 | module MODULE1 (
clk,
reset,
VAR12,
VAR7,
VAR6,
VAR4,
VAR14,
VAR16,
VAR5 );
input clk;
input reset;
input VAR12;
input VAR7;
input VAR6;
input VAR4;
input VAR14;
output reg [7:0] VAR16;
output reg VAR5;
localparam VAR2 = 3'h0,
VAR11 = 3'h1,
VAR8 = 3'h2,
VAR10 = 3'h3,
VAR13 = 3'h4;
reg [3:0] VAR3;
reg [7:0] VAR9;
reg [2... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfbbn/sky130_fd_sc_lp__sdfbbn.behavioral.pp.v | 3,448 | module MODULE1 (
VAR24 ,
VAR38 ,
VAR25 ,
VAR7 ,
VAR34 ,
VAR27 ,
VAR32 ,
VAR8,
VAR29 ,
VAR1 ,
VAR22 ,
VAR17
);
output VAR24 ;
output VAR38 ;
input VAR25 ;
input VAR7 ;
input VAR34 ;
input VAR27 ;
input VAR32 ;
input VAR8;
input VAR29 ;
input VAR1 ;
input VAR22 ;
input VAR17 ;
wire VAR23 ;
wire VAR16 ;
wire VAR4 ;
wire V... | apache-2.0 |
8l/kestrel | 2/nexys2/uxa/mgia/M_uxa_mgia.v | 1,551 | module MODULE1(
input VAR4,
input VAR53,
output VAR10,
output VAR52,
output VAR44,
output [2:0] VAR54,
output [2:0] VAR1,
output [2:1] VAR8,
output [13:1] VAR55,
input [15:0] VAR3,
output VAR16,
output VAR2,
input VAR27
);
wire VAR26;
wire VAR15;
wire VAR29;
wire VAR40;
wire VAR42;
wire [ 5:0] VAR51;
wire [15:0] VAR39;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.functional.pp.v | 2,125 | module MODULE1( VAR21, VAR16, VAR20, VAR25, VAR5, VAR27, VAR10, VAR17 );
input VAR5, VAR27, VAR20, VAR16, VAR25;
inout VAR10, VAR17;
output VAR21;
wire VAR3;
not VAR26( VAR3, VAR5 );
wire VAR2;
not VAR6( VAR2, VAR20 );
wire VAR15;
not VAR1( VAR15, VAR25 );
wire VAR19;
and VAR7( VAR19, VAR3, VAR2, VAR15 );
wire VAR13;
n... | apache-2.0 |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | project/Predefined/2Ch8Way-1.0.0/OpenSSD2_2Ch8Way-1.0.0/OpenSSD2.srcs/sources_1/ipshared/ENCLab/V2NFC100DDR_v1_0_0/81152d2e/src/NPM_Toggle_POR.v | 5,348 | module MODULE1
(
VAR3 ,
VAR10 ,
VAR17 ,
VAR4 ,
VAR2 ,
VAR6
);
input VAR3 ;
input VAR10 ;
output VAR17 ;
output VAR4 ;
input VAR2 ;
output VAR6 ;
parameter VAR11 = 4;
parameter VAR7 = 4'b0001;
parameter VAR8 = 4'b0010;
parameter VAR12 = 4'b0100; parameter VAR16 = 4'b1000;
reg [VAR11-1:0] VAR1 ;
reg [VAR11-1:0] VAR14 ;
r... | gpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ethernet_port_interface_0.v | 16,573 | module MODULE1 (
input wire clk, input wire reset, input wire [26:0] VAR46, input wire VAR19, output wire [31:0] VAR30, input wire VAR11, input wire [31:0] VAR62, output wire VAR18, input wire [7:0] VAR29, output wire VAR78, input wire VAR64, input wire [5:0] VAR31, input wire VAR77, input wire VAR28, input wire [7:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/diode/sky130_fd_sc_hd__diode.behavioral.pp.v | 1,200 | module MODULE1 (
VAR2,
VAR3 ,
VAR4 ,
VAR5 ,
VAR1
);
input VAR2;
input VAR3 ;
input VAR4 ;
input VAR5 ;
input VAR1 ;
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/atlas_linux_ghrd/soc_system/synthesis/submodules/soc_system_hps_0_hps_io.v | 10,563 | module MODULE1 (
output wire [14:0] VAR28, output wire [2:0] VAR56, output wire VAR4, output wire VAR62, output wire VAR7, output wire VAR15, output wire VAR58, output wire VAR11, output wire VAR50, output wire VAR49, inout wire [31:0] VAR66, inout wire [3:0] VAR61, inout wire [3:0] VAR63, output wire VAR44, output wir... | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_mini/spi.v | 3,079 | module MODULE1(
input clk,
input VAR11,
input VAR21,
inout VAR12,
input VAR7,
output VAR15,
output VAR5,
output [7:0] VAR30,
output [7:0] VAR31,
input [7:0] VAR2,
output [31:0] VAR4,
output [2:0] VAR18
);
reg [7:0] VAR6;
reg [7:0] VAR14;
reg [2:0] VAR24;
reg [2:0] VAR19;
always @(posedge clk) VAR24 <= {VAR24[1:0], VAR7... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/ebufn/sky130_fd_sc_hs__ebufn.symbol.v | 1,297 | module MODULE1 (
input VAR3 ,
output VAR2 ,
input VAR4
);
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
bigeagle/riffa | fpga/altera/de5/DE5Gen1x8If64/hdl/DE5Gen1x8If64.v | 23,796 | module MODULE1
parameter VAR186 = 8,
parameter VAR81 = 64,
parameter VAR176 = 256,
parameter VAR57 = 5
)
(
output [7:0] VAR78,
input VAR38,
input VAR97,
input [VAR186-1:0] VAR76,
output [VAR186-1:0] VAR205,
input VAR22
);
wire VAR103;
wire VAR172;
wire [11:0] VAR133;
wire [31:0] VAR41;
wire VAR173;
wire VAR111;
wire VA... | bsd-3-clause |
olgirard/openmsp430 | core/synthesis/altera/src/openMSP430_fpga.v | 9,352 | module MODULE1 (
VAR43, VAR41, VAR34, VAR37, VAR27, VAR48, VAR1, VAR45, VAR25,
VAR16, VAR20, irq, VAR10, VAR14, VAR2, VAR9 );
output VAR43; output VAR41; output VAR34; output [13:0] VAR37; output [7:0] VAR27; output [15:0] VAR48; output [1:0] VAR1; output VAR45; output VAR25;
input VAR16; input VAR20; input [13:0] irq;... | bsd-3-clause |
AbhishekShah212/School_Projects | ELEN232/pset4/Problem2.v | 1,942 | module MODULE1(
input [7:0] VAR1,
input VAR2,
output reg VAR3,
output reg VAR5,
output reg [2:0] VAR4
);
always @ (VAR1, VAR2)
begin
if (VAR2 == 0) begin
VAR3 = 0;
VAR5 = 0;
VAR4 = 3'b000;
end
else
begin
if (VAR1 == 8'b00000000) begin
VAR5 = 0;
VAR3 = 1;
VAR4 = 3'b000;
end
else
begin
VAR5 = 1;
VAR3 = 0; if (VAR1[7] == ... | mit |
ShirmanXia/EE469SPRING16 | lab4/db/ip/nios_system/submodules/nios_system_nios2_qsys_0_jtag_debug_slave_wrapper.v | 10,524 | module MODULE1 (
VAR60,
VAR22,
clk,
VAR48,
VAR55,
VAR21,
VAR58,
VAR25,
VAR37,
VAR41,
VAR30,
VAR34,
VAR59,
VAR20,
VAR31,
VAR18,
VAR6,
VAR1,
VAR11,
VAR24,
VAR4,
VAR8,
VAR13,
VAR26,
VAR12,
VAR14,
VAR32,
VAR45,
VAR33,
VAR5,
VAR2,
VAR43,
VAR10,
VAR53,
VAR39,
VAR28
)
;
output [ 37: 0] VAR4;
output VAR8;
output VAR13;
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2hv_hl/sky130_fd_sc_hvl__lsbufhv2hv_hl.blackbox.v | 1,390 | module MODULE1 (
VAR5,
VAR7
);
output VAR5;
input VAR7;
supply1 VAR6 ;
supply0 VAR2 ;
supply1 VAR1;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufbuf/sky130_fd_sc_ms__bufbuf.functional.pp.v | 1,768 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR8,
VAR5,
VAR11 ,
VAR7
);
output VAR6 ;
input VAR4 ;
input VAR8;
input VAR5;
input VAR11 ;
input VAR7 ;
wire VAR9 ;
wire VAR3;
buf VAR12 (VAR9 , VAR4 );
VAR10 VAR2 (VAR3, VAR9, VAR8, VAR5);
buf VAR1 (VAR6 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4bb/sky130_fd_sc_ls__nor4bb.blackbox.v | 1,332 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR3 ,
VAR9,
VAR1
);
output VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR9;
input VAR1;
supply1 VAR4;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/verilog/HLS_accel_fpext_32ns_64_1.v | 1,153 | module MODULE1
VAR4 = 6,
VAR7 = 1,
VAR15 = 32,
VAR5 = 64
)(
input wire [VAR15-1:0] VAR16,
output wire [VAR5-1:0] dout
);
wire VAR11;
wire [31:0] VAR1;
wire VAR10;
wire [63:0] VAR12;
VAR3 VAR8 (
.VAR6 ( VAR11 ),
.VAR9 ( VAR1 ),
.VAR2 ( VAR10 ),
.VAR13 ( VAR12 )
);
assign VAR11 = 1'b1;
assign VAR1 = VAR16==='VAR14 ? 'b0 ... | mit |
strigeus/fpganes | src/apu.v | 25,900 | module MODULE2(input [4:0] VAR35, output [7:0] VAR29);
reg [6:0] VAR16;
always @*
begin
case(VAR35)
0: VAR16 = 7'h05;
1: VAR16 = 7'h7F;
2: VAR16 = 7'h0A;
3: VAR16 = 7'h01;
4: VAR16 = 7'h14;
5: VAR16 = 7'h02;
6: VAR16 = 7'h28;
7: VAR16 = 7'h03;
8: VAR16 = 7'h50;
9: VAR16 = 7'h04;
10: VAR16 = 7'h1E;
11: VAR16 = 7'h05;
12... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a222o/sky130_fd_sc_hs__a222o.pp.symbol.v | 1,386 | module MODULE1 (
input VAR8 ,
input VAR7 ,
input VAR4 ,
input VAR5 ,
input VAR9 ,
input VAR6 ,
output VAR1 ,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.behavioral.v | 1,821 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR1
);
output VAR11 ;
input VAR4 ;
input VAR1;
supply1 VAR9;
supply0 VAR8;
supply1 VAR10 ;
supply0 VAR6 ;
wire VAR2 ;
wire VAR12;
wire VAR15 ;
reg VAR5 ;
wire VAR3 ;
VAR7 VAR14 (VAR2 , VAR15, VAR12, VAR5, VAR9, VAR8);
buf VAR13 (VAR11 , VAR2 );
assign VAR3 = ( VAR9 === 1'b1 );
endmodule | apache-2.0 |
twlostow/dsi-shield | hdl/rtl/hpdmc/spartan6/hpdmc_ddrio.v | 6,239 | module MODULE1 (
input VAR94,
input VAR53,
input VAR27,
input [3:0] VAR84,
input [31:0] do,
output [31:0] VAR31,
output [1:0] VAR16,
inout [15:0] VAR70,
inout [1:0] VAR17,
output VAR75,
output VAR11,
input VAR89,
input VAR36,
input VAR18,
input VAR47
);
parameter VAR85 = 0;
parameter VAR35 = 0;
parameter VAR21 = 0;
wir... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.behavioral.v | 1,611 | module MODULE1 (
VAR9 ,
VAR7,
VAR3,
VAR8,
VAR16
);
output VAR9 ;
input VAR7;
input VAR3;
input VAR8;
input VAR16;
supply1 VAR11;
supply0 VAR15;
supply1 VAR5 ;
supply0 VAR2 ;
wire VAR4 ;
wire VAR14 ;
wire VAR6;
and VAR13 (VAR4 , VAR8, VAR16 );
and VAR10 (VAR14 , VAR7, VAR3 );
or VAR1 (VAR6, VAR14, VAR4);
buf VAR12 (VAR9... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor3/gf180mcu_fd_sc_mcu9t5v0__nor3_4.functional.pp.v | 1,235 | module MODULE1( VAR1, VAR13, VAR2, VAR5, VAR4, VAR12 );
input VAR5, VAR1, VAR2;
inout VAR4, VAR12;
output VAR13;
wire VAR10;
not VAR8( VAR10, VAR5 );
wire VAR11;
not VAR7( VAR11, VAR1 );
wire VAR3;
not VAR6( VAR3, VAR2 );
and VAR9( VAR13, VAR10, VAR11, VAR3 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9671/axi_ad9671_channel.v | 5,886 | module MODULE1 (
VAR69,
VAR18,
VAR52,
VAR62,
VAR33,
VAR65,
VAR48,
VAR12,
VAR27,
VAR47,
VAR20,
VAR68,
VAR54,
VAR37,
VAR6,
VAR36,
VAR29,
VAR11,
VAR28,
VAR38,
VAR55);
parameter VAR44 = 0;
input VAR69;
input VAR18;
input VAR52;
input [15:0] VAR62;
input VAR33;
output VAR65;
output [15:0] VAR48;
output VAR12;
output VAR27;
... | gpl-3.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,705 | module MODULE1 (
clk,
reset,
VAR10,
VAR6,
VAR11,
VAR8,
VAR3,
VAR13
);
parameter VAR2 = 1;
parameter VAR4 = 8;
parameter VAR9 = 1;
localparam VAR15 = VAR2 * VAR4;
input clk;
input reset;
output VAR10;
input VAR6;
input [VAR15-1:0] VAR11;
input VAR8;
output VAR3;
output [VAR15-1:0] VAR13;
reg VAR5;
reg VAR16;
reg [VAR15-... | apache-2.0 |
yht1995/Digital-WeighingScale | FPGA/output_files/altpll0_bb.v | 10,680 | module MODULE1 (
VAR1,
VAR2);
input VAR1;
output VAR2;
endmodule | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpaddsub_arch2/LZD.v | 2,226 | module MODULE1#(parameter VAR8=26, parameter VAR13=5)(
input wire clk,
input wire rst,
input wire VAR3,
input wire [VAR8-1:0] VAR17,
output wire [VAR13-1:0] VAR12
);
wire [VAR13-1:0] VAR5;
generate
case (VAR8)
26:begin : VAR1
VAR18 VAR15(
.VAR2(VAR17),
.VAR14(VAR5)
);
end
55:begin : VAR4
VAR20 VAR10(
.VAR2(VAR17),
.VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.pp.symbol.v | 1,352 | module MODULE1 (
input VAR1 ,
input VAR4 ,
input VAR8 ,
output VAR7 ,
input VAR2 ,
input VAR5,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
jairov4/puj-ca-de1-audio-pump | ip/Binary_VGA_Controller/hdl/Img_RAM.v | 9,088 | module MODULE1 (
VAR25,
VAR22,
VAR2,
VAR6,
VAR43,
VAR60,
VAR52);
input [0:0] VAR25;
input VAR22;
input [18:0] VAR2;
input [15:0] VAR6;
input VAR43;
input VAR60;
output [7:0] VAR52;
wire [7:0] VAR37;
wire [7:0] VAR52 = VAR37[7:0];
VAR55 VAR53 (
.VAR50 (VAR22),
.VAR61 (VAR43),
.VAR30 (VAR60),
.VAR40 (VAR2),
.VAR34 (VAR6)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/buf/sky130_fd_sc_hs__buf_8.v | 1,866 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR1,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR1;
input VAR2;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6,
VAR5
);
output VAR6;
input VAR5;
supply1 VAR1;
supply0 VAR2;
VAR4 VAR3 (
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule | apache-2.0 |
juan199/Lab_Digitales | Proyecto/registers.v | 7,525 | module MODULE1(
input wire VAR4,
input wire [17:0] VAR11,
input wire [15:0] VAR38,
output wire [11:0] VAR16,
output wire VAR3,
input wire VAR33,
input wire VAR29,
input wire VAR41,
input wire VAR25,
input wire VAR18,
input wire VAR35,
input wire VAR39,
input wire VAR10,
input wire VAR22,
input wire VAR44,
input wire VA... | lgpl-3.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/ip/Gaussian_Filter/acl_optimized_clz_27.v | 1,322 | module MODULE1(VAR3, VAR5);
input [31:0] VAR3;
output [31:0] VAR5;
wire VAR2;
VAR6 VAR4( .VAR1(VAR3[26:0]),
.VAR5(VAR5[4:0]),
.VAR2(VAR2));
assign VAR5[5] = VAR2;
assign VAR5[31:6] = 26'd0;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2111o/sky130_fd_sc_ms__a2111o.behavioral.pp.v | 2,070 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR16 ,
VAR5 ,
VAR14 ,
VAR2 ,
VAR8,
VAR15,
VAR18 ,
VAR1
);
output VAR4 ;
input VAR11 ;
input VAR16 ;
input VAR5 ;
input VAR14 ;
input VAR2 ;
input VAR8;
input VAR15;
input VAR18 ;
input VAR1 ;
wire VAR17 ;
wire VAR6 ;
wire VAR12;
and VAR7 (VAR17 , VAR11, VAR16 );
or VAR9 (VAR6 , VAR14, V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkinv/gf180mcu_fd_sc_mcu7t5v0__clkinv_1.behavioral.pp.v | 1,182 | module MODULE1( VAR4, VAR5, VAR2, VAR7 );
input VAR4;
inout VAR2, VAR7;
output VAR5;
VAR3 VAR6(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7));
VAR3 VAR1(.VAR4(VAR4),.VAR5(VAR5),.VAR2(VAR2),.VAR7(VAR7)); | apache-2.0 |
jobisoft/jTDC | modules/tdc/jTDC_modules.v | 13,291 | module MODULE2 (VAR130,VAR45,VAR116,VAR53,VAR87,VAR16,VAR67,VAR24,VAR25,VAR122,VAR124,VAR133,VAR46,VAR107,VAR91,VAR103);
parameter VAR64 = 16;
input wire [VAR64-1:0] VAR130;
input wire [VAR64-1:0] VAR45;
input wire [VAR64-1:0] VAR116;
input wire [VAR64-1:0] VAR53;
input wire [VAR64-1:0] VAR87;
input wire [VAR64-1:0] VA... | gpl-3.0 |
rurume/openrisc_vision_hardware | ISE/or1200_alu.v | 12,751 | module MODULE1(
VAR12, VAR21, VAR2, VAR9,
VAR31, VAR19, VAR18,
VAR37, VAR33,
VAR13, VAR15, VAR17,
VAR6, VAR23, VAR16, flag
);
parameter VAR29 = VAR30;
input [VAR29-1:0] VAR12;
input [VAR29-1:0] VAR21;
input [VAR29-1:0] VAR2;
input VAR9;
input [VAR8-1:0] VAR31;
input [VAR3-1:0] VAR19;
input [VAR38-1:0] VAR18;
input [4:0... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/fifo.v | 7,420 | module MODULE1
parameter VAR33 = 32, parameter VAR28 = 1024, parameter VAR11 = 2
)
(
input VAR30, input VAR20,
input [VAR33-1:0] VAR44, input VAR14, output VAR40,
output [VAR33-1:0] VAR34, input VAR12, output VAR27 );
localparam VAR26 = 2**VAR2(VAR28);
localparam VAR25 = VAR18(VAR26);
wire [VAR11:0] VAR6;
wire VAR1;
wi... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_babasu/spw_babasu/synthesis/submodules/spw_babasu_hps_0_hps_io.v | 1,925 | module MODULE1 (
output wire [12:0] VAR17, output wire [2:0] VAR6, output wire VAR12, output wire VAR7, output wire VAR3, output wire VAR13, output wire VAR2, output wire VAR4, output wire VAR14, output wire VAR5, inout wire [7:0] VAR9, inout wire VAR10, inout wire VAR18, output wire VAR11, output wire VAR1, input wire... | gpl-3.0 |
fpgasystems/caribou | hw/src/regex/rem_halfrange.v | 2,585 | module MODULE1 #(parameter VAR11=0)
(
clk,
rst,
VAR14,
VAR7,
VAR8,
VAR2,
VAR9,
VAR13,
VAR12,
VAR3,
VAR6,
VAR5
);
input clk;
input rst;
input VAR14;
input [7:0] VAR7;
input VAR8;
input VAR2;
input VAR9;
input [7:0] VAR13;
input VAR12;
input VAR6; output VAR3;
output VAR5;
reg VAR1;
reg [7:0] VAR4;
reg VAR10;
reg VAR15;
... | gpl-3.0 |
ama142/Zynq-SoC-Training | lab3/Source Code/ZedboardOLED_v1_0.v | 4,214 | module MODULE1 #
(
parameter integer VAR25 = 32,
parameter integer VAR17 = 7
)
(
output wire VAR49,
output wire VAR44,
output wire VAR31,
output wire VAR48,
output wire VAR12,
output wire VAR40,
input wire VAR15,
input wire VAR6,
input wire [VAR17-1 : 0] VAR29,
input wire [2 : 0] VAR23,
input wire VAR43,
output wire VA... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4_0.v | 2,231 | module MODULE2 (
VAR2 ,
VAR1 ,
VAR8 ,
VAR6 ,
VAR5 ,
VAR10,
VAR9,
VAR3 ,
VAR11
);
output VAR2 ;
input VAR1 ;
input VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR10;
input VAR9;
input VAR3 ;
input VAR11 ;
VAR4 VAR7 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_ccat/util_ccat.v | 3,732 | module MODULE1 (
VAR4,
VAR10,
VAR2,
VAR13,
VAR9,
VAR5,
VAR11,
VAR7,
VAR1);
parameter VAR6 = 1;
parameter VAR12 = 8;
localparam VAR3 = 8;
input [(VAR6-1):0] VAR4;
input [(VAR6-1):0] VAR10;
input [(VAR6-1):0] VAR2;
input [(VAR6-1):0] VAR13;
input [(VAR6-1):0] VAR9;
input [(VAR6-1):0] VAR5;
input [(VAR6-1):0] VAR11;
input... | gpl-3.0 |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/ise/ipcore_dir/dram/user_design/rtl/ip_top/mig_7series_v1_9_mem_intfc.v | 40,945 | module MODULE1 #
(
parameter VAR235 = 100,
parameter VAR23 = 64,
parameter VAR17 = "1T",
parameter VAR118 = "0", parameter VAR115 = 3, parameter VAR170 = 2, parameter VAR298 = "8", parameter VAR175 = "VAR226", parameter VAR230 = "VAR290", parameter VAR220 = 1, parameter VAR145 = 4'hc,
parameter VAR162 = 4'hf,
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b.functional.pp.v | 1,898 | module MODULE1 (
VAR9,
VAR14,
VAR12 ,
VAR4 ,
VAR6 ,
VAR13
);
input VAR9;
input VAR14;
output VAR12 ;
input VAR4 ;
input VAR6 ;
input VAR13 ;
wire VAR10 ;
wire VAR1 ;
wire VAR5;
not VAR7 (VAR10 , VAR4 );
nand VAR2 (VAR1 , VAR6, VAR10, VAR13 );
VAR8 VAR3 (VAR5, VAR1, VAR9, VAR14);
buf VAR11 (VAR12 , VAR5 );
endmodule | apache-2.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab11/lab11/Code/CPU/MCtrl.v | 5,787 | module MODULE1(input clk,
input reset,
input [31:0] VAR34,
input VAR19,
input VAR54,
input VAR68,
output reg VAR6,
output reg VAR42,
output [2:0]VAR43,
output [4:0]VAR55,
output reg VAR53,
output reg VAR31,
output reg VAR39,
output reg [1:0]VAR26,
output reg VAR73,
output reg [1:0]VAR44,
output reg VAR69,
output reg [1... | gpl-3.0 |
horia141/bachelor-thesis | prj/components/Swc/Swc.v | 8,500 | module MODULE1(VAR7,reset,VAR9,VAR13,counter,ready);
input wire VAR7;
input wire reset;
input wire [11:0] VAR9;
input wire VAR13;
output wire [23:0] counter;
output wire ready;
reg [1:0] VAR34;
reg [3:0] VAR8;
reg [23:0] VAR22;
wire VAR5;
wire [3:0] VAR24;
wire [7:0] VAR32;
reg [256*8-1:0] VAR3;
reg [256*8-1:0] VAR15;
... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/atlys/rtl/verilog/dvi_gen/encode.v | 7,415 | module MODULE1 (
input VAR6, input VAR16, input [7:0] din, input VAR22, input VAR2, input VAR1, output reg [9:0] dout );
reg [3:0] VAR10; reg [7:0] VAR17;
always @ (posedge VAR6) begin
VAR10 <=din[0] + din[1] + din[2] + din[3] + din[4] + din[5] + din[6] + din[7];
VAR17 <=din;
end
wire VAR13;
assign VAR13 = (VAR10 > 4'h... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_init_ctrl_7vx.v | 14,254 | module MODULE1 # (
parameter VAR1 = 100,
parameter VAR35 = "VAR44"
) (
input VAR14,
output VAR27, output VAR47, output VAR43, output VAR19,
input VAR31, input VAR42,
input VAR26, output VAR2, input VAR11, output VAR23,
input VAR41,
output [2:0] VAR37
);
localparam VAR24 = 3'b000;
localparam VAR5 = 3'b001;
localparam VA... | gpl-3.0 |
revaldinho/opc | opc7/opc7cpu.v | 6,216 | module MODULE1(input[31:0] din,input clk,input VAR38,input[1:0] VAR86,input VAR78,output VAR65,output VAR40,output VAR10,output[31:0] dout,output[19:0] address,output VAR17);
parameter VAR90=5'h0,VAR92=5'h1,VAR66=5'h2,VAR98=5'h3,VAR24=5'h4,VAR69=5'h5,VAR1=5'h6,VAR29=5'h7,VAR74=5'h8,VAR44=5'h9,VAR8=5'hA,VAR72=5'hB,VAR71... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_sdram_0.v | 24,299 | module MODULE1 (
clk,
rd,
VAR51,
wr,
VAR54,
VAR12,
VAR49,
VAR81,
VAR66,
VAR75
)
;
output VAR12;
output VAR49;
output VAR81;
output VAR66;
output [ 40: 0] VAR75;
input clk;
input rd;
input VAR51;
input wr;
input [ 40: 0] VAR54;
wire VAR12;
wire VAR49;
wire VAR81;
reg [ 1: 0] VAR33;
reg [ 40: 0] VAR76;
reg [ 40: 0] VAR29... | gpl-2.0 |
tloinuy/opencpi-opencv | opencpi/hdl/prims/bsv/ResetToBool.v | 1,381 | module MODULE1( VAR1, VAR2);
input VAR1;
output VAR2;
assign VAR2 = (VAR1 == 1'b0);
endmodule | gpl-2.0 |
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