repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/bufbuf/sky130_fd_sc_hs__bufbuf.symbol.v | 1,222 | module MODULE1 (
input VAR2,
output VAR1
);
supply1 VAR4;
supply0 VAR3;
endmodule | apache-2.0 |
sam-falvo/kestrel | cores/KCP53K/processor/docs/example/arbiter.v | 1,595 | module MODULE1(
input [63:0] VAR13,
input [63:0] VAR23,
input VAR2,
input VAR24,
input VAR20,
input [1:0] VAR15,
input VAR11,
output VAR28,
output [63:0] VAR3,
input [63:0] VAR25,
input [63:0] VAR8,
input VAR29,
input VAR12,
input VAR4,
input [1:0] VAR10,
input VAR16,
output VAR19,
output [63:0] VAR14,
output [63:0] VA... | mpl-2.0 |
kwantam/multiexp-a5gx | verilog/pll_top.v | 2,225 | module MODULE1 ( input VAR14
, input rst
, output VAR11
, output VAR16
, input VAR8
, output VAR7
, input VAR10
, output VAR9
);
wire VAR6;
reg [5:0] VAR15, VAR4;
assign VAR16 = (VAR15 == '1);
reg [1:0] VAR2, VAR5;
assign VAR7 = VAR2[1];
assign VAR9 = VAR5[1];
VAR3 begin
VAR4 = VAR15;
if (VAR6) begin
if (~VAR16) begin
... | gpl-3.0 |
CospanDesign/vivado-ip-cores | ip/axi_pmod_tft/verilog/axi/slave/axi_pmod_tft/rtl/adapter_axi_stream_2_ppfifo_wl.v | 6,510 | module MODULE1 #(
parameter VAR28 = 32,
parameter VAR24 = VAR28 / 8,
parameter VAR11 = 0
)(
input rst,
input VAR15,
input VAR1,
input [31:0] VAR6,
input VAR23,
output VAR10,
input [VAR28 - 1:0] VAR16,
input [VAR24 - 1:0] VAR26,
input VAR2,
input VAR4,
output VAR8,
input [1:0] VAR19,
output reg [1:0] VAR3,
input [23:0] ... | mit |
dk00/old-stuff | csie/09computer-architecture/project/code/dcache_one_way_example/dcache_top.v | 4,556 | module MODULE1
(
VAR17,
VAR22,
VAR23,
VAR11,
VAR29,
VAR43,
VAR21,
VAR27,
VAR16,
VAR45,
VAR3,
VAR50,
VAR9,
VAR39
);
input VAR17;
input VAR22;
input [256-1:0] VAR23;
input VAR11;
output [256-1:0] VAR29;
output [32-1:0] VAR43;
output VAR21;
output VAR27;
input [32-1:0] VAR16;
input [32-1:0] VAR45;
input VAR3;
input VAR50;... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2o/sky130_fd_sc_lp__a2bb2o.functional.v | 1,609 | module MODULE1 (
VAR12 ,
VAR10,
VAR8,
VAR1 ,
VAR9
);
output VAR12 ;
input VAR10;
input VAR8;
input VAR1 ;
input VAR9 ;
wire VAR5 ;
wire VAR4 ;
wire VAR11;
and VAR2 (VAR5 , VAR1, VAR9 );
nor VAR6 (VAR4 , VAR10, VAR8 );
or VAR7 (VAR11, VAR4, VAR5);
buf VAR3 (VAR12 , VAR11 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.pp.symbol.v | 1,326 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
input VAR1 ,
output VAR7 ,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.pp.symbol.v | 1,341 | module MODULE1 (
input VAR4 ,
input VAR6 ,
input VAR3 ,
output VAR2 ,
input VAR8 ,
input VAR7,
input VAR5,
input VAR1
);
endmodule | apache-2.0 |
ShepardSiegel/ocpi | rtl/mkWsiAdapter4B32B.v | 35,451 | module MODULE1(VAR170,
VAR17,
VAR83,
VAR222,
VAR226,
VAR213,
VAR103,
VAR30,
VAR82,
VAR105,
VAR208,
VAR200,
VAR176,
VAR137,
VAR96,
VAR32,
VAR230,
VAR22,
VAR140,
VAR177,
VAR40,
VAR194);
input VAR170;
input VAR17;
input [2 : 0] VAR83;
input VAR222;
input VAR226;
input [11 : 0] VAR213;
input [31 : 0] VAR103;
input [3 : 0] ... | lgpl-3.0 |
e33b1711/rfnoc_pp_channelizer | custom_sources/noc_block_channelizer.v | 4,607 | module MODULE1 #(
parameter VAR23 = 64'h11F4000000000000,
parameter VAR55 = 11)
(
input VAR12, input VAR18,
input VAR66, input VAR28,
input [63:0] VAR16, input VAR15, input VAR57, output VAR27,
output [63:0] VAR72, output VAR46, output VAR22, input VAR71,
output [63:0] VAR19,
output [31:0] VAR45
);
wire [31:0] VAR42;
w... | gpl-3.0 |
Proxmark/proxmark3 | fpga/fpga_lf.v | 5,225 | module MODULE1(
input VAR71, output VAR22, input VAR65, input VAR59,
input VAR40, input VAR66, input VAR14,
output VAR39, output VAR54,
output VAR78, output VAR35, output VAR33, output VAR50,
input [7:0] VAR15, output VAR13, output VAR34,
output VAR46, output VAR76, input VAR10, output VAR36,
input VAR67, input VAR1,
o... | gpl-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/rx_control_data_rdy.v | 2,459 | module MODULE1(
input VAR10,
input VAR5,
input VAR12,
input VAR7,
input [2:0] VAR11,
input [2:0] VAR8,
input VAR6,
input [5:0] VAR13,
input VAR1,
output reg VAR9,
output reg VAR3,
output reg VAR2,
output reg VAR4
);
always@(posedge VAR10 or negedge VAR5)
begin
if(!VAR5)
begin
VAR4 <= 1'b0;
VAR3 <= 1'b0;
VAR2 <= 1'b0;
V... | gpl-3.0 |
davidlee80/miaow | src/verilog/rtl/sgpr/reg_512x32b_3r_2w.v | 17,551 | module MODULE1
(
VAR60, VAR41, VAR50,
clk, VAR45, VAR34, VAR11, VAR37, VAR28, VAR56,
VAR72, VAR1, VAR43
, VAR35
);
input clk;
input VAR35;
output [127:0] VAR60;
output [63:0] VAR41;
output [63:0] VAR50;
input [8:0] VAR45;
input [8:0] VAR34;
input [8:0] VAR11;
input [8:0] VAR37;
input [8:0] VAR28;
input [3:0] VAR56;
inp... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nand3b/sky130_fd_sc_hs__nand3b_2.v | 2,102 | module MODULE2 (
VAR1 ,
VAR7 ,
VAR5 ,
VAR3 ,
VAR4,
VAR8
);
output VAR1 ;
input VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR8;
VAR2 VAR6 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR1 ,
VAR7,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR7;
input VAR5 ... | apache-2.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_top.v | 20,385 | module MODULE1
(clk, reset, VAR83, VAR16, VAR102, VAR162,
VAR97, VAR112);
parameter VAR71 = 32;
parameter VAR74 = 2;
parameter VAR121 = 2;
localparam VAR56 = VAR74 * VAR121;
parameter VAR21 = 1;
localparam VAR99 = VAR56 * VAR21;
localparam VAR80 = VAR114(VAR99);
parameter VAR135 = 4;
localparam VAR150 = VAR114(VAR135);... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/offset_flag_to_one_hot.v | 2,686 | module MODULE1
parameter VAR2 = 4
)
(
input [VAR5(VAR2)-1:0] VAR1,
input VAR4,
output [VAR2-1:0] VAR3
);
assign VAR3 = {{(VAR2-1){1'b0}},VAR4} << VAR1;
endmodule | gpl-3.0 |
Jawanga/ece385lab8 | lab8_usb/usb_system/synthesis/submodules/usb_system_jtag_uart.v | 17,487 | module MODULE5 (
clk,
VAR41,
VAR49,
VAR3,
VAR6,
VAR32,
VAR5
)
;
output VAR3;
output [ 7: 0] VAR6;
output VAR32;
output [ 5: 0] VAR5;
input clk;
input [ 7: 0] VAR41;
input VAR49;
wire VAR3;
wire [ 7: 0] VAR6;
wire VAR32;
wire [ 5: 0] VAR5;
always @(posedge clk)
begin
if (VAR49)
("%VAR11", VAR41);
end
assign VAR5 = {6{1'... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.pp.symbol.v | 1,281 | module MODULE1 (
input VAR6 ,
input VAR5 ,
input VAR2 ,
output VAR4 ,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfrtp/sky130_fd_sc_hd__dfrtp.functional.pp.v | 1,863 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR14 ,
VAR13,
VAR7 ,
VAR8 ,
VAR10 ,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR14 ;
input VAR13;
input VAR7 ;
input VAR8 ;
input VAR10 ;
input VAR5 ;
wire VAR3;
wire VAR6;
not VAR12 (VAR6 , VAR13 );
VAR15 VAR11 VAR1 (VAR3 , VAR14, VAR2, VAR6, , VAR7, VAR8);
buf VAR9 (VAR4 , VAR3 );
endm... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/conb/sky130_fd_sc_hvl__conb.blackbox.v | 1,242 | module MODULE1 (
VAR2,
VAR6
);
output VAR2;
output VAR6;
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.pp.symbol.v | 1,228 | module MODULE1 (
input VAR4 ,
input VAR2,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
bqlabs/toolchain-icestorm | build-data/yosys/share/techmap.v | 11,989 | module 90simplemapboolops;
endmodule
module 90simplemapreduceops;
endmodule
module 90simplemaplogicops;
endmodule
module 90simplemapcompareops;
endmodule
module 90simplemapvarious;
endmodule
module 90simplemapregisters;
endmodule
module 90shiftopsshrshlsshlsshr (VAR29, VAR45, VAR24);
parameter VAR50 = 0;
parameter VAR6... | gpl-3.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_pl_free_pool.v | 2,714 | module MODULE1 (VAR7, VAR13,
VAR11, VAR15, VAR1, clk, VAR17);
parameter VAR10 = 4; parameter VAR14 = 4;
parameter VAR18 = 0;
parameter VAR9 = 0;
input [VAR10-1:0] VAR7;
input [VAR10-1:0] VAR13;
input [VAR10-1:0] VAR15;
output [VAR10-1:0] VAR11;
input [VAR10-1:0] VAR1;
input clk, VAR17;
logic [VAR10-1:0] VAR3;
VAR2 VAR4... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah_2.v | 2,283 | module MODULE2 (
VAR7,
VAR3 ,
VAR8 ,
VAR6 ,
VAR9 ,
VAR1,
VAR4,
VAR11 ,
VAR10
);
output VAR7;
output VAR3 ;
input VAR8 ;
input VAR6 ;
input VAR9 ;
input VAR1;
input VAR4;
input VAR11 ;
input VAR10 ;
VAR2 VAR5 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR11(VAR11),
.VAR... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src_previous/tmp/aemb/aeMB_ctrl.v | 9,003 | module MODULE1 (
VAR62, VAR73, VAR6, VAR45, VAR83, VAR8, VAR3, VAR68,
VAR26, VAR22,
VAR60, VAR5, VAR31, VAR71, VAR48, VAR11, VAR13, VAR19, VAR9, VAR25, VAR29,
VAR80, VAR77, VAR53, VAR36, VAR16, VAR50
);
output [1:0] VAR62;
output [1:0] VAR73, VAR6, VAR45;
output [2:0] VAR83;
output [4:0] VAR8;
input VAR60;
input [15:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busreceiver/sky130_fd_sc_lp__busreceiver.symbol.v | 1,289 | module MODULE1 (
input VAR5,
output VAR2
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2/sky130_fd_sc_hdll__nor2.functional.v | 1,262 | module MODULE1 (
VAR5,
VAR6,
VAR3
);
output VAR5;
input VAR6;
input VAR3;
wire VAR1;
nor VAR4 (VAR1, VAR6, VAR3 );
buf VAR2 (VAR5 , VAR1 );
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab2-ManualKeypadScannerAndEncoder/Lab2Part1Fall2015AJM.v | 1,044 | module MODULE1(VAR10, VAR6, VAR13, VAR22, VAR8, VAR23, VAR15, VAR1);
parameter VAR20 = 4;
input [VAR20-1:0] VAR10;
input VAR6, VAR13, VAR22, VAR8;
output [VAR20-1:0] VAR23;
output [VAR20:0] VAR15;
output VAR1;
wire VAR4, VAR3;
VAR14 VAR11(VAR6, VAR16, VAR1);
VAR7 VAR17(VAR8, VAR2, VAR22, VAR16);
VAR9 VAR19(VAR2, VAR3, ... | mit |
mdsalman729/flexpret_project | fpga/atlys/core/top.v | 6,312 | module MODULE1(
input clk,
input VAR82,
input[7:0] VAR75,
output[7:0] VAR71
);
wire VAR30;
wire VAR66;
wire[11:0] VAR9;
wire VAR22;
wire VAR78;
wire[31:0] VAR10;
wire[11:0] VAR72;
wire VAR35;
wire VAR1;
wire VAR52;
wire VAR45;
wire VAR19;
wire[31:0] VAR70;
wire[31:0] VAR56;
wire[31:0] VAR12;
wire VAR40;
wire VAR55;
wir... | bsd-3-clause |
cpulabs/mist1032isa | src/core/decode/decode.v | 12,221 | module MODULE1(
input wire VAR134,
input wire VAR144,
input wire VAR14,
input wire VAR148,
input wire VAR93,
input wire VAR94,
input wire VAR82,
input wire VAR79,
input wire VAR73,
input wire VAR20,
input wire VAR89,
input wire [31:0] VAR47,
input wire [31:0] VAR132,
input wire [31:0] VAR54,
output wire VAR90,
output w... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtp/sky130_fd_sc_hs__sdfrtp.blackbox.v | 1,404 | module MODULE1 (
VAR1,
VAR4 ,
VAR2 ,
VAR3 ,
VAR7 ,
VAR6
);
input VAR1;
input VAR4 ;
input VAR2 ;
output VAR3 ;
input VAR7 ;
input VAR6 ;
supply1 VAR5;
supply0 VAR8;
endmodule | apache-2.0 |
KestrelComputer/kestrel | cores/SIA/rtl/verilog/sia_receiver.v | 2,651 | module MODULE1(
input VAR16,
input VAR9,
input [VAR28:0] VAR3,
input [VAR21:0] VAR26,
input VAR18, input VAR2,
input VAR4,
input VAR12,
output [VAR8:0] VAR17,
output VAR13,
output VAR20
);
parameter VAR10 = 16;
parameter VAR11 = 32;
parameter VAR6 = 5;
parameter VAR8 = VAR10 - 1;
parameter VAR21 = VAR11 - 1;
parameter ... | mpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/edk/pcores/iop_fpga_v1_00_a/hdl/verilog/iop_fpga.v | 4,957 | module MODULE1(VAR4, VAR48,
VAR34,
VAR18,
VAR25,
VAR23,
VAR37,
VAR39,
VAR20
);
output [4:0] VAR18;
output VAR25;
output [123:0] VAR23;
input [4:0] VAR37;
input VAR39;
input [144:0] VAR20;
input VAR4;
input VAR48;
input [1:0] VAR34;
parameter VAR26 = 0;
wire VAR31;
wire VAR5;
wire VAR22;
wire VAR17;
wire VAR7;
wire VAR3... | gpl-2.0 |
combinatorylogic/soc | backends/c2/hw/rtl/mul.v | 1,542 | module MODULE1(input clk,
input rst,
input req,
input [31:0] VAR9,
input [31:0] VAR6,
output reg ack,
output reg [31:0] out);
wire [31:0] VAR7;
reg [15:0] VAR2;
reg [15:0] VAR11;
reg [31:0] VAR1;
reg [2:0] VAR5;
wire [15:0] VAR14 = VAR9[31:16];
wire [15:0] VAR3 = VAR9[15:0];
wire [15:0] VAR13 = VAR6[31:16];
wire [15:0]... | mit |
dm-urievich/afc-smm | software/third-patry/pipelined_fft_256/trunk/SRC/ram256.v | 3,786 | module MODULE1 ( VAR2, VAR9,VAR4 ,VAR8 ,VAR5 ,VAR6 );
output [VAR1-1:0] VAR6 ;
reg [VAR1-1:0] VAR6 ;
input VAR2 ;
wire VAR2 ;
input VAR9;
input VAR4 ;
wire VAR4 ;
input [7:0] VAR8 ;
wire [7:0] VAR8 ;
input [VAR1-1:0] VAR5 ;
wire [VAR1-1:0] VAR5 ;
reg [VAR1-1:0] VAR3 [255:0];
reg [7:0] VAR7;
always @(posedge VAR2) begin... | apache-2.0 |
chimeh/stopwatch_verilog | src/display_connet_port.v | 1,691 | module MODULE1(
input VAR25, input VAR32, input [3:0] VAR34,
input [3:0] VAR2,
input [3:0] VAR23,
input [3:0] VAR38,
input [3:0] VAR31,
input [3:0] VAR4,
input [3:0] VAR18,
input [3:0] VAR22,
output [7:0]VAR27, output [7:0] VAR33);
wire [2:0] VAR21;
wire [3:0] VAR11;
VAR12 VAR28(reset(VAR25),
.VAR29(VAR32),
.VAR26(VAR2... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b.pp.symbol.v | 1,333 | module MODULE1 (
input VAR1 ,
input VAR2 ,
output VAR7 ,
input VAR5 ,
input VAR6,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de/dex_smdisp.v | 3,497 | module MODULE1
(
input VAR20,
input VAR16,
input VAR14,
input VAR6,
input VAR8,
input VAR9,
input VAR11,
input VAR5,
output reg VAR7,
output reg VAR2,
output reg VAR15,
output reg VAR12,
output reg VAR13,
output reg [1:0] VAR18
);
parameter
VAR10=2'b00,
VAR17=2'b01,
VAR3=2'b10;
reg [1:0] VAR19;
always @(posedge VAR20 o... | gpl-3.0 |
bobnewgard/fcs | ver/uut_16_top.v | 3,284 | module MODULE1
(
output wire [31:0] VAR16,
output wire [31:0] VAR2,
output wire [31:0] VAR27,
output wire VAR1,
input wire [15:0] VAR18,
input wire VAR19,
input wire VAR20,
input wire VAR12
);
localparam VAR14 = 1'b0;
localparam VAR10 = 1'b1;
localparam [31:0] VAR22 = {32{VAR14}};
localparam [31:0] VAR26 = {32{VAR10}};... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a32oi/sky130_fd_sc_hs__a32oi.pp.symbol.v | 1,407 | module MODULE1 (
input VAR7 ,
input VAR6 ,
input VAR4 ,
input VAR8 ,
input VAR3 ,
output VAR1 ,
input VAR2,
input VAR5
);
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/usb_enum.v | 3,201 | module MODULE1
(input VAR23, input rst, input en, output VAR8, input VAR24,
output [18:0] VAR16,
output VAR28,
output [7:0] VAR37,
output VAR14,
input [7:0] VAR27,
input VAR2,
output VAR19
);
wire VAR12;
wire [6:0] addr = VAR12 ? 7'b0 : VAR10;
wire [63:0] VAR15;
wire VAR20, VAR17;
VAR25 VAR40
(.VAR23(VAR23), .rst(rst),... | apache-2.0 |
OrganicMonkeyMotion/fpga_experiments | bmax10/j1/j1.v | 4,446 | module MODULE1(
input VAR22, input VAR34, input [15:0] VAR27,
output VAR9, output VAR41, output [15:0] VAR4, output [15:0] VAR20);
wire [15:0] VAR24;
wire [15:0] VAR12 = { 1'b0, VAR24[14:0] };
wire [15:0] VAR33;
reg [4:0] VAR39; reg [4:0] VAR39;
reg [15:0] VAR7; reg [15:0] VAR7;
wire VAR37;
reg [12:0] VAR26;
reg [12:0]... | unlicense |
kyzhai/NUNY | src/hardware/six_new2.v | 6,389 | module MODULE1 (
address,
VAR31,
VAR33);
input [9:0] address;
input VAR31;
output [11:0] VAR33;
tri1 VAR31;
wire [11:0] VAR6;
wire [11:0] VAR33 = VAR6[11:0];
VAR41 VAR51 (
.VAR2 (address),
.VAR52 (VAR31),
.VAR12 (VAR6),
.VAR5 (1'b0),
.VAR43 (1'b0),
.VAR24 (1'b1),
.VAR11 (1'b0),
.VAR15 (1'b0),
.VAR10 (1'b1),
.VAR14 (1'b... | gpl-2.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v | 6,474 | module MODULE1
( input VAR53,
output VAR49
);
VAR60 VAR45
(.VAR6 (VAR35),
.VAR77 (VAR53));
wire [15:0] VAR14;
wire VAR72;
wire VAR76;
wire VAR5;
wire VAR16;
wire VAR79;
wire VAR32;
wire VAR9;
wire VAR8;
wire VAR4;
wire VAR69;
wire VAR11;
wire VAR43;
wire VAR75;
wire VAR47;
wire VAR27;
wire VAR70;
wire VAR66;
wire VAR34... | gpl-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipvfr131_vfr.v | 15,323 | module MODULE1
( VAR165,
reset,
VAR140,
VAR160,
VAR115,
VAR7,
VAR155,
VAR87,
VAR167,
VAR53,
VAR119,
VAR147,
VAR136,
VAR110,
VAR148,
VAR98,
VAR1,
VAR21,
VAR61,
VAR77,
VAR121);
parameter VAR102 = 8;
parameter VAR145 = 3; parameter VAR67 = 1;
parameter VAR131 = 1920; parameter VAR129 = 1080; parameter VAR51 = 256;
paramet... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/fill/gf180mcu_fd_sc_mcu7t5v0__fill_4.behavioral.pp.v | 1,069 | module MODULE1( VAR1, VAR4 );
inout VAR1, VAR4;
VAR3 VAR5(.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR2(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
orbancedric/DeepGate | src/interface/custom/deepgate_top.v | 4,793 | module MODULE1(
input VAR55,
output wire [13:0] VAR48,
input VAR28,
input VAR14,
input VAR9,
output VAR56,
output VAR7,
output VAR5,
output VAR62,
output VAR58,
output VAR44,
output VAR12,
output VAR51,
output [1:0] VAR1,
output [12:0] VAR16,
inout [7:0] VAR61
);
wire rst = 0;
wire clk;
assign clk = VAR55;
wire VAR19;
... | gpl-3.0 |
hsnuonly/PikachuVolleyFPGA | VGA.srcs/sources_1/ip/bg_pole/bg_pole_stub.v | 1,266 | module MODULE1(VAR5, VAR2, VAR4, VAR1, VAR3)
;
input VAR5;
input [0:0]VAR2;
input [6:0]VAR4;
input [11:0]VAR1;
output [11:0]VAR3;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.blackbox.v | 1,400 | module MODULE1 (
VAR3,
VAR7 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR5
);
input VAR3;
input VAR7 ;
input VAR8 ;
output VAR1 ;
input VAR6 ;
input VAR5 ;
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2bb2ai/sky130_fd_sc_hs__o2bb2ai.functional.pp.v | 2,085 | module MODULE1 (
VAR10,
VAR16,
VAR5 ,
VAR17,
VAR14,
VAR6 ,
VAR15
);
input VAR10;
input VAR16;
output VAR5 ;
input VAR17;
input VAR14;
input VAR6 ;
input VAR15 ;
wire VAR15 VAR3 ;
wire VAR15 VAR12 ;
wire VAR13 ;
wire VAR7;
nand VAR2 (VAR3 , VAR14, VAR17 );
or VAR8 (VAR12 , VAR15, VAR6 );
nand VAR4 (VAR13 , VAR3, VAR12 )... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch2/CORDIC_Arch2v1.v | 20,293 | module MODULE1 #(parameter VAR23 = 32, parameter VAR28 = 8, parameter VAR21 = 23, parameter VAR45=26, parameter VAR130 = 5)/*#(parameter VAR23 = 64, parameter VAR28 = 11, parameter VAR21 = 52, parameter VAR45 = 55, parameter VAR130 = 6) (
input wire clk, input wire rst, input wire VAR76, input wire VAR127, input wire V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a221oi/sky130_fd_sc_hs__a221oi_2.v | 2,330 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR6 ,
VAR3 ,
VAR9 ,
VAR5 ,
VAR7,
VAR10
);
output VAR4 ;
input VAR8 ;
input VAR6 ;
input VAR3 ;
input VAR9 ;
input VAR5 ;
input VAR7;
input VAR10;
VAR1 VAR2 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR10(VAR10)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfstp/sky130_fd_sc_hd__dfstp_4.v | 2,273 | module MODULE2 (
VAR1 ,
VAR2 ,
VAR5 ,
VAR9,
VAR4 ,
VAR7 ,
VAR6 ,
VAR10
);
output VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR9;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR10 ;
VAR3 VAR8 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR10(VAR10)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o_0.v | 2,444 | module MODULE2 (
VAR11 ,
VAR7 ,
VAR3 ,
VAR10 ,
VAR2 ,
VAR9 ,
VAR6,
VAR12,
VAR1 ,
VAR4
);
output VAR11 ;
input VAR7 ;
input VAR3 ;
input VAR10 ;
input VAR2 ;
input VAR9 ;
input VAR6;
input VAR12;
input VAR1 ;
input VAR4 ;
VAR8 VAR5 (
.VAR11(VAR11),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6... | apache-2.0 |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/Exponential/Deslinealizador.v | 5,148 | module MODULE1#(parameter VAR4 = 32)(
input wire VAR36, input wire [VAR4-1:0] VAR25, input wire VAR45, input wire VAR49, output wire VAR11, output wire VAR40,
output wire VAR21,
output wire VAR43,
output wire VAR13, output wire VAR7, output wire VAR48, output wire VAR16, output wire VAR27, output wire VAR10, output wir... | gpl-3.0 |
franmolinaca/papiGB | rtl/gpu.v | 27,423 | module MODULE1
(
input wire VAR18,
input wire VAR225,
output wire VAR16, output wire [15:0] VAR200, output wire [15:0] VAR23,
output wire [15:0] VAR27, output reg VAR109, input wire [3:0] VAR59, input wire [7:0] VAR6, input wire [7:0] VAR216, input wire VAR10,
output wire [7:0] VAR8, output wire [7:0] VAR130, output wi... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.blackbox.v | 1,628 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR8 ,
VAR5 ,
VAR2 ,
VAR6,
VAR4 ,
VAR3
);
output VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR6;
input VAR4 ;
input VAR3 ;
endmodule | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_gen_clock.v | 1,175 | module MODULE1(
VAR11,
VAR2,
VAR12,
VAR4,
VAR15,
VAR5
);
input VAR11;
output VAR2;
output VAR12;
output VAR4;
output VAR15;
output VAR5;
parameter VAR13 = 50;
parameter VAR9 = 50;
parameter VAR1 = 50;
parameter VAR7 = 50;
reg VAR10 = 1'b0;
reg VAR6 = 1'b0;
reg VAR3 = 1'b0;
reg VAR8 = 1'b0;
reg VAR2 = 1'b0;
assign VAR5 ... | mit |
iori-yja/ball_detector | i2c.v | 13,850 | module MODULE1 (
input VAR28,
input clk,
input VAR3,
input VAR21,
input VAR46,
input [7:0] VAR49,
output VAR48,
inout VAR40
);
parameter VAR24 = 8'h7c;
parameter VAR1 = 12'h400;
parameter VAR7 = 12'h200;
parameter VAR41 = 12'h100;
parameter VAR30 = 3'h0,
VAR35 = 3'h1,
VAR23 = 3'h2,
VAR11 = 3'h3,
VAR12 = 3'h4,
VAR15 = 3... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_gclk_inv_288x.v | 1,296 | module MODULE1 (
VAR1,
VAR2 );
output VAR1;
input VAR2;
assign VAR1 = ~( VAR2 );
endmodule | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/ucore/inst_decoder.v | 13,760 | module MODULE1(VAR52,VAR40);
parameter VAR44 = VAR44;
parameter
VAR5 = VAR5 , VAR7 = VAR7 , VAR20 = VAR20 , VAR69 = VAR69 , VAR9 = VAR9 , VAR30 = VAR30 , VAR23 = VAR23 , VAR29 = VAR29 , VAR36 = VAR36 , VAR8 = VAR8 , VAR6 = VAR6 , VAR67 = VAR67 , VAR58 = VAR58 , VAR16 = VAR16 , VAR43 = VAR43 , VAR17 = VAR17 , VAR64 = VA... | mit |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_one_cold.v | 1,466 | module MODULE1 (VAR6, reset, enable, VAR1, VAR19);
parameter VAR20 = VAR8;
parameter VAR24 = 32;
parameter VAR18 = VAR11;
parameter VAR16 = VAR10;
parameter VAR17 = VAR14;
parameter VAR22 = VAR9;
parameter VAR3 = VAR2;
parameter VAR7 = VAR13;
parameter VAR5 = VAR12;
input VAR6, reset, enable;
input [VAR24-1:0] VAR1;
ou... | mit |
aj-michael/Digital-Systems | Lab4-Part2-RAMwithHyperTerminalDisplay/ipcore_dir/Clock70MHz/example_design/Clock70MHz_exdes.v | 4,919 | module MODULE1
parameter VAR19 = 100
)
( input VAR8,
input VAR13,
output [1:1] VAR7,
output VAR1,
output VAR11
);
localparam VAR9 = 16;
wire VAR16 = !VAR11 || VAR13;
reg VAR6;
reg VAR26;
reg VAR14;
reg VAR3;
wire VAR23;
wire VAR21;
wire clk;
reg [VAR9-1:0] counter;
VAR15 VAR12
( .VAR8 (VAR8),
.VAR10 (VAR23),
.VAR11 (VA... | mit |
cpulabs/mist1032isa | src/debugger/sdi_debugger.v | 11,473 | module MODULE1(
input wire VAR126,
input wire VAR7,
output wire VAR106,
input wire VAR15,
output wire [3:0] VAR125,
output wire [7:0] VAR57,
output wire [31:0] VAR119,
input wire VAR102,
input wire VAR63,
input wire [31:0] VAR5,
input wire VAR84,
output wire VAR26,
input wire VAR4,
output wire VAR120,
input wire [7:0] ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbufhv2lv/sky130_fd_sc_hvl__lsbufhv2lv.symbol.v | 1,338 | module MODULE1 (
input VAR3,
output VAR4
);
supply1 VAR6 ;
supply0 VAR2 ;
supply1 VAR5;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2.symbol.v | 1,291 | module MODULE1 (
input VAR1,
input VAR4,
output VAR5
);
supply1 VAR3;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.behavioral.pp.v | 1,726 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR5,
VAR8 ,
VAR10 ,
VAR4 ,
VAR1
);
output VAR9 ;
input VAR7 ;
input VAR5;
input VAR8 ;
input VAR10 ;
input VAR4 ;
input VAR1 ;
wire VAR6;
or VAR11 (VAR6, VAR7, VAR5 );
VAR2 VAR3 (VAR9 , VAR6, VAR8, VAR10);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a211o/sky130_fd_sc_hs__a211o_2.v | 2,221 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR6 ,
VAR1 ,
VAR5 ,
VAR9,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR6 ;
input VAR1 ;
input VAR5 ;
input VAR9;
input VAR3;
VAR8 VAR7 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3)
);
endmodule
module MODULE2 (
VAR4 ,
VAR2,
VAR6,
VAR1,
VAR5
);... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_avalon_st_adapter.v | 6,847 | module MODULE1 #(
parameter VAR9 = 8,
parameter VAR28 = 1,
parameter VAR27 = 8,
parameter VAR10 = 1,
parameter VAR24 = 0,
parameter VAR5 = 0,
parameter VAR4 = 1,
parameter VAR6 = 1,
parameter VAR7 = 0,
parameter VAR3 = 8,
parameter VAR16 = 0,
parameter VAR29 = 0,
parameter VAR1 = 0,
parameter VAR14 = 1,
parameter VAR21... | gpl-3.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T25-uart-rx/uart_tx.v | 5,006 | module MODULE1
parameter VAR12 = VAR18
)
(
input wire clk, input wire VAR10, input wire VAR19, input wire [7:0] VAR16, output reg VAR4, output wire ready );
reg VAR7;
wire VAR3;
reg [3:0] VAR8;
reg [7:0] VAR5;
wire VAR20; wire VAR11;
always @(posedge clk)
VAR7 <= VAR19;
always @(posedge clk)
if (VAR19 == 1 && state == ... | gpl-2.0 |
grindars/bfcore | InstructionDecoder.v | 1,277 | module MODULE1 (
input [7:0] VAR1,
output reg [8:0] VAR2
);
always @(VAR1)
case(VAR1)
8'h3E: VAR2 <= 9'b000000001;
8'h3C: VAR2 <= 9'b000000010;
8'h2B: VAR2 <= 9'b000000100;
8'h2D: VAR2 <= 9'b000001000;
8'h2E: VAR2 <= 9'b000010000;
8'h2C: VAR2 <= 9'b000100000;
8'h5B: VAR2 <= 9'b001000000;
8'h5D: VAR2 <= 9'b010000000;
de... | gpl-3.0 |
pemsac/ANN_project | ANN_project.ip_user_repository/UC3M_MISEA_Thesis_feedforward_1_3/hdl/verilog/feedforward_mux_4to1_sel2_8_1.v | 1,204 | module MODULE1 #(
parameter
VAR16 = 0,
VAR7 = 1,
VAR2 = 32,
VAR13 = 32,
VAR15 = 32,
VAR3 = 32,
VAR9 = 32,
VAR10 = 32
)(
input [7 : 0] VAR6,
input [7 : 0] VAR8,
input [7 : 0] VAR12,
input [7 : 0] VAR11,
input [1 : 0] VAR14,
output [7 : 0] dout);
wire [1 : 0] sel;
wire [7 : 0] VAR5;
wire [7 : 0] VAR4;
wire [7 : 0] VAR1;
... | gpl-3.0 |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/ll_crc.v | 3,588 | module MODULE1(
VAR27, VAR24,
clk, VAR30, VAR25, VAR15, VAR3, VAR13,
VAR1, VAR29, VAR7, VAR26, VAR16,
VAR11, VAR18, VAR17, VAR2, VAR20,
VAR22, VAR31
);
input clk;
input VAR30;
input [31:0] VAR25;
input [3:0] VAR15;
input VAR3;
input VAR13;
input VAR1;
input VAR29;
input VAR7;
input VAR26;
input [31:0] VAR16;
input [3:0... | gpl-2.0 |
ccckmit/nand2tetris_verilog | memory.v | 3,931 | module MODULE9 (input in, VAR18, VAR81, output out);
reg VAR11;
assign out = VAR11;
always @(posedge VAR18) begin
if (VAR81) VAR11 = in;
end
endmodule
module MODULE4(input in, VAR18, VAR81, output out);
MODULE9 MODULE3(in, VAR18, VAR81, out);
endmodule
module MODULE5(input[15:0] in, input VAR18, VAR81, output[15:0] out... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffq/gf180mcu_fd_sc_mcu9t5v0__sdffq_2.functional.pp.v | 1,681 | module MODULE1( VAR23, VAR5, VAR1, VAR11, VAR16, VAR25, VAR20, VAR24 );
input VAR11, VAR1, VAR23, VAR5, VAR25, VAR20, VAR24;
output VAR16;
wire VAR14;
not VAR3( VAR14, VAR1 );
wire VAR13;
not VAR19( VAR13, VAR23 );
wire VAR15;
and VAR22( VAR15, VAR14, VAR13 );
wire VAR9;
not VAR8( VAR9, VAR5 );
wire VAR12;
and VAR2( VA... | apache-2.0 |
Digilent/vivado-library | ip/hls_gamma_correction_1_0/hdl/verilog/Loop_loop_height_g8j.v | 2,034 | module MODULE1 (
VAR9, VAR12, VAR1, VAR6, VAR11, VAR3, VAR2, VAR4, VAR5, clk);
parameter VAR14 = 8;
parameter VAR7 = 8;
parameter VAR10 = 256;
input[VAR7-1:0] VAR9;
input VAR12;
output reg[VAR14-1:0] VAR1;
input[VAR7-1:0] VAR6;
input VAR11;
output reg[VAR14-1:0] VAR3;
input[VAR7-1:0] VAR2;
input VAR4;
output reg[VAR14-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdlclkp/sky130_fd_sc_hdll__sdlclkp_2.v | 2,278 | module MODULE1 (
VAR3,
VAR10 ,
VAR6,
VAR7 ,
VAR5,
VAR9,
VAR1 ,
VAR2
);
output VAR3;
input VAR10 ;
input VAR6;
input VAR7 ;
input VAR5;
input VAR9;
input VAR1 ;
input VAR2 ;
VAR8 VAR4 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
... | apache-2.0 |
silent-observer/RCPU | CPU/source/cpuController.v | 23,727 | module MODULE1( input wire clk,
input wire rst,
input wire[15:0] VAR78, input wire[3:0] VAR89, input wire VAR102,
input wire irq,
output reg[2:0] VAR57, output reg VAR83, output reg VAR110, output reg VAR70, output reg VAR94, output reg VAR7, output reg[3:0] VAR104, output reg[3:0] VAR115, output reg[3:0] VAR46, output... | mit |
mindrobots/P8X32A_Emulation | P8X32A_DE0_Nano/cog_ctr.v | 3,794 | module MODULE1
(
input VAR14,
input VAR19,
input VAR9,
input VAR6,
input VAR1,
input VAR17,
input [31:0] VAR3,
input [31:0] VAR21,
output reg [32:0] VAR12,
output [31:0] VAR15,
output VAR11
);
reg [31:0] VAR4;
reg [31:0] VAR5;
always @(posedge VAR14 or negedge VAR9)
if (!VAR9)
VAR4 <= 32'b0;
else if (VAR6)
VAR4 <= VAR3... | gpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_data_fifo.v | 10,783 | module MODULE1
parameter VAR64 = 128,
parameter VAR15 = 1,
parameter VAR31 = 1,
parameter VAR45 = 256 )
(
input VAR68,
input VAR58,
input [VAR64-1:0] VAR39,
input VAR21,
input VAR65,
input [(VAR64/32)-1:0] VAR3,
input [(VAR64/32)-1:0] VAR47,
output VAR66,
input [(VAR64/32)-1:0] VAR59,
output [VAR64-1:0] VAR53,
output V... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cmn/block_ram/single_port_ram_sync.v | 2,395 | module MODULE1
parameter VAR6 = 6,
parameter VAR7 = 8
)
(
input wire clk,
input wire VAR5,
input wire [VAR6-1:0] VAR1,
input wire [VAR7-1:0] VAR3,
output wire [VAR7-1:0] VAR2
);
reg [VAR7-1:0] VAR4 [2**VAR6-1:0];
reg [VAR6-1:0] VAR8;
always @(posedge clk)
begin
if (VAR5)
VAR4[VAR1] <= VAR3;
VAR8 <= VAR1;
end
assign VAR... | mit |
alexforencich/xfcp | lib/eth/example/ML605/fpga_rgmii/rtl/fpga.v | 6,079 | module MODULE1 (
input wire VAR10,
input wire VAR110,
input wire reset,
input wire VAR71,
input wire VAR120,
input wire VAR89,
input wire VAR123,
input wire VAR50,
input wire [7:0] VAR11,
output wire VAR42,
output wire VAR93,
output wire VAR24,
output wire VAR74,
output wire VAR107,
output wire [7:0] VAR86,
input wire ... | mit |
ehab93/MIPS-Processor | ALU/alu_control.v | 1,459 | module MODULE1 (
input [5:0] VAR9,
input [1:0] VAR17,
output [3:0] VAR21 );
wire VAR5, VAR1, VAR4, VAR16, VAR7, VAR18;
wire VAR6, VAR2, VAR12, VAR25, VAR3, VAR19;
wire [3:0] VAR22;
not (VAR6, VAR9[0]);
not (VAR2, VAR9[1]);
not (VAR12, VAR9[2]);
not (VAR25, VAR9[3]);
not (VAR3, VAR9[4]);
not (VAR19, VAR9[5]);
and (VAR5,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.functional.v | 1,470 | module MODULE1 (
VAR3 ,
VAR1,
VAR6
);
output VAR3 ;
input VAR1;
input VAR6 ;
wire VAR4;
VAR2 VAR8 VAR7 (VAR4 , VAR6, VAR1 );
buf VAR5 (VAR3 , VAR4 );
endmodule | apache-2.0 |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_auto_cc_0/bd_auto_cc_0_stub.v | 5,746 | module MODULE1(VAR66, VAR5, VAR79,
VAR6, VAR23, VAR10, VAR24, VAR28, VAR52,
VAR12, VAR30, VAR8, VAR25, VAR68, VAR2,
VAR44, VAR27, VAR21, VAR60, VAR78, VAR49, VAR42,
VAR62, VAR41, VAR9, VAR48, VAR26, VAR74,
VAR54, VAR1, VAR7, VAR35, VAR61, VAR3,
VAR57, VAR47, VAR34, VAR19, VAR14, VAR31, VAR59,
VAR39, VAR16, VAR22, VAR70... | mit |
elkhadiy/xph-leons | grlib-gpl-1.4.1-b4156/lib/opencores/ge_1000baseX/ge_1000baseX_an.v | 17,391 | module MODULE1 #(
parameter VAR54 = 0
) (
input VAR4,
input reset,
input VAR44,
output reg [2:0] VAR52,
output reg [15:0] VAR43,
input [15:0] VAR68,
input VAR65,
input VAR67,
input VAR46,
input VAR7,
input VAR3,
input [2:0] VAR21,
input VAR58,
input VAR72,
input VAR75,
input VAR27,
input VAR1,
output reg VAR37,
input [... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfxbp/sky130_fd_sc_hs__dfxbp.functional.pp.v | 1,657 | module MODULE1 (
VAR3,
VAR1,
VAR5 ,
VAR12 ,
VAR6 ,
VAR11
);
input VAR3;
input VAR1;
output VAR5 ;
output VAR12 ;
input VAR6 ;
input VAR11 ;
wire VAR10;
VAR8 VAR4 VAR2 (VAR10 , VAR11, VAR6, VAR3, VAR1);
buf VAR9 (VAR5 , VAR10 );
not VAR7 (VAR12 , VAR10 );
endmodule | apache-2.0 |
shailcoolboy/Warp-Trinity | PlatformSupport/Deprecated/pcores/clock_board_config_v1_02_a/hdl/verilog/clock_board_config.v | 25,726 | module MODULE1 (
VAR37,
VAR57,
VAR46,
VAR11,
VAR66,
VAR33,
VAR32,
VAR25,
VAR50,
VAR43,
VAR58
);
parameter VAR21 = 120000000;
parameter VAR20 = 16'h1Aff;
parameter VAR7 = 16'h1Aff;
input VAR37;
input VAR57;
output VAR46; reg VAR46 = 1'b1;
output VAR11; reg VAR11 = 1'b1;
output VAR66; reg VAR66 = 1'b1;
output VAR33; reg ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o_4.v | 2,469 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR2 ,
VAR5 ,
VAR8 ,
VAR10 ,
VAR3,
VAR7,
VAR1 ,
VAR4
);
output VAR6 ;
input VAR11 ;
input VAR2 ;
input VAR5 ;
input VAR8 ;
input VAR10 ;
input VAR3;
input VAR7;
input VAR1 ;
input VAR4 ;
VAR9 VAR12 (
.VAR6(VAR6),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR3(... | apache-2.0 |
AmeerAbdelhadi/Indirectly-Indexed-2D-Binary-Content-Addressable-Memory-BCAM | vacram.v | 5,889 | module MODULE1
input VAR14,
input [4 :0] VAR9 ,
output [4 :0] VAR11 );
wire [VAR31(VAR16)+4:0] VAR4 = VAR33[VAR31(VAR16)+9:5];
wire [31:0] VAR23;
wire [31:0] VAR5;
wire [31:0] VAR17;
VAR28 #( .VAR19 (32 ), .VAR21 (32 ), .VAR3 (VAR16*1024/32), .VAR29 (0 ), .VAR2 (1 )) VAR27 ( .clk (clk ), .rst (rst ), .VAR32 (VAR32 ), .... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v | 4,013 | module MODULE1
(
inout [35:0] VAR11,
inout [35:0] VAR7,
inout [35:0] VAR1,
inout [35:0] VAR5,
inout [35:0] VAR10
) ;
endmodule
module MODULE4
(
input VAR6,
input [383:0] VAR2,
input [7:0] VAR8,
inout [35:0] VAR3
) ;
endmodule
module MODULE2
(
input [255:0] VAR4,
inout [35:0] VAR3
) ;
endmodule
module MODULE3
(
output [... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2o/sky130_fd_sc_ls__a2bb2o.functional.v | 1,609 | module MODULE1 (
VAR12 ,
VAR10,
VAR2,
VAR1 ,
VAR8
);
output VAR12 ;
input VAR10;
input VAR2;
input VAR1 ;
input VAR8 ;
wire VAR11 ;
wire VAR5 ;
wire VAR6;
and VAR7 (VAR11 , VAR1, VAR8 );
nor VAR4 (VAR5 , VAR10, VAR2 );
or VAR9 (VAR6, VAR5, VAR11);
buf VAR3 (VAR12 , VAR6 );
endmodule | apache-2.0 |
hoangt/NOCulator | hring/hw/buffered/src/c_extractor.v | 2,672 | module MODULE1
(VAR11, VAR1);
parameter VAR5 = 32;
function integer VAR10(input [0:VAR5-1] VAR7);
integer VAR3;
begin
VAR10 = 0;
for(VAR3 = 0; VAR3 < VAR5; VAR3 = VAR3 + 1)
VAR10 = VAR10 + VAR7[VAR3];
end
endfunction
parameter [0:VAR5-1] VAR2 = {VAR5{1'b1}};
localparam VAR8 = VAR10(VAR2);
input [0:VAR5-1] VAR11;
output... | mit |
hanw/sonic-lite | hw/verilog/port/sonic_single_port.v | 7,519 | module MODULE1 (
VAR25,
VAR69,
VAR56,
VAR18,
VAR43,
VAR3,
VAR31,
VAR12,
VAR66,
VAR34,
VAR2,
VAR57,
VAR64,
VAR47,
VAR4,
VAR8,
VAR35,
VAR6,
VAR68,
VAR48,
VAR59,
VAR72,
VAR55,
VAR19
);
output wire [39:0] VAR25;
input wire [39:0] VAR31;
input wire VAR12;
input wire VAR66;
input wire VAR34;
input wire VAR2;
input wire VAR57... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/rtl/bw_clk_cl_iobdg_jbus.v | 3,648 | module MODULE1 (
VAR1, VAR12, VAR13, VAR2,
VAR8, VAR11, VAR4, VAR10, VAR7, VAR6, VAR3,
VAR5
);
input VAR5; input VAR3; input VAR6; input VAR7; input VAR10; input VAR4; input VAR11; input VAR8;
output VAR2; output VAR13; output VAR12; output VAR1;
VAR9 VAR9 (
.VAR13(VAR13),
.VAR2(VAR2),
.VAR12 (VAR12),
.VAR1 (VAR1),
.VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22o/sky130_fd_sc_ms__a22o.symbol.v | 1,363 | module MODULE1 (
input VAR1,
input VAR2,
input VAR6,
input VAR9,
output VAR5
);
supply1 VAR3;
supply0 VAR8;
supply1 VAR4 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfrbp/sky130_fd_sc_hvl__dfrbp.symbol.v | 1,427 | module MODULE1 (
input VAR5 ,
output VAR1 ,
output VAR7 ,
input VAR4,
input VAR3
);
supply1 VAR6;
supply0 VAR2;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/usbf/usbf_utmi_ls.v | 20,580 | module MODULE1( clk, rst,
VAR91,
VAR53, VAR30, VAR70,
VAR59, VAR34, VAR47, VAR74, VAR35,
VAR90,
VAR44, VAR8, VAR71, VAR77,
VAR5
);
input clk;
input rst;
input VAR91;
input VAR53, VAR30;
output VAR70;
output VAR59;
output VAR34;
output VAR47;
input [1:0] VAR74;
output [1:0] VAR35;
input VAR90;
output VAR44; output VAR8;... | gpl-2.0 |
thinkoco/de1_soc_opencl | de10_nano_sharedonly_mil/ip/I8080_Controller/I8080_Controller.v | 1,088 | module MODULE1#(
VAR11 = 32
)(
clk,
VAR4,
VAR3,
VAR5,
VAR10,
VAR6,
VAR2,
VAR7, VAR1,
VAR9,
VAR8,
);
input clk;
input VAR4;
input VAR3;
input VAR5;
input [31:0] VAR10;
input [2:0] VAR6;
output VAR2;
output VAR7;output VAR1;
output VAR9;
output [31:0] VAR8;
assign VAR2 = VAR3;
assign VAR7 = VAR6[2];
assign VAR1 = 1'b1;
a... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr_pp_pkg_s/sky130_fd_sc_lp__udp_dlatch_pr_pp_pkg_s.blackbox.v | 1,490 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR1 ,
VAR8 ,
VAR5,
VAR7 ,
VAR6 ,
VAR4
);
output VAR2 ;
input VAR3 ;
input VAR1 ;
input VAR8 ;
input VAR5;
input VAR7 ;
input VAR6 ;
input VAR4 ;
endmodule | apache-2.0 |
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