repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
twlostow/dsi-shield | hdl/rtl/sysctl/edid_eeprom.v | 2,805 | module MODULE1 (
input VAR22,
input VAR23,
inout VAR36,
inout VAR16,
input VAR25,
input VAR1,
input VAR18,
output VAR32,
input VAR43,
output VAR8,
input [7:0] VAR27,
input [7:0] VAR12,
input VAR34);
parameter VAR33 = 128;
parameter VAR20 = 7'h50;
reg [7:0] VAR6='haa;
wire [7:0] VAR37;
wire VAR29, VAR45, VAR39;
wire VAR... | lgpl-3.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_eq.v | 35,592 | module MODULE1 #
(
parameter VAR36 = "VAR35",
parameter VAR14 = "VAR75",
parameter VAR83 = 1
)
(
input VAR54,
input VAR55,
input VAR26,
input [ 1:0] VAR108,
input [ 3:0] VAR28,
input [ 3:0] VAR105,
input [ 5:0] VAR116,
input [ 1:0] VAR109,
input [ 2:0] VAR53,
input [ 5:0] VAR9,
input [ 3:0] VAR32,
input VAR123,
input [... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/cmm_errman_cpl.v | 5,724 | module MODULE1 (
VAR9, VAR4,
VAR5, VAR1,
rst,
clk
);
output [2:0] VAR9;
output VAR4;
input VAR5;
input VAR1;
input rst;
input clk;
parameter VAR8 = 1;
reg [2:0] VAR7;
reg VAR2;
always @(VAR5 or VAR1)
begin
case ({VAR5, VAR1}) 2'b00: begin VAR7 = 3'b000;
VAR2 = 1'b1;
end
2'b01: begin VAR7 = 3'b001;
VAR2 = 1'b0;
end
2'b1... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb.functional.pp.v | 1,890 | module MODULE1 (
VAR6,
VAR5,
VAR10 ,
VAR14 ,
VAR7 ,
VAR11 ,
VAR9
);
input VAR6;
input VAR5;
output VAR10 ;
input VAR14 ;
input VAR7 ;
input VAR11 ;
input VAR9 ;
wire VAR9 VAR4 ;
wire VAR1 ;
wire VAR13;
nand VAR12 (VAR4 , VAR9, VAR11 );
or VAR15 (VAR1 , VAR7, VAR14, VAR4 );
VAR8 VAR3 (VAR13, VAR1, VAR6, VAR5);
buf VAR2 ... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/altera_jtag_sld_node.v | 5,748 | module MODULE1 (
VAR50,
VAR19,
VAR31,
VAR47,
VAR49,
VAR52,
VAR62,
VAR53,
VAR14,
VAR59,
VAR5,
VAR67,
VAR43
);
parameter VAR48 = 20;
localparam VAR55 = (1000/VAR48)/2;
localparam VAR35 = 3;
input [VAR35 - 1:0] VAR50;
input VAR19;
output reg [VAR35 - 1:0] VAR31;
output VAR47;
output reg VAR49 = 1'b0;
output VAR52;
output ... | mit |
peteasa/oh | src/spi/hdl/spi_slave_io.v | 6,106 | module MODULE1 #( parameter VAR49 = 104 )
(
input VAR30, input VAR54, input VAR34, output VAR51, input VAR48, input VAR1, input VAR39, input VAR33, output VAR20, output VAR12, output [5:0] VAR7, output [7:0] VAR31, input [7:0] VAR36, input clk, input VAR3, output reg VAR9, output [VAR49-1:0] VAR8, input VAR27 );
reg [1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dlyc/gf180mcu_fd_sc_mcu9t5v0__dlyc_2.behavioral.pp.v | 1,164 | module MODULE1( VAR2, VAR3, VAR6, VAR1 );
input VAR2;
inout VAR6, VAR1;
output VAR3;
VAR5 VAR7(.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1));
VAR5 VAR4(.VAR2(VAR2),.VAR3(VAR3),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | models/udp_dlatch_pr_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_pr_pp_pg_n.symbol.v | 1,505 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR1 ,
input VAR3 ,
input VAR6,
input VAR7 ,
input VAR2
);
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_adapter.v | 22,103 | module MODULE1 #
(
parameter VAR26 = 8,
parameter VAR11 = (VAR26>8),
parameter VAR31 = (VAR26/8),
parameter VAR2 = 8,
parameter VAR9 = (VAR2>8),
parameter VAR25 = (VAR2/8),
parameter VAR5 = 0,
parameter VAR18 = 8,
parameter VAR14 = 0,
parameter VAR29 = 8,
parameter VAR10 = 1,
parameter VAR38 = 1
)
(
input wire clk,
inp... | mit |
jayant-sharma/matrix | hdl/BRAM_Matrix.v | 2,344 | module MODULE1 #(
parameter VAR8 = 6,
parameter VAR13 = 16,
parameter VAR12 = 2*VAR13+VAR8-1,
parameter VAR20 = 12
)(
input VAR39,
input VAR24,
input VAR3,
input [VAR20-1:0] VAR2,
input [VAR8*VAR13-1:0] VAR4,
input VAR32,
input [VAR20-1:0] VAR14,
input [VAR8*VAR13-1:0] VAR21,
input VAR16,
input [VAR20-1:0] VAR34,
outpu... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4b/sky130_fd_sc_hdll__nand4b_4.v | 2,327 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR2 ,
VAR1 ,
VAR3 ,
VAR6,
VAR7,
VAR4 ,
VAR9
);
output VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR6;
input VAR7;
input VAR4 ;
input VAR9 ;
VAR11 VAR10 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(V... | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_0/affine_block_uint_to_ieee754_fp_0_0_stub.v | 1,322 | module MODULE1(VAR1, VAR2)
;
input [9:0]VAR1;
output [31:0]VAR2;
endmodule | mit |
rbarzic/async_logic | async_lib/pausible_clock_sync/pausible_clock_sync.v | 1,179 | module MODULE1 (
VAR21, VAR24,
req, VAR1, VAR19
);
input req;
output VAR21;
output VAR24;
input VAR1;
input VAR19;
parameter VAR16=10;
wire VAR24;
wire VAR21;
wire sync;
VAR10 VAR13(.VAR20(VAR24),.VAR23(VAR14));
delay #(.VAR16(VAR16)) VAR26(.VAR20(VAR14),.VAR4(VAR2));
VAR5 VAR22(.VAR12(VAR28),.VAR7(VAR2), .VAR11(sync),... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor4/sky130_fd_sc_ls__nor4.behavioral.pp.v | 1,870 | module MODULE1 (
VAR11 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR5 ,
VAR14,
VAR15,
VAR13 ,
VAR1
);
output VAR11 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR5 ;
input VAR14;
input VAR15;
input VAR13 ;
input VAR1 ;
wire VAR10 ;
wire VAR6;
nor VAR12 (VAR10 , VAR7, VAR9, VAR4, VAR5 );
VAR2 VAR8 (VAR6, VAR10, VAR14, VAR15);
buf VAR3 ... | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/new/AXI_SRAM.v | 10,187 | module MODULE1(
input VAR60, input VAR27,
input VAR8,
input VAR43,
output VAR66,
input [32-1:0] VAR30,
input [3-1:0] VAR14,
input VAR73,
output VAR61,
input [32-1:0] VAR49,
input [4-1:0] VAR29,
output reg VAR37,
input VAR26,
input VAR54,
output VAR32,
input [32-1:0] VAR15,
input [3-1:0] VAR18,
output reg VAR1,
input VA... | mit |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_immu_top.v | 16,179 | module MODULE1(
clk, rst,
VAR45, VAR17, VAR4, VAR24, VAR6,
VAR32, VAR20, VAR52, VAR60,
VAR13, VAR37, VAR42, VAR12, VAR22,
VAR23, VAR36, VAR21,
VAR41, VAR40, VAR35, VAR3, VAR34, VAR59
);
parameter VAR29 = VAR7;
parameter VAR31 = VAR7;
input clk;
input rst;
input VAR45;
input VAR17;
input VAR4;
input [VAR31-1:0] VAR24;
i... | gpl-2.0 |
Anirudh94/Connect4-FPGA | Connect4/vga_adapter/vga_pll.v | 8,477 | module MODULE1 (
VAR17,
VAR15);
input VAR17;
output VAR15;
wire [5:0] VAR1;
wire [1:0] VAR10;
wire VAR19;
assign VAR19 = 1'b0;
assign VAR10 = { VAR19, VAR17 };
VAR13 VAR4 (
.VAR24 (VAR10),
.clk (VAR1)
);
VAR4.VAR22 = "VAR20",
VAR4.VAR5 = "VAR21 VAR23",
VAR4.VAR9 = "VAR13",
VAR4.VAR16 = "VAR2",
VAR4.VAR7 = 20000,
VAR4.... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/inv/sky130_fd_sc_hvl__inv.pp.blackbox.v | 1,229 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR2,
VAR3,
VAR1 ,
VAR6
);
output VAR5 ;
input VAR4 ;
input VAR2;
input VAR3;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtp/sky130_fd_sc_hd__dlrtp.pp.blackbox.v | 1,399 | module MODULE1 (
VAR2 ,
VAR1,
VAR4 ,
VAR6 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR8
);
output VAR2 ;
input VAR1;
input VAR4 ;
input VAR6 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor2/sky130_fd_sc_hs__xor2.blackbox.v | 1,228 | module MODULE1 (
VAR4,
VAR3,
VAR2
);
output VAR4;
input VAR3;
input VAR2;
supply1 VAR5;
supply0 VAR1;
endmodule | apache-2.0 |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_modedecode.v | 2,963 | module MODULE1(
input wire clk,
input wire [ 1:0] VAR1, input wire [ 2:0] VAR9,
output reg VAR2,
output reg VAR11,
output reg VAR12, output reg VAR7,
output reg VAR3, output reg VAR10, output reg VAR4, output reg VAR5,
output reg VAR6,
output reg [ 1:0] VAR8 );
always @(posedge clk)
begin
case( VAR9 )
3'b010: VAR2 <= 1... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/altera_up_video_dma_to_memory.v | 6,525 | module MODULE1 (
clk,
reset,
VAR14,
VAR3,
VAR8,
VAR11,
VAR13,
VAR2,
VAR16,
VAR10,
VAR4,
VAR7,
VAR1
);
parameter VAR6 = 15; parameter VAR9 = 0;
parameter VAR12 = 15;
input clk;
input reset;
input [VAR6: 0] VAR14;
input VAR3;
input VAR8;
input [VAR9: 0] VAR11;
input VAR13;
input VAR2;
output VAR16;
output VAR10;
output [... | gpl-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_ddsv_vdma.v | 11,716 | module MODULE1 (
VAR40,
VAR38,
VAR42,
VAR10,
VAR4,
VAR46,
VAR31,
VAR27,
VAR15,
VAR52,
VAR58,
VAR47,
VAR17,
VAR55,
VAR21,
VAR25);
input VAR40;
output VAR38;
input VAR42;
input [63:0] VAR10;
output VAR4;
output VAR46;
output VAR31;
input VAR27;
input VAR15;
input VAR52;
output [95:0] VAR58;
input [15:0] VAR47;
output [19... | mit |
YosysHQ/yosys | techlibs/xilinx/brams_xc5v_map.v | 5,590 | module MODULE2 (...);
parameter VAR109 = 0;
parameter VAR60 = "VAR46";
parameter VAR120 = 1;
parameter VAR100 = 1;
parameter VAR119 = 1;
parameter VAR42 = 1;
parameter VAR54 = 1;
parameter VAR68 = "VAR75";
parameter VAR105 = 0;
parameter VAR19 = 0;
parameter VAR11 = 1;
parameter VAR78 = 1;
parameter VAR14 = 1;
paramete... | isc |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_8c_v1_00_a/hdl/verilog/cf_adc_8c.v | 11,506 | module MODULE1 (
VAR69,
VAR62,
VAR51,
VAR42,
VAR82,
VAR20,
VAR60,
VAR16,
VAR68,
VAR66,
VAR8,
VAR47,
VAR53,
VAR12,
VAR45,
VAR43,
VAR19,
VAR13,
VAR34,
VAR3,
VAR65,
VAR81,
VAR58,
VAR6,
VAR15,
VAR5,
VAR36,
VAR44);
input VAR69;
input VAR62;
input [ 7:0] VAR51;
input [ 7:0] VAR42;
input VAR82;
input VAR20;
input VAR60;
outpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22a/sky130_fd_sc_lp__o22a.behavioral.v | 1,607 | module MODULE1 (
VAR2 ,
VAR5,
VAR10,
VAR3,
VAR7
);
output VAR2 ;
input VAR5;
input VAR10;
input VAR3;
input VAR7;
supply1 VAR11;
supply0 VAR1;
supply1 VAR12 ;
supply0 VAR15 ;
wire VAR4 ;
wire VAR13 ;
wire VAR16;
or VAR14 (VAR4 , VAR10, VAR5 );
or VAR8 (VAR13 , VAR7, VAR3 );
and VAR6 (VAR16, VAR4, VAR13);
buf VAR9 (VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o221a/sky130_fd_sc_hdll__o221a.blackbox.v | 1,403 | module MODULE1 (
VAR5 ,
VAR3,
VAR2,
VAR7,
VAR4,
VAR10
);
output VAR5 ;
input VAR3;
input VAR2;
input VAR7;
input VAR4;
input VAR10;
supply1 VAR1;
supply0 VAR8;
supply1 VAR9 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/Pmods/PmodPIR_v1_0/src/PmodPIR.v | 9,715 | module MODULE1
(VAR149,
VAR74,
VAR101,
VAR58,
VAR97,
VAR55,
VAR159,
VAR11,
VAR90,
VAR131,
VAR162,
VAR128,
VAR106,
VAR120,
VAR132,
VAR81,
VAR34,
VAR133,
VAR150,
VAR8,
VAR73,
VAR44,
VAR75,
VAR93,
VAR94,
VAR142,
VAR152,
VAR95,
VAR147,
VAR64,
VAR126,
VAR115,
VAR45,
VAR22,
VAR72,
VAR12,
VAR154,
VAR91,
VAR43,
VAR157,
VAR87,
... | mit |
mbus/mbus | mbus/verilog/no_pwr_gating_yesheng/mbus_ctrl_wrapper.v | 3,670 | module MODULE1(
input VAR20,
input VAR41,
output VAR1,
input VAR8,
input VAR17,
output VAR28,
input [VAR5-1:0] VAR30,
input [VAR49-1:0] VAR43,
input VAR19,
input VAR52,
input VAR53,
output VAR57,
output [VAR5-1:0] VAR7,
output [VAR49-1:0] VAR29,
output VAR13,
input VAR40,
output VAR48,
output VAR38,
output VAR56,
outpu... | apache-2.0 |
oceanborn-mx/sirius | src.verilog/Matrix_Multiplication_Torus/Matrix_Multiplication_Torus/src/fsm_ctrol.v | 1,440 | module MODULE1 (
input VAR8, input VAR5, input VAR3, output reg VAR4, output reg VAR11, output reg VAR10, output reg VAR9, output reg VAR13, output reg VAR1 );
reg[2:0] VAR2,VAR12;
always @ *
begin : VAR6
case (VAR2)
3'b000 : begin if (VAR3)
VAR12 = 3'b001;
end
else
VAR12 = VAR2;
VAR4 = 1'b0;
VAR11 = 1'b0;
VAR10 = 1'b0... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.symbol.v | 1,354 | module MODULE1 (
input VAR7,
input VAR3,
input VAR1,
input VAR9,
output VAR5
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way/src/riffa/txc_engine_classic.v | 16,141 | parameter VAR7 = 1,
parameter VAR18 = 0,
parameter VAR35 = 64,
parameter VAR80 = 10,
parameter VAR39 = "VAR93")
( input VAR135,
input VAR133, output VAR23,
input [VAR62-1:0] VAR96,
input VAR111,
output [VAR117-1:0] VAR55,
output VAR130,
output VAR1,
output [VAR60(VAR117/32)-1:0] VAR14,
output VAR58,
output [VAR60(VAR11... | mit |
zhaishaomin/ring_network-based-multicore- | communication_assist/dc_rep_upload.v | 3,434 | module MODULE1( clk,
rst,
VAR10,
VAR18,
VAR19,
VAR3,
VAR7,
VAR5,
VAR4,
VAR15,
VAR13
);
input clk;
input rst;
input [175:0] VAR10;
input VAR18;
input [3:0] VAR19;
input VAR3;
input VAR7;
output [15:0] VAR5;
output VAR4;
output [1:0] VAR15;
output VAR13;
parameter VAR16=1'b0;
parameter VAR1=1'b1;
reg VAR12;
reg [175:0] V... | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6t_OA_LVT_TT_210930.v | 242,182 | module MODULE1 (VAR10, VAR9, VAR1, VAR2, VAR8, VAR4);
output VAR10;
input VAR9, VAR1, VAR2, VAR8, VAR4;
wire VAR3, VAR6, VAR7;
wire VAR12, VAR5, VAR13;
wire VAR11;
not (VAR5, VAR4);
not (VAR12, VAR8);
not (VAR7, VAR2);
and (VAR13, VAR7, VAR12);
not (VAR6, VAR1);
not (VAR3, VAR9);
and (VAR11, VAR3, VAR6, VAR12);
or (VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb_2.v | 2,314 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR1 ,
VAR6,
VAR5,
VAR8 ,
VAR10
);
output VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR6;
input VAR5;
input VAR8 ;
input VAR10 ;
VAR11 VAR2 (
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR10... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_cmpgif.v | 10,643 | module MODULE1(
VAR6, VAR93, VAR57, VAR11,
VAR3, VAR8, VAR69,
VAR61, VAR64, VAR51,
VAR58, VAR83, VAR17,
VAR72, VAR29, VAR16,
VAR13, VAR32, VAR88,
VAR66, VAR79, VAR46,
VAR41, VAR28, VAR81,
VAR63, VAR92, VAR60,
VAR53, VAR73,
VAR4, VAR48, VAR86, VAR76,
VAR50, VAR49, VAR14,
VAR77, VAR80, VAR78,
VAR40, VAR56, VAR10,
VAR27, ... | gpl-2.0 |
ultraembedded/riscv | core/riscv/riscv_alu.v | 7,144 | module MODULE1
(
input [ 3:0] VAR14
,input [ 31:0] VAR8
,input [ 31:0] VAR11
,output [ 31:0] VAR12
);
reg [31:0] VAR6;
reg [31:16] VAR16;
reg [31:0] VAR2;
reg [31:0] VAR3;
reg [31:0] VAR13;
reg [31:0] VAR1;
reg [31:0] VAR4;
reg [31:0] VAR10;
reg [31:0] VAR7;
reg [31:0] VAR9;
wire [31:0] VAR15 = VAR8 - VAR11;
always @ (... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp.behavioral.v | 1,842 | module MODULE1 (
VAR5 ,
VAR14,
VAR12,
VAR9
);
output VAR5 ;
output VAR14;
input VAR12;
input VAR9 ;
supply1 VAR1;
supply0 VAR16;
supply1 VAR15 ;
supply0 VAR6 ;
wire VAR3 ;
reg VAR4 ;
wire VAR8 ;
wire VAR13;
VAR7 VAR10 (VAR3 , VAR8, VAR13, VAR4, VAR1, VAR16);
buf VAR2 (VAR5 , VAR3 );
not VAR11 (VAR14 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand4bb/sky130_fd_sc_hdll__nand4bb.behavioral.v | 1,540 | module MODULE1 (
VAR5 ,
VAR13,
VAR6,
VAR11 ,
VAR1
);
output VAR5 ;
input VAR13;
input VAR6;
input VAR11 ;
input VAR1 ;
supply1 VAR3;
supply0 VAR7;
supply1 VAR12 ;
supply0 VAR2 ;
wire VAR14;
wire VAR9;
nand VAR4 (VAR14, VAR1, VAR11 );
or VAR10 (VAR9, VAR6, VAR13, VAR14);
buf VAR8 (VAR5 , VAR9 );
endmodule | apache-2.0 |
hoglet67/CoPro6502 | src/NextZ80/NextZ80ALU.v | 10,420 | module MODULE2(
input [7:0] VAR16,
input [7:0] VAR26,
input [7:0] VAR14,
output reg[7:0] VAR1,
output reg [15:0] VAR7,
input [4:0] VAR23,
input [5:0] VAR20, input VAR12, input VAR6 );
wire [7:0] MODULE1;
wire VAR18, hdaa;
MODULE1 MODULE1(.VAR22(VAR14), .VAR10(VAR16), .VAR24(MODULE1), .VAR18(VAR18), .hdaa(hdaa));
wire V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32ai/sky130_fd_sc_ls__o32ai_2.v | 2,441 | module MODULE2 (
VAR7 ,
VAR10 ,
VAR8 ,
VAR12 ,
VAR5 ,
VAR3 ,
VAR9,
VAR1,
VAR2 ,
VAR11
);
output VAR7 ;
input VAR10 ;
input VAR8 ;
input VAR12 ;
input VAR5 ;
input VAR3 ;
input VAR9;
input VAR1;
input VAR2 ;
input VAR11 ;
VAR4 VAR6 (
.VAR7(VAR7),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o_4.v | 2,444 | module MODULE2 (
VAR8 ,
VAR11 ,
VAR9 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR4,
VAR5,
VAR1 ,
VAR10
);
output VAR8 ;
input VAR11 ;
input VAR9 ;
input VAR3 ;
input VAR6 ;
input VAR2 ;
input VAR4;
input VAR5;
input VAR1 ;
input VAR10 ;
VAR7 VAR12 (
.VAR8(VAR8),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VA... | apache-2.0 |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_altpll_0.v | 11,481 | module MODULE1
(
VAR1,
VAR10,
VAR4,
VAR2) ;
input VAR1;
input VAR10;
input [0:0] VAR4;
output [0:0] VAR2;
tri0 VAR1;
tri1 VAR10;
reg [0:0] VAR8;
reg [0:0] VAR3;
reg [0:0] VAR7;
wire VAR9;
wire VAR5;
wire VAR6; | gpl-2.0 |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/host_interface/pcie_axi_bridge.v | 2,763 | module MODULE1 (
output VAR45,
output VAR23,
input VAR12,
input VAR52,
output VAR26,
output VAR16,
input [31:0] VAR33,
input [3:0] VAR68,
input [3:0] VAR65,
input VAR13,
input VAR5,
output [5:0] VAR4,
output VAR66,
input VAR58,
output VAR34,
output [31:0] VAR22,
output [3:0] VAR55,
output VAR49,
output VAR7,
input VAR5... | mit |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_xbar_0/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_ndeep_srl.v | 4,418 | module MODULE1 #
(
parameter VAR23 = "none", parameter VAR27 = 1 )
(
input wire VAR25, input wire [VAR27-1:0] VAR24, input wire VAR22, input wire VAR7, output wire VAR28 );
localparam VAR16 = 5;
localparam VAR3 = (VAR27>VAR16) ? (2**(VAR27-VAR16)) : 1;
wire [VAR3:0] VAR13;
wire [VAR3-1:0] VAR18;
wire [(VAR27>VAR16) ? (... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_addr_cmd_datapath.v | 6,175 | module MODULE1(
clk,
VAR27,
VAR32,
VAR3,
VAR19,
VAR49,
VAR60,
VAR47,
VAR29,
VAR13,
VAR52,
VAR44,
VAR53,
VAR25,
VAR11,
VAR26,
VAR48,
VAR37,
VAR21,
VAR38
);
parameter VAR41 = "";
parameter VAR45 = "";
parameter VAR35 = "";
parameter VAR8 = "";
parameter VAR39 = "";
parameter VAR18 = "";
parameter VAR28 = "";
parameter VA... | lgpl-3.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_bb.v | 3,176 | module MODULE1 (
VAR29,
VAR13,
VAR23,
VAR35,
VAR30,
VAR12,
VAR11,
VAR34,
VAR10,
VAR8,
VAR9,
VAR22,
VAR17,
VAR19,
VAR36,
VAR6,
VAR32,
VAR18,
VAR16,
VAR33,
VAR21,
VAR20,
VAR27,
VAR1,
VAR24,
VAR4,
VAR3,
VAR15,
VAR14,
VAR26,
VAR37,
VAR5,
VAR38,
VAR31,
VAR7,
VAR25,
VAR28,
VAR2);
input [24:0] VAR29;
input VAR13;
input VAR23;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrbp/sky130_fd_sc_ls__sdfrbp_1.v | 2,695 | module MODULE1 (
VAR9 ,
VAR5 ,
VAR4 ,
VAR10 ,
VAR3 ,
VAR1 ,
VAR8,
VAR12 ,
VAR11 ,
VAR7 ,
VAR13
);
output VAR9 ;
output VAR5 ;
input VAR4 ;
input VAR10 ;
input VAR3 ;
input VAR1 ;
input VAR8;
input VAR12 ;
input VAR11 ;
input VAR7 ;
input VAR13 ;
VAR6 VAR2 (
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR3(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s.pp.blackbox.v | 1,345 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR4,
VAR2,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR1 ;
input VAR4;
input VAR2;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/system_acl_iface_mm_interconnect_1.v | 18,247 | module MODULE1 (
input wire VAR101, input wire VAR83, input wire [29:0] VAR55, output wire VAR31, input wire [4:0] VAR74, input wire [31:0] VAR82, input wire VAR70, output wire [255:0] VAR100, output wire VAR13, input wire VAR102, input wire [255:0] VAR98, input wire VAR29, output wire [24:0] VAR26, output wire VAR2, o... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s15/sky130_fd_sc_hd__clkdlybuf4s15.behavioral.v | 1,439 | module MODULE1 (
VAR8,
VAR3
);
output VAR8;
input VAR3;
supply1 VAR2;
supply0 VAR9;
supply1 VAR1 ;
supply0 VAR6 ;
wire VAR7;
buf VAR4 (VAR7, VAR3 );
buf VAR5 (VAR8 , VAR7 );
endmodule | apache-2.0 |
ueokande/async_benchmark_circuit | src/gcd8/gcd8.v | 25,761 | module MODULE7 (
VAR41,
MODULE6,
MODULE26,
MODULE14,
MODULE10
);
output VAR41;
input MODULE6;
input MODULE26;
input MODULE14;
input MODULE10;
wire [1:0] VAR180;
VAR10 VAR260 (VAR41, VAR180[0], VAR180[1]);
VAR145 VAR65 (VAR180[1], MODULE14, MODULE10);
VAR145 VAR287 (VAR180[0], MODULE6, MODULE26);
endmodule
module MODULE... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/ebufn/sky130_fd_sc_hdll__ebufn.behavioral.v | 1,320 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR2
);
output VAR4 ;
input VAR8 ;
input VAR2;
supply1 VAR1;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR3 ;
bufif0 VAR5 (VAR4 , VAR8, VAR2 );
endmodule | apache-2.0 |
timtian090/Playground | UVM/UVMPlayground/Lab3/Lab3-Project/CLS_PWM_DutyCycle_Timer.v | 1,970 | module MODULE1
parameter VAR1 = 50000000, parameter VAR5 = 1000, parameter VAR2 = 50 )
(
input VAR4,
output reg VAR3,
input VAR6
);
begin
begin
begin
end
begin | mit |
vipinkmenon/scas | hw/fpga/source/enet_if/ethernet_controller_top.v | 6,872 | module MODULE1(
input VAR40,
input VAR1,
input VAR36,
input VAR68,
output VAR47,
output [7:0] VAR60,
output VAR72,
output VAR42,
output VAR75,
input [7:0] VAR44,
input VAR70,
input VAR52,
input VAR57,
input VAR17,
input VAR22,
input VAR81,
output VAR32,
input VAR53,
output VAR21,
output VAR55,
input VAR28,
input VAR10,... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | j1_soc/hdl/Timer_Counter/gen_clk_tst.v | 1,201 | module MODULE1;
reg clk;
reg rst;
reg en;
reg [31:0] VAR6;
wire [31:0] VAR4;
wire VAR3;
VAR5 VAR2 (
.clk(clk),
.en(en),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR3(VAR3)
);
VAR1 counter(
.clk(clk),
.en(en),
.rst(rst),
.VAR4(VAR4)
); | mit |
tmatsuya/milkymist-ml401 | cores/softusb/rtl/softusb_phy.v | 3,757 | module MODULE1(
input VAR40,
input VAR4,
output VAR42,
output VAR17,
input VAR21,
inout VAR59,
inout VAR33,
output VAR53,
output VAR54,
input VAR11,
inout VAR8,
inout VAR3,
output VAR30,
output VAR55,
output [1:0] VAR25,
output [1:0] VAR6,
input VAR48,
input [1:0] VAR7,
input [7:0] VAR13,
input VAR39,
output VAR61,
out... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/520N_MX/fpga_10g/rtl/fpga.v | 19,171 | module MODULE1 (
input wire VAR183,
output wire [1:0] VAR262,
output wire [1:0] VAR279,
output wire [3:0] VAR72,
output wire [3:0] VAR15,
input wire [3:0] VAR214,
input wire VAR238,
output wire [3:0] VAR75,
input wire [3:0] VAR338,
input wire VAR1,
output wire [3:0] VAR189,
input wire [3:0] VAR108,
input wire VAR225,
o... | mit |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/Integrador_Pos.v | 3,878 | module MODULE1(
input [15:0] VAR10,
input [15:0] VAR2,
input enable,
input rst,
input clk,
output [31:0] VAR4,
output reg VAR12
);
wire VAR22;
reg en;
reg [63:0] VAR24;
reg [63:0] VAR5;
wire [31:0] VAR13;
reg VAR16;
assign VAR4 = VAR24[63:32];
VAR17 VAR1(
.clk(clk),
.rst(VAR16),
.en(en),
.VAR11(VAR2),
.VAR23(VAR10),
.V... | mit |
rfotino/consolite-hardware | src/processor.v | 19,025 | module MODULE1
(
input clk,
input VAR20,
output reg [11:0] VAR10,
output reg VAR24,
output reg [VAR19-1:0] VAR13,
input VAR4,
input [VAR5-1:0] VAR9,
output reg VAR8,
output reg [VAR19-1:0] VAR12,
output reg [VAR1-1:0] VAR14,
input VAR7,
output reg VAR22,
output reg [VAR19-1:0] VAR21,
input [VAR1-1:0] VAR18,
input VAR17... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp.blackbox.v | 1,256 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR2
);
output VAR4 ;
input VAR1 ;
input VAR2;
supply1 VAR5;
supply0 VAR3;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/xnor2/gf180mcu_fd_sc_mcu9t5v0__xnor2_1.functional.pp.v | 1,184 | module MODULE1( VAR9, VAR6, VAR1, VAR13, VAR8 );
input VAR6, VAR9;
inout VAR13, VAR8;
output VAR1;
wire VAR10;
and VAR12( VAR10, VAR6, VAR9 );
wire VAR7;
not VAR4( VAR7, VAR6 );
wire VAR14;
not VAR5( VAR14, VAR9 );
wire VAR11;
and VAR3( VAR11, VAR7, VAR14 );
or VAR2( VAR1, VAR10, VAR11 );
endmodule | apache-2.0 |
gitpan/Verilog-Perl | verilog/example.v | 3,648 | module MODULE1;
VAR2 VAR2 ();
integer VAR3;
reg \VAR1[10] ; | artistic-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b_2.v | 2,302 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR5 ,
VAR6 ,
VAR11,
VAR8,
VAR10 ,
VAR9
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR11;
input VAR8;
input VAR10 ;
input VAR9 ;
VAR7 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4/sky130_fd_sc_lp__and4_m.v | 2,239 | module MODULE2 (
VAR11 ,
VAR2 ,
VAR10 ,
VAR6 ,
VAR5 ,
VAR3,
VAR4,
VAR7 ,
VAR8
);
output VAR11 ;
input VAR2 ;
input VAR10 ;
input VAR6 ;
input VAR5 ;
input VAR3;
input VAR4;
input VAR7 ;
input VAR8 ;
VAR9 VAR1 (
.VAR11(VAR11),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.functional.v | 1,966 | module MODULE1 (
VAR9,
VAR4,
VAR3 ,
VAR14 ,
VAR10 ,
VAR5 ,
VAR8 ,
VAR1
);
input VAR9;
input VAR4;
output VAR3 ;
input VAR14 ;
input VAR10 ;
input VAR5 ;
input VAR8 ;
input VAR1 ;
wire VAR8 VAR16 ;
wire VAR13 ;
wire VAR2;
or VAR6 (VAR16 , VAR10, VAR14 );
and VAR15 (VAR13 , VAR5, VAR8, VAR16, VAR1 );
VAR12 VAR7 (VAR2, VA... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/8-way/src/riffa/rotate.v | 3,074 | module MODULE1
parameter VAR5 = "VAR6",
parameter VAR10 = 4
)
(
input [VAR10-1:0] VAR1,
input [VAR9(VAR10)-1:0] VAR7,
output [VAR10-1:0] VAR2
);
wire [2*VAR10-1:0] VAR11;
wire [2*VAR10-1:0] VAR3;
wire [2*VAR10-1:0] VAR4;
wire [2*VAR10-1:0] VAR8;
assign VAR3 = {VAR1,VAR1};
assign VAR11 = {VAR1,VAR1};
assign VAR8 = VAR3 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.v | 2,160 | module MODULE1 (
VAR3,
VAR7 ,
VAR6 ,
VAR5 ,
VAR1
);
output VAR3;
input VAR7 ;
input VAR6 ;
input VAR5 ;
input VAR1 ;
VAR2 VAR4 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3,
VAR7
);
output VAR3;
input VAR7 ;
supply1 VAR6;
supply1 VAR5 ;
supply0 VAR1 ;
VAR2 VAR4 (
.... | apache-2.0 |
lvd2/zxevo | fpga/base_trdemu/trunk/z80/zwait.v | 1,951 | module MODULE1(
input wire VAR7,
input wire VAR2,
input wire VAR5,
input wire VAR3,
output reg [6:0] VAR1,
output wire VAR4,
output wire VAR6
);
begin | gpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/code/Valid_Monitor.v | 1,439 | module MODULE1(clk, VAR5, VAR4, VAR3);
input clk;
input VAR5;
input [7:0] VAR4;
output reg [3:0] VAR3;
always @(posedge clk or negedge VAR5)
begin
if(!VAR5)
begin
VAR3 <= 4'h0;
end
else
begin
casex(VAR4)
8'VAR2:begin
VAR3 <= 4'h1;
end
8'VAR9:begin
VAR3 <= 4'h2;
end
8'VAR7:begin
VAR3 <= 4'h3;
end
8'VAR6:begin
VAR3 <= 4'... | gpl-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/ifu/rtl/sparc_ifu_rndrob.v | 3,088 | module MODULE1(
VAR9, VAR10,
clk, reset, VAR14, VAR8, VAR3, VAR6, VAR11
);
input clk, reset, VAR14, VAR8;
input [3:0] VAR3;
input VAR6;
input VAR11;
output [3:0] VAR9;
output VAR10;
wire [3:0] VAR1,
VAR2,
VAR5,
VAR4;
assign VAR2 = VAR6 ? VAR9 :
VAR4;
assign VAR1[3:1] = VAR2[3:1] & {3{~reset}};
assign VAR1[0] = VAR2[0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_lsbuf_lh_isowell/sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell.pp.symbol.v | 1,522 | module MODULE1 (
input VAR4 ,
output VAR3 ,
input VAR5,
input VAR6 ,
input VAR1 ,
input VAR7 ,
input VAR2
);
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/id_stage.v | 6,833 | module MODULE1 (
input wire clk,
input wire reset,
input wire [VAR32] VAR46,
input wire [VAR32] VAR12,
output wire [VAR19] VAR10,
output wire [VAR19] VAR6,
input wire VAR4,
input wire [VAR32] VAR15,
input wire [VAR19] VAR49,
input wire VAR5,
input wire [VAR32] VAR29,
input wire [VAR26] VAR27,
input wire [VAR32] VAR8,
o... | apache-2.0 |
lvd2/zxevo | fpga/sdload/trunk/dram/arbiter.v | 11,294 | module MODULE1(
input clk,
input VAR28,
output [20:0] VAR24, output reg VAR13, output reg VAR31, input VAR36, input VAR8, output [1:0] VAR33, input [15:0] VAR39, output [15:0] VAR4,
output reg VAR11, output reg VAR29, output reg VAR9,
input VAR2,
input [1:0] VAR14,
input [20:0] VAR26, output [15:0] VAR16, output reg VA... | gpl-3.0 |
olgirard/openmsp430 | fpga/altera_de0_nano_soc/rtl/verilog/opengfx430/openGFX430.v | 27,943 | module MODULE1 (
VAR77,
VAR149, VAR15, VAR47, VAR76, VAR68, VAR31, VAR154, VAR122,
VAR199,
VAR78, VAR119, VAR51, VAR145, VAR19
VAR48, VAR204, VAR173, VAR7,
VAR36, VAR124, VAR54, VAR136, VAR115, VAR39, VAR105,
VAR214,
VAR159, VAR19
VAR134 );
parameter [14:0] VAR179 = 15'h0200; output VAR77;
output VAR149; output VAR15; ... | bsd-3-clause |
hhuang25/uwaterloo_ece224 | Lab1Good/green_led_pio.v | 2,120 | module MODULE1 (
address,
VAR2,
clk,
VAR7,
VAR8,
VAR5,
VAR4,
VAR3
)
;
output [ 7: 0] VAR4;
output [ 7: 0] VAR3;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR7;
input VAR8;
input [ 7: 0] VAR5;
wire VAR1;
reg [ 7: 0] VAR6;
wire [ 7: 0] VAR4;
wire [ 7: 0] VAR9;
wire [ 7: 0] VAR3;
assign VAR1 = 1;
assign VAR9 = {... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2/sky130_fd_sc_hs__and2.functional.v | 1,672 | module MODULE1 (
VAR3,
VAR11,
VAR6 ,
VAR10 ,
VAR1
);
input VAR3;
input VAR11;
output VAR6 ;
input VAR10 ;
input VAR1 ;
wire VAR7 ;
wire VAR5;
and VAR9 (VAR7 , VAR10, VAR1 );
VAR8 VAR2 (VAR5, VAR7, VAR3, VAR11);
buf VAR4 (VAR6 , VAR5 );
endmodule | apache-2.0 |
lvd2/ngs | fpga/obsolete/fpgaC_release/sound/sound_mulacc.v | 3,270 | module MODULE1(
VAR14,
VAR2, VAR7,
VAR17, VAR11,
ready, VAR4 );
input VAR14;
input [5:0] VAR2;
input [7:0] VAR7;
input VAR17;
input VAR11;
output reg ready;
output reg [15:0] VAR4;
wire [5:0] VAR10;
wire [6:0] VAR12;
reg [6:0] VAR6;
reg [7:0] VAR15;
reg [5:0] VAR9;
wire VAR13;
reg [3:0] counter;
reg VAR16;
wire [1:0] V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfsbp/sky130_fd_sc_ms__dfsbp.pp.symbol.v | 1,412 | module MODULE1 (
input VAR9 ,
output VAR5 ,
output VAR2 ,
input VAR3,
input VAR1 ,
input VAR7 ,
input VAR6 ,
input VAR4 ,
input VAR8
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_rptr_b.v | 6,235 | module MODULE1(VAR48 ,VAR67 ,VAR95 ,VAR36 ,VAR49 ,VAR5 ,VAR47
,VAR54 ,VAR11 ,VAR51 ,VAR45 ,VAR89 ,VAR19 ,VAR94 ,VAR81 ,VAR21 ,VAR91 ,
VAR35 ,VAR1 ,VAR72 ,VAR46 ,VAR33 ,VAR14 ,VAR55 ,VAR4 ,VAR69 ,VAR40 ,VAR25 ,
VAR37 ,VAR7 ,VAR20 ,VAR60 ,VAR24 ,VAR88 ,VAR38 ,VAR58 ,VAR42 ,VAR39 ,VAR63
,VAR23 ,VAR64 ,VAR76 ,VAR61 ,VAR90 ... | gpl-2.0 |
olofk/wb_intercon | rtl/verilog/wb_upsizer.v | 6,547 | module MODULE1
parameter VAR60 = 0,
parameter VAR19 = 32)
(input VAR61,
input VAR54,
input [VAR19-1:0] VAR7,
input [VAR32-1:0] VAR10,
input [VAR32/8-1:0] VAR49,
input VAR14,
input VAR22,
input VAR17,
input [2:0] VAR30,
input [1:0] VAR25,
output [VAR32-1:0] VAR56,
output VAR42,
output VAR47,
output VAR21,
output [VAR19-... | lgpl-3.0 |
MarcoVogt/basil | firmware/modules/uart/uart_master.v | 8,719 | module MODULE1(
input VAR10,
input VAR39,
input VAR22,
output VAR11,
inout [7:0] VAR31,
output reg [31:0] VAR40,
output reg VAR33,
output reg VAR32
);
wire clk;
assign clk = VAR10;
wire [7:0] VAR48;
reg [7:0] VAR27;
assign VAR48 = VAR31;
assign VAR31 = VAR33 ? VAR27 : 8'VAR41;
reg [7:0] VAR43;
wire [7:0] VAR34;
wire VA... | bsd-3-clause |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_m04_regslice_12/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axic_srl_fifo.v | 6,587 | module MODULE1 #(
parameter VAR15 = "VAR33",
parameter integer VAR8 = 1,
parameter integer VAR9 = 16 )
(
input wire VAR30, input wire VAR13, input wire [VAR8-1:0] VAR16, input wire VAR7, output reg VAR19, output wire [VAR8-1:0] VAR4, output reg VAR28, input wire VAR21 );
function integer VAR24 (input integer VAR23);
in... | bsd-2-clause |
kyzhai/NUNY | src/hardware/reading_bb.v | 4,996 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
mbuesch/toprammer | libtoprammer/fpga/src/at89s5xdip40/at89s5xdip40.v | 8,441 | module MODULE1(VAR25, VAR4, write, read, VAR14, VAR8);
inout [7:0] VAR25;
input VAR4;
input write;
input read;
input VAR14;
inout [48:1] VAR8;
wire VAR19;
reg [7:0] address;
reg [7:0] VAR11;
wire VAR12, VAR13;
reg [1:0] VAR5;
reg [3:0] VAR15;
reg [3:0] VAR17;
reg [3:0] VAR20;
reg VAR6;
reg [7:0] VAR1;
reg [13:0] VAR10;... | gpl-2.0 |
cafe-alpha/wascafe | v10/fpga_firmware/wasca/synthesis/submodules/wasca_mm_interconnect_0_avalon_st_adapter_001.v | 6,161 | module MODULE1 #(
parameter VAR9 = 34,
parameter VAR17 = 0,
parameter VAR12 = 34,
parameter VAR19 = 0,
parameter VAR16 = 0,
parameter VAR22 = 0,
parameter VAR25 = 1,
parameter VAR11 = 1,
parameter VAR10 = 0,
parameter VAR14 = 34,
parameter VAR3 = 0,
parameter VAR4 = 1,
parameter VAR1 = 0,
parameter VAR24 = 1,
parameter... | gpl-2.0 |
nyaxt/dmix | ringbuf_t.v | 1,786 | module MODULE1;
reg clk;
reg rst;
reg [23:0] VAR3;
reg VAR4;
reg VAR7;
reg [3:0] VAR6;
VAR5 VAR2(
.clk(clk), .rst(rst),
.VAR3(VAR3), .VAR4(VAR4),
.VAR7(VAR7), .VAR6(VAR6));
parameter VAR1 = 41.0; | mit |
MForever78/CPUFly | src/single_cycle_cpu_io.v | 7,927 | module MODULE1 (clk,reset,VAR35,VAR13,VAR16,VAR37,VAR18,VAR25,VAR44,VAR19,VAR34); input clk, reset; input [31:0] VAR13; input [31:0] VAR37; input VAR44;
output [31:0] VAR35; output [31:0] VAR16; output [31:0] VAR18; output VAR25; output VAR19;
output [31: 0] VAR34;
reg VAR2; reg VAR49,VAR14; reg [31:0] VAR41; reg [4:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr.behavioral.pp.v | 1,940 | module MODULE1 (
VAR3 ,
VAR12 ,
VAR4 ,
VAR2 ,
VAR6,
VAR13 ,
VAR10
);
output VAR3 ;
input VAR12 ;
input VAR4 ;
input VAR2 ;
input VAR6;
input VAR13 ;
input VAR10 ;
wire VAR1 ;
wire VAR11;
buf VAR5 (VAR1 , VAR12 );
VAR9 VAR8 (VAR11, VAR1, VAR6, VAR2);
buf VAR7 (VAR3 , VAR11 );
endmodule | apache-2.0 |
svenstaro/uni-projekt | verilog/ram_bb.v | 5,948 | module MODULE1 (
address,
VAR6,
VAR1,
VAR4,
VAR2,
VAR3,
VAR5);
input [9:0] address;
input [3:0] VAR6;
input VAR1;
input [31:0] VAR4;
input VAR2;
input VAR3;
output [31:0] VAR5;
tri1 [3:0] VAR6;
tri1 VAR1;
tri1 VAR2;
endmodule | gpl-3.0 |
nyaxt/dmix | ddr3_fb_t.v | 3,013 | module MODULE1;
reg clk;
parameter VAR4 = 20;
VAR38 clk = 0;
always #(VAR4/2) clk = ~clk;
reg rst;
wire VAR32 = 1'b1;
reg [31:0] VAR35;
reg [6:0] VAR8;
wire [29:0] VAR2;
wire [8:0] VAR13;
wire [6:0] VAR27;
wire VAR6;
wire VAR42;
wire VAR17;
wire [5:0] VAR21;
wire [5:0] VAR14;
wire [5:0] VAR22;
wire VAR12;
VAR11 VAR11(
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi_1.v | 2,499 | module MODULE1 (
VAR7 ,
VAR12 ,
VAR1 ,
VAR4 ,
VAR3 ,
VAR10 ,
VAR6,
VAR5,
VAR11 ,
VAR2
);
output VAR7 ;
input VAR12 ;
input VAR1 ;
input VAR4 ;
input VAR3 ;
input VAR10 ;
input VAR6;
input VAR5;
input VAR11 ;
input VAR2 ;
VAR8 VAR9 (
.VAR7(VAR7),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6... | apache-2.0 |
alexforencich/xfcp | example/Arty/fpga/rtl/fpga_core.v | 18,839 | module MODULE1 #
(
parameter VAR20 = "VAR133"
)
(
input wire clk,
input wire rst,
input wire [3:0] VAR96,
input wire [3:0] VAR160,
output wire VAR176,
output wire VAR47,
output wire VAR169,
output wire VAR252,
output wire VAR208,
output wire VAR131,
output wire VAR57,
output wire VAR175,
output wire VAR227,
output wire... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/io_queues/ethernet_mac/src/rx_queue.v | 18,307 | module MODULE1
parameter VAR24 = VAR81/8,
parameter VAR13 = 0,
parameter VAR62 = 'hff,
parameter VAR43 = 0
)
(output reg [VAR81-1:0] VAR58,
output reg [VAR24-1:0] VAR94,
output reg VAR33,
input VAR71,
input [7:0] VAR131,
input VAR107,
input VAR95,
input VAR117,
output VAR15,
output VAR65,
output VAR80,
output reg [11:0... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_125/source/pcie_7x_v1_3_qpll_wrapper.v | 17,077 | module MODULE1 #
(
parameter VAR51 = "VAR8", parameter VAR57 = "VAR25", parameter VAR14 = "1.1", parameter VAR29 = "VAR4", parameter VAR56 = 0
)
(
input VAR47,
input VAR41,
output VAR26,
output VAR37,
output VAR6,
input VAR21,
input VAR40,
input VAR2,
input [ 7:0] VAR67,
input VAR65,
input [15:0] VAR23,
input VAR48,
ou... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.v | 2,020 | module MODULE2 (
VAR1,
VAR4 ,
VAR6 ,
VAR5 ,
VAR7
);
input VAR1;
input VAR4 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
VAR3 VAR2 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
supply1 VAR5 ;
supply0 VAR7 ;
VAR3 VAR2 ();
endmodul... | apache-2.0 |
EEorCS/Signal_Generator_based_on_FPGA | Verilog_sources/DDS.v | 2,359 | module MODULE1(
clk,
reset,
VAR19,
VAR8,
VAR24,
VAR4
);
parameter VAR12 = 8;
parameter VAR16 = 16;
input [2:0] VAR4;
input VAR19;
reg [VAR16-1:0] VAR2;
input clk;
input reset;
output [VAR12-1:0] VAR24;
reg [VAR12-1:0] VAR14;
reg [VAR12-1:0] VAR7;
reg [VAR12-1:0] VAR13;
reg [VAR12-1:0] VAR18;
reg [VAR12-1:0] VAR6;
reg [... | gpl-2.0 |
Gum-Joe/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/dma_ctrl_wrapper.v | 17,939 | module MODULE1(
input clk,
input VAR77,
input rst,
output VAR44,
input VAR106,
output VAR32,
input [31:0] VAR76,
input [11:0] VAR147,
input VAR127,
input VAR6,
input [31:0] VAR63,
input [31:0] VAR22,
input [31:0] VAR95,
input [23:0] VAR41,
input [7:0] VAR34,
output VAR45,
output VAR11,
input [11:0] VAR72,
output [31:0]... | bsd-2-clause |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/user_mgmt_slave.v | 5,037 | module MODULE1(
input clk,
input VAR8,
input VAR7,
input VAR22, input [31:0] VAR12,
input VAR9,
output VAR21,
output [31:0] VAR13,
output VAR5,
output VAR3,
output [31:0] VAR18,
output VAR24,
input VAR19,
input [31:0] VAR11,
output reg VAR20, input VAR15, output VAR17, output reg [15:0] VAR16,
output [31:0] VAR23,
inpu... | apache-2.0 |
omicronns/studies-sys-rek | de1-soc-template/v/I2C_CCD_Config.v | 10,085 | module MODULE1 ( VAR11,
VAR18,
VAR31,
VAR14,
VAR27,
VAR37,
VAR26
);
input VAR11;
input VAR18;
input VAR31;
output VAR37;
inout VAR26;
reg [15:0] VAR34;
reg [31:0] VAR23;
reg VAR38;
reg VAR29;
wire VAR21;
wire VAR1;
reg [23:0] VAR32;
reg [5:0] VAR15;
reg [3:0] VAR13;
input VAR14;
input VAR27;
parameter VAR35 = 16'h07c0;... | mit |
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