repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21oi/sky130_fd_sc_lp__a21oi.behavioral.pp.v | 2,006 | module MODULE1 (
VAR13 ,
VAR12 ,
VAR2 ,
VAR15 ,
VAR7,
VAR5,
VAR3 ,
VAR6
);
output VAR13 ;
input VAR12 ;
input VAR2 ;
input VAR15 ;
input VAR7;
input VAR5;
input VAR3 ;
input VAR6 ;
wire VAR11 ;
wire VAR9 ;
wire VAR4;
and VAR1 (VAR11 , VAR12, VAR2 );
nor VAR14 (VAR9 , VAR15, VAR11 );
VAR10 VAR16 (VAR4, VAR9, VAR7, VAR5)... | apache-2.0 |
tmeissner/cryptocores | cbctdes/rtl/verilog/cbctdes.v | 4,112 | module MODULE1
(
input VAR29, input VAR26, input VAR3, input VAR4, input [0:63] VAR1, input [0:63] VAR7, input [0:63] VAR16, input [0:63] VAR30, input [0:63] VAR6, input VAR5, output reg VAR21, output reg [0:63] VAR13, output VAR2 );
reg VAR33;
wire VAR18;
reg VAR22;
reg [0:63] VAR12;
wire [0:63] VAR23;
wire [0:63] VAR... | gpl-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/bc3bf9cf92381990/ip_design_xbar_0_stub.v | 3,589 | module MODULE1(VAR38, VAR23, VAR19, VAR22,
VAR11, VAR12, VAR28, VAR34, VAR20, VAR31,
VAR4, VAR24, VAR29, VAR27, VAR39, VAR21,
VAR37, VAR15, VAR3, VAR17, VAR36, VAR2,
VAR9, VAR14, VAR32, VAR6, VAR26, VAR18,
VAR40, VAR5, VAR1, VAR33, VAR8, VAR35,
VAR13, VAR7, VAR25, VAR10, VAR30, VAR16)
;
input VAR38;
input VAR23;
input ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.blackbox.v | 1,371 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR3 ,
VAR8
);
output VAR6 ;
input VAR2 ;
input VAR3 ;
input VAR8;
supply1 VAR7;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,547 | module MODULE1
parameter VAR11 = 8,
VAR3 = 8,
VAR42 = 0,
VAR44 = 0,
VAR24 = 1,
VAR7 = 0,
VAR21 = 1,
VAR35 = 2,
VAR37 = 2,
VAR45 = 1,
VAR13 = VAR11 / VAR3,
VAR4 = VAR18(VAR13)
)
(
input VAR27,
input VAR26,
input VAR39,
input VAR40,
output VAR29,
input VAR28,
input [VAR11 - 1 : 0] VAR33,
input [VAR24 - 1 : 0] VAR10,
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s6s/sky130_fd_sc_ms__dlymetal6s6s.functional.v | 1,345 | module MODULE1 (
VAR5,
VAR4
);
output VAR5;
input VAR4;
wire VAR1;
buf VAR2 (VAR1, VAR4 );
buf VAR3 (VAR5 , VAR1 );
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/hpdmc_ddr32/rtl/virtex4/hpdmc_ddrio.v | 2,168 | module MODULE1(
input VAR4,
input VAR17,
input VAR13,
input VAR28,
input VAR12,
input VAR3,
input [7:0] VAR42,
input [63:0] do,
output [63:0] VAR18,
output [3:0] VAR43,
inout [31:0] VAR35,
inout [3:0] VAR21,
input VAR19,
input VAR32,
input VAR2
);
wire [31:0] VAR25;
assign VAR35 = VAR12 ? VAR25 : 32'VAR7;
assign VAR21 ... | lgpl-3.0 |
dawsonjon/fpu | int_to_float/int_to_float.v | 2,831 | module MODULE1(
VAR19,
VAR5,
VAR14,
clk,
rst,
VAR21,
VAR22,
VAR18);
input clk;
input rst;
input [31:0] VAR19;
input VAR5;
output VAR18;
output [31:0] VAR21;
output VAR22;
input VAR14;
reg VAR13;
reg [31:0] VAR16;
reg VAR23;
reg VAR6;
reg [2:0] state;
parameter VAR15 = 3'd0,
VAR20 = 3'd1,
VAR2 = 3'd2,
VAR4 = 3'd3,
VAR11... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/diode/sky130_fd_sc_hvl__diode.behavioral.v | 1,181 | module MODULE1 (
VAR3
);
input VAR3;
supply1 VAR4;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
sybreon/dcpu16 | rtl/verilog/dcpu16_cpu.v | 4,913 | module MODULE1 (
VAR15, VAR14, VAR22, VAR10, VAR28, VAR20, VAR35, VAR29,
rst, VAR33, VAR3, VAR13, VAR23, clk
);
output [15:0] VAR29; output [15:0] VAR35; output VAR20; output VAR28; output [15:0] VAR10; output [15:0] VAR22; output VAR14; output VAR15;
input clk; input VAR23; input [15:0] VAR13; input VAR3; input [15:0]... | lgpl-3.0 |
google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram | cells/gf180mcu_fd_ip_sram__sram128x8m8wm1/gf180mcu_fd_ip_sram__sram128x8m8wm1.v | 16,183 | module MODULE1 (
VAR46,
VAR1,
VAR38,
VAR30,
VAR4,
VAR33,
VAR10,
VAR18,
VAR2
);
input VAR46;
input VAR1; input VAR38; input [7:0] VAR30; input [6:0] VAR4;
input [7:0] VAR33;
output [7:0] VAR10;
inout VAR18;
inout VAR2;
reg [7:0] VAR16[127:0];
reg [7:0] VAR41;
wire VAR36;
wire VAR45;
wire VAR21;
reg VAR29; reg VAR34;
reg... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai.blackbox.v | 1,347 | module MODULE1 (
VAR9 ,
VAR3,
VAR1,
VAR6,
VAR4
);
output VAR9 ;
input VAR3;
input VAR1;
input VAR6;
input VAR4;
supply1 VAR5;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/bp_common/syn/v/bsg_mem_2r1w_sync.v | 3,372 | if (VAR3 == VAR4 && VAR9 == VAR33) \
begin: VAR13 \
VAR43 \
VAR35 \
(.VAR44 ( VAR44 ) \
,.VAR1 ( VAR1 ) \
,.VAR25 ( VAR25 ) \
,.VAR21( VAR21 ) \
,.VAR37( VAR37 ) \
,.VAR42 ( VAR29 ) \
,.VAR12( VAR15 ) \
,.VAR22( VAR24 ) \
); \
VAR43 \
VAR6 \
(.VAR44 ( VAR44 ) \
,.VAR1 ( VAR1 ) \
,.VAR25 ( VAR25 ) \
,.VAR21( VAR21 ) \
,... | bsd-3-clause |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC/clckctrl/greybox/unnamed.v | 2,913 | module MODULE1 (
VAR4,
VAR15,
VAR1);
input VAR4;
input VAR15;
output VAR1;
wire VAR11;
wire VAR5;
wire VAR9;
assign VAR11 = 1'b0;
assign VAR5 = 1'b1;
assign VAR9 = 1'b0;
wire \MODULE1|MODULE2|VAR10 ;
wire \VAR15~VAR16 ;
wire \VAR4~VAR16 ;
MODULE2 MODULE1(
.VAR1(\MODULE1|MODULE2|VAR10 ),
.VAR15(\VAR15~VAR16 ),
.VAR4(\VA... | bsd-3-clause |
vad-rulezz/megabot | minsoc/rtl/verilog/ethmac/rtl/verilog/eth_txstatem.v | 10,010 | module MODULE1 (VAR16, VAR42, VAR21, VAR29, VAR7, VAR43, VAR24,
VAR11, VAR6, VAR17, VAR12, VAR37, VAR48, VAR2,
VAR20, VAR1, VAR13, VAR10, VAR14, VAR34, VAR35,
VAR40, VAR33, VAR23, VAR47, VAR27, VAR15,
VAR30, VAR26, VAR41, VAR46, VAR38, VAR5,
VAR4, VAR22, VAR31, VAR39, VAR25, VAR28,
VAR32, VAR36, VAR9, VAR8, VAR19, VAR1... | gpl-2.0 |
olofk/wb_streamer | rtl/verilog/wb_stream_writer_ctrl.v | 2,462 | module MODULE1
parameter VAR6 = 32,
parameter VAR12 = 0,
parameter VAR16 = 0)
( input VAR32,
input VAR25,
output [VAR31-1:0] VAR21,
output [VAR6-1:0] VAR18,
output [VAR6/8-1:0] VAR15,
output VAR33 ,
output VAR1,
output VAR7,
output reg [2:0] VAR3,
output [1:0] VAR30,
input [VAR6-1:0] VAR10,
input VAR9,
input VAR8,
outp... | lgpl-3.0 |
kkalavantavanich/SD2017 | main.v | 26,444 | /* VAR57 VAR54 VAR18 VAR51 VAR4 VAR62 VAR122.
* VAR83 VAR8 VAR49 use/VAR102/VAR71 in VAR22 VAR63 VAR80 this VAR79 VAR16 VAR117 VAR56 VAR46.
* VAR42: VAR3:
module MODULE1(
input VAR115,
input [15:0] VAR7,
input VAR118,
input VAR24,
input VAR60,
input VAR103,
input VAR84,
output [15:0] VAR23,
output [6:0] VAR67,
output V... | mit |
sirchuckalot/zet-ng | rtl/v1_3_1/zet_rxr8.v | 1,595 | module MODULE1 (
input [7:0] VAR3,
input VAR2,
input [3:0] VAR1,
input VAR6,
output reg [7:0] VAR4,
output reg VAR5
);
always @(VAR3 or VAR2 or VAR1 or VAR6)
case (VAR1)
default: {VAR5,VAR4} <= {VAR2,VAR3};
5'd01: {VAR5,VAR4} <= VAR6 ? {VAR3[0], VAR2, VAR3[7:1]} : {VAR2, VAR3[0], VAR3[7:1]};
5'd02: {VAR5,VAR4} <= VAR6 ... | gpl-3.0 |
timtian090/Playground | UVM/UVMPlayground/Lab2/Lab2-Project/TF_CLS_PWM_Interval_Timer.v | 1,245 | module MODULE1();
wire VAR1;
reg VAR3;
localparam VAR4 = 50000000; localparam VAR2 = ((1.0 / VAR4) * 1000000000.0) / 2.0;
begin | mit |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_rs232_0.v | 9,590 | module MODULE1 (
clk,
reset,
address,
VAR17,
VAR35,
read,
write,
VAR7,
VAR34,
irq,
VAR37,
VAR9
);
parameter VAR18 = 9; parameter VAR10 = 434;
parameter VAR1 = 217;
parameter VAR15 = 10; parameter VAR21 = 8; parameter VAR2 = 1'b0;
input clk;
input reset;
input address;
input VAR17;
input [ 3: 0] VAR35;
input read;
input... | apache-2.0 |
finnball/igloo | projects/chip8/hdl/draw_screen.v | 2,144 | module MODULE1(
input clk,
output [VAR2 - 1 : 0] VAR14,
output [VAR22 - 1 : 0] VAR9,
output VAR5,
output VAR7,
output VAR18,
output VAR13
);
localparam VAR1 = 64;
localparam VAR3 = 32;
localparam VAR2 = VAR4(VAR1);
localparam VAR22 = VAR4(VAR3);
localparam VAR8 = 640;
localparam VAR12 = 480;
localparam VAR20 = VAR8 / V... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N8_M8_P5_syn.v | 2,470 | module MODULE1 ( VAR12, VAR71, VAR15 );
input [7:0] VAR12;
input [7:0] VAR71;
output [8:0] VAR15;
wire VAR53, VAR82, VAR29, VAR21, VAR41, VAR91, VAR67, VAR8, VAR84, VAR92, VAR60, VAR11, VAR83, VAR86,
VAR7, VAR61, VAR31, VAR46, VAR94, VAR4, VAR34, VAR57, VAR36, VAR22, VAR20, VAR76;
VAR50 VAR30 ( .VAR19(VAR12[3]), .VAR10... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf.pp.blackbox.v | 1,223 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1,
VAR4,
VAR3 ,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.pp.blackbox.v | 1,255 | module MODULE1 (
VAR7 ,
VAR5 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR2,
VAR6
);
output VAR7 ;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR2;
input VAR6;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_4.behavioral.pp.v | 1,236 | module MODULE1( VAR6, VAR5, VAR3, VAR4, VAR7 );
input VAR6, VAR5;
inout VAR4, VAR7;
output VAR3;
VAR8 VAR1(.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7));
VAR8 VAR2(.VAR6(VAR6),.VAR5(VAR5),.VAR3(VAR3),.VAR4(VAR4),.VAR7(VAR7)); | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_light/spw_light/spw_light_bb.v | 3,138 | module MODULE1 (
VAR21,
VAR13,
VAR22,
VAR6,
VAR4,
VAR39,
VAR5,
VAR36,
VAR28,
VAR23,
VAR1,
VAR46,
VAR2,
VAR7,
VAR16,
VAR33,
VAR14,
VAR18,
VAR29,
VAR10,
VAR45,
VAR26,
VAR35,
VAR25,
VAR24,
VAR38,
VAR31,
VAR44,
VAR47,
VAR43,
VAR32,
VAR19,
VAR41,
VAR11,
VAR20,
VAR42,
VAR17,
VAR27,
VAR37,
VAR34,
VAR15,
VAR8,
VAR12,
VAR30,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a211oi/sky130_fd_sc_hdll__a211oi_4.v | 2,377 | module MODULE2 (
VAR11 ,
VAR5 ,
VAR7 ,
VAR2 ,
VAR1 ,
VAR9,
VAR6,
VAR4 ,
VAR10
);
output VAR11 ;
input VAR5 ;
input VAR7 ;
input VAR2 ;
input VAR1 ;
input VAR9;
input VAR6;
input VAR4 ;
input VAR10 ;
VAR8 VAR3 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR4(VAR4),
.VA... | apache-2.0 |
sittner/lcnc-mdsio | vhdl/source/can/can_acf.v | 18,728 | module MODULE1
(
clk,
rst,
VAR11,
VAR9,
VAR21,
VAR28,
VAR6,
VAR4,
VAR1,
VAR22,
VAR20,
VAR2,
VAR16,
VAR27,
VAR26,
VAR10,
VAR8,
VAR19,
VAR12,
VAR15,
VAR25,
VAR3,
VAR14,
VAR17,
VAR7
);
parameter VAR13 = 1;
input clk;
input rst;
input [28:0] VAR11;
input VAR9;
input VAR21;
input VAR28;
input [7:0] VAR6;
input [7:0] VAR4;
i... | gpl-3.0 |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_triangle.v | 5,552 | module MODULE1
(
input wire VAR24, input wire VAR18, input wire VAR32, input wire VAR27, input wire VAR4, input wire VAR21, input wire [1:0] VAR1, input wire [7:0] din, input wire VAR31, output wire [3:0] VAR39, output wire VAR34 );
reg [10:0] VAR17;
wire [10:0] VAR16;
wire VAR40;
always @(posedge VAR24)
begin
if (VAR1... | mit |
lvd2/ngs | fpga/obsolete/fpgaC_release/main.v | 9,934 | module MODULE1(
VAR99, VAR134,
VAR80, VAR67,
VAR119,
VAR114, VAR56,
VAR87, VAR41, VAR100, VAR34, VAR59, VAR16, VAR75, VAR136, VAR133, VAR93,
VAR101, VAR46, VAR30, VAR78, VAR68, VAR90, VAR95, VAR92, VAR48, VAR66, VAR28, VAR26,
VAR102, VAR50, VAR45, VAR84, VAR53, VAR147, VAR107, VAR63, VAR17, VAR5, VAR51, VAR91, VAR8, VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.behavioral.pp.v | 1,868 | module MODULE1( VAR6, VAR1, VAR2, VAR4, VAR5, VAR10, VAR3 );
input VAR2, VAR1, VAR4, VAR5;
inout VAR10, VAR3;
output VAR6;
VAR8 VAR9(.VAR6(VAR6),.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5),.VAR10(VAR10),.VAR3(VAR3));
VAR8 VAR7(.VAR6(VAR6),.VAR1(VAR1),.VAR2(VAR2),.VAR4(VAR4),.VAR5(VAR5),.VAR10(VAR10),.VAR3(VAR3)); | apache-2.0 |
Jesus89/open-fpga-verilog-tutorial | tutorial/ICESTICK/T16-countsec/divider.v | 1,351 | module MODULE1(input wire VAR6, output wire VAR4);
parameter VAR2 = VAR5;
localparam VAR7 = VAR1(VAR2);
reg [VAR7-1:0] VAR3 = 0;
always @(posedge VAR6)
VAR3 <= (VAR3 == VAR2 - 1) ? 0 : VAR3 + 1;
assign VAR4 = VAR3[VAR7-1];
endmodule | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/tmu2/rtl/tmu2.v | 19,273 | module MODULE1 #(
parameter VAR204 = 4'h0,
parameter VAR160 = 26,
parameter VAR163 = 14
) (
input VAR120,
input VAR220,
input [13:0] VAR139,
input VAR212,
input [31:0] VAR124,
output [31:0] VAR200,
output irq,
output [31:0] VAR235,
output [2:0] VAR34,
output VAR153,
output VAR136,
input VAR116,
input [31:0] VAR89,
outp... | lgpl-3.0 |
olajep/oh | src/emesh/hdl/emesh_readback.v | 3,175 | module MODULE1 (
VAR2, VAR18, VAR20,
VAR14, clk, VAR24, VAR25, VAR17, VAR5
);
parameter VAR1 = 32; parameter VAR15 = 104;
input VAR14; input clk;
input VAR24; input [VAR15-1:0] VAR25; output VAR2;
input [63:0] VAR17;
output VAR18; output [VAR15-1:0] VAR20; input VAR5;
wire [4:0] VAR3; wire [VAR1-1:0] VAR16; wire [1:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a_4.v | 2,428 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR12 ,
VAR11 ,
VAR1 ,
VAR9 ,
VAR7,
VAR2,
VAR5 ,
VAR10
);
output VAR4 ;
input VAR8 ;
input VAR12 ;
input VAR11 ;
input VAR1 ;
input VAR9 ;
input VAR7;
input VAR2;
input VAR5 ;
input VAR10 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR12(VAR12),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2bb2a/sky130_fd_sc_ls__o2bb2a.blackbox.v | 1,389 | module MODULE1 (
VAR1 ,
VAR2,
VAR8,
VAR9 ,
VAR3
);
output VAR1 ;
input VAR2;
input VAR8;
input VAR9 ;
input VAR3 ;
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a_4.v | 2,428 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3 ,
VAR5 ,
VAR6 ,
VAR11 ,
VAR10,
VAR8,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR7 ;
input VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR11 ;
input VAR10;
input VAR8;
input VAR2 ;
input VAR1 ;
VAR9 VAR12 (
.VAR4(VAR4),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR11(VAR11),
.VAR10(V... | apache-2.0 |
FAST-Switch/fast | projects/SDTS/example/hw-src/send2controller/transmit.v | 10,557 | module MODULE1(
input clk,
input reset,
input VAR6,
input VAR24, input [138:0] VAR14,
output [7:0] VAR29,
input VAR55,
input [19:0] VAR51, input VAR4,
input [138:0] VAR46,
output [7:0] VAR26,
output reg VAR34,
output reg [29:0] VAR41,
output reg VAR42,
output reg [138:0] VAR1,
input [4:0] VAR63,
input VAR27 );
wire [13... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_decapkapwr/sky130_fd_sc_hd__lpflow_decapkapwr.pp.symbol.v | 1,321 | module MODULE1 (
input VAR3,
input VAR4 ,
input VAR5 ,
input VAR1 ,
input VAR2
);
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/cache/TwoWayCache.v | 12,488 | module MODULE1
(
input clk,
input reset, input VAR28,
output ready,
input [31:0] VAR31,
input VAR17,
output VAR55,
input VAR49, output reg VAR72, output reg VAR40, input VAR12, input VAR74,
input VAR48,
input [15:0] VAR73,
output [15:0] VAR47,
output reg [31:0] VAR67,
input [15:0] VAR52,
output reg [15:0] VAR32,
output... | gpl-3.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GDA_St_N8_M4_P4_syn.v | 2,313 | module MODULE1 ( VAR63, VAR49, VAR68 );
input [7:0] VAR63;
input [7:0] VAR49;
output [8:0] VAR68;
wire VAR25, VAR6, VAR18, VAR92, VAR79, VAR57, VAR9, VAR76, VAR65, VAR14, VAR23, VAR51, VAR52, VAR81,
VAR29, VAR10, VAR16, VAR8, VAR61, VAR87, VAR40, VAR70, VAR11, VAR71;
VAR73 VAR55 ( .VAR77(VAR49[7]), .VAR74(VAR51), .VAR7... | gpl-3.0 |
Lan-Hekary/ARM | Control.v | 2,794 | module MODULE1(input wire [31:0] VAR19, input wire [3:0] VAR17, input wire VAR13,
output reg VAR8, output reg VAR12, output reg VAR18,
output reg [1:0] VAR14, output reg VAR2, output reg [1:0] VAR10,
output reg VAR3, output reg VAR5 );
reg [3:0] VAR7;
reg VAR1;
always @* begin
VAR1 = 0;
case (VAR19[31:28])
4'b0000: if(... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.pp.symbol.v | 1,334 | module MODULE1 (
input VAR6 ,
input VAR7 ,
input VAR1 ,
input VAR8 ,
output VAR9 ,
input VAR5 ,
input VAR3,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
Ribeiro/sd2snes | verilog/sd2snes_obc1/cheat.v | 6,568 | module MODULE1(
input clk,
input [23:0] VAR3,
input [7:0] VAR8,
input VAR18,
input VAR36,
input VAR31,
input [2:0] VAR21,
input VAR33,
input [31:0] VAR14,
output [7:0] VAR5,
output VAR11,
output VAR39
);
reg VAR16 = 0;
reg VAR7 = 0;
reg VAR22 = 0;
reg VAR4 = 0;
reg VAR9 = 1;
reg VAR15 = 0;
reg VAR10 = 0;
reg VAR24 = 0;... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a21oi/sky130_fd_sc_ms__a21oi.pp.symbol.v | 1,352 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR8 ,
output VAR5 ,
input VAR4 ,
input VAR7,
input VAR2,
input VAR1
);
endmodule | apache-2.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | projects/KC705_experimental/KC705_experimental.srcs/sources_1/ip/xadc_temp_sensor/xadc_temp_sensor.v | 8,585 | module MODULE1
(
VAR68, VAR34, VAR42, VAR60, VAR66, VAR57, VAR43, VAR9, VAR48, VAR19, VAR73, VAR40, VAR38, VAR78, VAR63, VAR16, VAR18, VAR36);
input [6:0] VAR68;
input VAR34;
input VAR42;
input [15:0] VAR60;
input VAR66;
input VAR18;
input VAR36;
output VAR57;
output [4:0] VAR43;
output [15:0] VAR9;
output VAR48;
outpu... | gpl-3.0 |
wamgoo/FPGA-Imaging-Library | Generator/CountGenerator/CountGenerator.srcs/sources_1/new/CountGenerator.v | 3,782 | module MODULE1(
clk,
VAR9,
VAR6,
VAR11,
VAR5,
VAR10,
VAR12,
VAR2);
parameter VAR8 = 0;
parameter VAR7 = 8;
parameter VAR4 = 320;
parameter VAR1 = 240;
parameter VAR3 = 9;
input clk;
input VAR9;
input VAR6;
input [VAR7 - 1 : 0] VAR11;
output VAR5;
output[VAR7 - 1 : 0] VAR10;
output reg[VAR3 - 1 : 0] VAR12;
output reg[VA... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.blackbox.v | 1,345 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR1;
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
karatekid/ultrasonic-fountain | hardware/src/mojo_com_logic.v | 2,248 | module MODULE1 #(
parameter VAR16 = 256
)(
input clk,
input rst,
input [VAR12-1:0] VAR29,
input write,
input VAR17,
input [7:0] VAR3,
output [7:0] VAR26,
input VAR11,
output [8*VAR16-1:0] VAR13,
output VAR5,
output VAR20,
input [8*VAR16-1:0] VAR14,
output VAR30
);
parameter VAR12 = VAR8(VAR16);
parameter VAR22 = 8;
par... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb.pp.symbol.v | 1,328 | module MODULE1 (
input VAR8 ,
input VAR6 ,
input VAR2 ,
input VAR1 ,
output VAR7 ,
input VAR4 ,
input VAR5,
input VAR3,
input VAR9
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/analog/bw_clk/rtl/bw_clk_cclk_hdr_64x.v | 3,245 | module MODULE1 (
VAR5, VAR24, clk, VAR22,
VAR8, VAR6, VAR15, VAR20, VAR28, VAR4, VAR21, VAR12,
VAR25
);
input VAR8;
input VAR25;
input VAR6;
input VAR15;
input VAR20;
input VAR28;
input VAR4;
output VAR24;
output VAR5;
output clk;
input VAR21; input VAR12;
output VAR22;
wire VAR14;
wire VAR10;
wire VAR11;
wire VAR24;
w... | gpl-2.0 |
m13253/riscade | hdl/src/step_ex_ld.v | 1,389 | module MODULE1(clk, rst, VAR7, VAR8,
VAR11, VAR12, VAR4,
VAR10, VAR3, VAR5);
input clk;
input rst;
input VAR7;
output VAR8;
output VAR11;
output[7:0] VAR12;
input[7:0] VAR4;
input[7:0] VAR10;
output[7:0] VAR3;
output VAR5;
reg VAR9;
assign VAR8 = VAR9 ? 1'b0 : 1'VAR1;
reg VAR6;
assign VAR11 = VAR6 ? 1'b0 : 1'VAR1;
assi... | mit |
SymbiFlow/prjxray | fuzzers/050-pip-seed/top.v | 2,113 | module MODULE2(input clk, din, VAR29, output dout);
reg [41:0] VAR2;
wire [78:0] VAR5;
reg [41:0] VAR12;
reg [78:0] VAR20;
always @(posedge clk) begin
if (VAR29) begin
VAR2 <= VAR12;
VAR20 <= VAR5;
end else begin
VAR12 <= {VAR12, din};
VAR20 <= {VAR20, VAR12[41]};
end
end
assign dout = VAR20[78];
MODULE3 MODULE3 (
.clk... | isc |
htogarcia/Microcontrolador-Calculadora | arm/InstructionMemory.v | 3,886 | module MODULE1(
output reg[31:0] VAR1,
input [31:0] VAR2
);
always @ (*) begin
case (VAR2)
32'h00000004: VAR1 = 32'hE3A00000; 32'h00000008: VAR1 = 32'hE3A04004; 32'h0000000c: VAR1 = 32'hE3A05010; 32'h00000010: VAR1 = 32'hE3A06014; 32'h00000014: VAR1 = 32'hE3A07018; 23'h00000018: VAR1 = 32'hE3A0D024; 32'h0000001c: VAR1 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd2/sky130_fd_sc_ms__clkdlyinv3sd2.behavioral.pp.v | 1,867 | module MODULE1 (
VAR12 ,
VAR8 ,
VAR3,
VAR10,
VAR7 ,
VAR6
);
output VAR12 ;
input VAR8 ;
input VAR3;
input VAR10;
input VAR7 ;
input VAR6 ;
wire VAR4 ;
wire VAR1;
not VAR5 (VAR4 , VAR8 );
VAR2 VAR11 (VAR1, VAR4, VAR3, VAR10);
buf VAR9 (VAR12 , VAR1 );
endmodule | apache-2.0 |
petrmikheev/miksys | verilog/COMMAND_RAM_bb.v | 7,515 | module MODULE1 (
VAR5,
VAR2,
VAR3,
VAR4,
VAR1,
VAR6);
input VAR5;
input [15:0] VAR2;
input [10:0] VAR3;
input [11:0] VAR4;
input VAR1;
output [31:0] VAR6;
tri1 VAR5;
tri0 VAR1;
endmodule | gpl-3.0 |
gralco/mojo-ide | Mojo IDE/base/mojo-v2/source/spi_slave.v | 1,414 | module MODULE1(
input clk,
input rst,
input VAR16,
input VAR11,
output VAR17,
input VAR3,
output VAR6,
input [7:0] din,
output [7:0] dout
);
reg VAR10, VAR20;
reg VAR1, VAR15;
reg VAR12, VAR2;
reg VAR22, VAR7;
reg [7:0] VAR14, VAR23;
reg VAR4, VAR19;
reg [2:0] VAR5, VAR9;
reg [7:0] VAR18, VAR21;
reg VAR13, VAR8;
assign... | gpl-3.0 |
secworks/6502 | src/rtl/m6502.v | 11,874 | module MODULE1(
input wire clk,
input wire VAR104,
output wire VAR35,
output wire wr,
output wire [15 : 0] address,
input wire VAR25,
input wire VAR63,
input wire [7 : 0] VAR22,
output wire [7 : 0] VAR70
);
localparam VAR21 = 16'h0000;
localparam VAR33 = 1'h0;
localparam VAR27 = 1'h1;
localparam VAR31 = 2'h0;
localpara... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.behavioral.pp.v | 2,016 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR12 ,
VAR3 ,
VAR9,
VAR10,
VAR11 ,
VAR2
);
output VAR7 ;
input VAR6 ;
input VAR12 ;
input VAR3 ;
input VAR9;
input VAR10;
input VAR11 ;
input VAR2 ;
wire VAR8 ;
wire VAR5 ;
wire VAR4;
and VAR15 (VAR8 , VAR6, VAR12 );
nor VAR1 (VAR5 , VAR3, VAR8 );
VAR14 VAR13 (VAR4, VAR5, VAR9, VAR10);
b... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o221ai/sky130_fd_sc_ls__o221ai_2.v | 2,457 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR8 ,
VAR1 ,
VAR2 ,
VAR7 ,
VAR3,
VAR11,
VAR9 ,
VAR6
);
output VAR4 ;
input VAR5 ;
input VAR8 ;
input VAR1 ;
input VAR2 ;
input VAR7 ;
input VAR3;
input VAR11;
input VAR9 ;
input VAR6 ;
VAR10 VAR12 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR3(VAR3)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_isosrchvaon/sky130_fd_sc_hvl__lsbuflv2hv_isosrchvaon_1.v | 2,651 | module MODULE2 (
VAR6 ,
VAR9 ,
VAR5,
VAR8 ,
VAR7 ,
VAR10 ,
VAR2 ,
VAR4
);
output VAR6 ;
input VAR9 ;
input VAR5;
input VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR2 ;
input VAR4 ;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfrtn/sky130_fd_sc_ls__dfrtn.pp.blackbox.v | 1,401 | module MODULE1 (
VAR1 ,
VAR5 ,
VAR7 ,
VAR8,
VAR3 ,
VAR2 ,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR7 ;
input VAR8;
input VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
kevintownsend/R3 | coregen/fifo_36x512_hf.v | 15,289 | module MODULE2 (
clk, VAR137, rst, VAR117, VAR133, VAR39, VAR8, VAR100, dout, din
);
input clk;
input VAR137;
input rst;
output VAR117;
input VAR133;
output VAR39;
output VAR8;
output VAR100;
output [35 : 0] dout;
input [35 : 0] din;
wire VAR33;
wire VAR108;
wire \VAR104/VAR22/VAR82.VAR126/VAR84.VAR63/VAR119/VAR37 ;
wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/xor2/sky130_fd_sc_hdll__xor2.functional.pp.v | 1,832 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR11 ,
VAR10,
VAR9,
VAR5 ,
VAR1
);
output VAR8 ;
input VAR3 ;
input VAR11 ;
input VAR10;
input VAR9;
input VAR5 ;
input VAR1 ;
wire VAR12 ;
wire VAR13;
xor VAR7 (VAR12 , VAR11, VAR3 );
VAR4 VAR6 (VAR13, VAR12, VAR10, VAR9);
buf VAR2 (VAR8 , VAR13 );
endmodule | apache-2.0 |
ymei/TMSPlane | Firmware/src/aurora64b66b/KC705/aurora_64b66b_0_support_reset_logic.v | 11,210 | module MODULE2
(
VAR38,
VAR12,
VAR36,
VAR25,
VAR1,
VAR8
);
input VAR38;
input VAR12;
input VAR36;
input VAR25;
output VAR1;
output VAR8;
reg [0:3] VAR41 = 4'h0;
reg VAR1 = 1'b1;
reg VAR7 = 1'b0;
reg [19:0] VAR20 = 20'h00000;
reg [0:3] VAR49 = 4'h0;
wire VAR6;
MODULE1 #
(
.VAR2 (5)
)VAR26
(
.VAR17 (VAR7),
.VAR21 (VAR12)... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/ecc/ecc_buf.v | 6,155 | module MODULE1
parameter VAR23 = 100,
parameter VAR29 = 64,
parameter VAR22 = 4,
parameter VAR5 = 1,
parameter VAR30 = 64
)
(
VAR26,
clk, rst, VAR15, VAR40, VAR11,
VAR21, VAR37, VAR24
);
input clk;
input rst;
input [VAR22-1:0] VAR15;
input [VAR5-1:0] VAR40;
wire [4:0] VAR1;
input [VAR22-1:0] VAR11;
input [VAR5-1:0] VAR... | lgpl-3.0 |
bpervan/zedboard | LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_processing_system7_0_0/hdl/processing_system7_bfm_v2_0_arb_hp2_3.v | 3,360 | module MODULE1(
VAR7,
VAR22,
VAR65,
VAR43,
VAR20,
VAR46,
VAR6,
VAR64,
VAR61,
VAR58,
VAR57,
VAR9,
VAR66,
VAR24,
VAR23,
VAR21,
VAR32,
VAR39,
VAR12,
VAR44,
VAR60,
VAR2,
VAR8,
VAR49,
VAR56,
VAR3,
VAR36,
VAR63,
VAR5,
VAR62,
VAR48,
VAR54,
VAR16,
VAR52,
VAR28,
VAR55,
VAR27,
VAR40
);
input VAR7;
input VAR22;
input [VAR67-1:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi_1.v | 2,332 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR4 ,
VAR2,
VAR9,
VAR3,
VAR5 ,
VAR1
);
output VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR2;
input VAR9;
input VAR3;
input VAR5 ;
input VAR1 ;
VAR8 VAR10 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
V... | apache-2.0 |
e33b1711/rfnoc_pp_channelizer | sysgen_models/syntheses/checkpoint/sysgen/xlclockdriver_rd.v | 5,347 | module MODULE1 (VAR21, VAR22, VAR3, clk, VAR15, VAR1, VAR24);
parameter signed [31:0] VAR28 = 1;
parameter signed [31:0] period = 2;
parameter signed [31:0] VAR9 = 1'b0;
parameter signed [31:0] VAR7 = 5;
input VAR21;
input VAR22;
input VAR3;
output clk;
output VAR15;
output VAR1;
output VAR24;
parameter signed [31:0] V... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyd/gf180mcu_fd_sc_mcu7t5v0__dlyd_2.behavioral.v | 1,098 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR4 VAR3(.VAR5(VAR5),.VAR1(VAR1));
VAR4 VAR2(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.behavioral.v | 1,032 | module MODULE1( VAR3 );
input VAR3;
VAR2 VAR4(.VAR3(VAR3));
VAR2 VAR1(.VAR3(VAR3)); | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_cx4/main.v | 24,728 | module MODULE1(
output [22:0] VAR316,
output VAR262,
input VAR338,
output VAR274,
input VAR30,
output [21:0] VAR316,
output VAR350,
output VAR251,
output VAR304,
output VAR360,
output VAR88,
input VAR235,
input VAR81,
input [23:0] VAR52,
input VAR104,
input VAR59,
input VAR287,
inout [7:0] VAR43,
input VAR221,
input VA... | gpl-2.0 |
Microsoft/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/rx_mem_data_fsm.v | 14,752 | module MODULE1(
input wire clk,
input wire rst,
output reg [127:0] VAR32,
output reg VAR34,
output reg [2:0] VAR13,
output reg [27:6] VAR9,
output reg VAR5,
input wire VAR39,
input wire VAR19, input wire [27:6] VAR2,
input wire [10:0] VAR18,
input wire VAR25, input wire VAR31,
output reg VAR1,
input wire [127:0] VAR20,... | bsd-2-clause |
mcoughli/root_of_trust | operational_os/hls/contact_discovery_hls_2017.1/solution1/impl/verilog/contact_discovery_AXILiteS_s_axi.v | 12,293 | module MODULE1
VAR75 = 6,
VAR57 = 32
)(
input wire VAR12,
input wire VAR14,
input wire VAR5,
input wire [VAR75-1:0] VAR55,
input wire VAR60,
output wire VAR42,
input wire [VAR57-1:0] VAR66,
input wire [VAR57/8-1:0] VAR13,
input wire VAR20,
output wire VAR43,
output wire [1:0] VAR72,
output wire VAR35,
input wire VAR19,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21bo/sky130_fd_sc_lp__a21bo.pp.symbol.v | 1,385 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR2,
output VAR1 ,
input VAR4 ,
input VAR5,
input VAR7,
input VAR8
);
endmodule | apache-2.0 |
kmod/bitcoin_mining | fpga/ipcore_dir/dcm.v | 5,487 | module MODULE1
( input VAR29,
output VAR24
);
VAR30 VAR13
(.VAR7 (VAR26),
.VAR8 (VAR29));
wire VAR42;
wire VAR25;
wire [7:0] VAR48;
wire VAR22;
wire VAR36;
wire VAR10;
VAR19
.VAR35 (5),
.VAR37 (4),
.VAR28 ("VAR31"),
.VAR47 (10.0),
.VAR33 ("VAR43"),
.VAR6 ("1X"),
.VAR41 ("VAR39"),
.VAR17 (0),
.VAR44 ("VAR31"))
VAR4
(.VA... | gpl-2.0 |
mattmckillip/Cpre281 | Final Project - Vending Machine/nsl.v | 1,729 | module MODULE1(VAR29,VAR9,VAR13,VAR35,VAR17,VAR31,VAR25,VAR27,VAR5,VAR15);
input VAR29,VAR9,VAR13,VAR35;
output VAR27,VAR5,VAR15;
reg VAR27,VAR5,VAR15;
always@(VAR29 or VAR9 or VAR13 or VAR35)
begin
casex({VAR29,VAR9,VAR13,VAR35})
7'b0000000: VAR19= 3'b000;
7'b0000001: VAR19= 3'b001;
7'b0000010: VAR19= 3'b010;
7'b00000... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/maj3/sky130_fd_sc_ls__maj3_4.v | 2,174 | module MODULE1 (
VAR7 ,
VAR1 ,
VAR6 ,
VAR9 ,
VAR5,
VAR3,
VAR4 ,
VAR8
);
output VAR7 ;
input VAR1 ;
input VAR6 ;
input VAR9 ;
input VAR5;
input VAR3;
input VAR4 ;
input VAR8 ;
VAR2 VAR10 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufbuf/sky130_fd_sc_ls__bufbuf.functional.v | 1,245 | module MODULE1 (
VAR5,
VAR3
);
output VAR5;
input VAR3;
wire VAR2;
buf VAR1 (VAR2, VAR3 );
buf VAR4 (VAR5 , VAR2 );
endmodule | apache-2.0 |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/internal_dma_ctrl.v | 7,516 | module MODULE1
(
input clk,
input rst,
input [31:0] VAR2,
input [6:0] VAR1,
input [6:0] VAR11,
input VAR8,
output reg [31:0] VAR9,
output [63:0] VAR14, output reg [31:0] VAR10, output reg [31:0] VAR6,
output VAR3, input VAR13,
input [31:0] VAR15,
input [31:0] VAR12
);
reg [31:0] VAR7, VAR5;
reg [31:0] VAR4;
assign VAR1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlrtp/sky130_fd_sc_hdll__dlrtp_1.v | 2,378 | module MODULE1 (
VAR3 ,
VAR7,
VAR2 ,
VAR8 ,
VAR1 ,
VAR10 ,
VAR4 ,
VAR6
);
output VAR3 ;
input VAR7;
input VAR2 ;
input VAR8 ;
input VAR1 ;
input VAR10 ;
input VAR4 ;
input VAR6 ;
VAR5 VAR9 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODU... | apache-2.0 |
katherinejlu/ece3400 | code dump/ECE3400/Lab3_team1/DE0_NANO.v | 3,919 | module MODULE1(
VAR20,
VAR12,
VAR19,
VAR5,
VAR8,
VAR4,
VAR25,
VAR24,
);
localparam VAR3 = 25000000;
input VAR20;
output [7:0] VAR12;
input [1:0] VAR19;
input [3:0] VAR5;
inout [33:0] VAR8;
input [1:0] VAR4;
inout [33:0] VAR25;
input [1:0] VAR24;
reg VAR11;
wire reset; reg address;
wire [9:0] VAR10; wire [9:0] VAR16; wi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor2/sky130_fd_sc_ms__nor2.functional.pp.v | 1,783 | module MODULE1 (
VAR9 ,
VAR3 ,
VAR8 ,
VAR13,
VAR1,
VAR7 ,
VAR5
);
output VAR9 ;
input VAR3 ;
input VAR8 ;
input VAR13;
input VAR1;
input VAR7 ;
input VAR5 ;
wire VAR6 ;
wire VAR12;
nor VAR10 (VAR6 , VAR3, VAR8 );
VAR11 VAR4 (VAR12, VAR6, VAR13, VAR1);
buf VAR2 (VAR9 , VAR12 );
endmodule | apache-2.0 |
racerxdl/SuperINT | Slave Codes/FPGA/FrequencyCounter.v | 2,120 | module MODULE1(
input clk,
input VAR7,
output [23:0] VAR6
);
parameter VAR2 = 8001800;
reg [23:0] counter = 0; reg [23:0] VAR4 = 0; reg [23:0] VAR5 = 0; reg VAR3 = 0; reg VAR1 = 0;
always @(posedge clk)
begin
if(VAR5 == VAR2)
begin
VAR5 <= 0;
VAR3 <= 1;
VAR4 <= counter*2;
end
else
if(~VAR3)
VAR5 <= VAR5 + 1;
if(VAR1)
V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2.behavioral.v | 1,625 | module MODULE1 (
VAR8 ,
VAR5,
VAR11,
VAR3
);
output VAR8 ;
input VAR5;
input VAR11;
input VAR3 ;
supply1 VAR12;
supply0 VAR6;
supply1 VAR4 ;
supply0 VAR1 ;
wire VAR9;
VAR10 VAR7 (VAR9, VAR5, VAR11, VAR3 );
buf VAR2 (VAR8 , VAR9);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapvgnd/sky130_fd_sc_hs__tapvgnd.pp.blackbox.v | 1,205 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/output_queues/sram_rr_output_queues/src/oq_regs_dual_port_ram.v | 1,752 | module MODULE1
parameter VAR2 = VAR10,
parameter VAR9 = 8,
parameter VAR4 = VAR11(VAR9)
)
(
input [VAR4-1:0] VAR16,
input VAR14,
input [VAR2-1:0] VAR1,
output reg [VAR2-1:0] VAR15,
input VAR17,
input [VAR4-1:0] VAR13,
input VAR12,
input [VAR2-1:0] VAR7,
output reg [VAR2-1:0] VAR3,
input VAR6
);
function integer VAR11;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd2/sky130_fd_sc_hs__dlygate4sd2.symbol.v | 1,286 | module MODULE1 (
input VAR3,
output VAR1
);
supply1 VAR2;
supply0 VAR4;
endmodule | apache-2.0 |
cynngah/virtualsynthesizer | sound_files/Altera_UP_Audio_In_Deserializer.v | 9,343 | module MODULE1 (
clk,
reset,
VAR22,
VAR8,
VAR19,
VAR21,
VAR30,
VAR2,
VAR1,
VAR20,
VAR35,
VAR36,
VAR13,
VAR9
);
parameter VAR38 = 16;
parameter VAR25 = 5'h0F;
input clk;
input reset;
input VAR22;
input VAR8;
input VAR19;
input VAR21;
input VAR30;
input VAR2;
input VAR1;
input VAR20;
output reg [7:0] VAR35;
output reg [7... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ccx/rtl/cpx_io_grant_ff.v | 2,046 | module MODULE1(
VAR4, VAR8,
VAR5, VAR3, VAR9, VAR6
);
output [7:0] VAR4;
output VAR8;
input [7:0] VAR5;
input VAR3;
input VAR9;
input VAR6;
VAR7 #(8) VAR1(
.din (VAR5[7:0]),
.VAR2 (VAR4[7:0]),
.clk (VAR3),
.VAR6 (1'b0),
.VAR9 (8'd0),
.VAR8 ());
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b_1.v | 2,127 | module MODULE2 (
VAR1 ,
VAR3 ,
VAR6 ,
VAR5,
VAR7,
VAR8 ,
VAR9
);
output VAR1 ;
input VAR3 ;
input VAR6 ;
input VAR5;
input VAR7;
input VAR8 ;
input VAR9 ;
VAR2 VAR4 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR1 ,
VAR3 ,
VAR6
);
output VAR1... | apache-2.0 |
asicguy/gplgpu | stim/graph_core_stim.v | 45,668 | module MODULE1;
parameter
VAR106 = 4,
VAR107 = 2,
VAR106 = 8,
VAR107 = 3,
VAR106 = 16,
VAR107 = 4,
VAR106 = 32,
VAR107 = 5,
VAR162 = 32'h800,
VAR165 = 4,
VAR40 = 29,
VAR51 = 2,
VAR36 = 4,
VAR139 = 3,
VAR167 = 2,
VAR156 = 2,
VAR131 = 4,
VAR177 = 3;
reg VAR142 = 0;
reg VAR132; reg VAR95; reg VAR168; wire VAR44; reg VAR18... | gpl-3.0 |
miamiasheep/nctu-dlab-99 | lab4/t_counter.v | 1,485 | module MODULE1;
reg [3:0] VAR7;
reg VAR5;
reg [1:0] VAR4;
wire [7:0] VAR6;
counter VAR3 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR4(VAR4)
); | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi_4.v | 2,350 | module MODULE1 (
VAR3 ,
VAR8,
VAR6,
VAR5 ,
VAR4 ,
VAR9,
VAR1
);
output VAR3 ;
input VAR8;
input VAR6;
input VAR5 ;
input VAR4 ;
input VAR9;
input VAR1;
VAR7 VAR2 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR3 ,
VAR8,
VAR6,
VAR5 ,
VAR4
);
ou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sedfxbp/sky130_fd_sc_hdll__sedfxbp.functional.v | 2,050 | module MODULE1 (
VAR10 ,
VAR18,
VAR6,
VAR11 ,
VAR3 ,
VAR13,
VAR8
);
output VAR10 ;
output VAR18;
input VAR6;
input VAR11 ;
input VAR3 ;
input VAR13;
input VAR8;
wire VAR17 ;
wire VAR2;
wire VAR16 ;
VAR7 VAR14 (VAR2, VAR16, VAR13, VAR8 );
VAR7 VAR15 (VAR16 , VAR17, VAR11, VAR3 );
VAR1 VAR9 VAR4 (VAR17 , VAR2, VAR6 );
bu... | apache-2.0 |
google/CFU-Playground | soc/cfu/Cfu.v | 2,051 | module MODULE1 (
input VAR3,
output VAR5,
input [2:0] VAR2,
input [31:0] VAR10,
input [31:0] VAR11,
output VAR12,
input VAR8,
output [31:0] VAR9,
input clk,
input reset
);
assign VAR12 = VAR3;
assign VAR5 = VAR8;
wire [31:0] VAR6;
assign VAR6[31:0] = VAR10[7:0] + VAR11[7:0] +
VAR10[15:8] + VAR11[15:8] +
VAR10[23:16] + ... | apache-2.0 |
chrisfrederickson/verilog-nerf-sentry | Nerf_Sentry_sm3.v | 3,683 | module MODULE1(VAR1, VAR5, VAR9, reset, pos, VAR12);
input VAR1;
input [7:0] VAR5;
input VAR9;
input reset;
output reg [7:0] pos;
output reg VAR12;
reg [4:0] state;
reg [7:0] VAR14;
reg [7:0] VAR27, VAR22, VAR21;
parameter VAR13 = 5'b00000,
VAR19 = 5'b00001,
VAR17 = 5'b00010,
VAR15 = 5'b00011,
VAR18 = 5'b00100,
VAR8 = ... | mit |
hoglet67/CoPro6502 | src/zet/zet/zet_memory_regs.v | 1,794 | module MODULE1 (
input [2:0] VAR2,
input [1:0] VAR4,
input [2:0] VAR3,
output reg [3:0] VAR5,
output reg [3:0] VAR7,
output [1:0] VAR6
);
reg [1:0] VAR1;
assign VAR6 = VAR3[2] ? VAR3[1:0] : VAR1;
always @(VAR2 or VAR4)
case (VAR2)
3'b000: begin VAR5 <= 4'b0011; VAR7 <= 4'b0110; VAR1 <= 2'b11; end
3'b001: begin VAR5 <= ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.behavioral.pp.v | 2,529 | module MODULE1 (
VAR10,
VAR13 ,
VAR5,
VAR24 ,
VAR7,
VAR17,
VAR23 ,
VAR18
);
output VAR10;
input VAR13 ;
input VAR5;
input VAR24 ;
input VAR7;
input VAR17;
input VAR23 ;
input VAR18 ;
wire VAR9 ;
wire VAR25 ;
wire VAR16 ;
wire VAR14 ;
wire VAR19 ;
wire VAR8 ;
wire VAR11;
reg VAR3 ;
wire VAR2 ;
wire VAR21 ;
wire VAR4 ;
n... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a221o/sky130_fd_sc_lp__a221o.functional.v | 1,566 | module MODULE1 (
VAR1 ,
VAR10,
VAR8,
VAR7,
VAR3,
VAR4
);
output VAR1 ;
input VAR10;
input VAR8;
input VAR7;
input VAR3;
input VAR4;
wire VAR11 ;
wire VAR6 ;
wire VAR2;
and VAR9 (VAR11 , VAR7, VAR3 );
and VAR12 (VAR6 , VAR10, VAR8 );
or VAR13 (VAR2, VAR6, VAR11, VAR4);
buf VAR5 (VAR1 , VAR2 );
endmodule | apache-2.0 |
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