repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
peteasa/parallella-fpga | AdiHDLLib/library/common/sync_bits.v | 3,410 | module MODULE1
(
input [VAR6-1:0] in,
input VAR4,
input VAR5,
output [VAR6-1:0] out
);
parameter VAR6 = 1;
parameter VAR2 = 1;
reg [VAR6-1:0] VAR1 = 'h0;
reg [VAR6-1:0] VAR3 = 'h0;
always @(posedge VAR5)
begin
if (VAR4 == 1'b0) begin
VAR1 <= 'b0;
VAR3 <= 'b0;
end else begin
VAR1 <= in;
VAR3 <= VAR1;
end
end
assign out ... | lgpl-3.0 |
neale/CS-program | 474-VLSI/Lab_5/db/phase_altpll.v | 4,545 | module MODULE1
(
VAR2,
clk,
VAR7,
VAR6) ;
input VAR2;
output [4:0] clk;
input [1:0] VAR7;
output VAR6;
tri0 VAR2;
tri0 [1:0] VAR7;
reg VAR5;
wire [4:0] VAR4;
wire VAR1;
wire VAR3; | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31ai/sky130_fd_sc_ls__o31ai.pp.symbol.v | 1,359 | module MODULE1 (
input VAR8 ,
input VAR4 ,
input VAR1 ,
input VAR6 ,
output VAR9 ,
input VAR7 ,
input VAR5,
input VAR2,
input VAR3
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a22oi/sky130_fd_sc_hdll__a22oi_1.v | 2,368 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR2 ,
VAR6 ,
VAR4 ,
VAR1,
VAR5,
VAR8 ,
VAR9
);
output VAR7 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR4 ;
input VAR1;
input VAR5;
input VAR8 ;
input VAR9 ;
VAR10 VAR11 (
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv.pp.symbol.v | 1,264 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR4 ,
input VAR2,
input VAR3,
input VAR1
);
endmodule | apache-2.0 |
rohit21122012/CPU | ALU/Arith/Signed/Signed.v | 1,106 | module MODULE1(output [31:0] VAR4, input [31:0] VAR10,input [31:0] VAR14,input [1:0] VAR5);
output [31:0] VAR3;
output [31:0] VAR6;
output [63:0] VAR20;
output [31:0] VAR12;
output [31:0] VAR8;
wire VAR22;
wire VAR11;
VAR13 VAR15(VAR3, VAR8, VAR10, VAR14);
VAR18 VAR23(VAR6, VAR8, VAR10, VAR14);
VAR17 VAR19(VAR20, VAR10... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | models/udp_dlatch_pr/sky130_fd_sc_ms__udp_dlatch_pr.blackbox.v | 1,291 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR4 ,
VAR1
);
output VAR3 ;
input VAR2 ;
input VAR4 ;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/decaphe/sky130_fd_sc_ls__decaphe_6.v | 1,899 | module MODULE1 (
VAR3,
VAR6,
VAR1 ,
VAR4
);
input VAR3;
input VAR6;
input VAR1 ;
input VAR4 ;
VAR5 VAR2 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule
module MODULE1 ();
supply1 VAR3;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR4 ;
VAR5 VAR2 ();
endmodule | apache-2.0 |
James534/SubZero | SubZero/fpga/fpga_hw/top_level/DE0_Nano_SOPC/synthesis/submodules/altera_avalon_st_pipeline_base.v | 4,579 | module MODULE1 (
clk,
reset,
VAR13,
VAR1,
VAR11,
VAR5,
VAR7,
VAR9
);
parameter VAR8 = 1;
parameter VAR3 = 8;
parameter VAR16 = 1;
localparam VAR15 = VAR8 * VAR3;
input clk;
input reset;
output VAR13;
input VAR1;
input [VAR15-1:0] VAR11;
input VAR5;
output VAR7;
output [VAR15-1:0] VAR9;
reg VAR12;
reg VAR6;
reg [VAR15-1... | mit |
MCDELTAT/CSE311 | lab4/asm_ex.v | 1,485 | module MODULE1(
input clk, VAR7, reset,
input [3:0] din,
output reg [6:0] dout,
output reg VAR1
);
reg [1:0] VAR8, VAR3;
reg [3:0] VAR9, VAR4;
reg [6:0] VAR11, VAR2;
localparam VAR10=2'b00, VAR5=2'b01, VAR6=2'b10;
always @(posedge clk, posedge reset)
if (reset)
begin
VAR3 <= VAR10;
VAR4 <= 0;
VAR2 <= 1;
end
else
begin
... | mit |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_mm_bridge_0/ghrd_10as066n2_mm_bridge_0_bb.v | 1,883 | module MODULE1 #(
parameter VAR15 = 512,
parameter VAR22 = 8,
parameter VAR3 = 32,
parameter VAR1 = 5,
parameter VAR25 = 1,
parameter VAR10 = 1
) (
input wire clk, input wire VAR16, input wire [VAR15-1:0] VAR7, input wire VAR20, output wire [VAR1-1:0] VAR11, output wire [VAR15-1:0] VAR14, output wire [VAR3-1:0] VAR4, o... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_16.behavioral.v | 1,106 | module MODULE1( VAR5, VAR1 );
input VAR5;
output VAR1;
VAR3 VAR2(.VAR5(VAR5),.VAR1(VAR1));
VAR3 VAR4(.VAR5(VAR5),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s6s/sky130_fd_sc_ls__dlymetal6s6s.functional.v | 1,345 | module MODULE1 (
VAR1,
VAR5
);
output VAR1;
input VAR5;
wire VAR3;
buf VAR2 (VAR3, VAR5 );
buf VAR4 (VAR1 , VAR3 );
endmodule | apache-2.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/bus/interconnect/wishbone_interconnect.v | 4,989 | module MODULE1 (
input clk,
input rst,
input VAR7,
input VAR14,
input VAR40,
input [3:0] VAR26,
input [31:0] VAR3,
input [31:0] VAR22,
output reg [31:0] VAR19,
output reg VAR41,
output VAR31,
output VAR28,
output VAR4,
output VAR27,
output [3:0] VAR21,
input VAR33,
output [31:0] VAR36,
input [31:0] VAR23,
output [31:0]... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_cmp/float_cmp_bb.v | 3,402 | module MODULE1 (
VAR6,
VAR2,
VAR5,
VAR4,
VAR1,
VAR3);
input VAR6;
input VAR2;
input [31:0] VAR5;
input [31:0] VAR4;
output VAR1;
output VAR3;
endmodule | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/acme/prj/solution1/impl/ip/hdl/verilog/image_filter.v | 40,905 | module MODULE1 (
VAR108,
VAR278,
VAR181,
VAR135,
VAR215,
VAR90,
VAR120,
VAR235,
VAR180,
VAR41,
VAR45,
VAR259,
VAR211,
VAR92,
VAR197,
VAR146,
VAR222,
VAR199,
VAR204,
VAR241,
VAR9,
VAR107,
VAR86,
VAR144,
VAR104,
VAR119
);
parameter VAR109 = 32'b00000000000000000000000000000000;
parameter VAR251 = 4'b0000;
parameter VAR2 ... | gpl-3.0 |
alexforencich/verilog-axis | rtl/axis_fifo.v | 16,039 | module MODULE1 #
(
parameter VAR15 = 4096,
parameter VAR41 = 8,
parameter VAR35 = (VAR41>8),
parameter VAR27 = ((VAR41+7)/8),
parameter VAR2 = 1,
parameter VAR3 = 0,
parameter VAR18 = 8,
parameter VAR1 = 0,
parameter VAR19 = 8,
parameter VAR28 = 1,
parameter VAR36 = 1,
parameter VAR34 = 1,
parameter VAR8 = 0,
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.functional.v | 1,735 | module MODULE1 (
VAR6 ,
VAR12,
VAR5,
VAR14,
VAR2,
VAR15,
VAR10
);
output VAR6 ;
input VAR12;
input VAR5;
input VAR14;
input VAR2;
input VAR15;
input VAR10;
wire VAR8 ;
wire VAR4 ;
wire VAR3 ;
wire VAR13;
nand VAR7 (VAR8 , VAR5, VAR12 );
nand VAR1 (VAR4 , VAR2, VAR14 );
nand VAR9 (VAR3 , VAR10, VAR15 );
and VAR11 (VAR13... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/or3/sky130_fd_sc_hvl__or3.behavioral.pp.v | 1,810 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR1 ,
VAR11 ,
VAR5,
VAR3,
VAR6 ,
VAR9
);
output VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR11 ;
input VAR5;
input VAR3;
input VAR6 ;
input VAR9 ;
wire VAR12 ;
wire VAR13;
or VAR10 (VAR12 , VAR1, VAR7, VAR11 );
VAR8 VAR2 (VAR13, VAR12, VAR5, VAR3);
buf VAR14 (VAR4 , VAR13 );
endmodule | apache-2.0 |
cr88192/bgbtech_bjx1core | smalltst/compdec/ModFbTxtW.v | 7,027 | module MODULE1(VAR27, reset,
VAR20, VAR6, VAR29, VAR17, VAR22,
VAR21, VAR11,
VAR5, VAR12);
input VAR27;
input reset;
input[9:0] VAR20;
input[9:0] VAR6;
output[7:0] VAR29;
output[7:0] VAR17;
output[7:0] VAR22;
output[13:0] VAR21;
input[127:0] VAR11;
output[15:0] VAR5;
input[63:0] VAR12;
reg[9:0] VAR28;
reg[9:0] VAR3;
re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/xor2/sky130_fd_sc_lp__xor2.blackbox.v | 1,264 | module MODULE1 (
VAR5,
VAR6,
VAR4
);
output VAR5;
input VAR6;
input VAR4;
supply1 VAR3;
supply0 VAR7;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a31oi/sky130_fd_sc_ls__a31oi.symbol.v | 1,369 | module MODULE1 (
input VAR6,
input VAR8,
input VAR3,
input VAR1,
output VAR4
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or3/sky130_fd_sc_hdll__or3_1.v | 2,169 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR7 ,
VAR8 ,
VAR2,
VAR3,
VAR10 ,
VAR4
);
output VAR9 ;
input VAR6 ;
input VAR7 ;
input VAR8 ;
input VAR2;
input VAR3;
input VAR10 ;
input VAR4 ;
VAR1 VAR5 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODULE... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/decap/sky130_fd_sc_hd__decap_3.v | 1,881 | module MODULE2 (
VAR5,
VAR1,
VAR2 ,
VAR3
);
input VAR5;
input VAR1;
input VAR2 ;
input VAR3 ;
VAR4 VAR6 (
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR5;
supply0 VAR1;
supply1 VAR2 ;
supply0 VAR3 ;
VAR4 VAR6 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtn/sky130_fd_sc_ms__sdfrtn.pp.symbol.v | 1,513 | module MODULE1 (
input VAR9 ,
output VAR3 ,
input VAR8,
input VAR2 ,
input VAR10 ,
input VAR6 ,
input VAR5 ,
input VAR4 ,
input VAR1 ,
input VAR7
);
endmodule | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_xor.v | 1,548 | if (VAR19 && (VAR18==VAR8)) \
begin: VAR7 \
VAR20 VAR15 (.VAR6(VAR10),.VAR1(VAR9),.VAR14); \
end
module MODULE1 #(parameter VAR13(VAR18)
, parameter VAR19=0
)
(input [VAR18-1:0] VAR10
, input [VAR18-1:0] VAR9
, output [VAR18-1:0] VAR14
);
begin :VAR4
end
VAR17 assert(VAR19==0) else ("## %VAR12 VAR16 VAR2 VAR5 VAR11 VAR... | bsd-3-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_fifo_v1_00_a/hdl/verilog/address_gray.v | 2,920 | module MODULE1 (
input VAR20,
input VAR23,
input VAR4,
output reg VAR1,
output [VAR8-1:0] VAR16,
input VAR5,
input VAR22,
output reg VAR10,
input VAR14,
output reg VAR21,
output [VAR8-1:0] VAR26
);
parameter VAR8 = 4;
reg [VAR8:0] VAR26 = 'h00;
reg [VAR8:0] VAR17;
reg [VAR8:0] VAR18 = 'h00;
reg [VAR8:0] VAR16;
reg [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a22oi/sky130_fd_sc_lp__a22oi.behavioral.v | 1,641 | module MODULE1 (
VAR10 ,
VAR5,
VAR2,
VAR12,
VAR6
);
output VAR10 ;
input VAR5;
input VAR2;
input VAR12;
input VAR6;
supply1 VAR3;
supply0 VAR11;
supply1 VAR9 ;
supply0 VAR14 ;
wire VAR13 ;
wire VAR1 ;
wire VAR16;
nand VAR15 (VAR13 , VAR2, VAR5 );
nand VAR7 (VAR1 , VAR6, VAR12 );
and VAR4 (VAR16, VAR13, VAR1);
buf VAR8 ... | apache-2.0 |
minosys-jp/FPGA | Zybo/vgagraph/vgagraph/HDL/vgagraph_ctrl.v | 2,205 | module MODULE1 (
input VAR15,
input VAR1,
input VAR4,
input VAR5,
input VAR13,
input VAR3,
output VAR7,
output VAR9
);
localparam VAR12 = 640 * 480 / (2 * 16);
reg VAR16 = 1'b0;
reg VAR6 = 1'b0;
reg [8:0] VAR2 = 9'd0;
reg [22:0] VAR11 = 23'd0;
reg VAR10 = 1'b0;
reg VAR14 = 1'b0;
reg VAR8 = 1'd0;
assign VAR7 = VAR16 & (... | bsd-2-clause |
vkchettimada/aayudha | mojo/src/serial_rx.v | 2,455 | module MODULE1 #(
parameter VAR8 = 50
)(
input clk,
input rst,
input VAR13,
output [7:0] VAR1,
output VAR17
);
parameter VAR18 = VAR2(VAR8);
localparam VAR6 = 2;
localparam VAR16 = 2'd0,
VAR4 = 2'd1,
VAR19 = 2'd2,
VAR7 = 2'd3;
reg [VAR18-1:0] VAR9, VAR11;
reg [2:0] VAR12, VAR14;
reg [7:0] VAR20, VAR22;
reg VAR10, VAR5;... | mit |
qeedquan/fpga | de2-115/nios_lights/lights/synthesis/submodules/lights_jtag_uart_0.v | 16,629 | module MODULE5 (
clk,
VAR30,
VAR23,
VAR6,
VAR52,
VAR11,
VAR53
)
;
output VAR6;
output [ 7: 0] VAR52;
output VAR11;
output [ 5: 0] VAR53;
input clk;
input [ 7: 0] VAR30;
input VAR23;
wire VAR6;
wire [ 7: 0] VAR52;
wire VAR11;
wire [ 5: 0] VAR53;
always @(posedge clk)
begin
if (VAR23)
("%VAR45", VAR30);
end
assign VAR53 ... | mit |
ragulbalaji/Random-Cool-Things | FPGA/VGA/binarycounter.v | 1,230 | module MODULE1(
input wire VAR6,
input wire VAR4,
output wire [2:0]VAR7,
output wire VAR2,
output wire VAR5
);
reg VAR1;
reg [10:0] VAR10;
reg [10:0] VAR9;
reg VAR11;
reg VAR3;
reg VAR8; | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_105.v | 1,421 | module MODULE1 (
VAR1,
VAR2
);
input [31:0] VAR1;
output [31:0]
VAR2;
wire [31:0]
VAR5,
VAR4,
VAR7,
VAR6,
VAR11,
VAR9,
VAR8;
assign VAR5 = VAR1;
assign VAR7 = VAR4 - VAR5;
assign VAR4 = VAR5 << 2;
assign VAR11 = VAR6 - VAR7;
assign VAR6 = VAR7 << 4;
assign VAR8 = VAR9 - VAR5;
assign VAR9 = VAR11 << 7;
assign VAR2 = VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a.behavioral.pp.v | 2,188 | module MODULE1 (
VAR15 ,
VAR2 ,
VAR9 ,
VAR5 ,
VAR18 ,
VAR10 ,
VAR12,
VAR20,
VAR8 ,
VAR16
);
output VAR15 ;
input VAR2 ;
input VAR9 ;
input VAR5 ;
input VAR18 ;
input VAR10 ;
input VAR12;
input VAR20;
input VAR8 ;
input VAR16 ;
wire VAR13 ;
wire VAR17 ;
wire VAR3 ;
wire VAR7;
or VAR6 (VAR13 , VAR9, VAR2, VAR5 );
or VAR1... | apache-2.0 |
c4puter/bridge-hdl | modules/wb_conmax/wb_conmax_pri_dec.v | 4,127 | module MODULE1(valid, VAR2, VAR1);
parameter [1:0] VAR3 = 2'd0;
input valid;
input [1:0] VAR2;
output [3:0] VAR1;
wire [3:0] VAR1;
reg [3:0] VAR5;
reg [3:0] VAR4;
always @(valid or VAR2)
if(!valid) VAR4 = 4'b0001;
else
if(VAR2==2'h0) VAR4 = 4'b0001;
else
if(VAR2==2'h1) VAR4 = 4'b0010;
else
if(VAR2==2'h2) VAR4 = 4'b0100... | gpl-2.0 |
himansurathi/labCourseWork | VLSI lab/VLSI codes/sequencDetector.v | 1,709 | module MODULE1(
input in,
input reset,
input VAR7,
output reg out
);
reg [2:0] state;
parameter VAR3 = 3'b000, VAR5 = 3'b001, VAR6 = 3'b010, VAR4 = 3'b011, VAR1 = 3'b100, VAR2 = 3'b101;
always @(posedge VAR7)
begin
if (reset)
begin
state <= VAR3;
out <= 0 ;
end
else
case(state)
VAR3 : if (in) begin state <= VAR5; out <... | mit |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/clocking/mig_7series_v2_0_clk_ibuf.v | 4,796 | module MODULE1 #
(
parameter VAR13 = "VAR2",
parameter VAR20 = "VAR23"
)
(
input VAR5, input VAR17,
input VAR10,
output VAR7
);
wire VAR6 ;
generate
if (VAR13 == "VAR2") begin: VAR21
VAR11 #
(
.VAR22 (VAR20),
.VAR18 ("VAR12")
)
VAR19
(
.VAR9 (VAR5),
.VAR16 (VAR17),
.VAR4 (VAR6)
);
end else if (VAR13 == "VAR1") begin: V... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41a/sky130_fd_sc_ms__o41a.behavioral.v | 1,549 | module MODULE1 (
VAR9 ,
VAR14,
VAR11,
VAR15,
VAR1,
VAR4
);
output VAR9 ;
input VAR14;
input VAR11;
input VAR15;
input VAR1;
input VAR4;
supply1 VAR3;
supply0 VAR13;
supply1 VAR7 ;
supply0 VAR8 ;
wire VAR5 ;
wire VAR6;
or VAR12 (VAR5 , VAR1, VAR15, VAR11, VAR14 );
and VAR10 (VAR6, VAR5, VAR4 );
buf VAR2 (VAR9 , VAR6 );
... | apache-2.0 |
secworks/fltfpga | cpu/src/rtl/fltcpu.v | 11,170 | module MODULE1(
input wire clk,
input wire VAR14,
output wire VAR8,
output wire [3 : 0] VAR87,
output wire [31 : 0] VAR64,
input wire [31 : 0] VAR95,
output wire [31 : 0] VAR77
);
localparam VAR65 = 4'h0;
localparam VAR36 = 4'h1;
localparam VAR33 = 4'h2;
localparam VAR75 = 4'h3;
localparam VAR18 = 4'h4;
localparam VAR9... | bsd-2-clause |
nliu96/openHMC_Altera | src/rx_crc_compare.v | 19,806 | module MODULE1 #(
parameter VAR35 = 2,
parameter VAR73 = 4,
parameter VAR10 = 512
) (
input wire clk,
input wire VAR53,
input wire [VAR73-1:0] VAR23,
input wire [VAR73-1:0] VAR66,
input wire [VAR73-1:0] VAR48,
input wire [VAR10-1:0] VAR24,
input wire [(VAR73*4)-1:0] VAR49,
output wire [VAR10-1:0] VAR27,
output reg [VAR... | lgpl-3.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/hps_sdram_p0_acv_ldc.v | 3,413 | module MODULE1
(
VAR9,
VAR20,
VAR34,
VAR42,
VAR8,
VAR45,
VAR44,
VAR38,
VAR1
);
parameter VAR30 = "";
parameter VAR43 = 0;
parameter VAR17 = "false";
parameter VAR36 = "false";
input VAR9;
input VAR20;
input VAR34;
input [VAR30-1:0] VAR42;
output VAR8;
output VAR45;
output VAR44;
output VAR38;
output VAR1;
wire VAR12;
w... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_12.behavioral.v | 1,113 | module MODULE1( VAR3, VAR4 );
input VAR3;
output VAR4;
VAR2 VAR5(.VAR3(VAR3),.VAR4(VAR4));
VAR2 VAR1(.VAR3(VAR3),.VAR4(VAR4)); | apache-2.0 |
asicguy/gplgpu | hdl/hbi/hbi_mw_ctl.v | 29,414 | module MODULE1
(
input VAR69,
input VAR116,
input VAR72,
input VAR42,
input VAR68,
input [25:2] VAR53,
input [3:0] VAR17,
input VAR121,
input VAR33,
input VAR112,
input [24:0] VAR79,
input [24:0] VAR21,
input [3:0] VAR55,
input [3:0] VAR14,
input [25:12] VAR46,
input [25:12] VAR84,
input VAR139,
input VAR142,
input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o_0.v | 2,337 | module MODULE2 (
VAR3 ,
VAR10 ,
VAR6 ,
VAR8 ,
VAR1 ,
VAR9,
VAR5,
VAR4 ,
VAR2
);
output VAR3 ;
input VAR10 ;
input VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR9;
input VAR5;
input VAR4 ;
input VAR2 ;
VAR7 VAR11 (
.VAR3(VAR3),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/xilinx_com_hls_nco_1_0/hdl/verilog/nco_sine_lut_V.v | 1,225 | module MODULE1 (
VAR4, VAR3, VAR7, clk);
parameter VAR5 = 16;
parameter VAR1 = 12;
parameter VAR2 = 4096;
input[VAR1-1:0] VAR4;
input VAR3;
output reg[VAR5-1:0] VAR7;
input clk;
reg [VAR5-1:0] VAR6[VAR2-1:0];
begin
begin | mit |
Marcoslz22/Tercer_Proyecto | Contador_AD_Mes.v | 1,242 | module MODULE1(
input rst,
input [7:0]VAR5,
input [1:0] en,
input [7:0] VAR2,
input VAR3,
input clk,
output reg [(VAR6-1):0] VAR1
);
parameter VAR6 = 4;
parameter VAR4 = 12;
always @(posedge clk)
if (rst)
VAR1 <= 1;
else if (en == 2'd1 && VAR5 == 8'h7D)
begin
if (VAR2 == 8'h73 && VAR3)
begin
if (VAR1 == VAR4)
VAR1 <= 1... | mit |
Cognoscan/VerilogCogs | servo.v | 1,269 | module MODULE1
parameter VAR6 = 16, parameter VAR2 = 1 ) (
input VAR4, input rst, input [(VAR6*VAR2)-1:0] VAR1, output reg [VAR2-1:0] VAR8 );
wire [VAR6-1:0] VAR3[VAR2-1:0];
reg [19:0] counter;
integer VAR7;
genvar VAR5;
generate
begin
for (VAR5=0; VAR5<VAR2; VAR5=VAR5+1) begin
assign VAR3[VAR5] = VAR1[(VAR6*(VAR5+1)-1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlxbn/sky130_fd_sc_ls__dlxbn.behavioral.pp.v | 2,141 | module MODULE1 (
VAR13 ,
VAR15 ,
VAR16 ,
VAR9,
VAR3 ,
VAR14 ,
VAR10 ,
VAR11
);
output VAR13 ;
output VAR15 ;
input VAR16 ;
input VAR9;
input VAR3 ;
input VAR14 ;
input VAR10 ;
input VAR11 ;
wire VAR19 ;
wire VAR2 ;
wire VAR18;
wire VAR1 ;
reg VAR7 ;
wire VAR6 ;
wire 1 ;
not VAR12 (VAR19 , VAR18 );
VAR4 VAR5 (VAR2 , VAR... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/phy/phy_data_io.v | 17,003 | module MODULE1 #
(
parameter VAR22 = 100, parameter VAR54 = 2, parameter VAR5 = 3000, parameter VAR94 = 8, parameter VAR70 = 9, parameter VAR60 = 72, parameter VAR21 = 9, parameter VAR59 = "VAR45",
parameter VAR43 = 5, parameter VAR72 = "VAR71", parameter VAR30 = 300.0, parameter VAR6 = "VAR71", parameter VAR19 = "VAR6... | lgpl-3.0 |
devinacker/sd2snes | verilog/sd2snes_cx4/spi.v | 3,231 | module MODULE1(
input clk,
input VAR16,
input VAR1,
inout VAR25,
input VAR19,
output VAR27,
output VAR22,
output [7:0] VAR29,
output [7:0] VAR23,
output VAR9,
output VAR34,
input [7:0] VAR17,
output [31:0] VAR6,
output [2:0] VAR14
);
reg [7:0] VAR28;
reg [7:0] VAR5;
reg [2:0] VAR12;
reg [2:0] VAR7;
always @(posedge clk... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.v | 2,163 | module MODULE2 (
VAR6 ,
VAR1 ,
VAR8,
VAR7,
VAR4 ,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR8;
input VAR7;
input VAR4 ;
input VAR5 ;
VAR2 VAR3 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6,
VAR1
);
output VAR6;
input VAR1;
supply1 VAR8;
supply0 VAR7;... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerHdl_StandBy.v | 1,587 | module MODULE1
(
VAR4,
VAR5,
VAR3
);
output signed [19:0] VAR4; output signed [19:0] VAR5; output signed [19:0] VAR3;
wire signed [19:0] VAR1 [0:2];
assign VAR1[0] = 20'VAR2;
assign VAR1[1] = 20'VAR2;
assign VAR1[2] = 20'VAR2;
assign VAR4 = VAR1[0];
assign VAR5 = VAR1[1];
assign VAR3 = VAR1[2];
endmodule | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/daq3/common/daq3_spi.v | 3,829 | module MODULE1 (
VAR17,
VAR11,
VAR8,
VAR5,
VAR7,
VAR16);
input [ 2:0] VAR17;
input VAR11;
input VAR8;
output VAR5;
inout VAR7;
output VAR16;
reg [ 5:0] VAR4 = 'd0;
reg VAR9 = 'd0;
reg VAR3 = 'd0;
wire VAR2;
wire VAR14;
assign VAR2 = & VAR17;
assign VAR16 = ~VAR14;
assign VAR14 = VAR3 & ~VAR2;
always @(posedge VAR11 or ... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_lsu.v | 11,566 | module MODULE1(
clk,
VAR33, VAR41, VAR12, VAR47, VAR15, VAR1, VAR26,
VAR37, VAR44, VAR6, VAR42, VAR8,
VAR2, VAR46, VAR50, VAR25, VAR27, VAR28,
VAR23, VAR21, VAR9, VAR13, VAR17
);
parameter VAR39 = VAR32;
parameter VAR16 = VAR38;
input clk;
input [31:0] VAR33;
input [31:0] VAR41;
input [VAR34-1:0] VAR12;
input [VAR39-1:... | gpl-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_xcvr.v | 10,488 | module MODULE1 (
rst,
VAR45,
VAR59,
VAR31,
VAR7,
VAR32,
VAR53,
VAR57,
VAR21,
VAR63,
VAR58,
VAR18,
VAR5,
VAR10,
VAR56,
VAR17,
VAR43,
VAR44,
VAR48,
VAR60,
VAR12,
VAR16,
VAR2,
VAR40,
VAR50);
localparam VAR47 = 32'h00060162;
parameter VAR15 = 0;
parameter VAR62 = 0;
output rst;
input VAR45;
output VAR59;
input VAR31;
outpu... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor4/gf180mcu_fd_sc_mcu7t5v0__nor4_4.functional.pp.v | 1,404 | module MODULE1( VAR11, VAR5, VAR10, VAR9, VAR3, VAR4, VAR16 );
input VAR3, VAR9, VAR5, VAR11;
inout VAR4, VAR16;
output VAR10;
wire VAR2;
not VAR13( VAR2, VAR3 );
wire VAR1;
not VAR6( VAR1, VAR9 );
wire VAR8;
not VAR15( VAR8, VAR5 );
wire VAR12;
not VAR14( VAR12, VAR11 );
and VAR7( VAR10, VAR2, VAR1, VAR8, VAR12 );
end... | apache-2.0 |
titorgalaxy/Titor | rtl/verilog/util/Radix_Counter.v | 1,486 | module MODULE1(
VAR2, VAR4, VAR5,
reset,
clk
);
parameter VAR3 = 0;
input VAR2;
output VAR4;
output reg [VAR1-1:0] VAR5;
input reset;
input clk;
assign VAR4 = (VAR5 == VAR3-1) && VAR2;
always @(posedge clk) begin
if(reset) VAR5 <= 0;
end
else if(VAR2 && VAR4) VAR5 <= 0;
else if(VAR2) VAR5 <= VAR5+1;
else VAR5 <= VAR5;
... | gpl-3.0 |
fallen/milkymist-mmu | cores/minimac2/rtl/minimac2_memory.v | 3,621 | module MODULE1(
input VAR57,
input VAR25,
input VAR7,
input VAR29,
input [31:0] VAR22,
output [31:0] VAR16,
input [31:0] VAR8,
input [3:0] VAR28,
input VAR54,
input VAR15,
output reg VAR61,
input VAR27,
input [7:0] VAR37,
input [10:0] VAR47,
input VAR19,
input [7:0] VAR2,
input [10:0] VAR53,
input VAR40,
output [7:0] V... | lgpl-3.0 |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_ScratchRam_0_0/RAT_ScratchRam_0_0_stub.v | 1,353 | module MODULE1(VAR1, VAR2, VAR4, VAR3, VAR5)
;
input [9:0]VAR1;
output [9:0]VAR2;
input [7:0]VAR4;
input VAR3;
input VAR5;
endmodule | mit |
silent-observer/RCPU | CPU/source/Rintaro.v | 5,930 | module MODULE1 (
input wire VAR68,
input wire VAR48,
input wire VAR74,
input wire rst,
input wire[1:0] VAR65,
input wire[2:0] VAR70,
output wire[3:0] VAR6,
output wire[7:0] VAR11,
output wire[10:0] VAR39,
inout wire VAR57,
inout wire VAR67,
output wire VAR1,
input wire VAR41,
output wire VAR3,
output wire VAR42,
output... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfbbn/sky130_fd_sc_ls__sdfbbn.blackbox.v | 1,528 | module MODULE1 (
VAR10 ,
VAR12 ,
VAR3 ,
VAR2 ,
VAR9 ,
VAR1 ,
VAR8 ,
VAR6
);
output VAR10 ;
output VAR12 ;
input VAR3 ;
input VAR2 ;
input VAR9 ;
input VAR1 ;
input VAR8 ;
input VAR6;
supply1 VAR7;
supply0 VAR5;
supply1 VAR11 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.functional.pp.v | 1,792 | module MODULE1 (
VAR13 ,
VAR10 ,
VAR12 ,
VAR11,
VAR9,
VAR3 ,
VAR6
);
output VAR13 ;
input VAR10 ;
input VAR12 ;
input VAR11;
input VAR9;
input VAR3 ;
input VAR6 ;
wire VAR7 ;
wire VAR4;
nor VAR8 (VAR7 , VAR10, VAR12 );
VAR2 VAR5 (VAR4, VAR7, VAR11, VAR9);
buf VAR1 (VAR13 , VAR4 );
endmodule | apache-2.0 |
mosass/HexapodRobot | VIVADO/hexapod/hexapod.cache/ip/1b8b28a33d042401/design_1_processing_system7_0_0_stub.v | 5,652 | module MODULE1(VAR16, VAR76, VAR74, VAR66,
VAR59, VAR44, VAR56, VAR69, VAR12, VAR52, VAR26,
VAR45, VAR46, VAR70, VAR67,
VAR57, VAR65, VAR32, VAR1,
VAR19, VAR4, VAR38, VAR50, VAR10,
VAR33, VAR77, VAR24, VAR41,
VAR75, VAR58, VAR31, VAR14, VAR72,
VAR21, VAR42, VAR35, VAR73, VAR39,
VAR48, VAR40, VAR54, VAR8, VAR78,
VAR13, ... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_clsp_pllcnt.v | 12,630 | module MODULE1(
VAR34, VAR78, VAR40,
VAR12, VAR14, VAR55, VAR74,
VAR35, VAR25, VAR11
);
input VAR12;
input VAR14;
input VAR55;
input VAR74;
input VAR35;
input VAR25;
input VAR11;
output VAR34;
output VAR78;
output VAR40;
parameter VAR67 = 7'h7F; parameter VAR39 = 15'h0010; parameter VAR76 = 15'h7b00; parameter VAR36 = ... | gpl-2.0 |
niamster/hdl | m1/m1.v | 1,374 | module MODULE1(clk, VAR10, VAR1);
parameter VAR3=8;
input clk;
input VAR10;
output reg [VAR3-1:0] VAR1;
always @(posedge clk, negedge VAR10) begin
if (~VAR10)
VAR1 <= {VAR3{1'b0}};
end
else
VAR1 <= VAR1 + {{VAR3-1{1'b0}}, 1'b1};
end
endmodule
module MODULE2(VAR4, VAR10, VAR12, VAR1);
input VAR4;
input VAR10;
input VAR1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/einvp/sky130_fd_sc_hdll__einvp.pp.blackbox.v | 1,297 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR6 ,
VAR4,
VAR5,
VAR7 ,
VAR1
);
output VAR2 ;
input VAR3 ;
input VAR6 ;
input VAR4;
input VAR5;
input VAR7 ;
input VAR1 ;
endmodule | apache-2.0 |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_lbW.v | 1,187 | module MODULE1 (
VAR4, VAR1, VAR7, clk);
parameter VAR2 = 8;
parameter VAR6 = 8;
parameter VAR3 = 256;
input[VAR6-1:0] VAR4;
input VAR1;
output reg[VAR2-1:0] VAR7;
input clk;
reg [VAR2-1:0] VAR5[0:VAR3-1];
begin
begin | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/or3/gf180mcu_fd_sc_mcu7t5v0__or3_1.behavioral.pp.v | 1,311 | module MODULE1( VAR3, VAR1, VAR9, VAR8, VAR5, VAR4 );
input VAR3, VAR1, VAR9;
inout VAR5, VAR4;
output VAR8;
VAR6 VAR7(.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR4(VAR4));
VAR6 VAR2(.VAR3(VAR3),.VAR1(VAR1),.VAR9(VAR9),.VAR8(VAR8),.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/pcie_interface.v | 13,450 | module MODULE1
(
input clk,
input reset,
output reg VAR19,
output reg VAR59,
output reg VAR18,
output reg [31:0] VAR80,
output reg [9:0] VAR11,
output reg [31:0] VAR60,
output reg [3:0] VAR15,
input VAR46,
input [31:0] VAR24,
input VAR36,
input wire VAR43,
input wire VAR10,
input wire [31:0] VAR63,
input wire [31:0] VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nand3b/sky130_fd_sc_hdll__nand3b.pp.symbol.v | 1,321 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR6 ,
output VAR5 ,
input VAR3 ,
input VAR8,
input VAR4,
input VAR7
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor3/sky130_fd_sc_hvl__nor3.blackbox.v | 1,292 | module MODULE1 (
VAR6,
VAR8,
VAR5,
VAR3
);
output VAR6;
input VAR8;
input VAR5;
input VAR3;
supply1 VAR2;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/db/db_pu_edge.v | 24,083 | module MODULE1(
VAR7,
VAR12,
VAR3,VAR1,VAR2 ,VAR15 ,VAR17 ,VAR9 ,VAR8 ,VAR10 ,
VAR5,VAR16,VAR13,VAR6,VAR4,VAR11,VAR18,VAR14,
h1,h2,h3,h4,h5,h6,h7
);
input [20:0] VAR7 ;input [41:0] VAR12 ;
output [6:0] VAR3,VAR1,VAR2 ,VAR15 ,VAR17 ,VAR9 ,VAR8 ,VAR10 ;
output [6:0] VAR5,VAR16,VAR13,VAR6,VAR4,VAR11,VAR18,VAR14;
output [1... | gpl-3.0 |
ipburbank/Raster-Laser-Projector | src/Video_In/synthesis/submodules/altera_reset_synchronizer.v | 3,473 | module MODULE1
parameter VAR5 = 1,
parameter VAR3 = 2
)
(
input VAR1 ,
input clk,
output VAR6
);
reg [VAR3-1:0] VAR2;
reg VAR4;
generate if (VAR5) begin
always @(posedge clk or posedge VAR1) begin
if (VAR1) begin
VAR2 <= {VAR3{1'b1}};
VAR4 <= 1'b1;
end
else begin
VAR2[VAR3-2:0] <= VAR2[VAR3-1:1];
VAR2[VAR3-1] <= 0;
VAR... | gpl-3.0 |
hoangt/NOCulator | hring/hw/calf/sortnet.v | 5,072 | module MODULE2
(
input clk,
input VAR29 VAR25,
input VAR29 VAR39,
input VAR29 VAR55,
input VAR29 VAR56,
input VAR44 VAR48,
input VAR44 VAR11,
input VAR44 VAR35,
input VAR44 VAR9,
output VAR44 VAR34,
output VAR44 VAR8,
output VAR44 VAR18,
output VAR44 VAR6
);
wire VAR3 VAR30;
wire [15:0] rand;
MODULE4 MODULE3(.clk(clk),... | mit |
bgelb/digilite_zl | rtl/zl_sdp_ram.v | 2,200 | module MODULE1 #
(
parameter VAR63 = 0,
parameter VAR32 = 0,
parameter VAR47 = 0,
parameter VAR48 = 0
)
(
input VAR14,
input VAR62,
input [VAR32-1:0] VAR45,
input [VAR63-1:0] VAR53,
input VAR25,
input [VAR48-1:0] VAR54,
output [VAR47-1:0] VAR21
);
VAR58 #
(
.VAR64("VAR34"),
.VAR37("VAR11"),
.VAR5("VAR23"),
.VAR17("VAR2... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlrtp/sky130_fd_sc_hvl__dlrtp_1.v | 2,370 | module MODULE1 (
VAR8 ,
VAR5,
VAR1 ,
VAR3 ,
VAR9 ,
VAR7 ,
VAR6 ,
VAR2
);
output VAR8 ;
input VAR5;
input VAR1 ;
input VAR3 ;
input VAR9 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
VAR4 VAR10 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1... | apache-2.0 |
ellisgl/Driver-YL-3 | yl3_shiftregister.v | 10,284 | module MODULE1(
input VAR10,
input [15:0] VAR3,
input VAR13,
output VAR8,
output VAR2,
output VAR6,
output VAR5
);
reg [16:0] VAR14 = 0;
reg VAR2 = 0;
reg VAR6 = 0;
reg VAR8 = 1;
parameter VAR4 = 3;
parameter [VAR4-1:0] VAR12 = 6;
parameter [VAR4-1:0] VAR1 = 7;
wire VAR5;
assign VAR5 = VAR14[16];
reg [VAR4-1:0] VAR19 =... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb.behavioral.pp.v | 1,998 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR15 ,
VAR1 ,
VAR16 ,
VAR8,
VAR14,
VAR6 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR15 ;
input VAR1 ;
input VAR16 ;
input VAR8;
input VAR14;
input VAR6 ;
input VAR2 ;
wire VAR7 ;
wire VAR13 ;
wire VAR10;
nor VAR12 (VAR7 , VAR4, VAR15 );
and VAR9 (VAR13 , VAR7, VAR1, VAR16 );
VAR17 VAR3... | apache-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_021.v | 1,523 | module MODULE1 (
VAR10,
VAR1
);
input [31:0] VAR10;
output [31:0]
VAR1;
wire [31:0]
VAR3,
VAR14,
VAR5,
VAR6,
VAR13,
VAR7,
VAR2,
VAR9,
VAR4;
assign VAR3 = VAR10;
assign VAR4 = VAR9 - VAR2;
assign VAR14 = VAR3 << 4;
assign VAR9 = VAR3 << 14;
assign VAR5 = VAR3 + VAR14;
assign VAR7 = VAR13 << 3;
assign VAR2 = VAR13 + VAR7... | mit |
cr88192/bgbtech_bjx1core | bjx1core32/MemTile.v | 2,873 | module MODULE1(
clk,
VAR11,
VAR8,
VAR14,
VAR5,
VAR13,
VAR15
);
input clk; input VAR11; input VAR8; input[2:0] VAR14;
input[47:0] VAR5;
input[63:0] VAR15;
output[63:0] VAR13;
reg[11:0] VAR4;
reg[31:0] VAR16[4096];
reg[63:0] VAR3;
reg[63:0] VAR1;
reg[63:0] VAR22;
reg[63:0] VAR6;
reg[63:0] VAR10;
reg[63:0] VAR18;
reg[4:0]... | mit |
sstallion/apple-idun | cpld/fifo_mux.v | 3,244 | module MODULE1(input reset,
input VAR17,
input clk,
input VAR14,
output reg VAR10, VAR13,
input VAR8, VAR12,
output reg [6:0] VAR18,
input [6:0] VAR22,
output VAR15,
input VAR5, VAR23,
output reg VAR6, VAR20,
inout [7:0] VAR11);
localparam VAR16 = 3'b000;
localparam VAR21 = 3'b001;
localparam VAR3 = 3'b010;
localparam ... | bsd-2-clause |
sh-chris110/chris | FPGA/HPS.bak/Qsys/hps_design/synthesis/submodules/hps_design_hps_0_hps_io.v | 11,724 | module MODULE1 (
output wire [14:0] VAR7, output wire [2:0] VAR29, output wire VAR37, output wire VAR52, output wire VAR14, output wire VAR58, output wire VAR5, output wire VAR56, output wire VAR24, output wire VAR49, inout wire [31:0] VAR33, inout wire [3:0] VAR53, inout wire [3:0] VAR26, output wire VAR8, output wire... | gpl-2.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/acc_vadd/solution1/impl/ip/hdl/verilog/acc_vadd.v | 4,313 | module MODULE1 (
VAR19,
VAR24,
VAR17,
VAR6,
VAR3,
VAR13,
VAR20,
VAR10,
VAR18,
VAR12,
VAR11
);
parameter VAR14 = 1'b1;
parameter VAR5 = 1'b0;
parameter VAR21 = 1'b0;
parameter VAR8 = 1'b1;
input VAR19;
input VAR24;
input [31:0] VAR17;
input VAR6;
output VAR3;
input [31:0] VAR13;
input VAR20;
output VAR10;
output [31:0] ... | bsd-3-clause |
Elphel/x353 | control/dma_fifo353.v | 7,533 | module MODULE1 ( clk, VAR14, VAR11,
VAR9, VAR37, VAR24, VAR1, VAR26, VAR59, VAR4, VAR10, VAR53
,VAR17,
VAR40
);
input clk;
input VAR14;
input [2:0] VAR11; output VAR9;
input VAR37;
input VAR24;
input VAR1;
output [31:0] VAR26;
input VAR59;
input [15:0] VAR4;
output VAR10;
output VAR53;
output [7:0] VAR17;
output [7:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ha/sky130_fd_sc_lp__ha_2.v | 2,184 | module MODULE1 (
VAR5,
VAR8 ,
VAR7 ,
VAR3 ,
VAR1,
VAR2,
VAR9 ,
VAR6
);
output VAR5;
output VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR1;
input VAR2;
input VAR9 ;
input VAR6 ;
VAR4 VAR10 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
... | apache-2.0 |
545/Atari7800 | maria/maria.srcs/sources_1/ip/clock_divider/clock_divider.v | 4,245 | module MODULE1
(
input VAR3,
output VAR5,
output VAR6,
output VAR1,
input reset,
output VAR4
);
VAR7 VAR2
(
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.reset(reset),
.VAR4(VAR4)
);
endmodule | gpl-2.0 |
elegabriel/myzju | junior1/CA/LAB/lab5/code/ID_EX.v | 1,599 | module MODULE1(
clk,rst,
VAR5, VAR9, VAR4, VAR13, VAR3, VAR10, VAR7, VAR14,VAR8,
VAR12, VAR2, VAR15, VAR1, VAR18, VAR17, VAR16, VAR6,VAR11
);
input clk,rst;
input wire [31:0] VAR5,VAR9,VAR13,VAR8;
input wire [4:0] VAR4,VAR3;
input wire VAR10,VAR7,VAR14;
output reg [31:0] VAR12,VAR2,VAR1,VAR11;
output reg [4:0] VAR15,VA... | gpl-2.0 |
PeterMagnusson/modexp | src/rtl/blockmem2r1wptr.v | 4,706 | module MODULE1(
input wire clk,
input wire VAR8,
input wire [07 : 0] VAR7,
output wire [31 : 0] VAR10,
output wire [31 : 0] VAR14,
input wire rst,
input wire VAR12,
input wire wr,
input wire [31 : 0] VAR3
);
reg [31 : 0] VAR9 [0 : 255];
reg [31 : 0] VAR4;
reg [31 : 0] VAR11;
reg [7 : 0] VAR2;
reg [7 : 0] VAR5;
reg VAR1... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2/sky130_fd_sc_lp__and2.blackbox.v | 1,233 | module MODULE1 (
VAR4,
VAR1,
VAR2
);
output VAR4;
input VAR1;
input VAR2;
supply1 VAR6;
supply0 VAR5;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axi_crossbar_v2_1/hdl/verilog/axi_crossbar_v2_1_splitter.v | 4,368 | module MODULE1 #
(
parameter integer VAR10 = 2 )
(
input wire VAR5,
input wire VAR1,
input wire VAR8,
output wire VAR3,
output wire [VAR10-1:0] VAR6,
input wire [VAR10-1:0] VAR7
);
reg [VAR10-1:0] VAR4;
wire VAR9;
wire [VAR10-1:0] VAR2;
always @(posedge VAR5) begin
if (VAR1 | VAR9) VAR4 <= {VAR10{1'b0}};
end
else VAR4 ... | mit |
AmeerAbdelhadi/Switched-Multiported-RAM | mpram_xor.v | 9,142 | module MODULE1
localparam VAR38 = VAR27(VAR32);
reg [VAR38*VAR4-1:0] VAR19; reg [VAR3*VAR4-1:0] VAR15; reg [ VAR4-1:0] VAR22 ; always @(posedge clk) begin
VAR19 <= VAR9;
VAR15 <= VAR30;
VAR22 <= VAR37 ;
end
reg [VAR38 -1:0] VAR25 [VAR4-1:0] ; reg [VAR38 -1:0] VAR23 [VAR4-1:0] ; reg [VAR3 -1:0] VAR5 [VAR4-1:0] ; reg [VA... | bsd-3-clause |
CospanDesign/vivado-ip-cores | ip/axi_on_screen_display/bram.v | 2,369 | module MODULE1 #(
parameter VAR11 = 32,
parameter VAR5 = 10,
parameter VAR1 = "VAR2",
parameter VAR3 = -1
)(
input clk,
input rst,
input en,
input VAR9,
input [(VAR5 - 1):0] VAR8,
input [(VAR5 - 1):0] VAR4,
input [(VAR11 - 1):0] VAR7,
output reg [(VAR11 - 1):0] VAR10
);
reg [(VAR11 - 1):0] VAR12 [0:((1 << VAR5) - 1)]; ... | mit |
ptracton/wb_soc_template | rtl/ZIP/rtl/idecode.v | 17,912 | module MODULE1(VAR34, VAR23, VAR56, VAR21,
VAR101, VAR62, VAR10, VAR27,
VAR97,
VAR36,
VAR76, VAR51,
VAR64, VAR81,
VAR73, VAR57, VAR75, VAR45, VAR74,
VAR41, VAR86,
VAR72, VAR49, VAR63, VAR80, VAR53, VAR25, VAR88,
VAR12, VAR99, VAR1,
VAR61, VAR55, VAR30, VAR38,
VAR83,
VAR44, VAR60
);
parameter VAR46=24, VAR96=1, VAR40=1,... | mit |
BoulaZa5/32bit-alu | project.v | 2,591 | module MODULE1 (input VAR16, input [4:0] VAR14, input [4:0] VAR7, input [4:0] VAR11, input clk, input [3:0] VAR6, input [4:0] VAR4, output signed [31:0] VAR15, input VAR2, input [31:0] VAR12);
wire [31:0] VAR1;
wire signed [31:0] VAR3;
wire signed [31:0] VAR5;
VAR10 VAR9 (VAR16, VAR14, VAR1, VAR7, VAR3, VAR11, VAR5, cl... | unlicense |
Digilent/vivado-library | ip/Pmods/PmodJSTK2_v1_0/src/PmodJSTK2.v | 13,327 | module MODULE1
(VAR27,
VAR3,
VAR197,
VAR68,
VAR105,
VAR45,
VAR131,
VAR31,
VAR99,
VAR152,
VAR170,
VAR34,
VAR129,
VAR70,
VAR15,
VAR194,
VAR43,
VAR40,
VAR84,
VAR46,
VAR77,
VAR159,
VAR140,
VAR11,
VAR132,
VAR36,
VAR53,
VAR145,
VAR52,
VAR151,
VAR153,
VAR4,
VAR178,
VAR166,
VAR38,
VAR171,
VAR192,
VAR176,
VAR179,
VAR155,
VAR10,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.behavioral.v | 2,922 | module MODULE1 (
VAR5 ,
VAR22 ,
VAR25 ,
VAR15 ,
VAR31 ,
VAR7 ,
VAR26
);
output VAR5 ;
output VAR22 ;
input VAR25 ;
input VAR15 ;
input VAR31 ;
input VAR7 ;
input VAR26;
supply1 VAR18;
supply0 VAR23;
supply1 VAR1 ;
supply0 VAR27 ;
wire VAR19 ;
wire VAR29 ;
wire VAR16 ;
reg VAR2 ;
wire VAR9 ;
wire VAR14 ;
wire VAR4 ;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdfsbp/sky130_fd_sc_hd__sdfsbp.behavioral.v | 2,922 | module MODULE1 (
VAR6 ,
VAR18 ,
VAR29 ,
VAR30 ,
VAR22 ,
VAR17 ,
VAR33
);
output VAR6 ;
output VAR18 ;
input VAR29 ;
input VAR30 ;
input VAR22 ;
input VAR17 ;
input VAR33;
supply1 VAR14;
supply0 VAR21;
supply1 VAR19 ;
supply0 VAR12 ;
wire VAR32 ;
wire VAR13 ;
wire VAR26 ;
reg VAR1 ;
wire VAR23 ;
wire VAR9 ;
wire VAR11 ;... | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/picouser/picouser.v | 6,032 | module MODULE1
(
input wire VAR7,
input wire VAR30,
input wire VAR6,
input wire VAR16,
input wire [3:0] VAR37,
input wire VAR8,
input wire VAR12,
input wire VAR41,
input wire VAR22,
input wire clk,
output wire [3:0] VAR42,
output wire [3:0] VAR5,
output reg [3:0] VAR28
);
VAR34 #(.VAR33("VAR23"))
VAR13 (.async(VAR37[3]... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_av_config_auto_init_ltm.v | 6,602 | module MODULE1 (
VAR1,
VAR2
);
input [ 4: 0] VAR1;
output [23: 0] VAR2;
reg [23: 0] VAR3;
assign VAR2 = {VAR3[13: 8], 2'h0,
VAR3[ 7: 0]};
always @(*)
begin
case (VAR1)
0 : VAR3 <= {6'h02, 8'h07};
1 : VAR3 <= {6'h03, 8'hDF};
2 : VAR3 <= {6'h04, 8'h17};
3 : VAR3 <= {6'h11, 8'h00};
4 : VAR3 <= {6'h12, 8'h5B};
5 : VAR3 <= ... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/col_mach.v | 17,542 | module MODULE1 #
(
parameter VAR31 = 100,
parameter VAR38 = 3,
parameter VAR108 = "8",
parameter VAR74 = 12,
parameter VAR130 = 4,
parameter VAR73 = 8,
parameter VAR61 = 1,
parameter VAR95 = 0,
parameter VAR105 = 8,
parameter VAR69 = "VAR39",
parameter VAR6 = "VAR99",
parameter VAR32 = "VAR99",
parameter VAR57 = 31,
pa... | lgpl-3.0 |
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