repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
trivoldus28/pulsarch-verilog | design/sys/iop/srams/rtl/bw_r_idct.v | 12,181 | module MODULE1(VAR36, VAR14, VAR5, VAR11, VAR4, VAR31, VAR21,
VAR35, VAR26, VAR16, VAR9, VAR10, VAR23, VAR2,
VAR12, VAR6, VAR18, VAR15, VAR3, VAR20,
VAR28, VAR29);
input VAR31;
input VAR21;
input VAR35;
input VAR26;
input VAR16;
input VAR9;
input [6:0] VAR10;
input [6:0] VAR23;
input VAR2;
input [3:0] VAR12;
input VAR6... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/dspengine_16to8.v | 6,153 | module MODULE1
parameter VAR19 = 9)
(input clk, input reset, input VAR78,
input VAR60, input [7:0] VAR17, input [31:0] VAR5,
output VAR39,
output VAR38,
input VAR51,
output VAR28,
output VAR45,
output [VAR19-1:0] VAR30,
input [VAR19-1:0] VAR82,
output [35:0] VAR69,
input [35:0] VAR80
);
wire VAR64;
VAR52 #(.VAR26(VAR11... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/ram_2clk_1w_1r.v | 3,322 | module MODULE1
parameter VAR6 = 32,
parameter VAR10 = 1024
)
(
input VAR4,
input VAR12,
input VAR13,
input [VAR1(VAR10)-1:0] VAR9,
input [VAR1(VAR10)-1:0] VAR5,
input [VAR6-1:0] VAR2,
output [VAR6-1:0] VAR8
);
localparam VAR11 = VAR1(VAR10);
reg [VAR6-1:0] VAR7 [VAR10-1:0];
reg [VAR6-1:0] VAR3;
assign VAR8 = VAR3;
alwa... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111oi/sky130_fd_sc_hs__a2111oi.behavioral.v | 1,976 | module MODULE1 (
VAR11 ,
VAR2 ,
VAR15 ,
VAR8 ,
VAR1 ,
VAR6 ,
VAR14,
VAR9
);
output VAR11 ;
input VAR2 ;
input VAR15 ;
input VAR8 ;
input VAR1 ;
input VAR6 ;
input VAR14;
input VAR9;
wire VAR1 VAR7 ;
wire VAR16 ;
wire VAR13;
and VAR3 (VAR7 , VAR2, VAR15 );
nor VAR4 (VAR16 , VAR8, VAR1, VAR6, VAR7 );
VAR12 VAR5 (VAR13, V... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_stub.v | 5,572 | module MODULE1(VAR44, VAR49, VAR75, VAR67,
VAR29, VAR26, VAR71, VAR54, VAR34, VAR72,
VAR16, VAR63, VAR57, VAR66,
VAR5, VAR43, VAR42, VAR20, VAR55,
VAR64, VAR31, VAR4, VAR15, VAR12,
VAR59, VAR17, VAR3, VAR25,
VAR6, VAR73, VAR2, VAR14, VAR27,
VAR70, VAR74, VAR24, VAR9, VAR19,
VAR7, VAR65, VAR51, VAR21, VAR53,
VAR10, VAR1... | mit |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_nios2_gen2_0_cpu_debug_slave_sysclk.v | 6,284 | module MODULE1 (
clk,
VAR18,
VAR11,
VAR15,
VAR16,
VAR13,
VAR7,
VAR12,
VAR21,
VAR27,
VAR6,
VAR9,
VAR29,
VAR26,
VAR5,
VAR28
)
;
output [ 37: 0] VAR13;
output VAR7;
output VAR12;
output VAR21;
output VAR27;
output VAR6;
output VAR9;
output VAR29;
output VAR26;
output VAR5;
output VAR28;
input clk;
input [ 1: 0] VAR18;
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41oi/sky130_fd_sc_lp__a41oi.functional.pp.v | 2,070 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR15 ,
VAR18 ,
VAR2 ,
VAR13 ,
VAR11,
VAR5,
VAR1 ,
VAR16
);
output VAR8 ;
input VAR9 ;
input VAR15 ;
input VAR18 ;
input VAR2 ;
input VAR13 ;
input VAR11;
input VAR5;
input VAR1 ;
input VAR16 ;
wire VAR14 ;
wire VAR17 ;
wire VAR7;
and VAR10 (VAR14 , VAR9, VAR15, VAR18, VAR2 );
nor VAR12 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbp/sky130_fd_sc_ls__dlrbp.pp.symbol.v | 1,462 | module MODULE1 (
input VAR4 ,
output VAR2 ,
output VAR1 ,
input VAR6,
input VAR3 ,
input VAR5 ,
input VAR7 ,
input VAR8 ,
input VAR9
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlymetal6s2s/sky130_fd_sc_hd__dlymetal6s2s.blackbox.v | 1,321 | module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR3;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a211oi/sky130_fd_sc_ms__a211oi.symbol.v | 1,375 | module MODULE1 (
input VAR1,
input VAR7,
input VAR3,
input VAR9,
output VAR4
);
supply1 VAR2;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
merckhung/zet | cores/zet/rtl/zet_alu.v | 3,832 | module MODULE1 (
input [31:0] VAR11,
input [15:0] VAR45,
output [31:0] out,
input [ 2:0] VAR19,
input [ 2:0] VAR10,
input [15:0] VAR30,
output [ 8:0] VAR54,
input VAR1,
input [15:0] VAR12,
input [15:0] VAR51,
input clk,
output VAR18
);
wire [15:0] VAR33, VAR59, VAR32;
wire [15:0] VAR43;
wire [8:0] VAR3;
wire [19:0] VAR... | gpl-3.0 |
oddball/genMem | rtl/onePortMem.v | 2,848 | module MODULE1(VAR8,
VAR2,
address,
clk,
VAR7,
VAR3);
parameter VAR4 = 32;
parameter VAR5 = 8;
parameter VAR6 = 0;
localparam VAR9 =VAR1(VAR4);
output [VAR5-1:0] VAR8;
input VAR2;
input [VAR9-1:0] address;
input clk;
input VAR7;
input [VAR5-1:0] VAR3;
generate
if((VAR4==0)&&(VAR5==0))
begin
begin
begin
begin
begin
begi... | lgpl-3.0 |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/nfa_accept_samples_generic_hw.v | 45,177 | module MODULE1 (
VAR109,
VAR207,
VAR185,
VAR69,
VAR164,
VAR64,
VAR114,
VAR152,
VAR252,
VAR97,
VAR49,
VAR115,
VAR111,
VAR229,
VAR241,
VAR36,
VAR228,
VAR146,
VAR216,
VAR174,
VAR221,
VAR47,
VAR83,
VAR247,
VAR157,
VAR90,
VAR183,
VAR37,
VAR31,
VAR100,
VAR63,
VAR110,
VAR215,
VAR89,
VAR8,
VAR43,
VAR165,
VAR220,
VAR208,
VAR12,... | lgpl-3.0 |
cathalmccabe/PYNQ | boards/ip/interface_switch_1.1/interface_switch.v | 1,875 | module MODULE1 #(parameter VAR22 = 20)
(
input [2*VAR22-1:0] sel,
input [VAR22-1:0] VAR6,
input [VAR22-1:0] VAR9,
output [VAR22-1:0] VAR17,
input [VAR22-1:0] VAR13,
input [VAR22-1:0] VAR2,
input [VAR22-1:0] VAR8,
input [VAR22-1:0] VAR16,
output [VAR22-1:0] VAR7,
output [VAR22-1:0] VAR19,
output [VAR22-1:0] VAR18,
input... | bsd-3-clause |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_mult_mac.v | 15,794 | module MODULE1(
clk, rst,
VAR62, VAR15, VAR7, VAR37, VAR63, VAR2, VAR51,
VAR16, VAR12,
VAR25, VAR56,
VAR9, VAR11, VAR48, VAR60, VAR6
);
parameter VAR55 = VAR52;
input clk;
input rst;
input VAR62;
input VAR15;
input VAR7;
input [VAR55-1:0] VAR37;
input [VAR55-1:0] VAR63;
input [VAR35-1:0] VAR2;
input [VAR43-1:0] VAR51;
... | mit |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_phy_tempmon.v | 25,558 | module MODULE1 #
(
parameter VAR20 = 100, parameter VAR48 = 1465, parameter VAR22 = 1,
parameter VAR124 = 12'h8ac,
parameter VAR47 = 12'hca4
)
(
input clk, input rst, input VAR14, input VAR115, input [11:0] VAR19, output VAR120, output VAR64, output VAR13 );
localparam VAR84 = (VAR22 * 4096) / 504;
localparam VAR88 = (... | mit |
vpereira/golden_unicorn | bin/fpga/ztex_ufm1_15d4.v | 4,150 | module MODULE1 (VAR55, reset, VAR60, VAR28, VAR45, VAR47, VAR18, VAR33, VAR46, VAR2, read, write);
input VAR55, reset, VAR60, VAR28, VAR45, VAR47, VAR18, VAR33, VAR46, VAR2;
input [7:0] read;
output [7:0] write;
reg [3:0] VAR70, VAR59;
reg VAR51, VAR35, VAR17;
reg VAR74, VAR66, VAR30;
reg [4:0] VAR10;
reg [351:0] VAR15... | gpl-3.0 |
JY-Kim/CA2016 | Sources/ALU_1bit.v | 1,707 | module MODULE1
(
input VAR15,
input VAR4,
input VAR13,
input VAR2,
input VAR5,
input [1:0] VAR7,
output wire VAR14,
output wire VAR12
);
reg VAR8;
reg VAR9;
wire VAR18;
wire VAR1;
wire VAR22;
VAR10 VAR19 (
.VAR21 ( VAR15 ),
.VAR17 ( VAR8 ),
.VAR3 ( VAR13 ),
.VAR20 ( VAR18 ),
.VAR11 ( VAR12 )
);
always @ ( VAR2 or VAR4 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkinv/sky130_fd_sc_ms__clkinv_8.v | 2,036 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR7,
VAR4,
VAR3 ,
VAR5
);
output VAR1 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR3 ;
input VAR5 ;
VAR6 VAR8 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1,
VAR2
);
output VAR1;
input VAR2;
supply1 VAR7;
supply0 VAR4;... | apache-2.0 |
alexforencich/xfcp | lib/eth/example/HXT100G/fpga_cxpt16/rtl/fpga_core.v | 15,813 | module MODULE1
(
input wire clk,
input wire rst,
input wire [1:0] VAR121,
input wire [3:0] VAR62,
output wire [3:0] VAR199,
output wire VAR8,
input wire VAR154,
output wire VAR152,
output wire VAR167,
input wire VAR116,
output wire VAR5,
input wire VAR98,
output wire VAR66,
input wire VAR41,
output wire VAR118,
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/edfxbp/sky130_fd_sc_hd__edfxbp.symbol.v | 1,448 | module MODULE1 (
input VAR5 ,
output VAR8 ,
output VAR1,
input VAR4 ,
input VAR2
);
supply1 VAR9;
supply0 VAR3;
supply1 VAR6 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
pradeep9676/pradeep_9676 | BM_dut.v | 1,087 | module MODULE1( clk, reset,VAR8,VAR12,VAR7,VAR4
);
input [47:0] VAR8;
input [15:0] VAR12;
input clk,reset;
output reg signed [15:0] VAR7,VAR4;
wire signed [30:0]VAR1;
wire signed [16:0] VAR5;
wire signed [15:0] VAR11;
wire signed [15:0] VAR2;
VAR14 VAR3( .VAR8(VAR8),.VAR1(VAR1));
VAR6 VAR9( .VAR1(VAR1) , .VAR5(VAR5));
... | mit |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_alu.v | 12,978 | module MODULE1(
VAR7, VAR33, VAR8, VAR36,
VAR18, VAR27, VAR20,
VAR3, VAR31,
VAR29, VAR26, VAR21,
VAR34, VAR28, VAR38, flag
);
parameter VAR24 = VAR35;
input [VAR24-1:0] VAR7;
input [VAR24-1:0] VAR33;
input [VAR24-1:0] VAR8;
input VAR36;
input [VAR12-1:0] VAR18;
input [VAR4-1:0] VAR27;
input [VAR14-1:0] VAR20;
input [4:... | apache-2.0 |
sudov/options-accel | final_design/verilog/dut.v | 7,992 | module MODULE1 (
VAR1,
VAR38,
VAR54,
VAR50,
VAR30,
VAR11,
VAR27,
VAR47
);
input VAR1;
input VAR38;
input [31:0] VAR54;
input VAR50;
output VAR30;
output [31:0] VAR11;
input VAR27;
output VAR47;
reg VAR30;
reg[31:0] VAR11;
reg VAR47;
reg [31:0] VAR2;
reg [3:0] VAR19 = 4'b0000;
reg [31:0] VAR20;
reg [31:0] VAR14;
wire [6... | apache-2.0 |
golfit/QcmMasterController | QcmMasterControllerMain.v | 7,133 | module MODULE1(clk, VAR9, VAR10, VAR11, VAR5, VAR4, VAR2, VAR7, VAR1, VAR13, VAR8);
input clk, VAR9; output wire [6:0] VAR10, VAR11; output VAR5, VAR4; output VAR2; output VAR7; output VAR1; output VAR13; output VAR8;
wire [13:0] VAR6; wire [6:0] VAR3; wire [6:0] VAR14;
reg [4:0] VAR12; | mit |
Digilent/vivado-library | ip/hls_saturation_enhance_1_0/hdl/verilog/Loop_loop_height_jbC.v | 1,187 | module MODULE1 (
VAR1, VAR4, VAR7, clk);
parameter VAR6 = 8;
parameter VAR3 = 8;
parameter VAR2 = 256;
input[VAR3-1:0] VAR1;
input VAR4;
output reg[VAR6-1:0] VAR7;
input clk;
reg [VAR6-1:0] VAR5[0:VAR2-1];
begin
begin | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv3sd3/sky130_fd_sc_hs__clkdlyinv3sd3.pp.blackbox.v | 1,291 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR3,
VAR2
);
output VAR1 ;
input VAR4 ;
input VAR3;
input VAR2;
endmodule | apache-2.0 |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_CKINVDC_LVT_SS_210930.v | 11,786 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
not (VAR1, VAR2); | bsd-3-clause |
rurume/openrisc_vision_hardware | ISE/uart_top.v | 11,851 | module MODULE1 (
VAR46, VAR16, VAR12,
VAR49, VAR51, VAR4, VAR50, VAR38, VAR24, VAR47, VAR13, VAR8,
VAR15,
VAR2, VAR18,
VAR44, VAR32, VAR11, VAR31, VAR52, VAR43
, VAR26
);
parameter VAR17 = VAR34;
parameter VAR10 = VAR25;
output [7:0] VAR46;
assign VAR46 = VAR9;
output VAR16;
input VAR12;
input VAR49;
input [VAR10-1:0] ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2.pp.symbol.v | 1,263 | module MODULE1 (
input VAR2 ,
input VAR3 ,
output VAR7 ,
input VAR1 ,
input VAR6,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/vfabric_udiv.v | 3,078 | module MODULE1(VAR7, VAR38,
VAR29, VAR40, VAR15,
VAR36, VAR12, VAR31,
VAR26, VAR13, VAR6,
VAR30, VAR16, VAR25);
parameter VAR21 = 32;
parameter VAR4 = 32;
parameter VAR8 = 64;
input VAR7, VAR38;
input [VAR21-1:0] VAR29;
input [VAR21-1:0] VAR36;
input VAR40, VAR12;
output VAR15, VAR31;
output [VAR21-1:0] VAR26, VAR30;
o... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/add_rm_hdr/add_hdr.v | 5,876 | module MODULE1
parameter VAR46 = 64,
parameter VAR27=VAR46/8,
parameter VAR29 = 'hff,
parameter VAR30 = 0
)
(
VAR19,
VAR35,
VAR44,
VAR32,
VAR20,
VAR24,
VAR17,
VAR13,
reset,
clk
);
input [VAR46-1:0] VAR19;
input [VAR27-1:0] VAR35;
input VAR44;
output reg VAR32;
output reg [VAR46-1:0] VAR20;
output reg [VAR27-1:0] VAR24;... | mit |
tmolteno/TART | hardware/FPGA/tart_spi/bench/xilinx/IOBUF.v | 1,548 | module MODULE1
parameter VAR2 = "VAR5",
parameter VAR7 = "12")
(
input VAR3,
input VAR6,
output VAR4,
inout VAR8
);
assign VAR8 = VAR3 ? 1'VAR1 : VAR6;
assign VAR4 = VAR8;
endmodule | lgpl-3.0 |
AfterRace/SoC_Project | vivado/project/project.srcs/sources_1/bd/week1/ip/week1_auto_pc_0/synth/week1_auto_pc_0.v | 13,132 | module MODULE1 (
VAR17,
VAR35,
VAR9,
VAR72,
VAR19,
VAR74,
VAR36,
VAR18,
VAR60,
VAR90,
VAR69,
VAR52,
VAR102,
VAR67,
VAR103,
VAR44,
VAR93,
VAR51,
VAR101,
VAR7,
VAR5,
VAR79,
VAR50,
VAR49,
VAR20,
VAR114,
VAR8,
VAR100,
VAR86,
VAR104,
VAR29,
VAR110,
VAR77,
VAR1,
VAR66,
VAR4,
VAR33,
VAR11,
VAR65,
VAR53,
VAR78,
VAR26,
VAR92,
V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2.functional.v | 1,254 | module MODULE1 (
VAR4,
VAR3,
VAR5
);
output VAR4;
input VAR3;
input VAR5;
wire VAR6;
nor VAR2 (VAR6, VAR3, VAR5 );
buf VAR1 (VAR4 , VAR6 );
endmodule | apache-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_sb.v | 8,643 | module MODULE1(
clk, rst,
VAR30, VAR37, VAR13, VAR25, VAR26, VAR28, VAR18,
VAR14, VAR40, VAR4,
VAR21, VAR38, VAR9, VAR32, VAR19, VAR2, VAR34,
VAR8, VAR5, VAR39
);
parameter VAR23 = VAR1;
parameter VAR36 = VAR1;
input clk; input rst;
input [VAR23-1:0] VAR30; input [VAR36-1:0] VAR37; input VAR13; input VAR25; input VAR26... | gpl-2.0 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/versatile_fifo_async_cmp.v | 1,997 | module MODULE1 ( VAR17, VAR5, VAR3, VAR18, VAR16, VAR8, rst );
parameter VAR2 = 4;
parameter VAR19 = VAR2-1;
parameter VAR12 = 2'b00;
parameter VAR1 = 2'b01;
parameter VAR7 = 2'b11;
parameter VAR20 = 2'b10;
parameter VAR14 = 1'b0;
parameter VAR13 = 1'b1;
input [VAR19:0] VAR17, VAR5;
output reg VAR3, VAR18;
input VAR16,... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41oi/sky130_fd_sc_hs__a41oi_4.v | 2,312 | module MODULE1 (
VAR9 ,
VAR10 ,
VAR4 ,
VAR8 ,
VAR3 ,
VAR5 ,
VAR7,
VAR1
);
output VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR8 ;
input VAR3 ;
input VAR5 ;
input VAR7;
input VAR1;
VAR2 VAR6 (
.VAR9(VAR9),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR1(VAR1)
);
endmodule
module MODUL... | apache-2.0 |
skarpenko/ultiparc | rtl/src/fabric.v | 7,711 | module MODULE1(
clk,
VAR34,
VAR13, VAR64, VAR27, VAR53, VAR51, VAR17, VAR12,
VAR1, VAR24, VAR59, VAR19, VAR30, VAR10, VAR22,
VAR35, VAR18, VAR2, VAR33, VAR21, VAR67, VAR54,
VAR46, VAR42, VAR58, VAR36, VAR71, VAR66, VAR9,
VAR52, VAR25, VAR57, VAR8, VAR49, VAR41, VAR16,
VAR38, VAR7, VAR26, VAR43, VAR23, VAR20, VAR6,
VAR6... | bsd-2-clause |
jhennessy/parallella-hw-old | fpga/hdl/common/toggle2pulse.v | 1,143 | module MODULE1(
out,
clk, in, reset
);
input clk;
input in;
output out;
input reset;
reg VAR1;
always @ (posedge clk or posedge reset)
if(reset)
VAR1 <= 1'b0;
else
VAR1 <= in;
assign out = in ^ VAR1;
endmodule | gpl-3.0 |
zeruniverse/Single-cycle_CPU | .v source code/CPU_top.v | 2,580 | module MODULE1(
input wire VAR25,rst,clk,
input wire [1:0] VAR17,
input wire [4:0] VAR3,
output wire VAR56, output wire [5:0] VAR23,
output wire [3:0] VAR13,
output wire [7:0] VAR27 );
wire VAR6,VAR48,VAR28;
wire [31:0] VAR41;
wire [31:0] VAR44;
wire [31:0] VAR34;
wire [31:0] VAR30;
wire [31:0] VAR31,VAR12;
wire [4:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbp/sky130_fd_sc_ms__dlrbp.functional.v | 1,824 | module MODULE1 (
VAR12 ,
VAR10 ,
VAR9,
VAR1 ,
VAR2
);
output VAR12 ;
output VAR10 ;
input VAR9;
input VAR1 ;
input VAR2 ;
wire VAR7;
wire VAR4;
not VAR5 (VAR7 , VAR9 );
VAR13 VAR6 VAR3 (VAR4 , VAR1, VAR2, VAR7 );
buf VAR11 (VAR12 , VAR4 );
not VAR8 (VAR10 , VAR4 );
endmodule | apache-2.0 |
secworks/fltfpga | cpu/src/rtl/fltcpu_alu.v | 4,895 | module MODULE1(
input wire clk,
input wire VAR11,
input wire [5 : 0] VAR16,
input wire [31 : 0] VAR8,
input wire [31 : 0] VAR1,
output wire [31 : 0] VAR15,
output wire VAR20
);
localparam VAR12 = 6'h04;
localparam VAR6 = 6'h05;
localparam VAR24 = 6'h06;
localparam VAR13 = 6'h07;
localparam VAR14 = 6'h08;
localparam VAR... | bsd-2-clause |
asicguy/gplgpu | hdl/math/flt_fx1616_mult.v | 5,491 | module MODULE1
(
input clk,
input VAR12,
input [31:0] VAR21,
input [31:0] VAR38,
output reg [31:0] VAR46
);
reg VAR3; reg [31:0] VAR1;
reg [5:0] VAR32; reg [55:0] VAR30; reg [55:0] VAR24; reg VAR26;
reg VAR6;
reg [7:0] VAR37; reg [7:0] VAR16; reg VAR41; reg VAR44;
reg VAR9;
always @* begin
if(VAR21[31]) begin
VAR3 = 1;... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_2.functional.v | 1,040 | module MODULE1( VAR8, VAR1, VAR5 );
input VAR5, VAR8;
output VAR1;
wire VAR3;
not VAR7( VAR3, VAR5 );
wire VAR2;
not VAR6( VAR2, VAR8 );
and VAR4( VAR1, VAR3, VAR2 );
endmodule | apache-2.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/altera_reset_synchronizer.v | 3,547 | module MODULE1
parameter VAR3 = 1,
parameter VAR6 = 2
)
(
input VAR5 ,
input clk,
output VAR4
);
reg [VAR6-1:0] VAR1;
reg VAR2;
generate if (VAR3) begin
always @(posedge clk or posedge VAR5) begin
if (VAR5) begin
VAR1 <= {VAR6{1'b1}};
VAR2 <= 1'b1;
end
else begin
VAR1[VAR6-2:0] <= VAR1[VAR6-1:1];
VAR1[VAR6-1] <= 0;
VAR... | mit |
ptracton/wb_soc_template | behvioral/wb_intercon/wb_arbiter.v | 4,924 | module MODULE1
parameter VAR10 = 32,
parameter VAR2 = 2)
(
input VAR31,
input VAR3,
input [VAR2*VAR10-1:0] VAR27,
input [VAR2*VAR8-1:0] VAR22,
input [VAR2*4-1:0] VAR23,
input [VAR2-1:0] VAR14,
input [VAR2-1:0] VAR20,
input [VAR2-1:0] VAR19,
input [VAR2*3-1:0] VAR6,
input [VAR2*2-1:0] VAR34,
output [VAR2*VAR8-1:0] VAR21... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/bufz/gf180mcu_fd_sc_mcu9t5v0__bufz_3.behavioral.v | 1,170 | module MODULE1( VAR5, VAR4, VAR2 );
input VAR5, VAR4;
output VAR2;
VAR1 VAR3(.VAR5(VAR5),.VAR4(VAR4),.VAR2(VAR2));
VAR1 VAR6(.VAR5(VAR5),.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.functional.pp.v | 1,819 | module MODULE1 (
VAR1 ,
VAR6 ,
VAR14 ,
VAR7 ,
VAR11,
VAR9,
VAR8 ,
VAR5
);
output VAR1 ;
input VAR6 ;
input VAR14 ;
input VAR7 ;
input VAR11;
input VAR9;
input VAR8 ;
input VAR5 ;
wire VAR10 ;
wire VAR2;
nand VAR4 (VAR10 , VAR14, VAR6, VAR7 );
VAR13 VAR3 (VAR2, VAR10, VAR11, VAR9);
buf VAR12 (VAR1 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/bufinv/sky130_fd_sc_ms__bufinv_8.v | 2,044 | module MODULE2 (
VAR1 ,
VAR4 ,
VAR8,
VAR7,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR8;
input VAR7;
input VAR2 ;
input VAR5 ;
VAR6 VAR3 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR8;
supply0 VAR7;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi222/gf180mcu_fd_sc_mcu9t5v0__aoi222_2.functional.v | 3,002 | module MODULE1( VAR2, VAR9, VAR10, VAR32, VAR33, VAR31, VAR8 );
input VAR31, VAR8, VAR33, VAR32, VAR2, VAR10;
output VAR9;
wire VAR34;
not VAR1( VAR34, VAR31 );
wire VAR13;
not VAR21( VAR13, VAR33 );
wire VAR26;
not VAR18( VAR26, VAR2 );
wire VAR11;
and VAR7( VAR11, VAR34, VAR13, VAR26 );
wire VAR30;
not VAR22( VAR30, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o221ai/sky130_fd_sc_hd__o221ai.functional.pp.v | 2,212 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR17 ,
VAR7 ,
VAR13 ,
VAR18 ,
VAR2,
VAR12,
VAR6 ,
VAR20
);
output VAR3 ;
input VAR5 ;
input VAR17 ;
input VAR7 ;
input VAR13 ;
input VAR18 ;
input VAR2;
input VAR12;
input VAR6 ;
input VAR20 ;
wire VAR9 ;
wire VAR16 ;
wire VAR10 ;
wire VAR19;
or VAR14 (VAR9 , VAR13, VAR7 );
or VAR15 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.functional.v | 1,733 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR7 ,
VAR1 ,
VAR11,
VAR3
);
output VAR9 ;
input VAR4 ;
input VAR7 ;
input VAR1 ;
input VAR11;
input VAR3;
wire VAR8 ;
wire VAR2;
xor VAR10 (VAR8 , VAR4, VAR7, VAR1 );
VAR6 VAR12 (VAR2, VAR8, VAR11, VAR3);
buf VAR5 (VAR9 , VAR2 );
endmodule | apache-2.0 |
ludisu13/Estructuras2 | No tocar/controlMachine.v | 2,865 | module MODULE1
(
input wire VAR18,
input wire VAR11,
input wire VAR1,
input wire VAR3,
input wire VAR10,
output reg VAR15,
output reg VAR8,
output reg VAR13,
output reg VAR7,
output reg VAR5
);
reg [5:0] VAR12;
reg [1:0]VAR6;
reg [1:0]VAR9;
reg VAR14;
reg VAR2;
always @ ( posedge VAR18 )
if (VAR11)
begin
VAR6 = VAR16;
... | gpl-3.0 |
jmesmon/trifles | verilog/hw4/p24a.v | 1,328 | module MODULE1(output reg [7:0] VAR1, input clk, reset);
reg [3:0] state;
always @(posedge clk) begin
if (reset == 1) begin
state = 13;
end
case(state)
0: begin VAR1 <= 8'b00000010; state <= 1; end
1: begin VAR1 <= 8'b00000001; state <= 2; end
2: begin VAR1 <= 8'b00000100; state <= 3; end
3: begin VAR1 <= 8'b00000001; ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrbp/sky130_fd_sc_ms__sdfrbp.functional.v | 2,101 | module MODULE1 (
VAR15 ,
VAR17 ,
VAR1 ,
VAR9 ,
VAR3 ,
VAR14 ,
VAR6
);
output VAR15 ;
output VAR17 ;
input VAR1 ;
input VAR9 ;
input VAR3 ;
input VAR14 ;
input VAR6;
wire VAR7 ;
wire VAR5 ;
wire VAR8;
not VAR16 (VAR5 , VAR6 );
VAR4 VAR2 (VAR8, VAR9, VAR3, VAR14 );
VAR11 VAR13 VAR10 (VAR7 , VAR8, VAR1, VAR5);
buf VAR18 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlclkp/sky130_fd_sc_hs__dlclkp_1.v | 2,027 | module MODULE1 (
VAR3,
VAR6,
VAR1 ,
VAR4,
VAR7
);
output VAR3;
input VAR6;
input VAR1 ;
input VAR4;
input VAR7;
VAR2 VAR5 (
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR6,
VAR1
);
output VAR3;
input VAR6;
input VAR1 ;
supply1 VAR4;
supply0 VAR7;
VAR2 VAR5 (
.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkdlyinv5sd2/sky130_fd_sc_hs__clkdlyinv5sd2.symbol.v | 1,321 | module MODULE1 (
input VAR1,
output VAR4
);
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/alu_mult.v | 52,027 | module MODULE1(VAR30,VAR28,VAR15,VAR24,VAR3);
output [0:127] VAR3;
input [0:127] VAR30;
input [0:127] VAR28;
input [0:1] VAR15;
input [0:4] VAR24;
parameter VAR35 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR3;
reg [0:127] VAR6;
reg [0:15] VAR11;
reg [0:15] VAR32;
reg [0:15] VAR29;
reg [0:15] VAR36;
reg [0:1... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrsnq/gf180mcu_fd_sc_mcu7t5v0__dffrsnq_1.behavioral.pp.v | 8,945 | module MODULE1( VAR53, VAR29, VAR78, VAR11, VAR27, VAR26, VAR50 );
input VAR53, VAR29, VAR11, VAR78;
inout VAR26, VAR50;
output VAR27;
reg VAR42;
VAR87 VAR4(.VAR53(VAR53),.VAR29(VAR29),.VAR78(VAR78),.VAR11(VAR11),.VAR27(VAR27),.VAR26(VAR26),.VAR50(VAR50),.VAR42(VAR42));
VAR87 VAR24(.VAR53(VAR53),.VAR29(VAR29),.VAR78(VA... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_chroma_top.v | 10,980 | module MODULE1 (
clk ,
VAR65 ,
VAR24 ,
VAR34 ,
VAR27 ,
VAR3 ,
VAR49 ,
VAR33 ,
VAR13 ,
VAR8 ,
VAR6 ,
VAR16 ,
VAR28 ,
VAR42 ,
VAR38 ,
VAR46
);
input [1-1:0] clk ; input [1-1:0] VAR65 ;
input VAR24 ;
input VAR34;output VAR27 ;
output [1-1:0] VAR3 ; output [6-1:0] VAR49 ; input [2*VAR51-1:0] VAR33 ;
output [1-1:0] VAR13 ; ... | gpl-3.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/TopModuleTransfLineal.v | 7,670 | module MODULE1(
input clk,
input rst,
input enable,
input [15:0] VAR2,
input [15:0] VAR23,
input [15:0] VAR3,
input [15:0] VAR33,
input [15:0] VAR45,
output reg [31:0] VAR7,
output reg [31:0] VAR35,
output [31:0] VAR37,
output reg VAR25
);
assign VAR37 = VAR3;
wire VAR15; wire[31:0] VAR13; reg [15:0]VAR14; reg [15:0]VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o31ai/sky130_fd_sc_lp__o31ai.symbol.v | 1,354 | module MODULE1 (
input VAR8,
input VAR3,
input VAR4,
input VAR1,
output VAR9
);
supply1 VAR2;
supply0 VAR7;
supply1 VAR5 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
ZiCog/xoro | pll_sys_bb.v | 13,476 | module MODULE1 (
VAR2,
VAR5,
VAR3,
VAR1,
VAR4);
input VAR2;
output VAR5;
output VAR3;
output VAR1;
output VAR4;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxtp/sky130_fd_sc_hs__dlxtp.behavioral.pp.v | 1,772 | module MODULE1 (
VAR7,
VAR8,
VAR13 ,
VAR6 ,
VAR2
);
input VAR7;
input VAR8;
output VAR13 ;
input VAR6 ;
input VAR2;
wire VAR12 VAR3;
wire VAR12 VAR9 ;
reg VAR10 ;
wire VAR12 ;
wire VAR1 ;
VAR4 VAR11 (VAR12 , VAR9, VAR3, VAR10, VAR7, VAR8);
buf VAR5 (VAR13 , VAR12 );
assign VAR1 = ( VAR7 === 1'b1 );
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/dram/rtl/dramctl.v | 25,274 | module MODULE1 (
VAR103, VAR141, VAR100,
VAR134, VAR109, VAR56,
VAR22, VAR70, VAR83,
VAR75, VAR119, VAR121,
VAR171, VAR24, VAR54, VAR113,
VAR118, VAR195, VAR43,
VAR90, VAR5, VAR81,
VAR110, VAR14, VAR174,
VAR25, VAR167, VAR45,
VAR41, VAR147, VAR50,
VAR198, VAR60, VAR3,
VAR194,
VAR57, VAR130, VAR93,
VAR44, VAR144, VAR78,... | gpl-2.0 |
oere/progressive-learning-platform | reference/hw/verilog/mod_sram.v | 5,695 | module MODULE1(rst, clk, VAR22, VAR15, VAR5, VAR20, VAR17, din, VAR10, dout, VAR31, VAR19, VAR26, VAR7, VAR2, VAR23, VAR21, VAR14, VAR33, VAR12, VAR32, VAR1, VAR24, VAR3, VAR9);
input rst;
input clk;
input VAR22,VAR15;
input [31:0] VAR5, VAR20;
input [1:0] VAR17;
input [31:0] din;
output [31:0] VAR10, dout;
output [31:... | gpl-3.0 |
ptracton/wb_soc_template | rtl/LM32/rtl/lm32_load_store_unit.v | 33,769 | module MODULE1 (
VAR169,
VAR141,
VAR74,
VAR89,
VAR54,
VAR59,
VAR151,
VAR67,
VAR25,
VAR27,
VAR82,
VAR49,
VAR53,
VAR118,
VAR48,
VAR143,
VAR103,
VAR20,
VAR122,
VAR149,
VAR112,
VAR123,
VAR14,
VAR134,
VAR126,
VAR30,
VAR52,
VAR171,
VAR166,
VAR117,
VAR13,
VAR10,
VAR23,
VAR2,
VAR17,
VAR42,
VAR4,
VAR11,
VAR93,
VAR121,
VAR65,
VA... | mit |
fabianz66/cursos-tec | taller-digital/Proyecto Final/tec-drums/top_module.v | 1,463 | module MODULE1(
input VAR15,
input reset,
output VAR3,
output VAR7,
output VAR10,
output VAR11,
output[15:0] VAR6,
output [15:0] VAR17
);
wire VAR16;
VAR5 VAR2(
.VAR15(VAR15),
.reset(reset),
.VAR9(VAR16)
);
wire[15:0] VAR8;
wire[15:0] VAR13;
assign VAR6 = VAR8;
assign VAR17 = VAR13;
VAR14 VAR4 (
.reset(reset),
.VAR8(VA... | mit |
545/Atari7800 | core/ag_6502/trunk/agat7/ag_6502.v | 8,526 | module MODULE6(input VAR102, output VAR159, output VAR74);
wire VAR103;
not(VAR159,VAR102);
or(VAR103,~VAR102, VAR159);
not(VAR74, VAR103);
endmodule
module MODULE2(input VAR105, input VAR102, output reg VAR159);
parameter VAR132 = 1; VAR15 VAR159 = 0;
integer VAR137 = 0;
always @(posedge VAR105) begin
if (VAR102 != VA... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_project/ram_128_32x32_dp/ram_128_32x32_dp.v | 8,821 | module MODULE1 (
VAR32,
VAR3,
VAR38,
VAR47,
VAR27,
VAR7,
VAR23);
input [127:0] VAR32;
input [3:0] VAR3;
input VAR38;
input [1:0] VAR47;
input VAR27;
input VAR7;
output [31:0] VAR23;
wire [31:0] VAR36;
wire [31:0] VAR23 = VAR36[31:0];
VAR42 VAR13 (
.VAR53 (VAR7),
.VAR48 (VAR27),
.VAR26 (VAR38),
.VAR37 (VAR47),
.VAR10 (V... | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_spram_1024x32_bw.v | 12,875 | module MODULE1(
VAR7, VAR36, VAR53,
clk, rst, VAR11, VAR52, VAR33, addr, VAR46, VAR22
);
input VAR7;
input [VAR50 - 1:0] VAR53; output VAR36;
input clk; input rst; input VAR11; input [3:0] VAR52; input VAR33; input [9:0] addr; input [31:0] VAR46; output [31:0] VAR22;
assign VAR36 = VAR7;
VAR20 VAR51(
VAR24 VAR51(
VAR20... | gpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ip/zc702_xlconcat_1_0/synth/zc702_xlconcat_1_0.v | 4,462 | module MODULE1 (
VAR60,
dout
);
input wire [0 : 0] VAR60;
output wire [0 : 0] dout;
VAR23 #(
.VAR4(1),
.VAR13(1),
.VAR10(1),
.VAR37(1),
.VAR44(1),
.VAR49(1),
.VAR52(1),
.VAR30(1),
.VAR12(1),
.VAR67(1),
.VAR53(1),
.VAR54(1),
.VAR39(1),
.VAR1(1),
.VAR31(1),
.VAR2(1),
.VAR34(1),
.VAR9(1),
.VAR51(1),
.VAR28(1),
.VAR41(1),
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/conb/sky130_fd_sc_hd__conb.functional.pp.v | 1,889 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR4,
VAR1,
VAR3 ,
VAR13
);
output VAR6 ;
output VAR11 ;
input VAR4;
input VAR1;
input VAR3 ;
input VAR13 ;
wire VAR14 ;
wire VAR10;
pullup VAR2 (VAR14 );
VAR7 VAR9 (VAR6 , VAR14, VAR4 );
pulldown VAR8 (VAR10);
VAR12 VAR5 (VAR11 , VAR10, VAR1);
endmodule | apache-2.0 |
cpulabs/mist1032sa | src/core/rename/rename.v | 31,737 | module MODULE1(
input wire VAR104,
input wire VAR195,
input wire VAR180,
input wire VAR42,
input wire VAR173,
input wire [4:0] VAR1,
input wire [5:0] VAR86,
input wire VAR56,
input wire VAR51,
input wire [4:0] VAR124,
input wire [5:0] VAR132,
input wire VAR230,
input wire VAR5,
input wire [4:0] VAR61,
input wire [5:0] ... | bsd-2-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/NTNU FPU/low-cost-fpu-src/exponent_alu.v | 1,096 | module MODULE1(VAR5, VAR7, VAR4, VAR3, VAR6, VAR8);
input [2:0] VAR5;
input [VAR2:0] VAR7, VAR4; output VAR3, VAR6;
output [VAR2:0] VAR8;
reg [VAR2:0] VAR9;
assign VAR8 = VAR9;
assign VAR3 = (VAR9[VAR2] == 1'b1 ) ? 1'b1 : 1'b0;
assign VAR6 = (VAR9 == 9'b0) ? 1'b1 : 1'b0;
always @(VAR5, VAR7, VAR4) begin
VAR9 = 9'VAR1;
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.symbol.v | 1,322 | module MODULE1 (
input VAR3,
output VAR2
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR1 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_adc_2c_v1_00_a/hdl/verilog/cf_dcfilter.v | 3,460 | module MODULE1 (
VAR9,
VAR10,
VAR2,
VAR4);
input VAR9;
input [13:0] VAR10;
output [13:0] VAR2;
input [15:0] VAR4;
reg [13:0] VAR8 = 'd0;
reg [13:0] VAR2 = 'd0;
wire [30:0] VAR11;
always @(posedge VAR9) begin
VAR8 <= VAR11[30:17];
VAR2 <= VAR10 - VAR8;
end
VAR6 VAR13 (
.clk (VAR9),
.VAR5 (VAR10),
.VAR12 (VAR4),
.VAR7 (V... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_list.v | 7,712 | module MODULE1
parameter
VAR9 = 3, VAR11 = 8,
VAR18 = "VAR10", VAR14 = "VAR12" )
(
VAR3,
VAR6,
VAR22,
VAR20,
VAR2,
VAR13,
VAR17,
VAR23,
VAR8
);
input VAR3;
input VAR6;
input VAR20;
output VAR22;
output [VAR9-1:0] VAR2;
output [VAR11-1:0] VAR13;
output VAR23;
input VAR17;
input [VAR9-1:0] VAR8;
reg VAR22;
wire VAR20;
re... | lgpl-3.0 |
chris-wood/yield | sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_mux.v | 6,125 | module MODULE1 #
(
parameter VAR12 = "VAR22",
parameter integer VAR14 = 4,
parameter integer VAR19 = 2
)
(
input wire [VAR14-1:0] VAR8,
input wire [(2**VAR14)*VAR19-1:0] VAR23,
output wire [VAR19-1:0] VAR21
);
genvar VAR5;
generate
if ( VAR12 == "VAR22" || VAR14 < 3 ) begin : VAR9
assign VAR21 = VAR23[(VAR8)*VAR19 +: V... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_fpaddsub_arch2/integracion_fisica/front_end/db/SINGLE/Barrel_Shifter_syn.v | 60,182 | module MODULE3 ( VAR178, VAR101, VAR10, VAR4 );
input [0:0] VAR101;
input [0:0] VAR10;
output [0:0] VAR4;
input VAR178;
wire VAR34;
VAR147 VAR152 ( .VAR60(VAR101[0]), .VAR205(VAR34), .VAR193(VAR178), .VAR104(VAR10[0]), .VAR112(VAR4[0]) );
VAR216 VAR180 ( .VAR71(VAR178), .VAR112(VAR34) );
endmodule
module MODULE25 ( VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o22ai/sky130_fd_sc_hdll__o22ai.blackbox.v | 1,372 | module MODULE1 (
VAR7 ,
VAR6,
VAR1,
VAR4,
VAR3
);
output VAR7 ;
input VAR6;
input VAR1;
input VAR4;
input VAR3;
supply1 VAR9;
supply0 VAR8;
supply1 VAR2 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
bqlabs/toolchain-icestorm | build-data/yosys/share/greenpak4/cells_map.v | 1,029 | module \VAR20 (input VAR16, VAR5, output VAR2);
VAR12 VAR7 (
.VAR16(VAR16),
.VAR2(VAR2),
.VAR11(VAR5),
.VAR4(1'b1),
.VAR21(1'b1)
);
endmodule
module \VAR1 (input VAR5, VAR9, VAR14, VAR16, output VAR2);
VAR12 VAR7 (
.VAR16(VAR16),
.VAR2(VAR2),
.VAR11(VAR5),
.VAR4(VAR14),
.VAR21(VAR9)
);
endmodule
module MODULE2 (VAR3, V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.pp.blackbox.v | 1,308 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR5 ,
VAR6 ,
VAR7 ,
VAR4,
VAR3,
VAR8 ,
VAR9
);
output VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR8 ;
input VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp.blackbox.v | 1,268 | module MODULE1 (
VAR4 ,
VAR7 ,
VAR3
);
output VAR4 ;
input VAR7 ;
input VAR3;
supply1 VAR2;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ptracton/wb_soc_template | rtl/ZIP/rtl/div.v | 12,606 | module MODULE1(VAR5, VAR1, VAR6, VAR19, VAR4, VAR26,
VAR24, VAR8, VAR11, VAR3, VAR9);
parameter VAR15=32, VAR22 = 5;
input wire VAR5, VAR1;
input wire VAR6, VAR19;
input wire [(VAR15-1):0] VAR4, VAR26;
output reg VAR24, VAR8, VAR11;
output reg [(VAR15-1):0] VAR3;
output wire [3:0] VAR9;
reg VAR13;
reg [(2*VAR15-2):0] V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o21a/sky130_fd_sc_hs__o21a_4.v | 2,121 | module MODULE1 (
VAR8 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR5,
VAR2
);
output VAR8 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR5;
input VAR2;
VAR6 VAR1 (
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR8 ,
VAR3,
VAR4,
VAR7
);
output VAR8 ;
input VAR3;
input VAR4;
... | apache-2.0 |
betontalpfa2/AXI2SPI-bridge | hdl/axi2spi_bridge.v | 3,675 | module MODULE1(
input VAR21,
input VAR17,
input [31:0] VAR26, input [2:0] VAR40, output [0:0] VAR2, input [0:0] VAR35, input [31:0] VAR29, input [2:0] VAR31, output [0:0] VAR9, input [0:0] VAR46, input [0:0] VAR18, output [1:0] VAR19, output [0:0] VAR15, output [31:0] VAR50, input [0:0] VAR38, output [1:0] VAR42, outpu... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sgb/sgb_icd2.v | 22,727 | module MODULE1(
input VAR18,
output VAR23,
input VAR21,
input VAR78,
output VAR37,
input VAR91,
input VAR71,
input [23:0] VAR13,
input [7:0] VAR53,
output [7:0] VAR19,
input VAR7,
input VAR52,
input VAR12,
input [1:0] VAR81,
input VAR34,
input VAR64,
input [1:0] VAR65,
output [3:0] VAR32,
output VAR59,
input [15:0] VAR... | gpl-2.0 |
binderclip/BCOpenMIPS | cpu-code/openmips_min_sopc.v | 1,100 | module MODULE1 (
input wire clk,
input wire rst
);
wire[VAR25] VAR9;
wire[VAR27] VAR34;
wire VAR11;
wire[VAR4] VAR12;
wire[VAR4] VAR30;
wire[3:0] VAR17;
wire VAR5;
wire VAR31;
wire[VAR4] VAR32;
wire[5:0] int;
wire VAR1;
assign int = {5'b00000, VAR1};
VAR7 VAR33 (
.rst(rst),
.clk(clk),
.VAR10(VAR34),
.VAR18(VAR32),
.VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfrtp/sky130_fd_sc_ls__sdfrtp.functional.v | 1,972 | module MODULE1 (
VAR5 ,
VAR1 ,
VAR13 ,
VAR16 ,
VAR4 ,
VAR12
);
output VAR5 ;
input VAR1 ;
input VAR13 ;
input VAR16 ;
input VAR4 ;
input VAR12;
wire VAR8 ;
wire VAR10 ;
wire VAR15;
not VAR2 (VAR10 , VAR12 );
VAR6 VAR9 (VAR15, VAR13, VAR16, VAR4 );
VAR7 VAR3 VAR11 (VAR8 , VAR15, VAR1, VAR10);
buf VAR14 (VAR5 , VAR8 );
e... | apache-2.0 |
bluespec/Flute | builds/Flute_RV32CI_MU_WT_L1_iverilog_tohost/Verilog_RTL/mkBoot_ROM.v | 58,304 | module MODULE1(VAR2,
VAR7,
VAR90,
VAR127,
VAR38,
VAR8,
VAR82,
VAR176,
VAR144,
VAR173,
VAR48,
VAR5,
VAR9,
VAR130,
VAR40,
VAR77,
VAR128,
VAR63,
VAR109,
VAR170,
VAR11,
VAR94,
VAR142,
VAR42,
VAR143,
VAR85,
VAR106,
VAR65,
VAR49,
VAR163,
VAR167,
VAR100,
VAR131,
VAR124,
VAR19,
VAR135,
VAR116,
VAR162,
VAR103,
VAR166,
VAR175,
V... | apache-2.0 |
bunnie/novena-afe-hs-fpga | novena-afe-hs.srcs/sources_1/imports/imports/eim_debug.v | 4,275 | module MODULE1(
input wire VAR16,
input wire VAR32,
input wire VAR34,
input wire VAR13,
input wire VAR18,
input wire [2:0] VAR33,
input wire [15:0] VAR31,
input wire VAR1,
input wire VAR28,
input wire VAR3,
input wire VAR14,
output wire VAR20,
output wire VAR15,
output wire [23:0] VAR26,
input wire VAR5
);
wire VAR12;
... | apache-2.0 |
vvk/sysrek | hdmi_example/ipcore_dir/BINARYZACJA.v | 3,860 | module MODULE1(
VAR32,
clk,
VAR11
);
input [7 : 0] VAR32;
input clk;
output [7 : 0] VAR11;
VAR26 #(
.VAR45(8),
.VAR6("0"),
.VAR51(256),
.VAR22("VAR56"),
.VAR8(1),
.VAR53(0),
.VAR28(0),
.VAR7(0),
.VAR47(0),
.VAR5(0),
.VAR18(0),
.VAR55(0),
.VAR30(0),
.VAR38(0),
.VAR24(1),
.VAR35(0),
.VAR4(0),
.VAR50(0),
.VAR17(0),
.VAR54... | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/video_sys/synthesis/submodules/video_sys_Pixel_RGB_Resampler.v | 7,563 | module MODULE1 (
clk,
reset,
VAR9,
VAR19,
VAR4,
VAR7,
VAR21,
VAR2,
VAR18,
VAR10,
VAR11,
VAR8,
VAR1,
VAR17
);
parameter VAR15 = 15;
parameter VAR22 = 29;
parameter VAR5 = 0;
parameter VAR20 = 1;
parameter VAR12 = 10'h3FF;
input clk;
input reset;
input [VAR15:0] VAR9;
input VAR19;
input VAR4;
input [VAR5:0] VAR7;
input V... | gpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/ip_lpm.v | 9,017 | module MODULE1
parameter VAR29 = 5,
parameter VAR72 = VAR34,
parameter VAR37 = VAR49(VAR72)
)
( input [VAR7-1:0] VAR68,
output reg [31:0] VAR66,
output reg [VAR29-1:0] VAR67,
output reg VAR64,
output reg VAR61,
input VAR62,
input VAR1,
input [VAR37-1:0] VAR60, input VAR3, output [31:0] VAR74, output [31:0] VAR9, output... | apache-2.0 |
sehugg/8bitworkshop | presets/verilog/paddles.v | 1,118 | module MODULE1(clk, reset, VAR14, VAR16, VAR4, VAR2, VAR11);
input clk, reset;
input VAR4, VAR2;
output VAR14, VAR16;
output [2:0] VAR11;
wire VAR12;
wire [8:0] VAR13;
wire [8:0] VAR7;
reg [7:0] VAR10;
reg [7:0] VAR3;
reg [7:0] VAR9;
reg [7:0] VAR1;
always @(posedge VAR4)
VAR9 <= VAR7[7:0];
always @(posedge VAR2)
VAR1 ... | gpl-3.0 |
freecores/zet86 | soc/vga/rtl/ram2k_b16_attr.v | 7,578 | module MODULE1 (clk, rst, VAR10, VAR55, addr, VAR65, VAR18);
input clk;
input rst;
input VAR10;
input VAR55;
input [10:0] addr;
output [7:0] VAR65;
input [7:0] VAR18;
wire VAR39;
VAR37 VAR76 (.VAR31(VAR65),
.VAR13 (VAR39),
.VAR57 (addr),
.VAR72 (clk),
.VAR64 (VAR18),
.VAR80 (VAR39),
.VAR24 (VAR10),
.VAR23 (rst),
.VAR51... | gpl-3.0 |
omicronns/studies-sys-rek | de1-soc/src/image_processor_dbg.v | 1,632 | module MODULE1 (
input VAR6,
input VAR4,
input VAR9,
input VAR5,
output [23:0] VAR10
);
assign VAR10 = (VAR5 == 1) ? VAR1 : VAR2;
reg [23:0] VAR1 = 0;
reg [23:0] VAR2 = 0;
reg [23:0] VAR11 = 0;
reg [32:0] VAR8 = 0;
reg [23:0] VAR3 = 0;
reg [23:0] VAR7 = 0;
reg VAR12 = 0;
reg VAR13 = 0;
always@(posedge VAR6)
begin
VAR8 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/maj3/sky130_fd_sc_lp__maj3.symbol.v | 1,284 | module MODULE1 (
input VAR5,
input VAR7,
input VAR3,
output VAR1
);
supply1 VAR8;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
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