repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_2.functional.pp.v | 1,462 | module MODULE1( VAR10, VAR15, VAR17, VAR7, VAR1, VAR8, VAR4 );
input VAR1, VAR7, VAR17, VAR10;
inout VAR8, VAR4;
output VAR15;
wire VAR16;
not VAR3( VAR16, VAR1 );
wire VAR18;
not VAR12( VAR18, VAR7 );
wire VAR11;
not VAR14( VAR11, VAR17 );
wire VAR9;
and VAR2( VAR9, VAR16, VAR18, VAR11 );
wire VAR6;
not VAR13( VAR6, V... | apache-2.0 |
Marcoslz22/Tercer_Proyecto | MainActivity.v | 6,404 | module MODULE1
(
input [7:0] VAR55,
input [7:0]VAR48,
input [7:0]VAR28,
input [7:0]VAR1,
input VAR5,
input VAR14,
input [3:0] VAR12, VAR37,
input [3:0] VAR44,
input clk, reset, VAR20,VAR33, output [7:0] VAR4, output VAR47, output VAR29, output [7:0] VAR27,
output [7:0] VAR58,
output [7:0] VAR60
);
reg VAR38 = 0;
reg [7... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cic_dec_shifter.v | 3,983 | module MODULE1(VAR5,VAR1,VAR2);
parameter VAR6 = 16;
parameter VAR3 = 28;
input [7:0] VAR5;
input wire [VAR6+VAR3-1:0] VAR1;
output reg [VAR6-1:0] VAR2;
function [4:0] VAR4;
input [7:0] VAR5;
case(VAR5)
8'd1 : VAR4 = 0;
8'd2 : VAR4 = 4;
8'd4 : VAR4 = 8;
8'd8 : VAR4 = 12;
8'd16 : VAR4 = 16;
8'd32 : VAR4 = 20;
8'd64 : VA... | gpl-2.0 |
merckhung/zet | cores/ps2/rtl/ps2.v | 19,681 | module MODULE1 (
input VAR8, input VAR5, input [15:0] VAR66, output [15:0] VAR41, input VAR87, input VAR82, input [ 2:1] VAR93, input [ 1:0] VAR83, input VAR4, output VAR24, output VAR45, output VAR70,
input VAR11, inout VAR95, inout VAR25, inout VAR84 );
wire [7:0] VAR7;
wire [2:0] VAR90;
wire VAR100;
wire VAR65;
wire... | gpl-3.0 |
asicguy/gplgpu | hdl/mc_cache/mc_cache_full.v | 11,050 | module MODULE1
(
input VAR7,
input VAR69,
input [3:0] VAR34,
input VAR42,
input VAR30,
input VAR8,
input [23:0] VAR46,
input [127:0] VAR63,
input [15:0] VAR27,
input [5:0] VAR22,
output VAR28,
output reg [127:0] VAR35,
output reg VAR11,
input VAR33,
input VAR6,
input [255:0] VAR48,
output reg VAR66,
output reg VAR55,
o... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21ai/sky130_fd_sc_lp__o21ai.functional.pp.v | 2,010 | module MODULE1 (
VAR2 ,
VAR16 ,
VAR14 ,
VAR8 ,
VAR4,
VAR13,
VAR1 ,
VAR9
);
output VAR2 ;
input VAR16 ;
input VAR14 ;
input VAR8 ;
input VAR4;
input VAR13;
input VAR1 ;
input VAR9 ;
wire VAR3 ;
wire VAR6 ;
wire VAR11;
or VAR7 (VAR3 , VAR14, VAR16 );
nand VAR5 (VAR6 , VAR8, VAR3 );
VAR12 VAR10 (VAR11, VAR6, VAR4, VAR13);... | apache-2.0 |
rkrajnc/minimig-mist | rtl/sdram/dpram_be_1024x16.v | 11,569 | module MODULE1 (
VAR20,
VAR49,
VAR18,
VAR25,
VAR27,
VAR41,
VAR55,
VAR59,
VAR48,
VAR28,
VAR35);
input [9:0] VAR20;
input [9:0] VAR49;
input [1:0] VAR18;
input [1:0] VAR25;
input VAR27;
input [15:0] VAR41;
input [15:0] VAR55;
input VAR59;
input VAR48;
output [15:0] VAR28;
output [15:0] VAR35;
tri1 [1:0] VAR18;
tri1 [1:0]... | gpl-3.0 |
duttondj/DigitalDesignI-P2 | receive.v | 1,457 | module MODULE1(clk, VAR9, VAR2, VAR8);
input clk; input[9:0] VAR9; output[8:0] VAR2; output VAR8; wire[8:0] VAR2;
wire VAR8;
wire VAR1; wire VAR10, VAR5;
VAR3 VAR7(clk, VAR9, {VAR1, VAR2});
hc280 VAR6(VAR2, VAR5, VAR10);
xnor VAR4(VAR8, VAR10, VAR1);
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.v | 2,034 | module MODULE2 (
VAR5 ,
VAR6 ,
VAR4,
VAR8,
VAR1 ,
VAR2
);
output VAR5 ;
input VAR6 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR2 ;
VAR7 VAR3 (
.VAR5(VAR5),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.functional.pp.v | 1,867 | module MODULE1 (
VAR1 ,
VAR12 ,
VAR10,
VAR5,
VAR6 ,
VAR9
);
output VAR1 ;
input VAR12 ;
input VAR10;
input VAR5;
input VAR6 ;
input VAR9 ;
wire VAR7 ;
wire VAR2;
not VAR3 (VAR7 , VAR12 );
VAR8 VAR4 (VAR2, VAR7, VAR10, VAR5);
buf VAR11 (VAR1 , VAR2 );
endmodule | apache-2.0 |
VitorCBSB/hw-verilog | C++/Verilog/circ_gen/uart_transceiver.v | 3,784 | module MODULE1(
input VAR8,
input VAR19,
input VAR20,
output reg VAR9,
input [15:0] VAR14,
output reg [7:0] VAR4,
output reg VAR17,
input [7:0] VAR16,
input VAR18,
output reg VAR13
);
reg [15:0] VAR6;
wire VAR12;
assign VAR12 = (VAR6 == 16'd0);
always @(posedge VAR19) begin
if(VAR8)
VAR6 <= VAR14 - 16'b1;
end
else begi... | mit |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_chroma_resampler_0.v | 7,298 | module MODULE1 (
clk,
reset,
VAR10,
VAR18,
VAR16,
VAR9,
VAR5,
VAR25,
VAR24,
VAR11,
VAR1,
VAR14,
VAR20,
VAR12
);
parameter VAR4 = 15; parameter VAR23 = 23;
parameter VAR19 = 0; parameter VAR17 = 1;
input clk;
input reset;
input [VAR4:0] VAR10;
input VAR18;
input VAR16;
input [VAR19:0] VAR9;
input VAR5;
input VAR25;
outp... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.pp.blackbox.v | 1,253 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR1,
VAR6,
VAR4 ,
VAR5
);
output VAR3 ;
input VAR2 ;
input VAR1;
input VAR6;
input VAR4 ;
input VAR5 ;
endmodule | apache-2.0 |
tmolteno/TART | hardware/FPGA/ddrmem/ddr_lite.v | 10,734 | module MODULE1 (
VAR27,
VAR31,
VAR118,
VAR44,
VAR66,
VAR17,
VAR40,
VAR43,
VAR81,
VAR24,
VAR96,
VAR75,
VAR116,
VAR46,
VAR52,
VAR101,
VAR97,
VAR94,
VAR47,
VAR16,
VAR32,
VAR112,
VAR5,
VAR9,
VAR64,
VAR34,
VAR127,
VAR19,
VAR68
);
parameter VAR99 = 585; parameter VAR21 = 2; parameter VAR89 = 2;
input VAR27;
input VAR31;
inpu... | lgpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_mc_controller/control_registers.v | 8,703 | module MODULE1
(
input VAR27,
input VAR40,
input VAR34,
input [13:0] VAR38,
input [31:0] VAR29,
output reg VAR18,
input VAR10,
input [13:0] VAR6,
output reg [31:0] VAR26,
output reg VAR32,
input [31:0] VAR9,
output [10:0] VAR24,
output [31:0] VAR2,
output [31:0] VAR41,
output [31:0] VAR11,
output [31:0] VAR35,
output [... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3b/sky130_fd_sc_ms__nand3b.blackbox.v | 1,301 | module MODULE1 (
VAR6 ,
VAR3,
VAR2 ,
VAR5
);
output VAR6 ;
input VAR3;
input VAR2 ;
input VAR5 ;
supply1 VAR8;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2bb2oi/sky130_fd_sc_hs__a2bb2oi.pp.symbol.v | 1,424 | module MODULE1 (
input VAR6,
input VAR7,
input VAR1 ,
input VAR3 ,
output VAR2 ,
input VAR4,
input VAR5
);
endmodule | apache-2.0 |
aj-michael/Digital-Systems | Lab6-Part2/ipcore_dir/SystemClockUnit/example_design/SystemClockUnit_exdes.v | 4,934 | module MODULE1
parameter VAR8 = 100
)
( input VAR26,
input VAR27,
output [1:1] VAR1,
output VAR19,
output VAR10
);
localparam VAR3 = 16;
wire VAR12 = !VAR10 || VAR27;
reg VAR24;
reg VAR25;
reg VAR14;
reg VAR7;
wire VAR9;
wire VAR23;
wire clk;
reg [VAR3-1:0] counter;
VAR20 VAR18
( .VAR26 (VAR26),
.VAR22 (VAR9),
.VAR10 (... | mit |
moizumi99/brainf__k_CPU | hdl/dmem16.v | 7,000 | module MODULE1 (
address,
VAR30,
VAR37,
VAR28,
VAR27);
input [11:0] address;
input VAR30;
input [15:0] VAR37;
input VAR28;
output [15:0] VAR27;
tri1 VAR30;
wire [15:0] VAR26;
wire [15:0] VAR27 = VAR26[15:0];
VAR19 VAR20 (
.VAR25 (address),
.VAR16 (VAR30),
.VAR36 (VAR37),
.VAR6 (VAR28),
.VAR4 (VAR26),
.VAR10 (1'b0),
.VA... | unlicense |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/ml605/pcie_core/source/axi_basic_rx_pipeline.v | 26,810 | module MODULE1 #(
parameter VAR42 = 128, parameter VAR75 = "VAR36", parameter VAR40 = 1,
parameter VAR55 = (VAR42 == 128) ? 2 : 1, parameter VAR6 = VAR42 / 8 ) (
output reg [VAR42-1:0] VAR13, output reg VAR30, input VAR15, output [VAR6-1:0] VAR77, output VAR29, output reg [21:0] VAR74,
input [VAR42-1:0] VAR35, input VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2oi/sky130_fd_sc_ms__a2bb2oi.behavioral.pp.v | 2,245 | module MODULE1 (
VAR18 ,
VAR7,
VAR14,
VAR3 ,
VAR19 ,
VAR16,
VAR9,
VAR11 ,
VAR6
);
output VAR18 ;
input VAR7;
input VAR14;
input VAR3 ;
input VAR19 ;
input VAR16;
input VAR9;
input VAR11 ;
input VAR6 ;
wire VAR1 ;
wire VAR12 ;
wire VAR10 ;
wire VAR5;
and VAR15 (VAR1 , VAR3, VAR19 );
nor VAR8 (VAR12 , VAR7, VAR14 );
nor ... | apache-2.0 |
horie-t/TD4-GateLevel | TD4-GateLevel_prj/TD4-GateLevel.srcs/sources_1/new/Clocks.v | 3,144 | module MODULE2
(input VAR8,
input reset,
output VAR3,
output VAR2);
parameter VAR1 = 26'd49999999;
parameter VAR5 = 26;
parameter VAR4 = 23'd4999999;
parameter VAR13 = 23;
MODULE1 #(VAR1, VAR5)VAR12(VAR8, reset, VAR3);
MODULE1 #(VAR4, VAR13)VAR14(VAR8, reset, VAR2);
endmodule
module MODULE1
VAR6 = 26)
(input VAR8,
inpu... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux4/gf180mcu_fd_sc_mcu7t5v0__mux4_2.behavioral.pp.v | 8,324 | module MODULE1( VAR2, VAR6, VAR9, VAR11, VAR10, VAR3, VAR12, VAR4, VAR7 );
input VAR12, VAR3, VAR2, VAR9, VAR6, VAR10;
inout VAR4, VAR7;
output VAR11;
VAR1 VAR5(.VAR2(VAR2),.VAR6(VAR6),.VAR9(VAR9),.VAR11(VAR11),.VAR10(VAR10),.VAR3(VAR3),.VAR12(VAR12),.VAR4(VAR4),.VAR7(VAR7));
VAR1 VAR8(.VAR2(VAR2),.VAR6(VAR6),.VAR9(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31a/sky130_fd_sc_ms__o31a.blackbox.v | 1,339 | module MODULE1 (
VAR3 ,
VAR6,
VAR8,
VAR7,
VAR4
);
output VAR3 ;
input VAR6;
input VAR8;
input VAR7;
input VAR4;
supply1 VAR2;
supply0 VAR5;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
jfzazo/pcapFromVerilog | pcap_parse.v | 10,818 | module MODULE1 #(
parameter VAR8 = "none",
parameter VAR6 = "VAR16",
parameter VAR7 = 6 ,
parameter VAR28 = 0 ,
parameter VAR17 = 0 ,
parameter VAR29 = 156250000,
parameter VAR32 = 64
) (
input VAR23 ,
output reg [ VAR32-1:0] VAR31 , output reg [(VAR32/8)-1:0] VAR10 , input wire ready , output reg valid , output reg VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/mux2i/sky130_fd_sc_ms__mux2i.blackbox.v | 1,291 | module MODULE1 (
VAR1 ,
VAR2,
VAR8,
VAR4
);
output VAR1 ;
input VAR2;
input VAR8;
input VAR4 ;
supply1 VAR5;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
njZhuMin/curriculum_design | Lift_control/LiftControl.v | 16,822 | module MODULE1(VAR41,VAR31,VAR6,VAR2,VAR20,VAR38,reset,VAR29,VAR37,VAR52,VAR9,VAR39
,VAR33,VAR55,VAR42,VAR4,VAR49,VAR19,VAR27,VAR24
,VAR23,VAR1,VAR40,VAR48);
output VAR33,VAR55,VAR42,VAR4,VAR49,VAR19,VAR27,VAR24,VAR23,VAR1; output[3:0] VAR40; output[6:0] VAR48;
input VAR41,VAR31,VAR6,VAR2,VAR20,VAR38,reset,VAR29,VAR37,... | gpl-3.0 |
horia141/bachelor-thesis | prj/components/Rotary/RotaryInterface.v | 3,324 | module MODULE1(VAR5,reset,VAR3,VAR7,VAR2);
input wire VAR5;
input wire reset;
input wire [1:0] VAR3;
output wire VAR7;
output wire VAR2;
reg VAR9;
reg VAR8;
reg VAR11;
reg VAR1;
reg VAR4;
reg VAR10;
reg VAR6;
assign VAR7 = VAR1;
assign VAR2 = VAR10;
always @ (posedge VAR5) begin
if (reset) begin
VAR9 <= 0;
VAR8 <= 0;
e... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4bb/sky130_fd_sc_ms__nor4bb.symbol.v | 1,333 | module MODULE1 (
input VAR3 ,
input VAR1 ,
input VAR8,
input VAR9,
output VAR5
);
supply1 VAR7;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
GREO/GNU-Radio | usrp/fpga/sdr_lib/tx_chain_hb.v | 2,471 | module MODULE1
(input VAR2,
input reset,
input enable,
input wire [7:0] VAR39,
input VAR19,
input VAR11,
input VAR34,
input wire [31:0] VAR8,
input wire [15:0] VAR21,
input wire [15:0] VAR24,
output wire [15:0] VAR29,
output wire [15:0] VAR37,
output wire [15:0] VAR35, output [15:0] VAR30
);
assign VAR35[15:13] = {VAR1... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_4.functional.v | 1,666 | module MODULE1( VAR5, VAR1, VAR18, VAR9, VAR2, VAR15 );
input VAR18, VAR5, VAR1, VAR15, VAR2;
output VAR9;
wire VAR6;
not VAR4( VAR6, VAR18 );
wire VAR21;
not VAR11( VAR21, VAR5 );
wire VAR19;
not VAR8( VAR19, VAR1 );
wire VAR13;
and VAR14( VAR13, VAR6, VAR21, VAR19 );
wire VAR16;
not VAR17( VAR16, VAR15 );
wire VAR3;
... | apache-2.0 |
DeadWitcher/amber-de0-nano | hw/vlog/ethmac/eth_random.v | 5,732 | module MODULE1 (VAR5, VAR7, VAR6, VAR10, VAR2, VAR12, VAR1,
VAR14, VAR11);
parameter VAR9 = 1;
input VAR5;
input VAR7;
input VAR6;
input VAR10;
input [3:0] VAR2;
input [15:0] VAR12;
input [9:0] VAR1;
output VAR14;
output VAR11;
wire VAR8;
reg [9:0] VAR4;
wire [9:0] VAR3;
reg [9:0] VAR13;
always @ (posedge VAR5 or posed... | lgpl-2.1 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_4.behavioral.pp.v | 18,950 | module MODULE1( VAR81, VAR115, VAR119, VAR120, VAR220, VAR2, VAR245, VAR68 );
input VAR120, VAR119, VAR81, VAR220, VAR115;
inout VAR245, VAR68;
output VAR2;
reg VAR27;
VAR90 VAR210(.VAR81(VAR81),.VAR115(VAR115),.VAR119(VAR119),.VAR120(VAR120),.VAR220(VAR220),.VAR2(VAR2),.VAR245(VAR245),.VAR68(VAR68),.VAR27(VAR27));
VAR... | apache-2.0 |
jotego/jt12 | ver/common/sep24.v | 3,469 | module MODULE1 #(parameter VAR15=10, parameter VAR22=5'd0)
(
input clk,
input VAR23,
input [VAR15-1:0] VAR10,
input [23:0] VAR31,
input [4:0] VAR20,
output reg [VAR15-1:0] VAR13,
output reg [VAR15-1:0] VAR17,
output reg [VAR15-1:0] VAR27,
output reg [VAR15-1:0] VAR30,
output reg [VAR15-1:0] VAR24,
output reg [VAR15-1:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221a/sky130_fd_sc_ms__o221a_4.v | 2,444 | module MODULE2 (
VAR8 ,
VAR6 ,
VAR2 ,
VAR4 ,
VAR10 ,
VAR1 ,
VAR9,
VAR11,
VAR12 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR2 ;
input VAR4 ;
input VAR10 ;
input VAR1 ;
input VAR9;
input VAR11;
input VAR12 ;
input VAR3 ;
VAR5 VAR7 (
.VAR8(VAR8),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR9(V... | apache-2.0 |
somethingnew2-0/CS552-CPU | InstructionDecode.v | 1,455 | module MODULE1(VAR36, clk, VAR5, VAR9, VAR6, VAR32, VAR19, VAR21, VAR25, VAR29, VAR10, VAR3, VAR12, VAR26, VAR38, VAR28, VAR16, VAR23, VAR14, VAR35, VAR17, VAR33, VAR27, VAR24, VAR8, VAR30, VAR2);
input [15:0] VAR36;
input clk, VAR5;
input [15:0] VAR6; input [3:0] VAR9; input VAR32;
output [15:0] VAR19, VAR21;
output [... | mit |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/synth/zynq_1_auto_pc_9.v | 13,116 | module MODULE1 (
VAR3,
VAR24,
VAR40,
VAR55,
VAR86,
VAR98,
VAR63,
VAR85,
VAR44,
VAR78,
VAR76,
VAR67,
VAR2,
VAR93,
VAR39,
VAR14,
VAR97,
VAR64,
VAR79,
VAR90,
VAR99,
VAR107,
VAR26,
VAR83,
VAR51,
VAR54,
VAR7,
VAR13,
VAR71,
VAR72,
VAR70,
VAR69,
VAR20,
VAR75,
VAR6,
VAR96,
VAR34,
VAR66,
VAR17,
VAR82,
VAR12,
VAR113,
VAR43,
VAR1... | mit |
alexforencich/verilog-ethernet | lib/axis/rtl/axis_arb_mux.v | 11,643 | module MODULE1 #
(
parameter VAR27 = 4,
parameter VAR29 = 8,
parameter VAR34 = (VAR29>8),
parameter VAR21 = ((VAR29+7)/8),
parameter VAR23 = 0,
parameter VAR2 = 8,
parameter VAR5 = VAR2+VAR18(VAR27),
parameter VAR31 = 0,
parameter VAR14 = 8,
parameter VAR13 = 1,
parameter VAR1 = 1,
parameter VAR33 = 1,
parameter VAR20 ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21oi/sky130_fd_sc_ls__a21oi.pp.blackbox.v | 1,359 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1 ,
VAR7 ,
VAR6,
VAR2,
VAR8 ,
VAR4
);
output VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR7 ;
input VAR6;
input VAR2;
input VAR8 ;
input VAR4 ;
endmodule | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_timeIn.v | 2,097 | module MODULE1 (
address,
VAR5,
clk,
VAR6,
VAR7,
VAR2,
VAR9,
VAR1
)
;
output [ 5: 0] VAR9;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR5;
input clk;
input VAR6;
input VAR7;
input [ 31: 0] VAR2;
wire VAR3;
reg [ 5: 0] VAR4;
wire [ 5: 0] VAR9;
wire [ 5: 0] VAR8;
wire [ 31: 0] VAR1;
assign VAR3 = 1;
assign VAR8 ... | gpl-3.0 |
jaechoon2/FPGA-Imaging-Library | Point/ColorReversal/HDL/ColorReversal.srcs/sources_1/new/ColorReversal.v | 2,820 | module MODULE1(
clk,
VAR7,
VAR3,
VAR1,
VAR9,
VAR2);
parameter[0 : 0] VAR4 = 0;
parameter VAR11 = 3;
parameter[3: 0] VAR8 = 8;
input clk;
input VAR7;
input VAR3;
input [VAR11 * VAR8 - 1 : 0] VAR1;
output VAR9;
output[VAR11 * VAR8 - 1 : 0] VAR2;
reg VAR5;
reg[VAR11 * VAR8 - 1 : 0] VAR6;
genvar VAR10;
generate
always @(po... | lgpl-2.1 |
mgohde/MiniMicroII | RevisionB/intpipe.v | 2,888 | module MODULE1(VAR25, clk, rst, VAR32, VAR13, VAR17, VAR21, VAR28, VAR18, VAR5, VAR26, VAR6, VAR33, VAR24, VAR30, VAR22, VAR34, VAR11);
input [3:0] VAR25;
input clk;
input rst;
input VAR32;
input VAR13;
input [2:0] VAR17;
input [2:0] VAR21;
input [2:0] VAR28;
input [15:0] VAR18;
input [15:0] VAR5;
input [7:0] VAR26;
ou... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_0.v | 2,036 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR3,
VAR6,
VAR5 ,
VAR8
);
output VAR1 ;
input VAR7 ;
input VAR3;
input VAR6;
input VAR5 ;
input VAR8 ;
VAR4 VAR2 (
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR1,
VAR7
);
output VAR1;
input VAR7;
supply1 VAR3;
supply0 VAR6;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp.behavioral.pp.v | 1,957 | module MODULE1 (
VAR1 ,
VAR13 ,
VAR3,
VAR6,
VAR11,
VAR12 ,
VAR4
);
output VAR1 ;
input VAR13 ;
input VAR3;
input VAR6;
input VAR11;
input VAR12 ;
input VAR4 ;
wire VAR9 ;
wire VAR5;
VAR8 VAR7 (VAR9 , VAR13, VAR6, VAR11 );
VAR8 VAR2 (VAR5, VAR3, VAR6, VAR11 );
bufif0 VAR10 (VAR1 , VAR9, VAR5);
endmodule | apache-2.0 |
YoelRP/PROYECTO | bin/enpoint/data_setup/CRC16_D72 (1).v | 4,903 | module MODULE1(
VAR3,
VAR2,
VAR7
);
output reg [15:0] VAR3;
input wire [71:0] VAR2;
input wire [15:0] VAR7;
reg [71:0] VAR1;
reg [15:0] VAR6;
reg [15:0] VAR4;
begin
VAR1 = VAR2;
VAR6 = VAR7;
VAR4[0] = VAR1[71] ^ VAR1[69] ^ VAR1[68] ^ VAR1[67] ^ VAR1[66] ^ VAR1[65] ^ VAR1[64] ^ VAR1[63] ^ VAR1[62] ^ VAR1[61] ^ VAR1[60] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkinv/sky130_fd_sc_hd__clkinv.functional.v | 1,251 | module MODULE1 (
VAR4,
VAR5
);
output VAR4;
input VAR5;
wire VAR1;
not VAR3 (VAR1, VAR5 );
buf VAR2 (VAR4 , VAR1 );
endmodule | apache-2.0 |
google/yaricv32 | mem.v | 3,849 | module MODULE1(
input rst,
input clk,
input VAR22,
input [VAR1-1 : 0] VAR16,
input [VAR1-1 : 0] VAR5,
input [VAR17-1 : 0] VAR18,
input [2:0] VAR11,
output [VAR17-1 : 0] VAR15,
output VAR19);
parameter VAR1 = 12;
parameter VAR17 = 32;
parameter VAR21 = 2; parameter VAR12 = 3'b000;
parameter VAR23 = 3'b001;
parameter VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.symbol.v | 1,264 | module MODULE1 (
input VAR3,
input VAR2,
output VAR1
);
supply1 VAR5;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_15kHz/fir_lp_15kHz_stub.v | 1,493 | module MODULE1(VAR3, VAR6, VAR1, VAR4, VAR5, VAR2)
;
input VAR3;
input VAR6;
output VAR1;
input [15:0]VAR4;
output VAR5;
output [47:0]VAR2;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv/sky130_fd_sc_hvl__lsbuflv2hv.symbol.v | 1,405 | module MODULE1 (
input VAR2,
output VAR4
);
supply1 VAR7 ;
supply0 VAR1 ;
supply1 VAR3;
supply1 VAR6 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x8_250/source/pcie_7x_v1_3_pipe_reset.v | 16,482 | module MODULE1 #
(
parameter VAR8 = "VAR14", parameter VAR21 = "VAR45", parameter VAR7 = "VAR4", parameter VAR51 = 1, parameter VAR2 = 6'd63, parameter VAR18 = 1
)
(
input VAR12,
input VAR10,
input VAR37,
input VAR11,
input [VAR51-1:0] VAR16,
input VAR66,
input [VAR51-1:0] VAR32,
input [VAR51-1:0] VAR44,
input VAR25,
i... | lgpl-3.0 |
MarcoVogt/basil | firmware/modules/fei4_rx/fei4_rx.v | 2,359 | module MODULE1
parameter VAR25 = 32'h0000,
parameter VAR17 = 32'h0000,
parameter VAR28 = 10,
parameter VAR15 = 0,
parameter VAR20 = 16,
parameter VAR21 = 0
)
(
input wire VAR22,
input wire VAR29,
input wire VAR6,
input wire VAR4,
output wire VAR9,
output wire VAR2,
output wire VAR26,
input wire VAR19,
input wire VAR36,... | bsd-3-clause |
ptracton/Picoblaze | projects/display/rtl/cpu.v | 2,787 | module MODULE1 (
VAR21, VAR2, VAR14, VAR18, VAR7,
clk, VAR5, interrupt, VAR17, VAR8
) ;
input clk;
input [7:0] VAR5;
output [7:0] VAR21;
output [7:0] VAR2;
output VAR14;
output VAR18;
input interrupt; output VAR7;
input VAR17;
input VAR8;
wire [11:0] address;
wire [17:0] VAR16;
wire [7:0] VAR2;
wire [7:0] VAR21;
wire V... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai21/gf180mcu_fd_sc_mcu9t5v0__oai21_1.functional.v | 1,264 | module MODULE1( VAR13, VAR11, VAR12, VAR2 );
input VAR12, VAR13, VAR2;
output VAR11;
wire VAR8;
not VAR4( VAR8, VAR12 );
wire VAR1;
not VAR9( VAR1, VAR13 );
wire VAR3;
and VAR10( VAR3, VAR8, VAR1 );
wire VAR5;
not VAR6( VAR5, VAR2 );
or VAR7( VAR11, VAR3, VAR5 );
endmodule | apache-2.0 |
alexforencich/verilog-uart | example/ATLYS/fpga/rtl/fpga.v | 4,379 | module MODULE1 (
input wire clk,
input wire VAR36,
input wire VAR46,
input wire VAR71,
input wire VAR51,
input wire VAR29,
input wire VAR18,
input wire [7:0] VAR9,
output wire [7:0] VAR59,
input wire VAR13,
input wire [7:0] VAR32,
input wire VAR55,
input wire VAR43,
output wire VAR76,
output wire [7:0] VAR81,
output wi... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_stub.v | 1,748 | module MODULE1(VAR9, VAR3, VAR12, VAR14, VAR10, VAR11, VAR6, VAR5, VAR7, VAR8,
VAR4, VAR2, VAR13, VAR1)
;
input VAR9;
input VAR3;
input VAR12;
input [3:0]VAR14;
input [31:0]VAR10;
input [31:0]VAR11;
output [31:0]VAR6;
input VAR5;
input VAR7;
input VAR8;
input [3:0]VAR4;
input [31:0]VAR2;
input [31:0]VAR13;
output [31:0... | mit |
ffu/DSA-3.2.2 | usrp/fpga/toplevel/usrp_std/usrp_std.v | 12,631 | module MODULE1
(output VAR160,
input VAR157,
input VAR97,
input VAR123,
inout VAR53,
input VAR58,
input VAR106,
output VAR191,
output VAR23,
input wire [11:0] VAR62,
input wire [11:0] VAR64,
input wire [11:0] VAR2,
input wire [11:0] VAR27,
output wire [13:0] VAR72,
output wire [13:0] VAR15,
output wire VAR155,
output w... | gpl-3.0 |
YosysHQ/yosys | techlibs/intel_alm/common/quartus_rename.v | 7,552 | module MODULE13(output VAR20);
MODULE7 #(.VAR5(4'b1111)) VAR82 (.VAR56(1'b1), .VAR99(1'b1), .VAR20(VAR20));
endmodule
module MODULE17(output VAR20);
MODULE7 #(.VAR5(4'b0000)) VAR82 (.VAR56(1'b1), .VAR99(1'b1), .VAR20(VAR20));
endmodule
module MODULE6(input VAR7, VAR74, VAR35, VAR16, VAR76, VAR43, VAR26, output reg VAR2... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd_1.v | 1,928 | module MODULE2 (
VAR2,
VAR4,
VAR1 ,
VAR6
);
input VAR2;
input VAR4;
input VAR1 ;
input VAR6 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR4;
supply1 VAR1 ;
supply0 VAR6 ;
VAR3 VAR5 ();
endmodule | apache-2.0 |
sh-chris110/chris | FPGA/chris.final/db/ip/soc_design/submodules/soc_design_SystemID.v | 2,203 | module MODULE1 (
address,
VAR2,
VAR3,
VAR1
)
;
output [ 31: 0] VAR1;
input address;
input VAR2;
input VAR3;
wire [ 31: 0] VAR1;
assign VAR1 = address ? 1501038747 : 255;
endmodule | gpl-2.0 |
Nrpickle/ECE272 | Lab2_TekbotRemote/Lab2_TekbotRemote_schematic_tf.v | 1,121 | module MODULE1();
reg VAR6;
reg VAR2;
reg VAR3;
wire VAR8;
wire VAR1;
wire VAR9;
wire VAR7;
VAR4 VAR5 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR9(VAR9),
.VAR7(VAR7)
); | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_xbar_1/synth/tutorial_xbar_1.v | 19,514 | module MODULE1 (
VAR18,
VAR72,
VAR45,
VAR67,
VAR69,
VAR61,
VAR115,
VAR120,
VAR87,
VAR62,
VAR102,
VAR77,
VAR27,
VAR103,
VAR50,
VAR91,
VAR114,
VAR89,
VAR79,
VAR104,
VAR51,
VAR95,
VAR107,
VAR76,
VAR17,
VAR6,
VAR110,
VAR9,
VAR36,
VAR90,
VAR96,
VAR12,
VAR14,
VAR85,
VAR128,
VAR70,
VAR68,
VAR16,
VAR105,
VAR92,
VAR132,
VAR83,
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.v | 2,474 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR8,
VAR7 ,
VAR4 ,
VAR10 ,
VAR5 ,
VAR2 ,
VAR11
);
output VAR1 ;
output VAR3 ;
input VAR8;
input VAR7 ;
input VAR4 ;
input VAR10 ;
input VAR5 ;
input VAR2 ;
input VAR11 ;
VAR6 VAR9 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR2(VAR2),
... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9361/axi_ad9361_tx_channel.v | 14,897 | module MODULE1 (
VAR18,
VAR14,
VAR59,
VAR19,
VAR22,
VAR99,
VAR61,
VAR84,
VAR42,
VAR27,
VAR46,
VAR40,
VAR34,
VAR81,
VAR12,
VAR98,
VAR2,
VAR24,
VAR88,
VAR9,
VAR8);
parameter VAR20 = 32'h0;
parameter VAR13 = 0;
parameter VAR41 = 0;
localparam VAR69 = VAR20;
localparam VAR3 = 0;
localparam VAR67 = 1;
localparam VAR32 = 2;
... | gpl-3.0 |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s344.v | 8,880 | module MODULE2 (VAR325,VAR366,VAR211);
input VAR325,VAR211;
output VAR366;
wire VAR205,VAR59;
trireg VAR300,VAR336;
nmos VAR170 (VAR336,VAR211,VAR59);
not VAR176 (VAR205,VAR336);
nmos VAR301 (VAR300,VAR205,VAR325);
not VAR111 (VAR366,VAR300);
not VAR29 (VAR59,VAR325);
endmodule
module MODULE1(VAR283,VAR138,VAR325,VAR30... | gpl-3.0 |
jessegit/proxmark3 | fpga/lo_edge_detect.v | 2,337 | module MODULE1(
input VAR15, input VAR17,
output VAR30, output VAR23,
output VAR8, output VAR32, output VAR5, output VAR34,
input [7:0] VAR18, output VAR25,
output VAR4, input VAR20, output VAR2,
input VAR11,
output VAR7,
input VAR14,
input VAR12, input [7:0] VAR27
);
wire VAR6 = VAR20 & !VAR14;
wire VAR19 = !VAR20 & V... | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/MySource/data_path.v | 4,660 | module MODULE1(
input [15:0] VAR3,
output [31:0] VAR1,
input [31:0] VAR12,
output [63:0] VAR16,
output [63:0] VAR40,
input VAR5,
input VAR21,
input VAR30,
input VAR67,
input VAR55,
output VAR59,
output VAR38,
output VAR25,
output VAR7
);
localparam VAR61 = 2;
VAR45 #(
.VAR61(VAR61), .VAR58("7SERIES") ) VAR22 (
.VAR53(V... | gpl-2.0 |
trnewman/VT-USRP-daughterboard-drivers_python | usrp/fpga/sdr_lib/rx_buffer.v | 6,425 | module MODULE1
( input VAR34,
input VAR52,
output [15:0] VAR50,
input VAR53,
output reg VAR13,
output reg VAR15,
input VAR9,
input VAR26,
input reset, input VAR36,
input wire [3:0] VAR5,
input wire [15:0] VAR18,
input wire [15:0] VAR41,
input wire [15:0] VAR59,
input wire [15:0] VAR32,
input wire [15:0] VAR60,
input wi... | gpl-3.0 |
asicguy/gplgpu | hdl/de_temp/der_smdisp.v | 8,481 | module MODULE1
(
input VAR30,
input VAR4,
input VAR33,
input VAR3,
input VAR27,
input VAR54,
input VAR18,
input [3:0] VAR12,
input [3:0] VAR39,
input [3:0] VAR8,
input VAR35, input VAR15,
input VAR26,
output reg VAR46,
output reg VAR14, output reg VAR24, output reg VAR37, output reg VAR25,
output reg VAR34,
output reg ... | gpl-3.0 |
CatherineH/QubitekkCC | TDH/src/DE0Nano/verilog/counterselect_bb.v | 3,491 | module MODULE1 (
VAR3,
VAR5,
VAR4,
VAR1,
sel,
VAR2);
input [20:0] VAR3;
input [20:0] VAR5;
input [20:0] VAR4;
input [20:0] VAR1;
input [1:0] sel;
output [20:0] VAR2;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a.behavioral.v | 1,555 | module MODULE1 (
VAR2 ,
VAR13,
VAR11,
VAR8,
VAR15,
VAR3
);
output VAR2 ;
input VAR13;
input VAR11;
input VAR8;
input VAR15;
input VAR3;
supply1 VAR1;
supply0 VAR14;
supply1 VAR12 ;
supply0 VAR6 ;
wire VAR7 ;
wire VAR10;
or VAR4 (VAR7 , VAR11, VAR13, VAR8 );
and VAR9 (VAR10, VAR7, VAR15, VAR3);
buf VAR5 (VAR2 , VAR10 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor3/sky130_fd_sc_ms__nor3.behavioral.pp.v | 1,844 | module MODULE1 (
VAR11 ,
VAR5 ,
VAR1 ,
VAR12 ,
VAR6,
VAR8,
VAR13 ,
VAR14
);
output VAR11 ;
input VAR5 ;
input VAR1 ;
input VAR12 ;
input VAR6;
input VAR8;
input VAR13 ;
input VAR14 ;
wire VAR3 ;
wire VAR4;
nor VAR2 (VAR3 , VAR12, VAR5, VAR1 );
VAR10 VAR9 (VAR4, VAR3, VAR6, VAR8);
buf VAR7 (VAR11 , VAR4 );
endmodule | apache-2.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_pll/db/ip/niosii/submodules/niosii_jtag_uart_0.v | 16,748 | module MODULE2 (
clk,
VAR54,
VAR4,
VAR29,
VAR56,
VAR11,
VAR16
)
;
output VAR29;
output [ 7: 0] VAR56;
output VAR11;
output [ 5: 0] VAR16;
input clk;
input [ 7: 0] VAR54;
input VAR4;
wire VAR29;
wire [ 7: 0] VAR56;
wire VAR11;
wire [ 5: 0] VAR16;
always @(posedge clk)
begin
if (VAR4)
("%VAR17", VAR54);
end
assign VAR16 ... | mit |
hcabrera-/lancetfish | RTL/processing_element/des_engine/rtl/des_sbox6.v | 3,337 | module MODULE1
(
input wire [0:5] VAR1,
output reg [0:3] VAR2
);
always @(*)
case ({VAR1[0], VAR1[5]})
2'b00:
case (VAR1[1:4])
4'd0: VAR2 = 4'd12;
4'd1: VAR2 = 4'd1;
4'd2: VAR2 = 4'd10;
4'd3: VAR2 = 4'd15;
4'd4: VAR2 = 4'd9;
4'd5: VAR2 = 4'd2;
4'd6: VAR2 = 4'd6;
4'd7: VAR2 = 4'd8;
4'd8: VAR2 = 4'd0;
4'd9: VAR2 = 4'd13;... | gpl-3.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/if_stage.v | 4,119 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR9] VAR24, output wire [VAR32] VAR23, output wire VAR26, output wire VAR25, output wire [VAR9] VAR34,
input wire [VAR9] VAR8, input wire VAR17, input wire VAR20, output wire VAR29, output wire [VAR32] VAR18, output wire VAR15, output wire VAR4, output wir... | apache-2.0 |
ehliar/schematic_gui | add.v | 1,168 | module MODULE1 #(parameter VAR3 = 1) (input wire VAR2,
input wire [VAR3:0] VAR1, VAR6,
output reg [VAR3:0] VAR5,
output reg VAR4); | gpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_assembler_out.v | 2,917 | module MODULE1 #(parameter VAR21(VAR17 )
,parameter VAR21(VAR12 )
,parameter VAR21(VAR1 )
,parameter VAR28=(1 << (VAR1-1)))
(input clk
, input reset
, input VAR10
, input VAR34
, input [VAR12*VAR17-1:0] VAR15
, output VAR16
, input [VAR26(VAR19(VAR12)-1,0):0] VAR14
, input [VAR26(VAR19(VAR1)-1,0):0] VAR27
, output [VAR... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o41a/sky130_fd_sc_lp__o41a_2.v | 2,411 | module MODULE1 (
VAR9 ,
VAR6 ,
VAR12 ,
VAR8 ,
VAR7 ,
VAR3 ,
VAR10,
VAR5,
VAR1 ,
VAR11
);
output VAR9 ;
input VAR6 ;
input VAR12 ;
input VAR8 ;
input VAR7 ;
input VAR3 ;
input VAR10;
input VAR5;
input VAR1 ;
input VAR11 ;
VAR2 VAR4 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR10(... | apache-2.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/spi/spi_layer.v | 12,237 | module MODULE1
parameter VAR17 = VAR11-2,
parameter VAR47 = 2, parameter VAR13 = 8'hA7, parameter VAR29 = 3)
( input VAR60,
input VAR41,
output VAR24, output VAR7, input VAR16, output VAR10, input VAR1, input [7:0] VAR77,
output [7:0] VAR20,
output reg VAR21 = 1'b0,
output reg VAR40 = 1'b0,
input VAR23, input VAR72,
in... | lgpl-3.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/out_switch.v | 18,159 | module MODULE1(
input clk,
input reset,
output [239:0] VAR7,
input [63:0] VAR17,
input [23:0] VAR121,
input VAR139,
input VAR141,
output VAR37,
input [1:0] VAR50,
input VAR87,
input VAR130,
output VAR18,
input VAR127,
input [63:0] VAR101,
input [23:0] VAR25,
input VAR98,
input VAR133,
output VAR1,
input [1:0] VAR100,
i... | mit |
google/skywater-pdk-libs-sky130_fd_io | cells/top_sio_macro/sky130_fd_io__top_sio_macro.blackbox.v | 3,298 | module MODULE1 (
VAR11 ,
VAR26 ,
VAR3 ,
VAR9 ,
VAR25 ,
VAR38 ,
VAR29 ,
VAR14 ,
VAR24 ,
VAR30 ,
VAR33 ,
VAR13,
VAR7 ,
VAR22 ,
VAR5 ,
VAR10 ,
VAR34 ,
VAR41 ,
VAR16 ,
VAR6 ,
VAR12 ,
VAR36 ,
VAR8 ,
VAR32 ,
VAR20 ,
VAR27 ,
VAR28 ,
VAR35 ,
VAR4 ,
VAR18 ,
VAR23 ,
VAR2
);
inout VAR11 ;
inout VAR26 ;
inout VAR3 ;
inout VAR9 ;
i... | apache-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_binarization.v | 239,776 | module MODULE1(
clk ,
VAR136 ,
VAR164 ,
VAR203 ,
VAR102 ,
VAR99 ,
VAR80 ,
VAR117 ,
VAR3 , VAR157 ,
VAR86 ,
VAR217 ,
VAR234 ,
VAR55 ,
VAR28 ,
VAR36 ,
VAR161 ,
VAR173 ,
VAR222 ,
VAR49 ,
VAR249 ,
VAR195 ,
VAR286 ,
VAR51 ,
VAR17 ,
VAR97 ,
VAR216 ,
VAR9 ,
VAR31 ,
VAR228 ,
VAR158 ,
VAR243 ,
VAR213 ,
VAR171 ,
VAR48 ,
VAR283 ,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and2b/sky130_fd_sc_lp__and2b.symbol.v | 1,291 | module MODULE1 (
input VAR3,
input VAR4 ,
output VAR5
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfsbp/sky130_fd_sc_hs__sdfsbp_2.v | 2,484 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR10 ,
VAR3 ,
VAR9 ,
VAR6 ,
VAR7,
VAR2 ,
VAR4
);
input VAR1 ;
input VAR11 ;
output VAR10 ;
output VAR3 ;
input VAR9 ;
input VAR6 ;
input VAR7;
input VAR2 ;
input VAR4 ;
VAR5 VAR8 (
.VAR1(VAR1),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2)... | apache-2.0 |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/ip/Sobel/vfabric_gep.v | 3,299 | module MODULE1(VAR18, VAR5,
VAR20, VAR37, VAR3,
VAR16, VAR6, VAR21,
VAR35, VAR27, VAR29,
VAR38, VAR25);
parameter VAR34 = 32;
parameter VAR14 = 32;
parameter VAR32 = 5;
parameter VAR36 = 64;
input VAR18, VAR5;
input [VAR34-1:0] VAR20;
input VAR37;
output VAR3;
input [VAR14-1:0] VAR16;
input VAR6;
output VAR21;
output [... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/ebufn/sky130_fd_sc_lp__ebufn_2.v | 2,148 | module MODULE2 (
VAR4 ,
VAR2 ,
VAR9,
VAR7,
VAR3,
VAR1 ,
VAR8
);
output VAR4 ;
input VAR2 ;
input VAR9;
input VAR7;
input VAR3;
input VAR1 ;
input VAR8 ;
VAR5 VAR6 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4 ,
VAR2 ,
VAR9
);
output VAR4 ;... | apache-2.0 |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_register.v | 4,468 | module MODULE1(VAR6, VAR8, VAR2, VAR7, VAR1, VAR3);
parameter VAR4 = 8; parameter VAR5 = 0;
input [VAR4-1:0] VAR6;
input VAR2;
input VAR7;
input VAR1;
input VAR3;
output [VAR4-1:0] VAR8;
reg [VAR4-1:0] VAR8;
always @ (posedge VAR7 or posedge VAR1)
begin
if(VAR1)
VAR8<=VAR5;
end
else
if(VAR3)
VAR8<=VAR5;
else
if(VAR2) V... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu9t5v0__aoi221_1.behavioral.v | 3,306 | module MODULE1( VAR7, VAR8, VAR6, VAR9, VAR2, VAR4 );
input VAR4, VAR2, VAR8, VAR7, VAR6;
output VAR9;
VAR1 VAR5(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR9(VAR9),.VAR2(VAR2),.VAR4(VAR4));
VAR1 VAR3(.VAR7(VAR7),.VAR8(VAR8),.VAR6(VAR6),.VAR9(VAR9),.VAR2(VAR2),.VAR4(VAR4)); | apache-2.0 |
JakeMercer/mac | MAC/rtl/mac/fifo/fifo.v | 2,777 | module MODULE1
parameter VAR18 = 8,
parameter VAR7 = 12
)
(
input wire reset,
output reg [VAR7:0] VAR9,
output reg VAR13,
input wire [VAR18-1:0] VAR19,
input wire VAR3,
input wire VAR16,
input wire VAR14,
input wire VAR2,
output reg [VAR7-1:0] VAR6,
input wire VAR12,
input wire [VAR7-1:0] VAR17,
output reg [VAR18-1:0] ... | mit |
scalable-networks/ext | uhd/fpga/usrp2/timing/timer.v | 1,480 | module MODULE1
(input VAR14, input VAR15,
input VAR3, input VAR11, input [2:0] VAR13,
input VAR12, input [31:0] VAR4, output [31:0] VAR6, output VAR10,
input VAR5, input [31:0] VAR2,
output VAR9 );
reg [31:0] VAR7;
always @(posedge VAR14)
VAR7 <= VAR2;
assign VAR10 = VAR11;
reg [31:0] VAR1;
reg VAR8;
always @(posedge V... | gpl-2.0 |
h-j-13/MyNote | Programming language/Verilog/sync_FIFO/BackUp/fifo/fifo.v | 7,962 | module MODULE1(VAR10, reset, read, write, VAR31, VAR11, VAR3, VAR22, VAR29 );
parameter VAR17 = 128; parameter VAR6 = 7; parameter VAR28 = 4; parameter VAR15 = 7'b1111111;
parameter
VAR32 = 7'b0000001,
VAR23 = 7'b1001111,
VAR24 = 7'b0010010,
VAR27 = 7'b1111001,
VAR1 = 7'b1001100,
VAR4 = 7'b0100100,
VAR7 = 7'b0100000,
V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and2b/sky130_fd_sc_ms__and2b.blackbox.v | 1,270 | module MODULE1 (
VAR3 ,
VAR5,
VAR6
);
output VAR3 ;
input VAR5;
input VAR6 ;
supply1 VAR7;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/xor_32.v | 2,013 | module MODULE1(
input [31:0] VAR1, input [31:0] VAR2,
output [31:0] out );
assign out[0] = VAR1[0] ^ VAR2[0];
assign out[1] = VAR1[1] ^ VAR2[1];
assign out[2] = VAR1[2] ^ VAR2[2];
assign out[3] = VAR1[3] ^ VAR2[3];
assign out[4] = VAR1[4] ^ VAR2[4];
assign out[5] = VAR1[5] ^ VAR2[5];
assign out[6] = VAR1[6] ^ VAR2[6];
... | gpl-3.0 |
phasza/axi_spi_if | regs_mod.v | 4,867 | module MODULE1 (
input VAR2, input VAR13,
input VAR8,
input VAR14,
input VAR1,
input VAR11,
output [31:0] VAR5,
output [31:0] VAR9,
output [31:0] VAR4,
input [31:0] VAR12,
input VAR15,
input [1:0] VAR6
);
reg [11:0] VAR3;
always @ (posedge VAR2, negedge VAR13)
begin
if (!VAR13)
begin
VAR3 <= 32'd1;
end
else
if (VAR15 &... | gpl-3.0 |
jotego/jt12 | hdl/alt/eg_mux.v | 3,683 | module MODULE1(
input clk,
input VAR5,
input rst,
input [14:0] VAR15,
input [2:0] VAR2,
input [5:0] VAR8,
output reg [2:0] VAR6,
output reg [5:0] VAR14,
output reg [2:0] VAR7,
output reg VAR4
);
localparam VAR10=3'd0, VAR1=3'd1, VAR12=3'd2, VAR3=3'd7, VAR13=3'd3;
wire VAR20;
reg [3:0] VAR18;
always @(*) begin
VAR18 = (... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/endpoint_blk_plus_v1_14.v | 19,617 | module MODULE1 # (
parameter VAR16 = "VAR174",
parameter VAR88 = 1,
parameter VAR173 = 8,
parameter VAR114 = 1,
parameter VAR127 = 0,
parameter VAR46 = 64,
parameter VAR196 = 8,
parameter VAR76 = 4,
parameter VAR166 = 7,
parameter VAR178 = 8,
parameter VAR128 = 12,
parameter VAR149 = 32,
parameter VAR117 = 10,
paramete... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22o/sky130_fd_sc_hd__a22o.symbol.v | 1,363 | module MODULE1 (
input VAR8,
input VAR4,
input VAR2,
input VAR1,
output VAR6
);
supply1 VAR9;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/models/IBUFG.v | 1,895 | module MODULE1 (VAR7, VAR8);
parameter VAR6 = "VAR5";
parameter VAR3 = "0";
parameter VAR4 = "VAR2";
output VAR7;
input VAR8;
buf VAR1 (VAR7, VAR8); | gpl-2.0 |
vipinkmenon/scas | hw/fpga/source/memory_if/mig_7series_v1_8_arb_row_col.v | 18,940 | module MODULE1 #
(
parameter VAR89 = 100,
parameter VAR39 = "1T",
parameter VAR80 = 5,
parameter VAR76 = "VAR64",
parameter VAR78 = 4,
parameter VAR74 = 2,
parameter VAR19 = 37500, parameter VAR4 = 12500, parameter VAR38 = 6 )
(
VAR70, VAR59, VAR104, VAR35, VAR51, VAR79,
VAR75, VAR15, VAR8,
VAR37, VAR29, VAR9, VAR25, V... | mit |
ShepardSiegel/ocpi | coregen/pcie_4243_trn_v5_gtx_x8_125/source/pcie_blk_cf_arb.v | 35,528 | module MODULE1
(
input wire clk,
input wire VAR40,
input [7:0] VAR52,
input [4:0] VAR95,
input [2:0] VAR11,
input [15:0] VAR20,
input [31:0] VAR58,
input [31:0] VAR23,
input VAR99,
input VAR112,
input VAR34,
input VAR90,
input VAR86,
input [49:0] VAR28,
input [49:0] VAR19,
output reg [49:0] VAR46 = 0,
output reg VAR24 ... | lgpl-3.0 |
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