repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
asicguy/gplgpu | hdl/de_temp/der_rdmux.v | 10,306 | module MODULE1
(
input [8:2] VAR47, input [1:0] VAR26, input [1:0] VAR6, input [4:0] VAR12, input VAR21, input [14:0] VAR2, input [31:0] VAR19, input [31:0] VAR52, input [11:0] VAR27, input [11:0] VAR20, input [3:0] VAR23, input [3:0] VAR8, input [4:0] VAR38, input [3:0] VAR22, input [2:0] hdf1, input [2:0] VAR24, inpu... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/settings_bus_crossclock.v | 1,563 | module MODULE1
(input VAR5, input VAR7, input VAR4, input [7:0] VAR16, input [31:0] VAR9,
input VAR10, input VAR14, output VAR8, output [7:0] VAR20, output [31:0] VAR11, input VAR18);
wire VAR17, VAR15;
VAR13 VAR19
(.rst(VAR7),
.VAR2(VAR5), .din({VAR16,VAR9}), .VAR12(VAR4 & ~VAR17), .VAR17(VAR17),
.VAR1(VAR10), .dout({... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfsbp/sky130_fd_sc_ls__sdfsbp.pp.symbol.v | 1,523 | module MODULE1 (
input VAR8 ,
output VAR2 ,
output VAR6 ,
input VAR3,
input VAR9 ,
input VAR11 ,
input VAR1 ,
input VAR7 ,
input VAR5 ,
input VAR4 ,
input VAR10
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32oi/sky130_fd_sc_lp__a32oi_4.v | 2,483 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR11 ,
VAR12,
VAR2,
VAR1 ,
VAR9
);
output VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR11 ;
input VAR12;
input VAR2;
input VAR1 ;
input VAR9 ;
VAR7 VAR10 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR11(VAR11),
.VAR12(V... | apache-2.0 |
balanx/laotzu | RTL/LTZ_CDCF.v | 1,846 | module MODULE1 #(
parameter VAR3 = 1,
parameter [VAR3 -1:0] VAR1 = {VAR3{1'b0}}
) (
input VAR5 ,
input clk ,
input [VAR3 -1:0] din ,
output reg [VAR3 -1:0] dout
);
reg [VAR3 -1:0] VAR6 ;
reg [1:0] state;
always @(posedge clk or negedge VAR5)
if (!VAR5)
VAR6 <= VAR1;
else
VAR6 <= din;
always @(posedge clk or negedge VAR... | apache-2.0 |
jeremycw/tetris-verilog | tetris_vga.v | 6,179 | module MODULE2(input clk, output VAR5, output VAR7, output VAR10,
input VAR13, output[9:0] VAR11, output[9:0] VAR1, input rst);
reg[9:0] VAR9, VAR15;
assign VAR5 = VAR9 < 96 ? 1'b0 : 1'b1;
assign VAR7 = VAR15 < 2 ? 1'b0 : 1'b1;
assign VAR10 = VAR5 & VAR7;
assign VAR11 = VAR9 - 10'd144; assign VAR1 = VAR15 - 10'd34;
alw... | mit |
jefg89/proyecto_final_prototipado | ProyectoFinal/db/ip/SOC/submodules/SOC_NIOS_II_jtag_debug_module_sysclk.v | 6,808 | module MODULE1 (
clk,
VAR5,
VAR3,
VAR13,
VAR19,
VAR10,
VAR24,
VAR16,
VAR6,
VAR23,
VAR9,
VAR1,
VAR7,
VAR22,
VAR27,
VAR29,
VAR12,
VAR30,
VAR15
)
;
output [ 37: 0] VAR10;
output VAR24;
output VAR16;
output VAR6;
output VAR23;
output VAR9;
output VAR1;
output VAR7;
output VAR22;
output VAR27;
output VAR29;
output VAR12;
ou... | gpl-2.0 |
LordRafa/Sobel-FPGA | SISSources/V/Sobel_cache.v | 5,083 | module MODULE1 (
input clk,
input rst,
input VAR7,
input [VAR60-1:0] VAR36,
input [13:0] VAR10,
output wire [12:0] VAR22,
input VAR46,
output wire [ 7:0] VAR13,
output wire [VAR60-1:0] VAR34,
input VAR35,
input VAR54,
output wire [VAR5-1:0] VAR26,
output wire VAR29,
input [VAR20-1:0] VAR8,
output wire [VAR12-1:0] VAR37... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/counter.v | 3,260 | module MODULE1
parameter VAR9 = 10,
parameter VAR10 = 0)
(
input VAR4,
input VAR2,
input VAR1,
output [VAR8(VAR3+1)-1:0] VAR5
);
wire VAR7;
reg [VAR8(VAR3+1)-1:0] VAR11;
reg [VAR8(VAR3+1)-1:0] VAR6;
assign VAR7 = VAR1 & (VAR9 > VAR6);
assign VAR5 = VAR6;
always @(posedge VAR4) begin
if(VAR2) begin
VAR6 <= VAR10;
end el... | gpl-3.0 |
jefflieu/recon | hw/recon_2/recon_2_top.v | 4,251 | module MODULE1 #(parameter VAR4 = 32) (
input VAR58,
input VAR14,
inout [ VAR4-1:0] VAR43,
output VAR21,
input VAR3,
output VAR7,
output [11:0] VAR52,
output [1:0] VAR39,
output VAR5,
output VAR46,
output VAR15,
inout [15:0] VAR41,
output [1:0] VAR28,
output VAR34,
output VAR56
);
wire [VAR4-1:0] VAR6;
wire [VAR4-1:0] ... | gpl-3.0 |
jyzhiyu/USB2SPDIF | board/hdl/worklib/atsam3u1cb#2dau/entity/verilog.v | 2,987 | module \VAR103-VAR49 (VAR80, VAR1, VAR16, VAR112, VAR121, VAR59, VAR17, VAR92,
VAR106, VAR57, VAR41, VAR31, VAR104, VAR99, VAR108, VAR91,
VAR38, VAR98, \VAR88/VAR70 , \VAR128/VAR53 , \VAR125/VAR54 ,
\VAR36/VAR85 , \VAR95/VAR72 , \VAR34/VAR20 , \VAR94/VAR117 ,
\VAR55/VAR78 , \VAR113/VAR83 , \VAR119/VAR45 , \VAR35/VAR110... | mit |
xuefei1/ElectronicEngineControl | db/ip/niosII_system/submodules/niosII_system_generic_tristate_controller_0.v | 28,062 | module MODULE1 #(
parameter VAR15 = 22,
parameter VAR13 = 8,
parameter VAR57 = 1,
parameter VAR8 = 160,
parameter VAR40 = 160,
parameter VAR68 = 40,
parameter VAR72 = 40,
parameter VAR10 = 2,
parameter VAR16 = 0,
parameter VAR50 = 2,
parameter VAR7 = 1,
parameter VAR1 = 1,
parameter VAR55 = 1,
parameter VAR12 = 1,
para... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/ctu/rtl/ctu_dft.v | 29,369 | module MODULE1 (
VAR6, VAR55, VAR141, VAR28, VAR29,
VAR12, VAR2, VAR223, VAR103, VAR11,
VAR59, VAR160, VAR179,
VAR117, VAR72,
VAR203, VAR208,
VAR76, VAR206, VAR107,
VAR15, VAR145, VAR108,
VAR171, VAR35, VAR98, VAR192, VAR92,
VAR60, VAR123, VAR110, VAR112,
VAR114, VAR1, VAR212,
VAR127, VAR180, VAR22,
VAR143, VAR118, VAR... | gpl-2.0 |
cpulabs/mist1032isa | src/core/execute/execute_mul.v | 1,128 | module MODULE1(
input wire [4:0] VAR2,
input wire [31:0] VAR3,
input wire [31:0] VAR5,
output wire [31:0] VAR11,
output wire [4:0] VAR13
);
wire [63:0] VAR7;
wire VAR1;
wire VAR8;
wire VAR18;
wire VAR14;
wire VAR12;
wire VAR16;
wire VAR9;
wire VAR6;
wire VAR17;
wire VAR10;
assign VAR7 = VAR3 * VAR5;
assign VAR1 = VAR7[... | bsd-2-clause |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_hdmi_tx/axi_hdmi_tx.v | 12,186 | module MODULE1 (
VAR128,
VAR178,
VAR5,
VAR170,
VAR15,
VAR143,
VAR86,
VAR162,
VAR82,
VAR124,
VAR188,
VAR98,
VAR67,
VAR101,
VAR88,
VAR50,
VAR61,
VAR183,
VAR105,
VAR142,
VAR136,
VAR156,
VAR100,
VAR172,
VAR104,
VAR169,
VAR64,
VAR179,
VAR155,
VAR160,
VAR93,
VAR4,
VAR66,
VAR108,
VAR145,
VAR54,
VAR70,
VAR122,
VAR132,
VAR111,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2_4.v | 2,097 | module MODULE2 (
VAR4 ,
VAR8 ,
VAR9 ,
VAR7,
VAR2,
VAR1 ,
VAR5
);
output VAR4 ;
input VAR8 ;
input VAR9 ;
input VAR7;
input VAR2;
input VAR1 ;
input VAR5 ;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR4,
VAR8,
VAR9
);
output VAR4;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/mux2/sky130_fd_sc_ls__mux2.pp.symbol.v | 1,325 | module MODULE1 (
input VAR4 ,
input VAR2 ,
output VAR1 ,
input VAR5 ,
input VAR7 ,
input VAR3,
input VAR6,
input VAR8
);
endmodule | apache-2.0 |
JY-Kim/CA2016 | Sources/ProcessorControl.v | 1,893 | module MODULE1
(
input [5:0] VAR18,
input VAR3,
input [5:0] VAR22,
output wire [1:0] VAR19,
output wire VAR8,
output wire [1:0] VAR21,
output wire VAR10,
output wire VAR11,
output wire VAR16,
output wire VAR14,
output wire [1:0] VAR2,
output wire VAR5,
output wire VAR20,
output wire VAR15
);
wire VAR9;
wire VAR13;
wire... | mit |
golfit/QcmPhaseDelayBoard | PosEdgeDelay.v | 2,398 | module MODULE1(clk, VAR5, VAR4, VAR7, VAR3);
parameter VAR8=11;
input clk, VAR5;
input [VAR8-1:0] VAR4;
input VAR7; output VAR3;
reg VAR2, VAR9;
reg [VAR8-1:0] VAR1;
reg VAR6; | mit |
olajep/oh | src/adi/hdl/library/axi_clkgen/axi_clkgen.v | 6,878 | module MODULE1 #(
parameter VAR98 = 0,
parameter VAR12 = 0,
parameter VAR100 = 0,
parameter real VAR81 = 5.000,
parameter real VAR57 = 5.000,
parameter integer VAR105 = 11,
parameter real VAR88 = 49.000,
parameter real VAR99 = 6.000,
parameter real VAR14 = 0.000,
parameter integer VAR101 = 6,
parameter real VAR29 = 0.0... | mit |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/backend/rtl/verilog/ddr_ctrl_ip/ddr_ctrl_ip_phy_alt_mem_phy_pll.v | 22,658 | module MODULE1 (
VAR129,
VAR42,
VAR66,
VAR89,
VAR99,
VAR110,
VAR115,
VAR79,
VAR50,
VAR137,
VAR34,
VAR75,
VAR98);
input VAR129;
input VAR42;
input [2:0] VAR66;
input VAR89;
input VAR99;
input VAR110;
output VAR115;
output VAR79;
output VAR50;
output VAR137;
output VAR34;
output VAR75;
output VAR98;
tri0 VAR129;
tri0 [2:... | gpl-2.0 |
gbraad/minimig-de1 | rtl/ctrl/ctrl_regs.v | 14,047 | module MODULE1 #(
parameter VAR52 = 22, parameter VAR62 = 32, parameter VAR64 = VAR62/8 )(
input wire clk,
input wire rst,
input wire [VAR52-1:0] VAR45,
input wire VAR16,
input wire VAR66,
input wire [VAR64-1:0] sel,
input wire [VAR62-1:0] VAR42,
output reg [VAR62-1:0] VAR14,
output reg ack,
output wire VAR74,
output r... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/tx_spw.v | 3,266 | module MODULE1 (
input VAR12,
input [8:0] VAR2,
input VAR13,
input [7:0] VAR31,
input VAR25,
input VAR22,
input VAR18,
input VAR6,
input VAR10,
input VAR16,
output VAR27,
output VAR36,
output VAR24,
output VAR4
);
wire [13:0] VAR15;
wire [5:0] VAR7;
wire VAR5;
wire [8:0] VAR11;
wire [8:0] VAR19;
wire VAR33;
wire VAR34;... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a21boi/sky130_fd_sc_lp__a21boi.functional.pp.v | 2,172 | module MODULE1 (
VAR10 ,
VAR17 ,
VAR8 ,
VAR14,
VAR4,
VAR1,
VAR13 ,
VAR15
);
output VAR10 ;
input VAR17 ;
input VAR8 ;
input VAR14;
input VAR4;
input VAR1;
input VAR13 ;
input VAR15 ;
wire VAR18 ;
wire VAR16 ;
wire VAR11 ;
wire VAR5;
not VAR7 (VAR18 , VAR14 );
and VAR12 (VAR16 , VAR17, VAR8 );
nor VAR9 (VAR11 , VAR18, V... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/Approximate_Adders/integracion_fisica/front_end/db/GeAr_N16_R4_P8_syn.v | 5,999 | module MODULE1 ( VAR55, VAR123, VAR44 );
input [15:0] VAR55;
input [15:0] VAR123;
output [16:0] VAR44;
wire VAR69, VAR148, VAR201, VAR101, VAR66, VAR68, VAR192, VAR10, VAR222, VAR67, VAR153, VAR60, VAR25, VAR172, VAR205,
VAR164, VAR211, VAR141, VAR134, VAR35, VAR180, VAR36, VAR218, VAR199, VAR98, VAR133, VAR71, VAR46, ... | gpl-3.0 |
csturton/wirepatch | system/hardware/cores/ethmac/eth_outputcontrol.v | 6,095 | module MODULE1(VAR15, VAR9, VAR1, VAR3, VAR7, VAR8, VAR6, VAR10, VAR2, VAR16);
parameter VAR12 = 1;
input VAR15; input VAR9; input VAR8; input VAR6; input VAR1; input VAR3; input [6:0] VAR7; input VAR10;
output VAR2; output VAR16;
wire VAR14;
reg VAR11;
reg VAR13;
reg VAR16;
reg VAR4;
reg VAR5;
reg VAR2;
assign VAR14 =... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_032bits.v | 1,917 | module MODULE1 (
clk,
VAR9, VAR24, VAR2, VAR19, VAR28, VAR21, VAR8, VAR30,
sum,
);
input clk;
input [VAR27+0-1:0] VAR9, VAR24, VAR2, VAR19, VAR28, VAR21, VAR8, VAR30;
output [VAR27 :0] sum;
reg [VAR27 :0] sum;
wire [VAR27+3-1:0] VAR16;
wire [VAR27+2-1:0] VAR5, VAR3;
wire [VAR27+1-1:0] VAR26, VAR6, VAR25, VAR7;
reg [VAR... | mit |
audiocircuit/NCSU-Low-Power-RFID | rfid-verilog/tag/preamble.v | 2,410 | module MODULE1(reset, clk, VAR7, VAR2, out, VAR6, VAR4);
input clk, reset, VAR2;
input [1:0] VAR7;
output out, VAR6, VAR4;
reg out, VAR4, VAR6;
reg [5:0] VAR1;
wire [5:0] VAR3, VAR5;
assign VAR3 = (VAR2 == 6'd1) ? (VAR1) : (VAR1 + 6'd12);
assign VAR5 = (VAR3 > 6'd25) ? (VAR1) : (VAR1 + 6'd1);
always @ (posedge clk or p... | gpl-3.0 |
iAklis/teoca | EXPR7/MAIN.v | 1,099 | module MODULE1(
input [0:0] VAR2,
input [0:0] rst,
output [5:0] address,
output [31:0] VAR6
);
wire [31:0] VAR1;
wire [5:0] VAR3;
reg [31:0] VAR8;
wire [31:0] VAR4;
VAR7 VAR5 (
.VAR2(VAR2), .VAR3(VAR3), .VAR1(VAR1) );
assign VAR4 = VAR8 + 4;
assign VAR6 = VAR1;
assign VAR3 = VAR8[7:2];
assign address = VAR8[7:2];
alway... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and3/sky130_fd_sc_lp__and3_4.v | 2,164 | module MODULE2 (
VAR10 ,
VAR6 ,
VAR1 ,
VAR3 ,
VAR9,
VAR4,
VAR8 ,
VAR7
);
output VAR10 ;
input VAR6 ;
input VAR1 ;
input VAR3 ;
input VAR9;
input VAR4;
input VAR8 ;
input VAR7 ;
VAR2 VAR5 (
.VAR10(VAR10),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE... | apache-2.0 |
jairov4/puj-ca-de1-audio-pump | ip/i2c_opencores/i2c_master_byte_ctrl.v | 10,549 | module MODULE1 (
clk, rst, VAR26, VAR34, VAR16, VAR8, VAR15, read, write, VAR41, din,
VAR12, VAR25, dout, VAR40, VAR3, VAR28, VAR5, VAR23, VAR22, VAR35, VAR38 );
input clk; input rst; input VAR26; input VAR34;
input [15:0] VAR16;
input VAR8;
input VAR15;
input read;
input write;
input VAR41;
input [7:0] din;
output VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2i/sky130_fd_sc_hs__mux2i.pp.symbol.v | 1,314 | module MODULE1 (
input VAR6 ,
input VAR3 ,
output VAR4 ,
input VAR2 ,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2b/sky130_fd_sc_hd__nor2b.pp.blackbox.v | 1,322 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR4,
VAR7,
VAR2 ,
VAR1
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR4;
input VAR7;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
m-labs/milkymist | cores/memcard/rtl/memcard.v | 5,095 | module MODULE1 #(
parameter VAR29 = 4'h0
) (
input VAR23,
input VAR21,
input [13:0] VAR38,
input VAR40,
input [31:0] VAR39,
output reg [31:0] VAR27,
inout [3:0] VAR15,
inout VAR33,
output VAR32
);
reg [10:0] VAR18;
reg VAR35;
reg VAR12;
reg VAR30;
reg VAR3;
reg VAR5;
reg [7:0] VAR25;
reg VAR1;
reg VAR10;
reg VAR6;
reg ... | lgpl-3.0 |
benreynwar/fpga-sdrlib | verilog/message/qa_message_stream_combiner_bits.v | 1,448 | module MODULE1
parameter VAR12 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR12-1:0] VAR10,
input wire VAR21,
output wire [VAR12-1:0] VAR1,
output wire VAR20
);
reg VAR13;
reg [VAR12-1:0] VAR15;
wire VAR3;
wire [VAR12-1:0] VAR6;
wire VAR18;
wire VAR16;
always @ (posedge clk)
if (reset)
begin
VAR13 <= 1'b0;
... | mit |
cliffordwolf/picorv32 | scripts/vivado/synth_area_top.v | 3,287 | module MODULE3 (
input clk, VAR25,
output VAR4,
output VAR1,
input VAR30,
output [31:0] VAR16,
output [31:0] VAR15,
output [ 3:0] VAR14,
input [31:0] VAR23
);
VAR2 #(
.VAR12(0),
.VAR13(1),
.VAR18(0),
.VAR20(0),
.VAR17(0)
) VAR2 (
.clk (clk ),
.VAR25 (VAR25 ),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR30(VAR30),
.VAR16 (VAR16 ),
.V... | isc |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/or2/gf180mcu_fd_sc_mcu9t5v0__or2_2.behavioral.pp.v | 1,239 | module MODULE1( VAR2, VAR8, VAR4, VAR7, VAR1 );
input VAR2, VAR8;
inout VAR7, VAR1;
output VAR4;
VAR5 VAR6(.VAR2(VAR2),.VAR8(VAR8),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1));
VAR5 VAR3(.VAR2(VAR2),.VAR8(VAR8),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.symbol.v | 1,256 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/UM_OPENFLOW/bv-288/bv_count.v | 1,039 | module MODULE1(
reset,
clk,
VAR4,
VAR2,
VAR7,
VAR6,
VAR3,
VAR8
);
parameter VAR1 = 64;
parameter VAR9 = 6;
parameter VAR5 = 1;
parameter VAR10 = 1;
input reset;
input clk;
input VAR4;
input [VAR1-1:0] VAR2;
input [VAR9-1:0] VAR7;
output reg VAR6;
output reg [VAR1-1:0] VAR3;
output reg [VAR9-1:0] VAR8;
always @ (posedge... | apache-2.0 |
mfkiwl/parallella-platform | hdl/ewrapper_link_receiver.v | 6,937 | module MODULE1 (
VAR29, VAR10, VAR27, VAR23,
VAR6, VAR13, VAR34,
VAR11, VAR32, VAR26,
reset, VAR4, VAR19, VAR1, VAR16,
VAR39
);
input reset;
input [63:0] VAR4; input VAR19; input [7:0] VAR1; input VAR16;
input VAR39;
output VAR29; output VAR10;
output VAR27;
output VAR23;
output VAR6;
output [1:0] VAR13;
output [3:0] V... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPM_Toggle_IDLE_DDR100.v | 4,469 | module MODULE1
(
parameter VAR16 = 4
)
(
VAR4 ,
VAR9 ,
VAR10 ,
VAR14 ,
VAR2 ,
VAR19 ,
VAR6 ,
VAR18 ,
VAR11 ,
VAR17 ,
VAR7 ,
VAR1 ,
VAR13 ,
VAR8 ,
VAR15 ,
VAR5 ,
VAR12 ,
VAR3
);
input VAR4 ;
output VAR9 ;
output VAR10 ;
output VAR14 ;
output VAR2 ;
output VAR19 ;
output [2:0] VAR6 ;
output VAR18 ;
output [4:0] VAR11 ;
o... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/sram_fifo/sram_fifo_core.v | 8,707 | module MODULE1 #(
parameter VAR18 = 21'h100000,
parameter VAR63 = 95, parameter VAR23 = 5 ) (
input wire VAR67,
input wire VAR55,
input wire [15:0] VAR45,
input wire [7:0] VAR7,
input wire VAR6,
input wire VAR10,
output reg [7:0] VAR24,
output wire [19:0] VAR58,
inout wire [15:0] VAR50,
output wire VAR51,
output wire V... | bsd-3-clause |
FelixWinterstein/LEAP-HLS | filtering_algorithm/wrappers/verilog/fifo.v | 2,161 | module MODULE1
parameter VAR7 = 8,
parameter VAR9 = 3
)
(
input clk,
input VAR12,
input [VAR7-1:0] din,
input VAR8,
input VAR5,
output reg [VAR7-1:0] dout,
output VAR4,
output VAR6,
output reg valid
);
parameter VAR10 = 2**VAR9;
reg [VAR9-1 : 0] VAR1;
reg [VAR9-1 : 0] VAR3;
reg [VAR7-1 : 0] VAR2[VAR10-1 : 0]; reg [VAR9... | bsd-3-clause |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/fpu/FPU_Interface_1v1.v | 9,004 | module MODULE1 #(parameter VAR87 = 64, VAR11 = 11, VAR37 = 52, VAR79 = 55, VAR82 = 6)
(
input wire clk,
input wire rst,
input wire VAR93,
input wire VAR99,
input wire [2:0] VAR3,
input wire [1:0] VAR39,
input wire [VAR87-1:0] VAR83,
input wire [VAR87-1:0] VAR89,
input wire [1:0] VAR73,
output wire VAR41,
output wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd1/sky130_fd_sc_hs__dlygate4sd1.pp.blackbox.v | 1,256 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
lee-dohm/atom-linguist | samples/Verilog/button_debounce.v | 3,334 | module MODULE1
(
input clk, input VAR10, input VAR9, output reg VAR6 );
parameter
VAR11 = 66000000,
VAR7 = 2;
localparam
VAR3 = VAR11 / VAR7,
VAR8 = 0,
VAR4 = 1,
VAR5 = 2;
reg [1:0] state, VAR1;
reg [25:0] VAR2;
always @ (posedge clk or negedge VAR10)
state <= (!VAR10) ? VAR8 : VAR1;
always @ (posedge clk or negedge VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dlxtp/sky130_fd_sc_hvl__dlxtp.blackbox.v | 1,296 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR2
);
output VAR6 ;
input VAR3 ;
input VAR2;
supply1 VAR1;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
merckhung/zet | cores/fmlarb/rtl/fmlarb.v | 5,340 | module MODULE1 #(
parameter VAR36 = 26
) (
input VAR19,
input VAR33,
input [VAR36-1:0] VAR32,
input VAR13,
input VAR1,
output VAR48,
input [1:0] VAR25,
input [15:0] VAR23,
output [15:0] VAR46,
input [VAR36-1:0] VAR30,
input VAR24,
input VAR9,
output VAR27,
input [1:0] VAR39,
input [15:0] VAR16,
output [15:0] VAR11,
inp... | gpl-3.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_fifo_adapter.v | 11,662 | module MODULE1 #
(
parameter VAR42 = 4096,
parameter VAR22 = 8,
parameter VAR1 = (VAR22>8),
parameter VAR7 = (VAR22/8),
parameter VAR28 = 8,
parameter VAR41 = (VAR28>8),
parameter VAR3 = (VAR28/8),
parameter VAR32 = 0,
parameter VAR9 = 8,
parameter VAR4 = 0,
parameter VAR27 = 8,
parameter VAR25 = 1,
parameter VAR10 = 1... | mit |
glennchid/font5-firmware | src/verilog/synthesis/uart_unload.v | 1,303 | module MODULE1 #(parameter VAR4 = 8, VAR6 = 13) (
input rst,
input clk,
input VAR5,
input [VAR4-1:0] din,
output reg signed [VAR6-1:0] dout,
output reg VAR2
);
reg VAR7 = 1'b0;
reg [VAR6-2:0] VAR1 = {VAR4-1{1'b0}};
always @(posedge clk) begin
if (rst) begin
VAR2 <= 1'b0;
VAR7 <= 1'b0;
VAR1 <= {VAR4-1{1'b0}};
dout <= {V... | gpl-3.0 |
DigitalLogicSummerTerm2015/mips-cpu-single-cycle | CPU.v | 3,380 | module MODULE1(dout,VAR7,VAR20,VAR69,din,clk,reset);
output dout;
output [7:0]VAR7;
output [11:0]VAR20;
input [7:0]VAR69;
input din;
input clk;
input reset;
wire [31:0]VAR33;
wire [31:0]VAR31;
wire [25:0]VAR40;
parameter VAR64 = 32'h80000004;
parameter VAR15 = 32'h80000008;
wire [31:0]VAR63;
wire [2:0]VAR57;
wire [31:0... | mit |
tnsrb93/G1_RealTimeDCTSteganography | src/ips/decoder_ip_prj/decoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_16kb/dcfifo_32in_32out_16kb_stub.v | 1,551 | module MODULE1(rst, VAR3, VAR2, din, VAR7, VAR1, dout, VAR5, VAR6, VAR4)
;
input rst;
input VAR3;
input VAR2;
input [31:0]din;
input VAR7;
input VAR1;
output [31:0]dout;
output VAR5;
output VAR6;
output [1:0]VAR4;
endmodule | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_4.functional.v | 1,164 | module MODULE1( VAR2, VAR14, VAR13, VAR10 );
input VAR2, VAR14;
output VAR13, VAR10;
and VAR9( VAR13, VAR2, VAR14 );
wire VAR6;
not VAR1( VAR6, VAR14 );
wire VAR4;
and VAR5( VAR4, VAR6, VAR2 );
wire VAR7;
not VAR12( VAR7, VAR2 );
wire VAR3;
and VAR11( VAR3, VAR7, VAR14 );
or VAR8( VAR10, VAR4, VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p.pp.symbol.v | 1,344 | module MODULE1 (
input VAR8 ,
output VAR9 ,
input VAR6 ,
input VAR2,
input VAR3,
input VAR4 ,
input VAR1 ,
input VAR5 ,
input VAR7
);
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_7x_v1_8_pipe_reset.v | 16,549 | module MODULE1 #
(
parameter VAR42 = "VAR24", parameter VAR32 = "VAR60", parameter VAR36 = "VAR21", parameter VAR57 = 1, parameter VAR53 = 6'd63, parameter VAR64 = 1
)
(
input VAR30,
input VAR47,
input VAR16,
input VAR17,
input [VAR57-1:0] VAR54,
input VAR20,
input [VAR57-1:0] VAR66,
input [VAR57-1:0] VAR51,
input VAR4... | mit |
travisg/cpu | rtl/cpu/stage2_decode.v | 5,034 | module MODULE1(
input VAR21,
input VAR7,
input [31:0] VAR22,
input [29:0] VAR13,
input VAR15,
input VAR12,
input [4:0] VAR35,
input [31:0] VAR32,
output VAR9,
output reg [1:0] VAR31,
output reg VAR1,
output reg VAR39,
output reg [3:0] VAR36,
output reg [31:0] VAR5,
output reg [31:0] VAR20,
output [31:0] VAR2,
output re... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31a/sky130_fd_sc_hd__o31a.functional.pp.v | 2,015 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR6 ,
VAR8 ,
VAR14 ,
VAR4,
VAR1,
VAR9 ,
VAR3
);
output VAR12 ;
input VAR5 ;
input VAR6 ;
input VAR8 ;
input VAR14 ;
input VAR4;
input VAR1;
input VAR9 ;
input VAR3 ;
wire VAR2 ;
wire VAR10 ;
wire VAR16;
or VAR17 (VAR2 , VAR6, VAR5, VAR8 );
and VAR11 (VAR10 , VAR2, VAR14 );
VAR13 VAR7 (V... | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/single_cycle_cpu.v | 9,598 | module MODULE1(
input clk, input VAR4,
input [ 4:0] VAR31,
input [31:0] VAR89,
output [31:0] VAR49,
output [31:0] VAR85,
output [31:0] VAR9,
output [31:0] VAR7
);
reg [31:0] VAR23;
wire [31:0] VAR90;
wire [31:0] VAR67;
wire [31:0] VAR93;
wire VAR73;
assign VAR67[31:2] = VAR23[31:2] + 1'b1;
assign VAR67[1:0] = VAR23[1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.behavioral.pp.v | 1,936 | module MODULE1 (
VAR8 ,
VAR7 ,
VAR6 ,
VAR5,
VAR11,
VAR9 ,
VAR15
);
output VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR5;
input VAR11;
input VAR9 ;
input VAR15 ;
wire VAR2 ;
wire VAR12 ;
wire VAR4;
not VAR3 (VAR2 , VAR6 );
or VAR1 (VAR12 , VAR2, VAR7 );
VAR14 VAR13 (VAR4, VAR12, VAR5, VAR11);
buf VAR10 (VAR8 , VAR4 );
end... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/recv_credit_flow_ctrl.v | 4,918 | module MODULE1
(
input VAR6,
input VAR14,
input [2:0] VAR15, input [11:0] VAR13, input [7:0] VAR9, input VAR12, input VAR8, input VAR1, output VAR3 );
reg VAR4=0;
reg VAR18=0;
reg VAR10=0;
reg [12:0] VAR5=0;
reg [11:0] VAR7=0;
reg [7:0] VAR16=0;
reg [11:0] VAR17=0;
reg [7:0] VAR11=0;
reg VAR19; reg VAR2;
assign VAR3 = ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a221oi/sky130_fd_sc_hdll__a221oi.functional.pp.v | 2,229 | module MODULE1 (
VAR13 ,
VAR2 ,
VAR1 ,
VAR5 ,
VAR11 ,
VAR15 ,
VAR18,
VAR8,
VAR4 ,
VAR19
);
output VAR13 ;
input VAR2 ;
input VAR1 ;
input VAR5 ;
input VAR11 ;
input VAR15 ;
input VAR18;
input VAR8;
input VAR4 ;
input VAR19 ;
wire VAR9 ;
wire VAR7 ;
wire VAR12 ;
wire VAR14;
and VAR10 (VAR9 , VAR5, VAR11 );
and VAR16 (VA... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature_KOA/ecp/ks15.v | 9,147 | module MODULE1(VAR23, VAR114, VAR39);
input wire [0:14] VAR23;
input wire [0:14] VAR114;
output wire [0:28] VAR39;
wire VAR57, VAR27, VAR13, VAR50, VAR24, VAR2, VAR52, VAR5, VAR111, VAR17, VAR25, VAR66, VAR22, VAR51, VAR64;
wire VAR79, VAR109, VAR42, VAR93, VAR37, VAR28, VAR87, VAR12, VAR72, VAR34, VAR69, VAR15, VAR44,... | gpl-3.0 |
fpgasystems/caribou | hw/src/regex/rem_charmatch.v | 1,974 | module MODULE1
(
clk,
rst,
VAR7,
VAR8,
VAR4,
VAR6,
VAR5,
VAR2,
VAR9
);
input clk;
input rst;
input VAR7;
input [7:0] VAR8;
input VAR4;
input VAR6;
input [7:0] VAR5;
input VAR2;
output VAR9;
reg VAR10;
reg [7:0] VAR1;
reg VAR3;
assign VAR9 = VAR10;
always @(posedge clk)
begin
if(rst) begin
VAR1 <= 0;
VAR10 <= 0;
end
els... | gpl-3.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/spu_ma_mon.v | 1,984 | module MODULE1 (
clk, VAR8, VAR1,
VAR4, VAR9,
VAR5, VAR2, VAR6
);
input clk;
input VAR8;
input VAR1;
input VAR4;
input VAR9;
input [6:0] VAR5;
input [6:0] VAR2;
input [63:0] VAR6;
always @(negedge clk)
begin
if (VAR8 | VAR4) begin
(0,"VAR3[",VAR5,"] = %VAR7",VAR6);
end
if (VAR1 | VAR9) begin
(0,"VAR3[",VAR2,"] = %VAR7"... | gpl-2.0 |
Progressive-Learning-Platform/progressive-learning-platform | reference/hw/verilog/cpu.v | 3,467 | module MODULE1(rst, clk, VAR13, VAR35, dout, din, VAR15, VAR51, VAR38, int, VAR16);
input clk, rst, VAR13;
output [31:0] VAR35;
output [31:0] dout;
input [31:0] din;
output [1:0] VAR15;
output [31:0] VAR51;
input [31:0] VAR38;
input int;
output VAR16;
wire [31:0] VAR31;
wire [31:0] VAR17;
wire [31:0] VAR1;
wire [31:0] ... | gpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/6-pipe_registers/latch_IF_ID.v | 1,367 | module MODULE1
parameter VAR7=32 )
(
input wire clk,
input wire reset,
input wire VAR6,
input wire VAR1,
input wire VAR5,
input wire [VAR7-1:0]VAR8,
input wire [VAR7-1:0]VAR2,
output reg [VAR7-1:0]VAR9,
output reg [VAR7-1:0]VAR4
);
reg [VAR7-1:0] VAR3;
reg [VAR7-1:0] VAR10;
always @(posedge clk)
begin
if (reset)
begin
... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/b9c82e235214f825/zynq_design_1_auto_pc_0_stub.v | 4,653 | module MODULE1(VAR29, VAR5, VAR3, VAR56,
VAR51, VAR37, VAR58, VAR30, VAR35, VAR46,
VAR43, VAR4, VAR47, VAR54, VAR40, VAR1,
VAR41, VAR11, VAR55, VAR8, VAR20, VAR45, VAR52,
VAR44, VAR50, VAR16, VAR15, VAR10, VAR57,
VAR39, VAR31, VAR2, VAR28, VAR38, VAR26,
VAR24, VAR59, VAR18, VAR49, VAR23, VAR27, VAR17,
VAR7, VAR13, VAR3... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2bb2ai/sky130_fd_sc_hd__o2bb2ai_2.v | 2,411 | module MODULE1 (
VAR1 ,
VAR4,
VAR6,
VAR10 ,
VAR3 ,
VAR9,
VAR11,
VAR2 ,
VAR5
);
output VAR1 ;
input VAR4;
input VAR6;
input VAR10 ;
input VAR3 ;
input VAR9;
input VAR11;
input VAR2 ;
input VAR5 ;
VAR8 VAR7 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR5... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlxtp/sky130_fd_sc_ms__dlxtp.functional.pp.v | 1,656 | module MODULE1 (
VAR9 ,
VAR4 ,
VAR3,
VAR2,
VAR7,
VAR8 ,
VAR11
);
output VAR9 ;
input VAR4 ;
input VAR3;
input VAR2;
input VAR7;
input VAR8 ;
input VAR11 ;
wire VAR10;
VAR6 VAR1 (VAR10 , VAR4, VAR3, , VAR2, VAR7);
buf VAR5 (VAR9 , VAR10 );
endmodule | apache-2.0 |
bargei/NoC264 | NoC264_3x3/RegFileLoadSyn.v | 2,404 | module MODULE1
(VAR11, VAR8,
VAR14, VAR10, VAR4,
VAR6, VAR1
);
parameter VAR3 = "";
parameter VAR13 = 1;
parameter VAR7 = 1;
parameter VAR5 = 0;
parameter VAR12 = 1;
parameter VAR2 = 0;
input VAR11;
input VAR8;
input [VAR13 - 1 : 0] VAR14;
input [VAR7 - 1 : 0] VAR10;
input VAR4;
input [VAR13 - 1 : 0] VAR6;
output [VAR7... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.behavioral.pp.v | 1,927 | module MODULE1 (
VAR4,
VAR2,
VAR9 ,
VAR12 ,
VAR13 ,
VAR10 ,
VAR15
);
input VAR4;
input VAR2;
output VAR9 ;
input VAR12 ;
input VAR13 ;
input VAR10 ;
input VAR15 ;
wire VAR15 VAR14 ;
wire VAR8 ;
wire VAR3;
and VAR5 (VAR14 , VAR10, VAR12, VAR13 );
or VAR7 (VAR8 , VAR14, VAR15 );
VAR1 VAR11 (VAR3, VAR8, VAR4, VAR2);
buf V... | apache-2.0 |
SiLab-Bonn/monopix_daq | firmware/src/mono_data_rx/mono_data_rx.v | 2,011 | module MODULE1
parameter VAR18 = 16'h0000,
parameter VAR1 = 16'h0000,
parameter VAR6 = 16,
parameter VAR8 = 2'b00
)(
input wire VAR15,
input wire [VAR6-1:0] VAR23,
inout wire [7:0] VAR21,
input wire VAR25,
input wire VAR28,
input wire VAR24,
input wire [63:0] VAR19,
input wire VAR16,
input wire VAR2, VAR20, VAR17,
outp... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_1.behavioral.pp.v | 9,064 | module MODULE1( VAR52, VAR20, VAR32, VAR85, VAR69, VAR74, VAR27 );
input VAR52, VAR20, VAR85, VAR32;
inout VAR74, VAR27;
output VAR69;
reg VAR89;
VAR35 VAR8(.VAR52(VAR52),.VAR20(VAR20),.VAR32(VAR32),.VAR85(VAR85),.VAR69(VAR69),.VAR74(VAR74),.VAR27(VAR27),.VAR89(VAR89));
VAR35 VAR38(.VAR52(VAR52),.VAR20(VAR20),.VAR32(VA... | apache-2.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_mux_6to1_sel3_12_1.v | 1,585 | module MODULE1 #(
parameter
VAR4 = 0,
VAR3 = 1,
VAR15 = 32,
VAR16 = 32,
VAR2 = 32,
VAR23 = 32,
VAR13 = 32,
VAR6 = 32,
VAR14 = 32,
VAR20 = 32
)(
input [11 : 0] VAR8,
input [11 : 0] VAR7,
input [11 : 0] VAR17,
input [11 : 0] VAR1,
input [11 : 0] VAR21,
input [11 : 0] VAR9,
input [2 : 0] VAR22,
output [11 : 0] dout);
wire... | apache-2.0 |
igalanommatis/zdma | hw/oled/hdl/ZedboardOLED_v1_0_S00_AXI.v | 44,014 | module MODULE1 #
(
parameter integer VAR98 = 32,
parameter integer VAR150 = 7
)
(
output VAR59,
output VAR13,
output VAR22,
output VAR121,
output VAR67,
output VAR127,
input wire VAR90,
input wire VAR32,
input wire [VAR150-1 : 0] VAR94,
input wire [2 : 0] VAR70,
input wire VAR39,
output wire VAR99,
input wire [VAR98-1 ... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_csc_CrYCb2RGB.v | 5,152 | module MODULE1 (
clk,
VAR6,
VAR20,
VAR1,
VAR34,
VAR17,
VAR22,
VAR21,
VAR30);
input clk;
input VAR6;
input VAR20;
input VAR1;
input [23:0] VAR34;
output VAR17;
output VAR22;
output VAR21;
output [23:0] VAR30;
reg VAR17 = 'd0;
reg VAR22 = 'd0;
reg VAR21 = 'd0;
reg [23:0] VAR30 = 'd0;
wire VAR28;
wire VAR13;
wire VAR18;
w... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/cordic_stage.v | 1,783 | module MODULE1( VAR1, reset, enable, VAR11,VAR12,VAR5,VAR8,VAR10,VAR7,VAR3);
parameter VAR6 = 16;
parameter VAR2 = 16;
parameter VAR9 = 1;
input VAR1;
input reset;
input enable;
input [VAR6-1:0] VAR11,VAR12;
input [VAR2-1:0] VAR5;
input [VAR2-1:0] VAR8;
output [VAR6-1:0] VAR10,VAR7;
output [VAR2-1:0] VAR3;
wire VAR4 = ... | gpl-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/acl_channel_fifo.v | 6,156 | module MODULE1
parameter integer VAR3 = 16,
parameter integer VAR10 = 64, parameter integer VAR5 = 0,
parameter integer VAR46=0, parameter integer VAR2=32,
parameter integer VAR22=0
)
(
input logic VAR4,
input logic VAR30,
input logic VAR55,
input logic [VAR10-1:0] VAR49,
output logic VAR37,
output logic [VAR2-1:0] VAR... | mit |
dingzh/piplined-MIPS-CPU | src/LAB6/Alu.v | 1,477 | module MODULE1(
input [31:0] VAR2,
input [31:0] VAR3,
input [3:0] VAR5,
output reg VAR4,
output reg [31:0] VAR1
);
always @(VAR2 or VAR3 or VAR5)
begin
case(VAR5)
'b0000: begin
VAR1 = VAR2 & VAR3;
VAR4 = 0;
end
'b0001: begin
VAR1 = VAR2 | VAR3;
VAR4 = 0;
end
'b0010: begin
VAR1 = VAR2 + VAR3;
VAR4 = 0;
end
'b0110: begin... | gpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_Tiger4NSC_0_0/synth/OpenSSD2_Tiger4NSC_0_0.v | 14,564 | module MODULE1 (
VAR14,
VAR64,
VAR80,
VAR73,
VAR34,
VAR39,
VAR49,
VAR43,
VAR45,
VAR87,
VAR15,
VAR32,
VAR79,
VAR74,
VAR1,
VAR46,
VAR56,
VAR59,
VAR82,
VAR21,
VAR75,
VAR37,
VAR22,
VAR25,
VAR58,
VAR94,
VAR50,
VAR36,
VAR42,
VAR44,
VAR47,
VAR16,
VAR77,
VAR27,
VAR48,
VAR4,
VAR71,
VAR9,
VAR19,
VAR26,
VAR65,
VAR35,
VAR31,
VAR90... | gpl-3.0 |
gbraad/minimig-de1 | lib/models/sd_card.v | 3,262 | module MODULE1 #(
parameter VAR4=""
)(
input wire VAR5,
input wire VAR3,
input wire VAR7,
output wire VAR1
);
integer VAR6;
integer VAR2;
begin | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/sdlclkp/sky130_fd_sc_hd__sdlclkp.behavioral.pp.v | 2,529 | module MODULE1 (
VAR21,
VAR8 ,
VAR17,
VAR7 ,
VAR13,
VAR22,
VAR9 ,
VAR20
);
output VAR21;
input VAR8 ;
input VAR17;
input VAR7 ;
input VAR13;
input VAR22;
input VAR9 ;
input VAR20 ;
wire VAR15 ;
wire VAR10 ;
wire VAR2 ;
wire VAR6 ;
wire VAR16 ;
wire VAR3 ;
wire VAR4;
reg VAR12 ;
wire VAR5 ;
wire VAR24 ;
wire VAR25 ;
not... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ip_top/mem_intfc.v | 30,889 | module MODULE1 #
(
parameter VAR231 = 100,
parameter VAR161 = 64,
parameter VAR65 = "1T",
parameter VAR95 = "0", parameter VAR40 = 3, parameter VAR221 = 2, parameter VAR137 = "8", parameter VAR152 = "VAR171", parameter VAR240 = 1, parameter VAR96 = 4'hc,
parameter VAR46 = 4'hf,
parameter VAR226 = 4'hf,
parameter VAR228... | lgpl-3.0 |
jbelloncastro/amber_arm | hw/vlog/ethmac/eth_top.v | 36,598 | module MODULE1
(
VAR4, VAR16, VAR154, VAR197,
VAR251, VAR23, VAR92, VAR276, VAR33, VAR253, VAR128,
VAR70, VAR36, VAR250,
VAR96, VAR274, VAR199,
VAR240, VAR237, VAR192,
VAR182, VAR231,
VAR172, VAR286, VAR239, VAR132,
VAR66, VAR160, VAR39, VAR156, VAR97, VAR290,
VAR91, VAR2, VAR63, VAR261,
VAR106
,
VAR29, VAR158, VAR289 ... | lgpl-3.0 |
hoglet67/opc | copro/src/Tube/ph_reg3.v | 6,276 | module MODULE1 (
input VAR8,
input VAR25,
input VAR31,
input VAR14,
input [7:0] VAR4,
input VAR17,
input VAR9,
input VAR5,
input VAR2,
output [7:0] VAR15,
output VAR22,
output VAR18,
output VAR24
);
wire [1:0] VAR30;
wire [1:0] VAR16;
reg [7:0] VAR29 ;
reg [7:0] VAR23 ;
wire [7:0] VAR12 ;
wire [7:0] VAR26 ;
assign VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd2/sky130_fd_sc_ls__clkdlyinv5sd2.functional.v | 1,344 | module MODULE1 (
VAR2,
VAR1
);
output VAR2;
input VAR1;
wire VAR5;
not VAR4 (VAR5, VAR1 );
buf VAR3 (VAR2 , VAR5 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/antenna/gf180mcu_fd_sc_mcu7t5v0__antenna.behavioral.pp.v | 1,098 | module MODULE1( VAR6, VAR4, VAR5 );
input VAR6;
inout VAR4, VAR5;
VAR3 VAR2(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5));
VAR3 VAR1(.VAR6(VAR6),.VAR4(VAR4),.VAR5(VAR5)); | apache-2.0 |
niketancm/tsea26 | lab2-3/rtl/fwd_ctrl.v | 1,738 | module MODULE1(
input wire[VAR23-1:0] VAR18,
input wire VAR17,
input wire VAR21,
input wire VAR7,
input wire [VAR15-1:0] VAR22,
output reg [VAR2-1:0] VAR13
);
wire VAR1;
assign VAR1 = (VAR4 == 4'b0001) ? 1'b1 : 1'b0;
always@* begin
VAR10 = 0;
casex({VAR20, 1'b1, VAR1})
{1'b0, VAR6, 1'VAR19}: begin
if((VAR16 == 4'b0010)... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/verilog/raygentop.v | 84,818 | module MODULE10 (VAR336, VAR137, VAR6, VAR26, VAR316, VAR215, VAR232, VAR64, VAR87, VAR23, VAR194, VAR15, VAR272, VAR313, VAR140, VAR76, VAR142, VAR275, VAR219, VAR86, VAR145, VAR2, VAR172, VAR234, VAR294, VAR102, VAR293, VAR144, VAR249, VAR117, VAR270, VAR72, VAR332, VAR263, VAR187, VAR181, VAR29, VAR242, VAR205);
out... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor2/sky130_fd_sc_ls__nor2_4.v | 2,086 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR9 ,
VAR3,
VAR7,
VAR8 ,
VAR1
);
output VAR2 ;
input VAR4 ;
input VAR9 ;
input VAR3;
input VAR7;
input VAR8 ;
input VAR1 ;
VAR6 VAR5 (
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR1(VAR1)
);
endmodule
module MODULE1 (
VAR2,
VAR4,
VAR9
);
output VAR2;
... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_2.behavioral.v | 1,620 | module MODULE1( VAR1, VAR7, VAR4, VAR2 );
input VAR2, VAR7, VAR4;
output VAR1;
VAR5 VAR6(.VAR1(VAR1),.VAR7(VAR7),.VAR4(VAR4),.VAR2(VAR2));
VAR5 VAR3(.VAR1(VAR1),.VAR7(VAR7),.VAR4(VAR4),.VAR2(VAR2)); | apache-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_3r1w_synth.v | 1,799 | module MODULE1 #(parameter VAR4(VAR18)
, parameter VAR4(VAR20)
, parameter VAR13=0
, parameter VAR11=VAR8(VAR20)
)
(input VAR24
, input VAR12
, input VAR22
, input [VAR11-1:0] VAR3
, input [VAR15(VAR18, 1):0] VAR6
, input VAR27
, input [VAR11-1:0] VAR16
, output logic [VAR15(VAR18, 1):0] VAR5
, input VAR17
, input [VAR... | bsd-3-clause |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/frontend/fir_band_pass_st.v | 92,343 | module MODULE1 (clk,
rst,
VAR122,
VAR85,
VAR369,
VAR379,
VAR19);
parameter VAR160 = 11;
parameter VAR406 = 11;
parameter VAR74 = 24;
parameter VAR377 = 0;
parameter VAR313 = 8;
parameter VAR231 = VAR74-VAR313;
input clk, rst;
input [VAR160-1:0] VAR122;
input VAR85;
output VAR369;
wire VAR369;
wire VAR150;
wire VAR43;
o... | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_axis_tx.v | 15,089 | module MODULE1 #
(
parameter VAR12 = 8,
parameter VAR17 = (VAR12>8),
parameter VAR19 = (VAR12/8)
)
(
input wire clk,
input wire rst,
input wire VAR9,
output wire VAR24,
input wire [47:0] VAR22,
input wire [47:0] VAR23,
input wire [15:0] VAR13,
input wire [VAR12-1:0] VAR5,
input wire [VAR19-1:0] VAR16,
input wire VAR3,
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21bo/sky130_fd_sc_hs__a21bo.pp.blackbox.v | 1,339 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR5,
VAR1,
VAR6
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR6;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn.pp.symbol.v | 1,458 | module MODULE1 (
input VAR5 ,
output VAR6 ,
output VAR3 ,
input VAR9,
input VAR2 ,
input VAR8 ,
input VAR4 ,
input VAR7 ,
input VAR1
);
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/gpif/fifo36_to_gpmc16.v | 2,421 | module MODULE1
parameter VAR6 = 9,
parameter VAR25 = 2
)
(
input VAR35, input VAR47,
input [35:0] VAR28,
input VAR44,
output VAR10,
input VAR19, input VAR8,
output [15:0] VAR46,
output valid,
input enable,
output VAR11,
output reg VAR17
);
wire [15:0] VAR27;
always @(posedge VAR19)
VAR17 <= (VAR27 >= VAR25);
wire [35:0... | gpl-2.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0/LCD_control.v | 4,806 | module MODULE1(
input [7:0] VAR11,
input [7:0] VAR20,
input [7:0] VAR26,
output [9:0] VAR24, output [9:0] VAR7, output [21:0] VAR9, output VAR27, output reg VAR12, output [7:0] VAR22,
output [7:0] VAR8,
output [7:0] VAR5,
output reg VAR3, output reg VAR10, output VAR17, input VAR29,
input VAR15
);
reg [10:0] VAR1;
reg ... | apache-2.0 |
hakehuang/pycpld | ips/ip/spi_slave_b2b/spi_slave_act_l_b2b.v | 5,035 | module MODULE1
(
clk,VAR5,VAR18,VAR20,VAR15,VAR19,VAR4
);
input clk;
input VAR19;
input VAR5,VAR18,VAR15;
output VAR20;
output VAR4;
reg VAR4;
reg[2:0] VAR14;
reg[2:0] VAR6;
reg[1:0] VAR8;
reg[2:0] VAR22;
reg[7:0] VAR7;
reg VAR1; reg [7:0] VAR23;
reg[7:0] VAR24;
reg [7:0] VAR12;
reg [7:0] VAR11;
reg [7:0] VAR17;
wire V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand2/sky130_fd_sc_ms__nand2.symbol.v | 1,266 | module MODULE1 (
input VAR5,
input VAR2,
output VAR7
);
supply1 VAR6;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
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