repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
bnossum/uart_ice40 | src/uartICE40.v | 8,968 | module MODULE4
wire VAR16; wire VAR74; MODULE1 MODULE3 (
.VAR25 (VAR25),
.VAR71 (VAR71),
.clk (clk),
.VAR65 (VAR65),
.VAR16 (VAR16),
.VAR43 (VAR43[7:0]));
MODULE2 MODULE2 (
.VAR44 (VAR44),
.VAR26 (VAR26[1:0]),
.VAR39 (VAR39[7:0]),
.clk (clk),
.VAR74 (VAR74),
.VAR76 (VAR76));
MODULE5 #( .VAR18(VAR18),
.VAR62(VAR62))
VAR... | mit |
CospanDesign/nysa-verilog | verilog/wishbone/interconnect/wishbone_mem_interconnect.v | 1,674 | module MODULE1 (
input clk,
input rst,
input VAR5,
input VAR1,
input VAR2,
input [3:0] VAR11,
input [31:0] VAR4,
input [31:0] VAR6,
output reg [31:0] VAR9,
output reg VAR12,
output reg VAR14,
{VAR16}
);
{VAR7}
{VAR13}
{VAR3}
{VAR10}
{VAR8}
{VAR15}
endmodule | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution4/syn/verilog/matrix_mult.v | 27,218 | module MODULE1 (
VAR63,
VAR23,
VAR5,
VAR21,
VAR78,
VAR134,
VAR55,
VAR150,
VAR82,
VAR116,
VAR139,
VAR143,
VAR33,
VAR49,
VAR18,
VAR26
);
parameter VAR118 = 3'd1;
parameter VAR20 = 3'd2;
parameter VAR144 = 3'd4;
input VAR63;
input VAR23;
input VAR5;
output VAR21;
output VAR78;
output VAR134;
output [2:0] VAR55;
output VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.v | 2,804 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR7 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR14,
VAR13 ,
VAR9 ,
VAR10 ,
VAR8 ,
VAR12
);
output VAR2 ;
input VAR6 ;
input VAR7 ;
input VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR14;
input VAR13 ;
input VAR9 ;
input VAR10 ;
input VAR8 ;
input VAR12 ;
VAR3 VAR4 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR7(VAR7),
.V... | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/user_settings.v | 1,889 | module MODULE1
(input clk,
input rst,
input VAR13,
input [7:0] VAR17,
input [31:0] VAR9,
output VAR4,
output [7:0] VAR8,
output [31:0] VAR16
);
wire VAR10, VAR7;
reg VAR1;
VAR3 #(.VAR12(VAR6+0),.VAR11(8)) VAR2
(.clk(clk),.rst(rst),.VAR15(VAR13),.addr(VAR17),
.in(VAR9),.out(VAR8),.VAR14(VAR10) );
VAR3 #(.VAR12(VAR6+1)) ... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_2.functional.pp.v | 1,190 | module MODULE1( VAR14, VAR9, VAR6, VAR16, VAR2, VAR11 );
input VAR9, VAR6;
inout VAR2, VAR11;
output VAR14, VAR16;
and VAR1( VAR14, VAR9, VAR6 );
wire VAR4;
not VAR12( VAR4, VAR6 );
wire VAR10;
and VAR8( VAR10, VAR4, VAR9 );
wire VAR15;
not VAR13( VAR15, VAR9 );
wire VAR7;
and VAR3( VAR7, VAR15, VAR6 );
or VAR5( VAR16,... | apache-2.0 |
monotone-RK/FACE | MCSoC-15/4-way_2-parallel/src/vivado_ip_dram/phy/mig_7series_v2_3_ddr_byte_group_io.v | 21,896 | module MODULE1 #(
parameter VAR11 = 12'b111111111111,
parameter VAR173 = 12'b000000000000,
parameter VAR27 = "VAR114",
parameter VAR142 = "VAR128",
parameter VAR129 = 4,
parameter VAR118 = "VAR97",
parameter VAR109 = 00,
parameter VAR120 = "VAR51",
parameter VAR1 = 1,
parameter real VAR164 = 2500.0,
parameter VAR77 = 1... | mit |
alexforencich/hdg2000 | fpga/rtl/fpga.v | 30,431 | module MODULE1 #(
parameter VAR240 = "VAR242"
)
(
input wire VAR95,
input wire VAR381,
output wire VAR327,
input wire VAR91,
input wire VAR434,
input wire VAR61,
output wire VAR344,
input wire VAR152,
input wire VAR178,
output wire VAR52,
output wire VAR400,
output wire VAR456,
output wire [2:0] VAR123,
output wire VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/bufinv/sky130_fd_sc_ls__bufinv.blackbox.v | 1,238 | module MODULE1 (
VAR2,
VAR3
);
output VAR2;
input VAR3;
supply1 VAR1;
supply0 VAR5;
supply1 VAR4 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ebufn/sky130_fd_sc_ms__ebufn.functional.v | 1,216 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4
);
output VAR1 ;
input VAR2 ;
input VAR4;
bufif0 VAR3 (VAR1 , VAR2, VAR4 );
endmodule | apache-2.0 |
kevintownsend/inara-hdl-libraries | cross_bar/cross_bar.v | 3,248 | module MODULE1(rst, clk, VAR23, VAR8, VAR9, valid, VAR27, VAR25, VAR15);
parameter VAR20 = 8;
parameter VAR19 = 8;
parameter VAR4 = VAR19;
parameter VAR29 = 32;
parameter VAR16 = VAR24(VAR19-1);
parameter VAR18 = VAR24(VAR4-1);
parameter VAR17 = 0;
parameter VAR10 = 1;
input rst;
input clk;
input [0:VAR19-1] VAR23;
inp... | apache-2.0 |
mindstation/TrafficLightFPGA | Svetofors_025/tri_light_svetofor.v | 5,688 | module MODULE1 ( input wire VAR4,
input wire reset,
output wire VAR7,
output wire VAR10,
output wire VAR11
);
parameter VAR8 = 8'd26 * 8'd2, VAR2 = 8'd84 * 8'd2,
VAR5 = 8'd3 * 8'd2,
VAR9 = 8'd4 * 8'd2,
VAR6 = VAR8 + VAR9 + VAR2 + VAR5 * 8'd2;
reg [7:0] VAR3; reg [2:0] VAR1;
assign VAR7 = VAR1[0];
assign VAR10 = VAR1[1]... | mit |
sh-chris110/chris | FPGA/atlas_linux_ghrd/ip/intr_capturer/intr_capturer.v | 2,405 | module MODULE1 #(
parameter VAR10 = 32
)(
input clk,
input VAR7,
input [VAR10-1:0] VAR4,
input addr,
input read,
output [31:0] VAR9
);
reg [VAR10-1:0] VAR2;
reg [31:0] VAR1;
wire [31:0] VAR8;
wire [31:0] VAR3;
wire [31:0] VAR11;
wire VAR5;
wire VAR12;
always @(posedge clk or negedge VAR7) begin
if (!VAR7) VAR2 <= 'b0;
... | gpl-2.0 |
rkrajnc/minimig-de1 | rtl/minimig/Floppy.v | 24,883 | module MODULE1
(
input clk, input reset, input VAR94, input VAR125, input enable, input [8:1] VAR26, input [15:0] VAR11, output [15:0] VAR76, output VAR27, output VAR39, input VAR100, input VAR116, input [3:0] sel, input VAR31, input VAR105, output VAR130, output VAR108, output ready, output VAR77, output VAR111, outpu... | gpl-3.0 |
AbhishekShah212/School_Projects | ELEN232/pset4/Problem1.v | 5,642 | module MODULE1(
input [3:0] VAR2,
output reg [6:0] VAR1,
output reg VAR3
);
always @ ( VAR2)
begin
VAR3 = 0;
case(VAR2)
4'b0000: begin VAR1[0] = 0;
VAR1[1] = 0;
VAR1[2] = 0;
VAR1[3] = 0;
VAR1[4] = 0;
VAR1[5] = 0;
VAR1[6] = 1;
end
4'b0001: begin VAR1[0] = 1;
VAR1[1] = 0;
VAR1[2] = 0;
VAR1[3] = 1;
VAR1[4] = 1;
VAR1[5] = ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2ai/sky130_fd_sc_ms__o2bb2ai_1.v | 2,411 | module MODULE1 (
VAR10 ,
VAR9,
VAR5,
VAR11 ,
VAR8 ,
VAR3,
VAR4,
VAR2 ,
VAR7
);
output VAR10 ;
input VAR9;
input VAR5;
input VAR11 ;
input VAR8 ;
input VAR3;
input VAR4;
input VAR2 ;
input VAR7 ;
VAR6 VAR1 (
.VAR10(VAR10),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7... | apache-2.0 |
ptracton/wb_soc_template | rtl/LM32/rtl/lm32_multiplier.v | 3,907 | module MODULE1 (
VAR3,
VAR11,
VAR5,
VAR10,
VAR8,
VAR4,
VAR2
);
input VAR3; input VAR11; input VAR5; input VAR10; input [VAR14] VAR8; input [VAR14] VAR4;
output [VAR14] VAR2; reg [VAR14] VAR2;
reg [VAR14] VAR13;
reg [VAR14] VAR7;
reg [VAR14] VAR1;
always @(posedge VAR3 VAR6)
begin
if (VAR11 == VAR12)
begin
VAR13 <= {VAR... | mit |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/bd/system/ip/system_auto_pc_1/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_fifo_gen.v | 15,129 | module MODULE1 #(
parameter VAR78 = "VAR226",
parameter integer VAR423 = 1,
parameter integer VAR294 = 3,
parameter integer VAR102 = 5,
parameter integer VAR408 = 64,
parameter VAR409 = "lut"
)(
clk,
rst,
VAR136,
VAR252,
VAR379,
VAR395,
VAR16,
VAR91,
VAR280,
VAR236);
input clk;
input VAR136;
input VAR16;
input rst;
inp... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_col_mach.v | 16,535 | module MODULE1 #
(
parameter VAR7 = 100,
parameter VAR21 = 3,
parameter VAR27 = "8",
parameter VAR84 = 12,
parameter VAR94 = 4,
parameter VAR14 = 8,
parameter VAR16 = 1,
parameter VAR110 = 0,
parameter VAR46 = 8,
parameter VAR30 = "VAR18",
parameter VAR115 = "VAR9",
parameter VAR109 = "VAR9",
parameter VAR55 = 31,
para... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xor2/gf180mcu_fd_sc_mcu7t5v0__xor2_1.behavioral.v | 1,410 | module MODULE1( VAR2, VAR1, VAR5 );
input VAR1, VAR2;
output VAR5;
VAR4 VAR3(.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5));
VAR4 VAR6(.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2_1.v | 2,094 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR5 ,
VAR4,
VAR6,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR9 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR3 ;
input VAR2 ;
VAR1 VAR8 (
.VAR7(VAR7),
.VAR9(VAR9),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR7,
VAR9,
VAR5
);
output VAR7;
... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/phy/rd_bitslip.v | 5,421 | module MODULE1 #
(
parameter VAR2 = 100
)
(
input clk,
input [1:0] VAR6,
input [1:0] VAR7,
input [5:0] din,
output reg [3:0] VAR3
);
reg VAR9;
reg [3:0] VAR5;
reg [3:0] VAR4;
reg [3:0] VAR8;
reg [3:0] VAR1;
always @(posedge clk)
always @(VAR6 or din or VAR9)
case (VAR6)
2'b00: VAR5 = {din[3], din[2], din[1], din[0]};
2... | lgpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_dtl_bscl1.v | 1,737 | module MODULE1(VAR15 ,VAR12 ,VAR13 ,VAR6 ,
VAR14 );
output VAR15 ;
output VAR12 ;
input VAR13 ;
input VAR6 ;
input VAR14 ;
wire VAR9 ;
wire VAR1 ;
VAR16 VAR7 (
.VAR4 (VAR12 ),
.VAR5 (VAR9 ) );
VAR2 VAR11 (
.VAR4 (VAR1 ),
.VAR5 (VAR14 ),
.VAR8 (VAR6 ) );
VAR2 VAR3 (
.VAR4 (VAR15 ),
.VAR5 (VAR13 ),
.VAR8 (VAR1 ) );
VAR10... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dlygate4sd2/sky130_fd_sc_hdll__dlygate4sd2.pp.blackbox.v | 1,317 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR2,
VAR5,
VAR4 ,
VAR1
);
output VAR6 ;
input VAR3 ;
input VAR2;
input VAR5;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
hightoon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_RXMSG_Byte_Alignment.v | 8,385 | module MODULE1(
input clk,
input enable, input [7:0] VAR2,
output reg VAR19,
output reg [7:0] VAR4,
output reg VAR14,
output reg VAR5,
output reg [39:0] VAR18
);
reg [7:0] VAR15; reg [7:0] VAR6; reg [7:0] VAR1; reg [2:0] VAR12; reg VAR16; reg [7:0] VAR9; reg [2:0] VAR7;
reg [7:0] VAR13;
reg [7:0] VAR3;
wire [7:0] VAR11... | bsd-2-clause |
chadharrington/all_spark_cube | fpga/cube_controller.v | 3,424 | module MODULE1
(
input VAR25, input [1:0] VAR8,
input [3:0] VAR26,
inout [12:0] VAR35,
input [2:0] VAR34,
inout [33:0] VAR43,
input [1:0] VAR39,
inout [33:0] VAR15,
input [1:0] VAR32,
output [7:0] VAR40
);
wire clk, VAR18, VAR11;
wire VAR31, VAR24;
wire VAR16;
wire [15:0] VAR3;
wire VAR42, VAR12, VAR7, VAR30, VAR45;
wi... | mit |
lsnow/mips32 | data_cache.v | 2,121 | module MODULE1();
input [31:0] VAR10;
input [31:0] VAR26;
input VAR11;
input VAR4;
input clk, rst;
output [31:0] VAR20;
output VAR18;
output [31:0] VAR17;
output [31:0] VAR24;
output VAR19;
output VAR15;
input VAR1;
reg VAR23 [0:63];
reg [23:0] VAR2 [0:63];
reg [31:0] VAR12 [0:63];
wire [5:0] VAR13 = VAR10[7:2];
wire [... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/inv/gf180mcu_fd_sc_mcu9t5v0__inv_1.behavioral.v | 1,101 | module MODULE1( VAR2, VAR5 );
input VAR2;
output VAR5;
VAR4 VAR1(.VAR2(VAR2),.VAR5(VAR5));
VAR4 VAR3(.VAR2(VAR2),.VAR5(VAR5)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/addh/gf180mcu_fd_sc_mcu7t5v0__addh_1.behavioral.pp.v | 1,568 | module MODULE1( VAR7, VAR4, VAR6, VAR8, VAR2, VAR1 );
input VAR4, VAR6;
inout VAR2, VAR1;
output VAR7, VAR8;
VAR9 VAR3(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1));
VAR9 VAR5(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1)); | apache-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/uart/uart_master.v | 8,440 | module MODULE1(
input VAR5,
input VAR23,
input VAR27,
output VAR9,
inout [7:0] VAR32,
output reg [31:0] VAR41,
output reg VAR25,
output reg VAR48
);
wire clk;
assign clk = VAR5;
wire [7:0] VAR1;
reg [7:0] VAR6;
assign VAR1 = VAR32;
assign VAR32 = VAR25 ? VAR6 : 8'VAR21;
reg [7:0] VAR14;
wire [7:0] VAR16;
wire VAR47, VA... | bsd-3-clause |
HashRatio/mm-hashratio | verilog/superkdf9/components/uart_core/uart_core.v | 12,428 | module MODULE1
parameter VAR50 = 4,
parameter VAR57 = 8,
parameter VAR51 = 115200,
parameter VAR40 = 0,
parameter VAR5 = 8,
parameter VAR77 = 1,
parameter VAR56 = 0,
parameter VAR14 = 0,
parameter VAR75 = 0,
parameter VAR99 = 0,
parameter VAR1 = 0,
parameter VAR55 = 0
)
(
input VAR26,
input VAR71,
input VAR13,
input VA... | unlicense |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/ddr_core/user_design/rtl/clocking/mig_7series_v1_8_tempmon.v | 15,167 | module MODULE1 #
(
parameter VAR10 = 100, parameter VAR83 = "VAR22", parameter VAR48 = 5000, parameter VAR74 = 10000000 )
(
input clk, input VAR17,
input rst, input [11:0] VAR44, output [11:0] VAR24 );
function integer VAR68 (input integer VAR35, input integer VAR13);
begin
VAR68 = (VAR35/VAR13) + (((VAR35%VAR13)>0) ? ... | lgpl-3.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_transmitcontrol.v | 11,065 | module MODULE1 (VAR8, VAR14, VAR19, VAR5, VAR33, VAR24,
VAR10, VAR1, VAR17, VAR30, VAR18,
VAR11, VAR20, VAR27, VAR29, VAR3, VAR16,
VAR31, VAR26, VAR12
);
parameter VAR4 = 1;
input VAR8;
input VAR14;
input VAR19;
input VAR5;
input VAR33;
input VAR24;
input VAR10;
input VAR1;
input VAR17;
input VAR30;
input VAR18;
input ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a41o/sky130_fd_sc_hs__a41o.functional.pp.v | 1,959 | module MODULE1 (
VAR13,
VAR11,
VAR6 ,
VAR5 ,
VAR3 ,
VAR12 ,
VAR14 ,
VAR10
);
input VAR13;
input VAR11;
output VAR6 ;
input VAR5 ;
input VAR3 ;
input VAR12 ;
input VAR14 ;
input VAR10 ;
wire VAR14 VAR7 ;
wire VAR2 ;
wire VAR4;
and VAR1 (VAR7 , VAR5, VAR3, VAR12, VAR14 );
or VAR8 (VAR2 , VAR7, VAR10 );
VAR9 VAR15 (VAR4, ... | apache-2.0 |
svenstaro/uni-projekt | verilog/rom_bb.v | 5,145 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3);
input [7:0] address;
input VAR1;
input VAR2;
output [31:0] VAR3;
tri1 VAR1;
tri1 VAR2;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrbp/sky130_fd_sc_hdll__sdfrbp_1.v | 2,711 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR12 ,
VAR5 ,
VAR9 ,
VAR11 ,
VAR8,
VAR7 ,
VAR4 ,
VAR13 ,
VAR3
);
output VAR6 ;
output VAR1 ;
input VAR12 ;
input VAR5 ;
input VAR9 ;
input VAR11 ;
input VAR8;
input VAR7 ;
input VAR4 ;
input VAR13 ;
input VAR3 ;
VAR10 VAR2 (
.VAR6(VAR6),
.VAR1(VAR1),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR9(VAR... | apache-2.0 |
lneuhaus/pyrpl | pyrpl/fpga/rtl/red_pitaya_iq_lpf_block.v | 3,102 | module MODULE1 #(
parameter VAR7 = 25,
parameter VAR1 = 18,
parameter VAR11 = 18 )
(
input VAR8,
input VAR3 ,
input signed [VAR1-1:0] VAR9,
input signed [VAR11-1:0] VAR4,
output signed [VAR11-1:0] VAR10
);
reg signed [VAR11+VAR7-1:0] VAR2;
reg signed [VAR11+VAR7-1:0] VAR5; wire signed [VAR11-1:0] VAR6;
assign VAR6 = VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o2111ai/sky130_fd_sc_ls__o2111ai.functional.pp.v | 2,086 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR1 ,
VAR7 ,
VAR18 ,
VAR3,
VAR6,
VAR4 ,
VAR15
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR7 ;
input VAR18 ;
input VAR3;
input VAR6;
input VAR4 ;
input VAR15 ;
wire VAR16 ;
wire VAR17 ;
wire VAR12;
or VAR11 (VAR16 , VAR5, VAR2 );
nand VAR10 (VAR17 , VAR7, VAR1,... | apache-2.0 |
chipsalliance/yosys-f4pga-plugins | ql-qlf-plugin/pp3/lut_map.v | 1,624 | module MODULE1 (
VAR14,
VAR2
);
parameter VAR1 = 0;
parameter VAR3 = 0;
input [VAR1-1:0] VAR14;
output VAR2;
generate
if (VAR1 == 1) begin
VAR15 #(
.VAR16 (""),
.VAR9(VAR3)
) VAR8 (
.VAR6 (VAR2),
.VAR7(VAR14[0])
);
end else if (VAR1 == 2) begin
VAR11 #(
.VAR16 (""),
.VAR9(VAR3)
) VAR8 (
.VAR6 (VAR2),
.VAR7(VAR14[0]),
.... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_dpram_32x32.v | 14,117 | module MODULE1(
VAR5, VAR148, VAR115, VAR18, VAR152, VAR106,
VAR7, VAR100, VAR126, VAR86, VAR117, VAR141
);
parameter VAR146 = 5;
parameter VAR79 = 32;
input VAR5; input VAR148; input VAR115; input VAR18; input [VAR146-1:0] VAR152; output [VAR79-1:0] VAR106; input VAR7; input VAR100; input VAR126; input VAR86; input [V... | apache-2.0 |
P3Stor/P3Stor | pcie/IP core/RX_RECV_FIFO.v | 13,371 | module MODULE1(
clk,
VAR94,
din,
VAR12,
VAR78,
dout,
VAR1,
VAR344
);
input clk;
input VAR94;
input [31 : 0] din;
input VAR12;
input VAR78;
output [31 : 0] dout;
output VAR1;
output VAR344;
VAR262 #(
.VAR27(0),
.VAR282(0),
.VAR224(0),
.VAR246(0),
.VAR107(0),
.VAR321(0),
.VAR64(0),
.VAR356(32),
.VAR166(1),
.VAR388(1),
.V... | gpl-2.0 |
migajv/mips_pipeline | verilog/regstatus.v | 1,668 | module MODULE1 (
input clk,
input rst,
input VAR12,
input [4:0] VAR10,
input [3:0] VAR13,
input [4:0] VAR2,
input [4:0] VAR8,
input VAR4,
input [4:0] VAR1,
input VAR6,
output [3:0] VAR17,
output VAR15,
output [3:0] VAR5,
output VAR9
);
typedef struct packed {
bit [3:0] VAR3;
bit VAR16;
}VAR7;
VAR7 VAR14 [31:0];
always ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/alt_mem_ddrx_ecc_encoder_64_syn.v | 21,837 | module MODULE2 #
( parameter
VAR3 = 0
)
(
clk,
VAR7,
VAR5,
VAR9
) ;
input clk;
input VAR7;
input [63:0] VAR5;
output [71:0] VAR9;
wire [63:0] VAR1;
wire [34:0] VAR16;
wire [17:0] VAR15;
wire [8:0] VAR17;
wire [3:0] VAR19;
wire [1:0] VAR13;
wire [30:0] VAR18;
wire [6:0] VAR2;
wire [70:0] VAR6;
wire [70:0] VAR14;
reg [70... | lgpl-3.0 |
Groundworkstech/rc4-prbs | rc4.v | 3,864 | module MODULE1(clk,rst,VAR15,VAR13,VAR14);
input clk; input rst; input [7:0] VAR13; output VAR15; output [7:0] VAR14;
wire clk, rst; reg VAR15;
wire [7:0] VAR13;
reg [7:0] VAR12[0:VAR2-1];
reg [7:0] VAR17[0:256];
reg [9:0] VAR1;
reg [3:0] VAR4;
reg [7:0] VAR10; reg [7:0] VAR16;
reg [7:0] VAR14;
reg [7:0] VAR3;
always @... | lgpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_stub.v | 1,914 | module MODULE1(VAR5, VAR3, VAR6,
VAR8, VAR7, VAR10, VAR4, VAR1,
VAR9, VAR2)
;
input VAR5;
input VAR3;
input VAR6;
input VAR8;
input VAR7;
output VAR10;
output [0:0]VAR4;
output [0:0]VAR1;
output [0:0]VAR9;
output [0:0]VAR2;
endmodule | mit |
praveendath92/DDR2_Interface_Xilinx_XUPV5 | source/ddr2_usr_addr_fifo.v | 4,681 | module MODULE1 #
(
parameter VAR14 = 2,
parameter VAR25 = 10,
parameter VAR33 = 0,
parameter VAR11 = 14
)
(
input VAR16,
input VAR23,
input [2:0] VAR42,
input [30:0] VAR40,
input VAR4,
input VAR30,
output [2:0] VAR21,
output [30:0] VAR1,
output VAR34,
output VAR13
);
wire [35:0] VAR20;
reg VAR24;
always @(posedge VAR16... | mit |
bigeagle/riffa | fpga/riffa_hdl/counter.v | 3,257 | module MODULE1
parameter VAR2 = 10,
parameter VAR7 = 0)
(
input VAR11,
input VAR6,
input VAR8,
output [VAR9(VAR3+1)-1:0] VAR1
);
wire VAR10;
reg [VAR9(VAR3+1)-1:0] VAR4;
reg [VAR9(VAR3+1)-1:0] VAR5;
assign VAR10 = VAR8 & (VAR2 > VAR5);
assign VAR1 = VAR5;
always @(posedge VAR11) begin
if(VAR6) begin
VAR5 <= VAR7;
end e... | bsd-3-clause |
SI-RISCV/e200_opensource | rtl/e203/subsys/e203_subsys_hclkgen.v | 3,688 | module MODULE1(
input VAR38,
input VAR10,
input VAR27,
input VAR22 ,
input VAR41 ,
input VAR34 ,
input [1:0] VAR29,
input [7:0] VAR42,
input [4:0] VAR17,
input VAR16,
input [5:0] VAR2,
output VAR11,
output VAR37,
output VAR25 );
wire VAR3 = ~VAR10;
wire VAR19;
wire VAR12 = VAR34 | VAR10; VAR1 VAR5(
.VAR26 (VAR12 ),
.VA... | apache-2.0 |
antmicro/yosys | techlibs/anlogic/arith_map.v | 2,473 | module MODULE1(
module 80anlogicalu (VAR23, VAR3, VAR8, VAR21, VAR27, VAR30, VAR20);
parameter VAR36 = 0;
parameter VAR33 = 0;
parameter VAR6 = 1;
parameter VAR24 = 1;
parameter VAR2 = 1;
input [VAR6-1:0] VAR23;
input [VAR24-1:0] VAR3;
output [VAR2-1:0] VAR27, VAR30;
input VAR8, VAR21;
output [VAR2-1:0] VAR20;
wire VAR... | isc |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21a/sky130_fd_sc_ls__o21a.functional.v | 1,412 | module MODULE1 (
VAR2 ,
VAR3,
VAR5,
VAR7
);
output VAR2 ;
input VAR3;
input VAR5;
input VAR7;
wire VAR1 ;
wire VAR8;
or VAR4 (VAR1 , VAR5, VAR3 );
and VAR9 (VAR8, VAR1, VAR7 );
buf VAR6 (VAR2 , VAR8 );
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | bin_Gaussian_Filter/system/synthesis/submodules/lsu_wide_wrapper.v | 14,593 | module MODULE1
(
VAR15, VAR53, VAR39, VAR102, VAR12, VAR62, VAR78, VAR56,
VAR41, VAR81, VAR38, VAR70, VAR71, VAR33, VAR77, VAR14, VAR57, VAR112,
VAR91, VAR76, VAR84, VAR4, VAR37, VAR52,
VAR61, VAR115, VAR82,
VAR68,
VAR59,
VAR63,
VAR72,
VAR43,
VAR1,
VAR116
);
parameter VAR60="VAR11"; parameter VAR100=32; parameter VAR54... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p.pp.blackbox.v | 1,271 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR7,
VAR6,
VAR2 ,
VAR3 ,
VAR5
);
output VAR1 ;
input VAR4 ;
input VAR7;
input VAR6;
input VAR2 ;
input VAR3 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlygate4sd2/sky130_fd_sc_ls__dlygate4sd2.behavioral.pp.v | 1,832 | module MODULE1 (
VAR11 ,
VAR10 ,
VAR7,
VAR3,
VAR12 ,
VAR5
);
output VAR11 ;
input VAR10 ;
input VAR7;
input VAR3;
input VAR12 ;
input VAR5 ;
wire VAR6 ;
wire VAR2;
buf VAR1 (VAR6 , VAR10 );
VAR4 VAR9 (VAR2, VAR6, VAR7, VAR3);
buf VAR8 (VAR11 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi_2.v | 2,439 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR9 ,
VAR4 ,
VAR1 ,
VAR10 ,
VAR6,
VAR3,
VAR8 ,
VAR11
);
output VAR2 ;
input VAR7 ;
input VAR9 ;
input VAR4 ;
input VAR1 ;
input VAR10 ;
input VAR6;
input VAR3;
input VAR8 ;
input VAR11 ;
VAR12 VAR5 (
.VAR2(VAR2),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6(VA... | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/PFF_DSP_16.v | 19,890 | module MODULE1 (
input clk,
input VAR19,
input VAR87,
input VAR5, VAR133,
input VAR124, VAR113,
input VAR36,
input [9:0] VAR29,
input [9:0] VAR67,
input [4:0] VAR21,
input [4:0] VAR41,
input [1:0] VAR47, input [1:0] VAR60, input signed [12:0] VAR25, VAR18,
input signed [15:0] VAR62, VAR35,
input signed [12:0] VAR140,
i... | gpl-3.0 |
progranism/Open-Source-FPGA-Bitcoin-Miner | cores/crc/crc32.v | 1,099 | module MODULE1 (
input clk,
input reset,
input VAR13,
input [7:0] VAR10,
output reg [31:0] VAR4 = 32'd0
);
localparam [31:0] VAR12 = 32'b00000100110000010001110110110111;
wire [31:0] VAR3 = reset ? 32'd0 : VAR4;
wire [7:0] byte = VAR13 ? VAR10 : 8'd0;
wire [31:0] VAR7 = {VAR3[30:0], byte[7]} ^ ({32{VAR3[31]}} & VAR12);... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2_1.v | 2,105 | module MODULE2 (
VAR6 ,
VAR5 ,
VAR9 ,
VAR3,
VAR1,
VAR4 ,
VAR2
);
output VAR6 ;
input VAR5 ;
input VAR9 ;
input VAR3;
input VAR1;
input VAR4 ;
input VAR2 ;
VAR8 VAR7 (
.VAR6(VAR6),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR6,
VAR5,
VAR9
);
output VAR6;
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfbbp/sky130_fd_sc_ls__dfbbp.symbol.v | 1,467 | module MODULE1 (
input VAR4 ,
output VAR6 ,
output VAR3 ,
input VAR2,
input VAR1 ,
input VAR10
);
supply1 VAR7;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_Leds/picoblze/uart_tx_plus.v | 4,479 | module MODULE1
( VAR3,
VAR15,
VAR8,
VAR17,
VAR10,
VAR11,
VAR16,
VAR13,
clk);
input[7:0] VAR3;
input VAR15;
input VAR8;
input VAR17;
output VAR10;
output VAR11;
output VAR16;
output VAR13;
input clk;
wire [7:0] VAR3;
wire VAR15;
wire VAR8;
wire VAR17;
wire VAR10;
wire VAR11;
wire VAR16;
wire VAR13;
wire clk;
wire [7:0] ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/nor2b/sky130_fd_sc_hdll__nor2b.pp.blackbox.v | 1,330 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR7,
VAR5,
VAR6 ,
VAR1
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR7;
input VAR5;
input VAR6 ;
input VAR1 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/bufz/gf180mcu_fd_sc_mcu7t5v0__bufz_16.behavioral.v | 1,175 | module MODULE1( VAR3, VAR4, VAR6 );
input VAR3, VAR4;
output VAR6;
VAR2 VAR1(.VAR3(VAR3),.VAR4(VAR4),.VAR6(VAR6));
VAR2 VAR5(.VAR3(VAR3),.VAR4(VAR4),.VAR6(VAR6)); | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_impctl_smachine_new.v | 4,909 | module MODULE1(VAR16 ,VAR6 ,VAR53 ,
VAR28 ,VAR7 ,VAR60 ,VAR55 ,VAR47 ,VAR50 ,VAR59 ,
VAR48 ,VAR52 ,VAR13 ,VAR1 ,VAR23 ,
VAR63 ,VAR20 ,VAR42 ,VAR40 ,VAR18 ,VAR15 ,
VAR26 ,VAR24 ,VAR58 ,VAR46 );
output [7:0] VAR16 ;
output [7:0] VAR58 ;
output [7:0] VAR46 ;
input [7:0] VAR47 ;
output VAR6 ;
output VAR20 ;
output VAR18 ;
... | gpl-2.0 |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_042.v | 1,540 | module MODULE1 (
VAR5,
VAR4
);
input [31:0] VAR5;
output [31:0]
VAR4;
wire [31:0]
VAR8,
VAR6,
VAR9,
VAR12,
VAR13,
VAR14,
VAR1,
VAR11,
VAR2;
assign VAR8 = VAR5;
assign VAR11 = VAR8 << 7;
assign VAR14 = VAR8 << 4;
assign VAR2 = VAR1 - VAR11;
assign VAR13 = VAR9 - VAR12;
assign VAR1 = VAR13 + VAR14;
assign VAR6 = VAR8 << ... | mit |
skarpenko/ultiparc | rtl/src/fabric2.v | 12,872 | module MODULE1(
clk,
VAR117,
VAR131, VAR12, VAR72, VAR122, VAR35, VAR21, VAR10,
VAR91, VAR22, VAR45, VAR39, VAR25, VAR49, VAR48,
VAR120, VAR81, VAR113, VAR4, VAR86, VAR28, VAR51,
VAR41, VAR102, VAR6, VAR96, VAR68, VAR123, VAR15,
VAR77, VAR31, VAR55, VAR46, VAR11, VAR132, VAR30,
VAR57, VAR99, VAR50, VAR116, VAR8, VAR38,... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.functional.v | 1,425 | module MODULE1 (
VAR6 ,
VAR3,
VAR7,
VAR5,
VAR10
);
output VAR6 ;
input VAR3;
input VAR7;
input VAR5;
input VAR10;
wire VAR4 ;
wire VAR9;
or VAR8 (VAR4 , VAR7, VAR3, VAR5 );
and VAR1 (VAR9, VAR4, VAR10 );
buf VAR2 (VAR6 , VAR9 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_4.behavioral.v | 1,620 | module MODULE1( VAR7, VAR4, VAR2, VAR1 );
input VAR1, VAR4, VAR2;
output VAR7;
VAR3 VAR6(.VAR7(VAR7),.VAR4(VAR4),.VAR2(VAR2),.VAR1(VAR1));
VAR3 VAR5(.VAR7(VAR7),.VAR4(VAR4),.VAR2(VAR2),.VAR1(VAR1)); | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_1.functional.v | 1,909 | module MODULE1( VAR11, VAR10, VAR5, VAR8, VAR3, VAR21, VAR23 );
input VAR23, VAR21, VAR5, VAR3, VAR10, VAR11;
output VAR8;
wire VAR15;
not VAR1( VAR15, VAR23 );
wire VAR7;
not VAR22( VAR7, VAR21 );
wire VAR25;
and VAR19( VAR25, VAR15, VAR7 );
wire VAR12;
not VAR26( VAR12, VAR5 );
wire VAR2;
not VAR6( VAR2, VAR3 );
wire... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_mux_4to2/sky130_fd_sc_hvl__udp_mux_4to2.blackbox.v | 1,302 | module MODULE1 (
VAR6 ,
VAR7,
VAR5,
VAR2,
VAR4,
VAR1,
VAR3
);
output VAR6 ;
input VAR7;
input VAR5;
input VAR2;
input VAR4;
input VAR1;
input VAR3;
endmodule | apache-2.0 |
natsutan/NPU | fpga_implement/npu8/npu8.ip_user_files/ip/mul_16_32/mul_16_32_stub.v | 1,262 | module MODULE1(VAR2, VAR3, VAR1, VAR4)
;
input VAR2;
input [15:0]VAR3;
input [31:0]VAR1;
output [47:0]VAR4;
endmodule | bsd-3-clause |
uastw-embsys/Verilog-Perl | verilog/parser_vectors.v | 1,120 | module MODULE1(VAR15,VAR4);
input [31:0] VAR15;
output [31:0] VAR4;
wire [3:0] VAR13, VAR10;
wire VAR17,VAR2,VAR9;
wire [29:0] VAR16;
parameter VAR3 = 10;
assign VAR16=VAR15[31:2];
assign VAR4[1]=VAR17;
assign VAR4[2]=VAR2;
assign VAR4[0]=1'b0;
assign VAR4[3]=VAR10[2];
assign VAR4[28:4]=25'b0;
assign VAR4[31]=~VAR17;
V... | artistic-2.0 |
jairov4/puj-ca-de1-audio-pump | ip/TERASIC_AUDIO/AUDIO_IF.v | 6,462 | module MODULE1(
VAR3,
VAR23,
VAR28,
VAR33,
VAR5,
VAR24,
VAR43,
VAR20,
VAR16,
VAR42,
VAR6,
VAR9
);
input VAR3;
input VAR23;
input [2:0] VAR28;
input VAR33;
output [15:0] VAR5;
input VAR24;
input [15:0] VAR43;
input VAR20;
input VAR16;
output VAR42;
input VAR6;
input VAR9;
reg [15:0] VAR4;
reg VAR31;
wire VAR35;
reg VAR3... | mit |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/udp/input_arbiter.v | 11,059 | module MODULE1
parameter VAR75=VAR32/8,
parameter VAR65 = 2,
parameter VAR16 = 2,
parameter VAR87 = 8
)
( output reg [VAR32-1:0] VAR52,
output reg [VAR75-1:0] VAR20,
output reg VAR28,
input VAR12,
input [VAR32-1:0] VAR63,
input [VAR75-1:0] VAR86,
input VAR6,
output VAR34,
input [VAR32-1:0] VAR57,
input [VAR75-1:0] VAR1... | lgpl-2.1 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/c7ba741286d72229/led_controller_design_auto_pc_0_stub.v | 4,499 | module MODULE1(VAR49, VAR24, VAR11, VAR21,
VAR1, VAR15, VAR26, VAR4, VAR19, VAR16,
VAR57, VAR54, VAR8, VAR13, VAR28, VAR32, VAR37,
VAR14, VAR41, VAR47, VAR43, VAR44, VAR39, VAR27,
VAR56, VAR6, VAR23, VAR48, VAR42, VAR3,
VAR50, VAR31, VAR34, VAR52, VAR33, VAR25, VAR38,
VAR36, VAR46, VAR10, VAR18, VAR55, VAR7,
VAR40, VAR... | mit |
ptracton/wb_soc_template | rtl/lm32_top/rtl/verilog/lm32_top.v | 15,142 | module MODULE1 (
VAR72,
VAR6,
VAR49,
VAR53,
VAR24,
VAR1,
VAR5,
VAR43,
VAR36,
VAR12,
VAR2,
VAR40,
VAR77,
VAR21,
VAR11,
VAR69,
VAR17,
VAR81,
VAR28,
VAR97,
VAR96,
VAR50,
VAR34,
VAR59,
VAR22,
VAR105,
VAR86,
VAR75,
VAR88,
VAR51,
VAR83,
VAR8,
VAR41,
VAR98,
VAR56,
VAR99,
VAR30,
VAR20,
VAR103,
VAR108,
VAR14,
VAR52,
VAR73,
VAR4... | mit |
FPGA1988/udp_ip_stack | Network/udp_ip_core/trunk/ic/digital/rtl/eth_tri_mode/RMON/RMON_ctrl.v | 10,097 | module MODULE1 (
VAR30 ,
VAR1 ,
VAR3 ,
VAR10 ,
VAR6 ,
VAR7 ,
VAR26 ,
VAR13 ,
VAR25 ,
VAR23 ,
VAR8 ,
VAR22 ,
VAR15 ,
VAR27 ,
VAR14 ,
VAR31 ,
VAR11 ,
VAR12
);
input VAR30 ;
input VAR1 ;
input VAR3 ;
input [4:0] VAR10 ;
input [15:0] VAR6 ;
output VAR7 ;
input VAR26 ;
input [4:0] VAR13 ;
input [15:0] VAR25 ;
output VAR23 ;... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_4.behavioral.pp.v | 3,497 | module MODULE1( VAR1, VAR2, VAR5, VAR4, VAR8, VAR10, VAR7, VAR6 );
input VAR5, VAR1, VAR2, VAR10, VAR8;
inout VAR7, VAR6;
output VAR4;
VAR9 VAR3(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8),.VAR10(VAR10),.VAR7(VAR7),.VAR6(VAR6));
VAR9 VAR11(.VAR1(VAR1),.VAR2(VAR2),.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8),.VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.blackbox.v | 1,395 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR5 ,
VAR2,
VAR4 ,
VAR6
);
output VAR1 ;
input VAR3 ;
input VAR5 ;
input VAR2;
input VAR4 ;
input VAR6 ;
endmodule | apache-2.0 |
khldragon/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/transfer_controller.v | 22,029 | module MODULE1(
input clk,
input rst,
input VAR14,
input VAR54,
output VAR9,
input [63:0] VAR59,
input VAR25,
input [31:0] VAR28,
input [31:0] VAR37,
input [31:0] VAR24,
input [23:0] VAR30,
input [7:0] VAR61,
output reg VAR32,
output reg VAR36,
input VAR39,
output reg [63:0] VAR52,
output reg [31:0] VAR13,
output reg [... | bsd-2-clause |
fabianz66/cursos-tec | taller-digital/Lab3/laboratorio3/Main_Module.v | 3,054 | module MODULE1(VAR23, reset, VAR39, VAR6, VAR15, VAR33, VAR18,
addr, VAR20,VAR29,VAR24,VAR8,VAR41);
input VAR23, reset;
input [1:0] VAR39;
output wire VAR29, VAR6, VAR15, VAR33, VAR18, VAR41;
output wire [3:0] VAR24, VAR8;
output wire [6:0] addr, VAR20;
wire [1:0] VAR19;
wire VAR22;
wire VAR10;
wire [3:0] VAR31, VAR32,... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4/sky130_fd_sc_lp__or4_2.v | 2,231 | module MODULE2 (
VAR10 ,
VAR11 ,
VAR1 ,
VAR4 ,
VAR5 ,
VAR3,
VAR2,
VAR7 ,
VAR8
);
output VAR10 ;
input VAR11 ;
input VAR1 ;
input VAR4 ;
input VAR5 ;
input VAR3;
input VAR2;
input VAR7 ;
input VAR8 ;
VAR9 VAR6 (
.VAR10(VAR10),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.... | apache-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T21-baud-tx/baudtx3.v | 2,537 | module MODULE1(input wire clk, output wire VAR5 );
parameter VAR12 = VAR7;
parameter VAR8 = VAR3;
reg [9:0] VAR14;
wire VAR4;
wire VAR9;
reg VAR10;
always @(posedge VAR4)
if (VAR10 == 0)
VAR14 <= {"VAR1",2'b01};
else
VAR14 <= {1'b1, VAR14[9:1]};
assign VAR5 = (VAR10) ? VAR14[0] : 1;
always @(posedge VAR4)
VAR10 <= VAR9... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlymetal6s4s/sky130_fd_sc_ms__dlymetal6s4s_1.v | 2,160 | module MODULE2 (
VAR7 ,
VAR1 ,
VAR5,
VAR8,
VAR3 ,
VAR2
);
output VAR7 ;
input VAR1 ;
input VAR5;
input VAR8;
input VAR3 ;
input VAR2 ;
VAR6 VAR4 (
.VAR7(VAR7),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR7,
VAR1
);
output VAR7;
input VAR1;
supply1 VAR5;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvn/sky130_fd_sc_ms__einvn_2.v | 2,150 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR1,
VAR7,
VAR9,
VAR4 ,
VAR2
);
output VAR3 ;
input VAR5 ;
input VAR1;
input VAR7;
input VAR9;
input VAR4 ;
input VAR2 ;
VAR6 VAR8 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR3 ,
VAR5 ,
VAR1
);
output VAR3 ;... | apache-2.0 |
htuNCSU/MmcCommunicationVerilog | DE2_115_MASTER/source_code/eth_miim.v | 11,306 | module MODULE1
(
VAR52,
VAR27,
VAR1,
VAR33,
VAR21,
VAR4,
VAR60,
VAR44,
VAR36,
VAR55,
VAR7,
VAR43,
VAR32,
VAR8,
VAR26,
VAR12,
VAR17,
VAR40,
VAR23,
VAR22,
VAR61
);
input VAR52; input VAR27; input [7:0] VAR1; input [15:0] VAR21; input [4:0] VAR4; input [4:0] VAR60; input VAR33; input VAR44; input VAR36; input VAR55; input... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor2b/sky130_fd_sc_hs__nor2b.pp.symbol.v | 1,292 | module MODULE1 (
input VAR1 ,
input VAR5 ,
output VAR4 ,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
mbuesch/pyprofibus | phy_fpga/edge_detect_mod.v | 1,468 | module MODULE1 #(
parameter VAR2 = 1,
) (
input wire clk,
input wire [VAR2 - 1 : 0] VAR3,
output wire [VAR2 - 1 : 0] VAR5,
output wire [VAR2 - 1 : 0] VAR4,
);
reg [VAR2 - 1 : 0] VAR1;
always @(posedge clk) begin
VAR1 <= VAR3;
end
assign VAR5 = ~VAR1 & VAR3;
assign VAR4 = VAR1 & ~VAR3;
endmodule | gpl-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_dsp/cheat.v | 15,825 | module MODULE1(
input clk,
input [7:0] VAR60,
input [23:0] VAR15,
input [7:0] VAR20,
input VAR13,
input VAR19,
input VAR58,
input VAR32,
input VAR24,
input VAR3,
input VAR72,
input VAR42,
input VAR7,
input VAR66,
input VAR5,
input VAR38,
input VAR31,
input [2:0] VAR63,
input VAR33,
input [31:0] VAR40,
input VAR41,
outp... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_inputisolatch/sky130_fd_sc_hd__lpflow_inputisolatch.symbol.v | 1,416 | module MODULE1 (
input VAR1 ,
output VAR3 ,
input VAR6
);
supply1 VAR4;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
jairov4/accel-oil | solution_spartan6/syn/verilog/sample_iterator_next.v | 21,326 | module MODULE1 (
VAR8,
VAR36,
VAR107,
VAR71,
VAR58,
VAR3,
VAR47,
VAR78,
VAR41,
VAR9,
VAR52,
VAR112,
VAR75,
VAR73,
VAR66,
VAR98,
VAR86,
VAR80,
VAR57,
VAR42,
VAR16,
VAR51,
VAR5,
VAR94,
VAR23,
VAR60,
VAR46,
VAR68,
VAR83,
VAR82,
VAR40,
VAR17,
VAR77,
VAR105,
VAR76,
VAR92,
VAR87,
VAR55
);
input VAR8;
input VAR36;
input VAR10... | lgpl-3.0 |
glennchid/font5-firmware | src/verilog/synthesis/uart2_rx.v | 3,613 | module MODULE1 #(parameter VAR1 = 8, parameter real VAR20 = 9600) (
input reset,
input clk,
input VAR4,
output reg [VAR1-1:0] VAR18 = {VAR1{1'b0}},
input VAR13,
input VAR19,
output reg VAR5 = 1'b0
);
localparam VAR15 = VAR2(VAR3/VAR20);
localparam VAR9 = VAR2(VAR1+2);
localparam [VAR15-1:0] VAR12 = VAR3/VAR20;
localpar... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp.blackbox.v | 1,327 | module MODULE1 (
VAR3 ,
VAR8 ,
VAR7 ,
VAR5
);
output VAR3 ;
output VAR8 ;
input VAR7 ;
input VAR5;
supply1 VAR4;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/lsbuflv2hv_symmetric/sky130_fd_sc_hvl__lsbuflv2hv_symmetric.pp.symbol.v | 1,430 | module MODULE1 (
input VAR2 ,
output VAR4 ,
input VAR7,
input VAR3 ,
input VAR5 ,
input VAR6 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.symbol.v | 1,318 | module MODULE1 (
input VAR2,
input VAR3,
input VAR5,
input VAR6,
output VAR4
);
supply1 VAR7;
supply0 VAR1;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/glbl.v | 1,081 | module MODULE1 ();
parameter VAR12 = 1000;
parameter VAR17 = 0;
wire VAR4;
wire VAR20;
wire VAR15;
reg VAR23;
reg VAR10;
reg VAR19;
wire VAR13;
wire VAR9;
wire VAR24;
wire VAR8;
wire VAR14;
reg VAR7;
reg VAR6;
reg VAR5;
reg VAR21;
reg VAR2 = 0;
reg VAR18 = 0 ;
reg VAR11 = 0;
reg VAR3 = 0;
reg VAR16 = 1'VAR22;
reg VAR26... | gpl-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v | 54,326 | module MODULE1 #
(
parameter VAR127 = 100, parameter VAR68 = 2, parameter VAR72 = 2500,
parameter VAR41 = 64, parameter VAR133 = 3, parameter VAR60 = 8, parameter VAR18 = 8, parameter VAR73 = "VAR43", parameter VAR24 = "VAR77" )
(
input clk,
input rst,
input VAR9,
input VAR163,
input VAR7,
input VAR192,
input VAR199,
o... | mit |
aj-michael/Digital-Systems | Lab4-Part1-40x7bit-RAM/OverallController.v | 1,305 | module MODULE1(VAR5, VAR8, VAR13, VAR10, VAR1, VAR11);
input VAR5, VAR8, VAR13, VAR10;
output reg VAR1, VAR11;
parameter VAR3 = 2'b00;
parameter VAR4 = 2'b01;
parameter VAR9 = 2'b10;
parameter VAR7 = 2'b11;
reg [2:0] VAR2;
reg [2:0] VAR12;
VAR6 VAR2 = VAR3;
VAR6 VAR12 = VAR3;
always @ (VAR2)
case (VAR2)
VAR3: begin VAR... | mit |
jotego/jt12 | hdl/jt12_pg.v | 3,005 | module MODULE1(
input clk,
input VAR8 ,
input rst,
input [10:0] VAR38,
input [ 2:0] VAR28,
input [ 3:0] VAR31,
input [ 2:0] VAR39, input [ 6:0] VAR14,
input [ 2:0] VAR24,
input VAR5,
input VAR6,
output reg [ 4:0] VAR19,
output [ 9:0] VAR7
);
parameter VAR11=6;
wire [4:0] VAR35;
wire signed [5:0] VAR4;
reg signed [5:0] ... | gpl-3.0 |
GSejas/Aproximate-Arithmetic-Operators | src_lib/addlib/ACA_II_N16_Q4.v | 1,064 | module MODULE1(
input [15:0] VAR7,
input [15:0] VAR4,
output [16:0] VAR3
);
wire [4:0] VAR6,VAR10,VAR1,VAR8,VAR2,VAR5,VAR9;
assign VAR6[4:0] = VAR7[ 3: 0] + VAR4[ 3: 0];
assign VAR10[4:0] = VAR7[ 5: 2] + VAR4[ 5: 2];
assign VAR1[4:0] = VAR7[ 7: 4] + VAR4[ 7: 4];
assign VAR8[4:0] = VAR7[ 9: 6] + VAR4[ 9: 6];
assign VAR2... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o41ai/sky130_fd_sc_ms__o41ai_4.v | 2,424 | module MODULE1 (
VAR10 ,
VAR7 ,
VAR11 ,
VAR9 ,
VAR12 ,
VAR4 ,
VAR1,
VAR2,
VAR3 ,
VAR8
);
output VAR10 ;
input VAR7 ;
input VAR11 ;
input VAR9 ;
input VAR12 ;
input VAR4 ;
input VAR1;
input VAR2;
input VAR3 ;
input VAR8 ;
VAR5 VAR6 (
.VAR10(VAR10),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR4(VAR4),
.VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu7t5v0__sdffsnq_2.functional.v | 1,734 | module MODULE1( VAR18, VAR3, VAR26, VAR22, VAR9, VAR8, VAR17 );
input VAR22, VAR26, VAR18, VAR9, VAR3, VAR17;
output VAR8;
not VAR13( VAR4, VAR9 );
wire VAR11;
not VAR1( VAR11, VAR26 );
wire VAR21;
not VAR5( VAR21, VAR18 );
wire VAR23;
and VAR16( VAR23, VAR11, VAR21 );
wire VAR19;
not VAR6( VAR19, VAR3 );
wire VAR12;
a... | apache-2.0 |
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