repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/synth/windows/ip_compiler_for_pci_express-library/altpcie_pll_100_125.v | 10,750 | module MODULE1 (
VAR40,
VAR30,
VAR24,
VAR34);
input VAR40;
input VAR30;
output VAR24;
output VAR34;
wire [5:0] VAR2;
wire VAR13;
wire [0:0] VAR19 = 1'h0;
wire [0:0] VAR36 = 1'h1;
wire [0:0] VAR41 = VAR2[0:0];
wire VAR24 = VAR41;
wire VAR34 = VAR13;
wire [5:0] VAR4 = {VAR19, VAR19, VAR19, VAR19, VAR19, VAR36};
wire VAR9... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_auto_pc_3/synth/zqynq_lab_1_design_auto_pc_3.v | 15,785 | module MODULE1 (
VAR98,
VAR67,
VAR11,
VAR25,
VAR46,
VAR63,
VAR84,
VAR60,
VAR89,
VAR29,
VAR73,
VAR91,
VAR53,
VAR3,
VAR106,
VAR16,
VAR65,
VAR95,
VAR81,
VAR69,
VAR49,
VAR32,
VAR22,
VAR110,
VAR56,
VAR70,
VAR61,
VAR105,
VAR94,
VAR112,
VAR76,
VAR2,
VAR5,
VAR96,
VAR31,
VAR90,
VAR62,
VAR13,
VAR21,
VAR1,
VAR93,
VAR44,
VAR108,
V... | mit |
skarpenko/ultiparc | rtl/src/cpu/uparc_decode.v | 14,429 | module MODULE1(
clk,
VAR5,
VAR62,
VAR75,
VAR32,
VAR44,
VAR37,
VAR23,
VAR59,
VAR38,
VAR21,
VAR26,
VAR69,
VAR60,
VAR7,
VAR24,
VAR76,
VAR45,
VAR58,
VAR78,
VAR50,
VAR65,
VAR36,
VAR17,
VAR48,
VAR18,
VAR77
);
localparam [VAR30-1:0] VAR52 = 32'h00000000;
input wire clk;
input wire VAR5;
input wire [VAR20-1:0] VAR62;
input wir... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4_0.v | 2,444 | module MODULE2 (
VAR6 ,
VAR12 ,
VAR3 ,
VAR7 ,
VAR1 ,
VAR8 ,
VAR13 ,
VAR11,
VAR2,
VAR5 ,
VAR9
);
output VAR6 ;
input VAR12 ;
input VAR3 ;
input VAR7 ;
input VAR1 ;
input VAR8 ;
input VAR13 ;
input VAR11;
input VAR2;
input VAR5 ;
input VAR9 ;
VAR10 VAR4 (
.VAR6(VAR6),
.VAR12(VAR12),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nor2/gf180mcu_fd_sc_mcu9t5v0__nor2_1.functional.v | 1,040 | module MODULE1( VAR6, VAR8, VAR2 );
input VAR2, VAR6;
output VAR8;
wire VAR3;
not VAR1( VAR3, VAR2 );
wire VAR4;
not VAR7( VAR4, VAR6 );
and VAR5( VAR8, VAR3, VAR4 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv.blackbox.v | 1,204 | module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR5;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
Tsung-Wei/OpenTimer | benchmark/c1908/c1908.v | 17,853 | module MODULE1 (
VAR326,
VAR414,
VAR379,
VAR378,
VAR127,
VAR109,
VAR204,
VAR228,
VAR330,
VAR282,
VAR452,
VAR168,
VAR313,
VAR315,
VAR340,
VAR342,
VAR216,
VAR478,
VAR200,
VAR195,
VAR223,
VAR328,
VAR373,
VAR486,
VAR332,
VAR458,
VAR278,
VAR239,
VAR253,
VAR97,
VAR67,
VAR40,
VAR53,
VAR483,
VAR169,
VAR283,
VAR424,
VAR58,
VAR6... | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/scdata/rtl/bw_clk_cl_scdata_cmp.v | 2,433 | module MODULE1 (VAR19 ,VAR16 ,VAR1 ,VAR7 ,VAR5 ,
VAR10,VAR13 ,VAR15 ,VAR2 ,VAR11 ,VAR18, VAR14 ,VAR4 );
output VAR19 ;
input VAR16 ;
input VAR1 ;
input [1:0] VAR7 ;
input VAR15 ;
output VAR5 ;
output VAR10 ;
output VAR13 ;
input VAR2 ;
input VAR11 ;
input VAR18 ;
input VAR14 ;
input VAR4 ;
wire VAR3 ;
wire VAR9 ;
wire ... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxtp/sky130_fd_sc_ls__dfxtp.blackbox.v | 1,262 | module MODULE1 (
VAR1 ,
VAR2,
VAR3
);
output VAR1 ;
input VAR2;
input VAR3 ;
supply1 VAR5;
supply0 VAR4;
supply1 VAR7 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
Jside/pdp1 | pdp1_memory.v | 1,479 | module MODULE1(VAR4, VAR2,
VAR1, VAR6, VAR3, VAR5);
input VAR4;
input VAR2;
input VAR1;
input [0:11] VAR6;
output [0:17] VAR3;
input [0:17] VAR5;
reg [0:18] VAR7 [0:4095];
integer VAR8;
assign VAR3 = (~VAR1) ? VAR7[VAR6] : 18'h00000;
always @(posedge VAR4) begin
if(VAR2) begin
for(VAR8 = 0; VAR8 < 4095; VAR8 = VAR8 + 1... | gpl-3.0 |
titets/MILL | rtl/millcpu.v | 1,042 | module MODULE1(
input wire clk, rst,
input wire [VAR1-1:0] VAR21,
output wire VAR8,
output wire [VAR1-1:0] VAR11, VAR26, VAR18
);
wire VAR12, VAR28, VAR6, VAR4;
wire [VAR7-1:0] VAR3;
wire [VAR2-1:0] VAR23, VAR20, VAR30;
wire [VAR1-1:0] VAR15, VAR16, dout;
assign VAR26 = VAR15;
assign VAR18 = VAR16;
VAR13 VAR13(
.clk(cl... | gpl-3.0 |
jaygreco/Peak-Current-Halfbridge | PeakCurrentHB.v | 2,565 | module MODULE1(clk, VAR14, VAR6, VAR11, VAR9, VAR1);
input clk, VAR14;
input [7:0] VAR6, VAR11;
output reg VAR9, VAR1;
reg [7:0] VAR13 = 0;
reg [7:0] VAR7 = 0;
reg [7:0] VAR15 = 0;
reg VAR3;
wire [7:0] VAR8, VAR12, VAR2;
wire VAR4, VAR5, VAR10;
begin
begin | mit |
Darkin47/Zynq-TX-UTT | Vivado/image_conv_2D/image_conv_2D.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_protocol_converter_v2_1/hdl/verilog/axi_protocol_converter_v2_1_b2s_b_channel.v | 5,685 | module MODULE1 #
(
parameter integer VAR23 = 4
)
(
input wire clk,
input wire reset,
output wire [VAR23-1:0] VAR9,
output wire [1:0] VAR50,
output wire VAR27,
input wire VAR47,
input wire [1:0] VAR16,
input wire VAR38,
output wire VAR33,
input wire VAR30,
input wire [VAR23-1:0] VAR4,
input wire [7:0] VAR48,
input wire ... | gpl-3.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_deltas_m1.v | 57,248 | module MODULE1 (
VAR184,
VAR17,
VAR300,
VAR264,
VAR146,
VAR400,
VAR53,
VAR54,
VAR58,
VAR83,
VAR287,
VAR155,
VAR339,
VAR43,
VAR200,
VAR262,
VAR253,
VAR176,
VAR222,
VAR261,
VAR411,
VAR98,
VAR387,
VAR117,
VAR346,
VAR338,
VAR180,
VAR335,
VAR39,
VAR147,
VAR89,
VAR212,
VAR234,
VAR245,
VAR78,
VAR51,
VAR179,
VAR4,
VAR362
);
pa... | apache-2.0 |
Obijuan/ACC | hw/roadmap/01-click-counter1/click_counter.v | 1,203 | module MODULE1 (input clk,
input rst,
output VAR6,
output VAR2,
output VAR9,
output VAR14,
output VAR16,
output VAR15,
output VAR17,
output VAR12);
wire VAR13, VAR3;
wire VAR1, VAR20;
VAR4 #(
.VAR19(6'VAR18 101001),
.VAR11(1'VAR18 1)
) VAR5 (
.VAR8(clk),
.VAR7(VAR3)
);
VAR4 #(
.VAR19(6'VAR18 101001),
.VAR11(1'VAR18 1)
... | gpl-3.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/pixelq_op_v1_0/0d718de5/hdl/verilog/pixelq_op_AXIvideo2Mat.v | 27,588 | module MODULE1 (
VAR37,
VAR115,
VAR103,
VAR9,
VAR75,
VAR60,
VAR88,
VAR106,
VAR114,
VAR43,
VAR108,
VAR29,
VAR78,
VAR122,
VAR40,
VAR117,
VAR93,
VAR85,
VAR16,
VAR65,
VAR50,
VAR70,
VAR84,
VAR14,
VAR63,
VAR120,
VAR25,
VAR57,
VAR1,
VAR104,
VAR100,
VAR105,
VAR4,
VAR68,
VAR55,
VAR64,
VAR56,
VAR58,
VAR6
);
parameter VAR34 = 1'b... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21a/sky130_fd_sc_lp__o21a.behavioral.v | 1,508 | module MODULE1 (
VAR2 ,
VAR5,
VAR3,
VAR13
);
output VAR2 ;
input VAR5;
input VAR3;
input VAR13;
supply1 VAR9;
supply0 VAR1;
supply1 VAR12 ;
supply0 VAR8 ;
wire VAR11 ;
wire VAR10;
or VAR7 (VAR11 , VAR3, VAR5 );
and VAR6 (VAR10, VAR11, VAR13 );
buf VAR4 (VAR2 , VAR10 );
endmodule | apache-2.0 |
alexforencich/xfcp | lib/eth/rtl/eth_phy_10g_rx.v | 3,785 | module MODULE1 #
(
parameter VAR4 = 64,
parameter VAR3 = (VAR4/8),
parameter VAR9 = 2,
parameter VAR8 = 0,
parameter VAR12 = 0,
parameter VAR18 = 0,
parameter VAR5 = 0,
parameter VAR17 = 1,
parameter VAR14 = 8,
parameter VAR20 = 125000/6.4
)
(
input wire clk,
input wire rst,
output wire [VAR4-1:0] VAR16,
output wire [V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.pp.blackbox.v | 1,281 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR2 ,
VAR6 ,
VAR1,
VAR4,
VAR3 ,
VAR7
);
output VAR5 ;
input VAR8 ;
input VAR2 ;
input VAR6 ;
input VAR1;
input VAR4;
input VAR3 ;
input VAR7 ;
endmodule | apache-2.0 |
hcabrera-/lancetfish | RTL/router/rtl/arbiter.v | 6,691 | module MODULE1
(
input wire clk,
input wire [3:0] VAR7,
input wire VAR3,
input wire VAR6,
output wire [3:0] VAR16
);
localparam VAR8 = 4'b0001;
localparam VAR5 = 4'b0010;
localparam VAR14 = 4'b0100;
localparam VAR12 = 4'b1000;
localparam VAR11 = 2'b01;
localparam VAR1 = 2'b10;
localparam VAR9 = 2'b11;
localparam VAR2 =... | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/b9c82e235214f825/zqynq_lab_1_design_auto_pc_2_stub.v | 4,668 | module MODULE1(VAR1, VAR51, VAR26, VAR43,
VAR58, VAR25, VAR28, VAR11, VAR53, VAR39,
VAR60, VAR30, VAR34, VAR40, VAR49, VAR47,
VAR21, VAR23, VAR36, VAR56, VAR3, VAR2, VAR14,
VAR48, VAR4, VAR18, VAR45, VAR10, VAR6,
VAR19, VAR24, VAR31, VAR54, VAR22, VAR35,
VAR16, VAR8, VAR55, VAR9, VAR50, VAR15, VAR27,
VAR7, VAR59, VAR33... | mit |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/Main.v | 23,043 | module MODULE1(
input VAR82,
output VAR188,
output VAR223,
output VAR49,
input VAR81,
inout [15:0] VAR65,
inout VAR227,
inout [35:0] VAR74,
inout [35:0] VAR23,
input VAR234,
output [28:0] VAR72,
output [7:0] VAR162,
input VAR92,
input [63:0] VAR126,
input VAR170,
output VAR148,
output [28:0] VAR105,
output [7:0] VAR272... | apache-2.0 |
monotone-RK/FACE | IEICE-Trans/16-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.v | 7,237 | module MODULE1(VAR38, VAR22, VAR74, VAR84, VAR40, VAR82, VAR80, VAR42, VAR53, VAR64, VAR5, VAR43, VAR34, VAR76, VAR33, VAR21, VAR81, VAR46, VAR39, VAR52, VAR11, VAR31, VAR3, VAR18, VAR44, VAR75, VAR66, VAR50, VAR59, VAR45, VAR19, VAR70, VAR13, VAR55, VAR65, VAR32, VAR2, VAR9, VAR28, VAR57, VAR71, VAR72, VAR86, VAR77, V... | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_pipe_sync.v | 24,502 | module MODULE1 #
(
parameter VAR25 = "VAR96", parameter VAR14 = "VAR8", parameter VAR68 = "VAR11", parameter VAR45 = 0, parameter VAR62 = 0, parameter VAR53 = 1, parameter VAR52 = 3, parameter VAR72 = 0, parameter VAR102 = 0
)
(
input VAR51,
input VAR17,
input VAR27,
input VAR44,
input VAR75,
input VAR56,
input VAR5,
i... | mit |
andrewandrepowell/axiplasma | hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/example_design/rtl/traffic_gen/mig_7series_v4_0_cmd_prbs_gen_axi.v | 10,316 | module MODULE1 #
(
parameter VAR18 = 100,
parameter VAR11 = "VAR6",
parameter VAR3 = 29,
parameter VAR9 = 32,
parameter VAR25 = "VAR17", parameter VAR21 = 64, parameter VAR27 = 32,
parameter VAR12 = 32'hFFFFD000,
parameter VAR20 = 32'h00002000,
parameter VAR7 = 32'h00002000,
parameter VAR22 = 32'h00002000
)
(
input VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtn/sky130_fd_sc_lp__dlrtn.pp.symbol.v | 1,420 | module MODULE1 (
input VAR1 ,
output VAR6 ,
input VAR7,
input VAR5 ,
input VAR4 ,
input VAR8 ,
input VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.v | 2,262 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR8 ,
VAR1,
VAR6,
VAR9,
VAR10 ,
VAR5
);
output VAR3 ;
output VAR4 ;
input VAR8 ;
input VAR1;
input VAR6;
input VAR9;
input VAR10 ;
input VAR5 ;
VAR7 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR10(VAR10),
.VAR5(VAR5)
);
endmodule
module MODULE1... | apache-2.0 |
freecores/eco32 | fpga/src/cpu/cpu.v | 83,155 | module MODULE4(clk, reset,
VAR187, VAR7, VAR8, VAR76,
VAR246, VAR196, VAR205,
irq);
input clk; input reset; output VAR187; output VAR7; output [1:0] VAR8; output [31:0] VAR76; input [31:0] VAR246; output [31:0] VAR196; input VAR205; input [15:0] irq;
wire [31:0] VAR192; wire VAR232; wire [2:0] VAR248; wire [31:0] VAR18... | bsd-2-clause |
545/Atari7800 | core/ag_6502/trunk/juke-box/ag_6502.v | 8,439 | module MODULE1(input VAR152, output VAR38, output VAR138);
wire VAR142;
not(VAR38,VAR152);
or(VAR142,~VAR152, VAR38);
not(VAR138, VAR142);
endmodule
module MODULE4(input VAR109, input VAR152, output reg VAR38);
parameter VAR70 = 1; VAR17 VAR38 = 0;
integer VAR58 = 0;
always @(posedge VAR109) begin
if (VAR152 != VAR38) ... | gpl-2.0 |
jkanasu/utl | lab14eve16/asic/j05a_fsmMealyWithOverlap.v | 1,278 | module MODULE1(VAR3, VAR4, reset, VAR11);
output reg VAR3;
input VAR4, reset, VAR11;
reg[2:0] VAR7, VAR9;
parameter VAR10 = 3'b000;
parameter VAR8 = 3'b001;
parameter VAR1 = 3'b010;
parameter VAR5 = 3'b011;
parameter VAR6 = 3'b100;
parameter VAR2 = 3'b101;
always @(posedge VAR4)
begin
if(reset)
VAR7 <= VAR10;
end
else
... | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-C/dyn_pll_ctrl.v | 3,424 | module MODULE1 # (parameter VAR9 = 25, parameter VAR3 = 100, parameter VAR13 = 25, parameter VAR11 = 100)
(clk,
VAR1,
VAR8,
VAR15,
VAR6,
VAR7,
VAR10,
reset,
VAR2,
VAR16);
input clk; input VAR1; input [7:0] VAR8;
input VAR15;
output reg VAR6 = 0;
output reg VAR7 = 0;
output reg VAR10 = 0;
output reg reset = 0;
input VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4bb/sky130_fd_sc_hs__or4bb.behavioral.pp.v | 1,890 | module MODULE1 (
VAR1,
VAR11,
VAR9 ,
VAR14 ,
VAR4 ,
VAR15 ,
VAR5
);
input VAR1;
input VAR11;
output VAR9 ;
input VAR14 ;
input VAR4 ;
input VAR15 ;
input VAR5 ;
wire VAR5 VAR3 ;
wire VAR2 ;
wire VAR12;
nand VAR8 (VAR3 , VAR5, VAR15 );
or VAR6 (VAR2 , VAR4, VAR14, VAR3 );
VAR7 VAR13 (VAR12, VAR2, VAR1, VAR11);
buf VAR10... | apache-2.0 |
grindars/bfcore | Nexys2Top.v | 1,440 | module MODULE1(
input VAR5,
input VAR7,
input VAR18,
output VAR24
);
wire VAR6, VAR22;
wire [7:0] VAR27, VAR21;
wire VAR15, VAR12, VAR1, VAR20;
VAR23 #(
.VAR14(16)
) VAR25 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR22(VAR22)
);
VAR28 #(
.VAR8(12)
) VAR13 (
.VAR19(VAR6),
.VAR22(VAR22),
.VAR27(VAR27),
.VAR21(VAR21),
.V... | gpl-3.0 |
SiLab-Bonn/basil | basil/firmware/modules/utils/cdc_syncfifo.v | 5,380 | module MODULE6 #(
parameter VAR5 = 32,
parameter VAR26 = 2
) (
output wire [VAR5-1:0] VAR29,
output wire VAR31,
output wire VAR36,
input wire [VAR5-1:0] VAR30,
input wire VAR27, VAR37, VAR13,
input wire VAR32, VAR3, VAR7
);
wire [VAR26-1:0] VAR22, VAR18;
wire [VAR26:0] VAR15, VAR17, VAR19, VAR21;
MODULE2 #(
.VAR28(VAR2... | bsd-3-clause |
kyflores/ice-mc | rtl/quadrature_decoder.v | 1,677 | module MODULE1(
VAR6,
VAR7,
VAR1,
clk,
VAR11,
VAR2,
VAR9,
VAR3,
VAR12,
VAR5,
VAR4,
VAR10
);
output VAR6, VAR7, VAR1, VAR12, VAR5, VAR4, VAR10;
input clk, VAR11, VAR2, VAR9, VAR3;
wire VAR8, VAR11, VAR2, VAR9, VAR3;
reg VAR6, VAR7, VAR1;
reg VAR12, VAR5, VAR4, VAR10;
always @(posedge clk) begin
if (VAR2) begin
VAR5 <= 0... | mit |
SymbiFlow/fpga-tool-perf | third_party/daisho-usb3/usb3_ep.v | 5,002 | module MODULE1 (
input wire VAR43,
input wire VAR18,
input wire VAR22,
input wire VAR46,
input wire VAR37,
input wire [8:0] VAR9,
input wire [31:0] VAR38,
input wire VAR5,
output wire VAR2,
output wire VAR56,
input wire VAR54,
input wire [10:0] VAR51,
output wire VAR25,
input wire [8:0] VAR28,
output wire [31:0] VAR41,... | isc |
freecores/btcminer | fpga/ztex_ufm1_15b1.v | 3,697 | module MODULE1 (VAR16, reset, VAR59, VAR13, VAR2, VAR17, VAR64, VAR62, VAR38, read, write);
input VAR16, reset, VAR59, VAR13, VAR2, VAR17, VAR64, VAR62, VAR38;
input [7:0] read;
output [7:0] write;
reg [3:0] VAR42, VAR12;
reg VAR27, VAR63, VAR36;
reg VAR3, VAR28, VAR4;
reg [4:0] VAR61;
reg [351:0] VAR26, VAR8;
reg [95:... | gpl-3.0 |
Jafet95/proy_3_grupo_2_sem_1_2016 | top_pruebas_controlador_VGA.v | 3,233 | module MODULE1
(
input VAR23, reset,
input [1:0]VAR6,
output VAR24, VAR4,
output [7:0]VAR2
);
wire [3:0] VAR1, VAR18, VAR29, VAR10, VAR12, VAR35,VAR14, VAR31, VAR34, VAR16, VAR13, VAR11,VAR8, VAR20, VAR15, VAR7, VAR25, VAR33;
wire VAR28;
wire [1:0] VAR17;
wire [1:0] VAR21;
wire VAR22;wire VAR3;
VAR30 VAR32
(
.VAR6(VAR6... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/cpc/dpram.v | 10,674 | module MODULE1 (
VAR6,
VAR39,
VAR23,
VAR31,
VAR20,
VAR12,
VAR14,
VAR48,
VAR26,
VAR40);
input [15:0] VAR6;
input [15:0] VAR39;
input VAR23;
input VAR31;
input [7:0] VAR20;
input [7:0] VAR12;
input VAR14;
input VAR48;
output [7:0] VAR26;
output [7:0] VAR40;
tri1 VAR23;
tri0 VAR14;
tri0 VAR48;
wire [7:0] VAR29;
wire [7:0]... | gpl-3.0 |
ptracton/pmodacl2 | rtl/spi_controller.v | 12,731 | module MODULE1 (
VAR17, VAR36, VAR8, VAR44, VAR6, VAR38, VAR33, VAR11,
VAR2, VAR43,
clk, rst, VAR15, VAR20, VAR19
) ;
input wire clk;
input wire rst;
input wire VAR20; input wire [7:0] VAR19; input wire [7:0] VAR15;
output reg [7:0] VAR17; output reg [7:0] VAR36; output reg [7:0] VAR8; output reg VAR44; output reg VAR6... | mit |
lvd2/ngs | fpga/current/memmap/memmap.v | 3,172 | module MODULE1(
VAR20,VAR1,
VAR7, VAR21, VAR13,
VAR19,VAR16, VAR15,VAR18, VAR2,VAR12,
VAR4, VAR8, VAR23, VAR5,
VAR6,
VAR17, VAR24,
VAR25, VAR3, VAR9, VAR14, VAR22, VAR10 );
input VAR20,VAR1;
input VAR7,VAR21,VAR13;
output reg VAR19, VAR16, VAR15, VAR18, VAR2, VAR12;
output reg VAR4,VAR8,VAR23,VAR5;
output reg VAR6;
out... | gpl-3.0 |
jakubfi/mera400f | src/mera400f.v | 6,954 | module MODULE1(
input VAR8,
input VAR26,
output VAR86,
output VAR125, VAR129, VAR36,
output [17:0] VAR56,
inout [15:0] VAR91,
output [0:15] VAR107,
output [10:0] VAR29,
output [0:9] VAR42
);
parameter VAR83;
localparam VAR5 = VAR83;
localparam VAR20 = VAR83;
wire VAR40 = VAR8;
wire VAR21 = VAR8;
wire VAR95 = VAR8;
wire... | gpl-2.0 |
SymbiFlow/symbiflow-arch-defs | xc/xc7/techmap/cells_map.v | 409,001 | module MODULE24(input VAR58, VAR34, output VAR65, VAR130);
parameter VAR36 = 0;
parameter VAR49 = 0;
parameter VAR147 = 0;
parameter VAR89 = 0;
localparam VAR88 = VAR36 == 0 || VAR49 == 0;
localparam VAR321 = VAR147 == 0 || VAR89 == 1;
if(VAR88) begin
assign VAR65 = VAR58;
end else begin
VAR156 VAR23(
.VAR73(VAR65)
);
... | isc |
SI-RISCV/e200_opensource | rtl/e203/debug/sirv_debug_module.v | 19,098 | module MODULE1
parameter VAR12 = 1,
parameter VAR103 = 2,
parameter VAR42 = 32,
parameter VAR201 = 1,
parameter VAR101 = 1
) (
output VAR204,
input [VAR42-1:0] VAR88,
input VAR62,
input [3-1:0] VAR214,
input VAR73,
input VAR142,
input VAR50 ,
input VAR125 ,
input VAR20,
input [32-1:0] VAR36 ,
output[32-1:0] VAR156 ,
ou... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu7t5v0__sdffrnq_4.behavioral.pp.v | 18,378 | module MODULE1( VAR189, VAR118, VAR65, VAR247, VAR256, VAR243, VAR36, VAR286 );
input VAR247, VAR65, VAR256, VAR189, VAR118;
inout VAR36, VAR286;
output VAR243;
reg VAR90;
VAR216 VAR68(.VAR189(VAR189),.VAR118(VAR118),.VAR65(VAR65),.VAR247(VAR247),.VAR256(VAR256),.VAR243(VAR243),.VAR36(VAR36),.VAR286(VAR286),.VAR90(VAR9... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrbn/sky130_fd_sc_ls__dlrbn.behavioral.pp.v | 2,608 | module MODULE1 (
VAR19 ,
VAR3 ,
VAR26,
VAR10 ,
VAR25 ,
VAR9 ,
VAR8 ,
VAR20 ,
VAR2
);
output VAR19 ;
output VAR3 ;
input VAR26;
input VAR10 ;
input VAR25 ;
input VAR9 ;
input VAR8 ;
input VAR20 ;
input VAR2 ;
wire VAR6 ;
wire VAR16 ;
reg VAR1 ;
wire VAR24 ;
wire VAR17 ;
wire VAR5 ;
wire VAR15;
wire VAR23 ;
wire VAR21 ;
... | apache-2.0 |
EmbeddedANT/XILINX_Spartan3AN-StarterKit | Spartan3AN_PicoBlaze_LCD/picoblze/uart_tx.v | 4,278 | module MODULE1
( VAR18,
VAR12,
VAR3,
VAR9,
VAR14,
VAR4,
VAR17,
clk);
input[7:0] VAR18;
input VAR12;
input VAR3;
input VAR9;
output VAR14;
output VAR4;
output VAR17;
input clk;
wire [7:0] VAR18;
wire VAR12;
wire VAR3;
wire VAR9;
wire VAR14;
wire VAR4;
wire VAR17;
wire clk;
wire [7:0] VAR8;
wire VAR11;
wire VAR2;
VAR1 VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o31ai/sky130_fd_sc_ms__o31ai.behavioral.v | 1,543 | module MODULE1 (
VAR9 ,
VAR13,
VAR7,
VAR10,
VAR12
);
output VAR9 ;
input VAR13;
input VAR7;
input VAR10;
input VAR12;
supply1 VAR8;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR11 ;
wire VAR14 ;
wire VAR5;
or VAR6 (VAR14 , VAR7, VAR13, VAR10 );
nand VAR2 (VAR5, VAR12, VAR14 );
buf VAR1 (VAR9 , VAR5 );
endmodule | apache-2.0 |
m13253/riscade | hdl/src/step_ex_st.v | 1,546 | module MODULE1(clk, rst, VAR10, VAR6,
VAR1, VAR9, VAR11,
VAR2, VAR3);
input clk;
input rst;
input VAR10;
output VAR6;
output VAR1;
output[7:0] VAR9;
output[7:0] VAR11;
input[7:0] VAR2, VAR3;
reg VAR4;
assign VAR6 = VAR4 ? 1'b0 : 1'VAR8;
reg VAR5;
assign VAR1 = VAR5 ? 1'b0 : 1'VAR8;
reg VAR7;
assign VAR9 = VAR7 ? VAR3 :... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o22a/sky130_fd_sc_hs__o22a.symbol.v | 1,327 | module MODULE1 (
input VAR4,
input VAR5,
input VAR6,
input VAR1,
output VAR7
);
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah_4.v | 2,283 | module MODULE1 (
VAR6,
VAR2 ,
VAR11 ,
VAR10 ,
VAR8 ,
VAR3,
VAR5,
VAR9 ,
VAR1
);
output VAR6;
output VAR2 ;
input VAR11 ;
input VAR10 ;
input VAR8 ;
input VAR3;
input VAR5;
input VAR9 ;
input VAR1 ;
VAR7 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.V... | apache-2.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/Exponential/Deslinealizador.v | 6,046 | module MODULE1#(parameter VAR51 = 32)(
input wire VAR27, input wire [VAR51-1:0] VAR26, input wire VAR9, input wire VAR39, output wire VAR36, output wire VAR31,
output wire VAR43,
output wire VAR44,
output wire VAR53,
output wire VAR46, output wire VAR57, output wire VAR14, output wire VAR8, output wire VAR61, output wi... | gpl-3.0 |
stanford-ppl/spatial-lang | spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_avlmm_pr_freeze_bridge_1/synth/ghrd_10as066n2_avlmm_pr_freeze_bridge_1.v | 7,375 | module MODULE1 (
input wire VAR17, input wire VAR25, output wire VAR22, input wire VAR18, output wire VAR14, input wire VAR35, input wire [31:0] VAR16, input wire [3:0] VAR12, input wire [31:0] VAR20, output wire [31:0] VAR28, input wire [2:0] VAR30, output wire VAR1, input wire VAR3, input wire VAR15, output wire [1:0... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/fah/sky130_fd_sc_ms__fah_1.v | 2,283 | module MODULE2 (
VAR10,
VAR4 ,
VAR6 ,
VAR3 ,
VAR9 ,
VAR1,
VAR7,
VAR2 ,
VAR11
);
output VAR10;
output VAR4 ;
input VAR6 ;
input VAR3 ;
input VAR9 ;
input VAR1;
input VAR7;
input VAR2 ;
input VAR11 ;
VAR8 VAR5 (
.VAR10(VAR10),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR... | apache-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/mac_core/altera_tse_false_path_marker.v | 2,665 | module MODULE1
parameter VAR3 = 1
)
(
input reset,
input clk,
input [VAR3 - 1 : 0] VAR1,
output [VAR3 - 1 : 0] VAR4
);
reg [VAR3 - 1 : 0] VAR2;
assign VAR4 = VAR2;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
VAR2 <= {VAR3{1'b0}};
end
else
begin
VAR2 <= VAR1;
end
end
endmodule | apache-2.0 |
Kumikomi/openreroc_pwm | hardware/src/pwm_ctl.v | 1,431 | module MODULE1(
input clk,
input rst,
input [14:0] VAR1,
input [0:0] VAR4,
output [0:0] VAR8,
output [0:0] VAR7
);
parameter VAR6 = 19999;
reg VAR3;
reg VAR3;
reg en;
reg [14:0] in;
reg [31:0] counter;
wire [31:0] VAR5;
reg [31:0] VAR9;
VAR2 VAR9 = VAR6;
VAR2 in = VAR6;
assign VAR5 = VAR9 - in;
assign VAR8 = VAR3;
assi... | bsd-3-clause |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkBoot_ROM.v | 57,603 | module MODULE1(VAR26,
VAR100,
VAR164,
VAR63,
VAR121,
VAR146,
VAR145,
VAR4,
VAR104,
VAR90,
VAR45,
VAR31,
VAR147,
VAR86,
VAR56,
VAR171,
VAR127,
VAR163,
VAR13,
VAR52,
VAR177,
VAR58,
VAR49,
VAR8,
VAR81,
VAR65,
VAR48,
VAR2,
VAR50,
VAR12,
VAR172,
VAR16,
VAR82,
VAR92,
VAR174,
VAR175,
VAR160,
VAR128,
VAR131,
VAR109,
VAR156,
VA... | apache-2.0 |
ymei/TMSPlane | Firmware/src/aurora64b66b/TE07412C1/aurora_64b66b_0_gt_common_wrapper.v | 9,477 | module MODULE1
(
output VAR41,
output VAR57,
input VAR67,
output VAR21,
input VAR55,
output VAR26,
input [7:0] VAR3,
input [15:0] VAR74,
input VAR52,
input VAR2,
input VAR63,
output [15:0] VAR54,
output VAR22
);
parameter VAR69 = "VAR29";
wire VAR17;
wire [63:0] VAR1;
wire VAR13;
assign VAR17 = 1'b0;
assign VAR1 = 64'h... | bsd-3-clause |
gigglesninja/digital-system-design | lab8_uart_tx/ipcore_dir/fifo.v | 13,637 | module MODULE1(
clk,
rst,
din,
VAR51,
VAR78,
dout,
VAR57,
VAR336
);
input clk;
input rst;
input [7 : 0] din;
input VAR51;
input VAR78;
output [7 : 0] dout;
output VAR57;
output VAR336;
VAR213 #(
.VAR75(0),
.VAR335(0),
.VAR405(0),
.VAR193(0),
.VAR97(0),
.VAR378(0),
.VAR331(0),
.VAR237(32),
.VAR292(1),
.VAR30(1),
.VAR141... | gpl-2.0 |
varunnagpaal/Digital-Hardware-Modelling | xilinx-vivado/snickerdoodle_try/snickerdoodle_try.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_stub.v | 2,234 | module MODULE1(VAR8, VAR2, VAR5, VAR22,
VAR14, VAR3, VAR1, VAR6, VAR10, VAR7, VAR12, VAR21, VAR11,
VAR17, VAR9, VAR4, VAR15, VAR19, VAR18, VAR20, VAR13, VAR16)
;
output VAR8;
inout [53:0]VAR2;
inout VAR5;
inout VAR22;
inout VAR14;
inout VAR3;
inout VAR1;
inout VAR6;
inout VAR10;
inout VAR7;
inout VAR12;
inout [2:0]VAR2... | mit |
scalable-networks/ext | uhd/fpga/usrp2/vrt/vita_tx_engine_glue.v | 4,518 | module MODULE1
parameter VAR8 = 0,
parameter VAR17 = 10,
parameter VAR22 = 0,
parameter VAR16 = 0
)
(
input VAR15, input reset, input VAR11,
input VAR9, input [7:0] VAR6, input [31:0] VAR5,
input VAR20, input [7:0] VAR12, input [31:0] VAR21,
output VAR23,
output VAR13,
input VAR27,
output VAR25,
output VAR24,
output [V... | gpl-2.0 |
camsoupa/cc3000 | cc3000fpga/component/Actel/DirectCore/CoreAPB3/4.0.100/rtl/vlog/amba_bfm/bfm_apbslaveext.v | 30,135 | module
MODULE1
(
VAR237
,
VAR179
,
VAR153
,
VAR228
,
VAR31
,
VAR197
,
VAR218
,
VAR212
,
VAR86
,
VAR274
,
VAR262
,
VAR88
,
VAR152
,
VAR49
,
VAR104
)
;
parameter
VAR207
=
10
;
parameter
VAR190
=
256
;
parameter
VAR46
=
32
;
parameter
VAR91
=
2
;
parameter
VAR236
=
" "
;
parameter
VAR184
=
0
;
parameter
VAR19
=
1
;
parame... | mit |
mammenx/synesthesia_moksha | wxp/dgn/rtl/altera/lpddr2_cntrlr/lpddr2_cntrlr/lpddr2_cntrlr_p0_acv_hard_io_pads.v | 11,416 | module MODULE1(
VAR65,
VAR139,
VAR45,
VAR97,
VAR20,
VAR89,
VAR100,
VAR36,
VAR27,
VAR123,
VAR15,
VAR10,
VAR49,
VAR147,
VAR37,
VAR33,
VAR16,
VAR42,
VAR142,
VAR129,
VAR145,
VAR67,
VAR43,
VAR25,
VAR29,
VAR143,
VAR14,
VAR108,
VAR101,
VAR54,
VAR124,
VAR7,
VAR81,
VAR4,
VAR38,
VAR71,
VAR95,
VAR137,
VAR56,
VAR128,
VAR5,
VAR47,
... | gpl-3.0 |
HSID/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/pcie_dma_engine/tx_engine.v | 12,232 | module MODULE1(
input clk,
input VAR16,
input VAR13,
input [31:0] VAR17, output [11:0] VAR36,
input [15:0] VAR56,
output [63:0] VAR20,
output [7:0] VAR51,
output VAR14,
output VAR25,
output VAR6,
output VAR37,
input VAR47,
input VAR44,
output VAR50,
input [2:0] VAR1,
input VAR33,
input [63:0] VAR59,
input VAR2,
input [... | bsd-2-clause |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mem/db_lcu_ram.v | 4,211 | module MODULE1(
VAR17 ,
VAR5 ,
VAR14 ,
VAR15 ,
VAR18 ,
VAR10 ,
VAR21 ,
VAR12 ,
VAR13 ,
VAR4 ,
VAR7 ,
VAR2 ,
VAR16 ,
VAR19
);
parameter VAR8 = 128 ;
parameter VAR3 = 8 ;
input VAR17 ; input VAR5 ; input VAR14 ; input VAR15 ; input [VAR3-1:0] VAR18; input [VAR8-1:0] VAR21; output [VAR8-1:0] VAR10;
input VAR12 ; input VAR... | gpl-3.0 |
parallella/oh | common/hdl/oh_par2ser.v | 2,460 | module MODULE1 #(parameter VAR12 = 64, parameter VAR2 = 1, parameter VAR5 = VAR15(VAR12/VAR2) )
(
input clk, input VAR6, input [VAR12-1:0] din, output [VAR2-1:0] dout, output VAR10, input VAR7, input VAR14, input [7:0] VAR8, input VAR16, input VAR17, input VAR4, output VAR11 );
reg [VAR12-1:0] VAR9;
reg [VAR5-1:0] VAR3... | mit |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_adc_common.v | 21,449 | module MODULE1 (
VAR110,
VAR99,
VAR104,
VAR135,
VAR131,
VAR38,
VAR69,
VAR8,
VAR32,
VAR106,
VAR133,
VAR46,
VAR5,
VAR17,
VAR78,
VAR84,
VAR45,
VAR6,
VAR48,
VAR123,
VAR50,
VAR29,
VAR68,
VAR10,
VAR124,
VAR113,
VAR82,
VAR90,
VAR88,
VAR61,
VAR107,
VAR116,
VAR34,
VAR35,
VAR140,
VAR23,
VAR44,
VAR3,
VAR132,
VAR56,
VAR70,
VAR66,
... | mit |
asicguy/gplgpu | hdl/vga/grap_data_wr.v | 9,574 | module MODULE1
(
input [31:0] VAR66,
input VAR11,
input VAR6, input VAR51, input VAR8, input VAR63, input [3:0] VAR61,
input [3:0] VAR57,
input [4:0] VAR64,
input [7:0] VAR28,
input [31:0] VAR17,
output [31:0] VAR14
);
reg [31:0] VAR41;
reg [7:0] VAR35;
reg VAR58;
reg VAR48;
reg VAR50;
reg VAR37;
reg [7:0] VAR24;
reg [... | gpl-3.0 |
peteg944/music-fpga | Experimental/RainbowMatrix and Partial Spectrum/animation.v | 12,279 | module MODULE1(clk, rst, VAR20, VAR14, VAR24, VAR25, VAR29, VAR12);
input clk, rst, VAR25, VAR29; input [8:0] VAR14;
input [7:0] VAR12;
output reg [47:0] VAR24;
reg [23:0] VAR17, VAR11;
input[3:0] VAR20;
integer VAR5 = 0;
reg [3:0] VAR8;
reg [4:0] VAR7 [0:15] ;
reg [7:0] VAR1;
parameter VAR3 = {8'd0 , 8'd0, 8'd255};
pa... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrtn/sky130_fd_sc_hs__dlrtn.blackbox.v | 1,313 | module MODULE1 (
VAR4,
VAR5 ,
VAR6 ,
VAR1
);
input VAR4;
input VAR5 ;
input VAR6 ;
output VAR1 ;
supply1 VAR2;
supply0 VAR3;
endmodule | apache-2.0 |
sirchuckalot/zet | cores/ps2/rtl/ps2_mouse.v | 7,245 | module MODULE1 (
input clk, input reset, inout VAR23, inout VAR19, input VAR18,
input [7:0] VAR5, input VAR13, output VAR20, output VAR11,
output [7:0] VAR29, output VAR25, output VAR14,
output VAR8
);
wire VAR27; wire VAR3;
reg [7:0] VAR15; reg VAR24;
reg VAR7;
reg VAR16;
reg [2:0] VAR6; reg [2:0] VAR9;
localparam VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor4b/sky130_fd_sc_hd__nor4b_4.v | 2,302 | module MODULE1 (
VAR4 ,
VAR11 ,
VAR10 ,
VAR1 ,
VAR8 ,
VAR3,
VAR7,
VAR5 ,
VAR2
);
output VAR4 ;
input VAR11 ;
input VAR10 ;
input VAR1 ;
input VAR8 ;
input VAR3;
input VAR7;
input VAR5 ;
input VAR2 ;
VAR9 VAR6 (
.VAR4(VAR4),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR5(VAR5),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/macro_sparecell/sky130_fd_sc_hd__macro_sparecell.behavioral.v | 2,334 | module MODULE1 (
VAR16
);
output VAR16;
wire VAR3 ;
wire VAR4 ;
wire VAR19;
wire VAR21 ;
wire VAR7 ;
wire VAR11 ;
wire VAR5 ;
wire VAR6 ;
VAR14 VAR13 (.VAR15(VAR3) , .VAR18(VAR4) );
VAR14 VAR2 (.VAR15(VAR19), .VAR18(VAR21) );
VAR10 VAR24 (.VAR12(VAR7) , .VAR15(VAR7), .VAR18(VAR3) );
VAR10 VAR23 (.VAR12(VAR11) , .VAR15(... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or4bb/sky130_fd_sc_hd__or4bb_1.v | 2,314 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR5 ,
VAR10 ,
VAR9 ,
VAR3,
VAR8,
VAR4 ,
VAR7
);
output VAR11 ;
input VAR6 ;
input VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR3;
input VAR8;
input VAR4 ;
input VAR7 ;
VAR1 VAR2 (
.VAR11(VAR11),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR4(VAR4),
.... | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | experimental/LX150-EIGHT-A/pbkdfengine.v | 18,162 | module MODULE1
(VAR25, VAR53, VAR35, VAR10, VAR21, VAR27, VAR13, VAR87, VAR92, VAR95,
VAR89, VAR97, VAR18, VAR68, VAR100, VAR20, VAR80);
input VAR25;
input [255:0] VAR53;
input [255:0] VAR35;
input [127:0] VAR10;
input [31:0] VAR21;
input [3:0] VAR27;
output [31:0] VAR13;
output [31:0] VAR87;
output VAR92; input VAR95;... | gpl-3.0 |
hhuang25/uwaterloo_ece224 | Lab1/pio_latency.v | 1,803 | module MODULE1 (
address,
clk,
VAR6,
VAR4,
VAR2
)
;
output [ 15: 0] VAR2;
input [ 1: 0] address;
input clk;
input [ 15: 0] VAR6;
input VAR4;
wire VAR3;
wire [ 15: 0] VAR5;
wire [ 15: 0] VAR1;
reg [ 15: 0] VAR2;
assign VAR3 = 1;
assign VAR1 = {16 {(address == 0)}} & VAR5;
always @(posedge clk or negedge VAR4)
begin
if (... | mit |
benreynwar/fpga-sdrlib | verilog/flow/qa_buffer_AA.v | 1,962 | module MODULE1
parameter VAR13 = 32
)
(
input wire clk,
input wire reset,
input wire [VAR13-1:0] VAR4,
input wire VAR15,
output reg [VAR13-1:0] VAR5,
output reg VAR6
);
wire VAR10;
assign VAR10 = ~reset;
reg VAR16;
wire VAR3;
wire [VAR13-1:0] VAR8;
wire VAR17;
wire VAR12;
VAR14 #(VAR13, VAR18, VAR2)
VAR7
(.clk(clk),
.V... | mit |
orbancedric/DeepGate | src/core/output_arbiter.v | 1,483 | module MODULE1 #(
parameter VAR4 = 10,
parameter VAR6 = 2,
parameter VAR7 = 5
)(
input clk,
input read,
input write,
input [7:0] VAR2,
output wire [7:0] VAR3,
output reg VAR8,
output reg VAR5
);
reg [7:0] VAR10 = 0;
reg [7:0] VAR1 = 0;
reg [VAR9(VAR4*VAR6 - 1'b1):0] VAR11 = 0;
assign VAR3 = VAR10;
always@(posedge clk) ... | gpl-3.0 |
cthulhuology/avm | stack.v | 2,672 | module MODULE1( reset, VAR10, VAR9, VAR14, VAR4, VAR1, VAR2, VAR7);
input reset;
input VAR10;
input VAR9;
input VAR14;
input VAR4;
input [VAR8-1:0] VAR1;
output [VAR8-1:0] VAR2;
output [VAR8-1:0] VAR7;
reg [VAR8-1:0] VAR11;
reg [VAR8-1:0] VAR6;
reg [VAR5-1:0] VAR12;
reg [VAR5-1:0] VAR3;
reg [VAR8-1:0] VAR15[VAR13-1:0];... | bsd-3-clause |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_usr_rd.v | 11,767 | module MODULE1 #
(
parameter VAR66 = 8,
parameter VAR83 = 9,
parameter VAR3 = 144,
parameter VAR12 = 72,
parameter VAR63 = 0
)
(
input VAR80,
input VAR7,
input [(VAR83*VAR66)-1:0] VAR73,
input [(VAR83*VAR66)-1:0] VAR56,
input [VAR83-1:0] VAR82,
input [VAR83-1:0] VAR17,
output reg [1:0] VAR46,
output VAR67,
output reg [... | lgpl-3.0 |
SeanZarzycki/openSPARC-FPU | dc_compiler/iscas_benchmarks/s382.v | 9,871 | module MODULE1 (VAR39,VAR129,VAR118);
input VAR39,VAR118;
output VAR129;
wire VAR343,VAR364;
trireg VAR228,VAR346;
nmos VAR11 (VAR346,VAR118,VAR364);
not VAR275 (VAR343,VAR346);
nmos VAR29 (VAR228,VAR343,VAR39);
not VAR120 (VAR129,VAR228);
not VAR61 (VAR364,VAR39);
endmodule
module MODULE2(VAR116,VAR154,VAR39,VAR125,VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/muxb16to1/sky130_fd_sc_hdll__muxb16to1.pp.blackbox.v | 1,360 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR5 ,
VAR6,
VAR1,
VAR7 ,
VAR4
);
output VAR3 ;
input [15:0] VAR2 ;
input [15:0] VAR5 ;
input VAR6;
input VAR1;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
alonso193/proyecto1 | FIFO.v | 14,782 | module MODULE1 (
VAR40, VAR18, VAR32, VAR8, VAR39, VAR51, VAR55, VAR15, reset, VAR46, VAR27, VAR24, VAR56, VAR10, VAR1, VAR9, VAR52 );
input [1:0] VAR51;
input [VAR28:0] VAR8;
input [VAR41:0] VAR40;
input [2:0] VAR18;
input [2:0] VAR1;
input VAR32,
VAR46,
reset,
VAR39,
VAR56,
VAR9;
output [VAR28:0] VAR27;
output [1:0] ... | gpl-3.0 |
martinmiranda14/Digitales | Lab_6/project_5/project_5.srcs/sources_1/new/display.v | 1,918 | module MODULE1(
input VAR1,
input [31:0] VAR7,
input [7:0] VAR2,
output [7:0] VAR4,
output reg [7:0] VAR8
);
reg [2:0] counter;
reg [3:0] VAR5;
always @(posedge VAR1) begin
counter <= counter+3'b1;
end
always @(counter) begin
case (counter)
4'd0: VAR8= 8'b01111111;
4'd1: VAR8= 8'b10111111;
4'd2: VAR8= 8'b11011111;
4'd3... | apache-2.0 |
mbuesch/toprammer | libtoprammer/fpga/common/i2c.v | 5,616 | module MODULE1(VAR6, VAR2,
VAR1, VAR14, VAR4,
VAR22, VAR27, VAR25,
VAR19, VAR28, VAR33,
ack, VAR15,
VAR31, VAR32,
VAR5);
input VAR6;
input VAR2;
output VAR1;
output VAR14;
input VAR4;
output VAR22;
output VAR27;
input VAR25;
input [7:0] VAR19;
output [7:0] VAR28;
input VAR33;
output ack;
input VAR15;
input VAR31;
input... | gpl-2.0 |
campsandrew/ECE-474A-Program-1 | Modules/MAIN.v | 2,189 | module MODULE1(VAR50, VAR8, VAR16, VAR28, VAR13, VAR25, VAR14, VAR26, VAR24, VAR35, VAR59, VAR1, VAR36, VAR61, VAR9, VAR48, clk, rst, VAR53, VAR7, VAR3, VAR57, VAR19, VAR31, VAR4, VAR62, VAR29, VAR45, VAR56, VAR33, VAR15, VAR5, VAR21, VAR10, VAR6, VAR40, VAR2, VAR46);
parameter VAR37 = 2;
input [VAR37 - 1:0] VAR50, VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.pp.symbol.v | 1,269 | module MODULE1 (
input VAR3 ,
input VAR8 ,
output VAR4,
output VAR6 ,
input VAR1 ,
input VAR2,
input VAR5,
input VAR7
);
endmodule | apache-2.0 |
alankarkotwal/lca-processor | USE THESE FILES PRAVEEN/lca_processor.v | 64,038 | module MODULE7(clk,reset);
input clk,reset;
wire [15:0] VAR173, VAR233 ,VAR332 ,VAR19, VAR238, VAR274, VAR189, VAR286,
VAR126, VAR277, VAR143, VAR113, VAR309, VAR29, VAR140,
VAR167, VAR76, VAR343, VAR3, VAR217, VAR287, VAR40, VAR262,
VAR172, VAR42, VAR38, VAR161, VAR159, VAR174, VAR86, VAR92,
VAR256, VAR330, VAR216, VA... | gpl-2.0 |
Obijuan/ACC | hw/roadmap/09-up-down-manual-counter/up-down-counter.v | 3,136 | module MODULE3 (input clk,
input VAR7,
input VAR35,
output VAR24,
output VAR12,
output VAR9,
output VAR22,
output VAR8,
output VAR17,
output VAR26,
output VAR20);
wire VAR33; wire VAR6;
wire VAR39;
wire VAR38;
VAR31 #(
.VAR29(6'VAR15 101001),
.VAR21(1'VAR15 1)
) VAR16 (
.VAR23(VAR7),
.VAR5(VAR33)
);
VAR31 #(
.VAR29(6'V... | gpl-3.0 |
sehugg/8bitworkshop | presets/verilog/font_cp437_8x8.v | 14,221 | module MODULE1(addr, VAR1);
input [10:0] addr;
output [7:0] VAR1;
assign VAR1 = VAR2[addr];
localparam [7:0] VAR2[0:2047] = '{
8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00,8'h00, 8'h7e,8'h81,8'ha5,8'h81,8'hbd,8'h99,8'h81,8'h7e, 8'h7e,8'hff,8'hdb,8'hff,8'hc3,8'he7,8'hff,8'h7e, 8'h6c,8'hfe,8'hfe,8'hfe,8'h7c,8'h38,8'h10,8'h0... | gpl-3.0 |
fanatid/gost28147-89 | rtl/gost89_mac.v | 1,902 | module MODULE1(
input clk,
input reset,
input VAR2,
input [511:0] VAR7,
input [255:0] VAR5,
input [63:0] in,
output reg [31:0] out,
output reg VAR10
);
reg [4:0] counter;
reg [31:0] VAR8;
reg VAR11;
reg [31:0] VAR3, VAR9;
wire [31:0] VAR1, VAR4;
VAR6
rnd(clk, VAR7, VAR8, VAR3, VAR9, VAR1, VAR4);
always @(posedge clk) b... | bsd-3-clause |
CospanDesign/nysa-tx1-pcie-platform | tx1_pcie/slave/wb_tx1_pcie/rtl/xilinx/pcie_7x_v1_11_0_pipe_clock.v | 20,414 | module MODULE1 #
(
parameter VAR79 = "VAR131", parameter VAR18 = "VAR131", parameter VAR15 = 1, parameter VAR42 = 3, parameter VAR36 = 0, parameter VAR47 = 2, parameter VAR145 = 2, parameter VAR45 = 1, parameter VAR77 = 0
)
(
input VAR19,
input VAR98,
input [VAR15-1:0] VAR113,
input VAR149,
input [VAR15-1:0] VAR10,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i_2.v | 2,230 | module MODULE2 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR5 ,
VAR9,
VAR1,
VAR8 ,
VAR7
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR5 ;
input VAR9;
input VAR1;
input VAR8 ;
input VAR7 ;
VAR6 VAR10 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE2 (... | apache-2.0 |
olajep/oh | src/adi/hdl/library/axi_dmac/response_handler.v | 2,837 | module MODULE1 #(
parameter VAR14 = 3)(
input clk,
input VAR2,
input VAR12,
output VAR6,
input [1:0] VAR9,
output reg [VAR14-1:0] VAR3,
input [VAR14-1:0] VAR10,
input enable,
output reg VAR15,
input VAR8,
output VAR5,
input VAR1,
output VAR4,
output [1:0] VAR11
);
assign VAR11 = VAR9;
assign VAR4 = VAR8;
wire VAR13 = V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfstp/sky130_fd_sc_lp__sdfstp.functional.v | 1,938 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR2 ,
VAR5 ,
VAR15 ,
VAR8
);
output VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR5 ;
input VAR15 ;
input VAR8;
wire VAR12 ;
wire VAR7 ;
wire VAR3;
not VAR16 (VAR7 , VAR8 );
VAR9 VAR14 (VAR3, VAR2, VAR5, VAR15 );
VAR11 VAR10 VAR4 (VAR12 , VAR3, VAR1, VAR7);
buf VAR13 (VAR6 , VAR12 );
endmodu... | apache-2.0 |
praveendath92/securePUF | source/NIST.v | 1,360 | module MODULE1(
input wire clk,
input wire rst,
input wire rand,
output wire [7:0] VAR15
);
assign VAR15[7] = 0;
VAR13 VAR10(
.clk(clk),
.rst(rst),
.rand(rand),
.VAR16(VAR15[0])
);
VAR5 VAR7(
.clk(clk),
.rst(rst),
.rand(rand),
.VAR16(VAR15[1])
);
VAR8 VAR4(
.clk(clk),
.rst(rst),
.rand(rand),
.VAR16(VAR15[2])
);
VAR2 VA... | gpl-2.0 |
yanhongwang/ColorImage | ColorImageProcess/ColorImageProcess.v | 69,160 | module MODULE1
(
input VAR103,
input VAR32,
input[ VAR66 - 1 : 0 ]VAR61,
input[ VAR66 - 1 : 0 ]VAR41,
input[ VAR66 - 1 : 0 ]VAR55,
output[ VAR66 - 1 : 0 ]VAR57,
output[ VAR66 - 1 : 0 ]VAR10,
output[ VAR66 - 1 : 0 ]VAR92
);
reg[ VAR46 - 1 : 0 ]VAR4;
reg[ VAR46 - 1 : 0 ]VAR16;
reg[ VAR46 - 1 : 0 ]VAR72;
reg[ VAR46 - 1 : ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o211ai/sky130_fd_sc_hdll__o211ai.pp.blackbox.v | 1,405 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR4 ,
VAR5,
VAR7,
VAR1 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR4 ;
input VAR5;
input VAR7;
input VAR1 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/probec_p/sky130_fd_sc_hd__probec_p.pp.symbol.v | 1,282 | module MODULE1 (
input VAR5 ,
output VAR6 ,
input VAR2 ,
input VAR1,
input VAR3,
input VAR4
);
endmodule | apache-2.0 |
kernelpanics/Grad | CORDIC-Exponential-Function/Verilog/UART/FPU_UART.v | 4,067 | module MODULE1 #(parameter VAR26 = 32, parameter VAR29 = 8, parameter VAR33 = 23, parameter VAR19=26, parameter VAR16 = 5)/*#(parameter VAR26 = 64, parameter VAR29 = 11, parameter VAR33 = 52, parameter VAR19 = 55, parameter VAR16 = 6)
(
input wire clk,
input wire rst,
output wire VAR47
);
localparam VAR31 = 2; localpar... | gpl-3.0 |
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