repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/FPU_ADD_Substract_PIPELINED.v | 30,433 | module MODULE1
/*#(parameter VAR212 = 32, parameter VAR195 = 8, parameter VAR117 = 23,
parameter VAR13=26, parameter VAR186 = 5)
parameter VAR13 = 55, parameter VAR186 = 6) (
input wire clk,
input wire rst,
input wire VAR153,
input wire [VAR212-1:0] VAR110,
input wire [VAR212-1:0] VAR86,
input wire VAR16,
output wire V... | gpl-3.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_port_monitor_64.v | 8,166 | module MODULE1 #(
parameter VAR29 = 9'd64,
parameter VAR6 = 512,
parameter VAR8 = (VAR6 - 4),
parameter VAR18 = VAR19((2**VAR19(VAR6))+1),
parameter VAR41 = 1
)
(
input VAR38,
input VAR26,
input [VAR29:0] VAR16, input VAR42, output VAR33,
output [VAR29-1:0] VAR13, output VAR2, input [VAR18-1:0] VAR25,
output VAR10, inp... | bsd-3-clause |
vad-rulezz/megabot | minsoc/bench/verilog/vpi/dbg_comm_vpi.v | 5,593 | module MODULE1 (
VAR7,
VAR6,
VAR1,
VAR5,
VAR4,
VAR2
);
input VAR7;
output VAR6;
output VAR1;
output VAR5;
output VAR4;
input VAR2;
reg [4:0] memory;
wire VAR1;
wire VAR5;
wire VAR4;
wire VAR6;
wire VAR2;
reg [3:0] VAR8;
reg [5:0] VAR3;
begin
begin
begin
begin
end | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41o/sky130_fd_sc_ls__a41o.pp.blackbox.v | 1,415 | module MODULE1 (
VAR9 ,
VAR1 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR2,
VAR10,
VAR5 ,
VAR4
);
output VAR9 ;
input VAR1 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR2;
input VAR10;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
olgirard/openmsp430 | core/synthesis/actel/src/openMSP430.v | 20,747 | module MODULE1 (
VAR15, VAR55, VAR75, VAR92, VAR4, VAR78, VAR5, VAR12, VAR9, VAR31, VAR51, VAR26, VAR89, VAR25, VAR56, VAR10, VAR7, VAR70, VAR53,
VAR16, VAR88, VAR38, irq, VAR52, VAR87, VAR98, VAR46, VAR20 );
output VAR15; output VAR55; output VAR75; output [VAR22:0] VAR92; output VAR4; output [15:0] VAR78; output [1:0... | bsd-3-clause |
ShirmanXia/EE469SPRING16 | lab3/nios_system/synthesis/submodules/nios_system_regfile_data.v | 2,330 | module MODULE1 (
address,
VAR9,
clk,
VAR1,
VAR3,
VAR4,
VAR5,
VAR7
)
;
output [ 31: 0] VAR5;
output [ 31: 0] VAR7;
input [ 1: 0] address;
input VAR9;
input clk;
input VAR1;
input VAR3;
input [ 31: 0] VAR4;
wire VAR6;
reg [ 31: 0] VAR2;
wire [ 31: 0] VAR5;
wire [ 31: 0] VAR8;
wire [ 31: 0] VAR7;
assign VAR6 = 1;
assign V... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxtp/sky130_fd_sc_ms__sdfxtp.behavioral.pp.v | 2,370 | module MODULE1 (
VAR4 ,
VAR14 ,
VAR25 ,
VAR9 ,
VAR16 ,
VAR6,
VAR3,
VAR5 ,
VAR17
);
output VAR4 ;
input VAR14 ;
input VAR25 ;
input VAR9 ;
input VAR16 ;
input VAR6;
input VAR3;
input VAR5 ;
input VAR17 ;
wire VAR13 ;
wire VAR8 ;
reg VAR2 ;
wire VAR11 ;
wire VAR7;
wire VAR23;
wire VAR20;
wire VAR24 ;
wire VAR22 ;
wire VA... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai21/gf180mcu_fd_sc_mcu7t5v0__oai21_1.functional.pp.v | 1,290 | module MODULE1( VAR1, VAR13, VAR9, VAR7, VAR3, VAR2 );
input VAR9, VAR1, VAR7;
inout VAR3, VAR2;
output VAR13;
wire VAR11;
not VAR14( VAR11, VAR9 );
wire VAR12;
not VAR15( VAR12, VAR1 );
wire VAR4;
and VAR8( VAR4, VAR11, VAR12 );
wire VAR6;
not VAR5( VAR6, VAR7 );
or VAR10( VAR13, VAR4, VAR6 );
endmodule | apache-2.0 |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/Allign2.v | 2,623 | module MODULE1(
input [1:0] VAR20,
input [35:0] VAR11,
input [35:0] VAR3,
input [31:0] VAR6,
input [1:0] VAR8,
input VAR1,
input VAR2,
input [7:0] VAR25,
input [7:0] VAR12,
input VAR29,
output reg [1:0] VAR17,
output reg [35:0] VAR13,
output reg [35:0] VAR27,
output reg [31:0] VAR26,
output reg [1:0] VAR9,
output reg V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfxbp/sky130_fd_sc_ls__dfxbp.behavioral.v | 1,893 | module MODULE1 (
VAR9 ,
VAR14,
VAR17,
VAR5
);
output VAR9 ;
output VAR14;
input VAR17;
input VAR5 ;
supply1 VAR13;
supply0 VAR15;
supply1 VAR16 ;
supply0 VAR4 ;
wire VAR3 ;
reg VAR1 ;
wire VAR10 ;
wire VAR2;
wire VAR6 ;
VAR12 VAR8 (VAR3 , VAR10, VAR2, VAR1, VAR13, VAR15);
assign VAR6 = ( VAR13 === 1'b1 );
buf VAR7 (VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2/sky130_fd_sc_ls__nand2.functional.v | 1,270 | module MODULE1 (
VAR4,
VAR5,
VAR3
);
output VAR4;
input VAR5;
input VAR3;
wire VAR2;
nand VAR6 (VAR2, VAR3, VAR5 );
buf VAR1 (VAR4 , VAR2 );
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9250/axi_ad9250_channel.v | 5,893 | module MODULE1 (
VAR12,
VAR46,
VAR30,
VAR10,
VAR34,
VAR21,
VAR54,
VAR62,
VAR24,
VAR48,
VAR29,
VAR58,
VAR66,
VAR39,
VAR70,
VAR51,
VAR42,
VAR20,
VAR45);
parameter VAR26 = 0;
parameter VAR7 = 0;
input VAR12;
input VAR46;
input [27:0] VAR30;
input VAR10;
output [31:0] VAR34;
output VAR21;
output VAR54;
output VAR62;
output... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or4/sky130_fd_sc_hdll__or4.behavioral.pp.v | 1,846 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR6 ,
VAR15 ,
VAR1 ,
VAR9,
VAR4,
VAR11 ,
VAR10
);
output VAR8 ;
input VAR5 ;
input VAR6 ;
input VAR15 ;
input VAR1 ;
input VAR9;
input VAR4;
input VAR11 ;
input VAR10 ;
wire VAR14 ;
wire VAR3;
or VAR7 (VAR14 , VAR1, VAR15, VAR6, VAR5 );
VAR13 VAR12 (VAR3, VAR14, VAR9, VAR4);
buf VAR2 (VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a31o/sky130_fd_sc_hd__a31o.blackbox.v | 1,354 | module MODULE1 (
VAR9 ,
VAR3,
VAR1,
VAR6,
VAR7
);
output VAR9 ;
input VAR3;
input VAR1;
input VAR6;
input VAR7;
supply1 VAR8;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
dekuNukem/FAP80 | FAP_modules/video_card/FPGA_code/src/serial_tx.v | 2,894 | module MODULE1 #(
parameter VAR15 = 50
)(
input clk,
input rst,
output VAR17,
input VAR3,
output VAR18,
input [7:0] VAR9,
input VAR19
);
parameter VAR23 = VAR16(VAR15);
localparam VAR7 = 2;
localparam VAR24 = 2'd0,
VAR11 = 2'd1,
VAR6 = 2'd2,
VAR25 = 2'd3;
reg [VAR23-1:0] VAR10, VAR12;
reg [2:0] VAR8, VAR21;
reg [7:0] V... | mit |
Ricky-Gong/LegoCar | DE0-Nano/DE0Course/db/ip/NIOS_Sys/submodules/NIOS_Sys_led.v | 2,184 | module MODULE1 (
address,
VAR6,
clk,
VAR3,
VAR4,
VAR8,
VAR5,
VAR2
)
;
output [ 7: 0] VAR5;
output [ 31: 0] VAR2;
input [ 1: 0] address;
input VAR6;
input clk;
input VAR3;
input VAR4;
input [ 31: 0] VAR8;
wire VAR9;
reg [ 7: 0] VAR7;
wire [ 7: 0] VAR5;
wire [ 7: 0] VAR1;
wire [ 31: 0] VAR2;
assign VAR9 = 1;
assign VAR1 ... | gpl-2.0 |
spike556/HuffmanCode | rtl model/sortnet/SortX4.v | 1,578 | module MODULE1 # (
parameter VAR10 = 18,
parameter VAR14 = 8
)(
input [VAR10-1:0] VAR5,
input [VAR10-1:0] VAR9,
input [VAR10-1:0] VAR23,
input [VAR10-1:0] VAR4,
output wire [VAR10-1:0] VAR12,
output wire [VAR10-1:0] VAR21,
output wire [VAR10-1:0] VAR13,
output wire [VAR10-1:0] VAR26
);
wire [VAR10-1:0] VAR24;
wire [VAR... | gpl-3.0 |
SymbiFlow/yosys | techlibs/common/cmp2lut.v | 2,614 | module MODULE1(
module 90lutcmp (VAR4, VAR1, VAR2);
parameter VAR21 = 0;
parameter VAR7 = 0;
parameter VAR19 = 0;
parameter VAR17 = 0;
parameter VAR13 = 0;
input [VAR19-1:0] VAR4;
input [VAR17-1:0] VAR1;
output [VAR13-1:0] VAR2;
parameter VAR29 = "";
parameter VAR12 = 0;
parameter VAR25 = 0;
parameter VAR16 = 0;
parame... | isc |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_dma.v | 1,661 | module MODULE1(
input VAR11,
input VAR17,
input VAR14,
input [28:0] VAR2,
input [6:0] VAR7,
input [6:0] VAR1,
input [31:0] VAR3,
input [31:0] VAR9,
output ack,
output VAR18,
output [31:0] VAR6,
output [31:0] VAR10,
output VAR16,
output reg VAR5,
input VAR13
);
reg VAR15;
reg [28:0] VAR4;
reg [31:0] VAR8;
reg [31:0] VAR... | lgpl-3.0 |
Jafet95/I-Proyecto-Laboratorio-de-Dise-o-Sistemas-Digitales | Contador_Ascendente_Descendente.v | 1,088 | module MODULE1
input wire clk,
input wire reset,
input wire VAR2,
input wire VAR6,
output wire [VAR3-1:0] VAR4
);
reg [VAR3-1:0] VAR5, VAR1;
always@(posedge clk,posedge reset)
if(reset)
VAR5 <= 0;
else
VAR5 <= VAR1;
always@*
if(VAR2)
VAR1 = VAR5 + 1'b1;
else if (VAR6)
VAR1 = VAR5 - 1'b1;
else
VAR1 = VAR5;
assign VAR4 =... | apache-2.0 |
YoelRP/PROYECTO | bin/enpoint/transaction/Transaccion.v | 6,651 | module MODULE1 (
sync,
VAR27,
clk,
rst,
VAR6,
VAR61,
VAR3,
VAR21,
VAR32,
VAR43,
);
input wire VAR3;
input wire clk;
input wire rst;
input wire [88:0] VAR32;
input wire [1047:0]VAR6;
input wire [23:0] VAR61;
input wire [31:0]VAR27;
input wire [7:0] sync;
output reg [1047:0]VAR21;
output reg [7:0]VAR43;
reg VAR48 ;
reg [... | gpl-3.0 |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/internal_osc/synthesis/submodules/altera_int_osc.v | 2,597 | module MODULE1
(
VAR5,
VAR10);
parameter VAR7 = "VAR3 10";
parameter VAR4 = "08";
parameter VAR6 = "VAR12";
output VAR5;
input VAR10;
wire VAR13;
assign VAR5 = VAR13;
generate
if (VAR7 == "VAR3 10") begin
VAR2 # ( .VAR9(VAR4),
.VAR8(VAR6)
) VAR11 (
.VAR5(VAR13),
.VAR1(),
.VAR10(VAR10));
end
endgenerate
endmodule | apache-2.0 |
CospanDesign/nysa-artemis-usb2-platform | artemis_usb2/slave/wb_artemis_pcie_platform/rtl/c/axi_basic_top.v | 11,125 | module MODULE1 #(
parameter VAR51 = 128, parameter VAR24 = "VAR36", parameter VAR40 = "VAR26", parameter VAR14 = "VAR26", parameter VAR53 = 1,
parameter VAR25 = (VAR51 == 128) ? 2 : 1, parameter VAR39 = VAR51 / 8 ) (
input [VAR51-1:0] VAR22, input VAR23, output VAR3, input [VAR39-1:0] VAR44, input VAR2, input [3:0] VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.behavioral.v | 2,865 | module MODULE1 (
VAR9 ,
VAR22 ,
VAR13 ,
VAR7 ,
VAR3 ,
VAR4
);
output VAR9 ;
input VAR22 ;
input VAR13 ;
input VAR7 ;
input VAR3 ;
input VAR4;
supply1 VAR30;
supply0 VAR27;
supply1 VAR10 ;
supply0 VAR14 ;
wire VAR16 ;
wire VAR31 ;
wire VAR17 ;
reg VAR18 ;
wire VAR5 ;
wire VAR23 ;
wire VAR6 ;
wire VAR20;
wire VAR28 ;
wir... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn.blackbox.v | 1,280 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR6
);
output VAR5 ;
input VAR3 ;
input VAR6;
supply1 VAR4;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a41oi/sky130_fd_sc_ls__a41oi.functional.v | 1,476 | module MODULE1 (
VAR6 ,
VAR2,
VAR9,
VAR8,
VAR3,
VAR1
);
output VAR6 ;
input VAR2;
input VAR9;
input VAR8;
input VAR3;
input VAR1;
wire VAR7 ;
wire VAR4;
and VAR10 (VAR7 , VAR2, VAR9, VAR8, VAR3 );
nor VAR5 (VAR4, VAR1, VAR7 );
buf VAR11 (VAR6 , VAR4 );
endmodule | apache-2.0 |
mrehkopf/sd2snes | verilog/sd2snes_mini/main.v | 10,683 | module MODULE1(
output [22:0] VAR92,
output VAR152,
input VAR131,
output VAR140,
input VAR45,
output [21:0] VAR92,
output VAR110,
output VAR114,
output VAR77,
output VAR117,
output VAR73,
input VAR78,
input VAR53,
input [23:0] VAR10,
input VAR58,
input VAR44,
input VAR24,
inout [7:0] VAR30,
input VAR8,
input VAR49,
out... | gpl-2.0 |
Digilent/vivado-library | ip/Pmods/PmodCLS_v1_0/src/PmodCLS.v | 10,158 | module MODULE1
(VAR45,
VAR160,
VAR8,
VAR30,
VAR81,
VAR90,
VAR126,
VAR27,
VAR133,
VAR42,
VAR33,
VAR99,
VAR106,
VAR166,
VAR156,
VAR137,
VAR82,
VAR121,
VAR11,
VAR41,
VAR144,
VAR155,
VAR116,
VAR164,
VAR148,
VAR4,
VAR6,
VAR136,
VAR135,
VAR91,
VAR108,
VAR129,
VAR127,
VAR159,
VAR60,
VAR63,
VAR39,
VAR35,
VAR103,
VAR74,
VAR40,
... | mit |
plindstroem/oh | emesh/dv/egen.v | 3,557 | module MODULE1(
VAR13, VAR27, VAR16,
clk, reset, VAR25, VAR28
);
parameter VAR34 = 104;
parameter VAR19 = 32;
parameter VAR10 = 32;
parameter VAR24 = 0; parameter VAR32 = 12'h0;
parameter VAR33 = 12'h0;
parameter VAR31 = 16;
input clk;
input reset;
input VAR25; output VAR13;
output VAR27;
output [VAR34-1:0] VAR16;
inpu... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/control_lib/s3a_icap_wb.v | 2,332 | module MODULE1
(input clk, input reset,
input VAR14, input VAR19, input VAR15, output VAR6,
input [31:0] VAR20, output [31:0] VAR17);
assign VAR17[31:8] = 24'd0;
wire VAR9, VAR12, VAR8, VAR21;
reg [2:0] VAR10;
localparam VAR16 = 0;
localparam VAR13 = 1;
localparam VAR3 = 5;
localparam VAR11 = 2;
localparam VAR7 = 3;
al... | gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_axi4s_vid_out_0_0/synth/tutorial_v_axi4s_vid_out_0_0.v | 7,187 | module MODULE1 (
VAR11,
rst,
VAR7,
VAR9,
VAR1,
VAR17,
VAR28,
VAR33,
VAR38,
VAR19,
VAR34,
VAR27,
VAR13,
VAR25,
VAR5,
VAR18,
VAR2,
VAR14,
VAR26,
VAR30,
VAR15,
VAR21,
VAR10,
VAR36,
VAR31,
VAR23,
VAR8,
VAR29,
VAR6
);
input wire VAR11;
input wire rst;
input wire VAR7;
input wire VAR9;
input wire [15 : 0] VAR1;
input wire VA... | gpl-2.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_spram_1024x8.v | 10,524 | module MODULE1(
VAR2, VAR15, VAR6,
clk, rst, VAR50, VAR39, VAR48, addr, VAR26, VAR18
);
parameter VAR49 = 10;
parameter VAR13 = 8;
input VAR2;
input [VAR8 - 1:0] VAR6;
output VAR15;
input clk; input rst; input VAR50; input VAR39; input VAR48; input [VAR49-1:0] addr; input [VAR13-1:0] VAR26; output [VAR13-1:0] VAR18;
as... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21boi/sky130_fd_sc_hs__a21boi.pp.symbol.v | 1,361 | module MODULE1 (
input VAR1 ,
input VAR2 ,
input VAR5,
output VAR4 ,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/and4bb/sky130_fd_sc_lp__and4bb_2.v | 2,323 | module MODULE1 (
VAR2 ,
VAR6 ,
VAR10 ,
VAR8 ,
VAR3 ,
VAR5,
VAR1,
VAR11 ,
VAR4
);
output VAR2 ;
input VAR6 ;
input VAR10 ;
input VAR8 ;
input VAR3 ;
input VAR5;
input VAR1;
input VAR11 ;
input VAR4 ;
VAR9 VAR7 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR11(VAR11),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dfstp/sky130_fd_sc_ls__dfstp_2.v | 2,273 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2 ,
VAR10,
VAR1 ,
VAR6 ,
VAR7 ,
VAR8
);
output VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR10;
input VAR1 ;
input VAR6 ;
input VAR7 ;
input VAR8 ;
VAR9 VAR5 (
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR8(VAR8)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15.functional.pp.v | 1,866 | module MODULE1 (
VAR11 ,
VAR6 ,
VAR1,
VAR7,
VAR12 ,
VAR9
);
output VAR11 ;
input VAR6 ;
input VAR1;
input VAR7;
input VAR12 ;
input VAR9 ;
wire VAR2 ;
wire VAR8;
buf VAR10 (VAR2 , VAR6 );
VAR3 VAR4 (VAR8, VAR2, VAR1, VAR7);
buf VAR5 (VAR11 , VAR8 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi_2.v | 2,366 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR6 ,
VAR9 ,
VAR7 ,
VAR11,
VAR5,
VAR10 ,
VAR1
);
output VAR3 ;
input VAR4 ;
input VAR6 ;
input VAR9 ;
input VAR7 ;
input VAR11;
input VAR5;
input VAR10 ;
input VAR1 ;
VAR8 VAR2 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR10(VAR10),
.... | apache-2.0 |
cpulabs/mist1032sa | src/core/rename/register_renaming_table.v | 4,587 | module MODULE1 #(
parameter VAR20 = 5'h0
)(
input wire VAR11,
input wire VAR17,
input wire VAR1,
input wire VAR21,
input wire [4:0] VAR5,
input wire [5:0] VAR10,
input wire VAR15,
input wire [4:0] VAR22,
input wire [5:0] VAR30,
input wire VAR6,
input wire [4:0] VAR26,
input wire [5:0] VAR18,
input wire VAR31,
input wir... | bsd-2-clause |
xuwenyihust/MapReduce_NoC | RTL/sram_router.v | 4,124 | module MODULE1(clk, rst, VAR49, VAR45, VAR20, VAR14, VAR33, VAR34, VAR41,
VAR11, VAR42, VAR24, VAR30, VAR5,
VAR29, VAR27, VAR44, VAR46,
VAR10, VAR39, VAR58, VAR18,
VAR6, VAR38, VAR26, VAR19,
VAR22, VAR3);
parameter VAR47=36;
parameter VAR8=8;
parameter VAR25=4;
parameter VAR23=5;
parameter VAR37=5;
input clk;
input rst... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/tapmet1/sky130_fd_sc_hs__tapmet1.pp.blackbox.v | 1,179 | module MODULE1 (
VAR2,
VAR1
);
input VAR2;
input VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.functional.v | 1,558 | module MODULE1 (
VAR2 ,
VAR1,
VAR5,
VAR7
);
output VAR2 ;
input VAR1;
input VAR5;
input VAR7 ;
wire VAR8;
VAR3 VAR6 (VAR8, VAR1, VAR5, VAR7 );
buf VAR4 (VAR2 , VAR8);
endmodule | apache-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72.v | 13,714 | module MODULE1(
clk,
rst,
din,
VAR153,
VAR175,
dout,
VAR425,
VAR389,
VAR69
);
input clk;
input rst;
input [71 : 0] din;
input VAR153;
input VAR175;
output [71 : 0] dout;
output VAR425;
output VAR389;
output VAR69;
VAR10 #(
.VAR371(0),
.VAR108(0),
.VAR320(0),
.VAR301(0),
.VAR217(0),
.VAR149(0),
.VAR312(0),
.VAR160(32),
... | gpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/remove_pkt.v | 19,662 | module MODULE1
parameter VAR24 = 64,
parameter VAR121=VAR24/8,
parameter VAR34 = 8,
parameter VAR16 = 13,
parameter VAR103 = 6,
parameter VAR76 = 4,
parameter VAR120 = VAR112,
parameter VAR109 = 11,
parameter VAR117 = VAR109-VAR8(VAR121),
parameter VAR15 = VAR8(VAR34)
)
( VAR36,
VAR52,
VAR6,
VAR89,
VAR29,
VAR72,
VAR62,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a22o/sky130_fd_sc_hvl__a22o.pp.blackbox.v | 1,389 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR6 ,
VAR3 ,
VAR1 ,
VAR2,
VAR4,
VAR5 ,
VAR8
);
output VAR9 ;
input VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR1 ;
input VAR2;
input VAR4;
input VAR5 ;
input VAR8 ;
endmodule | apache-2.0 |
gigglesninja/digital-system-design | lab2_part2/satadd.v | 1,068 | module MODULE1(VAR5,VAR14,VAR8,VAR4);
input [11:0] VAR5,VAR14;
input [1:0] VAR8;
output [11:0] VAR4;
wire VAR16, VAR13, VAR11, VAR7, VAR9;
wire [12:0] VAR2;
VAR6 VAR1 (.VAR5({1'b0,VAR5}), .VAR14({1'b0,VAR14}), .VAR12(VAR2));
assign VAR9 = (~VAR16 & ~VAR13 & VAR11 | VAR16 & VAR13 & ~VAR11);
assign VAR7 = VAR2[12];
assig... | gpl-2.0 |
sh-chris110/chris | FPGA/chris.uart.ok/db/ip/soc_design/submodules/soc_design_UART_COM.v | 7,735 | module MODULE1 (
clk,
reset,
address,
VAR14,
VAR13,
read,
write,
VAR28,
VAR34,
irq,
VAR10,
VAR15
);
parameter VAR32 = 10; parameter VAR11 = 868;
parameter VAR21 = 434;
parameter VAR27 = 10; parameter VAR24 = 8; parameter VAR22 = 1'b0;
input clk;
input reset;
input address;
input VAR14;
input [ 3: 0] VAR13;
input read;
... | gpl-2.0 |
zhangly/azpr_cpu | rtl/io/timer/rtl/timer.v | 3,710 | module MODULE1 (
input wire clk, input wire reset,
input wire VAR11, input wire VAR12, input wire VAR25, input wire [VAR17] addr, input wire [VAR18] VAR15, output reg [VAR18] VAR20, output reg VAR10,
output reg irq );
reg VAR19; reg VAR2; reg [VAR18] VAR16; reg [VAR18] counter;
wire VAR4 = ((VAR2 == VAR27) && (counter ... | mit |
Anirudh94/Connect4-FPGA | Connect4/player1.v | 6,213 | module MODULE1 (
address,
VAR29,
VAR47);
input [10:0] address;
input VAR29;
output [2:0] VAR47;
tri1 VAR29;
wire [2:0] VAR11;
wire [2:0] VAR47 = VAR11[2:0];
VAR18 VAR40 (
.VAR14 (address),
.VAR46 (VAR29),
.VAR30 (VAR11),
.VAR31 (1'b0),
.VAR1 (1'b0),
.VAR48 (1'b1),
.VAR45 (1'b0),
.VAR50 (1'b0),
.VAR35 (1'b1),
.VAR38 (1'... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_096bits.v | 1,917 | module MODULE1 (
clk,
VAR6, VAR10, VAR30, VAR14, VAR12, VAR7, VAR3, VAR1,
sum,
);
input clk;
input [VAR21+0-1:0] VAR6, VAR10, VAR30, VAR14, VAR12, VAR7, VAR3, VAR1;
output [VAR21 :0] sum;
reg [VAR21 :0] sum;
wire [VAR21+3-1:0] VAR31;
wire [VAR21+2-1:0] VAR20, VAR4;
wire [VAR21+1-1:0] VAR11, VAR34, VAR5, VAR27;
reg [VAR... | mit |
berickson1/ECE492 | Quartus/DM9000A_IF.v | 1,784 | module MODULE1( VAR11,
VAR6,
VAR4,
VAR1,
VAR14,
VAR10,
VAR16,
VAR3,
VAR12,
VAR8,
VAR7,
VAR13,
VAR18,
VAR15,
VAR2,
VAR17,
VAR9
);
input [15:0] VAR11;
input VAR4;
input VAR1;
input VAR14;
input VAR10;
input VAR16;
input VAR3;
output [15:0] VAR6;
output VAR12;
inout [15:0] VAR8;
output VAR7;
output VAR13;
output VAR18;
ou... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/systems/neek/bench/ddr_model/ddr.v | 58,637 | module MODULE1 (VAR85, VAR63, VAR120, VAR12, VAR108, VAR87, VAR76, VAR109 , VAR104, VAR84, VAR45, VAR52);
input VAR85;
input VAR63;
input VAR120;
input VAR12;
input VAR108;
input VAR87;
input VAR76;
input [1 : 0] VAR109;
input [VAR49 - 1 : 0] VAR104;
input [VAR107 - 1 : 0] VAR84;
inout [VAR10 - 1 : 0] VAR45;
inout [VAR... | gpl-2.0 |
antmicro/yosys | techlibs/xilinx/mux_map.v | 2,498 | module \VAR11 (VAR5, VAR2, VAR16);
parameter VAR6 = 0;
parameter VAR10 = 0;
parameter VAR7 = 1;
parameter VAR15 = 1;
parameter VAR14 = 1;
input [VAR7-1:0] VAR5;
input [VAR15-1:0] VAR2;
output [VAR14-1:0] VAR16;
parameter [VAR15-1:0] VAR13 = 0;
parameter [VAR15-1:0] VAR12 = 0;
generate
if (VAR10) begin
if (VAR13[VAR15-1... | isc |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtp/sky130_fd_sc_lp__dlxtp.functional.pp.v | 1,745 | module MODULE1 (
VAR12 ,
VAR4 ,
VAR14,
VAR1,
VAR5,
VAR8 ,
VAR11
);
output VAR12 ;
input VAR4 ;
input VAR14;
input VAR1;
input VAR5;
input VAR8 ;
input VAR11 ;
wire VAR9 ;
wire VAR6;
wire VAR2 ;
VAR3 VAR10 VAR13 (VAR9 , VAR4, VAR14, , VAR1, VAR5);
buf VAR7 (VAR12 , VAR9 );
endmodule | apache-2.0 |
hewittc/proxmark3lcd | fpga/hi_read_tx.v | 2,267 | module MODULE1(
VAR14, VAR17, VAR22,
VAR9, VAR21, VAR13, VAR4, VAR8, VAR5,
VAR7, VAR19,
VAR16, VAR15, VAR18, VAR11,
VAR12, VAR10,
VAR2,
VAR1
);
input VAR14, VAR17, VAR22;
output VAR9, VAR21, VAR13, VAR4, VAR8, VAR5;
input [7:0] VAR7;
output VAR19;
input VAR18;
output VAR16, VAR15, VAR11;
input VAR12, VAR10;
output VAR2... | gpl-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7k325ffg900/pcie_core/source/pcie_core_pipe_eq.v | 35,564 | module MODULE1 #
(
parameter VAR74 = "VAR5",
parameter VAR77 = "VAR80",
parameter VAR89 = 1
)
(
input VAR110,
input VAR99,
input VAR122,
input [ 1:0] VAR115,
input [ 3:0] VAR42,
input [ 3:0] VAR55,
input [ 5:0] VAR125,
input [ 1:0] VAR46,
input [ 2:0] VAR57,
input [ 5:0] VAR116,
input [ 3:0] VAR93,
input VAR13,
input [... | lgpl-3.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/ipcore_dir/clk_divider/example_design/clk_divider_exdes.v | 4,987 | module MODULE1
parameter VAR25 = 100
)
( input VAR5,
input VAR12,
output [1:1] VAR7,
output VAR26,
input VAR15,
output VAR13
);
localparam VAR27 = 16;
wire VAR11 = !VAR13 || VAR15 || VAR12;
reg VAR2;
reg VAR16;
reg VAR28;
reg VAR18;
wire VAR17;
wire VAR3;
wire clk;
reg [VAR27-1:0] counter;
VAR19 VAR8
( .VAR5 (VAR5),
.V... | gpl-3.0 |
Saucyz/explode | Hardware/Mod2/nios_system/synthesis/submodules/altera_up_clock_edge.v | 6,484 | module MODULE1 (
clk,
reset,
VAR3,
VAR6,
VAR4
);
input clk;
input reset;
input VAR3;
output VAR6;
output VAR4;
wire VAR1;
reg VAR5;
reg VAR2;
always @(posedge clk)
VAR5 <= VAR3;
always @(posedge clk)
VAR2 <= VAR5;
assign VAR6 = VAR1 & VAR5;
assign VAR4 = VAR1 & VAR2;
assign VAR1 = VAR2 ^ VAR5;
endmodule | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/cabac/cabac_cu_binari_intra_luma_mode.v | 8,200 | module MODULE1(
VAR17 ,
VAR8 ,
VAR12 ,
VAR1 ,
VAR11
);
input [5:0] VAR17 ;
input [5:0] VAR8 ;
input [5:0] VAR12 ;
output [10:0] VAR1 ;
output [10:0] VAR11 ;
reg [5:0] VAR7 , VAR3 , VAR5 ;
reg [1:0] VAR9 ;
wire VAR15 ,VAR20 ,VAR10 ;
reg [5:0] VAR13 ,VAR6 ,VAR19 ;
wire [5:0] VAR4 ;
wire [5:0] VAR2 ;
wire [5:0] VAR18 ;
re... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_sa1/sa1_mult.v | 4,644 | module MODULE1 (
VAR20,
VAR2,
VAR19,
VAR3);
input VAR20;
input [15:0] VAR2;
input [15:0] VAR19;
output [31:0] VAR3;
wire [31:0] VAR4;
wire [31:0] VAR3 = VAR4[31:0];
VAR1 VAR10 (
.VAR20 (VAR20),
.VAR2 (VAR2),
.VAR19 (VAR19),
.VAR3 (VAR4),
.VAR6 (1'b0),
.VAR8 (1'b1),
.VAR12 (1'b0),
.sum (1'b0));
VAR10.VAR9 = "VAR16=5",
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a311oi/sky130_fd_sc_ms__a311oi.pp.symbol.v | 1,402 | module MODULE1 (
input VAR10 ,
input VAR4 ,
input VAR1 ,
input VAR2 ,
input VAR5 ,
output VAR7 ,
input VAR9 ,
input VAR8,
input VAR6,
input VAR3
);
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai31/gf180mcu_fd_sc_mcu7t5v0__oai31_4.functional.v | 1,436 | module MODULE1( VAR4, VAR1, VAR2, VAR12, VAR14 );
input VAR2, VAR12, VAR4, VAR14;
output VAR1;
wire VAR15;
not VAR6( VAR15, VAR2 );
wire VAR11;
not VAR3( VAR11, VAR12 );
wire VAR10;
not VAR13( VAR10, VAR4 );
wire VAR9;
and VAR16( VAR9, VAR15, VAR11, VAR10 );
wire VAR7;
not VAR5( VAR7, VAR14 );
or VAR8( VAR1, VAR9, VAR7... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_ssi/rtl/jbi_ssi_sif.v | 23,983 | module MODULE2(
VAR75, VAR112, VAR156,
VAR66, VAR21, VAR102,
VAR56, VAR71,
clk, VAR158, VAR121, VAR48, VAR65,
VAR7, VAR149, VAR101, VAR87,
VAR50, VAR131, VAR125,
VAR91
);
input clk;
input VAR158;
input VAR121;
input VAR48;
input [VAR30-1:0] VAR65;
input VAR7;
output VAR75; output VAR112; output VAR156;
output VAR66;
in... | gpl-2.0 |
hakehuang/pycpld | ips/ip/spi_master_kl/spi_ctrl.v | 1,349 | module MODULE1(
clk,VAR2,VAR8,VAR4,VAR16,VAR12,VAR7,VAR18,VAR10,VAR3
);
input clk,VAR2,VAR16;
input VAR10;
output VAR8,VAR4,VAR12;
output VAR3;
input VAR7;
input VAR18;
wire VAR17;
wire VAR3;
wire VAR15;
reg VAR6;
reg VAR12;
reg[7:0] VAR19;
reg[7:0] VAR14;
reg VAR9;
always @(posedge clk or negedge VAR2) begin
if(!VAR2)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221oi/sky130_fd_sc_ms__a221oi.functional.v | 1,582 | module MODULE1 (
VAR12 ,
VAR7,
VAR5,
VAR4,
VAR9,
VAR1
);
output VAR12 ;
input VAR7;
input VAR5;
input VAR4;
input VAR9;
input VAR1;
wire VAR11 ;
wire VAR13 ;
wire VAR2;
and VAR3 (VAR11 , VAR4, VAR9 );
and VAR10 (VAR13 , VAR7, VAR5 );
nor VAR6 (VAR2, VAR11, VAR1, VAR13);
buf VAR8 (VAR12 , VAR2 );
endmodule | apache-2.0 |
KestrelComputer/gpia3 | bench/verilog/GPIA_BYTE.v | 4,992 | module MODULE1();
reg VAR9;
reg VAR3;
reg [7:0] VAR4;
reg [1:0] VAR6;
reg [7:0] do;
reg VAR7;
wire [7:0] VAR2;
VAR14 VAR15 (
.VAR1(VAR9),
.VAR8(VAR3),
.VAR13(VAR6),
.VAR5(do),
.VAR16(VAR7),
.VAR11(VAR2)
);
always begin
VAR9 <= ~VAR9;
end
task VAR10;
begin @(negedge VAR9); @(posedge VAR9);
end
endtask
task VAR12;
begin
... | mpl-2.0 |
fallen/milkymist-mmu | cores/tmu2/rtl/tmu2_hinterp.v | 2,614 | module MODULE1(
input VAR25,
input VAR28,
output VAR9,
input VAR14,
output VAR11,
input signed [11:0] VAR19,
input signed [11:0] VAR34,
input signed [17:0] VAR6,
input signed [17:0] VAR15,
input VAR21,
input [16:0] VAR10,
input [16:0] VAR4,
input VAR31,
input [16:0] VAR18,
input [16:0] VAR3,
input [10:0] VAR16,
output ... | lgpl-3.0 |
kielfriedt/ece472 | lab3/lookahead.v | 1,396 | module MODULE1(VAR2, VAR4, VAR1, VAR6, VAR7, VAR5, VAR3);
input [3:0] VAR6, VAR7;
input VAR2;
output [2:0] VAR1;
output VAR4;
output VAR5, VAR3;
assign VAR1[0] = VAR7[0] | (VAR6[0] & VAR2);
assign VAR1[1] = VAR7[1] | (VAR7[0] & VAR6[1]) | (VAR6[1] & VAR6[0] & VAR2);
assign VAR1[2] = VAR7[2] | (VAR7[1] & VAR6[2]) | (VAR... | gpl-3.0 |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/spi_interface.v | 5,891 | module MODULE1 (
input wire clk, input wire reset,
input wire [31:0] VAR7,
output reg [31:0] VAR3,
input wire [7:0] VAR1,
input wire [7:0] VAR2,
input wire VAR11,
output wire VAR13,
output wire VAR22,
inout wire VAR15,
output reg VAR5
);
localparam VAR18 = 3'd0,
VAR27 = 3'd1,
VAR10 = 3'd2,
VAR28 = 3'd3,
VAR20 = 3'd4;
l... | gpl-2.0 |
FAST-Switch/fast | lib/hardware/pipeline/IPE_IF_OPENFLOW/SGMII_RX1.v | 16,210 | module MODULE1
(reset,
VAR24,
VAR21,
VAR35,
VAR32,
VAR17,
VAR25,
VAR9,
VAR34,
VAR23,
VAR7,
VAR6,
VAR36,
VAR29,
VAR18,
VAR12,
VAR28,
VAR15,
VAR30,
VAR14
);
input reset;
input VAR24;
output VAR21;
input [7:0] VAR35;
input VAR32;
input VAR17;
input [5:0] VAR25;
input [17:0] VAR9;
input [3:0] VAR34;
input VAR23;
input VAR7... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_Video_In_video_dma_controller_0.v | 7,553 | module MODULE1 (
clk,
reset,
VAR15,
VAR17,
VAR35,
VAR16,
VAR9,
VAR26,
VAR20,
VAR30,
VAR4,
VAR37,
VAR34,
VAR33,
VAR22,
VAR18,
VAR8,
VAR6
);
parameter VAR29 = 7; parameter VAR10 = 0; parameter VAR24 = 640; parameter VAR42 = 480;
parameter VAR45 = 18; parameter VAR19 = 9; parameter VAR43 = 8;
parameter VAR14 = 7;
paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21ba/sky130_fd_sc_hdll__o21ba.symbol.v | 1,394 | module MODULE1 (
input VAR6 ,
input VAR2 ,
input VAR7,
output VAR8
);
supply1 VAR4;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig_stub.v | 3,002 | module MODULE1(VAR14, VAR35, VAR18, VAR6, VAR12, VAR31, VAR32, VAR13, VAR3, VAR36, VAR22, VAR10, VAR24, VAR1, VAR11, VAR21, VAR29, VAR4, VAR16, VAR2, VAR20, VAR19, VAR30, VAR23, VAR7, VAR26, VAR37, VAR33, VAR38, VAR5, VAR15, VAR9, VAR34, VAR28, VAR17, VAR25, VAR8, VAR27)
;
inout [15:0]VAR14;
inout [1:0]VAR35;
inout [1:... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and4/sky130_fd_sc_hd__and4_1.v | 2,242 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR8 ,
VAR3 ,
VAR11 ,
VAR10,
VAR4,
VAR5 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR3 ;
input VAR11 ;
input VAR10;
input VAR4;
input VAR5 ;
input VAR1 ;
VAR9 VAR6 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR5(VAR5),
.... | apache-2.0 |
Murailab-arch/magukara | cores/coregen/asfifo9_4.v | 5,147 | module MODULE1(
din,
VAR81,
VAR94,
rst,
VAR73,
VAR3,
dout,
VAR98,
VAR41);
input [8 : 0] din;
input VAR81;
input VAR94;
input rst;
input VAR73;
input VAR3;
output [8 : 0] dout;
output VAR98;
output VAR41;
VAR51 #(
.VAR92(0),
.VAR87(0),
.VAR7(4),
.VAR58("VAR62"),
.VAR44(9),
.VAR54("0"),
.VAR52(9),
.VAR23(0),
.VAR85("VAR7... | gpl-3.0 |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/soc_system/synthesis/submodules/hps_sdram_p0_iss_probe.v | 1,734 | module MODULE1 (
VAR2
);
parameter VAR8 = 1;
parameter VAR9 = "VAR27";
input [VAR8-1:0] VAR2;
VAR19 VAR26 (
.VAR33 (VAR2),
.VAR1 ()
,
.VAR23 (),
.VAR32 (),
.VAR17 (),
.VAR5 (),
.VAR3 (),
.VAR13 (),
.VAR16 (),
.VAR7 (),
.VAR12 (),
.VAR21 (),
.VAR30 (),
.VAR15 (),
.VAR25 (),
.VAR34 (),
.VAR11 (),
.VAR29 (),
.VAR14 ()
);
... | apache-2.0 |
Jawanga/ece385lab9 | lab9_soc/synthesis/submodules/lab9_soc_jtag_uart_0.v | 17,487 | module MODULE4 (
clk,
VAR38,
VAR14,
VAR25,
VAR37,
VAR51,
VAR42
)
;
output VAR25;
output [ 7: 0] VAR37;
output VAR51;
output [ 5: 0] VAR42;
input clk;
input [ 7: 0] VAR38;
input VAR14;
wire VAR25;
wire [ 7: 0] VAR37;
wire VAR51;
wire [ 5: 0] VAR42;
always @(posedge clk)
begin
if (VAR14)
("%VAR24", VAR38);
end
assign VAR... | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | ICARUS-LX150/uart_receiver.v | 3,415 | module MODULE2 # (
parameter VAR7 = 100000000,
parameter VAR11 = 115200
) (
input clk,
input VAR12,
output reg VAR2 = 1'b0,
output reg [7:0] VAR9 = 8'd0
);
localparam [15:0] VAR17 = (VAR7 / VAR11) - 1;
wire VAR8;
MODULE1 MODULE1 (
.clk (clk),
.VAR12 (VAR12),
.VAR3 (VAR8)
);
reg VAR15 = 1'b1, VAR14 = 1'b1;
reg [15:0] VA... | gpl-3.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/db/ip/niosii/niosii.v | 67,608 | module MODULE1 (
input wire VAR67, output wire VAR337, output wire VAR84, output wire VAR236, input wire VAR161, output wire [1:0] VAR301, output wire [1:0] VAR339, output wire [7:0] VAR326, input wire VAR108, input wire VAR320, output wire VAR5 );
wire VAR82; wire VAR262; wire VAR72; wire VAR44; wire [31:0] VAR32; wir... | mit |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | Gray_Processing/ip/Gray_Processing/acl_work_item_iterator.v | 6,484 | module MODULE1 #(parameter VAR17=32) (
input VAR9,
input VAR19,
input VAR20, input VAR21, input [VAR17-1:0] VAR7[2:0],
input [VAR17-1:0] VAR3[2:0],
input [VAR17-1:0] VAR5[2:0],
output reg [VAR17-1:0] VAR2[2:0],
output reg [VAR17-1:0] VAR6[2:0],
output VAR13
);
wire [VAR17-1:0] VAR18 = VAR6[0] + VAR3[0] * ( VAR6[1] + VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.behavioral.pp.v | 1,810 | module MODULE1 (
VAR11 ,
VAR1 ,
VAR14 ,
VAR9 ,
VAR12,
VAR2,
VAR7 ,
VAR3
);
output VAR11 ;
input VAR1 ;
input VAR14 ;
input VAR9 ;
input VAR12;
input VAR2;
input VAR7 ;
input VAR3 ;
wire VAR10 ;
wire VAR6;
and VAR4 (VAR10 , VAR9, VAR1, VAR14 );
VAR13 VAR8 (VAR6, VAR10, VAR12, VAR2);
buf VAR5 (VAR11 , VAR6 );
endmodule | apache-2.0 |
yunqu/PYNQ | boards/ip/boolean_generator_1.1/src/boolean_gr.v | 2,772 | module MODULE1 # (parameter VAR6 = 24) (
input clk, input [VAR6-1:0] VAR5, input VAR16, input [31:0] VAR29, input [24:0] VAR25, output VAR4 );
wire VAR1;
wire VAR10;
wire [4:0] VAR12;
VAR20 #(
.VAR3(1'b0) ) VAR21 (
.VAR22(VAR15), .VAR11(VAR16), .VAR8(1'b1), .VAR10(VAR10), .VAR28(1'b1) );
VAR20 #(
.VAR3(1'b0) ) VAR26 (
... | bsd-3-clause |
bkboggy/MIPS | I_EXECUTE.v | 2,839 | module MODULE1(
input clk,
input [1:0] VAR13,
input [2:0] VAR12,
input [3:0] VAR54,
input [31:0] VAR8,
input [31:0] VAR44,
input [31:0] VAR2,
input [31:0] VAR57,
input [4:0] VAR7,
input [4:0] VAR41,
input [1:0] VAR32,
input [1:0] VAR47,
input [31:0] VAR29,
input [31:0] VAR42,
output [1:0] VAR52,
output [2:0] VAR31,
out... | mit |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/user_design/rtl/phy/prbs_gen.v | 5,793 | module MODULE1 #
(
parameter VAR8 = 4
)
(
input clk,
input VAR9,
input rst,
output [VAR8-1:0] VAR3
);
localparam VAR2 = 0;
reg [VAR8 - 1:0] VAR11;
reg [VAR8 - 1:0] VAR4;
reg [3:0] VAR5;
reg VAR1, VAR6;
integer VAR7;
always @ (posedge clk)
begin
if (rst )
VAR4 <= {{VAR8-1{1'b0}},1'b1};
end
else if (VAR9) begin
if ( VAR2... | lgpl-3.0 |
intelligenttoasters/CPC2.0 | FPGA/rtl/Altera/video720/video720_0002.v | 2,073 | module MODULE1(
input wire VAR70,
input wire rst,
output wire VAR48,
output wire VAR38
);
VAR65 #(
.VAR25("true"),
.VAR22("50.0 VAR62"),
.VAR72("VAR9"),
.VAR41(1),
.VAR67("74.250000 VAR62"),
.VAR40("0 VAR16"),
.VAR28(50),
.VAR56("0 VAR62"),
.VAR58("0 VAR16"),
.VAR3(50),
.VAR29("0 VAR62"),
.VAR13("0 VAR16"),
.VAR19(50),... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nand3/sky130_fd_sc_ms__nand3.pp.blackbox.v | 1,293 | module MODULE1 (
VAR7 ,
VAR3 ,
VAR6 ,
VAR8 ,
VAR4,
VAR2,
VAR1 ,
VAR5
);
output VAR7 ;
input VAR3 ;
input VAR6 ;
input VAR8 ;
input VAR4;
input VAR2;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
wgml/sysrek | hdmi_example/src/rx_nok/serdes_1_to_5_diff_data_nok.v | 14,289 | module MODULE1 # (
parameter VAR31 = "VAR53",
parameter VAR54 = 49,
parameter VAR45 = "VAR6"
)(
input wire VAR44, input wire VAR99, input wire VAR18, input wire VAR101, input wire VAR55, input wire reset, input wire VAR24, input wire VAR86, output wire [4:0] VAR15 );
wire VAR11;
wire VAR88;
wire VAR42;
wire VAR84;
wire... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfbbp/sky130_fd_sc_ms__sdfbbp.functional.pp.v | 2,572 | module MODULE1 (
VAR3 ,
VAR20 ,
VAR9 ,
VAR7 ,
VAR11 ,
VAR8 ,
VAR23 ,
VAR14,
VAR10 ,
VAR17 ,
VAR18 ,
VAR5
);
output VAR3 ;
output VAR20 ;
input VAR9 ;
input VAR7 ;
input VAR11 ;
input VAR8 ;
input VAR23 ;
input VAR14;
input VAR10 ;
input VAR17 ;
input VAR18 ;
input VAR5 ;
wire VAR22 ;
wire VAR25 ;
wire VAR24 ;
wire VAR2... | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/ik_swift_master_0.v | 19,029 | module MODULE1 #(
parameter VAR18 = 0,
parameter VAR38 = 50000,
parameter VAR12 = 2
) (
input wire VAR16, input wire VAR3, output wire [31:0] VAR45, input wire [31:0] VAR9, output wire VAR1, output wire VAR4, output wire [31:0] VAR17, input wire VAR33, input wire VAR15, output wire [3:0] VAR11, output wire VAR47 );
wir... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9652/axi_ad9652_pnmon.v | 7,070 | module MODULE1 (
VAR11,
VAR9,
VAR8,
VAR12,
VAR1);
input VAR11;
input [15:0] VAR9;
output VAR8;
output VAR12;
input [ 3:0] VAR1;
reg VAR4 = 'd0;
reg [31:0] VAR10 = 'd0;
reg [31:0] VAR7 = 'd0;
wire [31:0] VAR14;
function [31:0] VAR16;
input [31:0] din;
reg [31:0] dout;
begin
dout[31] = din[22] ^ din[17];
dout[30] = din[2... | gpl-3.0 |
Darkin47/Zynq-TX-UTT | Vivado_HLS/image_histogram/solution1/impl/ip/hdl/verilog/doHist.v | 11,767 | module MODULE1 (
VAR50,
VAR46,
VAR29,
VAR24,
VAR60,
VAR64,
VAR28,
VAR39,
VAR75,
VAR10,
VAR67,
VAR13,
VAR4,
VAR85,
VAR6,
VAR86,
VAR36,
VAR52,
VAR32,
VAR72,
VAR5,
VAR41,
VAR9,
VAR84,
VAR35,
VAR54,
VAR79,
VAR26,
VAR48,
VAR17,
VAR47,
VAR2,
VAR68,
VAR82,
VAR62,
interrupt
);
parameter VAR27 = 4'b1;
parameter VAR25 = 4'b10;
p... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inputiso1p/sky130_fd_sc_lp__inputiso1p.functional.v | 1,271 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3
);
output VAR4 ;
input VAR2 ;
input VAR3;
or VAR1 (VAR4 , VAR2, VAR3 );
endmodule | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/address.v | 9,049 | module MODULE1(
input VAR31,
input [15:0] VAR34, input [2:0] VAR28, input [23:0] VAR26, input [7:0] VAR38, input VAR39, output [23:0] VAR24, output VAR11, output VAR45, output VAR33, output VAR35, input [23:0] VAR36,
input [23:0] VAR43,
output VAR7,
output VAR27,
output VAR8,
output VAR3,
input [14:0] VAR44,
output VAR... | gpl-2.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_shift_reg.v | 2,732 | module MODULE1
(clk, reset, enable, VAR14, VAR10);
parameter VAR4 = 32;
parameter VAR13 = 2;
parameter VAR12 = VAR1;
input clk;
input reset;
input enable;
input [0:VAR4-1] VAR14;
output [0:VAR4-1] VAR10;
wire [0:VAR4-1] VAR10;
genvar VAR2;
wire [0:(VAR13+1)*VAR4-1] VAR5;
assign VAR5[0:VAR4-1] = VAR14;
generate
for(VAR2... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/led_controller/led_controller.srcs/sources_1/bd/led_controller_design/ip/led_controller_design_led_controller_0_0/synth/led_controller_design_led_controller_0_0.v | 7,076 | module MODULE1 (
VAR22,
VAR7,
VAR23,
VAR8,
VAR13,
VAR24,
VAR15,
VAR11,
VAR5,
VAR16,
VAR6,
VAR3,
VAR12,
VAR25,
VAR18,
VAR10,
VAR9,
VAR4,
VAR14,
VAR2,
VAR21,
VAR19
);
output wire [7 : 0] VAR22;
input wire [3 : 0] VAR7;
input wire [2 : 0] VAR23;
input wire VAR8;
output wire VAR13;
input wire [31 : 0] VAR24;
input wire [3 ... | mit |
Pylonight/MIPS-CPU | cpu/Immediate_Extend.v | 1,047 | module MODULE1(
output [15 : 0] VAR2,
input [2 : 0] VAR3,
input [15 : 0] VAR1
);
assign VAR2 =
(VAR3 == 0) ? {{8{VAR1[7]}}, VAR1[7 : 0]} :
(VAR3 == 1) ? {{12{VAR1[3]}}, VAR1[3 : 0]} :
(VAR3 == 2) ? {{5{VAR1[10]}}, VAR1[10 : 0]} :
(VAR3 == 3) ? {12'b0, VAR1[3 : 0]} :
(VAR3 == 4) ? {8'b0, VAR1[7 : 0]} :
(VAR3 == 5) ? {{1... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.v | 2,063 | module MODULE1 (
VAR6 ,
VAR3 ,
VAR4,
VAR2,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR3 ;
input VAR4;
input VAR2;
input VAR7 ;
input VAR5 ;
VAR1 VAR8 (
.VAR6(VAR6),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR6,
VAR3
);
output VAR6;
input VAR3;
supply1 VAR4;
supply0 VAR2;... | apache-2.0 |
borti4938/n64rgb | generalRGBmod/firmware/rtl/n64rgb_hk.v | 6,114 | module MODULE1 (
input VAR26,
input VAR3,
output reg VAR30,
input VAR25,
input VAR11,
input VAR14,
input VAR1,
input VAR24,
input VAR23,
output reg VAR13,
output reg VAR22
);
reg VAR15 = 1'b0; reg [2:0] VAR16 = 3'b000;
always @(posedge VAR26) begin
if (VAR16 == 3'b101) begin
VAR15 <= ~VAR15;
VAR16 <= 3'b000;
end else
V... | gpl-3.0 |
markusC64/1541ultimate2 | fpga/nios_dut/nios_dut/synthesis/submodules/nios_dut_audio_out_dma.v | 17,861 | module MODULE1 (
output wire [25:0] VAR17, output wire VAR22, output wire [3:0] VAR97, input wire [31:0] VAR88, input wire VAR58, input wire VAR32, input wire VAR10, input wire VAR36, input wire [31:0] VAR110, input wire VAR5, input wire [3:0] VAR12, output wire [31:0] VAR68, input wire VAR73, input wire [2:0] VAR41, i... | gpl-3.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/up_adc_channel.v | 14,496 | module MODULE1 (
VAR31,
VAR56,
VAR68,
VAR64,
VAR80,
VAR26,
VAR27,
VAR77,
VAR23,
VAR65,
VAR25,
VAR33,
VAR42,
VAR32,
VAR75,
VAR35,
VAR45,
VAR30,
VAR73,
VAR62,
VAR14,
VAR38,
VAR54,
VAR55,
VAR4,
VAR6,
VAR67,
VAR48,
VAR7,
VAR52,
VAR59,
VAR19,
VAR53,
VAR43,
VAR69,
VAR5,
VAR22,
VAR51,
VAR37,
VAR2,
VAR49,
VAR63);
parameter VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxbp/sky130_fd_sc_ls__edfxbp_1.v | 2,375 | module MODULE2 (
VAR9 ,
VAR7 ,
VAR8 ,
VAR3 ,
VAR6 ,
VAR4,
VAR2,
VAR10 ,
VAR5
);
output VAR9 ;
output VAR7 ;
input VAR8 ;
input VAR3 ;
input VAR6 ;
input VAR4;
input VAR2;
input VAR10 ;
input VAR5 ;
VAR1 VAR11 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR10(VAR10),
.VA... | apache-2.0 |
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