repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
parallella/oh | mio/hdl/mrx.v | 3,500 | module MODULE1 # ( parameter VAR9 = 104, parameter VAR4 = 32, parameter VAR13 = 8, parameter VAR29 = 16, parameter VAR2 = "VAR28" )
( input clk, input VAR24, input VAR15,
input [1:0] VAR3,
input VAR14, input [4:0] VAR18, input [1:0] VAR7, input [VAR4-1:0] VAR12, input VAR17, output VAR6, output VAR8, output VAR21, inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvgnd/sky130_fd_sc_hd__tapvgnd_1.v | 1,938 | module MODULE2 (
VAR1,
VAR4,
VAR3 ,
VAR5
);
input VAR1;
input VAR4;
input VAR3 ;
input VAR5 ;
VAR2 VAR6 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR5(VAR5)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
VAR2 VAR6 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2.behavioral.v | 1,402 | module MODULE1 (
VAR1 ,
VAR7 ,
VAR8
);
output VAR1 ;
input VAR7 ;
input VAR8;
supply1 VAR3;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR6 ;
bufif0 VAR2 (VAR1 , VAR7, VAR8 );
endmodule | apache-2.0 |
glenux/contrib-linguist | samples/Verilog/mux.v | 1,180 | module MODULE1(VAR1,VAR4,sum,VAR2,out);
input [3:0] VAR1,VAR4;
input [4:0] sum;
input [1:0] VAR2;
output [3:0] out;
reg VAR3;
always @ (sum)
begin
if (sum[4] == 1)
VAR3 <= 4'b0001;
end
else
VAR3 <= 4'b0000;
end
reg out;
always @(VAR2,sum,VAR3,VAR4,VAR1)
begin
if (VAR2 == 2'b00)
out <= sum[3:0];
end
else if (VAR2 == 2'b... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/aoi21/gf180mcu_fd_sc_mcu9t5v0__aoi21_4.behavioral.v | 1,495 | module MODULE1( VAR6, VAR7, VAR3, VAR5 );
input VAR6, VAR7, VAR5;
output VAR3;
VAR4 VAR1(.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR5(VAR5));
VAR4 VAR2(.VAR6(VAR6),.VAR7(VAR7),.VAR3(VAR3),.VAR5(VAR5)); | apache-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/master_wb.v | 3,585 | module MODULE1(
input clk,
input rst,
output reg VAR20,
input wire VAR12,
input wire VAR9,
input wire [31:0] VAR3,
input wire [31:0] VAR4,
output reg [31:0] VAR13,
input VAR16,
input [31:0] VAR15,
input VAR21,
output reg [31:0] VAR7,
output reg VAR14,
output [3:0] VAR11,
output reg [31:0] VAR10,
output reg VAR17,
outpu... | mit |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/xilinx_com_hls_nco_1_0/hdl/verilog/nco.v | 7,324 | module MODULE1 (
VAR32,
VAR62,
VAR75,
VAR60,
VAR79,
VAR73,
VAR45,
VAR77,
VAR80,
VAR57,
VAR58,
VAR7,
VAR27,
VAR47,
VAR46,
VAR41,
VAR34,
VAR29,
VAR55
);
parameter VAR6 = 1'b1;
parameter VAR56 = 1'b0;
parameter VAR59 = 2'b1;
parameter VAR43 = 2'b10;
parameter VAR48 = 32;
parameter VAR40 = 8;
parameter VAR3 = 6;
parameter ... | mit |
toomij/DE2Labs | Lab2/lab2_part7.v | 2,240 | module MODULE1 (VAR10, VAR1, VAR5, VAR8);
input [5:0] VAR10;
output [0:6] VAR5, VAR8;
output [5:0] VAR1;
reg [3:0] VAR6, VAR9;
assign VAR1 = VAR10;
always begin
if (VAR10[5:0] > 59) begin
VAR6 = 6;
VAR9 = VAR10[5:0] - 60;
end else if (VAR10[5:0] > 49) begin
VAR6 = 5;
VAR9 = VAR10[5:0] - 50;
end else if (VAR10[5:0] > 39... | gpl-2.0 |
benreynwar/fpga-sdrlib | verilog/fpgamath/qa_multiply_complex.v | 1,639 | module MODULE1
parameter VAR12 = 32,
parameter VAR2 = 1
)
(
input wire clk,
input wire VAR9,
input wire [VAR12-1:0] VAR18,
input wire VAR17,
input wire [VAR2-1:0] VAR3,
input wire [VAR20-1:0] VAR7,
input wire VAR21,
output wire [VAR12-1:0] VAR14,
output reg VAR15,
output reg [VAR2-1:0] VAR8,
output wire [VAR20-1:0] VAR... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig34/mig_v3_4/user_design/rtl/controller/rank_common.v | 15,104 | module MODULE1 #
(
parameter VAR4 = 100,
parameter VAR7 = "VAR77",
parameter VAR59 = 40,
parameter VAR36 = 4,
parameter VAR63 = 2,
parameter VAR73 = 4,
parameter VAR39 = 39,
parameter VAR26 = 640000
)
(
VAR3, VAR60, VAR71, VAR16,
VAR55, VAR74, VAR58,
VAR65,
clk, rst, VAR38, VAR49, VAR66,
VAR80, VAR56, VAR32, VAR12,
VAR... | lgpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/emon/hdl/axi_emon.v | 6,744 | module MODULE1 (
VAR14, VAR3, VAR46, VAR4,
VAR20, VAR7, VAR16, VAR23,
VAR11,
VAR41, VAR8, VAR19, VAR18,
VAR33, VAR2, VAR32, VAR40,
VAR9, VAR5, VAR6, VAR24,
VAR39, VAR30, VAR36,
VAR35, VAR10, VAR15,
VAR22, VAR1, VAR44,
VAR13, VAR12, VAR21,
VAR31
);
parameter VAR25 = 32; parameter VAR34 = 32; parameter VAR38 = VAR25/8; p... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp.symbol.v | 1,329 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR7
);
supply1 VAR6;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/azpr_soc/cpu/rtl/id_stage.v | 7,148 | module MODULE1 (
input wire clk, input wire reset,
input wire [VAR28] VAR48, input wire [VAR28] VAR5, output wire [VAR18] VAR49, output wire [VAR18] VAR47,
input wire VAR42, input wire [VAR28] VAR45, input wire [VAR18] VAR1, input wire VAR33, input wire [VAR28] VAR43,
input wire [VAR23] VAR50, input wire [VAR28] VAR3, ... | apache-2.0 |
bangonkali/quartus-sockit | soc_system/synthesis/submodules/alt_vipitc131_common_sample_counter.v | 1,560 | module MODULE1
VAR6 = 0,
VAR9 = 0,
VAR10 = 0)
(
input wire rst,
input wire clk,
input wire VAR8,
input wire VAR11,
input wire VAR7,
output wire VAR2,
output wire VAR1,
output wire [VAR10-1:0] VAR3);
generate
if(VAR6 == 1) begin
assign VAR2 = VAR11;
assign VAR1 = 1'b1;
assign VAR3 = 1'b0;
end else begin
reg [VAR10-1:0] ... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/spree/data_mem.v | 7,619 | module MODULE3( clk, VAR23, en,
VAR30,
VAR5,
VAR24, VAR15, VAR1,
VAR12,
VAR7,
VAR4,
VAR19,
VAR20,
VAR21
);
parameter VAR13=32;
parameter VAR29=32;
parameter VAR6=4; parameter VAR3=16;
parameter VAR8=16384;
input clk;
input VAR23;
input en;
input [31:0] VAR24;
input [31:0] VAR15;
input VAR1;
input [VAR13-1:0] VAR5;
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o221ai/sky130_fd_sc_ms__o221ai.symbol.v | 1,402 | module MODULE1 (
input VAR10,
input VAR3,
input VAR7,
input VAR2,
input VAR9,
output VAR6
);
supply1 VAR1;
supply0 VAR5;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311ai/sky130_fd_sc_hd__o311ai.symbol.v | 1,380 | module MODULE1 (
input VAR5,
input VAR2,
input VAR7,
input VAR4,
input VAR10,
output VAR9
);
supply1 VAR1;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
Triple-Z/COExperiment_Repo | Project_Assignment_OnBoard/data_ram.v | 3,984 | module MODULE1(
input clk, input [3:0] VAR3, input [4:0] addr, input [31:0] VAR5, output reg [31:0] VAR6,
input [4 :0] VAR2,
output reg [31:0] VAR1
);
reg [31:0] VAR4[31:0];
always @(posedge clk) begin
if (VAR3[3])
begin
VAR4[addr][31:24] <= VAR5[31:24];
end
end
always @(posedge clk)
begin
if (VAR3[2])
begin
VAR4[addr]... | mit |
OpticalMeasurementsSystems/2DImageProcessing | 2d_image_processing.srcs/sources_1/bd/image_processing_2d_design/ipshared/xilinx.com/generic_baseblocks_v2_1/hdl/verilog/generic_baseblocks_v2_1_command_fifo.v | 16,257 | module MODULE1 #
(
parameter VAR71 = "VAR29",
parameter integer VAR30 = 0,
parameter integer VAR25 = 0,
parameter integer VAR26 = 5, parameter integer VAR97 = 64 )
(
input wire VAR95, input wire VAR52, output wire VAR10, input wire [VAR97-1:0] VAR51, input wire VAR92, output wire VAR45, output wire [VAR97-1:0] VAR61, o... | gpl-2.0 |
ThotIP/async_fifo | src/vlog/async_bidir_fifo.v | 5,398 | module MODULE1
parameter VAR26 = 8,
parameter VAR32 = 4,
parameter VAR46 = "VAR45" ) (
input wire VAR22,
input wire VAR28,
input wire VAR48,
input wire [VAR26-1:0] VAR57,
input wire VAR65,
output wire [VAR26-1:0] VAR31,
output wire VAR61,
output wire VAR38,
output wire VAR62,
output wire VAR63,
input wire VAR14,
input ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrtp/sky130_fd_sc_lp__dlrtp.symbol.v | 1,428 | module MODULE1 (
input VAR8 ,
output VAR6 ,
input VAR3,
input VAR5
);
supply1 VAR1;
supply0 VAR4;
supply1 VAR2 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
P3Stor/P3Stor | DDR3/ip_top/example_top.v | 38,103 | module MODULE1 #
(
parameter VAR174 = 200,
parameter VAR235 = "VAR323",
parameter VAR352 = "VAR78",
parameter VAR48 = 8,
parameter VAR37 = 2,
parameter VAR80 = 4,
parameter VAR197 = 2,
parameter VAR58 = 2500,
parameter VAR280 = "VAR185",
parameter VAR198 = "VAR27",
parameter VAR136 = 1,
parameter VAR42 = 3,
parameter V... | gpl-2.0 |
chebykinn/university | circuitry/lab4/src/hdl/control.v | 4,101 | module MODULE1( input [5:0] VAR19,
input [5:0] VAR6,
input VAR10,
output reg [1:0] VAR17,
output VAR25,
output VAR29,
output reg VAR14,
output reg VAR11, output reg [1:0] VAR9,
output reg [1:0] VAR16,
output reg VAR3,
output reg VAR30,
output reg VAR12,
output reg VAR5 );
localparam VAR22 = 6'b100011,
VAR1 = 6'b101011,... | mit |
nishtahir/arty-blaze | src/bd/system/ip/system_dlmb_v10_0/system_dlmb_v10_0_stub.v | 2,259 | module MODULE1(VAR3, VAR24, VAR22, VAR5, VAR7,
VAR1, VAR21, VAR12, VAR16, VAR23, VAR25, VAR17, VAR6, VAR9, VAR19,
VAR13, VAR11, VAR14, VAR8, VAR4, VAR20,
VAR2, VAR18, VAR15, VAR10)
;
input VAR3;
input VAR24;
output VAR22;
input [0:31]VAR5;
input VAR7;
input VAR1;
input VAR21;
input [0:31]VAR12;
input [0:3]VAR16;
input ... | apache-2.0 |
linuxbest/lzs | pcores/comp_unit_v1_00_a/hdl/verilog/comp_copy.v | 13,218 | module MODULE1(
VAR30, VAR86, VAR48, VAR82, VAR62,
VAR78, VAR58, VAR102, VAR65,
VAR20, VAR71, VAR95, VAR74,
VAR80, VAR91, VAR16, VAR88, VAR24,
VAR45, VAR97, VAR4
);
input VAR20;
output VAR30;
input VAR71;
output [31:0] VAR86;
output [3:0] VAR48;
output VAR82;
output VAR62;
output VAR78;
output VAR58;
output VAR102;
inp... | gpl-2.0 |
peteasa/parallella-fpga | AdiHDLLib/library/common/up_delay_cntrl.v | 6,788 | module MODULE1 (
VAR21,
VAR22,
VAR32,
VAR11,
VAR29,
VAR27,
VAR7,
VAR24,
VAR20,
VAR4,
VAR26,
VAR8,
VAR2,
VAR15,
VAR34,
VAR5);
parameter VAR6 = 8;
parameter VAR25 = 6'h02;
input VAR21;
output VAR22;
input VAR32;
output [(VAR6-1):0] VAR11;
output [((VAR6*5)-1):0] VAR29;
input [((VAR6*5)-1):0] VAR27;
input VAR7;
input VAR2... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o31ai/sky130_fd_sc_hd__o31ai_1.v | 2,335 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR5 ,
VAR8 ,
VAR3 ,
VAR7,
VAR10,
VAR11 ,
VAR1
);
output VAR6 ;
input VAR2 ;
input VAR5 ;
input VAR8 ;
input VAR3 ;
input VAR7;
input VAR10;
input VAR11 ;
input VAR1 ;
VAR9 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR11(VAR11),
.... | apache-2.0 |
fpgasystems/caribou | hw/src/net/ten_gig_eth_pcs_pma_ip_GT_Common_wrapper.v | 9,579 | module MODULE1 # (
parameter VAR72 = "false" ) (
input VAR66,
input VAR78,
input VAR75,
output VAR19,
output VAR45,
output VAR18,
output VAR68
);
parameter VAR73 = 66;
parameter VAR14 = (VAR73 == 16) ? 10'b0000100000 :
(VAR73 == 20) ? 10'b0000110000 :
(VAR73 == 32) ? 10'b0001100000 :
(VAR73 == 40) ? 10'b0010000000 :
(V... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_027.v | 1,520 | module MODULE1 (
VAR6,
VAR5
);
input [31:0] VAR6;
output [31:0]
VAR5;
wire [31:0]
VAR14,
VAR12,
VAR9,
VAR2,
VAR10,
VAR11,
VAR1,
VAR8,
VAR13;
assign VAR14 = VAR6;
assign VAR8 = VAR10 << 2;
assign VAR13 = VAR1 + VAR8;
assign VAR2 = VAR9 << 3;
assign VAR10 = VAR9 + VAR2;
assign VAR12 = VAR14 << 9;
assign VAR9 = VAR14 + VA... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_buffer.v | 4,823 | module MODULE1
parameter
VAR29 = 3,
VAR6 = 8,
VAR32 = 0
)
(
VAR37,
VAR49,
VAR25,
VAR53,
VAR47,
VAR50,
VAR31,
VAR20
);
localparam VAR1 = VAR60(VAR29);
localparam VAR11 = (VAR32) ? "VAR66" : "VAR14";
input VAR37;
input VAR49;
input VAR25;
input [VAR29-1:0] VAR53;
input [VAR6-1:0] VAR47;
input VAR50;
input [VAR29-1:0] VAR... | gpl-3.0 |
sergachev/spi_mem_programmer | qspi_mem_controller.v | 7,564 | module MODULE1(
input clk,
input reset,
input VAR16,
input VAR41,
input [7:0] VAR21,
input [(3+256)*8-1:0] VAR31, output reg [7:0] VAR35,
output reg VAR6,
output reg VAR15,
inout [3:0] VAR34,
output VAR23
);
reg VAR12;
wire VAR9;
reg [260*8-1:0] VAR37;
reg [8:0] VAR40;
wire [7:0] VAR42;
reg VAR8;
reg [35:0] VAR19;
reg ... | mit |
deepakcu/maestro | fpga/DE4_Ethernet_0/float_mega/float_add_sub/float_add_sub_bb.v | 3,764 | module MODULE1 (
VAR2,
VAR5,
VAR4,
VAR3,
VAR6,
VAR1);
input VAR2;
input VAR5;
input [31:0] VAR4;
input [31:0] VAR3;
output VAR6;
output [31:0] VAR1;
endmodule | apache-2.0 |
trun/fpgaboy | src/tv80/rtl/core/tv80_alu.v | 11,474 | module MODULE1 (
VAR5, VAR37,
VAR34, VAR15, VAR17, VAR24, VAR21, VAR23, VAR14, VAR19
);
parameter VAR6 = 3;
parameter VAR16 = 0;
parameter VAR11 = 1;
parameter VAR29 = 2;
parameter VAR22 = 3;
parameter VAR36 = 4;
parameter VAR4 = 5;
parameter VAR2 = 6;
parameter VAR18 = 7;
input VAR34;
input VAR15;
input [3:0] VAR17 ;
... | mit |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_2L_017bits.v | 1,917 | module MODULE1 (
clk,
VAR4, VAR29, VAR13, VAR14, VAR18, VAR2, VAR16, VAR6,
sum,
);
input clk;
input [VAR32+0-1:0] VAR4, VAR29, VAR13, VAR14, VAR18, VAR2, VAR16, VAR6;
output [VAR32 :0] sum;
reg [VAR32 :0] sum;
wire [VAR32+3-1:0] VAR7;
wire [VAR32+2-1:0] VAR25, VAR34;
wire [VAR32+1-1:0] VAR24, VAR5, VAR26, VAR17;
reg [V... | mit |
trivoldus28/pulsarch-verilog | verif/env/cmp/pc_muxsel_mon.v | 3,379 | module MODULE1(
clk, VAR6, VAR9, VAR10, VAR8, VAR3, VAR5, VAR2, VAR4, VAR7,
VAR1
);
input clk;
input VAR6;
input [47:0] VAR8;
input [47:0] VAR3;
input [47:0] VAR5;
input [47:0] VAR2;
input [47:0] VAR9;
input VAR4;
input VAR7;
input [3:0] VAR10;
input [2:0] VAR1;
reg enable;
begin
begin
begin
begin
begin
end
begin
begin... | gpl-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build4/alu_current.v | 330,545 | module MODULE1 (VAR5,VAR3,VAR6,VAR1,VAR2);
output [0:127] VAR2;
input [0:127] VAR5;
input [0:127] VAR3;
input [0:1] VAR6;
input [0:4] VAR1;
reg [0:127] VAR2;
always @(VAR5 or VAR3 or VAR6 or VAR1)
begin
case(VAR1)
begin
case(VAR6)
case(VAR3[5:7])
0:
begin
VAR2[0:7]<=VAR5[0:7]>>0;
VAR2[8:15]<=VAR5[8:15]>>0;
VAR2[16:23]<... | mit |
bigeagle/riffa | fpga/altera/de5/riffa_wrapper_de5.v | 36,275 | module MODULE1
parameter VAR62 = 128,
parameter VAR13 = 256,
parameter VAR164 = 5
)
(
input [VAR62-1:0] VAR247,
input [0:0] VAR190,
input [0:0] VAR308,
input [0:0] VAR183,
output VAR335,
input [0:0] VAR328,
output [VAR62-1:0] VAR243,
output [0:0] VAR51,
input VAR204,
output [0:0] VAR130,
output [0:0] VAR50,
output [0:0... | bsd-3-clause |
MegaShow/college-programming | Homework/Digital Circuits and Logical Design/Watch/Print.v | 1,658 | module MODULE1(
input clk, input [15:0] VAR6, input [3:0] VAR2, output reg [7:0] VAR8, output reg [3:0] VAR9 );
reg VAR7; reg [3:0] VAR1;
reg [15:0] counter;
reg [31:0] VAR5;
reg [3:0] VAR12;
parameter [15:0] VAR3 = 16'VAR10;
parameter [31:0] VAR4 = 32'VAR11; | mit |
peteasa/oh | src/common/hdl/oh_memory_ram.v | 1,496 | module MODULE1 # (parameter VAR7 = 104, parameter VAR6 = 32, parameter VAR3 = VAR15(VAR6) )
( input VAR9, input VAR14, input [VAR3-1:0] VAR12, output reg [VAR7-1:0] VAR10, input VAR4, input VAR1, input [VAR3-1:0] VAR5, input [VAR7-1:0] VAR13, input [VAR7-1:0] VAR2 );
reg [VAR7-1:0] VAR11 [VAR6-1:0];
integer VAR8;
alway... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a211o/sky130_fd_sc_hd__a211o_1.v | 2,348 | module MODULE1 (
VAR11 ,
VAR9 ,
VAR2 ,
VAR8 ,
VAR7 ,
VAR4,
VAR6,
VAR5 ,
VAR3
);
output VAR11 ;
input VAR9 ;
input VAR2 ;
input VAR8 ;
input VAR7 ;
input VAR4;
input VAR6;
input VAR5 ;
input VAR3 ;
VAR10 VAR1 (
.VAR11(VAR11),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR... | apache-2.0 |
swallat/yosys | techlibs/xilinx/lut2lut.v | 1,116 | module MODULE6(output VAR10, input VAR11);
parameter [1:0] VAR3 = 0;
\lut #(
.VAR5(1),
.VAR7(VAR3)
) VAR12 (
.VAR1(VAR11),
.VAR4(VAR10)
);
endmodule
module MODULE1(output VAR10, input VAR11, VAR13);
parameter [3:0] VAR3 = 0;
\lut #(
.VAR5(2),
.VAR7(VAR3)
) VAR12 (
.VAR1({VAR13, VAR11}),
.VAR4(VAR10)
);
endmodule
module... | isc |
EEorCS/Taximeter_on_Altera_DE2 | Verilog_sources/wait_time_module.v | 1,366 | module MODULE1 (reset, VAR3, clk, VAR1);
input clk,VAR3,reset;
output [11:0] VAR1;
reg [11:0] VAR1;
reg [5:0] VAR2;
always @ (posedge clk or negedge reset)
begin
if(!reset)
begin
VAR1 <= 0;
VAR2 <= 0;
end
else if (VAR3 == 0)
begin
if(VAR2 >= 4)
begin
VAR1 <= VAR1 +1;
VAR2 <= 0;
end
else VAR2 <= VAR2+1;
end
end
endmodul... | gpl-2.0 |
Raimmaster/Breakout-FPGA | sine_wave_rom_do.v | 1,211 | module MODULE1 (
input [4:0] address,
output reg [3:0] VAR2
);
always @ (address) begin
case (address)
5'h0: VAR2 = 4'h8;
5'h1: VAR2 = 4'h9;
5'h2: VAR2 = 4'hA;
5'h3: VAR2 = 4'hC;
5'h4: VAR2 = 4'hD;
5'h5: VAR2 = 4'hE;
5'h6: VAR2 = 4'hE;
5'h7: VAR2 = 4'hF;
5'h8: VAR2 = 4'hF;
5'h9: VAR2 = 4'hF;
5'ha: VAR2 = 4'hE;
5'hb: VA... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_2.functional.v | 1,064 | module MODULE1( VAR7, VAR8, VAR1, VAR6, VAR10 );
input VAR1, VAR8, VAR7, VAR10;
output VAR6;
or VAR11( VAR4, VAR8, VAR7 );
VAR5( VAR9, 1'b0, 1'b0, VAR1, VAR4, VAR10 );
wire VAR12;
not VAR2( VAR12, VAR9 );
or VAR3( VAR6, VAR1, VAR12 );
endmodule | apache-2.0 |
tau-tao/FPGAIPFilter | FPGA_CODE/JTAG_RW_PKT_PROC_MOORE/pll_sys_syn.v | 15,984 | module MODULE1
(
clk,
VAR36,
VAR31) ;
output [4:0] clk;
input [1:0] VAR36;
output VAR31;
tri0 [1:0] VAR36;
wire [4:0] VAR41;
wire VAR44;
wire VAR39;
VAR49 VAR29
(
.VAR37(),
.clk(VAR41),
.VAR7(),
.VAR56(VAR44),
.VAR30(VAR44),
.VAR36(VAR36),
.VAR31(VAR39),
.VAR46(),
.VAR50(),
.VAR42(),
.VAR12(),
.VAR6()
,
.VAR4(1'b0),
.V... | bsd-3-clause |
walkthetalk/fsref | ip/fsa/src/include/mutex_buffer.v | 1,495 | module MODULE1 #
(
parameter integer VAR2 = 4
) (
input wire clk,
input wire VAR9,
output wire VAR11,
input wire VAR6,
output reg [VAR2-1:0] VAR3,
input wire VAR8,
output reg [VAR2-1:0] VAR1,
input wire VAR4,
output reg [VAR2-1:0] VAR7
);
assign VAR11 = VAR6;
reg [VAR2-1:0] VAR10;
always @(posedge clk) begin
if (VAR9 =... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu7t5v0__icgtn_1.behavioral.pp.v | 2,820 | module MODULE1( VAR17, VAR23, VAR8, VAR6, VAR24, VAR20 );
input VAR8, VAR23, VAR17;
inout VAR24, VAR20;
output VAR6;
reg VAR19;
VAR25 VAR2(.VAR17(VAR17),.VAR23(VAR23),.VAR8(VAR8),.VAR6(VAR6),.VAR24(VAR24),.VAR20(VAR20),.VAR19(VAR19));
VAR25 VAR10(.VAR17(VAR17),.VAR23(VAR23),.VAR8(VAR8),.VAR6(VAR6),.VAR24(VAR24),.VAR20(... | apache-2.0 |
drichmond/riffa | fpga/riffa_hdl/tx_port_monitor_64.v | 7,934 | module MODULE1 #(
parameter VAR29 = 9'd64,
parameter VAR15 = 512,
parameter VAR37 = (VAR15 - 4),
parameter VAR7 = VAR1((2**VAR1(VAR15))+1),
parameter VAR2 = 1
)
(
input VAR12,
input VAR25,
input [VAR29:0] VAR8, input VAR4, output VAR36,
output [VAR29-1:0] VAR33, output VAR18, input [VAR7-1:0] VAR32,
output VAR24, input... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlrbn/sky130_fd_sc_lp__dlrbn.behavioral.v | 2,566 | module MODULE1 (
VAR10 ,
VAR8 ,
VAR15,
VAR7 ,
VAR4
);
output VAR10 ;
output VAR8 ;
input VAR15;
input VAR7 ;
input VAR4 ;
supply1 VAR3;
supply0 VAR19;
supply1 VAR23 ;
supply0 VAR5 ;
wire VAR25 ;
wire VAR24 ;
reg VAR14 ;
wire VAR11 ;
wire VAR16 ;
wire VAR21 ;
wire VAR2;
wire VAR12 ;
wire VAR1 ;
wire VAR9 ;
wire VAR17 ;
... | apache-2.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/pcie_core/source/pcie_core_axi_basic_rx_pipeline.v | 26,669 | module MODULE1 #(
parameter VAR55 = 128, parameter VAR73 = "VAR63", parameter VAR56 = 1,
parameter VAR32 = (VAR55 == 128) ? 2 : 1, parameter VAR24 = VAR55 / 8 ) (
output reg [VAR55-1:0] VAR17, output reg VAR79, input VAR65, output [VAR24-1:0] VAR86, output VAR18, output reg [21:0] VAR27,
input [VAR55-1:0] VAR60, input ... | lgpl-3.0 |
m-labs/milkymist | cores/tmu2/rtl/tmu2_hdiv.v | 2,556 | module MODULE1(
input VAR33,
input VAR3,
output VAR37,
input VAR20,
output reg VAR11,
input signed [11:0] VAR34,
input signed [11:0] VAR7,
input signed [17:0] VAR16,
input signed [17:0] VAR35,
input VAR10,
input [16:0] VAR27,
input VAR4,
input [16:0] VAR29,
input [10:0] VAR2,
output reg VAR8,
input VAR1,
output reg sig... | lgpl-3.0 |
cr88192/bgbtech_bjx1core | bjx1c32b1/ExOp2.v | 19,732 | module MODULE1(
VAR187, reset,
VAR1, VAR153,
VAR32, VAR85,
VAR159, VAR121,
VAR56, VAR170,
VAR34, VAR97,
VAR138, VAR106,
VAR59, VAR152,
VAR116, VAR198,
VAR166, VAR24,
VAR10, VAR82,
VAR36, VAR29,
VAR45, VAR178,
VAR123, VAR38,
VAR129, VAR161,
VAR113, VAR199,
VAR111, VAR164,
VAR185, VAR146,
VAR104, VAR22,
VAR44, VAR70,
VAR... | mit |
egyp7/mor1kx | rtl/verilog/mor1kx_cpu_prontoespresso.v | 39,002 | module MODULE1
parameter VAR3 = 32,
parameter VAR171 = "VAR233",
parameter VAR155 = 5,
parameter VAR51 = 9,
parameter VAR238 = 2,
parameter VAR277 = "VAR233",
parameter VAR123 = "VAR233",
parameter VAR202 = "VAR233",
parameter VAR211 = 5,
parameter VAR150 = 9,
parameter VAR147 = 2,
parameter VAR31 = "VAR233",
parameter... | mpl-2.0 |
Given-Jiang/Erosion_Operation_Altera_OpenCL_DE1-SoC | bin_Erosion_Operation/system/synthesis/submodules/altera_irq_bridge.v | 5,256 | module MODULE1
parameter VAR32 = 32
)
(
input clk,
input reset,
input [VAR32 - 1:0] VAR21,
output VAR33,
output VAR28,
output VAR26,
output VAR22,
output VAR29,
output VAR27,
output VAR15,
output VAR8,
output VAR2,
output VAR1,
output VAR9,
output VAR6,
output VAR24,
output VAR20,
output VAR3,
output VAR10,
output VAR1... | mit |
jairov4/accel-oil | solution_virtex5/syn/verilog/bitset_next.v | 16,667 | module MODULE1 (
VAR27,
VAR48,
VAR64,
VAR68,
VAR18,
VAR3,
VAR13,
VAR58,
VAR23,
VAR35,
VAR26,
VAR12,
VAR66,
VAR59,
VAR65
);
parameter VAR28 = 1'b1;
parameter VAR45 = 1'b0;
parameter VAR34 = 1'b0;
parameter VAR60 = 1'b0;
parameter VAR61 = 32'b00000000000000000000000000000000;
parameter VAR43 = 1'b1;
parameter VAR24 = 2'b... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkmux2/sky130_fd_sc_hdll__clkmux2.functional.v | 1,529 | module MODULE1 (
VAR1 ,
VAR5,
VAR8,
VAR2
);
output VAR1 ;
input VAR5;
input VAR8;
input VAR2 ;
wire VAR4;
VAR3 VAR7 (VAR4, VAR5, VAR8, VAR2 );
buf VAR6 (VAR1 , VAR4);
endmodule | apache-2.0 |
jhennessy/parallella-hw-old | boards/archive/gen1.1/fpga/hdl/parallella_7020_top.v | 41,853 | module MODULE1 (
VAR136, VAR291, VAR358, VAR337,
VAR297, VAR295, VAR42, VAR268, VAR204, VAR131,
VAR322, VAR254, VAR354, VAR273, VAR323, VAR261,
VAR285, VAR36, VAR301, VAR333, VAR128, VAR316,
VAR220, VAR188, VAR100, VAR242, VAR258,
VAR157, VAR307, VAR175, VAR366, VAR141,
VAR231, VAR305, VAR236, VAR11, VAR166,
VAR302, VA... | gpl-3.0 |
asicguy/gplgpu | hdl/de_temp/der_smdisp_fast.v | 8,295 | module MODULE1
(
input VAR51,
input VAR47,
input VAR8,
input VAR49,
input VAR9,
input VAR45,
input VAR33,
input [3:0] VAR27,
input [3:0] VAR14,
input [3:0] VAR16,
input VAR18, input VAR32,
output reg VAR15,
output reg VAR11, output reg VAR3, output reg VAR46, output reg VAR4,
output reg VAR54,
output reg VAR43,
output ... | gpl-3.0 |
praveendath92/securePUF | source/Frequency.v | 1,145 | module MODULE1(
input wire clk,
input wire rst,
input wire rand,
output reg VAR8
);
parameter VAR7 = 20000, VAR2 = 10182, VAR1 = 9818;
reg [14:0] VAR3, VAR6, VAR5;
always @(posedge clk)
if (rst) begin
VAR3 <= 15'VAR4;
VAR6 <= 0;
VAR5 <= 0;
VAR8 <= 0;
end
else begin
VAR3 <= VAR3 + 1;
VAR6 <= VAR3;
if (VAR3 == (VAR7-1)) ... | gpl-2.0 |
eleqian/WiDSO | CPLD/DSO_LA/src/dsc.v | 1,705 | module MODULE1(VAR2, clk,
VAR9, VAR4, VAR7, VAR27,
VAR22, VAR18, VAR3, VAR6, VAR17, VAR8, VAR11,
VAR12, VAR20, VAR14, VAR5, VAR1);
input VAR2;
input clk;
input VAR9;
input VAR4;
input VAR7;
output VAR27;
output [18:0] VAR22;
inout [15:0] VAR18;
output VAR3;
output VAR6;
output VAR17;
output VAR8;
output VAR11;
inout [1... | mit |
ElegantLin/My-CPU | Final/Final.srcs/sources_1/imports/sources_1/imports/Chapter11/regfile.v | 4,555 | module MODULE1(
input wire clk,
input wire rst,
input wire VAR7,
input wire[VAR2] VAR3,
input wire[VAR19] VAR8,
input wire VAR9,
input wire[VAR2] VAR15,
output reg[VAR19] VAR11,
input wire VAR12,
input wire[VAR2] VAR4,
output reg[VAR19] VAR17
);
reg[VAR19] VAR6[0:VAR18-1];
always @ (posedge clk) begin
if (rst == VAR1) ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdlclkp/sky130_fd_sc_ms__sdlclkp.behavioral.v | 2,508 | module MODULE1 (
VAR4,
VAR15 ,
VAR20,
VAR10
);
output VAR4;
input VAR15 ;
input VAR20;
input VAR10 ;
supply1 VAR11;
supply0 VAR19;
supply1 VAR24 ;
supply0 VAR25 ;
wire VAR18 ;
wire VAR3 ;
wire VAR7 ;
wire VAR23 ;
wire VAR13 ;
wire VAR5 ;
wire VAR9;
reg VAR12 ;
wire VAR2 ;
wire VAR22 ;
wire VAR17 ;
not VAR1 (VAR3 , VAR1... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_mul_frac_dp.v | 15,099 | module MODULE1 (
VAR52,
VAR13,
VAR9,
VAR3,
VAR46,
VAR48,
VAR35,
VAR25,
VAR79,
VAR89,
VAR8,
VAR74,
VAR57,
VAR98,
VAR71,
VAR27,
VAR92,
VAR16,
VAR49,
VAR53,
VAR95,
VAR47,
VAR55,
VAR39,
VAR24,
VAR77,
VAR31,
VAR17,
VAR38,
VAR1,
VAR4,
VAR14,
VAR63,
VAR82,
VAR43,
VAR15,
VAR93,
VAR78,
VAR41,
VAR40,
VAR2,
VAR87,
VAR96,
VAR28,
V... | gpl-2.0 |
zhaishaomin/ring_network-based-multicore- | core/core_PHT.v | 3,118 | module MODULE1( clk,
rst,
VAR9, VAR11, VAR3,
VAR5,
VAR6,
VAR10,
VAR18,
VAR17,
VAR1,
VAR13
);
input clk;
input rst;
input VAR3;
input VAR5;
input VAR6;
input [5:0] VAR9; input [5:0] VAR11; input [3:0] VAR10;
input [1:0] VAR18;
output VAR17;
output [3:0] VAR1;
output [1:0] VAR13;
wire [1:0] VAR13;
wire [3:0] VAR1;
reg VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2.pp.symbol.v | 1,265 | module MODULE1 (
input VAR4 ,
input VAR1,
input VAR3,
input VAR2
);
endmodule | apache-2.0 |
xuwenyihust/MapReduce_NoC | RTL/word_com.v | 2,552 | module MODULE1(clk, rst, VAR1, VAR12);
parameter VAR6 = 8;
parameter VAR8 = 128; parameter VAR5 = 63;
parameter VAR11 = 4'b0000;
parameter VAR3 = 4'b0001;
parameter VAR13 = 4'b0010;
input clk;
input rst;
input VAR1;
input [VAR6-1:0] VAR12;
reg [VAR8-1:0] VAR4 [VAR5-1:0]; reg [5:0] VAR10; reg [7:0] VAR2; reg [6:0] VAR14... | mit |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/wasca_altpll_1.v | 10,635 | module MODULE1
(
VAR5,
VAR3,
VAR2,
VAR6) ;
input VAR5;
input VAR3;
input [0:0] VAR2;
output [0:0] VAR6;
tri0 VAR5;
tri1 VAR3;
reg [0:0] VAR10;
reg [0:0] VAR1;
reg [0:0] VAR9;
wire VAR4;
wire VAR8;
wire VAR7; | gpl-2.0 |
AloriumTechnology/XLR8Pong | extras/rtl/pong16.v | 3,658 | module MODULE1 (VAR38,
VAR27,
VAR30,
VAR34,
VAR25,
VAR11,
VAR26,
VAR3,
VAR20,
VAR18
);
input logic VAR38;
input logic VAR27;
input wire VAR30;
input wire VAR25;
input wire VAR11;
input wire [7:0] VAR34;
input [7:0] VAR26;
output VAR3;
output VAR20;
output VAR18;
wire VAR14;
wire VAR15;
reg VAR3;
reg VAR20;
reg VAR4=0;
... | lgpl-3.0 |
hydai/Verilog-Practice | DigitalDesign/hw1/hw1_101062124/hw1_B/hw1_B.v | 1,458 | module MODULE1 (
input [15:0] VAR4,
input [15:0] VAR3,
input clk,
input VAR6,
output reg [15:0] VAR5,
output reg [15:0] VAR2,
output reg [15:0] VAR1,
output reg [15:0] VAR11
);
wire [15:0] VAR8, VAR10, VAR7, VAR9;
always @(posedge clk or negedge VAR6) begin
if (!VAR6) begin
VAR5 <= 0;
VAR2 <= 0;
VAR1 <= 0;
VAR11 <= 0;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o22ai/sky130_fd_sc_hd__o22ai_2.v | 2,352 | module MODULE2 (
VAR9 ,
VAR8 ,
VAR3 ,
VAR2 ,
VAR6 ,
VAR4,
VAR1,
VAR5 ,
VAR7
);
output VAR9 ;
input VAR8 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
input VAR4;
input VAR1;
input VAR5 ;
input VAR7 ;
VAR10 VAR11 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR7(V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3/sky130_fd_sc_hd__and3_4.v | 2,164 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR2 ,
VAR3 ,
VAR7,
VAR6,
VAR10 ,
VAR9
);
output VAR8 ;
input VAR5 ;
input VAR2 ;
input VAR3 ;
input VAR7;
input VAR6;
input VAR10 ;
input VAR9 ;
VAR1 VAR4 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR10(VAR10),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9234/axi_ad9234_if.v | 4,694 | module MODULE1 (
VAR6,
VAR5,
VAR7,
VAR16,
VAR3,
VAR2,
VAR10,
VAR4,
VAR8);
input VAR6;
input [127:0] VAR5;
output VAR7;
input VAR16;
output [63:0] VAR3;
output [63:0] VAR2;
output VAR10;
output VAR4;
output VAR8;
reg VAR8 = 'd0;
wire [15:0] VAR9;
wire [15:0] VAR13;
wire [15:0] VAR11;
wire [15:0] VAR15;
wire [15:0] VAR1;... | gpl-3.0 |
P3Stor/P3Stor | ftl/Dynamic_Controller/code/MUX1_8.v | 3,292 | module MODULE1( address,
VAR8,din,
VAR5,VAR14,VAR10,VAR15,VAR17,VAR7,VAR13,VAR16,
VAR12 ,VAR9 ,VAR11 ,VAR1 ,VAR3 ,VAR2 ,VAR4 ,VAR6
);
input [2:0] address;
input VAR8;
input [127:0] din;
output reg VAR5;
output reg VAR14;
output reg VAR10;
output reg VAR15;
output reg VAR17;
output reg VAR7;
output reg VAR13;
output reg... | gpl-2.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | source/hardware/low-level-nfc/llnfc-ddr200mt-1.0.0/NPM_Toggle_DI_DDR100.v | 43,134 | module MODULE1
(
parameter VAR71 = 4
)
(
VAR127 ,
VAR122 ,
VAR64 ,
VAR31 ,
VAR28 ,
VAR46 ,
VAR91 ,
VAR121 ,
VAR35 ,
VAR48 ,
VAR50 ,
VAR15 ,
VAR5 ,
VAR21 ,
VAR55 ,
VAR131 ,
VAR67 ,
VAR43 ,
VAR2 ,
VAR110 ,
VAR133 ,
VAR8 ,
VAR54 ,
VAR22 ,
VAR101
);
input VAR127 ;
input VAR122 ;
output VAR64 ;
output VAR31 ;
input VAR28 ;
... | gpl-3.0 |
kyzhai/NUNY | src/hardware/mast_new_bb.v | 5,022 | module MODULE1 (
address,
VAR1,
VAR2);
input [11:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/uart/rtl/uart.v | 1,848 | module MODULE1 #(
parameter VAR2 = 4'h0,
parameter VAR21 = 100000000,
parameter VAR7 = 115200
) (
input VAR9,
input VAR15,
input [13:0] VAR10,
input VAR4,
input [31:0] VAR11,
output reg [31:0] VAR6,
output VAR22,
output VAR16,
input VAR17,
output VAR8
);
reg [15:0] VAR14;
wire [7:0] VAR23;
wire [7:0] VAR20;
wire VAR5;
... | lgpl-3.0 |
Digilent/vivado-library | ip/video_scaler/hdl/verilog/fifo_w32_d2_A.v | 2,988 | module MODULE2 (
clk,
VAR26,
VAR7,
VAR19,
VAR8);
parameter VAR23 = 32'd32;
parameter VAR16 = 32'd1;
parameter VAR6 = 2'd2;
input clk;
input [VAR23-1:0] VAR26;
input VAR7;
input [VAR16-1:0] VAR19;
output [VAR23-1:0] VAR8;
reg[VAR23-1:0] VAR18 [0:VAR6-1];
integer VAR11;
always @ (posedge clk)
begin
if (VAR7)
begin
for (V... | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/reg_cam_cell.v | 2,770 | module MODULE1 (
clk,rst,
VAR6,VAR2,VAR4,VAR7,
VAR5,VAR8
);
parameter VAR3 = 32;
input clk,rst;
input [VAR3-1:0] VAR6, VAR2;
input VAR4,VAR7;
input [VAR3-1:0] VAR5;
output VAR8;
reg VAR8;
reg VAR9;
reg [VAR3 - 1 : 0] VAR11;
reg [VAR3 - 1 : 0] VAR10;
always @(posedge clk) begin
if (rst) begin
VAR9 <= 1'b0;
VAR11 <= {VAR... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v | 1,476 | module MODULE1 #(parameter VAR7(VAR19)
, parameter VAR7(VAR10)
, parameter VAR9=0
, parameter VAR24=VAR23(VAR10)
, parameter VAR5=0
, parameter VAR3=1
)
(input VAR12
, input VAR11
, input [VAR17(VAR19, 1):0] VAR4
, input [VAR24-1:0] VAR8
, input VAR18
, input VAR6
, output logic [VAR17(VAR19, 1):0] VAR16
);
wire VAR20;... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o22ai/sky130_fd_sc_lp__o22ai.functional.pp.v | 2,159 | module MODULE1 (
VAR13 ,
VAR19 ,
VAR12 ,
VAR2 ,
VAR8 ,
VAR18,
VAR3,
VAR14 ,
VAR11
);
output VAR13 ;
input VAR19 ;
input VAR12 ;
input VAR2 ;
input VAR8 ;
input VAR18;
input VAR3;
input VAR14 ;
input VAR11 ;
wire VAR4 ;
wire VAR6 ;
wire VAR16 ;
wire VAR1;
nor VAR10 (VAR4 , VAR2, VAR8 );
nor VAR17 (VAR6 , VAR19, VAR12 );... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a21oi/sky130_fd_sc_hs__a21oi_1.v | 2,134 | module MODULE2 (
VAR1 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR3,
VAR6
);
output VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR3;
input VAR6;
VAR7 VAR8 (
.VAR1(VAR1),
.VAR5(VAR5),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR1 ,
VAR5,
VAR2,
VAR4
);
output VAR1 ;
input VAR5;
input VAR2;
... | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.ip_user_files/bd/design_1/ip/design_1_axis_broadcaster_0_0/hdl/tdata_design_1_axis_broadcaster_0_0.v | 3,332 | module MODULE1 #
(
parameter VAR2 = 8,
parameter VAR4 = 8
)
(
input wire [VAR2-1:0] VAR1,
output wire [VAR4-1:0] VAR3
);
assign VAR3 = {VAR1[7:0],VAR1[7:0]};
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.symbol.v | 1,349 | module MODULE1 (
input VAR4,
input VAR7,
input VAR1,
output VAR2
);
supply1 VAR8;
supply0 VAR6;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_demux_64_4.v | 10,477 | module MODULE1 #
(
parameter VAR43 = 64,
parameter VAR38 = (VAR43/8)
)
(
input wire clk,
input wire rst,
input wire [VAR43-1:0] VAR1,
input wire [VAR38-1:0] VAR44,
input wire VAR59,
output wire VAR47,
input wire VAR46,
input wire VAR2,
output wire [VAR43-1:0] VAR7,
output wire [VAR38-1:0] VAR56,
output wire VAR26,
inpu... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxbp/sky130_fd_sc_ls__sedfxbp_1.v | 2,564 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR12 ,
VAR5 ,
VAR11 ,
VAR2 ,
VAR7 ,
VAR8,
VAR1,
VAR3 ,
VAR10
);
output VAR9 ;
output VAR6 ;
input VAR12 ;
input VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR7 ;
input VAR8;
input VAR1;
input VAR3 ;
input VAR10 ;
VAR4 VAR13 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR12(VAR12),
.VAR5(VAR5),
.VAR11(VAR1... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_transmitFIFODataIn.v | 2,241 | module MODULE1 (
address,
VAR2,
clk,
VAR8,
VAR7,
VAR3,
VAR4,
VAR1
)
;
output [ 8: 0] VAR4;
output [ 31: 0] VAR1;
input [ 1: 0] address;
input VAR2;
input clk;
input VAR8;
input VAR7;
input [ 31: 0] VAR3;
wire VAR9;
reg [ 8: 0] VAR5;
wire [ 8: 0] VAR4;
wire [ 8: 0] VAR6;
wire [ 31: 0] VAR1;
assign VAR9 = 1;
assign VAR6 ... | gpl-3.0 |
takeshineshiro/fpga_linear_128 | LVDS_AD_bb.v | 5,334 | module MODULE1 (
VAR2,
VAR3,
VAR5,
VAR4,
VAR1);
input [7:0] VAR2;
input VAR3;
output VAR5;
output [95:0] VAR4;
output VAR1;
endmodule | mit |
dries007/Basys3 | VGA_text/VGA_text.srcs/sources_1/ip/ClockDivider/ClockDivider_clk_wiz.v | 6,939 | module MODULE1
( input clk,
output VAR43,
output VAR59,
output VAR31
);
VAR67 VAR13
(.VAR64 (VAR73),
.VAR39 (clk));
wire [15:0] VAR7;
wire VAR10;
wire VAR44;
wire VAR41;
wire VAR74;
wire VAR9;
wire VAR57;
wire VAR85;
wire VAR16;
wire VAR83;
wire VAR33;
wire VAR38;
wire VAR76;
wire VAR34;
wire VAR46;
wire VAR15;
wire VA... | mit |
sabertazimi/hust-lab | architecture/design/fpga/src/branch_hazard_detector.v | 1,386 | module MODULE1
(
input [4:0] VAR7,
input [4:0] VAR1,
input VAR6,
input [4:0] VAR2,
input VAR11,
input [4:0] VAR4,
input VAR9,
input VAR8,
input VAR5,
output VAR3,
output VAR10
);
assign VAR3 = VAR8 || VAR5;
assign VAR10 = (VAR9 && VAR6 && VAR2 != 0 && (VAR2 == VAR7 || VAR2 == VAR1))
|| (VAR9 && VAR11 && VAR4 != 0 && (V... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/rxc_engine_classic.v | 37,558 | module MODULE2
parameter VAR39 = 128,
parameter VAR26 = 10
)
(
input VAR187,
input VAR88,
input [VAR39-1:0] VAR35,
input VAR102,
input VAR138,
input [VAR170-1:0] VAR133,
input VAR51,
input [VAR170-1:0] VAR129,
input [VAR28-1:0] VAR147,
output [VAR39-1:0] VAR92,
output VAR152,
output [(VAR39/32)-1:0] VAR156,
output VAR1... | gpl-3.0 |
DreamSourceLab/DSLogic-hdl | src/cons_buf.v | 17,713 | module MODULE1 (
input VAR86,
input VAR40,
input VAR140,
input VAR104,
input VAR85,
input VAR59,
input VAR60,
input VAR95,
input [15:0] VAR102,
input VAR61,
input VAR16,
output VAR33,
input [31:0] VAR118,
output VAR132,
output [15:0] VAR37,
input [23:0] VAR92,
input [23:0] VAR5,
input [7:0] VAR71,
input [7:0] VAR143,
i... | gpl-2.0 |
alexforencich/xfcp | example/VCU118/fpga/rtl/fpga.v | 17,251 | module MODULE1 (
input wire VAR100,
input wire VAR117,
input wire reset,
input wire VAR198,
input wire VAR166,
input wire VAR4,
input wire VAR218,
input wire VAR248,
input wire [3:0] VAR74,
output wire [7:0] VAR29,
inout wire VAR61,
inout wire VAR104,
input wire VAR116,
input wire VAR69,
output wire VAR16,
output wire ... | mit |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_gen_reset.v | 4,863 | module MODULE1(
VAR28,
VAR5,
VAR38,
VAR22,
VAR19,
VAR8,
VAR13,
VAR40,
VAR4,
VAR16,
VAR31,
VAR33,
VAR23,
VAR44,
VAR30,
VAR10,
VAR18,
VAR6,
VAR21,
VAR3,
VAR37,
VAR34,
VAR17,
VAR41,
VAR43,
VAR26,
VAR27,
VAR1,
VAR9,
VAR29,
VAR36,
VAR24,
VAR35,
VAR14
);
input VAR28;
input VAR5;
input VAR22;
input VAR19;
input VAR8;
input VA... | gpl-2.0 |
RP7/R7-OCM | src/rtl/ad9361_1t1r.v | 3,619 | module MODULE1
(
VAR10,
VAR30,
VAR28,
VAR13,
VAR32,
VAR15,
VAR8,
VAR38,
VAR3,
VAR36,
VAR20,
VAR27,
clk,
rst,
VAR40,
VAR2,
VAR16,
VAR12,
VAR31,
VAR14
);
input VAR10; input VAR30; input VAR28; input VAR13; input [5:0]VAR32; input [5:0]VAR15;
output VAR8; output VAR38; output VAR3; output VAR36; output [5:0]VAR20; output ... | apache-2.0 |
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox | general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_0/affine_block_ieee754_fp_adder_subtractor_0_0_stub.v | 1,374 | module MODULE1(VAR1, VAR2, VAR3)
;
input [31:0]VAR1;
input [31:0]VAR2;
output [31:0]VAR3;
endmodule | mit |
chebykinn/university | circuitry/lab3/src/hdl/pipeline.v | 8,873 | module MODULE1 ( input wire clk,
input wire rst,
output VAR81,
output [31:0] VAR15,
input [31:0] VAR43,
input VAR57,
output wire VAR46,
output wire VAR18,
output wire [31:0] VAR9,
output wire [31:0] VAR34,
input wire [31:0] VAR32 );
wire [1:0] VAR65;
wire VAR76;
wire [31:0] VAR74;
wire [31:0] VAR47;
wire [31:0] VAR36;
... | mit |
lvd2/zxevo | unsupported/solegstar/fpga/current/sound/sound.v | 1,485 | module MODULE2(
input wire clk,
input wire [7:0] din,
input wire VAR1,
input wire VAR12,
input wire VAR14,
output wire VAR6
);
reg [6:0] VAR7;
reg [7:0] VAR3;
reg VAR11;
reg VAR13;
reg VAR5;
wire VAR9;
always @(posedge clk)
begin
if( VAR1 && (VAR13!=VAR5) )
VAR11 <= 1'b1;
end
else if( VAR12 )
VAR11 <= 1'b0;
end
always ... | gpl-3.0 |
mgolub2/T3MAPS_Model | t3mapsModel.v | 1,328 | module MODULE1 (
input VAR9,
input VAR3,
input VAR1,
input VAR2,
input VAR4,
output VAR12,
output VAR8
);
reg [63:0] VAR10[17:0]; reg [175:0] VAR7;
reg [31:0] VAR5;
reg [143:0]VAR6;
wire [5:0] VAR11;
assign VAR11 = VAR5[5:0];
assign VAR8 = VAR7[0];
assign VAR12 = VAR10[VAR11][0];
always @ (posedge VAR2, posedge VAR3, p... | gpl-2.0 |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/rinse_mode.v | 6,778 | module MODULE1
(
input VAR7, input VAR19, input VAR4, input [31:0]clk, input [2:0]VAR2,
output reg VAR16,
output reg VAR26, output reg VAR17,output reg VAR11,
output [2:0]VAR3, output reg VAR10, output reg [31:0]VAR29,
output reg [2:0]state
);
reg [2:0]VAR15;
reg VAR30, VAR8, VAR12, VAR27; wire [31:0]VAR24, VAR21, VAR5... | mit |
binderclip/BCOpenMIPS | cpu-code/data_ram.v | 1,394 | module MODULE1(
input wire clk,
input wire VAR8,
input wire VAR13,
input wire[VAR9] addr,
input wire[3:0] sel,
input wire[VAR9] VAR1,
output reg[VAR9] VAR15
);
reg[VAR4] VAR7[0:VAR14 - 1];
reg[VAR4] VAR3[0:VAR14 - 1];
reg[VAR4] VAR11[0:VAR14 - 1];
reg[VAR4] VAR10[0:VAR14 - 1];
always @(posedge clk) begin
if (VAR8 == VA... | mit |
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