repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
mamijaz/RISC-V | src/riscv_instruction_cache/MULTIPLEXER_16_TO_1.v | 3,023 | module MODULE1 #(
parameter VAR4 = 32
) (
input [VAR4 - 1 : 0] VAR15 ,
input [VAR4 - 1 : 0] VAR10 ,
input [VAR4 - 1 : 0] VAR17 ,
input [VAR4 - 1 : 0] VAR2 ,
input [VAR4 - 1 : 0] VAR7 ,
input [VAR4 - 1 : 0] VAR18 ,
input [VAR4 - 1 : 0] VAR16 ,
input [VAR4 - 1 : 0] VAR6 ,
input [VAR4 - 1 : 0] VAR20 ,
input [VAR4 - 1 : 0]... | bsd-2-clause |
Cosmos-OpenSSD/Cosmos-plus-OpenSSD | source/hardware/nvme/nvme_host_ctrl_8lane-1.0.0/pcie_hcmd.v | 15,112 | module MODULE1 # (
parameter VAR161 = 128,
parameter VAR21 = 36
)
(
input VAR82,
input VAR158,
input [VAR21-1:2] VAR190,
input [VAR21-1:2] VAR162,
input [7:0] VAR191,
input [7:0] VAR8,
input [7:0] VAR18,
input [7:0] VAR55,
input [7:0] VAR148,
input [7:0] VAR105,
input [7:0] VAR106,
input [7:0] VAR113,
input [7:0] VAR10... | gpl-3.0 |
n8thenetninja/Cloud-Car | VeriLog/QuartusProjects/ServoController/i2cslave/trunk/rtl/i2cSlaveTop.v | 3,075 | module MODULE1 (
clk,
rst,
VAR1,
VAR7,
VAR3
);
input clk;
input rst;
inout VAR1;
input VAR7;
output [7:0] VAR3;
VAR6 VAR8(
.clk(clk),
.rst(rst),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR4(),
.VAR10(),
.VAR5(),
.VAR2(8'h12),
.VAR11(8'h34),
.VAR12(8'h56),
.VAR9(8'h78)
);
endmodule | gpl-3.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_rhq_buf.v | 3,436 | module MODULE1(
VAR14,
clk, VAR17, VAR6, VAR24, VAR23, VAR4,
VAR7, VAR12, VAR11, VAR22
);
input clk;
input VAR17;
input VAR6;
input [4:0] VAR24;
input VAR23;
input VAR4;
input VAR7;
input [VAR21-1:0] VAR12;
input [VAR21-1:0] VAR11;
input [VAR20-1:0] VAR22;
output [VAR20-1:0] VAR14;
wire [VAR20-1:0] VAR14;
wire VAR5;
VA... | gpl-2.0 |
Jawanga/ece385final | usb_system/synthesis/submodules/usb_system_jtag_uart.v | 17,487 | module MODULE5 (
clk,
VAR15,
VAR20,
VAR22,
VAR25,
VAR50,
VAR48
)
;
output VAR22;
output [ 7: 0] VAR25;
output VAR50;
output [ 5: 0] VAR48;
input clk;
input [ 7: 0] VAR15;
input VAR20;
wire VAR22;
wire [ 7: 0] VAR25;
wire VAR50;
wire [ 5: 0] VAR48;
always @(posedge clk)
begin
if (VAR20)
("%VAR31", VAR15);
end
assign VAR... | apache-2.0 |
sabertazimi/hust-lab | verilog/labs/lab4/src/Datapath_with_mux_adder_register_memory.v | 1,865 | module MODULE1
(
input VAR35,
input reset,
input [(VAR25 - 1):0] VAR11,
input VAR3,
input VAR13,
input VAR4,
output [(VAR25 - 1):0] VAR7,
output [(VAR25 - 1):0] VAR22,
output [(VAR25 - 1):0] VAR10,
output [(VAR25 - 1):0] VAR8,
output [(VAR25 - 1):0] VAR27,
output [(VAR25 - 1):0] VAR1,
output [(VAR25 - 1):0] VAR31,
outp... | mit |
jncronin/jca | cpu/rom.v | 7,173 | module MODULE1 (
address,
VAR27,
VAR50,
VAR56,
VAR44);
input [11:0] address;
input VAR27;
input [7:0] VAR50;
input VAR56;
output [7:0] VAR44;
tri1 VAR27;
wire [7:0] VAR48;
wire [7:0] VAR44 = VAR48[7:0];
VAR25 VAR9 (
.VAR19 (address),
.VAR5 (VAR27),
.VAR53 (VAR50),
.VAR46 (VAR56),
.VAR43 (VAR48),
.VAR36 (1'b0),
.VAR29 (... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/iobdg/iobdg_dbg/rtl/iobdg_dbg_porta.v | 6,264 | module MODULE1 (
VAR15, VAR44, VAR8, VAR2,
VAR34, VAR37,
VAR42, clk, VAR17, VAR28, VAR23, VAR29, VAR5,
VAR24, VAR19, VAR33, VAR14, VAR1,
VAR38, VAR35, VAR21
);
input VAR42;
input clk;
input [39:0] VAR17;
input [39:0] VAR28;
input [39:0] VAR23;
input [39:0] VAR29;
input [39:0] VAR5;
input VAR24;
input VAR19;
input VAR33... | gpl-2.0 |
hly11/CollisionDetectionFPGA | hardware/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.v | 3,872 | module MODULE1
(
input VAR1,
output VAR4
);
VAR2 VAR3
(
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule | gpl-2.0 |
545/Atari7800 | core/ag_6502/trunk/juke-box/clkdiv.v | 1,167 | module MODULE2(input clk, output VAR10);
parameter VAR4 = 16;
wire VAR6;
VAR3 #(
.VAR9(VAR4) ) VAR8 (
.VAR1(VAR10), .VAR7(clk), .VAR12(VAR6),
.VAR5(VAR6),
.VAR11(0)
);
endmodule
module MODULE1(input clk, output reg VAR10 = 0);
parameter VAR4 = 16;
integer VAR2 = 0;
always @(posedge clk) begin
VAR2 <= (VAR2?VAR2:(VAR4/2... | gpl-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/clk_divider.v | 1,898 | module MODULE1
VAR4 = 100 )
(
input wire VAR3, input wire rst, output reg VAR7 );
localparam VAR6 = 1000000 / 2 / (VAR4/100) ;
reg [VAR8(VAR6)-1:0] VAR1;
always @( posedge(VAR3), posedge(rst) )
begin
if(rst)
begin : VAR5
VAR1 <= 0;
VAR7 <= 1'b0;
end
else
begin : VAR9
if (VAR1 == (VAR6 - 1))
begin : VAR10
VAR1 <= 0;
VAR... | mit |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/Fetch_FSL.v | 5,075 | module MODULE1(
input [107:0] VAR30,
input [107:0] VAR20,
input VAR9,
input reset,
input VAR3,
input VAR25,
output reg [31:0] VAR7 = 32'h00000000,
output reg [31:0] VAR6 = 32'h00000000,
output reg [31:0] VAR19 = 32'h00000000,
output reg [1:0] VAR13,
output reg VAR1,
output reg [7:0] VAR2,
output reg VAR33 = 1'b0,
outpu... | apache-2.0 |
phase4ground/DVB-receiver | modem/rfnoc-modem/rfnoc/fpga-src/apsk_modulator_configmod.v | 12,424 | module MODULE1 #
(
parameter integer VAR29 = 4,
parameter integer VAR35 = 40,
parameter integer VAR19 = 16,
parameter integer VAR77 = 16,
parameter integer VAR20 = 4,
parameter integer VAR67 = 32,
parameter integer VAR9 = 32,
parameter integer VAR82 = 32,
parameter integer VAR56 = 32,
parameter integer VAR42 = 32,
para... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkbuf/sky130_fd_sc_ls__clkbuf_16.v | 2,040 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR1,
VAR2,
VAR4 ,
VAR8
);
output VAR3 ;
input VAR7 ;
input VAR1;
input VAR2;
input VAR4 ;
input VAR8 ;
VAR6 VAR5 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR3,
VAR7
);
output VAR3;
input VAR7;
supply1 VAR1;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or2/sky130_fd_sc_hs__or2.blackbox.v | 1,191 | module MODULE1 (
VAR2,
VAR4,
VAR3
);
output VAR2;
input VAR4;
input VAR3;
supply1 VAR1;
supply0 VAR5;
endmodule | apache-2.0 |
briburrell/amica | device/scrypt_mono_pll/scrypt_mono_pll.srcs/sources_1/imports/scrypt_mono_pll/salsaengine.v | 20,437 | module MODULE1 (VAR92, reset, din, dout, VAR72, VAR33, VAR75, VAR54 );
input VAR92;
input reset; input VAR72;
input VAR33; output VAR75;
output reg VAR54 = 1'b0;
parameter VAR36 = 8; input [VAR36-1:0] din;
output [VAR36-1:0] dout;
parameter VAR74 = 11;
parameter VAR5 = 8;
function integer VAR56; input integer VAR98;
be... | gpl-3.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/iodelay_ctrl.v | 7,730 | module MODULE1 #
(
parameter VAR21 = 100, parameter VAR5 = "VAR14", parameter VAR1 = "VAR37", parameter VAR30 = 1 )
(
input VAR24,
input VAR29,
input VAR3,
input VAR35,
output VAR2, output VAR34
);
localparam VAR31 = 15;
wire VAR6;
wire VAR36;
wire VAR28;
reg [VAR31-1:0] VAR38 ;
wire VAR13;
wire VAR19;
assign VAR19 = V... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_read_datapath.v | 25,752 | module MODULE1(
VAR70,
VAR19,
VAR103,
VAR13,
VAR12,
VAR73,
VAR63,
VAR36,
VAR97,
VAR101,
VAR42,
VAR53,
VAR151,
VAR22,
VAR47,
VAR71,
VAR110,
VAR41,
VAR32,
VAR48
);
parameter VAR7 = "";
parameter VAR85 = "";
parameter VAR20 = "";
parameter VAR16 = "";
parameter VAR147 = "";
parameter VAR83 = "";
parameter VAR104 = "";
par... | lgpl-3.0 |
SWORDfpga/ComputerOrganizationDesign | labs/lab07/lab07/Code/CPU/SCtrl_M.v | 3,210 | module MODULE1(input[5:0]VAR5, input[5:0]VAR4, input wire VAR11, input wire VAR3, output reg VAR6,
output reg VAR9,
output reg [1:0] VAR12,
output reg VAR10,
output reg [1:0]VAR14,
output reg VAR8,
output reg VAR7,
output reg [2:0]VAR13,
output reg VAR1
);
always @* begin
VAR6=0;
VAR9=0;
VAR12=2'b00;
VAR8=0;
VAR14=2'b0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp_2.v | 2,130 | module MODULE1 (
VAR8 ,
VAR5 ,
VAR1 ,
VAR2,
VAR9,
VAR7 ,
VAR4
);
output VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR2;
input VAR9;
input VAR7 ;
input VAR4 ;
VAR6 VAR3 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR8 ,
VAR5 ,
VAR1
);
output VAR8... | apache-2.0 |
HighlandersFRC/fpga | lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_processing_system7_1_0/hdl/processing_system7_bfm_v2_0_fmsw_gp.v | 6,424 | module MODULE1(
VAR4,
VAR81,
VAR40,
VAR83,
VAR35,
VAR65,
VAR66,
VAR14,
VAR36,
VAR62,
VAR78,
VAR63,
VAR24,
VAR46,
VAR89,
VAR59,
VAR82,
VAR91,
VAR17,
VAR60,
VAR1,
VAR54,
VAR87,
VAR12,
VAR76,
VAR73,
VAR38,
VAR77,
VAR39,
VAR58,
VAR79,
VAR96,
VAR94,
VAR31,
VAR33,
VAR103,
VAR72,
VAR88,
VAR70,
VAR53,
VAR41,
VAR56,
VAR8,
VAR10... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnsnq/gf180mcu_fd_sc_mcu9t5v0__dffnsnq_1.behavioral.v | 3,781 | module MODULE1( VAR31, VAR3, VAR23, VAR32 );
input VAR31, VAR3, VAR23;
output VAR32;
reg VAR2;
VAR6 VAR26(.VAR31(VAR31),.VAR3(VAR3),.VAR23(VAR23),.VAR32(VAR32),.VAR2(VAR2));
VAR6 VAR15(.VAR31(VAR31),.VAR3(VAR3),.VAR23(VAR23),.VAR32(VAR32),.VAR2(VAR2));
not VAR12(VAR27,VAR3);
and VAR16(VAR11,VAR23,VAR27);
and VAR22(VAR7... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/nor3/sky130_fd_sc_hs__nor3.symbol.v | 1,272 | module MODULE1 (
input VAR4,
input VAR5,
input VAR1,
output VAR2
);
supply1 VAR6;
supply0 VAR3;
endmodule | apache-2.0 |
0a-/linguist | samples/Verilog/ps2_mouse.v | 7,180 | module MODULE1 (
input clk, input reset, inout VAR12, inout VAR22,
input [7:0] VAR11, input VAR8, output VAR21, output VAR14,
output [7:0] VAR24, output VAR16, output VAR7,
output VAR4
);
wire VAR18; wire VAR6;
reg [7:0] VAR9; reg VAR13;
reg VAR2;
reg VAR23;
reg [2:0] VAR15; reg [2:0] VAR19;
localparam VAR17 = 3'h0, VA... | mit |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v | 21,837 | module MODULE2 #
( parameter
VAR3 = 0
)
(
clk,
VAR14,
VAR9,
VAR18
) ;
input clk;
input VAR14;
input [63:0] VAR9;
output [71:0] VAR18;
wire [63:0] VAR12;
wire [34:0] VAR7;
wire [17:0] VAR11;
wire [8:0] VAR10;
wire [3:0] VAR5;
wire [1:0] VAR4;
wire [30:0] VAR15;
wire [6:0] VAR19;
wire [70:0] VAR8;
wire [70:0] VAR1;
reg [... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/ram_128_32x32_dp/ram_128_32x32_dp_bb.v | 7,352 | module MODULE1 (
VAR2,
VAR1,
VAR3,
VAR6,
VAR4,
VAR7,
VAR5);
input [127:0] VAR2;
input [3:0] VAR1;
input VAR3;
input [1:0] VAR6;
input VAR4;
input VAR7;
output [31:0] VAR5;
endmodule | gpl-3.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/impl/verilog/image_filter_FAST_t_opr_k_buf_val_0_V.v | 1,643 | module MODULE1 (VAR12, VAR14, VAR6, VAR4, VAR15, VAR9, VAR8, clk);
parameter VAR3 = 8;
parameter VAR11 = 11;
parameter VAR2 = 1920;
input[VAR11-1:0] VAR12;
input VAR14;
output reg[VAR3-1:0] VAR6;
input[VAR11-1:0] VAR4;
input VAR15;
input[VAR3-1:0] VAR9;
input VAR8;
input clk;
reg [VAR3-1:0] VAR7[VAR2-1:0];
always @(pos... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and2b/sky130_fd_sc_hs__and2b.pp.blackbox.v | 1,234 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR3 ,
VAR5,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR3 ;
input VAR5;
input VAR1;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_ddr_common/rtl/bw_io_ddr_4sig_clk.v | 4,648 | module MODULE1(VAR5 ,VAR32 ,VAR21 ,
VAR9 ,VAR28 ,VAR1 ,VAR7 ,VAR15 ,VAR16 ,VAR34 ,VAR10 ,VAR22
,VAR13 ,VAR14 ,VAR25 ,VAR2 ,VAR27 ,VAR36 ,VAR11 );
input [7:0] VAR28 ;
input [3:0] VAR27 ;
input [8:1] VAR36 ;
input [8:1] VAR11 ;
inout [3:0] VAR1 ;
output VAR9 ;
output VAR10 ;
input VAR5 ;
input VAR32 ;
input VAR21 ;
input... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_180_250/bsg_misc/bsg_tielo.v | 1,629 | if (VAR10 && (VAR6==VAR15)) \
begin: VAR14 \
VAR13 VAR11 (.VAR9); \
end
module MODULE1 #(parameter VAR8(VAR6)
, parameter VAR10=1
)
(output [VAR6-1:0] VAR9
);
begin :VAR4
assign VAR9 = { VAR6 {1'b0} };
end
VAR3 assert(VAR10==0) else ("## %VAR5 VAR2 VAR7 VAR12 VAR16 VAR1 VAR14");
end
endmodule | bsd-3-clause |
lkesteloot/alice | alice4/fpga/Alice4-DE0-Nano-SoC/Font_ROM.v | 95,880 | module MODULE1(
input wire clk,
input wire [10:0] addr,
output reg [7:0] VAR1);
reg [10:0] VAR2;
always @(posedge clk) begin
VAR2 <= addr;
end
always @*
case (VAR2)
11'h000: VAR1 = 8'b00000000; 11'h001: VAR1 = 8'b00000000; 11'h002: VAR1 = 8'b00000000; 11'h003: VAR1 = 8'b00000000; 11'h004: VAR1 = 8'b00000000; 11'h005: V... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_c0.v | 19,693 | module MODULE1 (
input wire VAR96, input wire VAR8, input wire VAR111, output wire VAR37, output wire VAR50, output wire VAR23, output wire [27:0] VAR70, output wire [3:0] VAR134, output wire [1:0] VAR48, output wire [1:0] VAR102, output wire [1:0] VAR43, output wire [1:0] VAR143, output wire [1:0] VAR145, output wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dlrbn/sky130_fd_sc_ms__dlrbn.functional.pp.v | 2,214 | module MODULE1 (
VAR4 ,
VAR16 ,
VAR8,
VAR9 ,
VAR5 ,
VAR13 ,
VAR12 ,
VAR10 ,
VAR18
);
output VAR4 ;
output VAR16 ;
input VAR8;
input VAR9 ;
input VAR5 ;
input VAR13 ;
input VAR12 ;
input VAR10 ;
input VAR18 ;
wire VAR19 ;
wire VAR11;
wire VAR15 ;
not VAR3 (VAR19 , VAR8 );
not VAR14 (VAR11, VAR5 );
VAR2 VAR7 VAR1 (VAR15 ... | apache-2.0 |
olgirard/openmsp430 | fpga/actel_m1a3pl_dev_kit/rtl/verilog/openmsp430/omsp_mem_backbone.v | 18,200 | module MODULE1 (
VAR8, VAR89, VAR71, VAR25, VAR64, VAR59, VAR47, VAR79, VAR16, VAR84, VAR41, VAR45, VAR92, VAR83, VAR37, VAR40, VAR38, VAR4, VAR13, VAR60,
VAR97, VAR15, VAR36, VAR52, VAR98, VAR75, VAR73, VAR44, VAR27, VAR74, VAR31, VAR3, VAR10, VAR29, VAR99, VAR96, VAR22, VAR87, VAR57, VAR32, VAR23, VAR55, VAR62 );
out... | bsd-3-clause |
theapi/nand2tetris_fpga | hack/rtl/verilog/register_display.v | 2,868 | module MODULE1(
input clk, input [15:0] VAR3, input [10:0] VAR6, input [10:0] VAR1, input [2:0] VAR2, output [2:0] VAR8, output VAR9 );
parameter VAR5 = 10; parameter VAR7 = 380;
reg [2:0] out = 0;
assign VAR8 = out;
reg VAR4 = 0;
assign VAR9 = VAR4;
always @ (posedge clk) begin
if (VAR1 >= VAR7 && VAR1 < VAR7 + 11'd6
... | mit |
sabertazimi/hust-lab | digitalLogic/design/washmach_design/src/time_display.v | 2,090 | module MODULE1
(
input VAR16,
input [(VAR6-1):0] VAR12,
input [(VAR6-1):0] VAR1,
input [(VAR6-1):0] VAR7,
output reg [7:0] VAR13,
output reg [7:0] VAR11
);
reg [2:0] VAR17; wire [15:0] VAR9, VAR15, VAR5;
VAR8 VAR2 (
.VAR14(VAR12),
.VAR3(VAR9)
);
VAR8 VAR4 (
.VAR14(VAR1),
.VAR3(VAR15)
);
VAR8 VAR10 (
.VAR14(VAR7),
.VAR3... | mit |
mfkiwl/parallella-platform | hdl/ewrapper_io_tx_slow.v | 8,735 | module MODULE1 (
VAR39, VAR45, VAR62,
VAR38,
VAR20, VAR71, VAR4, VAR14, VAR58,
VAR76
);
input VAR20; input VAR71; input VAR4; input VAR14;
input VAR58;
input [71:0] VAR76;
output [8:0] VAR39;
output [8:0] VAR45;
output VAR62;
output VAR38;
reg [1:0] VAR36;
reg VAR59;
reg VAR46;
reg [8:0] VAR69;
reg [8:0] VAR22;
reg [71... | gpl-3.0 |
lerwys/bpm-sw-old-backup | hdl/ip_cores/pcie/7a200ffg1156/ddr_core/user_design/rtl/clocking/mig_7series_v1_9_iodelay_ctrl.v | 9,718 | module MODULE1 #
(
parameter VAR35 = 100,
parameter VAR36 = "VAR20",
parameter VAR10 = "VAR19",
parameter VAR25 = "VAR19",
parameter VAR11 = "VAR12",
parameter VAR15 = 1,
parameter VAR9 = "VAR1"
)
(
input VAR29,
input VAR34,
input VAR5,
input VAR41,
output VAR23,
output VAR37,
output VAR43
);
localparam VAR49 = 15;
wir... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfrtn/sky130_fd_sc_lp__sdfrtn.blackbox.v | 1,440 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR1 ,
VAR5 ,
VAR6 ,
VAR2
);
output VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR6 ;
input VAR2;
supply1 VAR8;
supply0 VAR10;
supply1 VAR3 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b_4.v | 2,147 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR6 ,
VAR2,
VAR9,
VAR1 ,
VAR8
);
output VAR4 ;
input VAR5 ;
input VAR6 ;
input VAR2;
input VAR9;
input VAR1 ;
input VAR8 ;
VAR7 VAR3 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE2 (
VAR4 ,
VAR5,
VAR6
);
output VAR4 ... | apache-2.0 |
hydai/Verilog-Practice | HardwareLab/Lab8/LED7SEG.v | 1,178 | module MODULE1(VAR3, VAR9, VAR7, VAR8, VAR2, VAR4, clk);
input clk;
input [3:0] VAR2, VAR4, VAR7, VAR8;
output[3:0] VAR3;
output[7:0] VAR9;
reg[1:0] VAR6;
wire[1:0] VAR1;
wire[3:0] VAR5;
always@(posedge clk)
VAR6 <= VAR1;
assign VAR1 = VAR6 + 2'd1;
assign VAR5 = (VAR6==2'd0) ? VAR4 :
(VAR6==2'd1) ? VAR2 :
(VAR6==2'd2) ... | mit |
diegovalverde/papiGB | rtl/collaterals.v | 11,140 | module MODULE15 # ( parameter VAR3=VAR4 )
(
input wire VAR51,
input wire VAR5,
input wire VAR9,
input wire [VAR3-1:0] VAR14,
output reg [VAR3-1:0] VAR43
);
always @ (posedge VAR51)
begin
if ( VAR5 )
VAR43 <= {VAR3{1'b0}};
end
else
begin
if (VAR9)
VAR43 <= VAR14;
end
end
endmodule
module MODULE3 # (parameter VAR3=8)
(
i... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fah/sky130_fd_sc_ls__fah.functional.v | 1,648 | module MODULE1 (
VAR2,
VAR13 ,
VAR4 ,
VAR8 ,
VAR17
);
output VAR2;
output VAR13 ;
input VAR4 ;
input VAR8 ;
input VAR17 ;
wire VAR12;
wire VAR6 ;
wire VAR9 ;
wire VAR11 ;
wire VAR5;
xor VAR3 (VAR12, VAR4, VAR8, VAR17 );
buf VAR14 (VAR13 , VAR12 );
and VAR16 (VAR6 , VAR4, VAR8 );
and VAR15 (VAR9 , VAR4, VAR17 );
and VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21bo/sky130_fd_sc_ls__a21bo.blackbox.v | 1,383 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR7 ,
VAR5
);
output VAR6 ;
input VAR2 ;
input VAR7 ;
input VAR5;
supply1 VAR3;
supply0 VAR1;
supply1 VAR8 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/RAMB16_S4_altera_new_bb.v | 6,112 | module MODULE1 (
address,
VAR1,
VAR2,
VAR3,
VAR4,
VAR5);
input [7:0] address;
input VAR1;
input VAR2;
input [11:0] VAR3;
input VAR4;
output [11:0] VAR5;
tri1 VAR1;
tri1 VAR2;
endmodule | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_bram_7vx_req.v | 5,377 | module MODULE1 #(
parameter VAR10 = "VAR24", parameter VAR6 = "VAR22", parameter VAR30 = "500 VAR15", parameter VAR1 = "16 VAR29"
) (
input VAR28, input VAR2,
input [8:0] VAR9, input [8:0] VAR19, input [127:0] VAR7, input [15:0] VAR4, input VAR3, input VAR18, input VAR11, input VAR27,
input [8:0] VAR8, input [8:0] VAR1... | gpl-3.0 |
hwstar/bdcmotor | system.v | 11,196 | module MODULE1(
input clk,
input in,
output out);
reg VAR28;
reg [3:0] VAR72;
VAR134 VAR72 = 4'b0000;
assign out = VAR28;
always @ begin
VAR2 = 0;
if((VAR72[3] == 1) && (VAR72[4] == 0))
VAR2 = 1;
end
always @(posedge clk) begin
VAR72[4] <= VAR72[3];
VAR72[3] <= VAR72[2];
VAR72[2] <= VAR72[1];
VAR72[1] <= VAR72[0];
VAR7... | gpl-2.0 |
siamumar/TinyGarbled | circuit_synthesis/aes/KeyExpansion.v | 1,391 | module MODULE1
(
VAR16,
VAR8
);
localparam VAR12 = 10;
input [127:0] VAR16;
output [128*(VAR12+1)-1:0] VAR8;
wire [31:0] VAR4[4*(VAR12+1)-1:0];
wire [31:0] VAR3[VAR12-1:0];
wire [7:0] VAR1[VAR12-1:0];
wire [31:0] VAR21[VAR12-1:0];
wire [31:0] VAR17[VAR12-1:0];
wire [95:0] VAR18[VAR12-1:0];
assign VAR1[0] = 8'h01;
assig... | gpl-3.0 |
ChrisPVille/RL02 | FPGA/SPI.v | 1,819 | module MODULE1(
input clk,
input rst,
input VAR12,
input VAR22,
output VAR6,
input VAR7,
output VAR15,
input [15:0] din,
output [15:0] dout
);
reg VAR10, VAR5;
reg VAR23, VAR3;
reg VAR2, VAR14;
reg VAR8, VAR16;
reg [15:0] VAR1, VAR17;
reg VAR9, VAR11;
reg [3:0] VAR4, VAR13;
reg [15:0] VAR18, VAR20;
reg VAR21, VAR19;
as... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o.blackbox.v | 1,382 | module MODULE1 (
VAR4 ,
VAR1,
VAR5,
VAR2,
VAR3,
VAR6
);
output VAR4 ;
input VAR1;
input VAR5;
input VAR2;
input VAR3;
input VAR6;
supply1 VAR8;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
peteg944/music-fpga | Experimental/Zedboard UART/SPI.v | 3,407 | module MODULE1 #(parameter VAR22 = 4)( input clk,
input rst,
input VAR2,
output VAR25,
output VAR27,
input VAR19, input[7:0] VAR13,
output[7:0] VAR9,
output VAR17, output VAR7 );
localparam VAR23 = 2;
localparam VAR11 = 2'd0,
VAR15 = 2'd1,
VAR18 = 2'd2;
reg [VAR23-1:0] VAR8, VAR26;
reg [7:0] VAR10, VAR21;
reg [VAR22-1:... | mit |
Tsung-Wei/OpenTimer | benchmark/s400/s400.v | 15,771 | module MODULE1 (
VAR275,
VAR470,
VAR304,
VAR168,
VAR242,
VAR251,
VAR56,
VAR254,
VAR208,
VAR10,
VAR237);
input VAR275;
input VAR470;
input VAR304;
input VAR168;
input VAR242;
output VAR251;
output VAR56;
output VAR254;
output VAR208;
output VAR10;
output VAR237;
wire VAR44;
wire VAR76;
wire VAR246;
wire VAR223;
wire VAR... | gpl-3.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_jaxa/jaxa/synthesis/submodules/jaxa_receiveActivity.v | 1,886 | module MODULE1 (
address,
clk,
VAR4,
VAR6,
VAR3
)
;
output [ 31: 0] VAR3;
input [ 1: 0] address;
input clk;
input VAR4;
input VAR6;
wire VAR1;
wire VAR2;
wire VAR5;
reg [ 31: 0] VAR3;
assign VAR1 = 1;
assign VAR5 = {1 {(address == 0)}} & VAR2;
always @(posedge clk or negedge VAR6)
begin
if (VAR6 == 0)
VAR3 <= 0;
end
el... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/micron/ddr_sdram/mobile_ddr.v | 100,918 | module MODULE1 (VAR53, VAR119, VAR80, VAR109, VAR140, VAR79, VAR63, VAR181, VAR163, VAR92, VAR178, VAR145);
parameter VAR160 = 1.0; parameter VAR74 = 2.0; parameter VAR43 = 97.5; parameter VAR73 = 1.0; parameter VAR115 = 2.0; parameter VAR97 = 15.0;
parameter VAR175 = 13; parameter VAR116 = 13; parameter VAR7 = 16; par... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221a/sky130_fd_sc_lp__o221a_4.v | 2,444 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR11 ,
VAR8 ,
VAR10 ,
VAR12 ,
VAR2,
VAR7,
VAR3 ,
VAR5
);
output VAR4 ;
input VAR1 ;
input VAR11 ;
input VAR8 ;
input VAR10 ;
input VAR12 ;
input VAR2;
input VAR7;
input VAR3 ;
input VAR5 ;
VAR6 VAR9 (
.VAR4(VAR4),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR12(VAR12),
.VA... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | rtl/RTL_VB/spw_ulight_con_top_x.v | 4,167 | module MODULE1(
input VAR8,
input VAR14,
input VAR36,
input VAR27,
input VAR24,
input VAR16,
input VAR51,
input VAR49,
input VAR1,
input [8:0] VAR6,
input VAR31,
input [7:0] VAR42,
input VAR30,
output [8:0] VAR17,
output VAR3,
output [7:0] timeout,
output VAR25,
output VAR28,
output VAR39,
output VAR48,
output VAR46,
o... | gpl-3.0 |
slongfield/StereoCensus | verilog/lib/tapped_fifo.v | 1,803 | module MODULE1#(
parameter VAR5=1,
parameter VAR2=1
) (
input wire clk,
input wire rst,
input wire [VAR5-1:0] VAR9,
output wire [VAR5*VAR2-1:0] VAR4,
output wire [VAR5-1:0] VAR10
);
reg [VAR5-1:0] VAR11[VAR2];
assign VAR10 = VAR11[VAR2-1];
VAR7#(VAR5) VAR6(clk, rst, VAR9, VAR11[0]);
assign VAR4[(VAR5*VAR2-1):(VAR5*(VAR... | gpl-3.0 |
dwaipayanBiswas/ECG-feature-extraction-using-DWT | qrs_refinement1.v | 1,557 | module MODULE1(VAR2,VAR4,VAR1,VAR5,VAR6,VAR11,VAR15,
VAR13,VAR8,clk,VAR14,VAR12,VAR7,
VAR3);
output [15:0] VAR2,VAR4,VAR1
,VAR5;
reg signed [15:0] VAR2,VAR4,VAR1,
VAR5;
input [15:0] VAR6,VAR11;
input VAR12,VAR7,VAR15,VAR3;
input [3:0] VAR13;
input [8:0] VAR8;
input clk, VAR14;
wire clk, VAR14;
always @(posedge clk or n... | gpl-3.0 |
darrylring/SDRdrum | fpga/rtl/ad7980.v | 4,132 | module MODULE1
(
input wire clk,
input wire VAR20,
output wire [15:0] VAR12,
output wire valid,
input wire ready,
input wire VAR14,
output wire VAR5,
output wire VAR15
);
localparam [1:0]
VAR9 = 3'd0,
VAR3 = 3'd1,
VAR19 = 3'd2,
VAR17 = 3'd3;
reg [1:0] VAR18, VAR6;
reg [6:0] VAR4, VAR10;
reg [15:0] VAR1, VAR8;
reg VAR16... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o2111a/sky130_fd_sc_hs__o2111a.pp.blackbox.v | 1,374 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR6 ,
VAR7 ,
VAR4 ,
VAR1 ,
VAR2,
VAR8
);
output VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR7 ;
input VAR4 ;
input VAR1 ;
input VAR2;
input VAR8;
endmodule | apache-2.0 |
danthemango/IC7400 | sn7402/behaviour.v | 1,234 | module MODULE1 (VAR1, VAR4, VAR5, VAR14, VAR12, VAR7, VAR10, VAR3, VAR9, VAR13, VAR2, VAR15, VAR8, VAR6);
output reg VAR1, VAR14, VAR13, VAR8;
input VAR4, VAR5, VAR12, VAR7, VAR3, VAR9, VAR2, VAR15, VAR10, VAR6;
always @(VAR4, VAR5, VAR10, VAR6) begin
if ((VAR6 == 1'VAR11 1) && (VAR10 == 1'VAR11 0)) begin
VAR1 = ~(VAR4... | mit |
Fairyland0902/BlockyRoads | src/BlockyRoads/Detector.v | 8,175 | module MODULE1(
input wire [9:0] VAR12, VAR17,
input wire [9:0] VAR22, VAR4, VAR21, VAR25, VAR10,
input wire [9:0] VAR33, VAR7, VAR6, VAR14, VAR5,
output wire VAR31, VAR13, VAR2, VAR20, VAR35
);
parameter VAR23 = 60;
parameter VAR24 = 100;
parameter VAR32 = 15;
parameter VAR8 = 5;
parameter VAR18 = 10;
parameter VAR19 ... | mit |
osrf/wandrr | firmware/motor_controller/fpga/float32_int16.v | 33,407 | module MODULE1
(
VAR3,
VAR2,
VAR18,
VAR12,
VAR8,
VAR10) ;
input VAR3;
input VAR2;
input VAR18;
input [37:0] VAR12;
input [5:0] VAR8;
output [37:0] VAR10;
tri0 VAR3;
tri1 VAR2;
tri0 VAR18;
reg [1:0] VAR16;
reg [37:0] VAR5;
reg [37:0] VAR1;
reg VAR15;
reg VAR6;
reg VAR17;
wire [6:0] VAR9;
wire VAR4;
wire [31:0] VAR7;
wir... | apache-2.0 |
RGD2/swapforth | j1a/verilog/j4.v | 7,676 | module MODULE1(
input wire clk,
input wire VAR4,
output wire VAR21,
output wire VAR35,
output wire [15:0] VAR8,
output wire VAR48,
output wire [VAR12-1:0] dout,
input wire [VAR12-1:0] VAR27,
output wire [12:0] VAR39,
input wire [15:0] VAR46,
output wire [1:0] VAR51,
output wire [15:0] VAR33,
input wire [3:0] VAR34);
re... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi.pp.blackbox.v | 1,401 | module MODULE1 (
VAR8 ,
VAR2 ,
VAR5 ,
VAR4,
VAR7,
VAR1,
VAR3 ,
VAR6
);
output VAR8 ;
input VAR2 ;
input VAR5 ;
input VAR4;
input VAR7;
input VAR1;
input VAR3 ;
input VAR6 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a2bb2o/sky130_fd_sc_hdll__a2bb2o.behavioral.pp.v | 2,253 | module MODULE1 (
VAR11 ,
VAR7,
VAR10,
VAR4 ,
VAR9 ,
VAR2,
VAR16,
VAR13 ,
VAR18
);
output VAR11 ;
input VAR7;
input VAR10;
input VAR4 ;
input VAR9 ;
input VAR2;
input VAR16;
input VAR13 ;
input VAR18 ;
wire VAR12 ;
wire VAR8 ;
wire VAR19 ;
wire VAR5;
and VAR15 (VAR12 , VAR4, VAR9 );
nor VAR1 (VAR8 , VAR7, VAR10 );
or VA... | apache-2.0 |
cr88192/bgbtech_bjx1core | smalltst/compdec/ModFbTxt.v | 6,275 | module MODULE1(VAR6, reset,
VAR21, VAR25, VAR26, VAR3, VAR32,
VAR28, VAR11,
VAR15, VAR33);
input VAR6;
input reset;
input[9:0] VAR21;
input[9:0] VAR25;
output[7:0] VAR26;
output[7:0] VAR3;
output[7:0] VAR32;
output[13:0] VAR28;
input[31:0] VAR11;
output[15:0] VAR15;
input[63:0] VAR33;
reg[9:0] VAR9;
reg[9:0] VAR12;
reg... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/buf/sky130_fd_sc_lp__buf_8.v | 1,993 | module MODULE1 (
VAR6 ,
VAR4 ,
VAR2,
VAR1,
VAR3 ,
VAR8
);
output VAR6 ;
input VAR4 ;
input VAR2;
input VAR1;
input VAR3 ;
input VAR8 ;
VAR5 VAR7 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR6,
VAR4
);
output VAR6;
input VAR4;
supply1 VAR2;
supply0 VAR1;... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/controllerPeripheralHdlAdi.v | 19,100 | module MODULE1
(
VAR130,
reset,
VAR22,
VAR51,
VAR101,
VAR84,
VAR36,
VAR131,
VAR28,
VAR97,
VAR18,
VAR40,
VAR74,
VAR109,
VAR10,
VAR122,
VAR23,
VAR73,
VAR6,
VAR1,
VAR90,
VAR108,
VAR34,
VAR93,
VAR83,
VAR98,
VAR107,
VAR16,
VAR24,
VAR5,
VAR105,
VAR32
);
input VAR130;
input reset;
input VAR22;
input signed [17:0] VAR51; input... | gpl-3.0 |
asicguy/gplgpu | hdl/vga/hcrt.v | 19,041 | module MODULE1
(
input VAR38,
input VAR58,
input VAR102,
input VAR11, input VAR85, input VAR3,
input VAR61, input VAR42, input VAR77, input [15:0] VAR67, input [5:0] VAR71, input [7:0] VAR99, input VAR98, input VAR86, input VAR60, input VAR17,
input VAR31, input VAR48, input VAR24,
input VAR30, input VAR43, input VAR84... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o22ai/sky130_fd_sc_hvl__o22ai.symbol.v | 1,375 | module MODULE1 (
input VAR6,
input VAR8,
input VAR1,
input VAR3,
output VAR2
);
supply1 VAR5;
supply0 VAR9;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor2/gf180mcu_fd_sc_mcu7t5v0__nor2_1.behavioral.pp.v | 1,254 | module MODULE1( VAR2, VAR4, VAR7, VAR1, VAR8 );
input VAR7, VAR2;
inout VAR1, VAR8;
output VAR4;
VAR6 VAR5(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8));
VAR6 VAR3(.VAR2(VAR2),.VAR4(VAR4),.VAR7(VAR7),.VAR1(VAR1),.VAR8(VAR8)); | apache-2.0 |
8l/soc | backends/small1/hw/rtl/stack.v | 1,641 | module MODULE1 (input clk,
input [31:0] VAR4,
output [31:0] VAR6,
input [31:0] VAR1,
input VAR8,
input [31:0] VAR2,
output [31:0] VAR3
);
parameter VAR5 = VAR5;
reg [31:0] VAR7 [0:VAR5-1];
assign VAR6 = VAR8?VAR1:VAR7[VAR4];
assign VAR3 = VAR7[VAR2];
always @(posedge clk)
begin
if (VAR8) begin
VAR7[VAR4] = VAR1;
end
en... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b.behavioral.pp.v | 1,951 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR9 ,
VAR14 ,
VAR16,
VAR3,
VAR12 ,
VAR15
);
output VAR4 ;
input VAR1 ;
input VAR9 ;
input VAR14 ;
input VAR16;
input VAR3;
input VAR12 ;
input VAR15 ;
wire VAR13 ;
wire VAR8 ;
wire VAR6;
not VAR11 (VAR13 , VAR14 );
or VAR2 (VAR8 , VAR9, VAR1, VAR13 );
VAR7 VAR5 (VAR6, VAR8, VAR16, VAR3);... | apache-2.0 |
anderson1008/NOCulator | hring/hw/buffered/src/c_spreader.v | 2,657 | module MODULE1
(VAR5, VAR6);
parameter VAR4 = 32;
function integer VAR3(input [0:VAR4-1] VAR2);
integer VAR1;
begin
VAR3 = 0;
for(VAR1 = 0; VAR1 < VAR4; VAR1 = VAR1 + 1)
VAR3 = VAR3 + VAR2[VAR1];
end
endfunction
parameter [0:VAR4-1] VAR7 = {VAR4{1'b1}};
localparam VAR10 = VAR3(VAR7);
input [0:VAR10-1] VAR5;
output [0:V... | mit |
lokisz/openzcore | pippo-riscv/rtl/verilog/uic.v | 13,964 | module MODULE1(
clk,
rst,
VAR30,
VAR28,
VAR16,
VAR20,
VAR31,
VAR26,
VAR10,
VAR39,
VAR40,
VAR6,
VAR7,
VAR29,
VAR13,
VAR19,
VAR4,
VAR5,
VAR38,
VAR27,
VAR34,
VAR2
);
parameter VAR11 = 512 ;
input clk;
input rst;
input VAR30;
input VAR28;
input VAR16;
input VAR20;
input VAR31;
input VAR26;
input VAR10;
input[31:0] VAR39;
i... | gpl-2.0 |
yard2010/Arducar | Car/Modules/Video-and-Image-Processing-Design-Using-FPGAs-master/de1_ov7670/SRC/YCbCr2RGB.v | 3,343 | module MODULE1
(
VAR20,
VAR5,
VAR17,
VAR2,
VAR3,
VAR21,
VAR11,
VAR8,
VAR18,
VAR6
);
input [7:0] VAR20,VAR5,VAR17;
input VAR8,VAR18,VAR6;
output [9:0] VAR2,VAR3,VAR21;
output reg VAR11;
reg [9:0] VAR1,VAR7,VAR14;
reg [3:0] VAR23;
reg [19:0] VAR4,VAR10,VAR22;
wire [26:0] VAR9,VAR15,VAR12;
assign VAR2 = VAR1;
assign VAR3=... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sdfxbp/sky130_fd_sc_lp__sdfxbp.functional.pp.v | 2,082 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR11 ,
VAR17 ,
VAR9 ,
VAR10 ,
VAR19,
VAR18,
VAR7 ,
VAR6
);
output VAR5 ;
output VAR2 ;
input VAR11 ;
input VAR17 ;
input VAR9 ;
input VAR10 ;
input VAR19;
input VAR18;
input VAR7 ;
input VAR6 ;
wire VAR4 ;
wire VAR1;
VAR8 VAR14 (VAR1, VAR17, VAR9, VAR10 );
VAR3 VAR15 VAR13 (VAR4 , VAR1, ... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffq/gf180mcu_fd_sc_mcu7t5v0__dffq_1.behavioral.pp.v | 2,179 | module MODULE1( VAR13, VAR1, VAR12, VAR4, VAR3 );
input VAR13, VAR1;
inout VAR4, VAR3;
output VAR12;
reg VAR7;
VAR5 VAR6(.VAR13(VAR13),.VAR1(VAR1),.VAR12(VAR12),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7));
VAR5 VAR9(.VAR13(VAR13),.VAR1(VAR1),.VAR12(VAR12),.VAR4(VAR4),.VAR3(VAR3),.VAR7(VAR7));
not VAR10(VAR2,VAR1);
buf VAR8(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/mux2i/sky130_fd_sc_hdll__mux2i_1.v | 2,230 | module MODULE1 (
VAR2 ,
VAR3 ,
VAR5 ,
VAR10 ,
VAR4,
VAR1,
VAR7 ,
VAR9
);
output VAR2 ;
input VAR3 ;
input VAR5 ;
input VAR10 ;
input VAR4;
input VAR1;
input VAR7 ;
input VAR9 ;
VAR6 VAR8 (
.VAR2(VAR2),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_2048x32_bw.v | 15,337 | module MODULE1(
VAR8, VAR70, VAR40,
clk, rst, VAR6, VAR57, VAR4, addr, VAR85, VAR39
);
input VAR8;
input [VAR74 - 1:0] VAR40; output VAR70;
input clk; input rst; input VAR6; input [3:0] VAR57; input VAR4; input [10:0] addr; input [31:0] VAR85; output [31:0] VAR39;
assign VAR70 = VAR8;
VAR1 VAR30(
VAR58 VAR30(
VAR1 VAR3... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v6_mig39_2/mig_39_2/example_design/rtl/phy/phy_dq_iob.v | 23,027 | module MODULE1 #
(
parameter VAR190 = 100, parameter VAR25 = 5, parameter VAR162 = "VAR106", parameter VAR69 = "VAR22", parameter VAR32 = 300.0, parameter VAR157 = "VAR167", parameter VAR139 = "VAR22", parameter VAR151 = "VAR169" )
(
input VAR103,
input clk,
input rst,
input VAR83,
input VAR187,
input VAR86,
input [4:0... | lgpl-3.0 |
alexforencich/verilog-ethernet | example/VCU118/fpga_1g/rtl/fpga.v | 16,625 | module MODULE1 (
input wire VAR208,
input wire VAR96,
input wire reset,
input wire VAR229,
input wire VAR146,
input wire VAR15,
input wire VAR137,
input wire VAR163,
input wire [3:0] VAR67,
output wire [7:0] VAR243,
input wire VAR154,
input wire VAR144,
output wire VAR72,
output wire VAR142,
input wire VAR167,
input wi... | mit |
SeanZarzycki/openSPARC-FPU | project/src/fpu_mul_ctl.v | 52,492 | module MODULE1 (
VAR220,
VAR324,
VAR248,
VAR55,
VAR46,
VAR260,
VAR214,
VAR316,
VAR61,
VAR247,
VAR252,
VAR14,
VAR282,
VAR293,
VAR230,
VAR337,
VAR30,
VAR199,
VAR88,
VAR37,
VAR299,
VAR343,
VAR213,
VAR126,
VAR87,
VAR265,
VAR162,
VAR60,
VAR141,
VAR160,
VAR53,
VAR10,
VAR121,
VAR340,
VAR138,
VAR267,
VAR132,
VAR145,
VAR142,
VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp_1.v | 2,599 | module MODULE1 (
VAR12 ,
VAR3 ,
VAR9 ,
VAR1 ,
VAR7 ,
VAR11,
VAR6 ,
VAR10 ,
VAR4 ,
VAR5
);
output VAR12 ;
input VAR3 ;
input VAR9 ;
input VAR1 ;
input VAR7 ;
input VAR11;
input VAR6 ;
input VAR10 ;
input VAR4 ;
input VAR5 ;
VAR2 VAR8 (
.VAR12(VAR12),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR11(VAR11),
.VA... | apache-2.0 |
alonso193/proyecto1 | modules/DMA.v | 6,471 | module MODULE1(input reset,
input clk,
input VAR7, input VAR20, input VAR22, input VAR21, input VAR11, input VAR13, input VAR6, input VAR19, input [63:0] VAR24, input [15:0] VAR4, input [5:0] VAR12, input VAR5, input VAR10, input VAR27, input valid, input VAR25, output VAR15,
output [63:0] VAR9, output VAR26, output VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fahcon/sky130_fd_sc_lp__fahcon.functional.pp.v | 2,730 | module MODULE1 (
VAR24,
VAR13 ,
VAR8 ,
VAR17 ,
VAR19 ,
VAR26 ,
VAR9 ,
VAR7 ,
VAR5
);
output VAR24;
output VAR13 ;
input VAR8 ;
input VAR17 ;
input VAR19 ;
input VAR26 ;
input VAR9 ;
input VAR7 ;
input VAR5 ;
wire VAR4 ;
wire VAR10 ;
wire VAR2 ;
wire VAR22 ;
wire VAR20 ;
wire VAR11 ;
wire VAR6;
xor VAR3 (VAR4 , VAR8, VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o311ai/sky130_fd_sc_lp__o311ai_2.v | 2,435 | module MODULE2 (
VAR2 ,
VAR5 ,
VAR9 ,
VAR3 ,
VAR4 ,
VAR8 ,
VAR7,
VAR11,
VAR1 ,
VAR6
);
output VAR2 ;
input VAR5 ;
input VAR9 ;
input VAR3 ;
input VAR4 ;
input VAR8 ;
input VAR7;
input VAR11;
input VAR1 ;
input VAR6 ;
VAR10 VAR12 (
.VAR2(VAR2),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR7(VAR7)... | apache-2.0 |
alan4186/Hardware-CNN | Hardware/v/feature_map_ram_1024w.v | 9,567 | module MODULE1 (
VAR55,
VAR2,
VAR42,
VAR47,
VAR19,
VAR59);
parameter VAR58 = "";
input VAR55;
input [23:0] VAR2;
input [9:0] VAR42;
input [9:0] VAR47;
input VAR19;
output [23:0] VAR59;
tri1 VAR55;
tri0 VAR19;
wire [23:0] VAR1;
wire [23:0] VAR59 = VAR1[23:0];
VAR22 VAR30 (
.VAR62 (VAR47),
.VAR33 (VAR42),
.VAR27 (VAR55),... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o211ai/sky130_fd_sc_ls__o211ai.blackbox.v | 1,368 | module MODULE1 (
VAR8 ,
VAR5,
VAR7,
VAR4,
VAR3
);
output VAR8 ;
input VAR5;
input VAR7;
input VAR4;
input VAR3;
supply1 VAR6;
supply0 VAR2;
supply1 VAR9 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/fmcomms2/common/prcfg.v | 5,037 | module MODULE1 (
clk,
VAR5,
VAR6,
VAR9,
VAR2,
VAR14,
VAR27,
VAR28,
VAR24,
VAR17,
VAR10,
VAR21,
VAR16,
VAR7,
VAR26,
VAR4,
VAR11,
VAR23,
VAR15,
VAR8,
VAR25);
input clk;
input [31:0] VAR9;
output [31:0] VAR2;
input [31:0] VAR5;
output [31:0] VAR6;
output VAR14;
input VAR27;
input [63:0] VAR28;
input VAR24;
input VAR17;
ou... | gpl-3.0 |
nikhilghanathe/HLS-for-EMTF | verilog/sp_deltas_m0.v | 48,948 | module MODULE1 (
VAR312,
VAR208,
VAR207,
VAR103,
VAR203,
VAR47,
VAR11,
VAR96,
VAR199,
VAR321,
VAR345,
VAR62,
VAR148,
VAR338,
VAR25,
VAR46,
VAR340,
VAR202,
VAR151,
VAR250,
VAR226,
VAR265,
VAR42,
VAR206,
VAR239,
VAR322,
VAR225,
VAR115,
VAR297,
VAR6,
VAR82,
VAR369,
VAR258,
VAR91,
VAR257,
VAR33,
VAR195
);
parameter VAR366 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/a21oi/sky130_fd_sc_hvl__a21oi.behavioral.v | 1,520 | module MODULE1 (
VAR10 ,
VAR12,
VAR8,
VAR2
);
output VAR10 ;
input VAR12;
input VAR8;
input VAR2;
supply1 VAR9;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
wire VAR13 ;
wire VAR4;
and VAR7 (VAR13 , VAR12, VAR8 );
nor VAR11 (VAR4, VAR2, VAR13 );
buf VAR3 (VAR10 , VAR4 );
endmodule | apache-2.0 |
skyfex/svo-raycaster | orlink/hw/ngc/orlink_wtl_fifo.v | 13,392 | module MODULE1(
rst,
VAR306,
VAR339,
din,
VAR191,
VAR86,
dout,
VAR148,
VAR109
);
input rst;
input VAR306;
input VAR339;
input [31 : 0] din;
input VAR191;
input VAR86;
output [7 : 0] dout;
output VAR148;
output VAR109;
VAR151 #(
.VAR33(0),
.VAR335(0),
.VAR400(0),
.VAR126(0),
.VAR257(0),
.VAR73(0),
.VAR311(0),
.VAR55(32)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/conb/sky130_fd_sc_hdll__conb.pp.symbol.v | 1,276 | module MODULE1 (
output VAR3 ,
output VAR6 ,
input VAR5 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o2bb2a/sky130_fd_sc_hdll__o2bb2a.behavioral.pp.v | 2,193 | module MODULE1 (
VAR18 ,
VAR17,
VAR7,
VAR15 ,
VAR11 ,
VAR5,
VAR10,
VAR3 ,
VAR16
);
output VAR18 ;
input VAR17;
input VAR7;
input VAR15 ;
input VAR11 ;
input VAR5;
input VAR10;
input VAR3 ;
input VAR16 ;
wire VAR14 ;
wire VAR19 ;
wire VAR12 ;
wire VAR2;
nand VAR13 (VAR14 , VAR7, VAR17 );
or VAR9 (VAR19 , VAR11, VAR15 );... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_sigma_delta_spi/util_sigma_delta_spi.v | 1,803 | module MODULE1 (
input clk,
input VAR5,
input VAR13,
input VAR14,
input VAR6,
input VAR4,
output VAR18,
input [VAR9-1:0] VAR17,
output VAR8,
output VAR12,
output VAR7,
input VAR11,
output [VAR9-1:0] VAR10,
output reg VAR15
);
parameter VAR9 = 1;
parameter VAR2 = 0;
parameter VAR1 = 63;
assign VAR8 = VAR14;
assign VAR12... | gpl-3.0 |
AttackerJin/8bit_datapath_AES | AES128/key_expansion.v | 2,026 | module MODULE1(VAR37, VAR19, VAR35, VAR8, clk, VAR24, VAR41, VAR32, VAR21, VAR14);
input [7:0] VAR37;
output [7:0] VAR19;
output [7:0] VAR8;
input [3:0] VAR35;
input clk;
input VAR24, VAR41, VAR32, VAR21;
input [7:0] VAR14;
reg [7:0] VAR28, VAR5, VAR38, VAR4, VAR26, VAR9, VAR18, VAR42, VAR31, VAR11, VAR13, VAR27, VAR23... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22o/sky130_fd_sc_ls__a22o_2.v | 2,339 | module MODULE2 (
VAR10 ,
VAR2 ,
VAR6 ,
VAR8 ,
VAR3 ,
VAR11,
VAR7,
VAR4 ,
VAR1
);
output VAR10 ;
input VAR2 ;
input VAR6 ;
input VAR8 ;
input VAR3 ;
input VAR11;
input VAR7;
input VAR4 ;
input VAR1 ;
VAR5 VAR9 (
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR11(VAR11),
.VAR7(VAR7),
.VAR4(VAR4),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o21ai/sky130_fd_sc_ms__o21ai.functional.pp.v | 2,010 | module MODULE1 (
VAR9 ,
VAR11 ,
VAR4 ,
VAR12 ,
VAR2,
VAR14,
VAR6 ,
VAR7
);
output VAR9 ;
input VAR11 ;
input VAR4 ;
input VAR12 ;
input VAR2;
input VAR14;
input VAR6 ;
input VAR7 ;
wire VAR13 ;
wire VAR8 ;
wire VAR3;
or VAR5 (VAR13 , VAR4, VAR11 );
nand VAR15 (VAR8 , VAR12, VAR13 );
VAR16 VAR10 (VAR3, VAR8, VAR2, VAR14... | apache-2.0 |
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