repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
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google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux2/sky130_fd_sc_hs__mux2.behavioral.v | 1,771 | module MODULE1 (
VAR10 ,
VAR13 ,
VAR6 ,
VAR8 ,
VAR11,
VAR2
);
output VAR10 ;
input VAR13 ;
input VAR6 ;
input VAR8 ;
input VAR11;
input VAR2;
wire VAR1 ;
wire VAR12;
VAR5 VAR4 (VAR1 , VAR13, VAR6, VAR8 );
VAR9 VAR7 (VAR12, VAR1, VAR11, VAR2);
buf VAR3 (VAR10 , VAR12 );
endmodule | apache-2.0 |
rohit91/HDMI2USB | hdl/hdmi/dvi_decoder.v | 8,346 | module MODULE1 (
input wire VAR79, input wire VAR56, input wire VAR34, input wire VAR67, input wire VAR83, input wire VAR48, input wire VAR19, input wire VAR101, input wire VAR64,
output wire reset, output wire VAR94, output wire VAR85, output wire VAR91, output wire VAR4, output wire VAR60, output wire VAR22,
output w... | bsd-2-clause |
eckucukoglu/basic-vending-machine | src/Board232.v | 3,766 | module MODULE3 (
input VAR6,
input [3:0] VAR1,
input [7:0] VAR2,
output [7:0] VAR25,
output reg [6:0] VAR30,
output reg [3:0] VAR32,
output VAR29,
output [2:1] VAR15,
output [2:0] VAR35,
output [2:0] VAR31,
output VAR24,
output VAR5
);
assign VAR29 = 1'b1;
assign VAR25[7] = VAR1[3]; assign VAR25[6] = 1'b0;
wire [7:0] V... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/fill/sky130_fd_sc_lp__fill_4.v | 1,840 | module MODULE2 (
VAR2,
VAR1,
VAR4 ,
VAR6
);
input VAR2;
input VAR1;
input VAR4 ;
input VAR6 ;
VAR3 VAR5 (
.VAR2(VAR2),
.VAR1(VAR1),
.VAR4(VAR4),
.VAR6(VAR6)
);
endmodule
module MODULE2 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR6 ;
VAR3 VAR5 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o41ai/sky130_fd_sc_hs__o41ai.behavioral.pp.v | 1,960 | module MODULE1 (
VAR9,
VAR15,
VAR6 ,
VAR10 ,
VAR12 ,
VAR11 ,
VAR5 ,
VAR4
);
input VAR9;
input VAR15;
output VAR6 ;
input VAR10 ;
input VAR12 ;
input VAR11 ;
input VAR5 ;
input VAR4 ;
wire VAR5 VAR1 ;
wire VAR7 ;
wire VAR2;
or VAR13 (VAR1 , VAR5, VAR11, VAR12, VAR10 );
nand VAR3 (VAR7 , VAR4, VAR1 );
VAR16 VAR8 (VAR2, V... | apache-2.0 |
kyzhai/NUNY | src/hardware/nine_new2_bb.v | 5,018 | module MODULE1 (
address,
VAR1,
VAR2);
input [9:0] address;
input VAR1;
output [11:0] VAR2;
tri1 VAR1;
endmodule | gpl-2.0 |
atalbb/sha1 | SHA1_core.srcs/sources_1/new/Initial_hash.v | 1,559 | module MODULE1(input clk,
input rst,
input VAR5,
input [31:0]VAR3,
output reg VAR2,
output reg [159:0]VAR4
);
reg [2:0]VAR1;
always@(posedge clk or negedge rst) begin
if(rst == 0) begin
VAR2 <= 0;
VAR4 <= 0;
VAR1 <= 0;
end else begin
if(VAR5)
if(VAR1 < 6)
VAR1 <= VAR1 + 1;
end
end
always@(VAR1) begin
if(VAR1 == 1) begi... | apache-2.0 |
franmolinaca/papiGB | rtl/dzcpu_ucode_lut.v | 27,341 | module MODULE3
(
input wire[7:0] VAR60,
output reg [8:0] VAR15
);
always @ ( VAR60 )
begin
case ( VAR60 )
default:
VAR15 = 9'd278;
endcase
end
endmodule
module MODULE1
(
input wire[7:0] VAR60,
output reg [8:0] VAR15
);
always @ ( VAR60 )
begin
case ( VAR60 )
8'h7C: VAR15 = 9'd16; 8'h11: VAR15 = 9'd69; 8'h38: VAR15 = 9'... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/cpci/dma_engine_alignment.v | 11,144 | module MODULE1 (
input [VAR9-1:0] VAR12,
input VAR2,
input VAR13,
input [31:0] VAR7, output VAR10,
input VAR16,
output [VAR9 - 1 : 0] VAR8, output [VAR9 - 1 : 0] VAR32,
input VAR24,
input VAR20, input VAR25, input VAR22,
input VAR33,
input VAR30,
output reg VAR3, output VAR36,
input [1:0] VAR18,
output VAR38,
input VAR... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/hb/mult.v | 1,047 | module MODULE1 (input VAR2, input signed [15:0] VAR4, input signed [15:0] VAR3, output reg signed [30:0] VAR5,
input VAR1, output reg VAR6 );
always @(posedge VAR2)
if(VAR1)
VAR5 <= VAR4*VAR3;
else
VAR5 <= 31'd0;
always @(posedge VAR2)
VAR6 <= VAR1;
endmodule | gpl-2.0 |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/nfa_accept_samples_generic_hw_result.v | 1,448 | module MODULE2 (VAR14, VAR6, VAR1, VAR11, VAR8, clk);
parameter VAR12 = 1;
parameter VAR3 = 4;
parameter VAR13 = 16;
input[VAR3-1:0] VAR14;
input VAR6;
input[VAR12-1:0] VAR1;
input VAR11;
output reg[VAR12-1:0] VAR8;
input clk;
reg [VAR12-1:0] VAR5[VAR13-1:0];
always @(posedge clk)
begin
if (VAR6)
begin
if (VAR11)
begin... | lgpl-3.0 |
Cosmos-OpenSSD/Cosmos-OpenSSD-plus | project/Predefined/2Ch8Way-1.0.3/OpenSSD2_2Ch8Way-1.0.3/OpenSSD2.srcs/sources_1/bd/OpenSSD2/ip/OpenSSD2_auto_us_cc_df_1/synth/OpenSSD2_auto_us_cc_df_1.v | 14,826 | module MODULE1 (
VAR57,
VAR92,
VAR53,
VAR27,
VAR85,
VAR91,
VAR78,
VAR39,
VAR18,
VAR33,
VAR22,
VAR30,
VAR10,
VAR2,
VAR42,
VAR88,
VAR96,
VAR87,
VAR12,
VAR60,
VAR26,
VAR98,
VAR76,
VAR36,
VAR43,
VAR89,
VAR8,
VAR20,
VAR13,
VAR5,
VAR64,
VAR97,
VAR25,
VAR9,
VAR46,
VAR72,
VAR1,
VAR44,
VAR23,
VAR68,
VAR48,
VAR83,
VAR11,
VAR67,
... | gpl-3.0 |
aj-michael/Digital-Systems | Pong/Phase2/vsyncModule.v | 1,275 | module MODULE1(VAR2, VAR8, VAR12, VAR4, VAR7, VAR9, VAR5, reset, VAR1);
parameter VAR11=10;
input [VAR11-1:0] VAR8, VAR12, VAR4, VAR7;
input reset, VAR1, VAR2;
output VAR9;
output reg [VAR11-1:0] VAR5;
wire [VAR11-1:0] VAR14;
VAR17 VAR10(VAR2, VAR13, reset, VAR1);
assign VAR9 = ~((VAR14 > VAR4+VAR12) && (VAR14 <= VAR4+... | mit |
mbus/mbus | mbus/verilog/mbus_addr_rf.v | 1,371 | module MODULE1(
input VAR3,
input VAR1,
output reg [VAR10-1:0] VAR2,
input [VAR10-1:0] VAR7,
output reg VAR6,
input VAR8,
input VAR4
);
wire VAR5 = (VAR3 & VAR4);
wire VAR9 = (VAR8 & (~VAR1));
wire VAR9 = VAR8;
always @ (posedge VAR9 or negedge VAR5)
begin
if (~VAR5)
begin
VAR2 <= {VAR10{1'b1}};
VAR6 <= 0;
end
else
beg... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/einvp/sky130_fd_sc_ls__einvp_1.v | 2,130 | module MODULE2 (
VAR3 ,
VAR8 ,
VAR5 ,
VAR4,
VAR6,
VAR9 ,
VAR2
);
output VAR3 ;
input VAR8 ;
input VAR5 ;
input VAR4;
input VAR6;
input VAR9 ;
input VAR2 ;
VAR7 VAR1 (
.VAR3(VAR3),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR2(VAR2)
);
endmodule
module MODULE2 (
VAR3 ,
VAR8 ,
VAR5
);
output VAR3... | apache-2.0 |
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab10/kustar.v | 6,182 | module MODULE1;
reg VAR48, VAR33;
wire VAR78;
reg [31:0] VAR64;
reg [31:0] VAR67;
reg [31:0] VAR49;
reg [31:0] VAR75;
reg [31:0] VAR18;
reg [31:0] VAR27;
reg [4:0] VAR3;
reg [4:0] VAR26;
reg [8:0] VAR30;
reg [31:0] VAR81;
reg VAR36;
reg [31:0] VAR13;
reg [31:0] VAR62;
reg [4:0] VAR38;
reg [4:0] VAR12;
reg [31:0] VAR31;... | mit |
lkesteloot/alice | alice4/fpga/Alice4-DE0/SDRAM_clock_bb.v | 11,181 | module MODULE1 (
VAR4,
VAR2,
VAR3,
VAR1);
input VAR4;
input VAR2;
output VAR3;
output VAR1;
tri0 VAR4;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2bb2a/sky130_fd_sc_ms__o2bb2a_1.v | 2,398 | module MODULE2 (
VAR11 ,
VAR5,
VAR1,
VAR6 ,
VAR7 ,
VAR4,
VAR3,
VAR2 ,
VAR8
);
output VAR11 ;
input VAR5;
input VAR1;
input VAR6 ;
input VAR7 ;
input VAR4;
input VAR3;
input VAR2 ;
input VAR8 ;
VAR9 VAR10 (
.VAR11(VAR11),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR8(VA... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/util_upack/util_upack.v | 10,703 | module MODULE1 (
VAR60,
VAR18,
VAR36,
VAR69,
VAR23,
VAR37,
VAR67,
VAR39,
VAR53,
VAR74,
VAR15,
VAR32,
VAR71,
VAR11,
VAR1,
VAR8,
VAR47,
VAR7,
VAR43,
VAR76,
VAR34,
VAR46,
VAR56,
VAR20,
VAR17,
VAR72,
VAR40,
VAR14,
VAR49,
VAR68,
VAR27,
VAR52,
VAR9,
VAR57,
VAR19,
VAR22,
VAR10,
VAR58);
parameter VAR6 = 32;
parameter VAR54 = 8... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux4/sky130_fd_sc_lp__mux4_1.v | 2,444 | module MODULE1 (
VAR10 ,
VAR5 ,
VAR12 ,
VAR7 ,
VAR11 ,
VAR9 ,
VAR3 ,
VAR6,
VAR13,
VAR8 ,
VAR1
);
output VAR10 ;
input VAR5 ;
input VAR12 ;
input VAR7 ;
input VAR11 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR13;
input VAR8 ;
input VAR1 ;
VAR2 VAR4 (
.VAR10(VAR10),
.VAR5(VAR5),
.VAR12(VAR12),
.VAR7(VAR7),
.VAR11(VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.symbol.v | 1,273 | module MODULE1 (
input VAR5,
input VAR6,
input VAR3,
output VAR4
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/lfsr.v | 6,680 | module MODULE1 #(
parameter VAR2=8,
parameter VAR10=256
) (
VAR7,
VAR9,
VAR5,
enable,
clk,
reset
);
output wire [31:0] VAR9;
output reg [31:0] VAR5;
wire [31:0] VAR1;
input [31:0] VAR7;
input enable, clk, reset;
reg [31:0] out;
wire VAR4;
wire [31:0] VAR6;
reg state, VAR11;
reg [5:0] select;
wire [31:0] VAR3;
localpara... | apache-2.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_ic_ram.v | 5,719 | module MODULE1(
clk, rst,
VAR19, VAR16, VAR12,
addr, en, VAR3, VAR14, VAR6
);
parameter VAR7 = VAR2;
parameter VAR1 = VAR15;
input clk;
input rst;
input [VAR1-1:0] addr;
input en;
input [3:0] VAR3;
input [VAR7-1:0] VAR14;
output [VAR7-1:0] VAR6;
input VAR19;
input [VAR11 - 1:0] VAR12;
output VAR16;
assign VAR6 = {VAR7{... | apache-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/lib/verilog/core/bin_cam/src/decoder.v | 4,309 | module MODULE1 (
VAR1,
VAR5
);
parameter VAR2 = 64;
parameter VAR8 = VAR4(VAR2);
input [VAR8-1:0] VAR1;
output [VAR2-1:0] VAR5;
reg [VAR2-1:0] VAR5;
integer VAR6;
always @(*)
begin
VAR5 = 0;
VAR5 = VAR5 + 2**(VAR1);
end
function integer VAR4;
input [32:0] VAR7;
integer VAR3;
begin
VAR4 = 1;
for (VAR3=0; 2**VAR3 < VAR7;... | mit |
audiocircuit/NCSU-Low-Power-RFID | Memory/slave.v | 8,001 | module MODULE1(
input wire [6:0] VAR2,
input wire [7:0] VAR12,
input wire en,
input wire reset,
input wire VAR15,
inout wire VAR9
);
reg VAR7, VAR8, VAR10;
reg [7:0] VAR6;
reg [6:0] VAR3;
reg [2:0] state;
reg [4:0] counter;
reg VAR13, VAR1;
reg VAR5, VAR4;
assign #(1) VAR9 = (VAR5) ? ( VAR13 ) ? 1'VAR11 : 1'b0 : 1'VAR1... | gpl-3.0 |
m-labs/milkymist | cores/vgafb/rtl/vgafb_fifo64to16.v | 1,817 | module MODULE1(
input VAR10,
input VAR7,
input VAR9,
input [63:0] VAR8,
output VAR1,
output VAR6,
output reg [15:0] do,
input VAR2
);
reg [63:0] VAR12[0:7];
reg [2:0] VAR4;
reg [4:0] VAR5;
reg [5:0] VAR3;
wire [63:0] VAR11;
assign VAR11 = VAR12[VAR5[4:2]];
always @(*) begin
case(VAR5[1:0])
2'd0: do <= VAR11[63:48];
2'd... | lgpl-3.0 |
UCLONG/NetEmulation | BEE3_top/C3D_original_code/b2b/src/aur1_error_detect.v | 9,432 | module MODULE1
(
VAR3,
VAR17,
VAR7,
VAR1,
VAR13,
VAR15,
VAR4,
VAR12,
VAR16,
VAR6
);
input VAR3;
output VAR17;
output VAR7;
output VAR1;
input VAR13;
input [1:0] VAR15;
input [1:0] VAR4;
input VAR12;
input VAR16;
input VAR6;
reg VAR1;
reg VAR7;
reg [0:1] VAR5;
reg VAR10;
reg [0:1] VAR18;
reg [0:1] VAR14;
reg VAR9; reg V... | gpl-3.0 |
bfarago/xmos_cpld_slice | altera/concept/xmos_cpld_slice.v | 11,565 | module MODULE1
(
VAR100,
VAR47,
VAR36,
VAR81,
VAR83,
VAR11,
VAR78,
VAR23,
VAR119,
VAR72,
VAR76,
VAR98,
VAR21,
VAR3,
VAR63,
VAR12,
VAR94,
VAR18,
VAR37,
VAR73,
VAR42,
VAR58,
VAR104,
VAR9,
VAR52,
VAR61,
VAR101,
VAR107,
VAR54,
VAR48,
VAR35,
VAR120,
VAR5,
VAR15,
VAR124,
VAR59,
VAR67,
VAR93,
VAR39,
VAR49,
VAR10,
VAR86,
VAR12... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2b/sky130_fd_sc_ms__or2b.behavioral.v | 1,442 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR1
);
output VAR7 ;
input VAR6 ;
input VAR1;
supply1 VAR2;
supply0 VAR12;
supply1 VAR5 ;
supply0 VAR4 ;
wire VAR8 ;
wire VAR3;
not VAR11 (VAR8 , VAR1 );
or VAR9 (VAR3, VAR8, VAR6 );
buf VAR10 (VAR7 , VAR3 );
endmodule | apache-2.0 |
aap/pdp6 | verilog/dly_50.v | 7,972 | module MODULE12(input clk, input reset, input in, output VAR2);
reg [2-1:0] VAR1;
always @(posedge clk or posedge reset) begin
if(reset)
VAR1 <= 0;
end
else begin
if(VAR1)
VAR1 <= VAR1 + 2'b1;
if(in)
VAR1 <= 1;
end
end
assign VAR2 = VAR1 == 2;
endmodule
module MODULE26(input clk, input reset, input in, output VAR2);
re... | mit |
lloves/Sora | FPGA/MIMO/rtl/pcie_userapp_wrapper/Sora_Fast_Radio_Link/RCB_FRL_count_to_128.v | 2,234 | module MODULE1(
input clk,
input rst,
input VAR1,
input VAR2,
output reg [6:0] VAR3
);
wire [6:0] VAR4;
always@(posedge clk or posedge rst) begin
if(rst == 1'b1)
VAR3 = 7'h00;
end
else begin
case({VAR1,VAR2})
2'b00: VAR3 = 7'h00;
2'b01: VAR3 = VAR4;
2'b10: VAR3 = VAR4 - 1;
2'b11: VAR3 = VAR4 + 1;
default: VAR3 = 7'h00;... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a.pp.blackbox.v | 1,351 | module MODULE1 (
VAR6 ,
VAR1 ,
VAR2 ,
VAR4 ,
VAR7,
VAR3,
VAR8 ,
VAR5
);
output VAR6 ;
input VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR7;
input VAR3;
input VAR8 ;
input VAR5 ;
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/sparc/exu/rtl/sparc_exu_eclccr.v | 11,115 | module MODULE1 (
VAR28, VAR69, VAR20, VAR54,
VAR105,
clk, VAR66, VAR47, VAR42, VAR77, VAR16, VAR53,
VAR65, VAR83, VAR57, VAR43, VAR48,
VAR55, VAR36, VAR31,
VAR71, VAR21, VAR13,
VAR73, VAR80, VAR26, VAR46
) ;
input clk;
input VAR66;
input [3:0] VAR47; input [3:0] VAR42;
input [1:0] VAR77; input [3:0] VAR16; input VAR53;... | gpl-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_qpll_reset.v | 14,594 | module MODULE1 #
(
parameter VAR6 = "VAR38", parameter VAR30 = "VAR22", parameter VAR2 = 1, parameter VAR27 = 1
)
(
input VAR26,
input VAR31,
input VAR37,
input [VAR2-1:0] VAR47,
input [(VAR2-1)>>2:0]VAR8,
input [(VAR2-1)>>2:0]VAR40,
input [ 1:0] VAR29,
input [VAR2-1:0] VAR21,
input [VAR2-1:0] VAR9,
output VAR28,
outpu... | gpl-3.0 |
tuura/fantasi | dependencies/Altera_DE4/niosII/synthesis/submodules/system1_mm_interconnect_0_avalon_st_adapter.v | 6,174 | module MODULE1 #(
parameter VAR4 = 34,
parameter VAR20 = 0,
parameter VAR23 = 34,
parameter VAR17 = 0,
parameter VAR2 = 0,
parameter VAR13 = 0,
parameter VAR6 = 1,
parameter VAR19 = 1,
parameter VAR16 = 0,
parameter VAR15 = 34,
parameter VAR21 = 0,
parameter VAR11 = 1,
parameter VAR7 = 0,
parameter VAR25 = 1,
parameter... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/conb/sky130_fd_sc_hs__conb.behavioral.pp.v | 1,580 | module MODULE1 (
VAR5,
VAR8,
VAR7 ,
VAR6
);
input VAR5;
input VAR8;
output VAR7 ;
output VAR6 ;
wire VAR9;
pullup VAR3 (VAR9);
VAR2 VAR4 (VAR7 , VAR9, VAR5, VAR8);
pulldown VAR1 (VAR6 );
endmodule | apache-2.0 |
cafe-alpha/wascafe | v11/fpga_firmware/wasca/synthesis/submodules/wasca_nios2_gen2_0_cpu_debug_slave_wrapper.v | 9,436 | module MODULE1 (
VAR31,
VAR53,
clk,
VAR40,
VAR38,
VAR42,
VAR3,
VAR32,
VAR9,
VAR21,
VAR24,
VAR16,
VAR43,
VAR37,
VAR25,
VAR51,
VAR34,
VAR17,
VAR56,
VAR14,
VAR4,
VAR2,
VAR29,
VAR1,
VAR12,
VAR36,
VAR45,
VAR49,
VAR33,
VAR22,
VAR55,
VAR47,
VAR50
)
;
output [ 37: 0] VAR4;
output VAR2;
output VAR29;
output VAR1;
output VAR12;
... | gpl-2.0 |
fallen/milkymist-mmu | cores/dmx/rtl/dmx_rx.v | 5,307 | module MODULE1 #(
parameter VAR16 = 4'h0,
parameter VAR46 = 100000000
) (
input VAR49,
input VAR4,
input [13:0] VAR13,
input VAR6,
input [31:0] VAR51,
output [31:0] VAR8,
input VAR53
);
wire VAR28 = VAR13[13:10] == VAR16;
wire [7:0] VAR15;
reg [8:0] VAR18;
reg VAR11;
reg [7:0] VAR1;
VAR26 VAR37(
.clk(VAR49),
.VAR42(VAR... | lgpl-3.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/phy/mig_7series_v4_0_poc_tap_base.v | 10,963 | module MODULE1 #
(parameter VAR48 = 10,
parameter VAR45 = "VAR9",
parameter VAR56 = 100,
parameter VAR32 = 8,
parameter VAR17 = 2,
parameter VAR11 = 7,
parameter VAR12 = 112)
(
VAR59, VAR24, VAR19, VAR53, VAR8, VAR28,
VAR49, VAR27, VAR37, VAR14, VAR30, VAR41, VAR26,
VAR18, clk, VAR43, VAR29, VAR7, rst,
VAR6
);
function... | mit |
hightoon/Sora | FPGA/SISO/ip_cores/pcie_endpoint_plus_x8_250/endpoint_blk_plus_v1_14/source/endpoint_blk_plus_v1_14.v | 19,616 | module MODULE1 # (
parameter VAR114 = "VAR3",
parameter VAR192 = 0,
parameter VAR174 = 4,
parameter VAR12 = 1,
parameter VAR33 = 0,
parameter VAR169 = 64,
parameter VAR153 = 8,
parameter VAR130 = 4,
parameter VAR154 = 7,
parameter VAR74 = 8,
parameter VAR151 = 12,
parameter VAR9 = 32,
parameter VAR185 = 10,
parameter V... | bsd-2-clause |
ankitshah009/High-Radix-Adaptive-CORDIC | HCORDIC_Verilog/AddState.v | 2,418 | module MODULE1(
input [1:0] VAR9,
input [35:0] VAR15,
input [35:0] VAR12,
input [31:0] VAR8,
input [1:0] VAR27,
input VAR5,
input VAR3,
input [7:0] VAR11,
input VAR20,
output reg [1:0] VAR14,
output reg [31:0] VAR16,
output reg [1:0] VAR22,
output reg VAR24,
output reg VAR2,
output reg [27:0] VAR18,
output reg [7:0] VA... | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/iface/ip/Write_Master/ST_to_MM_Adapter.v | 5,150 | module MODULE1 (
clk,
reset,
enable,
address,
VAR10,
VAR11,
VAR12,
VAR20,
VAR17,
VAR9,
VAR8
);
parameter VAR16 = 32;
parameter VAR21 = 2;
parameter VAR4 = 32;
parameter VAR18 = 0; localparam VAR22 = VAR21 + 1;
input clk;
input reset;
input enable; input [VAR4-1:0] address;
input VAR10; input VAR11;
input VAR12;
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/clkdlyinv3sd3/sky130_fd_sc_ms__clkdlyinv3sd3.functional.pp.v | 1,867 | module MODULE1 (
VAR12 ,
VAR5 ,
VAR9,
VAR4,
VAR6 ,
VAR1
);
output VAR12 ;
input VAR5 ;
input VAR9;
input VAR4;
input VAR6 ;
input VAR1 ;
wire VAR3 ;
wire VAR7;
not VAR2 (VAR3 , VAR5 );
VAR11 VAR10 (VAR7, VAR3, VAR9, VAR4);
buf VAR8 (VAR12 , VAR7 );
endmodule | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/submodules/altera_avalon_st_handshake_clock_crosser.v | 7,553 | module MODULE1
parameter VAR38 = 8,
VAR43 = 8,
VAR6 = 0,
VAR23 = 0,
VAR25 = 1,
VAR39 = 0,
VAR45 = 1,
VAR16 = 2,
VAR20 = 2,
VAR7 = 1,
VAR17 = VAR38 / VAR43,
VAR27 = VAR36(VAR17)
)
(
input VAR35,
input VAR28,
input VAR29,
input VAR42,
output VAR34,
input VAR11,
input [VAR38 - 1 : 0] VAR26,
input [VAR25 - 1 : 0] VAR30,
in... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/or2/sky130_fd_sc_ms__or2_4.v | 2,075 | module MODULE1 (
VAR6 ,
VAR2 ,
VAR1 ,
VAR5,
VAR8,
VAR9 ,
VAR7
);
output VAR6 ;
input VAR2 ;
input VAR1 ;
input VAR5;
input VAR8;
input VAR9 ;
input VAR7 ;
VAR3 VAR4 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR6,
VAR2,
VAR1
);
output VAR6;
... | apache-2.0 |
alexforencich/xfcp | lib/eth/lib/axis/rtl/axis_tap.v | 11,847 | module MODULE1 #
(
parameter VAR13 = 8,
parameter VAR57 = (VAR13>8),
parameter VAR52 = (VAR13/8),
parameter VAR47 = 0,
parameter VAR65 = 8,
parameter VAR33 = 0,
parameter VAR31 = 8,
parameter VAR10 = 1,
parameter VAR6 = 1,
parameter VAR44 = 1'b1,
parameter VAR50 = 1'b1
)
(
input wire clk,
input wire rst,
input wire [VA... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/latq/gf180mcu_fd_sc_mcu7t5v0__latq_4.behavioral.v | 1,718 | module MODULE1( VAR4, VAR5, VAR6 );
input VAR5, VAR4;
output VAR6;
reg VAR3;
VAR7 VAR9(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3));
VAR7 VAR10(.VAR4(VAR4),.VAR5(VAR5),.VAR6(VAR6),.VAR3(VAR3));
not VAR8(VAR1,VAR5);
buf VAR11(VAR2,VAR5); | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/ac97/rtl/ac97.v | 5,027 | module MODULE1 #(
parameter VAR29 = 4'h0
) (
input VAR37,
input VAR69,
input VAR43,
input VAR14,
input VAR39,
output VAR67,
output VAR4,
input [13:0] VAR51,
input VAR64,
input [31:0] VAR26,
output [31:0] VAR48,
output VAR3,
output VAR20,
output VAR27,
output VAR8,
output [31:0] VAR76,
output [2:0] VAR58,
output VAR32,
... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfxtp/sky130_fd_sc_ms__dfxtp_1.v | 2,128 | module MODULE1 (
VAR8 ,
VAR9 ,
VAR4 ,
VAR5,
VAR3,
VAR7 ,
VAR6
);
output VAR8 ;
input VAR9 ;
input VAR4 ;
input VAR5;
input VAR3;
input VAR7 ;
input VAR6 ;
VAR1 VAR2 (
.VAR8(VAR8),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR7(VAR7),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR8 ,
VAR9,
VAR4
);
output VAR8 ... | apache-2.0 |
cpulabs/mist1032isa | src/core/l1_instruction/l1_inst_cache_64entry_4way_line64b_bus_8b_disable_cache.v | 1,457 | module MODULE1(
input wire VAR15,
input wire VAR12,
input wire VAR4,
input wire VAR16,
input wire VAR5,
output wire VAR8,
input wire [31:0] VAR2, output wire VAR13,
output wire VAR17,
input wire VAR7,
output wire [63:0] VAR11,
output wire [23:0] VAR6,
input wire VAR14,
output wire VAR10,
input wire [31:0] VAR9, input w... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrtn/sky130_fd_sc_hd__dlrtn.pp.blackbox.v | 1,385 | module MODULE1 (
VAR8 ,
VAR6,
VAR5 ,
VAR1 ,
VAR3 ,
VAR4 ,
VAR7 ,
VAR2
);
output VAR8 ;
input VAR6;
input VAR5 ;
input VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR2 ;
endmodule | apache-2.0 |
christakissgeo/Matrix-Vector-Multiplication | Libraries/NangateOpenCellLibrary.v | 220,307 | module MODULE1 (VAR1, VAR2, VAR3);
input VAR1;
input VAR2;
output VAR3;
and(VAR3, VAR1, VAR2); | mit |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/ucore/bypass.v | 9,242 | module MODULE1
(
VAR33,VAR48,
VAR25,VAR17,VAR5,VAR16,
VAR32,VAR31,
VAR27,VAR37,VAR8,VAR28,
VAR26,VAR15,VAR19,VAR13,
VAR34,VAR47,
VAR20,VAR50,VAR44,
VAR2,VAR46,VAR45,VAR18,
VAR42,VAR29,VAR9,
VAR36,VAR38,VAR35,
VAR30,VAR11,VAR24,
VAR49,VAR1,VAR51,
VAR6,VAR7,VAR43,
VAR3,VAR40,
VAR21
);
input VAR33;
input VAR48;
input [VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o32ai/sky130_fd_sc_hs__o32ai_2.v | 2,314 | module MODULE1 (
VAR5 ,
VAR10 ,
VAR7 ,
VAR4 ,
VAR9 ,
VAR3 ,
VAR6,
VAR1
);
output VAR5 ;
input VAR10 ;
input VAR7 ;
input VAR4 ;
input VAR9 ;
input VAR3 ;
input VAR6;
input VAR1;
VAR8 VAR2 (
.VAR5(VAR5),
.VAR10(VAR10),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR6(VAR6),
.VAR1(VAR1)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/sregsbp/sky130_fd_sc_lp__sregsbp.blackbox.v | 1,381 | module MODULE1 (
VAR6 ,
VAR11 ,
VAR1 ,
VAR5 ,
VAR2 ,
VAR4 ,
VAR3
);
output VAR6 ;
output VAR11 ;
input VAR1 ;
input VAR5 ;
input VAR2 ;
input VAR4 ;
input VAR3;
supply1 VAR10;
supply0 VAR7;
supply1 VAR8 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
glennchid/font5-firmware | src/verilog/synthesis/FFControl.v | 9,909 | module MODULE1 (
input clk,
input VAR28,
input VAR8,
input VAR4,
input [9:0] VAR56,
input [9:0] VAR39,
input [4:0] VAR51,
input [4:0] VAR37,
input [1:0] VAR46, input signed [12:0] VAR62,
input signed [12:0] VAR10,
input signed [12:0] VAR43,
input signed [12:0] VAR42,
input signed [6:0] VAR55,
input signed [6:0] VAR36,
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a221o/sky130_fd_sc_ls__a221o.behavioral.v | 1,662 | module MODULE1 (
VAR4 ,
VAR17,
VAR10,
VAR16,
VAR1,
VAR15
);
output VAR4 ;
input VAR17;
input VAR10;
input VAR16;
input VAR1;
input VAR15;
supply1 VAR11;
supply0 VAR14;
supply1 VAR8 ;
supply0 VAR6 ;
wire VAR13 ;
wire VAR2 ;
wire VAR7;
and VAR3 (VAR13 , VAR16, VAR1 );
and VAR5 (VAR2 , VAR17, VAR10 );
or VAR12 (VAR7, VAR2... | apache-2.0 |
mistryalok/Zedboard | learning/opencv_hls/xapp1167_vivado/sw/fast-corner/prj/solution1/syn/verilog/FIFO_image_filter_p_src_cols_V_2_loc_channel1.v | 3,047 | module MODULE2 (
clk,
VAR3,
VAR21,
VAR23,
VAR18);
parameter VAR11 = 32'd12;
parameter VAR10 = 32'd2;
parameter VAR6 = 32'd3;
input clk;
input [VAR11-1:0] VAR3;
input VAR21;
input [VAR10-1:0] VAR23;
output [VAR11-1:0] VAR18;
reg[VAR11-1:0] VAR14 [0:VAR6-1];
integer VAR27;
always @ (posedge clk)
begin
if (VAR21)
begin
fo... | gpl-3.0 |
JakeMercer/mac | crc.v | 4,790 | module MODULE1 #(
parameter VAR18 = 5'b00101,
parameter VAR20 = 8,
parameter VAR15 = 5,
parameter VAR12 = 0,
parameter VAR13 = 0,
parameter VAR14 = 1
)(
input [VAR20-1:0] VAR6,
input VAR7,
output reg [VAR15-1:0] VAR4,
input VAR3,
input VAR11,
input reset
);
function automatic VAR17;
input integer VAR10;
input integer V... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/bufinv/sky130_fd_sc_hd__bufinv.pp.symbol.v | 1,272 | module MODULE1 (
input VAR3 ,
output VAR6 ,
input VAR5 ,
input VAR2,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3b/sky130_fd_sc_lp__or3b_m.v | 2,206 | module MODULE1 (
VAR9 ,
VAR8 ,
VAR4 ,
VAR7 ,
VAR10,
VAR5,
VAR1 ,
VAR2
);
output VAR9 ;
input VAR8 ;
input VAR4 ;
input VAR7 ;
input VAR10;
input VAR5;
input VAR1 ;
input VAR2 ;
VAR6 VAR3 (
.VAR9(VAR9),
.VAR8(VAR8),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR2(VAR2)
);
endmodule
module MODULE... | apache-2.0 |
ychaim/FPGA-Litecoin-Miner | experimental/CM1/main_dcm.v | 5,673 | module MODULE1
( input VAR13,
output VAR17,
input VAR23,
input VAR32,
input VAR22,
output VAR18,
input VAR1,
output VAR24
);
parameter VAR35 = 10;
parameter VAR21 = 60;
VAR19 VAR14
(.VAR38 (VAR9),
.VAR12 (VAR13));
wire VAR27;
wire [2:1] VAR39;
wire VAR25;
wire VAR31;
wire VAR3;
VAR29
.VAR15 (VAR21),
.VAR30 ("VAR36"),
.... | gpl-3.0 |
zeruniverse/Single-cycle_CPU | ISE project/CPU_CTR.v | 1,152 | module MODULE1(
input [5:0]VAR1,
output wire VAR20,VAR3,VAR17,VAR6,VAR8,VAR11,VAR21,VAR19,VAR14 );
wire VAR5,VAR15,VAR4,VAR16,VAR18;
and VAR7(VAR14,~VAR1[5],~VAR1[4],~VAR1[3],~VAR1[2],VAR1[1],~VAR1[0]),
VAR2(VAR15,~VAR1[5],~VAR1[4],~VAR1[3],~VAR1[2],~VAR1[1],~VAR1[0]),
VAR13(VAR4,VAR1[5],~VAR1[4],~VAR1[3],~VAR1[2],VAR1... | gpl-3.0 |
masson2013/heterogeneous_hthreads | src/hardware/MyRepository/pcores/vivado_cores/sfa_2x2_v1_0/sfa_bif.v | 5,708 | module MODULE1(
output wire VAR11 ,
output wire VAR4 ,
output reg VAR13 ,
output reg [ 3 : 0] VAR12 ,
output wire [31 : 0] VAR21 ,
output wire [31 : 0] VAR7 ,
input wire [31 : 0] VAR24 ,
output wire VAR22 ,
input wire VAR26 ,
input wire [31 : 0] VAR29 ,
input wire VAR8 ,
output wire VAR31 ,
output wire [31 : 0] VAR25 ,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_nr_pp_pkg_s/sky130_fd_sc_hs__udp_dff_nr_pp_pkg_s.blackbox.v | 1,463 | module MODULE1 (
VAR8 ,
VAR1 ,
VAR7 ,
VAR6 ,
VAR3,
VAR5 ,
VAR2 ,
VAR4
);
output VAR8 ;
input VAR1 ;
input VAR7 ;
input VAR6 ;
input VAR3;
input VAR5 ;
input VAR2 ;
input VAR4 ;
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/ctrl/qmem_sram_longcycles.v | 5,602 | module MODULE1 #(
parameter VAR37 = 32,
parameter VAR9 = 32,
parameter VAR11 = VAR9/8
)(
input wire VAR35,
input wire VAR13,
input wire rst,
input wire [VAR37-1:0] VAR31,
input wire VAR30,
input wire VAR10,
input wire [VAR11-1:0] sel,
input wire [VAR9-1:0] VAR18,
output reg [VAR9-1:0] VAR5,
output wire ack,
output wire... | gpl-3.0 |
azonenberg/antikernel-ipcores | noc/rpcv3/RPCv3RouterReceiver_expanding.v | 8,426 | module MODULE1
parameter VAR1 = 32,
parameter VAR2 = 16
)
(
input wire clk,
input wire VAR5,
input wire[VAR2-1:0] VAR9,
output reg VAR8 = 0,
input wire VAR3,
output wire VAR6,
output reg VAR10 = 0,
output reg[VAR1-1:0] VAR7 = 0,
output reg VAR4 = 0
); | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/mux4/gf180mcu_fd_sc_mcu9t5v0__mux4_2.functional.pp.v | 1,410 | module MODULE1( VAR14, VAR13, VAR10, VAR16, VAR17, VAR4, VAR21, VAR2, VAR6 );
input VAR21, VAR4, VAR14, VAR10, VAR13, VAR17;
inout VAR2, VAR6;
output VAR16;
wire VAR19;
not VAR12( VAR19, VAR13 );
wire VAR18;
not VAR9( VAR18, VAR17 );
wire VAR20;
and VAR22( VAR20, VAR19, VAR18, VAR21 );
wire VAR11;
and VAR15( VAR11, VAR... | apache-2.0 |
saisrivathsa/Image-Watermarking | ipcore_dir/Bmul.v | 3,628 | module MODULE2 (
VAR12, VAR27
);
output [7 : 0] VAR12;
input [7 : 0] VAR27;
wire [7 : 1] VAR31;
assign
VAR12[6] = VAR31[7],
VAR12[5] = VAR31[6],
VAR12[4] = VAR31[5],
VAR12[3] = VAR31[4],
VAR12[2] = VAR31[3],
VAR12[1] = VAR31[2],
VAR12[0] = VAR31[1],
VAR31[7] = VAR27[7],
VAR31[6] = VAR27[6],
VAR31[5] = VAR27[5],
VAR31[4... | mit |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T09-inicializador/init.v | 1,067 | module MODULE1(input wire clk, output VAR1);
reg VAR1 = 0;
always @(posedge(clk))
VAR1 <= 1;
endmodule | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and3b/sky130_fd_sc_hd__and3b.blackbox.v | 1,295 | module MODULE1 (
VAR7 ,
VAR1,
VAR4 ,
VAR2
);
output VAR7 ;
input VAR1;
input VAR4 ;
input VAR2 ;
supply1 VAR3;
supply0 VAR5;
supply1 VAR6 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffsnq/gf180mcu_fd_sc_mcu9t5v0__sdffsnq_4.behavioral.pp.v | 18,950 | module MODULE1( VAR52, VAR190, VAR245, VAR197, VAR222, VAR74, VAR2, VAR68 );
input VAR197, VAR245, VAR52, VAR222, VAR190;
inout VAR2, VAR68;
output VAR74;
reg VAR289;
VAR298 VAR230(.VAR52(VAR52),.VAR190(VAR190),.VAR245(VAR245),.VAR197(VAR197),.VAR222(VAR222),.VAR74(VAR74),.VAR2(VAR2),.VAR68(VAR68),.VAR289(VAR289));
VAR... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_addr_cmd_wrap.v | 50,200 | module MODULE1
VAR109 = 2,
VAR81 = 2, VAR194 = 16, VAR180 = 16, VAR182 = 12, VAR132 = 3, VAR35 = 1,
VAR123 = 3,
VAR136 = 2,
VAR112 = 2,
VAR154 = 8,
VAR40 = 4,
VAR6 = 4,
VAR71 = 1,
VAR75 = 2,
VAR94 = 5,
VAR11 = 5,
VAR167 = 5,
VAR196 = 4,
VAR76 = 4,
VAR80 = 1
)
(
VAR3,
VAR26,
VAR193,
VAR93,
VAR124,
VAR103,
VAR22,
VAR70,
... | gpl-3.0 |
velizarefremov/MIPS | Part 2/Verilog Code/decoderparam.v | 1,127 | module MODULE1
( output reg [2**VAR7-1 : 0] VAR4,
input [VAR7-1 : 0] VAR6,
input VAR5
);
localparam VAR8 = VAR7;
integer VAR2, VAR3, VAR9;
reg [(VAR8+1)*(2**VAR8):0] VAR1;
always @(VAR6, VAR1, VAR5) begin
VAR1[VAR8*(2**VAR8)] <= VAR5;
for(VAR3=VAR8; VAR3 > 0; VAR3 = VAR3 - 1) begin
for (VAR9 = 0; VAR9 < 2**(VAR8 - VAR3... | gpl-2.0 |
davidjabon/Verilog | Seven_Segment_LED_drivers/seven_segment_leds_x_4.v | 2,090 | module MODULE1(
input [15:0] VAR3,
input [3:0] VAR5,
input clk,
output reg [6:0] VAR6,
output reg VAR1,
output reg [3:0] VAR4
);
wire [1:0] counter;
reg [3:0] VAR7;
reg [19:0] VAR2;
assign counter = VAR2[19:18];
always @(posedge clk)
case(counter)
0: {VAR7, VAR1} = {VAR3[3:0], VAR5[0]};
1: {VAR7, VAR1} = {VAR3[7:4], VA... | gpl-2.0 |
sabertazimi/hust-lab | architecture/design/fpga/src/alu.v | 1,655 | module MODULE1
(
input [VAR8-1:0] VAR1,
input [VAR8-1:0] VAR3,
input [3:0] VAR7,
output reg [VAR8-1:0] VAR6,
output VAR11,
output VAR5,
output VAR2
);
wire signed [VAR8-1:0] VAR10;
wire signed [VAR8-1:0] VAR9;
assign VAR10 = (VAR1);
assign VAR9 = (VAR3);
always @ ( * ) begin
case (VAR7)
4'd0: VAR6 <= VAR1 << VAR3;
4'd1... | mit |
AmeerAbdelhadi/Switched-Multiported-RAM | smpram.v | 11,221 | module MODULE1
localparam VAR7 = VAR34+VAR8 ; localparam VAR11 = VAR15+VAR40 ; localparam VAR41 = VAR5(VAR30);
localparam VAR26 = VAR5(VAR7) ;
localparam VAR4 = VAR37*(VAR7-1) ;
localparam VAR44 = VAR26*(VAR7+VAR11-1);
localparam VAR14 = (VAR7-1)*(VAR11+1) ;
localparam VAR21 = (VAR30<=1024 ) ? "VAR13" :
( (VAR30<=2048 ... | bsd-3-clause |
secworks/sha256 | src/rtl/sha256_w_mem.v | 8,495 | module MODULE1(
input wire clk,
input wire VAR32,
input wire [511 : 0] VAR39,
input wire VAR30,
input wire VAR13,
output wire [31 : 0] VAR22
);
reg [31 : 0] VAR37 [0 : 15];
reg [31 : 0] VAR11;
reg [31 : 0] VAR5;
reg [31 : 0] VAR34;
reg [31 : 0] VAR16;
reg [31 : 0] VAR10;
reg [31 : 0] VAR19;
reg [31 : 0] VAR4;
reg [31 :... | bsd-2-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai32/gf180mcu_fd_sc_mcu9t5v0__oai32_2.behavioral.v | 3,431 | module MODULE1( VAR8, VAR3, VAR5, VAR7, VAR1, VAR6 );
input VAR5, VAR3, VAR8, VAR6, VAR1;
output VAR7;
VAR4 VAR2(.VAR8(VAR8),.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6));
VAR4 VAR9(.VAR8(VAR8),.VAR3(VAR3),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR6(VAR6)); | apache-2.0 |
alan4186/16bit-Processor | main_memory.v | 7,215 | module MODULE1 (
address,
VAR32,
VAR48,
VAR29,
VAR15);
input [7:0] address;
input VAR32;
input [15:0] VAR48;
input VAR29;
output [15:0] VAR15;
tri1 VAR32;
wire [15:0] VAR22;
wire [15:0] VAR15 = VAR22[15:0];
VAR43 VAR38 (
.VAR12 (address),
.VAR45 (VAR32),
.VAR52 (VAR48),
.VAR18 (VAR29),
.VAR50 (VAR22),
.VAR28 (1'b0),
.V... | mit |
liuyenting/CA-Project | src/L1_Cache_Controller_rework.v | 4,058 | module MODULE1 (
input clk,
input rst,
input VAR4,
input VAR10,
output VAR9,
input VAR2,
output reg VAR1,
input VAR14,
input VAR16,
output reg VAR12,
output reg VAR7,
output reg VAR6,
output reg VAR5,
input VAR17
);
reg [3:0] state;
reg [3:0] VAR3;
reg VAR11; reg VAR13;
reg VAR8;
reg VAR15;
begin
end
begin
end
begin
en... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o21a/sky130_fd_sc_hd__o21a_4.v | 2,248 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR9,
VAR7,
VAR4 ,
VAR5
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR9;
input VAR7;
input VAR4 ;
input VAR5 ;
VAR10 VAR8 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR5(VAR5)
);
endmodule
module MODULE1 (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlygate4sd3/sky130_fd_sc_hs__dlygate4sd3_1.v | 1,992 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1,
VAR5
);
output VAR4 ;
input VAR2 ;
input VAR1;
input VAR5;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR1;
supply0 VAR5;
VAR6 VAR3 (
.VAR4(VAR4),
.VAR2(VAR2)
);
endmodule | apache-2.0 |
gbraad/minimig-de1 | rtl/audio/audio_top.v | 1,614 | module MODULE1 (
input wire clk,
input wire VAR15,
input wire VAR14,
input wire [ 15-1:0] VAR19,
input wire [ 15-1:0] VAR4,
input wire VAR13,
output wire VAR11,
output wire VAR18,
output wire VAR9,
output wire VAR5,
output wire VAR7,
inout VAR1
);
VAR16 VAR16 (
.clk (clk ),
.VAR2 (VAR15 ),
.VAR14 (VAR14 ),
.VAR19 (VAR1... | gpl-3.0 |
vvk/sysrek | skin_color_segm/src/common/DRAM16XN.v | 1,616 | module MODULE1 #(parameter VAR1 = 20)
(
VAR13,
VAR23,
VAR2,
VAR18,
VAR10,
VAR17,
VAR7);
input [VAR1-1:0]VAR13;
input [3:0] VAR23;
input [3:0] VAR2;
input VAR18;
input VAR10;
output [VAR1-1:0]VAR7;
output [VAR1-1:0]VAR17;
genvar VAR21;
generate
for(VAR21 = 0 ; VAR21 < VAR1 ; VAR21 = VAR21 + 1) begin : VAR25
VAR12 VAR6(
... | gpl-2.0 |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/tq/butterfly1_8.v | 2,072 | module MODULE1(
enable,
VAR10,
VAR3,
VAR1,
VAR12,
VAR7,
VAR11,
VAR9,
VAR8,
o0,
o1,
o2,
o3,
o4,
o5,
o6,
o7
);
input enable;
input signed [17:0] VAR10;
input signed [17:0] VAR3;
input signed [17:0] VAR1;
input signed [17:0] VAR12;
input signed [17:0] VAR7;
input signed [17:0] VAR11;
input signed [17:0] VAR9;
input signed... | gpl-3.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/FIR_filters/verilog/fir_pipe_50.v | 34,794 | module MODULE5 (
clk,
reset,
VAR131,
VAR9,
VAR42,
VAR28,
VAR149
);
parameter VAR241 = 18;
parameter VAR261 = 50;
parameter VAR132 = 25;
localparam VAR146 = 57;
input clk;
input reset;
input VAR131;
input VAR9;
input [VAR241-1:0] VAR42; output VAR28;
output [VAR241-1:0] VAR149;
localparam VAR95 = 18; localparam VAR119 =... | mit |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_dataflow/bsg_channel_tunnel_in.v | 3,789 | module MODULE1 #(parameter VAR37(VAR28)
, parameter VAR37(VAR4)
, parameter VAR37(VAR27)
, VAR5 = 0
, VAR19 = 0
, VAR33 = 4
, VAR6 = VAR34(VAR4+1)
, VAR30 = VAR6+VAR28
, VAR26 = VAR34(VAR27+1)
)
(input VAR16
, input VAR3
, input [VAR30-1:0] VAR8
, input VAR12
, output VAR2
, output [VAR4-1:0][VAR28-1:0] VAR7
, output [... | bsd-3-clause |
mrehkopf/sd2snes | verilog/sd2snes_obc1/msu.v | 5,513 | module MODULE1(
input VAR31,
input enable,
input [13:0] VAR37,
input [7:0] VAR46,
input VAR21,
input [2:0] VAR36,
input [7:0] VAR12,
output [7:0] VAR4,
input VAR39,
input VAR20,
input VAR16,
output [7:0] VAR44,
output [7:0] VAR3,
output VAR30,
output [31:0] VAR1,
output [15:0] VAR24,
input [5:0] VAR14,
input [5:0] VAR5... | gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_cx4/cx4_datrom.v | 6,427 | module MODULE1 (
address,
VAR24,
VAR38);
input [9:0] address;
input VAR24;
output [23:0] VAR38;
tri1 VAR24;
wire [23:0] VAR45;
wire [23:0] VAR38 = VAR45[23:0];
VAR32 VAR40 (
.VAR10 (address),
.VAR8 (VAR24),
.VAR31 (VAR45),
.VAR22 (1'b0),
.VAR30 (1'b0),
.VAR49 (1'b1),
.VAR25 (1'b0),
.VAR41 (1'b0),
.VAR15 (1'b1),
.VAR48 ... | gpl-2.0 |
SeanZarzycki/openSPARC-FPU | project/src/fpu_out_dp.v | 6,147 | module MODULE1 (
VAR3,
VAR37,
VAR39,
VAR45,
VAR14,
VAR6,
VAR23,
VAR17,
VAR11,
VAR26,
VAR31,
VAR20,
VAR19,
VAR1,
VAR32,
VAR24,
VAR4,
VAR13,
VAR36,
VAR35,
VAR40,
VAR8,
VAR18,
VAR41,
VAR9,
VAR30,
VAR5,
VAR7,
VAR27,
VAR34
);
input [2:0] VAR3; input [1:0] VAR37; input [4:0] VAR39; input VAR45; input VAR14; input VAR6; input... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_mult_mac.v | 12,399 | module MODULE1(
clk, rst,
VAR18, VAR6, VAR17, VAR43, VAR4, VAR37, VAR10, VAR39, VAR22,
VAR29, VAR46, VAR12, VAR40, VAR1
);
parameter VAR30 = VAR26;
input clk;
input rst;
input VAR18;
input VAR6;
input VAR17;
input [VAR30-1:0] VAR43;
input [VAR30-1:0] VAR4;
input [VAR14-1:0] VAR37;
input [VAR20-1:0] VAR10;
output [VAR30... | gpl-2.0 |
tdaede/daala_zynq | daala_zynq.srcs/sources_1/bd/daala_zynq/ip/daala_zynq_auto_pc_121_0/synth/daala_zynq_auto_pc_121.v | 12,253 | module MODULE1 (
VAR59,
VAR7,
VAR29,
VAR63,
VAR17,
VAR45,
VAR56,
VAR83,
VAR27,
VAR87,
VAR107,
VAR57,
VAR113,
VAR104,
VAR26,
VAR60,
VAR61,
VAR108,
VAR20,
VAR97,
VAR89,
VAR32,
VAR91,
VAR101,
VAR40,
VAR98,
VAR68,
VAR73,
VAR43,
VAR55,
VAR53,
VAR71,
VAR90,
VAR13,
VAR3,
VAR79,
VAR52,
VAR69,
VAR99,
VAR103,
VAR16,
VAR76,
VAR38... | bsd-2-clause |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/adi_common_v1_00_a/hdl/verilog/cf_adc_dma.v | 16,314 | module MODULE1 (
VAR81,
VAR88,
VAR32,
VAR44,
VAR8,
VAR6,
VAR41,
VAR57,
VAR4,
VAR39,
VAR77,
VAR13,
VAR80,
VAR7,
VAR21,
VAR87,
VAR9,
VAR51,
VAR49);
input VAR81;
input VAR88;
input [63:0] VAR32;
input VAR44;
output VAR8;
output [63:0] VAR6;
output [ 7:0] VAR41;
output VAR57;
input VAR4;
output VAR39;
output VAR77;
output ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/bufinv/sky130_fd_sc_lp__bufinv.pp.blackbox.v | 1,259 | module MODULE1 (
VAR4 ,
VAR3 ,
VAR2,
VAR1,
VAR6 ,
VAR5
);
output VAR4 ;
input VAR3 ;
input VAR2;
input VAR1;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
jaechoon2/FPGA-Imaging-Library | LocalFilter/MatchTemplateBin/HDL/MatchTemplateBin.srcs/sources_1/new/MatchTemplateBin.v | 2,847 | module MODULE1(
clk,
VAR5,
VAR9,
VAR7,
VAR10,
VAR1,
VAR4);
parameter[0 : 0] VAR8 = 0;
parameter[3 : 0] VAR3 = 3;
input clk;
input VAR5;
input[VAR3 * VAR3 - 1 : 0] VAR9;
input VAR7;
input [VAR3 * VAR3 - 1 : 0] VAR10;
output VAR1;
output VAR4;
reg VAR6;
reg VAR2;
generate
always @(posedge clk or negedge VAR5 or negedge V... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a2bb2o/sky130_fd_sc_ms__a2bb2o.symbol.v | 1,451 | module MODULE1 (
input VAR5,
input VAR6,
input VAR8 ,
input VAR7 ,
output VAR2
);
supply1 VAR9;
supply0 VAR1;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
cospan/prometheus_fpga | rtl/top.v | 5,510 | module MODULE1(
input VAR45,
input VAR73,
output [3:0] VAR86,
input [3:0] VAR41,
input [1:0] VAR85,
inout [31:0] VAR37,
output VAR62,
output VAR83,
output VAR76,
output VAR70,
output VAR77,
input VAR84,
input VAR24,
input VAR42,
input VAR64,
output [1:0] VAR9
);
wire rst;
wire clk;
reg [3:0] VAR14;
reg [31:0] VAR71;
wi... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/mux2/gf180mcu_fd_sc_mcu7t5v0__mux2_1.behavioral.v | 1,620 | module MODULE1( VAR7, VAR4, VAR6, VAR1 );
input VAR1, VAR4, VAR6;
output VAR7;
VAR2 VAR3(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1));
VAR2 VAR5(.VAR7(VAR7),.VAR4(VAR4),.VAR6(VAR6),.VAR1(VAR1)); | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | Literature FPUs/Lundgren FPU/branches/avendor/pipeline/fpu_addsub.v | 20,865 | module MODULE1( clk, rst, enable, VAR200, VAR153, VAR133, VAR198, out, ready);
input clk;
input rst;
input enable;
input VAR200;
input [1:0] VAR153;
input [63:0] VAR133, VAR198;
output [63:0] out;
output ready;
reg [63:0] VAR195, out;
reg [1:0] VAR176, VAR144, VAR146, VAR96, VAR36, VAR175, VAR41, VAR203, VAR48;
reg [1:... | gpl-3.0 |
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