repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
skatpgusskat/KoreaUnivHomework_2015_1 | Computer Architecture/Homework/Lab09/control_units.v | 2,749 | module MODULE2(clk, VAR16, VAR8, VAR9, VAR4, VAR18, VAR5, VAR6, VAR1, VAR12, VAR11, VAR15, VAR7, VAR3, VAR2, VAR13);
input clk, VAR16;
input [5:0] VAR8;
output VAR9, VAR4, VAR18, VAR5, VAR6, VAR1, VAR12, VAR3, VAR2, VAR13;
reg VAR9, VAR4, VAR18, VAR5, VAR6, VAR1, VAR12, VAR3, VAR2, VAR13;
output [1:0] VAR11, VAR15, VAR... | mit |
nyaxt/dmix | async_fifo_t.v | 1,122 | module MODULE1;
reg VAR7;
reg VAR9;
reg [7:0] VAR3;
reg VAR4;
reg VAR6;
reg VAR10;
reg VAR11;
VAR8 VAR1(
.VAR7(VAR7), .VAR9(VAR9), .VAR3(VAR3), .VAR4(VAR4),
.VAR6(VAR6), .VAR10(VAR10), .VAR11(VAR11));
parameter VAR2 = 10;
parameter VAR5 = 24;
always #(VAR2/2) VAR7 = ~VAR7;
always #(VAR5/2) VAR6 = ~VAR6; | mit |
C-L-G/azpr_soc | azpr_soc/trunk/ic/digital/rtl/cpu/gpr.v | 5,487 | module MODULE1(
input wire clk ,
input wire reset ,
input wire [VAR15] VAR6 , output wire [VAR1] VAR5 , input wire [VAR15] VAR4 , output wire [VAR1] VAR9 , input wire VAR17 , input wire [VAR8] VAR12 , input wire [VAR1] VAR7 );
reg [VAR1] MODULE1 [VAR3-1:0];
integer VAR2;
assign VAR5 = ((VAR17 == VAR11) && (VAR12 == VAR... | apache-2.0 |
disaderp/automatic-chainsaw | GPU/GPU.v | 2,526 | module MODULE1(
input clk,
input [15:0] VAR10,
input VAR21,
output VAR17, output VAR28, output VAR15
);
wire [7:0] out;
wire [9:0] VAR20; wire [9:0] VAR5;
reg [15:0] VAR7 = 0;
reg [15:0] VAR23 = 0;
reg [7:0] VAR9 [11:0];
reg [11:0] VAR11 = 0;
reg [11:0] VAR8 = 0;
reg [11:0] VAR30 = 0;
reg VAR6 = 0;
reg [15:0] VAR27 = 0... | gpl-3.0 |
ammelto/FPGAdventure | Adventure/BlackKeyRoom.v | 1,194 | module MODULE1(VAR1, VAR4, VAR3, VAR6, VAR2);
input VAR1;
input [9:0]VAR4;
input [8:0]VAR3;
input [7:0]VAR2;
output [7:0]VAR6;
reg [7:0]VAR5;
always @(posedge VAR1) begin
if(((VAR3 < 40) && (VAR4 < 260)) || ((VAR3 < 40) && ~(VAR4 < 380))) begin
VAR5[7:0] <= VAR2;
end
else if(VAR4 < 40) begin
VAR5[7:0] <= VAR2;
end
else... | mit |
The-OpenROAD-Project/asap7 | asap7sc6t_26/Verilog/asap7sc6T_INVBUF_SRAM_FF_210930.v | 14,992 | module MODULE1 (VAR1, VAR2);
output VAR1;
input VAR2;
buf (VAR1, VAR2); | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a22oi/sky130_fd_sc_hd__a22oi.behavioral.v | 1,641 | module MODULE1 (
VAR6 ,
VAR7,
VAR16,
VAR15,
VAR11
);
output VAR6 ;
input VAR7;
input VAR16;
input VAR15;
input VAR11;
supply1 VAR5;
supply0 VAR8;
supply1 VAR3 ;
supply0 VAR12 ;
wire VAR2 ;
wire VAR1 ;
wire VAR10;
nand VAR14 (VAR2 , VAR16, VAR7 );
nand VAR4 (VAR1 , VAR11, VAR15 );
and VAR13 (VAR10, VAR2, VAR1);
buf VAR9... | apache-2.0 |
YingcaiDong/Shunting-Model-Based-Path-Planning-Algorithm-Accelerator-Using-FPGA | System Design Source FIle/ipshared/xilinx.com/HLS_accel_v1_0/dbdcd11c/hdl/verilog/HLS_accel_fmul_32ns_32ns_32_4_max_dsp.v | 1,991 | module MODULE1
VAR20 = 3,
VAR19 = 4,
VAR12 = 32,
VAR22 = 32,
VAR21 = 32
)(
input wire clk,
input wire reset,
input wire VAR15,
input wire [VAR12-1:0] VAR5,
input wire [VAR22-1:0] VAR24,
output wire [VAR21-1:0] dout
);
wire VAR6;
wire VAR7;
wire VAR1;
wire [31:0] VAR8;
wire VAR16;
wire [31:0] VAR18;
wire VAR23;
wire [31... | mit |
KestrelComputer/gpia3 | rtl/verilog/GPIA_BYTE.v | 1,497 | module MODULE1(
input VAR1,
input VAR5,
input [1:0] VAR4,
input [7:0] VAR6,
input VAR11,
output [7:0] VAR15
);
VAR3 VAR7(
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6[0]),
.VAR11(VAR11),
.VAR15(VAR15[0])
);
VAR3 VAR12(
.VAR1(VAR1),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6[1]),
.VAR11(VAR11),
.VAR15(VAR15[1])
);
VAR3 V... | mpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dlyb/gf180mcu_fd_sc_mcu7t5v0__dlyb_1.behavioral.pp.v | 1,164 | module MODULE1( VAR3, VAR2, VAR4, VAR1 );
input VAR3;
inout VAR4, VAR1;
output VAR2;
VAR7 VAR5(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1));
VAR7 VAR6(.VAR3(VAR3),.VAR2(VAR2),.VAR4(VAR4),.VAR1(VAR1)); | apache-2.0 |
jotego/jt12 | hdl/jt12_csr.v | 2,860 | module MODULE1( input rst,
input clk,
input VAR8 ,
input [ 7:0] din,
input [43:0] VAR7,
output [43:0] VAR25,
input VAR4,
input VAR12,
input VAR18,
input VAR22,
input VAR17,
input VAR13,
input VAR1,
input VAR24,
input VAR11,
input VAR9
);
localparam VAR30=44;
reg [VAR30-1:0] VAR29;
VAR16 #(.VAR14(VAR30),.VAR26(12)) VAR1... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21boi/sky130_fd_sc_hd__a21boi_4.v | 2,332 | module MODULE2 (
VAR9 ,
VAR6 ,
VAR3 ,
VAR8,
VAR7,
VAR5,
VAR10 ,
VAR4
);
output VAR9 ;
input VAR6 ;
input VAR3 ;
input VAR8;
input VAR7;
input VAR5;
input VAR10 ;
input VAR4 ;
VAR2 VAR1 (
.VAR9(VAR9),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODULE2 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4bb/sky130_fd_sc_hs__and4bb.pp.blackbox.v | 1,298 | module MODULE1 (
VAR7 ,
VAR4 ,
VAR2 ,
VAR1 ,
VAR6 ,
VAR5,
VAR3
);
output VAR7 ;
input VAR4 ;
input VAR2 ;
input VAR1 ;
input VAR6 ;
input VAR5;
input VAR3;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o41ai/sky130_fd_sc_ls__o41ai.pp.symbol.v | 1,381 | module MODULE1 (
input VAR2 ,
input VAR7 ,
input VAR3 ,
input VAR8 ,
input VAR5 ,
output VAR9 ,
input VAR6 ,
input VAR4,
input VAR10,
input VAR1
);
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/commutator.v | 2,316 | module MODULE1
(input VAR45,
input [15:0] VAR38,
input [15:0] VAR12,
input [31:0] VAR25, output [47:0] VAR48);
wire [10:0] VAR22, VAR26, VAR41;
VAR6 #(11) VAR28
(.VAR45(VAR45), .VAR49(VAR38[10:0] + VAR12[10:0] ), .VAR13(VAR22));
VAR6 #(11) VAR8
(.VAR45(VAR45), .VAR49(VAR38[10:0] + VAR12[10:0] + 11'd683 ), .VAR13(VAR26)... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd2/sky130_fd_sc_ls__tapvgnd2_1.v | 1,950 | module MODULE2 (
VAR1,
VAR6,
VAR2 ,
VAR3
);
input VAR1;
input VAR6;
input VAR2 ;
input VAR3 ;
VAR5 VAR4 (
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR3(VAR3)
);
endmodule
module MODULE2 ();
supply1 VAR1;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR3 ;
VAR5 VAR4 ();
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xor3/sky130_fd_sc_hs__xor3.pp.symbol.v | 1,282 | module MODULE1 (
input VAR2 ,
input VAR3 ,
input VAR6 ,
output VAR5 ,
input VAR1,
input VAR4
);
endmodule | apache-2.0 |
PiJoules/Zybo-Vision-Processing | hdmi_passthrough_720p.srcs/sources_1/bd/design_1/ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0_clk_wiz.v | 5,849 | module MODULE1
( input VAR53,
output VAR13,
input reset,
output VAR3
);
VAR8 VAR27
(.VAR60 (VAR29),
.VAR5 (VAR53));
wire [15:0] VAR10;
wire VAR52;
wire VAR11;
wire VAR55;
wire VAR35;
wire VAR25;
wire VAR51;
wire VAR44;
wire VAR40;
wire VAR32;
wire VAR56;
wire VAR19;
wire VAR20;
wire VAR41;
wire VAR31;
wire VAR45;
VAR37... | unlicense |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_comm_link/bsg_comm_link.v | 34,564 | module MODULE1
, parameter VAR140(VAR50 )
, parameter VAR140(VAR192 )
, parameter VAR140(VAR70 ) , parameter VAR140(VAR29 )
, parameter VAR202=(1 << (VAR192))-1
, parameter VAR112 = 100
, parameter VAR208 = (VAR70) ' (0)
, parameter VAR199 = 1'b1
, parameter VAR67 = 1'b1
, parameter VAR278 = (VAR70) ' (0)
, parameter V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlrtn/sky130_fd_sc_ls__dlrtn.pp.blackbox.v | 1,385 | module MODULE1 (
VAR7 ,
VAR1,
VAR2 ,
VAR5 ,
VAR8 ,
VAR4 ,
VAR6 ,
VAR3
);
output VAR7 ;
input VAR1;
input VAR2 ;
input VAR5 ;
input VAR8 ;
input VAR4 ;
input VAR6 ;
input VAR3 ;
endmodule | apache-2.0 |
KorotkiyEugene/LAG_sv_syn_quartus | LAG_pl_unrestricted_allocator.v | 5,564 | module MODULE1 (req, VAR24, VAR1, VAR28, VAR19, VAR26, clk, VAR13);
parameter VAR35 = 4;
parameter VAR25=4;
parameter VAR11=4;
parameter VAR29=5;
parameter VAR39=4;
parameter VAR6 = 1;
input [VAR29-1:0][VAR39-1:0] req;
input VAR36 VAR24 [VAR29-1:0][VAR39-1:0];
input [VAR29-1:0][VAR39-1:0] VAR1;
output [VAR29-1:0][VAR39... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlrbn/sky130_fd_sc_hd__dlrbn.pp.symbol.v | 1,458 | module MODULE1 (
input VAR1 ,
output VAR8 ,
output VAR7 ,
input VAR3,
input VAR2 ,
input VAR6 ,
input VAR4 ,
input VAR9 ,
input VAR5
);
endmodule | apache-2.0 |
azonenberg/yosys | passes/techmap/adder_untechmap.v | 1,137 | module MODULE2 (input VAR16, input VAR6, input VAR17, output VAR1, output VAR18);
VAR11 VAR15 (
.VAR16(VAR16),
.VAR6(VAR6),
.VAR2(VAR17),
.VAR1(VAR1),
);
VAR12 VAR19 (
.VAR16(VAR16),
.VAR6(VAR6),
.VAR2(VAR17),
.VAR1(VAR18),
);
endmodule
module MODULE1 (input VAR16, input VAR6, output VAR1, output VAR18);
VAR7 VAR13 (
.... | isc |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlrbn/sky130_fd_sc_hs__dlrbn_1.v | 2,338 | module MODULE1 (
VAR8,
VAR4 ,
VAR6 ,
VAR3 ,
VAR5 ,
VAR7 ,
VAR9
);
input VAR8;
input VAR4 ;
input VAR6 ;
output VAR3 ;
output VAR5 ;
input VAR7 ;
input VAR9 ;
VAR2 VAR1 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR9(VAR9)
);
endmodule
module MODULE1 (
VAR8,
VAR4 ,
VAR6 ,
VAR3 ,
VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxbn/sky130_fd_sc_lp__dlxbn.blackbox.v | 1,339 | module MODULE1 (
VAR6 ,
VAR8 ,
VAR5 ,
VAR2
);
output VAR6 ;
output VAR8 ;
input VAR5 ;
input VAR2;
supply1 VAR4;
supply0 VAR1;
supply1 VAR7 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_dmac/axi_register_slice.v | 4,475 | module MODULE1 (
input clk,
input VAR11,
input VAR19,
output VAR4,
input [VAR13-1:0] VAR7,
output VAR10,
input VAR17,
output [VAR13-1:0] VAR20
);
parameter VAR13 = 32;
parameter VAR1 = 0;
parameter VAR9 = 0;
wire [VAR13-1:0] VAR12;
wire VAR16;
wire VAR3;
wire [VAR13-1:0] VAR15;
wire VAR14;
wire VAR18;
generate if (VAR1... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/ddr_controller/spartan3/rtl/r_w_dly.v | 4,246 | module MODULE1 (
VAR5,
VAR13,
VAR10,
VAR11,
VAR7,
VAR9,
VAR6,
VAR1
);
input VAR5;
input VAR13;
input VAR10;
input VAR11;
input VAR7;
output VAR9;
output VAR1;
output VAR6;
reg [4:0] VAR2;
reg VAR12;
reg VAR3;
reg VAR4;
reg VAR8;
assign VAR9 = VAR3;
assign VAR1 = VAR4;
assign VAR6 = VAR8;
always @ (posedge VAR5)
begin
i... | lgpl-3.0 |
cpulabs/mist1032sa | src/lib/mist1032sa_async_fifo.v | 3,798 | module MODULE1
parameter VAR21 = 16,
parameter VAR12 = 4,
parameter VAR27 = 2
)
(
input wire VAR7,
input wire VAR13,
input wire VAR5,
input wire VAR4,
input wire [VAR21-1:0] VAR18,
output wire VAR8,
input wire VAR28,
input wire VAR22,
output wire [VAR21-1:0] VAR25,
output wire VAR34
);
wire [VAR27:0] VAR26;
wire VAR35;... | bsd-2-clause |
sorgelig/Apogee_MIST | sram.v | 9,573 | module MODULE1 (
inout reg [15:0] VAR44, output reg [12:0] VAR52, output reg VAR25, output reg VAR60, output reg [1:0] VAR9, output VAR40, output VAR53, output VAR23, output VAR15, output VAR42,
input VAR5, input VAR47,
input [24:0] addr,
output reg [7:0] dout, input [7:0] din, input VAR29, input rd, output reg ready
)... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32oi/sky130_fd_sc_hd__a32oi.pp.symbol.v | 1,440 | module MODULE1 (
input VAR7 ,
input VAR1 ,
input VAR9 ,
input VAR6 ,
input VAR5 ,
output VAR8 ,
input VAR3 ,
input VAR10,
input VAR4,
input VAR2
);
endmodule | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/vfabric_barrier.v | 4,056 | module MODULE1(VAR8, VAR48, VAR54, VAR1, VAR41,
VAR3, VAR14, VAR42,
VAR29, VAR55, VAR26, VAR50, VAR34, VAR43,
VAR49, VAR5, VAR24, VAR27, VAR22, VAR2);
parameter VAR16 = 1;
parameter VAR25 = 4;
parameter VAR38 = 64;
parameter VAR17 = 4;
parameter VAR32 = 10;
input VAR8, VAR48;
input [VAR16-1:0] VAR54;
input [VAR16-1:0] ... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/projects/common/a5gte/system_top.v | 3,998 | module MODULE1 (
VAR19,
VAR13,
VAR3,
VAR4,
VAR17,
VAR14,
VAR12,
VAR16,
VAR21,
VAR1,
VAR8,
VAR20,
VAR2,
VAR18,
VAR6,
VAR11,
VAR15,
VAR9,
VAR7,
VAR5);
output VAR19;
output VAR13;
output [ 3:0] VAR3;
input VAR4;
input VAR17;
input [ 3:0] VAR14;
input VAR12;
output VAR16;
input VAR21;
input VAR1;
input VAR8;
output VAR20;
... | gpl-3.0 |
mbus/mbus | m3_mbus_releases/r04p2g/source/lname_mbus_member_ctrl.tsmc180.v | 10,278 | module MODULE1 (
input VAR88,
input VAR68,
input VAR116,
input VAR51,
input VAR16,
output VAR107,
output VAR19,
input VAR85,
input VAR25,
output VAR8,
output VAR103,
output VAR22,
output VAR32,
output VAR111,
output VAR33,
input VAR13,
output VAR101,
input VAR40,
input VAR77,
input [3:0] VAR17,
output [3:0] VAR91,
outp... | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_idelay_ctrl.v | 3,617 | module MODULE1 #
(
parameter VAR3 = "VAR2"
)
(
input VAR5,
input VAR4,
output VAR1
);
assign VAR1 = 1'b1;
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai.functional.v | 1,592 | module MODULE1 (
VAR10 ,
VAR13,
VAR9,
VAR11,
VAR4,
VAR3
);
output VAR10 ;
input VAR13;
input VAR9;
input VAR11;
input VAR4;
input VAR3;
wire VAR12 ;
wire VAR5 ;
wire VAR7;
or VAR6 (VAR12 , VAR4, VAR11 );
or VAR1 (VAR5 , VAR9, VAR13 );
nand VAR2 (VAR7, VAR5, VAR12, VAR3);
buf VAR8 (VAR10 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111a/sky130_fd_sc_ms__o2111a.blackbox.v | 1,394 | module MODULE1 (
VAR4 ,
VAR5,
VAR10,
VAR7,
VAR3,
VAR9
);
output VAR4 ;
input VAR5;
input VAR10;
input VAR7;
input VAR3;
input VAR9;
supply1 VAR8;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or4/sky130_fd_sc_hs__or4.pp.symbol.v | 1,258 | module MODULE1 (
input VAR5 ,
input VAR6 ,
input VAR1 ,
input VAR4 ,
output VAR2 ,
input VAR3,
input VAR7
);
endmodule | apache-2.0 |
jeichenhofer/chuck-light | SoC/soc_system/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,039 | module MODULE1
(
VAR6,
VAR14,
VAR15) ;
input [0:0] VAR6;
output [0:0] VAR14;
output [0:0] VAR15;
wire [0:0] VAR29;
wire [0:0] VAR31;
wire [0:0] VAR3;
wire [0:0] VAR8;
wire [0:0] VAR30;
wire [0:0] VAR10;
wire [0:0] VAR4;
wire [0:0] VAR11;
wire [0:0] VAR35;
wire [0:0] VAR23;
VAR1 VAR16
(
.VAR17(VAR10),
.VAR26(VAR29[0:0])... | gpl-3.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/synthesis/submodules/Video_System_Video_Scaler.v | 8,029 | module MODULE1 (
clk,
reset,
VAR24,
VAR14,
VAR9,
VAR30,
VAR12,
VAR2,
VAR16,
VAR19,
VAR8,
VAR10,
VAR11,
VAR21
);
parameter VAR17 = 15; parameter VAR32 = 0;
parameter VAR31 = 9; parameter VAR27 = 7; parameter VAR13 = 640;
parameter VAR23 = 4'b0101;
parameter VAR1 = 4'b0000;
parameter VAR28 = 8; parameter VAR5 = 320; para... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai222/gf180mcu_fd_sc_mcu7t5v0__oai222_2.behavioral.v | 7,158 | module MODULE1( VAR2, VAR5, VAR7, VAR1, VAR10, VAR6, VAR9 );
input VAR6, VAR9, VAR1, VAR10, VAR5, VAR7;
output VAR2;
VAR3 VAR8(.VAR2(VAR2),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR10(VAR10),.VAR6(VAR6),.VAR9(VAR9));
VAR3 VAR4(.VAR2(VAR2),.VAR5(VAR5),.VAR7(VAR7),.VAR1(VAR1),.VAR10(VAR10),.VAR6(VAR6),.VAR9(VAR9)); | apache-2.0 |
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC | bin_Gray_Processing/ip/Gray_Processing/acl_fp_custom_add_op_double.v | 2,476 | module MODULE1( VAR12, VAR11, VAR5, VAR1, VAR18, VAR16, VAR3,
VAR19, VAR14, VAR17,
VAR13, VAR4, VAR6, VAR10, enable);
parameter VAR8 = 1;
input VAR12, VAR11, VAR18, VAR16;
input [55:0] VAR5;
input [55:0] VAR1;
input [11:0] VAR3;
input VAR13, VAR6, enable;
output reg [56:0] VAR19;
output reg [11:0] VAR14;
output reg VAR... | mit |
rbarzic/async_logic | async_lib/single_rail_2ph/arbitrer_r1_2ph/arbitrer_r1_2ph.v | 2,448 | module MODULE1(
VAR11, VAR4, VAR2, VAR32,
VAR3, VAR37, VAR13, VAR36, VAR26
);
input VAR3;
output VAR11;
input VAR37;
output VAR4;
output VAR2;
input VAR13;
output VAR32;
input VAR36;
input VAR26;
wire VAR6, VAR42;
wire VAR22,VAR9;
wire VAR17,VAR30;
wire VAR21, VAR28;
VAR25 VAR29(.VAR10(!VAR21),
.VAR31(VAR3),
.VAR26(VAR... | gpl-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo19_to_ll8.v | 1,895 | module MODULE1
(input clk, input reset, input VAR11,
input [18:0] VAR4,
input VAR12,
output VAR18,
output reg [7:0] VAR9,
output VAR17,
output VAR6,
output VAR15,
input VAR7);
wire VAR14, VAR16, VAR8;
assign VAR17 = ~VAR14;
assign VAR6 = ~VAR16;
assign VAR15 = ~VAR8;
wire VAR3 = ~VAR7;
wire VAR13 = VAR4[16];
wire VAR10... | gpl-2.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/or1200_dc_top_wrapper.v | 8,722 | module MODULE1(
clk, rst,
VAR41, VAR43, VAR10, VAR16, VAR31, VAR25, VAR52,
VAR11, VAR45, VAR42,
VAR37,
VAR36, VAR44, VAR53,
VAR22, VAR14, VAR54, VAR7,
VAR56, VAR30, VAR51, VAR35, VAR23,
VAR39, VAR49, VAR26,
VAR28, VAR13, VAR8
);
parameter VAR17 = VAR5;
input clk;
input rst;
output [VAR17-1:0] VAR41;
output [31:0] VAR43... | gpl-3.0 |
google/myelin-acorn-electron-hardware | bga_in_two_layers/10m04_cpu_socket/internal_flash/synthesis/submodules/altera_onchip_flash.v | 11,127 | module MODULE1 (
VAR50,
VAR107,
VAR96,
VAR110,
VAR69,
VAR120,
VAR88,
VAR11,
VAR112,
VAR12,
VAR17,
VAR30,
VAR13,
VAR117,
VAR74
);
parameter VAR73 = "VAR47 10";
parameter VAR56 = "VAR95";
parameter VAR3 = "VAR60";
parameter VAR39 = "VAR60";
parameter VAR7 = "VAR60";
parameter VAR108 = "";
parameter VAR109 = "08";
paramet... | apache-2.0 |
ncos/Xilinx-Verilog | INTERFACES/src/ARINC429/reciever.v | 3,670 | module MODULE1(
input clk, input VAR9, input VAR4, output [22:0] VAR16, output [7:0] VAR7, output VAR5 );
parameter VAR11 = 50000000; parameter VAR19 = 100000; parameter VAR14 = 50000; parameter VAR18 = 12500; parameter VAR21 = VAR11/VAR19; parameter VAR10 = VAR11/VAR14;
parameter VAR13 = VAR11/VAR18;
reg [31:0]VAR20 =... | mit |
VerticalResearchGroup/miaow | scripts/xilinx/axi_slave_v1_0.v | 3,340 | module MODULE1 #
(
parameter integer VAR10 = 32,
parameter integer VAR35 = 11
)
(
output wire VAR40,
output wire VAR15,
output wire [VAR35-1 : 0] VAR8,
output wire [2 : 0] VAR31,
output wire VAR19,
input wire VAR7,
output wire [VAR10-1 : 0] VAR44,
output wire [(VAR10/8)-1 : 0] VAR12,
output wire VAR30,
input wire VAR1,... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fa/sky130_fd_sc_ls__fa.functional.v | 1,881 | module MODULE1 (
VAR4,
VAR13 ,
VAR12 ,
VAR9 ,
VAR1
);
output VAR4;
output VAR13 ;
input VAR12 ;
input VAR9 ;
input VAR1 ;
wire VAR7 ;
wire VAR6 ;
wire VAR10 ;
wire VAR19 ;
wire VAR3 ;
wire VAR17 ;
wire VAR23;
wire VAR15 ;
or VAR11 (VAR7 , VAR1, VAR9 );
and VAR16 (VAR6 , VAR7, VAR12 );
and VAR18 (VAR10 , VAR9, VAR1 );
o... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand4/gf180mcu_fd_sc_mcu9t5v0__nand4_4.functional.pp.v | 1,416 | module MODULE1( VAR6, VAR11, VAR13, VAR4, VAR14, VAR3, VAR16 );
input VAR14, VAR4, VAR6, VAR13;
inout VAR3, VAR16;
output VAR11;
wire VAR2;
not VAR15( VAR2, VAR14 );
wire VAR7;
not VAR1( VAR7, VAR4 );
wire VAR12;
not VAR10( VAR12, VAR6 );
wire VAR5;
not VAR8( VAR5, VAR13 );
or VAR9( VAR11, VAR2, VAR7, VAR12, VAR5 );
en... | apache-2.0 |
walkthetalk/fsref | ip/axis_interconnector/src/axis_interconnector.v | 9,627 | module MODULE1 #
(
parameter integer VAR42 = 8,
parameter integer VAR40 = 8,
parameter integer VAR73 = 8,
parameter integer VAR21 = 0
)
(
input wire clk,
input wire VAR29,
input wire VAR3,
input wire [VAR42-1:0] VAR67,
input wire VAR19,
input wire VAR58,
output wire VAR108,
input wire [VAR73-1:0] VAR87,
output wire VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.symbol.v | 1,332 | module MODULE1 (
input VAR1 ,
output VAR4,
input VAR3 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4/sky130_fd_sc_ls__nand4.behavioral.v | 1,408 | module MODULE1 (
VAR6,
VAR5,
VAR10,
VAR4,
VAR7
);
output VAR6;
input VAR5;
input VAR10;
input VAR4;
input VAR7;
supply1 VAR3;
supply0 VAR2;
supply1 VAR12 ;
supply0 VAR11 ;
wire VAR1;
nand VAR8 (VAR1, VAR7, VAR4, VAR10, VAR5 );
buf VAR9 (VAR6 , VAR1 );
endmodule | apache-2.0 |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_18to36.v | 5,396 | module MODULE1(
rst,
VAR93,
VAR74,
din,
VAR10,
VAR92,
dout,
VAR79,
VAR18,
VAR41,
VAR5);
input rst;
input VAR93;
input VAR74;
input [17 : 0] din;
input VAR10;
input VAR92;
output [35 : 0] dout;
output VAR79;
output VAR18;
output VAR41;
output VAR5;
VAR68 #(
.VAR15(0),
.VAR81(0),
.VAR24(10),
.VAR26("VAR77"),
.VAR51(18),
... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp.pp.symbol.v | 1,410 | module MODULE1 (
input VAR5 ,
output VAR8 ,
input VAR3,
input VAR1 ,
input VAR7 ,
input VAR6 ,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/dlymetal6s4s/sky130_fd_sc_ls__dlymetal6s4s_1.v | 2,160 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4,
VAR8,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR6 ;
input VAR5 ;
VAR2 VAR7 (
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR5(VAR5)
);
endmodule
module MODULE1 (
VAR1,
VAR3
);
output VAR1;
input VAR3;
supply1 VAR4;
supply0 VAR8;... | apache-2.0 |
alexforencich/verilog-ethernet | rtl/iddr.v | 4,130 | module MODULE1 #
(
parameter VAR44 = "VAR33",
parameter VAR17 = "VAR30",
parameter VAR20 = 1
)
(
input wire clk,
input wire [VAR20-1:0] VAR7,
output wire [VAR20-1:0] VAR34,
output wire [VAR20-1:0] VAR5
);
genvar VAR26;
generate
if (VAR44 == "VAR31") begin
for (VAR26 = 0; VAR26 < VAR20; VAR26 = VAR26 + 1) begin : MODULE... | mit |
HectorTorres/Verilog-ceti-tonala | S4/S4A2.v | 2,009 | module MODULE1(VAR5, VAR9, VAR12, VAR4,VAR2);
input VAR5; output reg VAR9; output reg [6:0] VAR12 = 7'h3F; output reg [3:0] VAR4 = 4'h0; output reg [3:0] VAR2 = 0; reg [25:0] VAR1 = 0; reg [25:0] VAR10 = 0;
reg VAR14 = 0;
reg [3:0] VAR8 = 0; reg [3:0] VAR6 = 0;
parameter [6:0] VAR3 = ~7'h3F;
parameter [6:0] VAR7 = ~7'h... | unlicense |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/buf/sky130_fd_sc_hvl__buf.functional.v | 1,227 | module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
wire VAR5;
buf VAR1 (VAR5, VAR4 );
buf VAR2 (VAR3 , VAR5 );
endmodule | apache-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/C5G/CPC2_C5G.v | 4,042 | module MODULE1(
VAR42,
VAR41,
VAR75,
VAR9,
VAR33,
VAR22,
VAR29,
VAR49,
VAR16,
VAR3,
VAR66,
VAR70,
VAR39,
VAR21,
VAR36,
VAR24,
VAR30,
VAR26,
VAR25,
VAR71,
VAR14,
VAR73,
VAR31,
VAR58,
VAR78,
VAR55,
VAR27,
VAR11,
VAR56,
VAR79,
VAR67,
VAR57,
VAR52,
VAR68,
VAR48,
VAR37,
VAR4
);
input VAR42;
input VAR41;
input VAR75;
input V... | gpl-3.0 |
mammenx/pegasus | wxp/dgn/rtl/l2/mac/peg_l2_mac_rx.v | 4,563 | module MODULE1 #(
parameter VAR5 = 8,
parameter VAR10 = 16,
parameter VAR1 = 8,
parameter VAR22 = 48
)
(
input clk,
input VAR15,
output VAR25,
);
wire [VAR1-1:0] VAR32;
wire [VAR22-1:0] VAR28;
wire VAR3;
wire VAR33;
wire [VAR5-1:0] VAR4;
VAR34 #(
.VAR5(VAR5),
.VAR10(VAR10),
.VAR1(VAR1),
.VAR22(VAR22)
)
VAR39
(
.clk (cl... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/einvp/sky130_fd_sc_ms__einvp_1.v | 2,130 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4 ,
VAR9,
VAR3,
VAR8 ,
VAR7
);
output VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR9;
input VAR3;
input VAR8 ;
input VAR7 ;
VAR6 VAR5 (
.VAR1(VAR1),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR9(VAR9),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR1 ,
VAR2 ,
VAR4
);
output VAR1... | apache-2.0 |
yipenghuang0302/csee4840_14 | software/peripheral/db/ip/ik_swift/submodules/altera_reset_synchronizer.v | 3,481 | module MODULE1
parameter VAR5 = 1,
parameter VAR3 = 2
)
(
input VAR4 ,
input clk,
output VAR1
);
reg [VAR3-1:0] VAR2;
reg VAR6;
generate if (VAR5) begin
always @(posedge clk or posedge VAR4) begin
if (VAR4) begin
VAR2 <= {VAR3{1'b1}};
VAR6 <= 1'b1;
end
else begin
VAR2[VAR3-2:0] <= VAR2[VAR3-1:1];
VAR2[VAR3-1] <= 0;
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_pg/sky130_fd_sc_hs__udp_dff_p_pp_pg.symbol.v | 1,364 | module MODULE1 (
input VAR4 ,
output VAR2 ,
input VAR5 ,
input VAR1,
input VAR3
);
endmodule | apache-2.0 |
rkrajnc/minimig-mist | rtl/minimig/paula_audio_channel.v | 11,424 | module MODULE1
(
input clk, input VAR12,
input VAR53, input reset, input VAR51, input VAR50, input [3:1] VAR15, input [15:0] VAR7, output [6:0] VAR27, output [7:0] VAR9, output VAR19, input VAR41, output reg VAR26, output reg VAR25, input VAR52 );
parameter VAR13 = 4'h4;
parameter VAR28 = 4'h6;
parameter VAR30 = 4'h8;
... | gpl-3.0 |
UCR-CS179-SUMMER2014/NES_FPGA | source/NES_FPGA/nios_system/synthesis/submodules/nios_system_CPU_jtag_debug_module_tck.v | 8,185 | module MODULE1 (
VAR21,
VAR31,
VAR17,
VAR29,
VAR4,
VAR22,
VAR20,
VAR24,
VAR7,
VAR1,
VAR19,
VAR37,
VAR35,
VAR36,
VAR18,
VAR10,
VAR5,
VAR12,
VAR14,
VAR38,
VAR34,
VAR33,
VAR25,
VAR30,
VAR9,
VAR2,
VAR3,
VAR8,
VAR6,
VAR39,
VAR23
)
;
output [ 1: 0] VAR3;
output VAR8;
output [ 37: 0] VAR6;
output VAR39;
output VAR23;
input [ ... | mit |
Ribeiro/sd2snes | verilog/sd2sneslite/spi.v | 3,109 | module MODULE1(
input clk,
input VAR6,
input VAR2,
inout VAR24,
input VAR12,
output VAR21,
output VAR26,
output [7:0] VAR9,
output [7:0] VAR25,
input [7:0] VAR16,
output [31:0] VAR17,
output [2:0] VAR3
);
reg [7:0] VAR27;
reg [7:0] VAR20;
reg [2:0] VAR22;
reg [2:0] VAR5;
always @(posedge clk) VAR22 <= {VAR22[1:0], VAR1... | gpl-2.0 |
fpgasystems/caribou | hw/src/net/rx_interface.v | 21,447 | module MODULE1 #(
parameter VAR75 = 11
)
(
input [63:0] VAR65,
input [7:0] VAR40,
input VAR33,
input VAR45,
input VAR15,
input VAR29,
output [63:0] VAR27,
output [7:0] VAR5,
output VAR14,
output VAR70,
output [15:0] VAR39,
output reg VAR63 = 1'b0,
input [29:0] VAR77,
input VAR57,
output [VAR75-1:0] VAR36 ,
input VAR23,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a31o/sky130_fd_sc_hs__a31o.functional.v | 1,918 | module MODULE1 (
VAR9,
VAR4,
VAR11 ,
VAR14 ,
VAR6 ,
VAR13 ,
VAR2
);
input VAR9;
input VAR4;
output VAR11 ;
input VAR14 ;
input VAR6 ;
input VAR13 ;
input VAR2 ;
wire VAR2 VAR12 ;
wire VAR7 ;
wire VAR5;
and VAR15 (VAR12 , VAR13, VAR14, VAR6 );
or VAR10 (VAR7 , VAR12, VAR2 );
VAR1 VAR3 (VAR5, VAR7, VAR9, VAR4);
buf VAR8 ... | apache-2.0 |
hj3938/FPGA-Imaging-Library | LocalFilter/ThresholdLocal/HDL/ThresholdLocal.srcs/sources_1/new/ThresholdLocal.v | 4,319 | module MODULE1(
clk,
VAR1,
VAR2,
VAR10,
VAR8,
VAR3,
VAR12,
VAR7);
parameter[0 : 0] VAR14 = 0;
parameter[3 : 0] VAR5 = 1;
parameter[3 : 0] VAR18 = 8;
parameter VAR13 = 8;
parameter VAR11 = 4;
input clk;
input VAR1;
input VAR2;
input [VAR18 * VAR5 * VAR5 - 1 : 0] VAR10;
input VAR8;
input[VAR18 - 1 : 0] VAR3;
output VAR12... | lgpl-2.1 |
bluespec/Flute | builds/RV64ACDFIMSU_Flute_verilator/Verilog_RTL/mkGPR_RegFile.v | 6,924 | module MODULE1(VAR30,
VAR1,
VAR62,
VAR70,
VAR55,
VAR17,
VAR5,
VAR44,
VAR13,
VAR46,
VAR2,
VAR58,
VAR26,
VAR51,
VAR39);
input VAR30;
input VAR1;
input VAR62;
output VAR70;
input VAR55;
output VAR17;
input [4 : 0] VAR5;
output [63 : 0] VAR44;
input [4 : 0] VAR13;
output [63 : 0] VAR46;
input [4 : 0] VAR2;
output [63 : 0] ... | apache-2.0 |
nyaxt/dmix | nkmdhpa.v | 22,654 | module MODULE1#(
parameter VAR98 = 2,
parameter VAR214 = 1,
parameter VAR420 = 5,
parameter VAR204 = VAR98*32,
parameter VAR178 = 16*8,
parameter VAR105 = VAR214*VAR420,
parameter VAR56 = VAR214*192,
parameter VAR147 = VAR56,
parameter VAR167 = 16, parameter VAR176 = 13, parameter VAR272 = 3, parameter VAR245 = 16, par... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a221o/sky130_fd_sc_ms__a221o.behavioral.v | 1,662 | module MODULE1 (
VAR3 ,
VAR9,
VAR11,
VAR16,
VAR5,
VAR4
);
output VAR3 ;
input VAR9;
input VAR11;
input VAR16;
input VAR5;
input VAR4;
supply1 VAR12;
supply0 VAR2;
supply1 VAR6 ;
supply0 VAR15 ;
wire VAR1 ;
wire VAR13 ;
wire VAR14;
and VAR17 (VAR1 , VAR16, VAR5 );
and VAR7 (VAR13 , VAR9, VAR11 );
or VAR8 (VAR14, VAR13, ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/nor2/sky130_fd_sc_hd__nor2.behavioral.v | 1,350 | module MODULE1 (
VAR1,
VAR7,
VAR2
);
output VAR1;
input VAR7;
input VAR2;
supply1 VAR3;
supply0 VAR10;
supply1 VAR9 ;
supply0 VAR5 ;
wire VAR6;
nor VAR8 (VAR6, VAR7, VAR2 );
buf VAR4 (VAR1 , VAR6 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/dffnrsnq/gf180mcu_fd_sc_mcu9t5v0__dffnrsnq_4.functional.pp.v | 1,027 | module MODULE1( VAR3, VAR10, VAR18, VAR12, VAR5, VAR14, VAR13, VAR9 );
input VAR3, VAR10, VAR12, VAR18, VAR14, VAR13, VAR9;
output VAR5;
not VAR4( VAR7, VAR3 );
not VAR19( VAR11, VAR12 );
not VAR2( VAR1, VAR18 );
not VAR17( VAR16, VAR10 );
VAR15( VAR8, VAR1, VAR11, VAR7, VAR16, VAR9 );
not VAR6( VAR5, VAR8 );
endmodule | apache-2.0 |
Tao-J/nexys3MIPSSoC | vgachar.v | 2,153 | module MODULE1(
input wire clk,
input wire VAR21,
input wire VAR18,
input wire [6:0] VAR16,
input wire [7:0] VAR14,
input wire [7:0] VAR12,
input wire VAR9,
input wire VAR20,
input wire VAR11,
input wire [11:0] VAR4,
input wire [11:0] VAR7,
input wire valid,
output reg [2:0] VAR3,
output reg [2:0] VAR22,
output reg [2:... | gpl-3.0 |
AnAtomInTheUniverse/578_project_col_panic | final_verilog/src/vcr_op_ctrl_mac.v | 13,456 | module MODULE1
(clk, reset, VAR50, VAR61, VAR57, VAR10,
VAR47, VAR14, VAR70, VAR79, VAR65, VAR103,
VAR17, VAR46, VAR94, VAR80, VAR100, VAR19,
VAR1);
parameter VAR43 = 32;
parameter VAR99 = 2;
parameter VAR98 = 2;
localparam VAR76 = VAR99 * VAR98;
parameter VAR73 = 1;
localparam VAR35 = VAR76 * VAR73;
localparam VAR55 =... | gpl-2.0 |
takeshineshiro/fpga_linear_128 | ABS.v | 3,027 | module MODULE1 (
VAR5,
VAR9);
input [29:0] VAR5;
output [29:0] VAR9;
wire [29:0] VAR3;
wire [29:0] VAR9 = VAR3[29:0];
VAR7 VAR1 (
.VAR5 (VAR5),
.VAR9 (VAR3),
.VAR2 ());
VAR1.VAR4 = "VAR8",
VAR1.VAR6 = 30;
endmodule | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222o/sky130_fd_sc_ms__a222o.functional.pp.v | 2,387 | module MODULE1 (
VAR2 ,
VAR16 ,
VAR20 ,
VAR10 ,
VAR9 ,
VAR19 ,
VAR7 ,
VAR8,
VAR11,
VAR3 ,
VAR22
);
output VAR2 ;
input VAR16 ;
input VAR20 ;
input VAR10 ;
input VAR9 ;
input VAR19 ;
input VAR7 ;
input VAR8;
input VAR11;
input VAR3 ;
input VAR22 ;
wire VAR5 ;
wire VAR17 ;
wire VAR13 ;
wire VAR4 ;
wire VAR1;
and VAR15 (V... | apache-2.0 |
Siliciumer/DOS-Mario-FPGA | sources/game_engine.v | 62,463 | module MODULE1
(
input wire clk,
input wire VAR113,
input wire rst,
input wire VAR4,
input wire VAR5,
input wire VAR8,
input wire VAR91,
input wire VAR122,
input wire VAR68,
input wire VAR98,
input wire VAR92,
input wire VAR13,
input wire VAR89,
input wire VAR66,
input wire VAR95,
input wire [5:0] VAR71,
input wire VAR... | mit |
asicguy/gplgpu | hdl/altera_project/sfifo_31x128/sfifo_31x128_bb.v | 5,846 | module MODULE1 (
VAR9,
VAR5,
VAR10,
VAR7,
VAR8,
VAR4,
VAR3,
VAR6,
VAR1,
VAR2);
input [30:0] VAR9;
input VAR5;
input VAR10;
input VAR7;
input VAR8;
output [30:0] VAR4;
output VAR3;
output VAR6;
output [6:0] VAR1;
output VAR2;
endmodule | gpl-3.0 |
iafnan/es2-hardwaresecurity | or1200/rtl/verilog/or1200/SSDS_profiler.v | 7,081 | module MODULE1(
clk,
VAR16,
VAR39,
VAR52,
VAR24,
VAR57,
VAR35,
VAR38,
VAR20,
VAR43,
VAR36,
VAR33,
VAR7,
VAR10,
VAR31,
reset
);
input clk;
input VAR16;
input VAR39;
input VAR52;
input VAR24;
input VAR57;
input VAR35;
input VAR38;
input VAR20;
input VAR43;
input VAR36;
input [31:0] VAR10;
input [31:0] VAR31;
input [31:0]... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1n/sky130_fd_sc_lp__iso1n.symbol.v | 1,305 | module MODULE1 (
input VAR7 ,
output VAR2 ,
input VAR6
);
supply1 VAR3 ;
supply0 VAR4;
supply1 VAR5 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/de/der_reg_2.v | 7,112 | module MODULE1
(
input VAR29, input VAR7, input VAR10, input VAR33, input [12:0] VAR22, input [31:0] VAR17, input [31:0] VAR3, input [11:0] VAR18, input [11:0] VAR44, input [3:0] VAR13, input [3:0] VAR11, input [4:0] VAR2, input VAR21, input [1:0] VAR6, input [2:0] VAR12, input [31:0] VAR43, input [31:0] VAR19, input [... | gpl-3.0 |
mrehkopf/sd2snes | verilog/sd2snes_gsu/cheat.v | 12,795 | module MODULE1(
input clk,
input [7:0] VAR45,
input [23:0] VAR29,
input [7:0] VAR34,
input VAR17,
input VAR14,
input VAR18,
input VAR37,
input VAR58,
input VAR8,
input VAR25,
input VAR9,
input VAR70,
input VAR7,
input VAR33,
input VAR69,
input [2:0] VAR51,
input VAR6,
input [31:0] VAR66,
input VAR30,
output [7:0] VAR49... | gpl-2.0 |
qeedquan/fpga | de2-115/lcdprint/lcd.v | 1,297 | module MODULE1
(
input wire clk,
output reg [4:0] VAR6,
output reg [7:0] VAR15
);
localparam VAR12 = 0;
localparam VAR2 = 1;
localparam VAR11 = 2;
localparam VAR1 = 3;
localparam VAR13 = 4;
localparam VAR14 = 0;
localparam VAR9 = 5;
localparam VAR4 = VAR9 + 16;
localparam VAR3 = VAR4 + 1;
localparam VAR5 = VAR3 + 16;
r... | mit |
pemsac/ANN_project | ANN_project.hls/ANN_complete/ANN_complete/solution1/impl/ip/hdl/verilog/ANN_fadd_32ns_32ns_32_5_full_dsp.v | 1,912 | module MODULE1
VAR9 = 0,
VAR7 = 5,
VAR18 = 32,
VAR26 = 32,
VAR4 = 32
)(
input wire clk,
input wire reset,
input wire VAR12,
input wire [VAR18-1:0] VAR16,
input wire [VAR26-1:0] VAR6,
output wire [VAR4-1:0] dout
);
wire VAR27;
wire VAR24;
wire VAR2;
wire [31:0] VAR25;
wire VAR17;
wire [31:0] VAR10;
wire VAR8;
wire [31:0... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fa/sky130_fd_sc_ls__fa.behavioral.pp.v | 3,007 | module MODULE1 (
VAR17,
VAR27 ,
VAR24 ,
VAR2 ,
VAR26 ,
VAR6,
VAR29,
VAR14 ,
VAR10
);
output VAR17;
output VAR27 ;
input VAR24 ;
input VAR2 ;
input VAR26 ;
input VAR6;
input VAR29;
input VAR14 ;
input VAR10 ;
wire VAR9 ;
wire VAR16 ;
wire VAR25 ;
wire VAR3 ;
wire VAR30 ;
wire VAR4 ;
wire VAR32 ;
wire VAR7;
wire VAR1 ;
w... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/and3/sky130_fd_sc_ls__and3.pp.blackbox.v | 1,287 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR6 ,
VAR1 ,
VAR4,
VAR8,
VAR2 ,
VAR7
);
output VAR5 ;
input VAR3 ;
input VAR6 ;
input VAR1 ;
input VAR4;
input VAR8;
input VAR2 ;
input VAR7 ;
endmodule | apache-2.0 |
takeshineshiro/fpga_linear_128 | mult30_9_bb.v | 4,078 | module MODULE1 (
VAR4,
VAR1,
VAR2,
VAR3);
input VAR4;
input [29:0] VAR1;
input [8:0] VAR2;
output [38:0] VAR3;
endmodule | mit |
jairov4/accel-oil | solution_virtex5_plb/syn/verilog/nfa_accept_sample_multi_next_buckets.v | 1,444 | module MODULE2 (VAR8, VAR4, VAR1, VAR11, VAR7, clk);
parameter VAR5 = 64;
parameter VAR13 = 4;
parameter VAR9 = 16;
input[VAR13-1:0] VAR8;
input VAR4;
input[VAR5-1:0] VAR1;
input VAR11;
output reg[VAR5-1:0] VAR7;
input clk;
reg [VAR5-1:0] VAR12[VAR9-1:0];
always @(posedge clk)
begin
if (VAR4)
begin
if (VAR11)
begin
VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o32a/sky130_fd_sc_lp__o32a.functional.v | 1,539 | module MODULE1 (
VAR8 ,
VAR12,
VAR6,
VAR4,
VAR7,
VAR5
);
output VAR8 ;
input VAR12;
input VAR6;
input VAR4;
input VAR7;
input VAR5;
wire VAR9 ;
wire VAR13 ;
wire VAR1;
or VAR2 (VAR9 , VAR6, VAR12, VAR4 );
or VAR10 (VAR13 , VAR5, VAR7 );
and VAR11 (VAR1, VAR9, VAR13);
buf VAR3 (VAR8 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand2b/sky130_fd_sc_ls__nand2b.pp.symbol.v | 1,296 | module MODULE1 (
input VAR6 ,
input VAR1 ,
output VAR4 ,
input VAR2 ,
input VAR3,
input VAR7,
input VAR5
);
endmodule | apache-2.0 |
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC | Gaussian_Filter/ip/Gaussian_Filter/logicblock_add.v | 2,294 | module MODULE1(VAR3, VAR23,
VAR6, VAR20, VAR1,
VAR14, VAR11, VAR8,
VAR5, VAR12, VAR27);
parameter VAR2 = 32;
parameter VAR7 = 64;
input VAR3, VAR23;
input [VAR2-1:0] VAR6;
input [VAR2-1:0] VAR14;
input VAR20, VAR11;
output VAR1, VAR8;
output [VAR2-1:0] VAR5;
output VAR12;
input VAR27;
wire [VAR2-1:0] VAR10;
wire [VAR2-... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.behavioral.v | 1,163 | module MODULE1 ();
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111o/sky130_fd_sc_lp__a2111o_m.v | 2,445 | module MODULE1 (
VAR3 ,
VAR1 ,
VAR2 ,
VAR11 ,
VAR9 ,
VAR7 ,
VAR8,
VAR5,
VAR10 ,
VAR12
);
output VAR3 ;
input VAR1 ;
input VAR2 ;
input VAR11 ;
input VAR9 ;
input VAR7 ;
input VAR8;
input VAR5;
input VAR10 ;
input VAR12 ;
VAR4 VAR6 (
.VAR3(VAR3),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR7(VAR7),
.VAR8(V... | apache-2.0 |
EPiCS/soundgates | hardware/design/reference/cf_lib/edk/pcores/axi_dac_4d_2c_v1_00_a/hdl/verilog/cf_ddsv.v | 5,507 | module MODULE1 (
VAR26,
VAR3,
VAR25,
VAR13,
VAR18,
VAR2,
VAR20,
VAR11,
VAR23,
VAR4,
VAR9,
VAR17,
VAR10,
VAR28,
VAR21,
VAR5,
VAR8,
VAR15,
VAR27,
VAR31,
VAR29,
VAR32,
VAR12,
VAR16);
input VAR26;
output VAR3;
input VAR25;
input [63:0] VAR13;
output VAR18;
output VAR2;
output VAR20;
input VAR11;
input VAR23;
output [15:0] ... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/and2/sky130_fd_sc_hdll__and2.symbol.v | 1,268 | module MODULE1 (
input VAR5,
input VAR6,
output VAR1
);
supply1 VAR2;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2_lp2.v | 2,113 | module MODULE2 (
VAR8 ,
VAR5 ,
VAR1 ,
VAR6,
VAR2,
VAR4 ,
VAR7
);
output VAR8 ;
input VAR5 ;
input VAR1 ;
input VAR6;
input VAR2;
input VAR4 ;
input VAR7 ;
VAR3 VAR9 (
.VAR8(VAR8),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR4(VAR4),
.VAR7(VAR7)
);
endmodule
module MODULE2 (
VAR8,
VAR5,
VAR1
);
output VAR8;
... | apache-2.0 |
eda-globetrotter/PicenoDecoders | final/src/alu_shift.v | 95,821 | module MODULE1 (VAR1,VAR8,VAR2,VAR4,VAR3);
output [0:127] VAR3;
input [0:127] VAR1;
input [0:127] VAR8;
input [0:1] VAR2;
input [0:4] VAR4;
parameter VAR6 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR3;
integer VAR7;
integer VAR9;
integer VAR5;
always @(VAR1 or VAR8 or VAR2 or VAR4)
begin
case(VAR4)
begin
ca... | mit |
hj3938/FPGA-Imaging-Library | BoardInit_AXI/hdl/BoardInit_AXI_v1_0.v | 3,663 | module MODULE1 #
(
parameter integer VAR44 = 9,
parameter integer VAR27 = 8,
parameter integer VAR29 = 8,
parameter integer VAR49 = 32,
parameter integer VAR9 = 7
)
(
input wire VAR67,
input wire VAR42,
output wire VAR38,
output wire VAR13,
output wire[VAR27 - 1 : 0] VAR43,
output wire[VAR27 - 1 : 0] VAR20,
output wire... | lgpl-2.1 |
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