repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.pp.blackbox.v | 1,406 | module MODULE1 (
VAR7 ,
VAR6 ,
VAR3 ,
VAR1,
VAR2,
VAR8,
VAR5 ,
VAR4
);
output VAR7 ;
input VAR6 ;
input VAR3 ;
input VAR1;
input VAR2;
input VAR8;
input VAR5 ;
input VAR4 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sedfxtp/sky130_fd_sc_ls__sedfxtp.symbol.v | 1,493 | module MODULE1 (
input VAR6 ,
output VAR10 ,
input VAR7 ,
input VAR2,
input VAR1,
input VAR8
);
supply1 VAR9;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nor2/sky130_fd_sc_hvl__nor2.behavioral.v | 1,354 | module MODULE1 (
VAR4,
VAR10,
VAR8
);
output VAR4;
input VAR10;
input VAR8;
supply1 VAR7;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
wire VAR9;
nor VAR2 (VAR9, VAR10, VAR8 );
buf VAR6 (VAR4 , VAR9 );
endmodule | apache-2.0 |
cafe-alpha/wascafe | v13/r07c_de10_20201014_abus4/wasca/synthesis/submodules/altera_up_clock_edge.v | 4,630 | module MODULE1 (
clk,
reset,
VAR4,
VAR6,
VAR2
);
input clk;
input reset;
input VAR4;
output VAR6;
output VAR2;
wire VAR3;
reg VAR5;
reg VAR1;
always @(posedge clk)
VAR5 <= VAR4;
always @(posedge clk)
VAR1 <= VAR5;
assign VAR6 = VAR3 & VAR5;
assign VAR2 = VAR3 & VAR1;
assign VAR3 = VAR1 ^ VAR5;
endmodule | gpl-2.0 |
ShepardSiegel/ocpi | coregen/dram_v5_mig34/mig_v3_4/user_design/rtl/ddr2_infrastructure.v | 12,950 | module MODULE1 #
(
parameter VAR83 = 3000,
parameter VAR71 = "VAR72",
parameter VAR110 = "VAR113",
parameter VAR11 = 0,
parameter VAR104 = 1
)
(
input VAR109,
input VAR118,
input VAR77,
input VAR125,
input VAR46,
input VAR6,
output VAR30,
output VAR17,
output VAR106,
output VAR40,
input VAR74,
input VAR134,
output VAR1... | lgpl-3.0 |
CMU-SAFARI/NOCulator | hring/hw/buffered/src/c_rotator.v | 2,695 | module MODULE1
(VAR9, VAR1, VAR2);
parameter VAR4 = 8;
parameter VAR3 = VAR7;
localparam VAR5 = VAR8(VAR4);
input [0:VAR4-1] VAR1;
input [0:VAR5-1] VAR9;
output [0:VAR4-1] VAR2;
wire [0:VAR4-1] VAR2;
wire [0:(2*VAR4-1)-1] VAR10;
wire [0:(2*VAR4-1)-1] VAR6;
generate
case (VAR3)
begin
assign VAR10 = {VAR1, VAR1[0:(VAR4-1... | mit |
airin711/Verilog-caches | free_config_cache.v | 42,119 | module MODULE1(clk,
rst,
VAR21,
VAR63,
VAR5,
VAR80,
VAR69,
VAR60,
VAR40,
VAR4,
VAR27,
VAR57,
VAR28,
VAR22,
VAR39,
VAR74,
VAR52,
VAR76,
VAR51,
VAR59,
VAR75,
VAR34,
VAR15,
VAR83,
VAR61,
VAR17);
parameter VAR47 = 9;
input wire clk, rst;
input wire [24:0] VAR21;
input wire [3:0] VAR63;
input wire [31:0] VAR5;
input wire VA... | mit |
iceman1001/proxmark3 | fpga/hi_flite.v | 13,042 | module MODULE1(
VAR28, VAR17, VAR35,
VAR24, VAR51, VAR38, VAR30, VAR31, VAR41,
VAR18, VAR20,
VAR48, VAR2, VAR33, VAR16,
VAR14, VAR27,
VAR37,
VAR23
);
input VAR28, VAR17, VAR35;
output VAR24, VAR51, VAR38, VAR30, VAR31, VAR41;
input [7:0] VAR18;
output VAR20;
input VAR33;
output VAR48, VAR2, VAR16;
input VAR14, VAR27;
o... | gpl-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/rw_manager_lfsr12.v | 1,390 | module MODULE1(
clk,
VAR2,
VAR1,
word
);
input clk;
input VAR2;
input VAR1;
output reg [11:0] word;
always @(posedge clk or negedge VAR2) begin
if(~VAR2) begin
word <= 12'b101001101011;
end
else if(VAR1) begin
word[11] <= word[0];
word[10] <= word[11];
word[9] <= word[10];
word[8] <= word[9];
word[7] <= word[8];
word[6... | gpl-3.0 |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ip_top/mig_7series_v2_0_memc_ui_top_std.v | 36,626 | module MODULE1 #
(
parameter VAR111 = 100,
parameter VAR1 = "135", parameter VAR152 = 64,
parameter VAR81 = "VAR63",
parameter VAR240 = "0", parameter VAR204 = 3, parameter VAR197 = 2, parameter VAR76 = "8", parameter VAR64 = "VAR299", parameter VAR278 = "VAR181", parameter VAR73 = 1, parameter VAR155 = 5,
parameter VA... | bsd-2-clause |
trivoldus28/pulsarch-verilog | design/sys/iop/scdata/rtl/scdata_subbank.v | 16,461 | module MODULE1(
VAR85,
VAR53, VAR93,
VAR12, VAR89,
VAR48, VAR61, VAR55,
VAR79, VAR64, VAR26, VAR69, VAR57, VAR67,
VAR11, VAR43,
VAR90, VAR98, VAR4,
VAR80, VAR1, VAR7, VAR38,
VAR24, VAR21, VAR54,
VAR72, VAR73, VAR40, VAR66, VAR68
);
input [11:0] VAR66; input VAR68;
input VAR40; input VAR73; input [155:0] VAR72; input VA... | gpl-2.0 |
bgelb/digilite_zl | rtl/zl_usb_fifo.v | 3,428 | module MODULE1
(
input clk,
input VAR8,
input VAR1,
output reg VAR19,
input [7:0] VAR15,
output VAR6,
input VAR9,
output [7:0] VAR14
);
reg VAR16;
reg VAR11;
reg [7:0] VAR4;
reg [7:0] VAR17;
always @(posedge clk or negedge VAR8) begin
if(!VAR8) begin
VAR16 <= 1'b1;
VAR11 <= 1'b1;
VAR4 <= 8'b0;
VAR17 <= 8'b0;
end
else b... | bsd-2-clause |
MiddleMan5/233 | Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_slice_12_8_0/RAT_slice_12_8_0_stub.v | 1,219 | module MODULE1(VAR1, VAR2)
;
input [17:0]VAR1;
output [4:0]VAR2;
endmodule | mit |
vipinkmenon/fpgadriver | src/hw/fpga/source/memory_if/mig_7series_v1_8_ddr_phy_tempmon.v | 13,336 | module MODULE1 #
(
parameter VAR11 = 100, parameter VAR49 = 0, parameter VAR46 = 12, parameter VAR32 = 46, parameter VAR35 = 82, parameter VAR36 = 5
)
(
input clk, input rst, input VAR34, input VAR33, input [11:0] VAR22, output VAR4, output VAR6, output VAR53 );
localparam VAR20 = (VAR36 * 4096) / 504;
localparam VAR29... | mit |
jairov4/accel-oil | solution_kintex7/impl/ip/hdl/verilog/nfa_accept_samples_generic_hw_mul_8ns_6ns_14_4.v | 1,511 | module MODULE2(clk, VAR14, VAR7, VAR12, VAR9);
input clk;
input VAR14;
input[8 - 1 : 0] VAR7; input[6 - 1 : 0] VAR12; output[14 - 1 : 0] VAR9;
reg[8 - 1 : 0] VAR16;
reg[6 - 1 : 0] VAR13;
wire [14 - 1 : 0] VAR2;
reg[14 - 1 : 0] VAR11;
reg[14 - 1 : 0] VAR6;
assign VAR9 = VAR6;
assign VAR2 = VAR16 * VAR13;
always @ (posed... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor4b/sky130_fd_sc_lp__nor4b.functional.pp.v | 1,988 | module MODULE1 (
VAR12 ,
VAR17 ,
VAR2 ,
VAR6 ,
VAR9 ,
VAR14,
VAR10,
VAR1 ,
VAR5
);
output VAR12 ;
input VAR17 ;
input VAR2 ;
input VAR6 ;
input VAR9 ;
input VAR14;
input VAR10;
input VAR1 ;
input VAR5 ;
wire VAR11 ;
wire VAR3 ;
wire VAR15;
not VAR7 (VAR11 , VAR9 );
nor VAR8 (VAR3 , VAR17, VAR2, VAR6, VAR11 );
VAR13 VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/clkbuf/sky130_fd_sc_hs__clkbuf_1.v | 1,907 | module MODULE1 (
VAR1 ,
VAR4 ,
VAR2,
VAR6
);
output VAR1 ;
input VAR4 ;
input VAR2;
input VAR6;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE1 (
VAR1,
VAR4
);
output VAR1;
input VAR4;
supply1 VAR2;
supply0 VAR6;
VAR3 VAR5 (
.VAR1(VAR1),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nor3b/sky130_fd_sc_ls__nor3b.functional.v | 1,417 | module MODULE1 (
VAR4 ,
VAR1 ,
VAR5 ,
VAR8
);
output VAR4 ;
input VAR1 ;
input VAR5 ;
input VAR8;
wire VAR6 ;
wire VAR9;
nor VAR2 (VAR6 , VAR1, VAR5 );
and VAR7 (VAR9, VAR8, VAR6 );
buf VAR3 (VAR4 , VAR9 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or3/sky130_fd_sc_lp__or3.symbol.v | 1,268 | module MODULE1 (
input VAR3,
input VAR8,
input VAR4,
output VAR7
);
supply1 VAR2;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/dfrtn/sky130_fd_sc_ms__dfrtn.pp.symbol.v | 1,436 | module MODULE1 (
input VAR4 ,
output VAR1 ,
input VAR3,
input VAR7 ,
input VAR5 ,
input VAR6 ,
input VAR8 ,
input VAR2
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a41o/sky130_fd_sc_lp__a41o.functional.v | 1,462 | module MODULE1 (
VAR2 ,
VAR7,
VAR6,
VAR3,
VAR11,
VAR8
);
output VAR2 ;
input VAR7;
input VAR6;
input VAR3;
input VAR11;
input VAR8;
wire VAR1 ;
wire VAR10;
and VAR9 (VAR1 , VAR7, VAR6, VAR3, VAR11 );
or VAR5 (VAR10, VAR1, VAR8 );
buf VAR4 (VAR2 , VAR10 );
endmodule | apache-2.0 |
AbhishekShah212/School_Projects | ELEN232/pset5/FullAdderNoError.v | 2,196 | module MODULE1(
input [3:0] VAR5,
input [3:0] VAR16,
input VAR4,
output [4:0] VAR7
);
wire VAR14;
wire VAR9, VAR3, VAR11, VAR15, VAR1;
VAR12 VAR17 (
.VAR5(VAR5[0]),
.VAR16(VAR16[0] ^ VAR4), .VAR7(VAR7[0]),
.VAR13(VAR9),
.VAR6(VAR4)
);
VAR12 VAR8 (
.VAR5(VAR5[1]),
.VAR16(VAR16[1] ^ VAR4),
.VAR7(VAR7[1]),
.VAR13(VAR3), .... | mit |
Rmin1995/NoC | priority_all_vc.v | 2,871 | module MODULE1(VAR30, VAR12, VAR6, VAR22, VAR20, VAR10, VAR18, VAR4);
parameter VAR27 = 4;
output [1:VAR8 * VAR31] VAR30;
output [0:VAR9*VAR31*VAR27-1] VAR12;
output [0:VAR31 * VAR27 -1] VAR6; input [0:VAR31 * VAR27 -1] VAR22; input [1:VAR8 * VAR31] VAR20;
input [0:VAR9*VAR31*VAR27-1] VAR10;
input [0:VAR27*VAR31-1] VAR... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/oai32/gf180mcu_fd_sc_mcu7t5v0__oai32_2.functional.v | 1,666 | module MODULE1( VAR3, VAR11, VAR21, VAR5, VAR20, VAR9 );
input VAR21, VAR11, VAR3, VAR9, VAR20;
output VAR5;
wire VAR19;
not VAR14( VAR19, VAR21 );
wire VAR10;
not VAR12( VAR10, VAR11 );
wire VAR13;
not VAR7( VAR13, VAR3 );
wire VAR2;
and VAR1( VAR2, VAR19, VAR10, VAR13 );
wire VAR8;
not VAR4( VAR8, VAR9 );
wire VAR16;... | apache-2.0 |
SymbiFlow/yosys | techlibs/ice40/brams_map.v | 7,976 | module \VAR48 (
output [15:0] VAR44,
input VAR56, VAR31, VAR19,
input [10:0] VAR24,
input VAR33, VAR51, VAR57,
input [10:0] VAR28,
input [15:0] VAR60, VAR47
);
parameter [1:0] VAR2 = 0;
parameter [1:0] VAR17 = 0;
parameter [0:0] VAR18 = 0;
parameter [0:0] VAR45 = 0;
parameter [255:0] VAR36 = 256'h0000000000000000000000... | isc |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_2.functional.v | 1,443 | module MODULE1( VAR10, VAR13, VAR11, VAR16, VAR4 );
input VAR11, VAR13, VAR16, VAR4;
output VAR10;
wire VAR7;
not VAR3( VAR7, VAR11 );
wire VAR2;
not VAR8( VAR2, VAR13 );
wire VAR6;
and VAR12( VAR6, VAR7, VAR2 );
wire VAR9;
not VAR1( VAR9, VAR16 );
wire VAR5;
not VAR15( VAR5, VAR4 );
or VAR14( VAR10, VAR6, VAR9, VAR5 )... | apache-2.0 |
firemark/katp91 | src/Alu.v | 2,353 | module MODULE1(VAR17, VAR3, VAR2, VAR7, VAR1, VAR9, VAR16, VAR5);
input VAR17;
input [15:0] VAR3, VAR2;
input [3:0] VAR7;
input VAR5;
reg VAR15; wire VAR8, VAR14, VAR12;
wire VAR6, VAR11, VAR4, VAR10;
output [3:0] VAR9;
output [3:0] VAR16;
output reg [15:0] VAR1;
assign VAR8 = VAR3[15] ^ VAR1[15];
assign VAR14 = ~|VAR1... | mit |
ShepardSiegel/ocpi | coregen/dram_v6_mig37/mig_37/user_design/rtl/ui/ui_wr_data.v | 20,842 | module MODULE1 #
(
parameter VAR109 = 100,
parameter VAR84 = 256,
parameter VAR57 = 32,
parameter VAR12 = "VAR103",
parameter VAR60 = "VAR103",
parameter VAR74 = 5
)
(
VAR85, VAR7, VAR62, VAR59, VAR31,
VAR39,
rst, clk, VAR26, VAR37, VAR73, VAR69,
VAR46, VAR64, VAR66, VAR101, VAR6,
VAR102, VAR16
);
input rst;
input clk;... | lgpl-3.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_binary_plus_one_to_gray.v | 1,840 | module MODULE1 #(parameter VAR10(VAR1 ))
(input [VAR1-1:0] VAR4
, output [VAR1-1:0] VAR12
);
wire [VAR1-1:0] VAR7;
VAR9 #(.VAR1(VAR1)
,.VAR3(1)
,.VAR13(1)
) VAR2 (.VAR5(VAR4), .VAR6(VAR7));
wire [VAR1:0] VAR8 = { 1'b0, VAR7[VAR1-2:0], 1'b1};
wire [VAR1-1:0] VAR11 = ~VAR8[VAR1:1] & VAR8[VAR1-1:0];
assign VAR12 = (VAR4 >... | bsd-3-clause |
archlabo/Frix | fpga/nexys4_ddr/project/project.srcs/sources_1/ip/mig/mig/user_design/rtl/ui/mig_7series_v2_0_ui_wr_data.v | 21,343 | module MODULE1 #
(
parameter VAR87 = 100,
parameter VAR30 = 256,
parameter VAR101 = 32,
parameter VAR53 = "VAR5",
parameter VAR4 = 2 ,
parameter VAR62 = "VAR5",
parameter VAR29 = 5
)
(
VAR20, VAR41, VAR14, VAR37, VAR77,
VAR98,
rst, clk, VAR34, VAR47, VAR8, VAR83,
VAR19, VAR36, VAR61, VAR33, VAR79,
VAR46, VAR84
);
input... | bsd-2-clause |
alexforencich/verilog-ethernet | example/HXT100G/fpga_cxpt16/rtl/fpga.v | 27,807 | module MODULE1 (
input wire VAR274,
input wire VAR40,
input wire [1:0] VAR177,
input wire [3:0] VAR161,
output wire [3:0] VAR100,
output wire VAR7,
input wire VAR370,
output wire VAR130,
output wire VAR286,
input wire VAR117,
output wire VAR138,
input wire VAR18,
output wire VAR309,
input wire VAR97,
output wire VAR220... | mit |
sh-chris110/chris | FPGA/chris.uart.ok/Qsys/soc_design/synthesis/submodules/soc_design_niosII_core.v | 6,655 | module MODULE1 (
input wire clk, input wire VAR15, input wire VAR26, output wire [17:0] VAR23, output wire [3:0] VAR6, output wire VAR29, input wire [31:0] VAR30, input wire VAR2, output wire VAR4, output wire [31:0] VAR18, output wire [3:0] VAR9, input wire VAR21, output wire VAR22, output wire [17:0] VAR3, output wir... | gpl-2.0 |
drichmond/riffa | fpga/altera/de5/riffa_wrapper_de5.v | 37,115 | module MODULE1
parameter VAR308 = 128,
parameter VAR275 = 256,
parameter VAR135 = 5,
parameter VAR169 = "VAR285")
( input [VAR308-1:0] VAR30,
input [0:0] VAR248,
input [0:0] VAR3,
input [0:0] VAR202,
output VAR328,
input [0:0] VAR209,
output [VAR308-1:0] VAR326,
output [0:0] VAR215,
input VAR147,
output [0:0] VAR233,
o... | bsd-3-clause |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_32.behavioral.pp.v | 1,074 | module MODULE1( VAR4, VAR3 );
inout VAR4, VAR3;
VAR1 VAR5(.VAR4(VAR4),.VAR3(VAR3));
VAR1 VAR2(.VAR4(VAR4),.VAR3(VAR3)); | apache-2.0 |
borti4938/sd2snes | verilog/sd2snes_cx4/cx4_datram.v | 10,672 | module MODULE1 (
VAR22,
VAR18,
VAR40,
VAR34,
VAR7,
VAR42,
VAR33,
VAR24,
VAR19);
input [11:0] VAR22;
input [11:0] VAR18;
input VAR40;
input [7:0] VAR34;
input [7:0] VAR7;
input VAR42;
input VAR33;
output [7:0] VAR24;
output [7:0] VAR19;
tri1 VAR40;
tri0 VAR42;
tri0 VAR33;
wire [7:0] VAR41;
wire [7:0] VAR50;
wire [7:0] V... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/cores/altera_virtual_jtag/altera_virtual_jtag.v | 4,413 | module MODULE1 (
output VAR19,
input VAR22,
output VAR4,
output VAR23,
output VAR34,
output VAR1,
output VAR11,
output VAR25,
output VAR5,
output VAR41
);
localparam [3:0] VAR15 = 4'b1000;
wire [3:0] VAR29;
wire VAR33;
wire VAR36;
wire VAR38;
wire VAR10;
VAR8 #(
.VAR13 ("VAR16"),
.VAR27 (0),
.VAR14 (4),
.VAR31 (""),
.V... | gpl-2.0 |
intelligenttoasters/CPC2.0 | FPGA/Quartus/DE10/mmio_if/synthesis/submodules/hps_sdram_p0_clock_pair_generator.v | 4,036 | module MODULE1
(
VAR10,
VAR32,
VAR2) ;
input [0:0] VAR10;
output [0:0] VAR32;
output [0:0] VAR2;
wire [0:0] VAR9;
wire [0:0] VAR16;
wire [0:0] VAR12;
wire [0:0] VAR15;
wire [0:0] VAR35;
wire [0:0] VAR30;
wire [0:0] VAR7;
wire [0:0] VAR11;
wire [0:0] VAR18;
wire [0:0] VAR23;
VAR21 VAR17
(
.VAR6(VAR30),
.VAR34(VAR9[0:0])... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o32a/sky130_fd_sc_ms__o32a_1.v | 2,428 | module MODULE1 (
VAR12 ,
VAR1 ,
VAR2 ,
VAR6 ,
VAR5 ,
VAR4 ,
VAR8,
VAR9,
VAR7 ,
VAR10
);
output VAR12 ;
input VAR1 ;
input VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR4 ;
input VAR8;
input VAR9;
input VAR7 ;
input VAR10 ;
VAR11 VAR3 (
.VAR12(VAR12),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR4(VAR4),
.VAR8(VA... | apache-2.0 |
uastw-embsys/Verilog-Perl | verilog/parser_sv.v | 9,555 | package VAR33;
bit [7:0] VAR41;
bit [7:0] VAR25;
endpackage
module MODULE6 ();
VAR18 VAR30;
VAR39 VAR30 = 33ns; endmodule : MODULE6
interface VAR23 #(parameter VAR3 = 0);
logic VAR27;
logic [7:0] addr, VAR15[9];
modport VAR1(input VAR15, VAR6, output addr);
endinterface : VAR23
module MODULE7 (
VAR23 VAR2,
VAR23.MODULE... | artistic-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/buf/sky130_fd_sc_ls__buf_8.v | 1,993 | module MODULE1 (
VAR5 ,
VAR8 ,
VAR1,
VAR2,
VAR6 ,
VAR4
);
output VAR5 ;
input VAR8 ;
input VAR1;
input VAR2;
input VAR6 ;
input VAR4 ;
VAR7 VAR3 (
.VAR5(VAR5),
.VAR8(VAR8),
.VAR1(VAR1),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule
module MODULE1 (
VAR5,
VAR8
);
output VAR5;
input VAR8;
supply1 VAR1;
supply0 VAR2;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/and4bb/sky130_fd_sc_ms__and4bb.functional.v | 1,416 | module MODULE1 (
VAR8 ,
VAR6,
VAR4,
VAR5 ,
VAR9
);
output VAR8 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR9 ;
wire VAR10 ;
wire VAR3;
nor VAR2 (VAR10 , VAR6, VAR4 );
and VAR1 (VAR3, VAR10, VAR5, VAR9 );
buf VAR7 (VAR8 , VAR3 );
endmodule | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_webcam/zybo_petalinux_webcam.ip_user_files/ipstatic/axi_infrastructure_v1_1/hdl/verilog/axi_infrastructure_v1_1_axi2vector.v | 11,282 | module MODULE1 #
(
parameter integer VAR2 = 0,
parameter integer VAR101 = 4,
parameter integer VAR120 = 32,
parameter integer VAR8 = 32,
parameter integer VAR38 = 0,
parameter integer VAR54 = 0,
parameter integer VAR134 = 1,
parameter integer VAR24 = 1,
parameter integer VAR127 = 1,
parameter integer VAR44 = 1,
paramet... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd.behavioral.v | 1,163 | module MODULE1 ();
supply1 VAR1;
supply0 VAR3;
supply1 VAR4 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
sirchuckalot/zet | cores/hpdmc_sdr16/rtl/hpdmc_mgmt.v | 9,148 | module MODULE1 #(
parameter VAR38 = 26,
parameter VAR15 = 9,
parameter VAR11 = VAR38-1-1-(VAR15+2)+1
) (
input VAR33,
input VAR12,
input [2:0] VAR32,
input [2:0] VAR28,
input [10:0] VAR5,
input [3:0] VAR52,
input VAR17,
input VAR10,
input [VAR38-1-1:0] address,
output reg ack,
output reg read,
output reg write,
output ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_p_pp_sn/sky130_fd_sc_hs__udp_dff_p_pp_sn.blackbox.v | 1,352 | module MODULE1 (
VAR5 ,
VAR3 ,
VAR1 ,
VAR4 ,
VAR2
);
output VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR4 ;
input VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfbbp/sky130_fd_sc_hdll__sdfbbp.symbol.v | 1,580 | module MODULE1 (
input VAR8 ,
output VAR5 ,
output VAR6 ,
input VAR10,
input VAR1 ,
input VAR12 ,
input VAR11 ,
input VAR7
);
supply1 VAR3;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nand3/sky130_fd_sc_lp__nand3.symbol.v | 1,280 | module MODULE1 (
input VAR7,
input VAR8,
input VAR6,
output VAR2
);
supply1 VAR3;
supply0 VAR1;
supply1 VAR5 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_solo/nios_solo/synthesis/submodules/nios_solo_mm_interconnect_0_avalon_st_adapter_002.v | 6,173 | module MODULE1 #(
parameter VAR17 = 34,
parameter VAR20 = 0,
parameter VAR23 = 34,
parameter VAR3 = 0,
parameter VAR10 = 0,
parameter VAR15 = 0,
parameter VAR16 = 1,
parameter VAR12 = 1,
parameter VAR11 = 0,
parameter VAR2 = 34,
parameter VAR14 = 0,
parameter VAR25 = 1,
parameter VAR8 = 0,
parameter VAR24 = 1,
paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a2bb2oi/sky130_fd_sc_ls__a2bb2oi.blackbox.v | 1,463 | module MODULE1 (
VAR2 ,
VAR6,
VAR1,
VAR4 ,
VAR8
);
output VAR2 ;
input VAR6;
input VAR1;
input VAR4 ;
input VAR8 ;
supply1 VAR5;
supply0 VAR3;
supply1 VAR7 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
lloves/Sora | FPGA/SISO/rtl/pcie_userapp_wrapper/pcie_dma_engine/completer_pkt_gen.v | 5,500 | module MODULE1(
input clk,
input rst,
input [6:0] VAR27, input VAR2, input [31:0] VAR8, input [15:0] VAR13, input [15:0] VAR14, input [7:0] VAR10, output reg VAR7,
output reg [63:0] VAR23
);
localparam VAR22 = 4'h0;
localparam VAR24 = 4'h1;
localparam VAR9 = 4'h2;
localparam VAR20 = 1'b0;
localparam VAR5 = 2'b10; local... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b.functional.pp.v | 1,951 | module MODULE1 (
VAR15 ,
VAR5 ,
VAR11 ,
VAR8 ,
VAR9,
VAR6,
VAR12 ,
VAR3
);
output VAR15 ;
input VAR5 ;
input VAR11 ;
input VAR8 ;
input VAR9;
input VAR6;
input VAR12 ;
input VAR3 ;
wire VAR14 ;
wire VAR1 ;
wire VAR16;
not VAR7 (VAR14 , VAR8 );
or VAR4 (VAR1 , VAR11, VAR5, VAR14 );
VAR13 VAR10 (VAR16, VAR1, VAR9, VAR6);... | apache-2.0 |
esihaj/MIPS-Multi-Cycle | Controller.v | 2,010 | module MODULE1(input clk, reset, VAR21, input [2:0] VAR16, output reg VAR22, VAR5, VAR15, VAR14, VAR30, VAR13, VAR20, VAR7, VAR27, VAR18);
parameter [2:0] VAR19 = 3'b000, VAR11 = 3'b001, VAR9 = 3'b010, VAR26 = 3'b011, VAR10 = 3'b100, VAR12 = 3'b101, VAR6 = 3'b110, VAR29 = 3'b111;
reg [2:0] VAR4 = VAR19, VAR1;
parameter... | mit |
jhoward321/pacman | usb_system/synthesis/submodules/usb_system_cpu_jtag_debug_module_tck.v | 8,113 | module MODULE1 (
VAR26,
VAR4,
VAR29,
VAR14,
VAR39,
VAR15,
VAR13,
VAR32,
VAR23,
VAR31,
VAR9,
VAR2,
VAR37,
VAR38,
VAR7,
VAR12,
VAR40,
VAR16,
VAR36,
VAR10,
VAR25,
VAR11,
VAR6,
VAR20,
VAR34,
VAR22,
VAR8,
VAR21,
VAR30,
VAR35,
VAR17
)
;
output [ 1: 0] VAR8;
output VAR21;
output [ 37: 0] VAR30;
output VAR35;
output VAR17;
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25_2.v | 2,163 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR7,
VAR4,
VAR1 ,
VAR8
);
output VAR3 ;
input VAR2 ;
input VAR7;
input VAR4;
input VAR1 ;
input VAR8 ;
VAR5 VAR6 (
.VAR3(VAR3),
.VAR2(VAR2),
.VAR7(VAR7),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8(VAR8)
);
endmodule
module MODULE1 (
VAR3,
VAR2
);
output VAR3;
input VAR2;
supply1 VAR7;
supply0 VAR4;... | apache-2.0 |
GSejas/Dise-o-ASIC-FPGA-FPU | my_sourcefiles/Source_Files/FPU_Interface/cordic_Arch3/CORDIC_Arch3v1.v | 18,737 | module MODULE1 #(parameter VAR116 = 32, parameter VAR65 = 8, parameter VAR125 = 23, parameter VAR132=26, parameter VAR23 = 5) /*#(parameter VAR116 = 64, parameter VAR65 = 11, parameter VAR125 = 52, parameter VAR132 = 55, parameter VAR23 = 6) (
input wire clk, input wire rst, input wire VAR30, input wire VAR27, input wi... | gpl-3.0 |
ultraembedded/riscv | top_cache_axi/src_v/dcache_pmem_mux.v | 5,191 | module MODULE1
(
input VAR6
,input VAR21
,input VAR36
,input VAR28
,input VAR23
,input [ 31:0] VAR33
,input VAR25
,input [ 3:0] VAR34
,input VAR24
,input [ 7:0] VAR2
,input [ 31:0] VAR17
,input [ 31:0] VAR13
,input [ 3:0] VAR32
,input VAR5
,input [ 7:0] VAR27
,input [ 31:0] VAR12
,input [ 31:0] VAR29
,output [ 3:0] VAR... | bsd-3-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/hard/tsmc_40/bsg_misc/bsg_nor3.v | 1,634 | if (VAR17 && (VAR22==VAR12)) \
begin: VAR18 \
VAR4 VAR20 (.VAR15(VAR13),.VAR19(VAR11),.VAR8(VAR21),.VAR6); \
end
module MODULE1 #(parameter VAR7(VAR22)
, parameter VAR17=0
)
(input [VAR22-1:0] VAR13
, input [VAR22-1:0] VAR11
, input [VAR22-1:0] VAR21
, output [VAR22-1:0] VAR6
);
begin :VAR10
end
VAR16 assert(VAR17==0) ... | bsd-3-clause |
rfotino/consolite-hardware | src/vga_buffer.v | 6,111 | module MODULE1
(
input clk, input VAR5, input VAR9,
input [7:0] VAR16,
input [7:0] VAR8,
input VAR3,
output [7:0] VAR17,
output reg VAR19,
output [2:0] VAR10,
output [5:0] VAR12,
output [29:0] VAR11,
input VAR2,
input VAR4,
output reg VAR6,
input [31:0] VAR13,
input VAR15,
input VAR1,
input [6:0] VAR7,
input VAR18,
inp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/diode/sky130_fd_sc_ms__diode_2.v | 1,978 | module MODULE1 (
VAR4,
VAR5 ,
VAR7 ,
VAR6 ,
VAR2
);
input VAR4;
input VAR5 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
VAR3 VAR1 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR6(VAR6),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR4
);
input VAR4;
supply1 VAR5;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR2 ;
VAR3 VAR1 (
.VAR4(VA... | apache-2.0 |
hitomi2500/wasca | fpga_firmware/wasca/wasca_bb.v | 2,444 | module MODULE1 (
VAR16,
VAR14,
VAR18,
VAR6,
VAR29,
VAR17,
VAR22,
VAR24,
VAR27,
VAR20,
VAR19,
VAR13,
VAR3,
VAR28,
VAR4,
VAR5,
VAR11,
VAR8,
VAR10,
VAR1,
VAR9,
VAR12,
VAR7,
VAR23,
VAR21,
VAR31,
VAR26,
VAR2,
VAR30,
VAR25,
VAR15);
input [24:0] VAR16;
input VAR14;
inout [15:0] VAR18;
input [2:0] VAR6;
output VAR29;
output VA... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/aoi221/gf180mcu_fd_sc_mcu7t5v0__aoi221_4.functional.v | 2,099 | module MODULE1( VAR23, VAR21, VAR10, VAR19, VAR14, VAR5 );
input VAR14, VAR5, VAR10, VAR21, VAR19;
output VAR23;
wire VAR8;
not VAR18( VAR8, VAR14 );
wire VAR11;
not VAR15( VAR11, VAR10 );
wire VAR12;
not VAR20( VAR12, VAR19 );
wire VAR22;
and VAR2( VAR22, VAR8, VAR11, VAR12 );
wire VAR13;
not VAR7( VAR13, VAR21 );
wir... | apache-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_example_driver.v | 35,109 | module MODULE1 (
clk,
VAR94,
VAR47,
VAR35,
VAR93,
VAR11,
VAR104,
VAR74,
VAR67,
VAR84,
VAR48,
VAR27,
VAR91,
VAR42,
VAR9,
VAR21,
VAR51,
VAR69,
VAR75
)
;
output [ 2: 0] VAR11;
output [ 15: 0] VAR104;
output VAR74;
output [ 9: 0] VAR67;
output VAR84;
output VAR48;
output [ 13: 0] VAR27;
output [ 6: 0] VAR91;
output [127: 0... | gpl-3.0 |
jakubfi/mera400f | src/fpm.v | 9,049 | module MODULE1(
output VAR84,
output VAR44,
input VAR55,
input [8:15] VAR158,
input VAR27,
input 0d,
input VAR155,
output [-2:7] VAR116,
input VAR123,
input VAR54,
input VAR43,
input 0f,
input VAR138,
input VAR102,
input VAR78,
input VAR15,
input VAR56,
input VAR31,
output VAR76,
output VAR147,
output VAR60,
output VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/diode/sky130_fd_sc_hdll__diode.behavioral.pp.v | 1,208 | module MODULE1 (
VAR5,
VAR4 ,
VAR3 ,
VAR2 ,
VAR1
);
input VAR5;
input VAR4 ;
input VAR3 ;
input VAR2 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2_1.v | 2,091 | module MODULE2 (
VAR3 ,
VAR4 ,
VAR7 ,
VAR5,
VAR8,
VAR2 ,
VAR6
);
output VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR5;
input VAR8;
input VAR2 ;
input VAR6 ;
VAR1 VAR9 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR6(VAR6)
);
endmodule
module MODULE2 (
VAR3,
VAR4,
VAR7
);
output VAR3;
... | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_stub.v | 5,787 | module MODULE1(VAR49, VAR3, VAR67, VAR57,
VAR39, VAR73, VAR70, VAR69, VAR66, VAR74,
VAR53, VAR77, VAR64, VAR31, VAR30, VAR55, VAR50,
VAR65, VAR71, VAR6, VAR20, VAR16, VAR58, VAR29,
VAR13, VAR78, VAR76, VAR34, VAR40, VAR14,
VAR43, VAR33, VAR18, VAR42, VAR75, VAR60, VAR62,
VAR25, VAR8, VAR63, VAR68, VAR47, VAR19, VAR72,
... | mit |
scalable-networks/ext | uhd/fpga/usrp2/sdr_lib/clip_and_round.v | 1,474 | module MODULE1
parameter VAR1=0,
parameter VAR6=0)
(input [VAR3-1:0] in,
output [VAR1-1:0] out);
wire [VAR1-1:0] VAR5;
VAR4 #(.VAR3(VAR3-VAR6),.VAR1(VAR1))
VAR4 (.in(in[VAR3-VAR6-1:0]),.out(VAR5));
wire VAR2 = |in[VAR3-1:VAR3-VAR6-1]
& ~(&in[VAR3-1:VAR3-VAR6-1]);
assign out = VAR2 ?
(in[VAR3-1] ? {1'b1,{(VAR1-1){1'b0}}... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.functional.v | 1,346 | module MODULE1 (
VAR4 ,
VAR2 ,
VAR1
);
output VAR4 ;
input VAR2 ;
input VAR1;
wire VAR8 ;
wire VAR5;
not VAR6 (VAR8 , VAR1 );
or VAR7 (VAR5, VAR8, VAR2 );
buf VAR3 (VAR4 , VAR5 );
endmodule | apache-2.0 |
takeshineshiro/fpga_fibre_scan | HUCB2P0_150701/03_usb/register_ctrl_top.v | 4,238 | module MODULE1(
input VAR19 ,
input VAR13 ,
output VAR20 ,
output [7 : 0] VAR17 ,
input VAR8 ,
output VAR12 ,
input [7 : 0] VAR1 ,
input VAR5 ,
output VAR16 ,
output VAR6 ,
output VAR9 ,
input VAR11
);
reg VAR3 ;
reg VAR18 ;
reg VAR10 ;
reg [7 : 0] VAR4 ;
reg VAR2 ;
reg [7 : 0] VAR14 ;
reg VAR7 ;
reg VAR15 ;
always@(po... | apache-2.0 |
olajep/oh | src/accelerator/hdl/axi_accelerator.v | 15,002 | module MODULE1(
irq, VAR103, VAR115, VAR96, VAR105,
VAR116, VAR98, VAR94, VAR100,
VAR62, VAR59, VAR86, VAR35, VAR78,
VAR25, VAR70, VAR37, VAR12, VAR109,
VAR111, VAR30, VAR24, VAR99,
VAR17, VAR76, VAR36, VAR44,
VAR80, VAR81, VAR53, VAR58, VAR68,
VAR22, VAR46, VAR88, VAR92, VAR79,
VAR32, VAR74,
VAR97, VAR107, VAR69, VAR9... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/and4b/sky130_fd_sc_hs__and4b.functional.pp.v | 1,885 | module MODULE1 (
VAR3,
VAR15,
VAR14 ,
VAR13 ,
VAR1 ,
VAR6 ,
VAR8
);
input VAR3;
input VAR15;
output VAR14 ;
input VAR13 ;
input VAR1 ;
input VAR6 ;
input VAR8 ;
wire VAR8 VAR5 ;
wire VAR7 ;
wire VAR2;
not VAR4 (VAR5 , VAR13 );
and VAR12 (VAR7 , VAR5, VAR1, VAR6, VAR8 );
VAR9 VAR10 (VAR2, VAR7, VAR3, VAR15);
buf VAR11 (... | apache-2.0 |
praveendath92/securePUF | source/puf_files/back_up/pdl_puf.v | 1,949 | module MODULE1 (VAR20, VAR14, VAR12, VAR9, reset, VAR16);
parameter VAR5 = 63;
input [VAR5:0] VAR20, VAR14;
input VAR12, VAR9, reset;
output VAR16;
wire [VAR5:0] VAR17,VAR15;
wire VAR8;
VAR18 VAR3 [VAR5:0] (
.VAR17({VAR12,VAR17[VAR5:1]}),
.VAR15({VAR9,VAR15[VAR5:1]}),
.VAR1(VAR20[VAR5:0]),
.VAR2(VAR14[VAR5:0]),
.o1(VAR... | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/fei4_rx/fei4_rx.v | 2,341 | module MODULE1 #(
parameter VAR36 = 32'h0000,
parameter VAR5 = 32'h0000,
parameter VAR13 = 10,
parameter VAR26 = 0,
parameter VAR34 = 16,
parameter VAR7 = 0
) (
input wire VAR14,
input wire VAR20,
input wire VAR9,
input wire VAR27,
output wire VAR15,
output wire VAR8,
output wire VAR22,
input wire VAR3,
input wire VAR6... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o2111ai/sky130_fd_sc_ms__o2111ai_2.v | 2,461 | module MODULE2 (
VAR12 ,
VAR7 ,
VAR5 ,
VAR11 ,
VAR2 ,
VAR3 ,
VAR4,
VAR8,
VAR1 ,
VAR9
);
output VAR12 ;
input VAR7 ;
input VAR5 ;
input VAR11 ;
input VAR2 ;
input VAR3 ;
input VAR4;
input VAR8;
input VAR1 ;
input VAR9 ;
VAR6 VAR10 (
.VAR12(VAR12),
.VAR7(VAR7),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR4(... | apache-2.0 |
efabless/openlane | designs/jpeg_encoder/src/jpeg_rzs.v | 6,397 | module MODULE1(clk, VAR18, rst, VAR3, VAR11, VAR1, VAR12, VAR4, VAR10, VAR2, VAR5, VAR13, VAR14);
input clk;
input VAR18;
input rst;
input VAR3;
input VAR11;
input [ 3:0] VAR12;
input [ 3:0] VAR1;
input [11:0] VAR4;
output VAR10;
output VAR2;
output [ 3:0] VAR13;
output [ 3:0] VAR5;
output [11:0] VAR14;
reg VAR10, VAR2... | apache-2.0 |
MegabytePhreak/Verilog-Perl | verilog/pli.v | 1,083 | module MODULE1;
integer VAR2; VAR3 VAR2 = 0;
integer VAR9; VAR3 VAR9 = 0;
integer VAR12; VAR3 VAR12 = 1;
always @ (VAR2 or VAR9) begin
if (VAR2!=0 || VAR9!=0) begin
VAR11 (0, "VAR7/VAR9 VAR8, VAR4!\VAR1");
end
if (VAR2!=0) begin
VAR11 (0, "VAR7 VAR8, VAR4!\VAR1");
end
else if (VAR9!=0) begin
VAR11 (0, {"VAR5 VAR8, ","V... | artistic-2.0 |
cafe-alpha/wasca | v12/fpga_firmware/wasca/synthesis/submodules/wasca_sd_card_spi.v | 11,932 | module MODULE1 (
VAR40,
clk,
VAR33,
VAR46,
VAR62,
VAR37,
VAR6,
VAR36,
VAR49,
VAR47,
VAR11,
VAR29,
VAR42,
VAR24,
irq,
VAR26
)
;
output VAR49;
output VAR47;
output VAR11;
output [ 15: 0] VAR29;
output VAR42;
output VAR24;
output irq;
output VAR26;
input VAR40;
input clk;
input [ 15: 0] VAR33;
input [ 2: 0] VAR46;
input V... | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand3/gf180mcu_fd_sc_mcu9t5v0__nand3_1.behavioral.pp.v | 1,333 | module MODULE1( VAR2, VAR1, VAR5, VAR9, VAR3, VAR7 );
input VAR9, VAR5, VAR2;
inout VAR3, VAR7;
output VAR1;
VAR8 VAR4(.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7));
VAR8 VAR6(.VAR2(VAR2),.VAR1(VAR1),.VAR5(VAR5),.VAR9(VAR9),.VAR3(VAR3),.VAR7(VAR7)); | apache-2.0 |
KestrelComputer/kestrel | cores/SIA/rtl/verilog/sia.v | 2,708 | module MODULE1(
input VAR68,
input VAR54,
input [3:1] VAR58,
input VAR74,
input VAR45,
input VAR57,
input [1:0] VAR65,
input [VAR82:0] VAR76,
output [VAR82:0] VAR66,
output VAR78,
output VAR19,
output VAR4,
input VAR52,
input VAR2,
output VAR24,
output VAR30,
output VAR49,
output VAR33
);
parameter VAR67 = 20;
paramete... | mpl-2.0 |
peteasa/parallella-fpga | AdaptevaLib/elink-gold/ewrapper_link_transmitter.v | 7,768 | module MODULE1(
VAR15, VAR47, VAR49,
reset, VAR35, VAR18, VAR24,
VAR32, VAR53, VAR23,
VAR42, VAR17, VAR43,
VAR52, VAR55, VAR45
);
input reset; input VAR35;
input VAR18;
input VAR24;
input VAR32;
input [1:0] VAR53;
input [3:0] VAR23;
input [31:0] VAR42;
input [31:0] VAR17;
input [31:0] VAR43;
input VAR52; input VAR55;
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.pp.symbol.v | 1,391 | module MODULE1 (
input VAR2 ,
input VAR8 ,
input VAR3,
output VAR1 ,
input VAR7 ,
input VAR4,
input VAR6,
input VAR5
);
endmodule | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/fpu/rtl/fpu_div_ctl.v | 50,877 | module MODULE1 (
VAR24,
VAR69,
VAR315,
VAR46,
VAR85,
VAR6,
VAR4,
VAR2,
VAR155,
VAR14,
VAR194,
VAR152,
VAR113,
VAR205,
VAR103,
VAR173,
VAR141,
VAR80,
VAR26,
VAR283,
VAR86,
VAR70,
VAR352,
VAR5,
VAR192,
VAR41,
VAR67,
VAR335,
VAR200,
VAR197,
VAR223,
VAR338,
VAR343,
VAR301,
VAR90,
VAR312,
VAR133,
VAR129,
VAR120,
VAR224,
VAR... | gpl-2.0 |
Tao-J/nexys3MIPSSoC | Regs.v | 1,379 | module MODULE1(
input clk,
input rst,
input [4:0] VAR7,
input [4:0] VAR4,
input [4:0] VAR1,
input [31:0] VAR2,
input VAR8,
output [31:0] VAR3,
output [31:0] VAR5
);
reg [31:0] register[1:31];
integer VAR6;
assign VAR3 = (VAR7 == 0)?0:register[VAR7];
assign VAR5 = (VAR4 == 0)?0:register[VAR4];
always @(posedge clk or po... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a32o/sky130_fd_sc_lp__a32o.blackbox.v | 1,425 | module MODULE1 (
VAR9 ,
VAR3,
VAR6,
VAR7,
VAR8,
VAR10
);
output VAR9 ;
input VAR3;
input VAR6;
input VAR7;
input VAR8;
input VAR10;
supply1 VAR1;
supply0 VAR5;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/ip/ddr_axi/ddr_axi/user_design/rtl/ddr_axi_mig.v | 67,514 | module MODULE1 #
(
parameter VAR398 = 1,
parameter VAR175 = 3,
parameter VAR93 = 1,
parameter VAR373 = 10,
parameter VAR163 = 1,
parameter VAR156 = 1,
parameter VAR40 = 1,
parameter VAR207 = 4,
parameter VAR157 = 4,
parameter VAR383 = 8,
parameter VAR356 = 2,
parameter VAR128 = 16,
parameter VAR106 = 2,
parameter VAR17... | mit |
bluespec/Flute | builds/AWSteria_Core_Flute_RV64_Linux/Verilog_RTL_PLATFORM_AWSF1/mkD_MMU_Cache.v | 85,395 | module MODULE1(VAR443,
VAR371,
VAR68,
VAR423,
VAR26,
VAR341,
VAR428,
VAR182,
VAR434,
VAR124,
VAR282,
VAR398,
valid,
addr,
VAR205,
VAR350,
VAR109,
VAR259,
VAR335,
VAR494,
VAR135,
VAR236,
VAR37,
VAR351,
VAR405,
VAR209,
VAR265,
VAR386,
VAR140,
VAR437,
VAR110,
VAR104,
VAR233,
VAR170,
VAR291,
VAR383,
VAR264,
VAR89,
VAR476,
... | apache-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/db/ip/video_sys/submodules/video_sys_Video_In_Decoder.v | 8,259 | module MODULE1 (
clk,
reset,
VAR12,
VAR10,
VAR11,
VAR38,
VAR24,
VAR40,
VAR3,
VAR30,
VAR23,
VAR41,
VAR36,
VAR19
);
parameter VAR33 = 7;
parameter VAR4 = 15;
parameter VAR2 = 17;
parameter VAR39 = 1280;
input clk;
input reset;
input VAR12;
input [ 7: 0] VAR10;
input VAR11;
input VAR38;
input VAR24;
output VAR40;
output r... | gpl-2.0 |
ShepardSiegel/ocpi | rtl/mkFrameGate4B.v | 56,227 | module MODULE1(VAR222,
VAR40,
VAR345,
VAR325,
VAR147,
VAR173,
VAR39,
VAR252,
VAR301,
VAR56,
VAR225,
VAR271,
VAR17,
VAR163,
VAR14,
VAR226,
VAR340,
VAR342,
VAR102,
VAR251,
VAR214,
VAR145,
VAR118,
VAR135,
VAR228,
VAR352,
VAR45,
VAR331,
VAR77,
VAR297,
VAR262,
VAR138);
parameter [31 : 0] VAR88 = 32'b0;
parameter [0 : 0] VAR... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o311a/sky130_fd_sc_hd__o311a_4.v | 2,422 | module MODULE1 (
VAR3 ,
VAR11 ,
VAR9 ,
VAR12 ,
VAR1 ,
VAR8 ,
VAR6,
VAR2,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR11 ;
input VAR9 ;
input VAR12 ;
input VAR1 ;
input VAR8 ;
input VAR6;
input VAR2;
input VAR7 ;
input VAR4 ;
VAR5 VAR10 (
.VAR3(VAR3),
.VAR11(VAR11),
.VAR9(VAR9),
.VAR12(VAR12),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR6(... | apache-2.0 |
merckhung/zet | cores/sound/rtl/sound.v | 8,411 | module MODULE1 (
input VAR17,
input VAR3,
input [ 2:0] VAR14,
input [ 1:0] VAR26,
input [15:0] VAR1,
output [15:0] VAR24,
input VAR31,
input VAR23,
input VAR20,
output reg VAR25,
output VAR32,
output VAR30
);
reg [7:0] VAR12;
wire [3:0] VAR11 = {VAR14, VAR26[1]};
wire [7:0] VAR34 = VAR26[0] ? VAR1[7:0] : VAR1[15:8]; as... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211oi/sky130_fd_sc_lp__a211oi_1.v | 2,361 | module MODULE1 (
VAR1 ,
VAR11 ,
VAR5 ,
VAR6 ,
VAR7 ,
VAR2,
VAR9,
VAR10 ,
VAR3
);
output VAR1 ;
input VAR11 ;
input VAR5 ;
input VAR6 ;
input VAR7 ;
input VAR2;
input VAR9;
input VAR10 ;
input VAR3 ;
VAR8 VAR4 (
.VAR1(VAR1),
.VAR11(VAR11),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR9(VAR9),
.VAR10(VAR10),
.... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfstp/sky130_fd_sc_hdll__dfstp_1.v | 2,289 | module MODULE1 (
VAR5 ,
VAR9 ,
VAR2 ,
VAR1,
VAR8 ,
VAR7 ,
VAR10 ,
VAR4
);
output VAR5 ;
input VAR9 ;
input VAR2 ;
input VAR1;
input VAR8 ;
input VAR7 ;
input VAR10 ;
input VAR4 ;
VAR3 VAR6 (
.VAR5(VAR5),
.VAR9(VAR9),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR4(VAR4)
);
endmodule
module MODU... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o32a/sky130_fd_sc_ls__o32a.pp.blackbox.v | 1,417 | module MODULE1 (
VAR10 ,
VAR3 ,
VAR8 ,
VAR7 ,
VAR6 ,
VAR2 ,
VAR9,
VAR5,
VAR4 ,
VAR1
);
output VAR10 ;
input VAR3 ;
input VAR8 ;
input VAR7 ;
input VAR6 ;
input VAR2 ;
input VAR9;
input VAR5;
input VAR4 ;
input VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdfxbp/sky130_fd_sc_ls__sdfxbp.symbol.v | 1,434 | module MODULE1 (
input VAR8 ,
output VAR6 ,
output VAR4,
input VAR7,
input VAR3,
input VAR5
);
supply1 VAR9;
supply0 VAR2;
supply1 VAR10 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
asicguy/gplgpu | hdl/altera_project/ram_32_128x8_dp_be/ram_32_128x8_dp_be_bb.v | 8,625 | module MODULE1 (
VAR8,
VAR11,
VAR6,
VAR3,
VAR9,
VAR5,
VAR7,
VAR10,
VAR1,
VAR4,
VAR2);
input [2:0] VAR8;
input [4:0] VAR11;
input [3:0] VAR6;
input VAR3;
input VAR9;
input [127:0] VAR5;
input [31:0] VAR7;
input VAR10;
input VAR1;
output [127:0] VAR4;
output [31:0] VAR2;
endmodule | gpl-3.0 |
cfib/bf2hw | lib/bambu_io_hw/bambu_putchar.v | 3,146 | module MODULE1 (input VAR23, input reset, input VAR19, output reg VAR24, input [7:0] VAR18, output reg [7:0] VAR5, output reg VAR26, input VAR29);
reg VAR2;
wire [7:0] VAR10;
wire VAR8;
reg [7:0] VAR25;
reg VAR27;
wire VAR28;
VAR3 #(.VAR22(8))
VAR20 (.clk(VAR23), .reset(reset), .VAR15(VAR27), .VAR31(VAR2),
.VAR6(VAR8),... | gpl-3.0 |
iceman1001/proxmark3 | fpga/hi_sniffer.v | 1,333 | module MODULE1(
VAR23, VAR13, VAR22,
VAR14, VAR1, VAR11, VAR5, VAR20, VAR18,
VAR6, VAR17,
VAR10, VAR9, VAR12, VAR19,
VAR2, VAR21,
VAR15,
VAR16, VAR3, VAR4 );
input VAR23, VAR13, VAR22;
output VAR14, VAR1, VAR11, VAR5, VAR20, VAR18;
input [7:0] VAR6;
output VAR17;
input VAR12;
output VAR10, VAR9, VAR19;
input VAR2, VAR2... | gpl-2.0 |
Ribeiro/sd2snes | verilog/sd2snes/dac.v | 3,710 | module MODULE1(
input VAR25,
input VAR11,
input VAR10,
input[10:0] VAR32,
input[7:0] VAR12,
input[7:0] VAR37,
input VAR29,
input VAR2,
input reset,
output VAR15,
output VAR14,
output VAR1,
output VAR6,
output VAR16
);
reg[8:0] VAR30;
wire[8:0] VAR8 = VAR30;
wire[31:0] VAR35;
assign VAR16 = VAR30[8];
reg[7:0] VAR45;
reg... | gpl-2.0 |
nyaxt/dmix | mixer_t.v | 1,418 | module MODULE1;
reg clk;
reg rst;
reg [7:0] VAR3;
reg [(8*24-1):0] VAR1;
reg [1:0] VAR6;
VAR2 VAR4(
.clk(clk), .rst(rst), .VAR8(0),
.VAR3(VAR3), .VAR1(VAR1),
.VAR5({32'h01000000, 32'h02000000, 32'h03000000, 32'h04000000,
32'h05000000, 32'h06000000, 32'h07000000, 32'h08000000}),
.VAR6(VAR6));
parameter VAR7 = 10;
always... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfsbp/sky130_fd_sc_hs__dfsbp.functional.v | 1,850 | module MODULE1 (
VAR14 ,
VAR3 ,
VAR6 ,
VAR2 ,
VAR1 ,
VAR12 ,
VAR15
);
input VAR14 ;
input VAR3 ;
output VAR6 ;
output VAR2 ;
input VAR1 ;
input VAR12 ;
input VAR15;
wire VAR13;
wire VAR4 ;
not VAR10 (VAR4 , VAR15 );
VAR7 VAR9 VAR8 (VAR13 , VAR12, VAR1, VAR4, VAR14, VAR3);
buf VAR11 (VAR6 , VAR13 );
not VAR5 (VAR2 , VAR... | apache-2.0 |
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