repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/clkinvlp/sky130_fd_sc_hdll__clkinvlp.pp.blackbox.v | 1,281 | module MODULE1 (
VAR3 ,
VAR2 ,
VAR6,
VAR4,
VAR1 ,
VAR5
);
output VAR3 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR1 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/sdlclkp/sky130_fd_sc_ls__sdlclkp_1.v | 2,262 | module MODULE2 (
VAR8,
VAR4 ,
VAR6,
VAR7 ,
VAR1,
VAR3,
VAR2 ,
VAR9
);
output VAR8;
input VAR4 ;
input VAR6;
input VAR7 ;
input VAR1;
input VAR3;
input VAR2 ;
input VAR9 ;
VAR5 VAR10 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR7(VAR7),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR2(VAR2),
.VAR9(VAR9)
);
endmodule
module MODULE2 (
VAR... | apache-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/common/ad_mem_asym.v | 5,032 | module MODULE1 (
VAR4,
VAR7,
VAR11,
VAR15,
VAR8,
VAR3,
VAR2);
parameter VAR6 = 10;
parameter VAR9 = 256;
parameter VAR1 = 8;
parameter VAR12 = 64;
localparam VAR10 = 2**VAR6;
localparam VAR14 = 2**VAR1;
localparam VAR16 = (VAR10 > VAR14) ? VAR10 : VAR14;
localparam VAR5 = VAR9/VAR12;
input VAR4;
input VAR7;
input [VAR6... | gpl-3.0 |
scalable-networks/ext | uhd/fpga/usrp2/fifo/fifo_2clock.v | 5,188 | module MODULE1
(input VAR20, input [VAR13-1:0] VAR21, input VAR6, output VAR3, output [15:0] VAR1,
input VAR23, output [VAR13-1:0] VAR14, output VAR12, input VAR15, output [15:0] VAR17,
input VAR9);
wire [VAR8:0] VAR29, VAR5; wire VAR7, VAR4, write, read;
assign VAR3 = ~VAR7;
assign VAR12 = ~VAR4;
assign write = VAR6 &... | gpl-2.0 |
schelleg/pynq_tutorial | Pynq-Z1/vivado/pynq_tutorial/ip/arduino_io_switch_1.0/src/arduino_switch.v | 7,222 | module MODULE1(
input [31:0] VAR15, input [15:0] VAR84, input [15:0] VAR97, input [15:0] VAR123,
input [5:0] VAR120,
output [5:0] VAR47,
output [5:0] VAR28,
input [1:0] VAR102,
output [1:0] VAR98,
output [1:0] VAR67,
input [11:0] VAR49,
output [11:0] VAR40,
output [11:0] VAR116,
input VAR50,
output VAR103,
output VAR70... | bsd-3-clause |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/main_0.v | 379,619 | module MODULE1(VAR17,VAR24,VAR102,VAR68,VAR91,VAR57,VAR65,VAR87,VAR109,VAR108,VAR31,VAR11,clk,rst,VAR44,VAR40,VAR81,VAR36,VAR67,VAR5,VAR100,VAR4,VAR64,VAR56,VAR82,VAR46,VAR95,VAR34,VAR30,VAR54);
integer VAR32;
parameter VAR96 = 4'd0,
VAR104 = 4'd1,
VAR2 = 4'd2,
VAR10 = 4'd3,
VAR78 = 4'd4,
VAR49 = 4'd5,
read = 4'd6,
wri... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.v | 2,204 | module MODULE2 (
VAR5 ,
VAR7 ,
VAR2,
VAR3 ,
VAR8 ,
VAR9 ,
VAR1
);
output VAR5 ;
input VAR7 ;
input VAR2;
input VAR3 ;
input VAR8 ;
input VAR9 ;
input VAR1 ;
VAR6 VAR4 (
.VAR5(VAR5),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR5 ,
VAR7 ,
VAR2
);
output VA... | apache-2.0 |
trivoldus28/pulsarch-verilog | design/sys/iop/pads/pad_common/rtl/bw_io_dtl_flps.v | 2,093 | module MODULE1 (
VAR9, VAR12,
VAR13, clk, VAR10, VAR6
);
output [2:0] VAR9;
input [2:0] VAR13;
output VAR12;
input clk;
input VAR10;
input VAR6;
VAR3 VAR8 (
.VAR9 (VAR9[0]),
.VAR12 (VAR1),
.VAR4 (clk),
.VAR13 (VAR13[0]),
.VAR6 (VAR6),
.VAR2 (VAR10)
);
VAR3 VAR5 (
.VAR9 (VAR9[1]),
.VAR12 (VAR11),
.VAR4 (clk),
.VAR13 (VA... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.functional.pp.v | 2,194 | module MODULE1 (
VAR9 ,
VAR14 ,
VAR3 ,
VAR13 ,
VAR7 ,
VAR16 ,
VAR5 ,
VAR8
);
input VAR9 ;
input VAR14 ;
output VAR3 ;
input VAR13 ;
input VAR7 ;
input VAR16 ;
input VAR5 ;
input VAR8;
wire VAR15 ;
wire VAR2 ;
wire VAR20 ;
wire VAR12;
not VAR18 (VAR2 , VAR8 );
not VAR17 (VAR20 , VAR13 );
VAR6 VAR4 (VAR12, VAR7, VAR16, V... | apache-2.0 |
GLADICOS/SPACEWIRESYSTEMC | altera_work/spw_fifo_ulight/ulight_fifo/synthesis/submodules/ulight_fifo_hps_0_hps_io.v | 1,928 | module MODULE1 (
output wire [12:0] VAR4, output wire [2:0] VAR8, output wire VAR13, output wire VAR6, output wire VAR5, output wire VAR2, output wire VAR3, output wire VAR7, output wire VAR9, output wire VAR18, inout wire [7:0] VAR14, inout wire VAR1, inout wire VAR10, output wire VAR11, output wire VAR15, input wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4/sky130_fd_sc_ms__nor4.blackbox.v | 1,308 | module MODULE1 (
VAR3,
VAR4,
VAR9,
VAR7,
VAR2
);
output VAR3;
input VAR4;
input VAR9;
input VAR7;
input VAR2;
supply1 VAR8;
supply0 VAR6;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dfxtp/sky130_fd_sc_hd__dfxtp_1.v | 2,128 | module MODULE2 (
VAR2 ,
VAR6 ,
VAR5 ,
VAR7,
VAR8,
VAR9 ,
VAR1
);
output VAR2 ;
input VAR6 ;
input VAR5 ;
input VAR7;
input VAR8;
input VAR9 ;
input VAR1 ;
VAR4 VAR3 (
.VAR2(VAR2),
.VAR6(VAR6),
.VAR5(VAR5),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR9(VAR9),
.VAR1(VAR1)
);
endmodule
module MODULE2 (
VAR2 ,
VAR6,
VAR5
);
output VAR2 ... | apache-2.0 |
markusC64/1541ultimate2 | fpga/nios_c5/nios/synthesis/submodules/nios_mem_if_ddr2_emif_0_dmaster.v | 21,669 | module MODULE1 #(
parameter VAR20 = 0,
parameter VAR21 = 50000,
parameter VAR26 = 2
) (
input wire VAR30, input wire VAR19, output wire [31:0] VAR32, input wire [31:0] VAR14, output wire VAR2, output wire VAR25, output wire [31:0] VAR47, input wire VAR35, input wire VAR46, output wire [3:0] VAR34, output wire VAR24 );
... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/iso1p/sky130_fd_sc_lp__iso1p.behavioral.pp.v | 1,872 | module MODULE1 (
VAR13 ,
VAR7 ,
VAR2,
VAR12,
VAR6 ,
VAR3 ,
VAR1
);
output VAR13 ;
input VAR7 ;
input VAR2;
input VAR12;
input VAR6 ;
input VAR3 ;
input VAR1 ;
wire VAR11 ;
wire VAR9;
VAR10 VAR5 (VAR11 , VAR7, VAR12, VAR6 );
VAR10 VAR8 (VAR9, VAR2, VAR12, VAR6 );
or VAR4 (VAR13 , VAR11, VAR9);
endmodule | apache-2.0 |
DProvinciani/Arquitectura_TPF | Codigo_fuente/3-execution/third_step.v | 2,411 | module MODULE1(
input wire VAR24,
input wire [5:0] VAR33,
input wire VAR1,
input wire [1:0] VAR18,
input wire [1:0] VAR21,
input wire [31:0] VAR7,
input wire [31:0] VAR19,
input wire [31:0] VAR37,
input wire [4:0] VAR14,
input wire [4:0] VAR36,
input wire [31:0] VAR27,
input wire [31:0] VAR25,
output wire [31:0] VAR32,... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfsbp/sky130_fd_sc_ms__sdfsbp.functional.pp.v | 2,306 | module MODULE1 (
VAR4 ,
VAR8 ,
VAR16 ,
VAR3 ,
VAR9 ,
VAR18 ,
VAR7,
VAR10 ,
VAR21 ,
VAR14 ,
VAR1
);
output VAR4 ;
output VAR8 ;
input VAR16 ;
input VAR3 ;
input VAR9 ;
input VAR18 ;
input VAR7;
input VAR10 ;
input VAR21 ;
input VAR14 ;
input VAR1 ;
wire VAR20 ;
wire VAR13 ;
wire VAR17;
not VAR5 (VAR13 , VAR7 );
VAR11 VA... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21bai/sky130_fd_sc_hdll__o21bai.behavioral.v | 1,662 | module MODULE1 (
VAR7 ,
VAR9 ,
VAR10 ,
VAR14
);
output VAR7 ;
input VAR9 ;
input VAR10 ;
input VAR14;
supply1 VAR15;
supply0 VAR6;
supply1 VAR5 ;
supply0 VAR13 ;
wire VAR4 ;
wire VAR2 ;
wire VAR11;
not VAR12 (VAR4 , VAR14 );
or VAR8 (VAR2 , VAR10, VAR9 );
nand VAR1 (VAR11, VAR4, VAR2 );
buf VAR3 (VAR7 , VAR11 );
endmod... | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pipe_rate.v | 46,086 | module MODULE1 #
(
parameter VAR79 = "VAR38", parameter VAR82 = "VAR53", parameter VAR67 = "3.0", parameter VAR130 = "VAR20", parameter VAR24 = "VAR106", parameter VAR131 = "VAR38", parameter VAR85 = "VAR38", parameter VAR39 = "VAR106", parameter VAR89 = 4'd15
)
(
input VAR56,
input VAR133,
input VAR9,
input VAR21,
inp... | gpl-3.0 |
bigeagle/riffa | fpga/xilinx/vc709/riffa_wrapper_vc709.v | 34,640 | module MODULE1
parameter VAR125 = 128,
parameter VAR81 = 256,
parameter VAR53 = 5
)
(
input VAR309,
input VAR299,
input [VAR125-1:0] VAR229,
input [(VAR125/32)-1:0] VAR264,
input [VAR164-1:0] VAR228,
output VAR168,
input VAR199,
input VAR126,
input [VAR125-1:0] VAR133,
input [(VAR125/32)-1:0] VAR17,
input [VAR89-1:0] V... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlymetal6s2s/sky130_fd_sc_hs__dlymetal6s2s.blackbox.v | 1,285 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy_example_design/example_project/ddr3_s4_uniphy_example/submodules/rw_manager_ram_csr.v | 2,354 | module MODULE1 #(
parameter VAR13 = 32,
parameter VAR8 = 2,
parameter VAR20 = 4
) (
input VAR21,
input VAR17,
input VAR6,
input VAR7,
input VAR23,
input [(VAR13-1):0] VAR1,
input [(VAR8-1):0] VAR18,
input [(VAR8-1):0] VAR11,
output reg [(VAR13-1):0] VAR22,
output reg VAR15
);
localparam integer VAR19 = VAR13*VAR20;
reg... | lgpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffrnq/gf180mcu_fd_sc_mcu7t5v0__dffrnq_4.behavioral.v | 3,634 | module MODULE1( VAR11, VAR4, VAR29, VAR10 );
input VAR11, VAR4, VAR29;
output VAR10;
reg VAR3;
VAR14 VAR20(.VAR11(VAR11),.VAR4(VAR4),.VAR29(VAR29),.VAR10(VAR10),.VAR3(VAR3));
VAR14 VAR2(.VAR11(VAR11),.VAR4(VAR4),.VAR29(VAR29),.VAR10(VAR10),.VAR3(VAR3));
not VAR26(VAR27,VAR4);
and VAR30(VAR24,VAR29,VAR27);
and VAR13(VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a31o/sky130_fd_sc_lp__a31o.blackbox.v | 1,354 | module MODULE1 (
VAR1 ,
VAR8,
VAR9,
VAR7,
VAR5
);
output VAR1 ;
input VAR8;
input VAR9;
input VAR7;
input VAR5;
supply1 VAR3;
supply0 VAR6;
supply1 VAR2 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
545/Atari7800 | core/ag_6502/trunk/digger/ag_main.v | 4,887 | module MODULE1(input VAR4, input[10:0] VAR1, input VAR5, input VAR9, output[7:0] VAR8, input[7:0] VAR3);
reg[7:0] VAR2[0:2047];
reg[7:0] VAR6;
assign VAR8 = VAR5? VAR6: 8'VAR7; | gpl-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/icgtn/gf180mcu_fd_sc_mcu9t5v0__icgtn_4.functional.pp.v | 1,081 | module MODULE1( VAR6, VAR4, VAR2, VAR14, VAR1, VAR5, VAR9 );
input VAR2, VAR4, VAR6, VAR1, VAR5, VAR9;
output VAR14;
or VAR7( VAR13, VAR4, VAR6 );
VAR10( VAR3, 1'b0, 1'b0, VAR2, VAR13, VAR9 );
wire VAR11;
not VAR8( VAR11, VAR3 );
or VAR12( VAR14, VAR2, VAR11 );
endmodule | apache-2.0 |
hydai/Verilog-Practice | DigitalDesign/101062124_hw4/fifo.v | 1,538 | module MODULE1 (
input clk,
input VAR10,
input VAR23,
input VAR8,
input [7:0] VAR4,
output VAR6,
output VAR24,
output VAR16,
output VAR11,
output VAR15,
output [7:0] VAR20
);
wire [4:0] addr;
wire VAR3;
wire VAR22;
wire VAR25;
wire [7:0] VAR9;
VAR19 VAR2 (
.clk(clk),
.VAR10(VAR10),
.VAR23(VAR23),
.VAR8(VAR8),
.VAR6(VAR... | mit |
BilkentCompGen/GateKeeper | FPGA Application/VC709_Gen3x4If128/GateKeeper.srcs/riffa2.2/tx_port_buffer_128.v | 8,453 | module MODULE1 #(
parameter VAR26 = 9'd128,
parameter VAR38 = 512,
parameter VAR23 = VAR37((2**VAR37(VAR38))+1),
parameter VAR13 = 2,
parameter VAR35 = 2,
parameter VAR48 = 3,
parameter VAR14 = 3,
parameter VAR12 = 1
)
(
input VAR7,
input VAR16,
input VAR20, input [1:0] VAR45, input VAR33,
input [VAR26-1:0] VAR46, inpu... | gpl-3.0 |
chcbaram/Altera_DE0_nano_Exam | prj_niosii_abot/db/ip/niosii/submodules/niosii_timer_us.v | 6,291 | module MODULE1 (
address,
VAR30,
clk,
VAR8,
VAR10,
VAR7,
irq,
VAR9
)
;
output irq;
output [ 15: 0] VAR9;
input [ 2: 0] address;
input VAR30;
input clk;
input VAR8;
input VAR10;
input [ 15: 0] VAR7;
wire VAR27;
wire VAR20;
reg VAR5;
wire VAR26;
reg VAR4;
wire VAR18;
wire [ 31: 0] VAR28;
reg [ 31: 0] VAR24;
reg VAR21;
wi... | mit |
lvd2/zxevo | unsupported/solegstar/fpga/current/video/video_addrgen.v | 4,473 | module MODULE1(
input wire clk,
output reg [20:0] VAR35, input wire VAR34,
input wire VAR17, input wire VAR32, input wire VAR28,
input wire VAR6,
input wire VAR5, input wire VAR21, input wire VAR30, input wire VAR1, input wire VAR7, input wire VAR24, input wire VAR31, input wire VAR13,
output wire [ 2:0] VAR18 );
wire ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr.functional.v | 1,374 | module MODULE1 (
VAR3,
VAR5
);
output VAR3;
input VAR5;
wire VAR2;
buf VAR4 (VAR2, VAR5 );
buf VAR1 (VAR3 , VAR2 );
endmodule | apache-2.0 |
ptracton/Picoblaze | projects/uart_echo_pb/rtl/cpu.v | 2,791 | module MODULE1 (
VAR2, VAR13, VAR11, VAR14, VAR15,
clk, VAR17, interrupt, VAR9, VAR20
) ;
input clk;
input [7:0] VAR17;
output [7:0] VAR2;
output [7:0] VAR13;
output VAR11;
output VAR14;
input interrupt; output VAR15;
input VAR9;
input VAR20;
wire [11:0] address;
wire [17:0] VAR21;
wire [7:0] VAR13;
wire [7:0] VAR2;
wi... | mit |
onchipuis/mriscv_vivado | mriscv_vivado.srcs/sources_1/imports/uart/uart_rx.v | 4,765 | module MODULE1 #
(
parameter VAR7 = 8
)
(
input wire clk,
input wire rst,
output wire [VAR7-1:0] VAR17,
output wire VAR13,
input wire VAR16,
input wire VAR10,
output wire VAR4,
output wire VAR3,
output wire VAR22,
input wire [3:0] VAR18,
input wire [1:0] VAR5,
input wire [1:0] VAR19,
input wire [15:0] VAR6
);
reg [VAR7... | mit |
cheehieu/qm-fir-digital-filter-core | ISAAC/qmfir_documentation/jasons_v/QMFIR_uart_if.v | 5,170 | module MODULE1 (
VAR2, VAR32, VAR1, VAR12, VAR25, VAR29,
VAR21, VAR11, clk, VAR37, VAR30
);
output [31:0] VAR2;
output [13:0] VAR32;
output VAR1;
output VAR12;
output VAR25;
output VAR29;
input [23:0] VAR21;
input [23:0] VAR11;
input clk;
input VAR37;
input VAR30;
reg [15:0] VAR5;
reg [31:0] VAR2;
parameter VAR27 = 0;
... | gpl-2.0 |
deepakcu/maestro | fpga/DE4_Ethernet_0/src/sram.v | 9,330 | module MODULE1 (
VAR60,
VAR36,
VAR3,
VAR20,
VAR48,
VAR57,
VAR31);
input VAR60;
input [71:0] VAR36;
input [9:0] VAR3;
input VAR20;
input [9:0] VAR48;
input VAR57;
output [71:0] VAR31;
tri1 VAR60;
tri1 VAR20;
tri0 VAR57;
wire [71:0] VAR21;
wire [71:0] VAR31 = VAR21[71:0];
VAR37 VAR33 (
.VAR27 (VAR48),
.VAR11 (VAR60),
.VA... | apache-2.0 |
kernelpanics/Grad | Expanded-Hyperbolic-CORDIC/Verilog/UART/Transmisor.v | 2,473 | module MODULE1
parameter VAR3 = 8 , VAR17 = 16 )
(
input wire clk, reset,
input wire VAR6, VAR11,
input wire [7:0] din,
output reg VAR12=0,
output wire VAR4
);
localparam [1:0]
VAR9 = 2'b00,
VAR18 = 2'b01,
VAR13 = 2'b10,
VAR10 = 2'b11;
reg [1:0] VAR16=0, VAR19=0;
reg [3:0] VAR15=0, VAR7=0;
reg [2:0] VAR14=0, VAR2=0;
re... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/bufbuf/sky130_fd_sc_hdll__bufbuf.functional.v | 1,253 | module MODULE1 (
VAR4,
VAR3
);
output VAR4;
input VAR3;
wire VAR2;
buf VAR5 (VAR2, VAR3 );
buf VAR1 (VAR4 , VAR2 );
endmodule | apache-2.0 |
osrf/wandrr | firmware/motor_controller/fpga/pwm.v | 1,910 | module MODULE1
input [47:0] VAR33,
input [15:0] VAR39, output [2:0] VAR19,
output [2:0] VAR20);
wire [15:0] VAR2, VAR5;
wire VAR10 = VAR2 == 16'h0;
wire [15:0] VAR40; VAR7 #(16) VAR27(.VAR4(VAR4), .rst(1'b0), .en(VAR10), .VAR37(VAR17), .VAR24(VAR40));
VAR7 #(16) wr(.VAR4(VAR4), .rst(1'b0), .en(1'b1), .VAR37(VAR5), .VAR... | apache-2.0 |
FAST-Switch/fast | lib/hardware/platform/NetMagic08/cdp/asyn_64_1_bb.v | 5,901 | module MODULE1 (
VAR8,
VAR3,
VAR7,
VAR5,
VAR6,
VAR2,
VAR1,
VAR4);
input VAR8;
input [0:0] VAR3;
input VAR7;
input VAR5;
input VAR6;
input VAR2;
output [0:0] VAR1;
output VAR4;
tri0 VAR8;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/o21ai/sky130_fd_sc_hvl__o21ai.pp.blackbox.v | 1,363 | module MODULE1 (
VAR2 ,
VAR7 ,
VAR5 ,
VAR3 ,
VAR4,
VAR1,
VAR6 ,
VAR8
);
output VAR2 ;
input VAR7 ;
input VAR5 ;
input VAR3 ;
input VAR4;
input VAR1;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/nand2/sky130_fd_sc_hvl__nand2.functional.pp.v | 1,801 | module MODULE1 (
VAR8 ,
VAR12 ,
VAR10 ,
VAR9,
VAR5,
VAR3 ,
VAR13
);
output VAR8 ;
input VAR12 ;
input VAR10 ;
input VAR9;
input VAR5;
input VAR3 ;
input VAR13 ;
wire VAR6 ;
wire VAR2;
nand VAR4 (VAR6 , VAR10, VAR12 );
VAR1 VAR11 (VAR2, VAR6, VAR9, VAR5);
buf VAR7 (VAR8 , VAR2 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or4b/sky130_fd_sc_lp__or4b.functional.pp.v | 1,978 | module MODULE1 (
VAR13 ,
VAR17 ,
VAR4 ,
VAR10 ,
VAR5 ,
VAR9,
VAR8,
VAR7 ,
VAR12
);
output VAR13 ;
input VAR17 ;
input VAR4 ;
input VAR10 ;
input VAR5 ;
input VAR9;
input VAR8;
input VAR7 ;
input VAR12 ;
wire VAR15 ;
wire VAR11 ;
wire VAR16;
not VAR14 (VAR15 , VAR5 );
or VAR2 (VAR11 , VAR15, VAR10, VAR4, VAR17 );
VAR6 V... | apache-2.0 |
praveendath92/securePUF | ipcore_dir/emac_single/example_design/client/address_swap_module_8.v | 14,697 | module MODULE1 (
VAR5, VAR6, VAR12, VAR3, VAR7, VAR21, VAR13, VAR17, VAR30, VAR22, VAR19 );
input VAR5;
input VAR6;
input [7:0] VAR12;
input VAR3;
input VAR7;
input VAR21;
output [7:0] VAR13;
reg [7:0] VAR13;
output VAR17;
output VAR30;
output VAR22;
input VAR19;
reg VAR16; reg VAR28; wire [7:0] VAR9; reg [7:0] VAR25;
... | gpl-2.0 |
asicguy/gplgpu | hdl/de_temp/dex_alu.v | 15,838 | module MODULE1
(
input VAR73,
input VAR108,
input [4:0] VAR2,
input [15:0] VAR56,
input [15:0] VAR13,
input [15:0] VAR93,
input [15:0] VAR28,
input [4:0] VAR59,
input VAR106,
input VAR75,
input VAR65,
input VAR58,
input VAR19,
input VAR109,
input VAR52,
input VAR100,
input VAR119,
output [15:0] VAR103,
output [15:0] VA... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/hdl/elink-gold/debouncer.v | 1,640 | module MODULE1 (
VAR2,
clk, VAR3
);
parameter VAR5 = 20;
input clk; input VAR3; output VAR2;
wire VAR6;
wire VAR4;
reg [VAR5-1:0] counter;
wire VAR7;
VAR1 #(1) VAR1(.out (VAR4),
.in (VAR3),
.clk (clk),
.reset (1'b0));
always @ (posedge clk)
if(VAR4)
counter[VAR5-1:0]={(VAR5){1'b1}};
else if(VAR7)
counter[VAR5-1:0]=coun... | gpl-3.0 |
tmolteno/TART | hardware/FPGA/tart_spi/verilog/mfsr/mfsr32.v | 2,194 | module MODULE1
(
input [31:0] VAR1,
output [31:0] VAR3
);
wire #VAR2 VAR5 = VAR1[0]^VAR1[1];
wire #VAR2 VAR4 = VAR1[1]^VAR1[28];
assign VAR3 = {VAR1[30:2], VAR4, VAR5, VAR1[31]};
endmodule | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/or2/sky130_fd_sc_hdll__or2.behavioral.v | 1,348 | module MODULE1 (
VAR3,
VAR8,
VAR2
);
output VAR3;
input VAR8;
input VAR2;
supply1 VAR7;
supply0 VAR4;
supply1 VAR10 ;
supply0 VAR1 ;
wire VAR6;
or VAR9 (VAR6, VAR2, VAR8 );
buf VAR5 (VAR3 , VAR6 );
endmodule | apache-2.0 |
vipinkmenon/fpgadriver | src/hw/fpga/source/pcie_if/pcie_7x_v1_8_qpll_drp.v | 19,387 | module MODULE1 #
(
parameter VAR62 = "VAR70", parameter VAR29 = "3.0", parameter VAR13 = "VAR80", parameter VAR55 = 0, parameter VAR11 = 3'd6
)
(
input VAR34,
input VAR16,
input VAR37,
input VAR78,
input VAR31,
input VAR44,
input [15:0] VAR7,
input VAR39,
output [ 7:0] VAR75,
output VAR15,
output [15:0] VAR64,
output V... | mit |
alexforencich/verilog-ethernet | example/HTG9200/fpga_10g/rtl/i2c_master.v | 30,561 | module MODULE1 (
input wire clk,
input wire rst,
input wire [6:0] VAR112,
input wire VAR17,
input wire VAR88,
input wire VAR92,
input wire VAR91,
input wire VAR27,
input wire VAR104,
output wire VAR102,
input wire [7:0] VAR43,
input wire VAR7,
output wire VAR36,
input wire VAR114,
output wire [7:0] VAR78,
output wire V... | mit |
P3Stor/P3Stor | pcie/app/BAR0_WRAPPER.v | 8,108 | module MODULE1(
clk,
VAR36,
en,
VAR41,
VAR25,
VAR10,
VAR24,
VAR18,
VAR56,
VAR62,
VAR60,
VAR37,
VAR5,
VAR54,
VAR53,
VAR40,
VAR57,
VAR8,
VAR34,
VAR63,
VAR47,
VAR35,
VAR14,
VAR21,
VAR39,
VAR22,
VAR38,
VAR30,
VAR26,
VAR42,
VAR45,
VAR46,
VAR19,
VAR6,
VAR51,
VAR61,
VAR44,
VAR1,
VAR31,
VAR13,
VAR23,
VAR17,
VAR32,
VAR33,
VAR28... | gpl-2.0 |
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors- | DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/mux_41.v | 2,777 | module MODULE1(
input [1:0] sel,
input [3:0] VAR24,
input VAR10,
input VAR15,
input VAR8,
input VAR12,
input [3:0] VAR30,
input VAR5,
input VAR6,
input VAR7,
input VAR3,
input [3:0] VAR17,
input VAR29,
input VAR14,
input VAR28,
input VAR20,
input [3:0] VAR23,
input VAR2,
input VAR21,
input VAR22,
input VAR26,
output [3... | mit |
aap/pdp6 | verilog/membus_1_connect.v | 1,038 | module MODULE1(
input wire clk,
input wire reset,
input wire VAR21,
input wire VAR20,
input wire VAR9,
input wire VAR6,
input wire [21:35] VAR3,
input wire [18:21] VAR17,
input wire VAR14,
input wire [0:35] VAR11,
output wire VAR1,
output wire VAR19,
output wire [0:35] VAR16,
output wire VAR8,
output wire VAR13,
output... | mit |
RushangKaria/Xilinx_Spartan6_vModTFT_Nexys3 | Verilog/VideoTimingCtl.v | 7,969 | module MODULE1
(
input wire VAR2,
input wire VAR23,
input wire [VAR1-1:0] VAR12,
output wire VAR16,
output wire VAR10,
output wire VAR8,
output wire [31:0] VAR7,
output wire [31:0] VAR5
);
reg [31:0] VAR11;
reg [31:0] VAR22;
reg [31:0] VAR3;
reg [31:0] VAR24;
reg [31:0] VAR25;
reg [31:0] VAR14;
reg [31:0] VAR4;
reg [31... | gpl-3.0 |
olajep/oh | src/adi/hdl/library/xilinx/common/ad_data_in.v | 6,150 | module MODULE1 #(
parameter VAR8 = 0,
parameter VAR22 = 0,
parameter VAR54 = 1,
parameter VAR42 = 0,
parameter VAR27 = "VAR64") (
input VAR60,
input VAR52,
input VAR32,
output VAR37,
output VAR82,
input VAR23,
input VAR80,
input [ 4:0] VAR11,
output [ 4:0] VAR17,
input VAR49,
input VAR19,
output VAR78);
localparam VAR8... | mit |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/cpu/apu/apu_envelope_generator.v | 4,351 | module MODULE1
(
input VAR8, input VAR20, input VAR1, input [5:0] VAR14, input VAR7, input VAR11, output [3:0] VAR22 );
reg [5:0] VAR10;
wire [5:0] VAR18;
reg [3:0] VAR17, VAR13;
reg VAR5, VAR15;
always @(posedge VAR8)
begin
if (VAR20)
begin
VAR10 <= 6'h00;
VAR17 <= 4'h0;
VAR5 <= 1'b0;
end
else
begin
VAR10 <= VAR18;
VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o221ai/sky130_fd_sc_lp__o221ai.pp.symbol.v | 1,409 | module MODULE1 (
input VAR5 ,
input VAR9 ,
input VAR2 ,
input VAR7 ,
input VAR1 ,
output VAR8 ,
input VAR3 ,
input VAR6,
input VAR10,
input VAR4
);
endmodule | apache-2.0 |
chasingegg/Computer_Systems | CS334_computer organization lab/source/lab4_data_memory/data_memory.v | 1,122 | module MODULE1( VAR4,address,VAR5,VAR3,VAR7,VAR1);
input VAR4;
input [31:0] address;
input [31:0] VAR5;
input VAR3;
input VAR7;
output [31:0] VAR1;
reg [31:0] VAR2[0:127];
reg [31:0] VAR1;
integer VAR6;
begin | mit |
Koheron/zynq-sdk | fpga/cores/axis_lfsr_v1_0/axis_lfsr.v | 1,663 | module MODULE1 #
(
parameter integer VAR4 = 64,
parameter VAR5 = "VAR7"
)
(
input wire VAR2,
input wire VAR10,
input wire VAR11,
output wire [VAR4-1:0] VAR6,
output wire VAR1
);
reg [VAR4-1:0] VAR3, VAR14;
reg VAR13, VAR8;
always @(posedge VAR2)
begin
if(~VAR10)
begin
VAR3 <= 64'h5555555555555555;
VAR13 <= 1'b0;
end
el... | mit |
ultraembedded/altor32 | rtl/soc/dmem_mux3.v | 5,901 | module MODULE1
(
output reg [31:0] VAR1,
output reg [31:0] VAR24,
input [31:0] VAR15,
output reg [3:0] VAR22,
output reg VAR34,
output reg VAR30,
output reg VAR11,
output reg [2:0] VAR10,
input VAR8,
input VAR27,
output reg [31:0] VAR20,
output reg [31:0] VAR16,
input [31:0] VAR12,
output reg [3:0] VAR40,
output reg VA... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o21ai/sky130_fd_sc_ls__o21ai.functional.v | 1,434 | module MODULE1 (
VAR6 ,
VAR5,
VAR3,
VAR7
);
output VAR6 ;
input VAR5;
input VAR3;
input VAR7;
wire VAR4 ;
wire VAR1;
or VAR9 (VAR4 , VAR3, VAR5 );
nand VAR2 (VAR1, VAR7, VAR4 );
buf VAR8 (VAR6 , VAR1 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o32ai/sky130_fd_sc_hdll__o32ai.pp.symbol.v | 1,406 | module MODULE1 (
input VAR4 ,
input VAR1 ,
input VAR5 ,
input VAR6 ,
input VAR7 ,
output VAR2 ,
input VAR8 ,
input VAR9,
input VAR3,
input VAR10
);
endmodule | apache-2.0 |
f3zz3h/Embedded-Co-Design | ts7300_top_restored/ethernet/eth_txstatem.v | 10,478 | module MODULE1 (VAR23, VAR26, VAR44, VAR9, VAR48, VAR19, VAR6,
VAR13, VAR1, VAR29, VAR31, VAR40, VAR41, VAR30,
VAR18, VAR4, VAR33, VAR34, VAR8, VAR46, VAR12,
VAR35, VAR39, VAR38, VAR45, VAR36, VAR47,
VAR2, VAR14, VAR42, VAR37, VAR17, VAR24,
VAR3, VAR27, VAR25, VAR5, VAR32, VAR10,
VAR21, VAR28, VAR11, VAR49, VAR43, VAR1... | gpl-2.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/controllerperipheralhdladi_pcore/velocityControlHdl_Convert_Data_Type1.v | 1,114 | module MODULE1
(
VAR2,
VAR3
);
input signed [35:0] VAR2; output signed [35:0] VAR3;
wire signed [35:0] VAR1;
assign VAR1 = {VAR2[35], VAR2[35:1]};
assign VAR3 = VAR1;
endmodule | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a311o/sky130_fd_sc_ls__a311o.pp.symbol.v | 1,394 | module MODULE1 (
input VAR4 ,
input VAR9 ,
input VAR10 ,
input VAR5 ,
input VAR7 ,
output VAR1 ,
input VAR8 ,
input VAR2,
input VAR3,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/mux4/sky130_fd_sc_hs__mux4_4.v | 2,317 | module MODULE2 (
VAR4 ,
VAR5 ,
VAR11 ,
VAR1 ,
VAR8 ,
VAR2 ,
VAR3 ,
VAR9,
VAR10
);
output VAR4 ;
input VAR5 ;
input VAR11 ;
input VAR1 ;
input VAR8 ;
input VAR2 ;
input VAR3 ;
input VAR9;
input VAR10;
VAR6 VAR7 (
.VAR4(VAR4),
.VAR5(VAR5),
.VAR11(VAR11),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR9(VAR9),
.V... | apache-2.0 |
alexforencich/verilog-ethernet | example/VCU118/fpga_10g/rtl/mdio_master.v | 6,510 | module MODULE1 (
input wire clk,
input wire rst,
input wire [4:0] VAR41,
input wire [4:0] VAR9,
input wire [15:0] VAR26,
input wire [1:0] VAR7,
input wire VAR6,
output wire VAR12,
output wire [15:0] VAR44,
output wire VAR34,
input wire VAR39,
output wire VAR13,
input wire VAR11,
output wire VAR38,
output wire VAR22,
ou... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_amphy/alt_mem_ddrx_ecc_decoder_64_syn.v | 57,799 | module MODULE1
(
VAR39,
VAR212) ;
input [6:0] VAR39;
output [127:0] VAR212;
tri0 [6:0] VAR39;
wire [5:0] VAR140;
wire VAR86;
wire VAR120;
wire [127:0] VAR161;
wire [63:0] VAR192;
wire [63:0] VAR224;
wire [3:0] VAR15;
wire [3:0] VAR63;
wire [3:0] VAR117;
wire [3:0] VAR54;
wire [3:0] VAR24;
wire [3:0] VAR156;
wire [3:0] ... | lgpl-3.0 |
csturton/wirepatch | system/hardware/cores/fabric/ovl_ported/redundant/ovl_increment.v | 1,451 | module MODULE1 (VAR11, reset, enable, VAR18, VAR23);
parameter VAR14 = VAR21;
parameter VAR19 = 1;
parameter VAR16 = 1;
parameter VAR1 = VAR5;
parameter VAR4 = VAR7;
parameter VAR15 = VAR22;
parameter VAR6 = VAR20;
parameter VAR2 = VAR8;
parameter VAR17 = VAR13;
input VAR11, reset, enable;
input [VAR19-1:0] VAR18;
outp... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_mux_4to2/sky130_fd_sc_hdll__udp_mux_4to2.symbol.v | 1,335 | module MODULE1 (
input VAR2,
input VAR3,
input VAR5,
input VAR4,
output VAR1 ,
input VAR6,
input VAR7
);
endmodule | apache-2.0 |
bluespec/Flute | src_bsc_lib_RTL/SyncFIFO.v | 11,866 | module MODULE1(
VAR30,
VAR27,
VAR8,
VAR1,
VAR39,
VAR33,
VAR18,
VAR20,
VAR2
) ;
parameter VAR3 = 1 ;
parameter VAR35 = 2 ; parameter VAR6 = 1 ;
input VAR30 ;
input VAR27 ;
input VAR1 ;
input [VAR3 -1 : 0] VAR39 ;
output VAR33 ;
input VAR8 ;
input VAR18 ;
output VAR2 ;
output [VAR3 -1 : 0] VAR20 ;
wire [VAR6 : 0] VAR26 =... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/csrbrg/rtl/csrbrg.v | 1,944 | module MODULE1(
input VAR19,
input VAR8,
input [31:0] VAR4,
input [31:0] VAR10,
output reg [31:0] VAR17,
input VAR11,
input VAR14,
input VAR9,
output reg VAR18,
output reg [13:0] VAR12,
output reg VAR6,
output reg [31:0] VAR13,
input [31:0] VAR2
);
always @(posedge VAR19) begin
VAR17 <= VAR2;
end
reg VAR15;
always @(po... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o211a/sky130_fd_sc_hs__o211a.functional.pp.v | 1,937 | module MODULE1 (
VAR5,
VAR10,
VAR4 ,
VAR15 ,
VAR3 ,
VAR2 ,
VAR6
);
input VAR5;
input VAR10;
output VAR4 ;
input VAR15 ;
input VAR3 ;
input VAR2 ;
input VAR6 ;
wire VAR6 VAR7 ;
wire VAR9 ;
wire VAR12;
or VAR13 (VAR7 , VAR3, VAR15 );
and VAR8 (VAR9 , VAR7, VAR2, VAR6 );
VAR14 VAR1 (VAR12, VAR9, VAR5, VAR10);
buf VAR11 (V... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/alu.v | 169,027 | module MODULE1 (VAR5,VAR7,VAR4,VAR3,VAR1,VAR2,VAR8);
output [0:127] VAR2;
input [0:127] VAR5;
input [0:127] VAR7;
input [0:2] VAR4;
input [0:1] VAR3;
input [0:4] VAR1;
input [15:0] VAR8;
parameter VAR6 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR2;
always @(VAR5 or VAR7 or VAR4 or VAR3 or VAR1 or VAR8)
begi... | mit |
osrf/wandrr | firmware/motor_controller/fpga/sigma_delta.v | 4,487 | module MODULE1
(input VAR45, input VAR73, input VAR48, input VAR77,
output [15:0] VAR22, output VAR69,
output [15:0] VAR33, output VAR71);
wire VAR67; sync VAR7(.in(VAR73), .clk(VAR45), .out(VAR67));
wire VAR47;
sync VAR55(.in(VAR77), .clk(VAR45), .out(VAR47));
localparam VAR2 = 16;
localparam VAR46 = 32;
wire [VAR2-1:... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a222oi/sky130_fd_sc_ms__a222oi.behavioral.pp.v | 2,413 | module MODULE1 (
VAR18 ,
VAR8 ,
VAR21 ,
VAR5 ,
VAR23 ,
VAR13 ,
VAR16 ,
VAR2,
VAR11,
VAR9 ,
VAR1
);
output VAR18 ;
input VAR8 ;
input VAR21 ;
input VAR5 ;
input VAR23 ;
input VAR13 ;
input VAR16 ;
input VAR2;
input VAR11;
input VAR9 ;
input VAR1 ;
wire VAR14 ;
wire VAR22 ;
wire VAR15 ;
wire VAR7 ;
wire VAR4;
nand VAR20 ... | apache-2.0 |
davidkoltak/tawas-core | ip/tawas/rtl/tawas_rcn_master_buf.v | 2,282 | module MODULE1
(
input rst,
input clk,
input [68:0] VAR19,
output [68:0] VAR26,
input VAR4,
input [4:0] VAR9,
input wr,
input [3:0] VAR23,
input [23:0] addr,
input [31:0] VAR3,
output VAR5,
output VAR24,
output VAR25,
output [4:0] VAR2,
output [3:0] VAR11,
output [23:0] VAR17,
output [31:0] VAR1
);
parameter VAR22 = 0;... | mit |
DeadWitcher/amber-de0-nano | hw/vlog/ethmac/eth_registers.v | 36,422 | module MODULE1( VAR185, VAR126, VAR131, VAR77, VAR247, VAR176, VAR22,
VAR233, VAR279, VAR53, VAR284, VAR86,
VAR26, VAR40, VAR28, VAR234, VAR107,
VAR48, VAR248, VAR29, VAR110, VAR70, VAR121,
VAR249, VAR33, VAR242, VAR112, VAR196,
VAR186, VAR65, VAR94, VAR276, VAR166, VAR105,
VAR67, VAR173, VAR221, VAR42,
VAR147, VAR201,... | lgpl-2.1 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai211/gf180mcu_fd_sc_mcu9t5v0__oai211_1.behavioral.pp.v | 1,868 | module MODULE1( VAR3, VAR6, VAR8, VAR2, VAR7, VAR5, VAR10 );
input VAR8, VAR3, VAR2, VAR7;
inout VAR5, VAR10;
output VAR6;
VAR4 VAR9(.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR10(VAR10));
VAR4 VAR1(.VAR3(VAR3),.VAR6(VAR6),.VAR8(VAR8),.VAR2(VAR2),.VAR7(VAR7),.VAR5(VAR5),.VAR10(VAR10)); | apache-2.0 |
alexforencich/hdg2000 | fpga/lib/axis/rtl/axis_ll_bridge.v | 2,422 | module MODULE1 #
(
parameter VAR3 = 8
)
(
input wire clk,
input wire rst,
input wire [VAR3-1:0] VAR12,
input wire VAR9,
output wire VAR7,
input wire VAR8,
output wire [VAR3-1:0] VAR10,
output wire VAR6,
output wire VAR2,
output wire VAR11,
input wire VAR5
);
reg VAR4 = 1'b1;
always @(posedge clk or posedge rst) begin
i... | mit |
Obijuan/ACC | hw/roadmap/12-ACC2/ACC2.v | 11,466 | module MODULE2 (
input wire clk, input wire VAR58, input wire VAR51,
output wire VAR3, output wire VAR37,
output wire VAR6,
output wire VAR18,
output wire VAR66,
output wire VAR12,
output wire VAR27,
output wire VAR7 );
localparam VAR82 = 1'b1;
localparam VAR8 = 1'b0;
localparam VAR23 = 24; localparam VAR20 = 22; local... | gpl-3.0 |
tdaede/daala_zynq | daala_4x4_transpose_1.0/hdl/daala_4x4_transpose_v1_0_M00_AXIS.v | 14,376 | module MODULE1 #
(
parameter integer VAR1 = 32,
parameter integer VAR25 = 32
)
(
input wire VAR15,
input wire VAR21,
output wire VAR5,
output wire [VAR1-1 : 0] VAR17,
output wire [(VAR1/8)-1 : 0] VAR14,
output wire VAR19,
input wire VAR6
);
localparam VAR2 = 8;
function integer VAR8 (input integer VAR23);
begin
for(VAR... | bsd-2-clause |
cr88192/bgbtech_bjx1core | bwjx1c64a/ExOp64_3A.v | 17,180 | module MODULE1(
VAR65, reset,
VAR164, VAR67,
VAR72, VAR186,
VAR99, VAR126,
VAR7, VAR56,
VAR74, VAR84,
VAR136, VAR148,
VAR138,
VAR11, VAR80,
VAR27, VAR160,
VAR34, VAR113,
VAR37, VAR175,
VAR162, VAR103,
VAR188, VAR68,
VAR42, VAR193,
VAR96, VAR62,
VAR6, VAR20,
VAR195, VAR71,
VAR69, VAR151,
VAR114, VAR127,
VAR39, VAR53,
VA... | mit |
borti4938/sd2snes | verilog/sd2snes_obc1/obc1.v | 2,896 | module MODULE1(
input clk,
input enable,
input [7:0] VAR42,
output [7:0] VAR3,
input [12:0] VAR23,
input VAR35
);
reg [7:0] VAR13 [7:0];
wire [6:0] VAR30 = VAR13[6][6:0];
wire VAR19 = VAR13[5][0];
wire VAR9 = enable & ((VAR23 & 13'h1a00) == 13'h1800);
wire VAR5 = enable & ((VAR23 & 13'h1a00) == 13'h1a00);
wire VAR10 = ... | gpl-2.0 |
walkthetalk/fsref | ip/fscpu/src/include/RM_ctl.v | 2,436 | module MODULE1 # (
parameter integer VAR18 = 32,
parameter integer VAR9 = 32
) (
input wire clk,
input wire VAR7,
output reg VAR13,
input wire VAR2,
input wire [VAR9-1:0] VAR22,
input wire signed [VAR18-1:0] VAR21,
output wire VAR17 ,
input wire VAR15 ,
input wire VAR12 ,
input wire VAR3 ,
input wire VAR24 ,
input wire... | gpl-3.0 |
rbarzic/async_logic | async_lib/misc/sync_merge/sync_merge.v | 5,059 | module MODULE1 (
VAR33, VAR15, VAR21,
VAR34, VAR13, VAR27, VAR28
);
input VAR34;
output VAR33;
input VAR13;
output VAR15;
output VAR21;
input VAR27;
input VAR28;
wire clk;
wire VAR21;
wire VAR33;
wire VAR15;
localparam VAR11 = 2'b00;
localparam VAR25 = 2'b01;
localparam VAR32 = 2'b10;
localparam VAR4 = 2'b11;
reg [1:0]... | gpl-2.0 |
ShepardSiegel/ocpi | libsrc/hdl/ocpi/fpgaTop_alst4.v | 5,552 | module MODULE1 (
input wire VAR50, input wire VAR71, input wire VAR62, input wire VAR56, input wire [ 3:0] VAR17, output wire [ 3:0] VAR61,
input wire [ 7:0] VAR44, output wire [15:0] VAR72, input wire [15:0] VAR38, output wire [15:0] VAR36, output wire [19:0] VAR18, output wire [19:0] VAR47, output wire [ 3:0] VAR65, ... | lgpl-3.0 |
impedimentToProgress/ProbableCause | ddr2/cores/or1200/or1200_spram_256x21.v | 11,051 | module MODULE1(
VAR46, VAR43, VAR54,
clk, rst, VAR38, VAR29, VAR40, addr, VAR36, VAR21
);
parameter VAR45 = 8;
parameter VAR33 = 21;
input VAR46;
input [VAR4 - 1:0] VAR54;
output VAR43;
input clk; input rst; input VAR38; input VAR29; input VAR40; input [VAR45-1:0] addr; input [VAR33-1:0] VAR36; output [VAR33-1:0] VAR21... | mit |
andrewandrepowell/kernel-on-chip | hdl/projects/Nexys4/bd/ip/bd_mig_7series_0_0/bd_mig_7series_0_0/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_axi.v | 57,367 | module MODULE1 #
(
parameter VAR355 = 100,
parameter VAR193 = "135", parameter VAR284 = 64,
parameter VAR67 = "VAR387",
parameter VAR172 = "0", parameter VAR326 = 3, parameter VAR158 = 2, parameter VAR267 = "8", parameter VAR300 = "VAR20", parameter VAR262 = "VAR451", parameter VAR257 = 1, parameter VAR280 = 5,
paramet... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/or2b/sky130_fd_sc_lp__or2b.pp.symbol.v | 1,284 | module MODULE1 (
input VAR4 ,
input VAR2 ,
output VAR6 ,
input VAR7 ,
input VAR3,
input VAR1,
input VAR5
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.v | 2,477 | module MODULE2 (
VAR1 ,
VAR9,
VAR8,
VAR10 ,
VAR2 ,
VAR6,
VAR4,
VAR5 ,
VAR3
);
output VAR1 ;
input VAR9;
input VAR8;
input VAR10 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR5 ;
input VAR3 ;
VAR11 VAR7 (
.VAR1(VAR1),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR10(VAR10),
.VAR2(VAR2),
.VAR6(VAR6),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR3(VA... | apache-2.0 |
andrewandrepowell/zybo_petalinux | zybo_petalinux_vga/zybo_petalinux_vga.ip_user_files/bd/block_design/ipshared/digilent/axi_dispctrl_v1_0/hdl/mmcme2_drp.v | 15,777 | module MODULE1
parameter VAR93 = 5
)
(
input VAR12,
input VAR53,
input VAR20,
output reg VAR65,
input [35:0] VAR94,
input [35:0] VAR35,
input [13:0] VAR91,
input [39:0] VAR33,
input [9:0] VAR19,
input VAR22,
output VAR103,
output VAR99,
input VAR69,
output VAR67
);
localparam VAR40 = 100;
wire [38:0] VAR57 [12:0]; reg ... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15.functional.pp.v | 1,832 | module MODULE1 (
VAR12 ,
VAR7 ,
VAR4,
VAR2,
VAR5 ,
VAR9
);
output VAR12 ;
input VAR7 ;
input VAR4;
input VAR2;
input VAR5 ;
input VAR9 ;
wire VAR1 ;
wire VAR10;
buf VAR8 (VAR1 , VAR7 );
VAR6 VAR3 (VAR10, VAR1, VAR4, VAR2);
buf VAR11 (VAR12 , VAR10 );
endmodule | apache-2.0 |
csturton/wirepatch | system/hardware/cores/uart16550/bench/verilog/uart_log.v | 6,824 | module MODULE1;
parameter VAR22 = "";
integer VAR35;
integer VAR4;
reg VAR21;
integer VAR45;
integer VAR16;
VAR1 VAR21 = 1;
VAR1 VAR45 = 0;
VAR1 VAR16 = 0;
task VAR49;
output VAR50;
begin
VAR35 =
VAR4 =
if ((VAR35 == 0) || (VAR4 == 0))
VAR50 = 1'b0;
end
else
VAR50 = 1'b1;
end
endtask
task VAR11;
begin
VAR6;
VAR2(VAR35,... | mit |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_adcfifo/axi_adcfifo_rd.v | 8,380 | module MODULE1 (
VAR15,
VAR12,
VAR35,
VAR42,
VAR43,
VAR29,
VAR4,
VAR18,
VAR34,
VAR33,
VAR6,
VAR41,
VAR30,
VAR3,
VAR27,
VAR37,
VAR20,
VAR26,
VAR16,
VAR11,
VAR1,
VAR23,
VAR32,
VAR7,
VAR8,
VAR19,
VAR28,
VAR22,
VAR45);
parameter VAR9 = 512;
parameter VAR25 = 2;
parameter VAR39 = 16;
parameter VAR36 = 32'h00000000;
paramete... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/nor4b/sky130_fd_sc_ms__nor4b_1.v | 2,302 | module MODULE2 (
VAR5 ,
VAR11 ,
VAR3 ,
VAR9 ,
VAR8 ,
VAR7,
VAR10,
VAR6 ,
VAR1
);
output VAR5 ;
input VAR11 ;
input VAR3 ;
input VAR9 ;
input VAR8 ;
input VAR7;
input VAR10;
input VAR6 ;
input VAR1 ;
VAR4 VAR2 (
.VAR5(VAR5),
.VAR11(VAR11),
.VAR3(VAR3),
.VAR9(VAR9),
.VAR8(VAR8),
.VAR7(VAR7),
.VAR10(VAR10),
.VAR6(VAR6),
.... | apache-2.0 |
jmesmon/trifles | verilog/hw7/risc_spm.v | 12,553 | module MODULE3 #(parameter VAR43=8, VAR77=3, VAR22=2)
( input clk, rst);
wire [VAR77-1:0]VAR75;
wire [VAR22-1:0]VAR38;
wire VAR16;
wire [VAR43-1:0] VAR23, addr, VAR21, VAR67, VAR103;
wire VAR6, VAR105, VAR70, VAR10, VAR56, VAR30, VAR34;
wire VAR42, VAR46, VAR106;
wire write;
wire VAR59;
MODULE9 MODULE4(VAR23, VAR16, ad... | gpl-3.0 |
DougFirErickson/parallella-hw | fpga/old/emon/hdl/emon.v | 6,387 | module MODULE1 (
VAR43, VAR23, VAR2,
clk, reset, VAR33, VAR16, VAR29, VAR15,
VAR1, VAR12, VAR22,
VAR3, VAR32, VAR40,
VAR34, VAR20, VAR36,
VAR25, VAR6, VAR18
);
parameter VAR28 = 32; parameter VAR41 = 6;
input clk;
input reset;
input VAR33;
input VAR16;
input [19:0] VAR29;
input [VAR28-1:0] VAR15;
output [VAR28-1:0] VAR... | gpl-3.0 |
alexforencich/hdg2000 | fpga/rtl/reset_stretch.v | 1,716 | module MODULE1 #(
parameter VAR3 = 4
)(
input wire clk,
input wire VAR2,
output wire VAR1
);
reg VAR5 = 1;
reg [VAR3-1:0] VAR4 = 0;
assign VAR1 = VAR5;
always @(posedge clk or posedge VAR2) begin
if (VAR2) begin
VAR4 <= 0;
VAR5 <= 1;
end else begin
if (&VAR4) begin
VAR5 <= 0;
end else begin
VAR5 <= 1;
VAR4 <= VAR4 + 1;... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/oai222/gf180mcu_fd_sc_mcu9t5v0__oai222_4.functional.v | 1,909 | module MODULE1( VAR24, VAR14, VAR7, VAR22, VAR4, VAR11, VAR13 );
input VAR11, VAR13, VAR22, VAR4, VAR14, VAR7;
output VAR24;
wire VAR1;
not VAR19( VAR1, VAR11 );
wire VAR17;
not VAR25( VAR17, VAR13 );
wire VAR23;
and VAR10( VAR23, VAR1, VAR17 );
wire VAR6;
not VAR3( VAR6, VAR22 );
wire VAR12;
not VAR2( VAR12, VAR4 );
w... | apache-2.0 |
fpgasystems/Centaur | rtl/mem/spl_sdp_mem.v | 2,285 | module MODULE1 #(
parameter VAR7 = 32,
parameter VAR3 = 8
) (
input wire clk,
input wire VAR2,
input wire VAR1,
input wire [VAR3-1:0] VAR6,
input wire [VAR3-1:0] VAR4,
input wire [VAR7-1:0] din,
output reg [VAR7-1:0] dout
);
reg [VAR7-1:0] VAR5[0:2**VAR3-1];
reg [VAR7-1:0] VAR5[0:2**VAR3-1];
always @(posedge clk) begin... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a22oi/sky130_fd_sc_ls__a22oi_2.v | 2,352 | module MODULE2 (
VAR3 ,
VAR5 ,
VAR10 ,
VAR9 ,
VAR1 ,
VAR11,
VAR2,
VAR4 ,
VAR6
);
output VAR3 ;
input VAR5 ;
input VAR10 ;
input VAR9 ;
input VAR1 ;
input VAR11;
input VAR2;
input VAR4 ;
input VAR6 ;
VAR7 VAR8 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR11(VAR11),
.VAR2(VAR2),
.VAR4(VAR4),
.... | apache-2.0 |
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