repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
sam-falvo/kestrel | cores/KCP53K/processor/rtl/verilog/polaris.v | 13,914 | module MODULE2(
output VAR231,
output VAR114,
output [3:0] VAR137,
output [63:0] VAR120,
output VAR57,
output VAR158,
input VAR175,
input VAR238,
input [31:0] VAR39,
output [63:0] VAR83,
output VAR20,
input VAR118,
input [63:0] VAR141,
output [63:0] VAR84,
output [63:0] VAR197,
output VAR169,
output VAR152,
output VAR2... | mpl-2.0 |
comododragon/SHA256_FPGA | Full/Verilog/sha256_core.v | 15,378 | module MODULE1(
input wire clk,
input wire VAR68,
input wire VAR89,
input wire VAR49,
input wire VAR30,
input wire [511 : 0] VAR50,
output wire ready,
output wire [255 : 0] VAR71,
output wire VAR93
);
parameter VAR100 = 32'hc1059ed8;
parameter VAR20 = 32'h367cd507;
parameter VAR90 = 32'h3070dd17;
parameter VAR65 = 32'h... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/dfrtp/sky130_fd_sc_hdll__dfrtp_1.v | 2,345 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR8 ,
VAR5,
VAR10 ,
VAR3 ,
VAR4 ,
VAR1
);
output VAR7 ;
input VAR2 ;
input VAR8 ;
input VAR5;
input VAR10 ;
input VAR3 ;
input VAR4 ;
input VAR1 ;
VAR6 VAR9 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3),
.VAR4(VAR4),
.VAR1(VAR1)
);
endmodule
module MODU... | apache-2.0 |
fbalakirev/red-pitaya-notes | cores/axis_scaler_v1_0/axis_scaler.v | 1,519 | module MODULE1 #
(
parameter integer VAR4 = 14
)
(
input wire VAR3,
input wire VAR15,
input wire signed [VAR4-1:0] VAR14,
input wire signed [VAR4-1:0] VAR10,
input wire VAR8,
output wire VAR6,
input wire VAR12,
output wire signed [VAR4-1:0] VAR11,
output wire VAR1
);
reg signed [VAR4-1:0] VAR9,VAR5;
reg [VAR4*2-1:0] VA... | mit |
YuxuanLing/trunk | trunk/references/h265enc_v1.0/rtl/mc/mc_chroma_ip4x4.v | 5,097 | module MODULE1(
clk,
VAR10,
VAR8,
VAR15,
VAR14,
VAR11,
VAR9,
VAR7,
VAR21,
VAR27,
VAR12,
VAR31,
VAR6 ,
VAR2,
VAR25
);
input clk;
input VAR10;
input [5 :0] VAR8;
input VAR15;
input VAR14;
input [VAR23-1:0] VAR11;
input [VAR23-1:0] VAR9;
input [VAR23-1:0] VAR7;
input [VAR23-1:0] VAR21;
input [VAR23-1:0] VAR27;
input [VAR2... | gpl-3.0 |
Cognoscan/BoostDSP | verilog/src/math/XorShift128Plus.v | 3,888 | module MODULE1 (
input clk,
input rst,
input [127:0] VAR5,
input VAR14,
input read,
output reg VAR1,
output reg [63:0] VAR12
);
localparam VAR6 = 0;
localparam VAR4 = 1;
localparam VAR11 = 2;
localparam VAR10 = 3;
localparam VAR3 = 4;
localparam VAR2 = 5;
localparam VAR8 = 6;
reg [2:0] state;
reg [63:0] VAR13;
reg [63:... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a41o/sky130_fd_sc_ms__a41o.behavioral.v | 1,558 | module MODULE1 (
VAR10 ,
VAR4,
VAR2,
VAR11,
VAR6,
VAR13
);
output VAR10 ;
input VAR4;
input VAR2;
input VAR11;
input VAR6;
input VAR13;
supply1 VAR1;
supply0 VAR7;
supply1 VAR14 ;
supply0 VAR9 ;
wire VAR8 ;
wire VAR3;
and VAR12 (VAR8 , VAR4, VAR2, VAR11, VAR6 );
or VAR5 (VAR3, VAR8, VAR13 );
buf VAR15 (VAR10 , VAR3 );
... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/lpflow_clkbufkapwr/sky130_fd_sc_hd__lpflow_clkbufkapwr.pp.symbol.v | 1,370 | module MODULE1 (
input VAR7 ,
output VAR1 ,
input VAR5,
input VAR3 ,
input VAR6 ,
input VAR4 ,
input VAR2
);
endmodule | apache-2.0 |
VerticalResearchGroup/miaow | src/verilog/rtl/issue/sgpr_comparator.v | 5,375 | module MODULE1
(
VAR9,
VAR33, VAR37, VAR38,
VAR31, VAR13, VAR26, VAR7,
VAR45
);
wire VAR1, VAR42, VAR43, VAR28,
VAR5, VAR35;
input [3:0] VAR33;
wire [3:0] VAR22, VAR11, VAR25;
wire [2:0] VAR14, VAR15, VAR16;
input [VAR12-1:0] VAR37;
input [13:0] VAR38, VAR31, VAR13;
input [12:0] VAR26, VAR7, VAR45;
output [VAR41-1:0] V... | bsd-3-clause |
hakehuang/pycpld | ips/ip/spi_master_reduced/spi_master_reduced.v | 4,000 | module MODULE1(
clk,VAR11,
VAR7,VAR1,VAR3,
VAR5,VAR18,VAR14,VAR12
);
parameter VAR17 = 64;
input clk;
input VAR11;
input VAR7;
output VAR1;
output VAR3;
input VAR5;
output VAR12;
input VAR18;
input VAR14;
reg[8:0] VAR15;
reg[7:0] VAR13;
reg[7:0] VAR16;
reg[4:0] VAR10;
reg VAR9;
reg VAR20;
reg VAR19;
reg VAR12;
reg[7:0]... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvgnd/sky130_fd_sc_ls__tapvgnd.blackbox.v | 1,249 | module MODULE1 ();
supply1 VAR2;
supply0 VAR1;
supply1 VAR4 ;
supply0 VAR3 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or2/sky130_fd_sc_hd__or2.pp.blackbox.v | 1,254 | module MODULE1 (
VAR1 ,
VAR3 ,
VAR4 ,
VAR7,
VAR2,
VAR6 ,
VAR5
);
output VAR1 ;
input VAR3 ;
input VAR4 ;
input VAR7;
input VAR2;
input VAR6 ;
input VAR5 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.behavioral.v | 1,711 | module MODULE1 (
VAR9 ,
VAR7,
VAR2,
VAR14,
VAR15,
VAR5
);
output VAR9 ;
input VAR7;
input VAR2;
input VAR14;
input VAR15;
input VAR5;
supply1 VAR1;
supply0 VAR6;
supply1 VAR13 ;
supply0 VAR11 ;
wire VAR3 ;
wire VAR17 ;
wire VAR8;
nand VAR16 (VAR3 , VAR2, VAR7, VAR14 );
nand VAR10 (VAR17 , VAR5, VAR15 );
and VAR4 (VAR8,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/clkinvlp/sky130_fd_sc_lp__clkinvlp.pp.symbol.v | 1,286 | module MODULE1 (
input VAR2 ,
output VAR1 ,
input VAR5 ,
input VAR3,
input VAR4,
input VAR6
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/tapvpwrvgnd/sky130_fd_sc_ls__tapvpwrvgnd.functional.v | 1,067 | module MODULE1 ();
endmodule | apache-2.0 |
vipinkmenon/scas | hw/fpga/source/pcie_if/pcie_clocking_v6.v | 11,347 | module MODULE1 # (
parameter VAR68 = "VAR18",
parameter VAR34 = 8, parameter VAR92 = 4'h1, parameter VAR41 = 0, parameter VAR22 = 3
)
(
input wire VAR79,
input wire VAR125,
input wire VAR107,
input wire [1:0] VAR47,
output wire VAR16,
output wire VAR59,
output wire VAR52,
output wire VAR117,
output wire VAR106,
output ... | mit |
intelligenttoasters/CPC2.0 | FPGA/rtl/support_io_if.v | 4,778 | module MODULE1(
input VAR26,
input [7:0] VAR29,
input [7:0] VAR18,
output [7:0] VAR7,
input VAR20,
input VAR27,
input VAR28,
output VAR5,
output [3:0] VAR12,
output [15:0] VAR24, output [15:0] VAR30, output [7:0] VAR21, input [8*16-1:0] VAR9, input VAR31, output [15:0] VAR13, output [15:0] VAR33, output [7:0] VAR1, out... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/o21a/sky130_fd_sc_hdll__o21a.functional.pp.v | 2,018 | module MODULE1 (
VAR10 ,
VAR15 ,
VAR8 ,
VAR12 ,
VAR9,
VAR4,
VAR14 ,
VAR16
);
output VAR10 ;
input VAR15 ;
input VAR8 ;
input VAR12 ;
input VAR9;
input VAR4;
input VAR14 ;
input VAR16 ;
wire VAR11 ;
wire VAR3 ;
wire VAR5;
or VAR6 (VAR11 , VAR8, VAR15 );
and VAR2 (VAR3 , VAR11, VAR12 );
VAR13 VAR1 (VAR5, VAR3, VAR9, VAR4... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/a2111o/sky130_fd_sc_hs__a2111o_4.v | 2,321 | module MODULE2 (
VAR7 ,
VAR2 ,
VAR5 ,
VAR3 ,
VAR1 ,
VAR10 ,
VAR6,
VAR8
);
output VAR7 ;
input VAR2 ;
input VAR5 ;
input VAR3 ;
input VAR1 ;
input VAR10 ;
input VAR6;
input VAR8;
VAR9 VAR4 (
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR3(VAR3),
.VAR1(VAR1),
.VAR10(VAR10),
.VAR6(VAR6),
.VAR8(VAR8)
);
endmodule
module MODUL... | apache-2.0 |
MegabytePhreak/Verilog-Perl | verilog/parser_sv.v | 8,859 | package VAR11;
bit [7:0] VAR37;
bit [7:0] VAR2;
endpackage
module MODULE7 ();
VAR23 VAR14;
VAR20 VAR14 = 33ns; endmodule : MODULE7
interface VAR24 #(parameter VAR13 = 0);
logic VAR29;
logic [7:0] addr, VAR16[9];
modport VAR38(input VAR16, VAR22, output addr);
endinterface : VAR24
module MODULE5 (
VAR24 VAR27,
VAR24.MOD... | artistic-2.0 |
eda-globetrotter/MarcheProcessor | final/src/tosynth Folder/regfileww.v | 1,951 | module MODULE1(VAR13, VAR9, VAR6, VAR11, VAR1, VAR2,
VAR5, VAR10, VAR4, VAR3, clk);
output [0:127] VAR13, VAR9;
input [0:127] VAR6;
input clk;
input VAR4;
input VAR5, VAR10;
input [0:4] VAR2, VAR11, VAR1;
input [0:15] VAR3;
reg [0:127] VAR13, VAR9;
reg [0:127] VAR12 [0:31];
reg [0:127] VAR7, VAR8;
always @(posedge clk)... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/o31ai/sky130_fd_sc_hs__o31ai.functional.v | 1,919 | module MODULE1 (
VAR12,
VAR15,
VAR7 ,
VAR2 ,
VAR3 ,
VAR9 ,
VAR13
);
input VAR12;
input VAR15;
output VAR7 ;
input VAR2 ;
input VAR3 ;
input VAR9 ;
input VAR13 ;
wire VAR13 VAR10 ;
wire VAR6 ;
wire VAR8;
or VAR4 (VAR10 , VAR3, VAR2, VAR9 );
nand VAR1 (VAR6 , VAR13, VAR10 );
VAR5 VAR11 (VAR8, VAR6, VAR12, VAR15);
buf VAR... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvn/sky130_fd_sc_lp__einvn_2.v | 2,150 | module MODULE2 (
VAR6 ,
VAR7 ,
VAR2,
VAR5,
VAR1,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR7 ;
input VAR2;
input VAR5;
input VAR1;
input VAR3 ;
input VAR4 ;
VAR9 VAR8 (
.VAR6(VAR6),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR1(VAR1),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6 ,
VAR7 ,
VAR2
);
output VAR6 ;... | apache-2.0 |
rqou/openfpga | hdl/xc2c-model/ConfigurableEdgeFlipflop.v | 3,069 | module MODULE1(
VAR1, clk, VAR11, VAR6, VAR2, VAR13, VAR14, VAR9
);
input wire VAR1;
input wire clk;
input wire VAR11;
output wire VAR13;
input wire VAR6;
input wire VAR2;
input wire VAR14;
input wire VAR9;
wire VAR3;
VAR19 #(
.VAR10(1'b0)
) VAR15 (
.VAR8(VAR3),
.VAR16(clk),
.VAR17(VAR11 & VAR14),
.VAR7(VAR6 && VAR2==0... | lgpl-2.1 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dlxbn/sky130_fd_sc_hs__dlxbn.behavioral.v | 2,021 | module MODULE1 (
VAR1 ,
VAR16 ,
VAR2 ,
VAR10,
VAR13 ,
VAR12
);
output VAR1 ;
output VAR16 ;
input VAR2 ;
input VAR10;
input VAR13 ;
input VAR12 ;
wire VAR3 ;
wire VAR5 ;
wire VAR6;
wire VAR15 ;
reg VAR7 ;
wire VAR9 ;
wire 1 ;
not VAR14 (VAR3 , VAR6 );
VAR8 VAR11 (VAR5 , VAR15, VAR3, VAR7, VAR13, VAR12);
assign VAR9 = (... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/mux2i/sky130_fd_sc_lp__mux2i.blackbox.v | 1,291 | module MODULE1 (
VAR1 ,
VAR7,
VAR2,
VAR5
);
output VAR1 ;
input VAR7;
input VAR2;
input VAR5 ;
supply1 VAR6;
supply0 VAR4;
supply1 VAR3 ;
supply0 VAR8 ;
endmodule | apache-2.0 |
TalentlessAlpaca/Automated_Vacuum_Cleaner | Position/intr_clk_tst.v | 1,314 | module MODULE1;
reg clk;
reg en;
reg VAR3;
reg [31:0] VAR4;
wire [31:0] VAR7;
reg rst;
wire VAR2;
VAR5 VAR6 (
.clk(clk),
.en(en),
.VAR4(VAR4),
.VAR7(VAR7),
.VAR2(VAR2)
);
VAR1 counter(
.clk(clk),
.en(VAR3),
.rst(rst),
.VAR7(VAR7)
); | mit |
Elphel/x353 | ddr/ddr.v | 55,741 | module MODULE1 (VAR56, VAR79, VAR45, VAR92, VAR40, VAR77, VAR3, VAR105, VAR112, VAR29, VAR53, VAR119);
inout [VAR67 - 1 : 0] VAR56;
inout [VAR41 - 1 : 0] VAR79;
input [VAR25 - 1 : 0] VAR45;
input [1 : 0] VAR92;
input VAR40;
input VAR77;
input VAR3;
input VAR105;
input VAR112;
input VAR29;
input VAR53;
input [VAR72 - 1 ... | gpl-3.0 |
lfmunoz/vhdl | ip_blocks/axi_to_stellarip/vivado_prj/vivado_prj.srcs/sources_1/ip/axi_traffic_gen_0/axi_traffic_gen_v2_0/hdl/src/verilog/axi_traffic_gen_v2_0_slvram_v7.v | 8,318 | module MODULE1 #(
parameter VAR8 = "VAR6" ,
parameter VAR28 = 64 ,
parameter VAR19 = 1024 ,
parameter VAR26= 10 ,
parameter VAR12 = "VAR13"
) (
input VAR18 ,
input [VAR28/8-1:0] VAR24 ,
input [VAR26-1:0] VAR21 ,
input [VAR28-1:0] VAR15,
output [VAR28-1:0] VAR16,
input VAR29 ,
input [VAR28/8-1:0] VAR1 ,
input [VAR26-1:0... | mit |
GSejas/Dise-o-ASIC-FPGA-FPU | ASIC_FLOW/ASIC_KOA_1_cycles/integracion_fisica/front_end/source/KOA_1c.v | 5,671 | module MODULE1
(
input wire clk,
input wire rst,
input wire VAR21,
input wire [VAR36-1:0] VAR19,
input wire [VAR36-1:0] VAR16,
output reg [2*VAR36-1:0] VAR27
);
wire [1:0] VAR14;
wire [3:0] VAR8;
assign VAR14 = 2'b00;
assign VAR8 = 4'b0000;
wire [VAR36/2-1:0] VAR13;
wire [VAR36/2:0] VAR12;
wire [VAR36/2-3:0] VAR32;
wir... | gpl-3.0 |
briburrell/amica | device/scrypt_mono_pll/scrypt_mono_pll.srcs/sources_1/imports/scrypt_mono_pll/ztex_ufm1_15y1.v | 10,882 | module MODULE1 (VAR18, reset, select, VAR68, VAR104, VAR107, VAR89, VAR76, VAR50, VAR94, VAR11, read, write);
input VAR18, select, reset, VAR68, VAR104, VAR107, VAR89, VAR76, VAR50, VAR94, VAR11;
input [7:0] read;
output [7:0] write;
function integer VAR79; input integer VAR100;
begin
VAR100 = VAR100-1;
for (VAR79=0; V... | gpl-3.0 |
r2t2sdr/r2t2 | fpga/modules/adi_hdl/library/axi_ad9652/axi_ad9652_if.v | 6,922 | module MODULE1 (
VAR21,
VAR16,
VAR28,
VAR27,
VAR13,
VAR12,
VAR33,
VAR40,
VAR25,
VAR29,
VAR23,
VAR2,
VAR49,
VAR10,
VAR18,
VAR22,
VAR30,
VAR44,
VAR45,
VAR5);
parameter VAR26 = 0;
parameter VAR6 = "VAR41";
input VAR21;
input VAR16;
input [15:0] VAR28;
input [15:0] VAR27;
input VAR13;
input VAR12;
output VAR33;
output [15:... | gpl-3.0 |
sergev/vak-opensource | hardware/s3esk-openrisc/or1200/or1200_spram_64x24.v | 11,148 | module MODULE1(
VAR15, VAR10, VAR34,
clk, rst, VAR23, VAR46, VAR22, addr, VAR5, VAR36
);
parameter VAR43 = 6;
parameter VAR17 = 24;
input VAR15;
input [VAR21 - 1:0] VAR34;
output VAR10;
input clk; input rst; input VAR23; input VAR46; input VAR22; input [VAR43-1:0] addr; input [VAR17-1:0] VAR5; output [VAR17-1:0] VAR36;... | apache-2.0 |
trivoldus28/pulsarch-verilog | verif/env/cmp/monitor.v | 177,470 | module MODULE1(
clk, VAR5, VAR6
);
input clk;
input VAR5;
input VAR6;
integer VAR3, VAR1, VAR2, VAR4;
begin
end
begin | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a32o/sky130_fd_sc_hd__a32o_1.v | 2,469 | module MODULE1 (
VAR3 ,
VAR5 ,
VAR6 ,
VAR2 ,
VAR11 ,
VAR10 ,
VAR1,
VAR12,
VAR7 ,
VAR4
);
output VAR3 ;
input VAR5 ;
input VAR6 ;
input VAR2 ;
input VAR11 ;
input VAR10 ;
input VAR1;
input VAR12;
input VAR7 ;
input VAR4 ;
VAR9 VAR8 (
.VAR3(VAR3),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR2(VAR2),
.VAR11(VAR11),
.VAR10(VAR10),
.VAR1... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/clkdlyinv5sd1/sky130_fd_sc_ls__clkdlyinv5sd1.pp.blackbox.v | 1,344 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR6,
VAR4,
VAR1 ,
VAR3
);
output VAR5 ;
input VAR2 ;
input VAR6;
input VAR4;
input VAR1 ;
input VAR3 ;
endmodule | apache-2.0 |
HirokiNakahara/HLS_FPGA_NES | mariones_VerilogHDLs/NES.v | 5,839 | module MODULE1(
input VAR53,
input VAR18,
output VAR27,
output VAR35,
output [3:0]VAR4,
output [3:0]VAR3,
output [3:0]VAR9,
input [5:0]VAR11,
input VAR49,
input VAR25,
input VAR30,
input VAR16,
output [10:0]VAR31
);
wire [31:0]VAR21; wire [11:0]VAR19; wire [15:0]VAR40; wire VAR52;
wire [11:0]VAR15; wire [9:0]VAR36; wir... | mit |
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC | bin_Sobel_Filter/system/synthesis/submodules/acl_loop_limiter.v | 4,888 | module MODULE1 #(
parameter VAR25 = 8, VAR7 = 8, VAR23 = 100,
VAR6 = 0, VAR5 = (VAR7 == 0)? 1 : VAR7 )(
input VAR28,
input VAR1,
input [VAR25-1:0] VAR20,
input [VAR25-1:0] VAR16,
input [VAR5-1:0] VAR8,
input [VAR5-1:0] VAR15,
output [VAR25-1:0] VAR19,
output [VAR25-1:0] VAR31
);
localparam VAR18 = VAR21(VAR25 + 1);
loc... | mit |
alexforencich/xfcp | lib/eth/example/HXT100G/fpga/rtl/fpga.v | 27,713 | module MODULE1 (
input wire VAR245,
input wire VAR270,
input wire [1:0] VAR248,
input wire [3:0] VAR40,
output wire [3:0] VAR333,
output wire VAR55,
input wire VAR247,
output wire VAR10,
output wire VAR116,
input wire VAR182,
output wire VAR106,
input wire VAR313,
output wire VAR72,
input wire VAR29,
output wire VAR308... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/nand4bb/sky130_fd_sc_ls__nand4bb.behavioral.v | 1,532 | module MODULE1 (
VAR10 ,
VAR2,
VAR12,
VAR5 ,
VAR9
);
output VAR10 ;
input VAR2;
input VAR12;
input VAR5 ;
input VAR9 ;
supply1 VAR8;
supply0 VAR4;
supply1 VAR6 ;
supply0 VAR1 ;
wire VAR14;
wire VAR3;
nand VAR7 (VAR14, VAR9, VAR5 );
or VAR11 (VAR3, VAR12, VAR2, VAR14);
buf VAR13 (VAR10 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/ha/sky130_fd_sc_ms__ha.functional.pp.v | 2,194 | module MODULE1 (
VAR9,
VAR6 ,
VAR8 ,
VAR1 ,
VAR7,
VAR16,
VAR4 ,
VAR5
);
output VAR9;
output VAR6 ;
input VAR8 ;
input VAR1 ;
input VAR7;
input VAR16;
input VAR4 ;
input VAR5 ;
wire VAR12 ;
wire VAR14;
wire VAR13 ;
wire VAR18 ;
and VAR3 (VAR12 , VAR8, VAR1 );
VAR10 VAR11 (VAR14, VAR12, VAR7, VAR16);
buf VAR17 (VAR9 , VA... | apache-2.0 |
walkthetalk/fsref | ip/mutex_buffer/src/mutex_buffer.v | 3,497 | module MODULE1 #
(
parameter integer VAR17 = 32,
parameter integer VAR29 = 64,
parameter integer VAR10 = 2
) (
input wire clk,
input wire VAR11,
output wire VAR20,
input wire [VAR17-1:0] VAR5,
input wire [VAR17-1:0] VAR27,
input wire [VAR17-1:0] VAR1,
input wire [VAR17-1:0] VAR25,
input wire [VAR29-1:0] VAR3,
input wir... | gpl-3.0 |
joseluisquiroga/bj-actor-model | hlang/hgen_net/vlg_fnd/pakin.v | 1,575 | module MODULE1
VAR4=VAR9,
VAR26=VAR17,
VAR7=VAR14,
VAR1=VAR29,
VAR10=VAR3
)(
);
parameter VAR20 = VAR8;
parameter VAR5 = VAR13;
localparam VAR15 = ((VAR19 / VAR4) + 1);
localparam VAR12 = (((VAR30(VAR26)-1) >= 0)?(VAR30(VAR26)-1):(0));
localparam VAR16 = (((VAR30(VAR15)-1) >= 0)?(VAR30(VAR15)-1):(0));
reg [0:0] VAR27 =... | gpl-3.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-nexys4/project_1/project_1.srcs/sources_1/imports/sources/or1200/or1200_spram_2048x32_bw.v | 17,496 | module MODULE1(
VAR69, VAR13, VAR56,
clk, rst, VAR73, VAR18, VAR62, addr, VAR55, VAR77
);
input VAR69;
input [VAR20 - 1:0] VAR56; output VAR13;
input clk; input rst; input VAR73; input [3:0] VAR18; input VAR62; input [10:0] addr; input [31:0] VAR55; output [31:0] VAR77;
assign VAR13 = VAR69;
VAR58 VAR74(
VAR40 VAR74(
V... | gpl-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_alu_rglr.v | 4,845 | module MODULE1(
input VAR49, output VAR55,
input [VAR1-1:0] VAR35,
input [VAR1-1:0] VAR7,
input [VAR1-1:0] VAR36,
input [VAR31-1:0] VAR43,
input [VAR25-1:0] VAR47,
output VAR42, input VAR28, output [VAR1-1:0] VAR15,
output VAR4,
output VAR51,
output VAR23,
output VAR14,
output VAR34 ,
output VAR53 ,
output VAR6 ,
outpu... | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_regf.v | 2,842 | module MODULE1(
input VAR2,
input VAR18,
output reg VAR12,
output [31:0] VAR6,
output [31:0] VAR27,
input [31:0] VAR19,
input VAR24,
input [6:0] VAR32,
input [6:0] VAR3,
input [6:0] VAR4,
input VAR16,
input [6:0] VAR14,
output [31:0] VAR25,
input [31:0] VAR5,
input VAR7,
input [31:0] VAR21,
input [31:0] VAR20,
output V... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah.symbol.v | 1,260 | module MODULE1 (
input VAR6 ,
input VAR3 ,
input VAR5 ,
output VAR4,
output VAR1
);
supply1 VAR7;
supply0 VAR2;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hvl | cells/dfxbp/sky130_fd_sc_hvl__dfxbp_1.v | 2,234 | module MODULE1 (
VAR8 ,
VAR4 ,
VAR6 ,
VAR9 ,
VAR1,
VAR5,
VAR10 ,
VAR3
);
output VAR8 ;
output VAR4 ;
input VAR6 ;
input VAR9 ;
input VAR1;
input VAR5;
input VAR10 ;
input VAR3 ;
VAR7 VAR2 (
.VAR8(VAR8),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR9(VAR9),
.VAR1(VAR1),
.VAR5(VAR5),
.VAR10(VAR10),
.VAR3(VAR3)
);
endmodule
module MODUL... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/dfrtn/sky130_fd_sc_hs__dfrtn.symbol.v | 1,395 | module MODULE1 (
input VAR2 ,
output VAR5 ,
input VAR4,
input VAR3
);
supply1 VAR6;
supply0 VAR1;
endmodule | apache-2.0 |
BilkentCompGen/GateKeeper | FPGA_Application_v2/VC709_Gen3x4If128/GateKeeper.srcs/sources_1/ip/pcie3_7x_0/source/pcie3_7x_0_pcie_bram_7vx_cpl.v | 7,282 | module MODULE1 #(
parameter VAR35 = "VAR11", parameter VAR6 = "VAR8", parameter VAR28 = "500 VAR33", parameter VAR24 = "16 VAR9"
) (
input VAR45, input VAR12,
input [9:0] VAR18, input [9:0] VAR16, input [9:0] VAR19, input [9:0] VAR37, input [127:0] VAR14, input [15:0] VAR36, input VAR30, input VAR43, input VAR7, input ... | gpl-3.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig11/mig_7series_v1_1/user_design/rtl/ui/ui_cmd.v | 7,688 | module MODULE1 #
(
parameter VAR10 = 100,
parameter VAR27 = 33,
parameter VAR3 = 3,
parameter VAR31 = 12,
parameter VAR11 = 2,
parameter VAR38 = 16,
parameter VAR2 = 4,
parameter VAR19 = "VAR48"
)
(
VAR34, VAR15, VAR7, VAR17, VAR13, VAR33, VAR9, VAR14, VAR8,
VAR52, VAR30, VAR44,
rst, clk, VAR20, VAR36, VAR57, VAR50, VA... | lgpl-3.0 |
mballance/oc_wb_ip | rtl/wb_dma/bench/verilog/wb_mast_model.v | 10,981 | module MODULE1(clk, rst, VAR2, din, dout, VAR9, VAR7, sel, VAR3, ack, VAR1, VAR10);
input clk, rst;
output [31:0] VAR2;
input [31:0] din;
output [31:0] dout;
output VAR9, VAR7;
output [3:0] sel;
output VAR3;
input ack, VAR1, VAR10;
parameter VAR11 = 4096;
reg [31:0] VAR2;
reg [31:0] dout;
reg VAR9, VAR7;
reg [3:0] sel;... | apache-2.0 |
bit0fun/Fusion-Core | Fusion-Core-Base/and_32.v | 2,013 | module MODULE1(
input [31:0] VAR1, input [31:0] VAR2,
output [31:0] out );
assign out[0] = VAR1[0] & VAR2[0];
assign out[1] = VAR1[1] & VAR2[1];
assign out[2] = VAR1[2] & VAR2[2];
assign out[3] = VAR1[3] & VAR2[3];
assign out[4] = VAR1[4] & VAR2[4];
assign out[5] = VAR1[5] & VAR2[5];
assign out[6] = VAR1[6] & VAR2[6];
... | gpl-3.0 |
Feuerwerk/fpgaNES | master_pll/master_pll_0002.v | 6,478 | module MODULE1(
input wire VAR42,
input wire rst,
output wire VAR78,
output wire VAR53,
input wire [63:0] VAR118,
output wire [63:0] VAR33
);
VAR132 #(
.VAR120("false"),
.VAR18("50.0 VAR24"),
.VAR200(32),
.VAR191("1storder"),
.VAR147("VAR173"),
.VAR122(1),
.VAR123("26.600985 VAR24"),
.VAR49("0 VAR26"),
.VAR206(50),
.VA... | gpl-3.0 |
CospanDesign/python | game/panda/panda_path/example_project/rtl/bus/slave/wb_gpio.v | 10,141 | module MODULE1#(
parameter VAR18 = 0,
parameter VAR28 = 0,
parameter VAR33 = 0,
parameter VAR11 = 0
)(
input clk,
input rst,
input VAR37,
input VAR38,
input [3:0] VAR34,
input [31:0] VAR3,
input VAR7,
output reg VAR17,
output reg [31:0] VAR8,
input [31:0] VAR4,
output reg VAR31,
output reg [31:0] VAR24,
input [31:0] VA... | mit |
trevortheblack/NewLondo16 | Verilog/RFT/arithmetic.v | 1,159 | module MODULE1(VAR15, VAR8, VAR3, VAR12, VAR7, VAR13, VAR10);
input [31:0] VAR15, VAR8;
input [2:0] VAR3;
input [3:0] VAR12;
output reg [31:0] VAR7;
output [1:0] VAR13;
input VAR10;
always @ (*) begin
case(VAR3)
3'b010: VAR7 = VAR16;
3'b011: VAR7 = VAR16;
3'b100: VAR7 = VAR9;
3'b101: VAR7 = VAR5;
3'b110: VAR7 = VAR16;
... | mit |
trivoldus28/pulsarch-verilog | design/sys/iop/jbi/jbi_min/rtl/jbi_min_rq_tag.v | 13,869 | module MODULE1(
VAR14,
clk, VAR21, VAR29, VAR31, VAR34, VAR60,
VAR65, VAR5, VAR16, VAR56, VAR26
);
input clk;
input VAR21;
input VAR29;
input VAR31;
input VAR34;
input [VAR69-1:0] VAR60;
input [3:0] VAR65;
input VAR5;
input [VAR69-1:0] VAR16;
input VAR56;
input [3:0] VAR26;
output VAR14;
reg VAR14;
wire VAR45;
wire VAR... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o22a/sky130_fd_sc_ls__o22a.blackbox.v | 1,356 | module MODULE1 (
VAR2 ,
VAR9,
VAR4,
VAR6,
VAR7
);
output VAR2 ;
input VAR9;
input VAR4;
input VAR6;
input VAR7;
supply1 VAR8;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or2b/sky130_fd_sc_ls__or2b.pp.blackbox.v | 1,281 | module MODULE1 (
VAR2 ,
VAR1 ,
VAR3 ,
VAR5,
VAR6,
VAR7 ,
VAR4
);
output VAR2 ;
input VAR1 ;
input VAR3 ;
input VAR5;
input VAR6;
input VAR7 ;
input VAR4 ;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu9t5v0__clkbuf_8.behavioral.v | 1,108 | module MODULE1( VAR5, VAR4 );
input VAR5;
output VAR4;
VAR1 VAR3(.VAR5(VAR5),.VAR4(VAR4));
VAR1 VAR2(.VAR5(VAR5),.VAR4(VAR4)); | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/o31a/sky130_fd_sc_ls__o31a.behavioral.pp.v | 2,015 | module MODULE1 (
VAR11 ,
VAR4 ,
VAR17 ,
VAR1 ,
VAR3 ,
VAR14,
VAR7,
VAR8 ,
VAR15
);
output VAR11 ;
input VAR4 ;
input VAR17 ;
input VAR1 ;
input VAR3 ;
input VAR14;
input VAR7;
input VAR8 ;
input VAR15 ;
wire VAR6 ;
wire VAR12 ;
wire VAR5;
or VAR13 (VAR6 , VAR17, VAR4, VAR1 );
and VAR2 (VAR12 , VAR6, VAR3 );
VAR10 VAR16... | apache-2.0 |
ipburbank/Raster-Laser-Projector | src/Raster_Laser_Projector/synthesis/submodules/Raster_Laser_Projector_X_Axis_Subsystem.v | 4,065 | module MODULE1 (
input wire VAR41, input wire VAR20, input wire VAR57, input wire VAR11 );
wire VAR63;
VAR47 VAR48 (
.clk (VAR41), .reset (VAR63), .VAR35 (), .VAR31 () );
VAR5 #(
.VAR45 (1),
.VAR40 ("VAR66"),
.VAR46 (2),
.VAR43 (0),
.VAR61 (1),
.VAR70 (3),
.VAR68 (1),
.VAR50 (0),
.VAR30 (0),
.VAR49 (0),
.VAR51 (0),
.VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | models/udp_dlatch_pr/sky130_fd_sc_hdll__udp_dlatch_pr.blackbox.v | 1,299 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR4 ,
VAR3
);
output VAR1 ;
input VAR2 ;
input VAR4 ;
input VAR3;
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/sdffrnq/gf180mcu_fd_sc_mcu9t5v0__sdffrnq_4.functional.v | 1,728 | module MODULE1( VAR16, VAR22, VAR15, VAR9, VAR6, VAR21, VAR25 );
input VAR9, VAR15, VAR6, VAR16, VAR22, VAR25;
output VAR21;
not VAR2( VAR26, VAR6 );
wire VAR12;
not VAR4( VAR12, VAR15 );
wire VAR11;
not VAR3( VAR11, VAR16 );
wire VAR13;
and VAR1( VAR13, VAR12, VAR11 );
wire VAR23;
not VAR14( VAR23, VAR22 );
wire VAR5;... | apache-2.0 |
orbancedric/DeepGate | src/interface/custom/master_control.v | 10,436 | module MODULE1 (
input clk,
input rst,
input VAR17,
input VAR65,
input [7:0] VAR1,
output reg [7:0] VAR5 = 8'd0,
output reg VAR33 = 0,
input VAR11,
input VAR15,
input VAR24,
input [7:0] VAR59,
output reg [7:0] VAR42 = 8'd0,
output reg VAR55 = 0,
output reg VAR53 = 0,
input [VAR10 - 1'b1 : 0] VAR38,
output reg [VAR10 - ... | gpl-3.0 |
AmeerAbdelhadi/Dynamic-Frequency-Phase-Sweeping | bin2bcd9.v | 3,046 | module MODULE1 (
input [8 :0] VAR1, output reg [11:0] VAR2
);
reg [19:0] VAR3;
integer VAR4;
always @(VAR1) begin
for(VAR4 = 0; VAR4 <= 19; VAR4 = VAR4+1) VAR3[VAR4] = 0;
VAR3[11:3] = VAR1;
for(VAR4 = 0; VAR4 <= 5; VAR4 = VAR4+1) begin
if(VAR3[12:9 ] > 4) VAR3[12:9 ] = VAR3[12:9 ] + 3;
if(VAR3[16:13] > 4) VAR3[16:13] =... | bsd-3-clause |
MeshSr/onetswitch30 | ons30-app21-ref_switch/vivado/onets_7030_4x_ref_switch/ip/ref_switch_core/src/ip/reg_access_fifo.v | 15,536 | module MODULE1(
VAR254,
VAR323,
VAR273,
VAR386,
VAR179,
VAR108,
VAR269,
VAR23,
VAR455,
VAR335,
VAR167,
VAR230,
VAR351,
VAR51,
VAR277,
VAR115,
VAR125,
VAR160,
VAR117,
VAR330,
VAR410,
VAR244,
VAR170,
VAR233,
VAR157,
VAR40,
VAR361,
VAR256,
VAR239,
VAR293,
VAR408,
VAR228,
VAR70,
VAR105,
VAR50,
VAR217,
VAR314,
VAR400,
VAR28... | lgpl-2.1 |
bluespec/Flute | builds/RV64ACIMU_Flute_iverilog/Verilog_RTL/mkCSR_MIP.v | 7,574 | module MODULE1(VAR7,
VAR20,
VAR9,
VAR15,
VAR46,
VAR31,
VAR10,
VAR8,
VAR21,
VAR30,
VAR28,
VAR57);
input VAR7;
input VAR20;
input VAR9;
output [63 : 0] VAR15;
input [27 : 0] VAR46;
input [63 : 0] VAR31;
input VAR10;
output [63 : 0] VAR8;
input VAR21;
input VAR30;
input VAR28;
input VAR57;
wire [63 : 0] VAR8, VAR15;
reg V... | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/nand2/gf180mcu_fd_sc_mcu9t5v0__nand2_4.behavioral.v | 1,193 | module MODULE1( VAR2, VAR6, VAR5 );
input VAR5, VAR2;
output VAR6;
VAR4 VAR3(.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5));
VAR4 VAR1(.VAR2(VAR2),.VAR6(VAR6),.VAR5(VAR5)); | apache-2.0 |
kyzhai/NUNY | src/hardware/clock_pll.v | 17,310 | module MODULE1 (
input wire VAR5, input wire rst, output wire VAR4, output wire VAR3 );
VAR6 VAR1 (
.VAR5 (VAR5), .rst (rst), .VAR4 (VAR4), .VAR3 (VAR3), .VAR2 () );
endmodule | gpl-2.0 |
LordRafa/Sobel-FPGA | Project_With_Cache/ip/SIS/SIS.v | 6,884 | module MODULE1 (
input clk,
input rst,
output wire[VAR4-1:0] VAR54,
input VAR69,
output wire[VAR58-1:0] VAR64,
output wire VAR86,
output wire[VAR30-1:0] VAR26,
output wire[VAR57-1:0] VAR44,
output wire[VAR4-1:0] VAR35,
input VAR16,
input VAR32,
output wire[VAR58-1:0] VAR29,
output wire VAR62,
input wire[VAR30-1:0] VAR3... | gpl-2.0 |
shailcoolboy/Warp-Trinity | edk_user_repository/WARP/pcores/eeprom_v1_07_a/hdl/verilog/one_wire_interface.v | 13,367 | module MODULE1 (
VAR63, VAR11, VAR4, VAR19, VAR64, VAR25, VAR28, VAR23,
VAR60, VAR54, VAR58, VAR65, VAR45,
VAR48, VAR9, VAR26, VAR31, VAR14, VAR10, VAR15,
VAR16, VAR36, VAR20, VAR12, VAR7, VAR46, VAR1, VAR61, VAR21,
VAR3, VAR62, VAR29, VAR50, VAR55, VAR24, VAR2, VAR13,
VAR22, VAR41, VAR38, VAR49, VAR30, VAR39, VAR53, V... | bsd-2-clause |
ShepardSiegel/ocpi | coregen/pcie_4243_axi_k7_x4_250/source/pcie_7x_v1_3_pcie_bram_top_7x.v | 8,784 | module MODULE1
parameter VAR19 = "VAR36", parameter VAR1 = 0, parameter [3:0] VAR6 = 4'h1, parameter [5:0] VAR21 = 6'h08,
parameter VAR33 = 31, parameter VAR26 = 24, parameter VAR9 = 1, parameter VAR35 = 2, parameter VAR31 = 1,
parameter VAR32 = 'h1FFF, parameter VAR5 = 1, parameter VAR25 = 2, parameter VAR23 = 1 )
(
i... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | models/udp_dff_pr_pp_sn/sky130_fd_sc_hs__udp_dff_pr_pp_sn.symbol.v | 1,449 | module MODULE1 (
input VAR5 ,
output VAR4 ,
input VAR3 ,
input VAR1 ,
input VAR2 ,
input VAR6
);
endmodule | apache-2.0 |
jhoward321/pacman | usb_system/synthesis/usb_system.v | 49,415 | module MODULE1 (
input wire VAR143, input wire VAR23, output wire [12:0] VAR312, output wire [1:0] VAR65, output wire VAR17, output wire VAR228, output wire VAR111, inout wire [31:0] VAR105, output wire [3:0] VAR208, output wire VAR296, output wire VAR313, output wire [7:0] VAR199, inout wire [15:0] VAR158, output wire... | mit |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk_prog_full.v | 5,400 | module MODULE1(
rst,
VAR37,
VAR30,
din,
VAR54,
VAR10,
dout,
VAR34,
VAR13,
VAR3,
VAR38);
input rst;
input VAR37;
input VAR30;
input [35 : 0] din;
input VAR54;
input VAR10;
output [35 : 0] dout;
output VAR34;
output VAR13;
output VAR3;
output VAR38;
VAR105 #(
.VAR17(0),
.VAR22(0),
.VAR16(9),
.VAR52("VAR81"),
.VAR97(36),
... | gpl-2.0 |
asicguy/gplgpu | hdl/altera_ddr3/ddr3_int_example_top_3.v | 7,205 | module MODULE1 (
VAR10,
VAR9,
VAR69,
VAR8,
VAR42,
VAR14,
VAR31,
VAR38,
VAR20,
VAR68,
VAR3,
VAR6,
VAR58,
VAR2,
VAR24,
VAR56,
VAR63,
VAR19,
VAR54,
VAR18,
VAR66
)
;
output [ 13: 0] VAR69;
output [ 2: 0] VAR8;
output VAR42;
output [ 0: 0] VAR14;
inout [ 0: 0] VAR31;
inout [ 0: 0] VAR38;
output [ 0: 0] VAR20;
output [ 7: 0]... | gpl-3.0 |
lvd2/ngs | fpga/current/dma/dma_sd.v | 4,759 | module MODULE1
(
input wire clk,
input wire VAR18,
output wire VAR15,
input wire VAR29,
input wire [7:0] VAR33,
input wire [7:0] din, output reg [7:0] dout,
input wire VAR30, input wire VAR22, input wire [1:0] VAR37,
output reg [21:0] VAR4,
output wire [7:0] VAR35, output wire VAR27,
output wire VAR26,
input wire VAR25... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/dpram_64_32x32_be/dpram_64_32x32_be_bb.v | 8,112 | module MODULE1 (
VAR7,
VAR5,
VAR8,
VAR4,
VAR1,
VAR6,
VAR2,
VAR3);
input [63:0] VAR7;
input VAR5;
input [4:0] VAR8;
input [5:0] VAR4;
input [7:0] VAR1;
input VAR6;
input VAR2;
output [31:0] VAR3;
endmodule | gpl-3.0 |
silverneko/dsdl | lab2/Timer.v | 1,374 | module MODULE1(VAR1, VAR4, VAR3);
input VAR1;
input [2:0] VAR4;
output [31:0] VAR3;
reg [31:0] counter;
reg [1:0] state;
reg [31:0] VAR2;
assign VAR3 = VAR2; | mit |
DougFirErickson/parallella-hw | fpga/old/emesh_split/hdl/emesh_split.v | 3,543 | module MODULE1 (
VAR22, VAR19, VAR12, VAR5, VAR21,
VAR8, VAR1, VAR13, VAR16, VAR11,
VAR2, VAR15, VAR25, VAR6,
VAR20, VAR14,
VAR7, VAR4, VAR24, VAR3, VAR18,
VAR17, VAR10, VAR23, VAR9
);
input VAR7;
input VAR4;
input [1:0] VAR24;
input [3:0] VAR3;
input [31:0] VAR18;
input [31:0] VAR17;
input [31:0] VAR10;
output VAR22;
... | gpl-3.0 |
alexforencich/verilog-ethernet | example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v | 9,140 | module MODULE1 #
(
parameter VAR25 = 1,
parameter VAR44 = 64,
parameter VAR10 = (VAR44/8),
parameter VAR21 = 2,
parameter VAR33 = 0,
parameter VAR59 = 0,
parameter VAR67 = 0,
parameter VAR14 = 1,
parameter VAR52 = 8,
parameter VAR115 = 125000/6.4
)
(
input wire VAR118,
input wire VAR79,
output wire VAR101,
input wire V... | mit |
osrf/wandrr | firmware/motor_controller/fpga/usb_tx_token.v | 1,986 | module MODULE1
(input VAR20,
input [18:0] VAR1,
input VAR5,
output [7:0] VAR23,
output VAR25);
localparam VAR26 = 3'd0;
localparam VAR21 = 3'd1;
localparam VAR3 = 3'd2;
localparam VAR8 = 3'd3;
localparam VAR31=4, VAR17=5;
reg [VAR17+VAR31-1:0] VAR24;
wire [VAR31-1:0] state;
wire [VAR31-1:0] VAR19 = VAR24[VAR31+VAR17-1:... | apache-2.0 |
apotocnik/redpitaya_guide | cores/axis_averager_v1_0/axis_averager.v | 4,980 | module MODULE1 #
(
parameter integer VAR32 = 32,
parameter integer VAR11 = 32,
parameter integer VAR28 = 16, parameter integer VAR42 = 32
)
(
input wire VAR4,
input wire VAR23,
input wire VAR22,
input wire VAR35,
input wire [15:0] VAR38,
input wire [VAR42-1:0] VAR3,
output wire VAR29,
output wire [VAR42-1:0] VAR37,
out... | gpl-3.0 |
asicguy/gplgpu | hdl/altera_project/fifo_301x128/fifo_301x128_bb.v | 6,096 | module MODULE1 (
VAR4,
VAR8,
VAR10,
VAR5,
VAR6,
VAR3,
VAR1,
VAR9,
VAR2,
VAR7);
input [300:0] VAR4;
input VAR8;
input VAR10;
input VAR5;
input VAR6;
output [300:0] VAR3;
output VAR1;
output VAR9;
output VAR2;
output [6:0] VAR7;
endmodule | gpl-3.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_rst_ps7_0_100M_0/ip_design_rst_ps7_0_100M_0_stub.v | 1,866 | module MODULE1(VAR3, VAR2, VAR8,
VAR1, VAR9, VAR10, VAR4, VAR6,
VAR5, VAR7)
;
input VAR3;
input VAR2;
input VAR8;
input VAR1;
input VAR9;
output VAR10;
output [0:0]VAR4;
output [0:0]VAR6;
output [0:0]VAR5;
output [0:0]VAR7;
endmodule | mit |
hewittc/proxmark3lcd | fpga/fpga_hf.v | 6,723 | module MODULE1(
input VAR32, output VAR37, input VAR7, input VAR108,
input VAR102, input VAR33, input VAR98,
output VAR45, output VAR74,
output VAR58, output VAR19, output VAR28, output VAR93,
input [7:0] VAR72, output VAR92, output VAR65,
output VAR64, output VAR24, input VAR55, output VAR49,
input VAR38, input VAR4,
... | gpl-2.0 |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.v | 1,591 | module MODULE1 #(parameter [31:0] VAR10=1
,parameter VAR9=0
,parameter VAR8=0
,parameter VAR15=0
,parameter VAR7=0
)
( input [4:0][2:0] VAR3
, input VAR20
, input [VAR10-1:0][3:0][1:0] VAR2
, output VAR5
, output [VAR10-1:0] VAR17
, output [VAR10-1:0] VAR1
);
wire [VAR10:0] VAR13;
genvar VAR21;
for (VAR21 = 0; VAR21 < ... | bsd-3-clause |
scalable-networks/ext | uhd/fpga/usrp2/fifo/packet_padder36.v | 5,114 | module MODULE1
parameter VAR26 = 0,
parameter VAR35 = 4096,
parameter VAR24 = 65536
)
(
input clk, input reset,
input VAR22, input [7:0] VAR36, input [31:0] VAR6,
input [35:0] VAR9,
input VAR1,
output VAR5,
output [35:0] VAR7,
output VAR23,
input VAR14,
input VAR10
);
wire VAR25;
wire [15:0] VAR37;
VAR31 #(.VAR20(VAR26... | gpl-2.0 |
DreamSourceLab/DSLogic-hdl | src/sdramc/sdram_init.v | 2,282 | module MODULE1 (
input VAR2,
input VAR3,
output reg VAR1 = 0,
output reg VAR8
);
parameter
VAR6 = 16'h4000,
VAR5 = VAR6 >> 1;
reg [15:0] VAR7;
wire VAR4;
assign VAR4 = (VAR7 == VAR6);
always @(posedge VAR2) begin
if (!VAR3)
VAR7 <= 'b0;
end
else if (!VAR4)
VAR7 <= VAR7 + 1'b1;
end
always @(posedge VAR2) begin
VAR1 <= V... | gpl-2.0 |
atti92/heterogenhomework | project1/solution1/syn/verilog/fir_hw_mul_18s_15s_33_3.v | 1,415 | module MODULE2(clk, VAR10, VAR13, VAR9, VAR5);
input clk;
input VAR10;
input[18 - 1 : 0] VAR13; input[15 - 1 : 0] VAR9; output[33 - 1 : 0] VAR5;
reg signed [18 - 1 : 0] VAR2;
reg signed [15 - 1 : 0] VAR8;
wire signed [33 - 1 : 0] VAR1;
reg signed [33 - 1 : 0] VAR11;
assign VAR5 = VAR11;
assign VAR1 = VAR2 * VAR8;
alway... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfxbp/sky130_fd_sc_ms__sdfxbp.blackbox.v | 1,377 | module MODULE1 (
VAR7 ,
VAR8,
VAR2,
VAR1 ,
VAR4,
VAR9
);
output VAR7 ;
output VAR8;
input VAR2;
input VAR1 ;
input VAR4;
input VAR9;
supply1 VAR6;
supply0 VAR3;
supply1 VAR5 ;
supply0 VAR10 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a31oi/sky130_fd_sc_hdll__a31oi.functional.pp.v | 2,058 | module MODULE1 (
VAR16 ,
VAR5 ,
VAR9 ,
VAR14 ,
VAR8 ,
VAR15,
VAR6,
VAR13 ,
VAR1
);
output VAR16 ;
input VAR5 ;
input VAR9 ;
input VAR14 ;
input VAR8 ;
input VAR15;
input VAR6;
input VAR13 ;
input VAR1 ;
wire VAR4 ;
wire VAR2 ;
wire VAR3;
and VAR12 (VAR4 , VAR14, VAR5, VAR9 );
nor VAR11 (VAR2 , VAR8, VAR4 );
VAR17 VAR7 ... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/einvp/sky130_fd_sc_lp__einvp_2.v | 2,130 | module MODULE1 (
VAR5 ,
VAR4 ,
VAR6 ,
VAR1,
VAR7,
VAR3 ,
VAR2
);
output VAR5 ;
input VAR4 ;
input VAR6 ;
input VAR1;
input VAR7;
input VAR3 ;
input VAR2 ;
VAR8 VAR9 (
.VAR5(VAR5),
.VAR4(VAR4),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR7(VAR7),
.VAR3(VAR3),
.VAR2(VAR2)
);
endmodule
module MODULE1 (
VAR5 ,
VAR4 ,
VAR6
);
output VAR5... | apache-2.0 |
google/bbcpu | alu.v | 1,504 | module MODULE1(
input [VAR24-1 : 0] VAR16,
input [VAR24-1 : 0] VAR5,
input VAR3,
input VAR17,
input VAR2,
input [2 : 0] VAR14,
output [VAR24-1 : 0] VAR21,
output VAR20);
parameter VAR24 = 8;
wire [VAR24-1 : 0] VAR13;
wire VAR1;
wire [7 : 0] VAR4;
wire VAR22;
wire [7: 0] VAR8;
assign VAR21 = (VAR3) ? VAR8 :
(VAR2) ? VAR... | apache-2.0 |
gbraad/minimig-de1 | rtl/or1200/or1200_dmmu_top.v | 8,196 | module MODULE1(
clk, rst,
VAR7, VAR9, VAR18, VAR5, VAR6, VAR13,
VAR12, VAR22,
VAR38, VAR53, VAR35, VAR39, VAR30,
VAR34, VAR48, VAR20,
VAR29, VAR1, VAR21, VAR50, VAR23
);
parameter VAR4 = VAR52;
parameter VAR28 = VAR52;
input clk;
input rst;
input VAR7;
input VAR9;
input VAR18;
input [VAR28-1:0] VAR5;
input VAR6;
input ... | gpl-3.0 |
hitomi2500/wasca | fpga_firmware/wasca/synthesis/submodules/altera_onchip_flash.v | 11,386 | module MODULE1 (
VAR33,
VAR34,
VAR98,
VAR58,
VAR57,
VAR96,
VAR81,
VAR120,
VAR65,
VAR94,
VAR68,
VAR47,
VAR49,
VAR37,
VAR117
);
parameter VAR45 = "VAR107 10";
parameter VAR88 = "VAR85";
parameter VAR111 = "VAR54";
parameter VAR17 = "VAR54";
parameter VAR122 = "VAR54";
parameter VAR35 = "";
parameter VAR14 = "08";
paramet... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/tapvpwrvgnd/sky130_fd_sc_hd__tapvpwrvgnd.symbol.v | 1,239 | module MODULE1 ();
supply1 VAR4;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_auto_ds_0/synth/design_1_auto_ds_0.v | 16,099 | module MODULE1 (
VAR13,
VAR58,
VAR74,
VAR22,
VAR23,
VAR68,
VAR93,
VAR57,
VAR61,
VAR96,
VAR29,
VAR48,
VAR71,
VAR82,
VAR10,
VAR69,
VAR63,
VAR38,
VAR78,
VAR60,
VAR91,
VAR30,
VAR45,
VAR95,
VAR77,
VAR98,
VAR49,
VAR12,
VAR39,
VAR40,
VAR59,
VAR85,
VAR31,
VAR87,
VAR88,
VAR32,
VAR89,
VAR41,
VAR47,
VAR84,
VAR73,
VAR97,
VAR21,
VA... | mit |
ElegantLin/My-CPU | Small Program/Small Program.srcs/sources_1/imports/imports/sources_1/imports/Chapter11/mem.v | 12,438 | module MODULE1(
input wire rst,
input wire[VAR33] VAR16,
input wire VAR51,
input wire[VAR6] VAR24,
input wire[VAR6] VAR39,
input wire[VAR6] VAR53,
input wire VAR25,
input wire[VAR59] VAR58,
input wire[VAR6] VAR22,
input wire[VAR6] VAR13,
input wire[VAR6] VAR48,
input wire VAR2,
input wire VAR37,
input wire VAR21,
input... | gpl-3.0 |
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