repo_name stringlengths 6 79 | path stringlengths 4 249 | size int64 1.02k 768k | content stringlengths 15 207k | license stringclasses 14
values |
|---|---|---|---|---|
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sedfxbp/sky130_fd_sc_ms__sedfxbp.blackbox.v | 1,432 | module MODULE1 (
VAR7 ,
VAR6,
VAR5,
VAR11 ,
VAR10 ,
VAR1,
VAR3
);
output VAR7 ;
output VAR6;
input VAR5;
input VAR11 ;
input VAR10 ;
input VAR1;
input VAR3;
supply1 VAR8;
supply0 VAR2;
supply1 VAR4 ;
supply0 VAR9 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/or4/sky130_fd_sc_ls__or4.behavioral.v | 1,382 | module MODULE1 (
VAR10,
VAR12,
VAR4,
VAR9,
VAR11
);
output VAR10;
input VAR12;
input VAR4;
input VAR9;
input VAR11;
supply1 VAR1;
supply0 VAR6;
supply1 VAR7 ;
supply0 VAR2 ;
wire VAR3;
or VAR8 (VAR3, VAR11, VAR9, VAR4, VAR12 );
buf VAR5 (VAR10 , VAR3 );
endmodule | apache-2.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/02 verilog/ultrasonido_modulo_1/Periferico/peripherial_ultrsnd.v | 1,726 | module MODULE1 (clk , reset , din , VAR4 , addr , rd , wr, dout, VAR3, VAR7, VAR2, [15:0]VAR6);
input clk;
input rst;
input [15:0]din;
input VAR4;
input [3:0]addr; input rd;
input wr;
output reg [15:0]dout;
input VAR3;
output VAR2
reg [5:0] VAR5;
reg VAR3 = 0;
reg VAR2 = 0;
wire [15:0]VAR6;
wire VAR7;
VAR1 (.clk(clk),.... | gpl-3.0 |
hakehuang/pycpld | ips/ip/i2c_slave_subad/i2c_slave_op_subad.v | 16,234 | module MODULE1(
VAR34,
VAR61,
VAR1,
VAR37,
VAR40,
VAR62,
);
input VAR61;
input VAR34;
input VAR37;
input VAR40;
output VAR62;
reg VAR62;
output VAR1;
reg VAR41;
reg VAR52;
reg VAR59;
reg VAR50;
reg VAR49;
reg VAR26;
reg VAR33;
reg VAR11;
reg [7:0] VAR24;
reg [7:0] VAR17;
reg [7:0] VAR8;
reg [7:0] VAR9;
reg [6:0] VAR48;... | mit |
sh-chris110/chris | FPGA/chris.system.dma.ok/db/altera_mult_add_37p2.v | 22,159 | module MODULE1
(
VAR204,
VAR390,
VAR134,
VAR178,
VAR370,
VAR323) ;
input VAR204;
input VAR390;
input [15:0] VAR134;
input [15:0] VAR178;
input VAR370;
output [31:0] VAR323;
tri0 VAR204;
tri1 VAR390;
tri0 [15:0] VAR134;
tri0 [15:0] VAR178;
tri1 VAR370;
wire [31:0] VAR35;
VAR386 VAR138
(
.VAR204(VAR204),
.VAR378(),
.VAR3... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/edfxtp/sky130_fd_sc_ms__edfxtp.functional.v | 1,753 | module MODULE1 (
VAR8 ,
VAR10,
VAR6 ,
VAR4
);
output VAR8 ;
input VAR10;
input VAR6 ;
input VAR4 ;
wire VAR3 ;
wire VAR1;
VAR9 VAR12 (VAR1, VAR3, VAR6, VAR4 );
VAR7 VAR5 VAR11 (VAR3 , VAR1, VAR10 );
buf VAR2 (VAR8 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfrtp/sky130_fd_sc_lp__dfrtp.pp.symbol.v | 1,402 | module MODULE1 (
input VAR6 ,
output VAR3 ,
input VAR4,
input VAR1 ,
input VAR8 ,
input VAR2 ,
input VAR5 ,
input VAR7
);
endmodule | apache-2.0 |
insop/hyos | hyos_plb_v1_00_e/hdl/verilog/user_logic.v | 12,613 | module MODULE1
(
VAR3, VAR42, VAR20, VAR9, VAR15, VAR13, VAR37, VAR6, VAR24, VAR30 );
parameter VAR38 = 32;
parameter VAR32 = 8;
input VAR3;
input VAR42;
input [0 : VAR38-1] VAR20;
input [0 : VAR38/8-1] VAR9;
input [0 : VAR32-1] VAR15;
input [0 : VAR32-1] VAR13;
output [0 : VAR38-1] VAR37;
output VAR6;
output VAR24;
ou... | gpl-3.0 |
katherinejlu/ece3400 | code dump/Lab 4 FPGA Code/DE0_NANO3.v | 6,212 | module MODULE1(
VAR49,
VAR13,
VAR51,
VAR30,
VAR29,
VAR11,
VAR14,
VAR2,
);
localparam VAR26 = 25000000; localparam VAR32 = 8'b11111111;
localparam VAR47 = 8'b0;
localparam VAR40 = 8'b11110011;
localparam VAR45 = 8'b10011011;
input VAR49;
output [7:0] VAR13;
input [1:0] VAR51;
input [3:0] VAR30;
inout [33:0] VAR29;
input... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0 | cells/fill/gf180mcu_fd_sc_mcu9t5v0__fill_2.behavioral.pp.v | 1,069 | module MODULE1( VAR1, VAR4 );
inout VAR1, VAR4;
VAR3 VAR5(.VAR1(VAR1),.VAR4(VAR4));
VAR3 VAR2(.VAR1(VAR1),.VAR4(VAR4)); | apache-2.0 |
ShepardSiegel/ocpi | coregen/dram_k7_mig12/mig_7series_v1_2/example_design/rtl/traffic_gen/vio_init_pattern_bram.v | 12,010 | module MODULE1 #
(
parameter VAR12 = 100,
parameter VAR40 = 32'h00000000,
parameter VAR26 = 8,
parameter VAR37 = 4,
parameter VAR15 = 16,
parameter VAR4 = 8,
parameter VAR5 = VAR4
)
(
input VAR19,
input VAR42,
input VAR56,
input [31:0] VAR7, input VAR36, input [3:0] VAR44, input [31:0] VAR43, input [31:0] VAR16, input ... | lgpl-3.0 |
benreynwar/fpga-sdrlib | verilog/fft/qa_butterfly.v | 3,141 | module MODULE1
parameter VAR19 = 32,
parameter VAR4 = 1
)
(
input wire clk,
input wire VAR32,
input wire [VAR19-1:0] VAR29,
input wire VAR13,
input wire [VAR4-1:0] VAR30,
input wire [VAR16-1:0] VAR1,
input wire VAR2,
output reg [VAR19-1:0] VAR12,
output reg VAR27,
output reg [VAR4-1:0] VAR6,
output wire [VAR16-1:0] VAR... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/dffnq/gf180mcu_fd_sc_mcu7t5v0__dffnq_4.behavioral.pp.v | 2,214 | module MODULE1( VAR9, VAR6, VAR12, VAR2, VAR5 );
input VAR9, VAR6;
inout VAR2, VAR5;
output VAR12;
reg VAR3;
VAR13 VAR1(.VAR9(VAR9),.VAR6(VAR6),.VAR12(VAR12),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3));
VAR13 VAR7(.VAR9(VAR9),.VAR6(VAR6),.VAR12(VAR12),.VAR2(VAR2),.VAR5(VAR5),.VAR3(VAR3));
not VAR4(VAR8,VAR6);
buf VAR10(VAR11,... | apache-2.0 |
timothympace/SHA1-Verilog | sha1_compression.v | 1,186 | module MODULE1(
input [159:0] VAR10,
input [ 31:0] VAR4,
input [ 6:0] VAR15,
output [159:0] VAR3
);
reg [31:0] VAR5;
reg [31:0] VAR13;
wire [31:0] VAR16;
wire [31:0] VAR1 = VAR10[159:128];
wire [31:0] VAR14 = VAR10[127:96 ];
wire [31:0] VAR8 = VAR10[ 95:64 ];
wire [31:0] VAR2 = VAR10[ 63:32 ];
wire [31:0] VAR9 = VAR10[... | mit |
rbarzic/async_logic | misc_lib/std_cells.v | 3,956 | module MODULE11 (
VAR8,
VAR10
);
parameter VAR25 = 1;
input VAR10;
output VAR8;
assign #VAR25 VAR8 = !VAR10;
endmodule
module MODULE4 (
VAR24,
VAR10
);
parameter VAR25 = 1;
input VAR10;
output VAR24;
assign #VAR25 VAR24 = VAR10;
endmodule
module MODULE2 (
VAR24,
VAR2, VAR9
);
parameter VAR25 = 1;
input VAR2,VAR9;
outpu... | gpl-2.0 |
SiLab-Bonn/basil | basil/firmware/modules/tdc_s3/tdc_s3.v | 2,413 | module MODULE1 #(
parameter VAR26 = 16'h0000,
parameter VAR12 = 16'h0000,
parameter VAR17 = 16,
parameter VAR40 = 4,
parameter VAR23 = 4'b0100,
parameter VAR10 = 1,
parameter VAR19 = 1,
parameter VAR22 = 0
) (
input wire VAR34,
input wire [VAR17-1:0] VAR13,
inout wire [7:0] VAR1,
input wire VAR29,
input wire VAR4,
inpu... | bsd-3-clause |
cfangmeier/VFPIX-telescope-Code | DAQ_Firmware/src/ram/alt_mem_ddrx_burst_tracking.v | 3,799 | module MODULE1
parameter
VAR13 = 7,
VAR7 = 6,
VAR2 = 4
)
(
VAR11,
VAR10,
VAR3,
VAR9,
VAR14,
VAR1,
VAR12,
VAR8
);
input VAR11;
input VAR10;
input VAR3;
input VAR9;
output [VAR13-1:0] VAR14;
output [VAR13-1:0] VAR1;
input VAR12;
input [VAR2-1:0] VAR8;
wire VAR11;
wire VAR10;
wire VAR3;
wire VAR9;
wire [VAR13-1:0] VAR14;
... | gpl-2.0 |
tmatsuya/milkymist-ml401 | cores/vgafb/rtl/vgafb_fifo64to16.v | 1,766 | module MODULE1(
input VAR8,
input VAR6,
input VAR3,
input [63:0] VAR9,
output VAR11,
output reg [15:0] do,
input VAR2
);
reg [63:0] VAR10[0:3];
reg [1:0] VAR5;
reg [3:0] VAR1;
reg [4:0] VAR7;
wire [63:0] VAR4;
assign VAR4 = VAR10[VAR1[3:2]];
always @(*) begin
case(VAR1[1:0])
2'd0: do <= VAR4[63:48];
2'd1: do <= VAR4[47... | lgpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/a32oi/sky130_fd_sc_hdll__a32oi.symbol.v | 1,441 | module MODULE1 (
input VAR7,
input VAR10,
input VAR9,
input VAR8,
input VAR1,
output VAR2
);
supply1 VAR6;
supply0 VAR5;
supply1 VAR3 ;
supply0 VAR4 ;
endmodule | apache-2.0 |
nishtahir/arty-blaze | src/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_stub.v | 2,384 | module MODULE1(VAR10, VAR15, VAR9,
VAR7, VAR17, VAR1, VAR16, VAR12, VAR3,
VAR4, VAR20, VAR19, VAR13, VAR22, VAR2,
VAR23, VAR21, VAR5, VAR8, VAR6, VAR11, VAR14,
VAR18)
;
input VAR10;
input VAR15;
input [8:0]VAR9;
input VAR7;
output VAR17;
input [31:0]VAR1;
input [3:0]VAR16;
input VAR12;
output VAR3;
output [1:0]VAR4;
ou... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18.behavioral.pp.v | 1,832 | module MODULE1 (
VAR5 ,
VAR2 ,
VAR9,
VAR10,
VAR1 ,
VAR8
);
output VAR5 ;
input VAR2 ;
input VAR9;
input VAR10;
input VAR1 ;
input VAR8 ;
wire VAR7 ;
wire VAR4;
buf VAR12 (VAR7 , VAR2 );
VAR3 VAR6 (VAR4, VAR7, VAR9, VAR10);
buf VAR11 (VAR5 , VAR4 );
endmodule | apache-2.0 |
ECE492-Team5/Platform | soc-platform-quartusii/soc_system/synthesis/submodules/soc_system_button_pio.v | 4,519 | module MODULE1 (
address,
VAR3,
clk,
VAR9,
VAR13,
VAR15,
VAR14,
irq,
VAR12
)
;
output irq;
output [ 31: 0] VAR12;
input [ 1: 0] address;
input VAR3;
input clk;
input [ 3: 0] VAR9;
input VAR13;
input VAR15;
input [ 31: 0] VAR14;
wire VAR6;
reg [ 3: 0] VAR11;
reg [ 3: 0] VAR7;
wire [ 3: 0] VAR4;
reg [ 3: 0] VAR2;
wire VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/sdfrtp/sky130_fd_sc_ms__sdfrtp_2.v | 2,583 | module MODULE2 (
VAR11 ,
VAR3 ,
VAR5 ,
VAR9 ,
VAR4 ,
VAR1,
VAR8 ,
VAR10 ,
VAR6 ,
VAR12
);
output VAR11 ;
input VAR3 ;
input VAR5 ;
input VAR9 ;
input VAR4 ;
input VAR1;
input VAR8 ;
input VAR10 ;
input VAR6 ;
input VAR12 ;
VAR2 VAR7 (
.VAR11(VAR11),
.VAR3(VAR3),
.VAR5(VAR5),
.VAR9(VAR9),
.VAR4(VAR4),
.VAR1(VAR1),
.VAR8... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/xnor2/sky130_fd_sc_hs__xnor2.symbol.v | 1,265 | module MODULE1 (
input VAR5,
input VAR3,
output VAR2
);
supply1 VAR1;
supply0 VAR4;
endmodule | apache-2.0 |
secworks/aes | src/rtl/aes_core.v | 10,557 | module MODULE1(
input wire clk,
input wire VAR35,
input wire VAR43,
input wire VAR16,
input wire VAR17,
output wire ready,
input wire [255 : 0] VAR19,
input wire VAR46,
input wire [127 : 0] VAR29,
output wire [127 : 0] VAR26,
output wire VAR3
);
localparam VAR31 = 2'h0;
localparam VAR38 = 2'h1;
localparam VAR6 = 2'h2;
... | bsd-2-clause |
litex-hub/pythondata-cpu-blackparrot | pythondata_cpu_blackparrot/system_verilog/black-parrot/external/basejump_stl/bsg_fsb/bsg_front_side_bus_hop_in.v | 2,424 | module MODULE1
, parameter VAR12=2
)
(input VAR5
, input VAR21
, output VAR9
, input VAR6
, input [VAR17-1:0] VAR7
, output [VAR12-1:0] VAR16
, output [VAR12-1:0] [VAR17-1:0] VAR3
, input [VAR12-1:0] VAR1
);
logic [VAR12-1:0] VAR4, VAR10;
genvar VAR14;
logic [VAR12-1:0] VAR8;
logic [VAR17-1:0] VAR20;
wire VAR2, VAR22;
... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/or3b/sky130_fd_sc_hd__or3b.pp.blackbox.v | 1,308 | module MODULE1 (
VAR2 ,
VAR5 ,
VAR1 ,
VAR4 ,
VAR3,
VAR7,
VAR6 ,
VAR8
);
output VAR2 ;
input VAR5 ;
input VAR1 ;
input VAR4 ;
input VAR3;
input VAR7;
input VAR6 ;
input VAR8 ;
endmodule | apache-2.0 |
zaqwes8811/hdl-fpga | ip-cores/rtl_vlog/shift_reg_lib.v | 4,297 | module MODULE2(
clk, rst, VAR17,
VAR5,
din,
VAR19,
dout,
VAR18
);
parameter VAR12 = 2; input clk, rst, VAR17;
input VAR5;
input [VAR11-1:0] din; output [VAR11-1:0] dout; input [VAR11*VAR12-1:0] VAR19; output [VAR11*VAR12-1:0] VAR18;
wire [VAR11-1:0] VAR4 [VAR12-1:0];
VAR1
VAR9(
.clk(clk), .rst(rst), .VAR17(VAR17),
.VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a32oi/sky130_fd_sc_ls__a32oi.functional.pp.v | 2,238 | module MODULE1 (
VAR2 ,
VAR9 ,
VAR14 ,
VAR3 ,
VAR6 ,
VAR12 ,
VAR20,
VAR10,
VAR8 ,
VAR13
);
output VAR2 ;
input VAR9 ;
input VAR14 ;
input VAR3 ;
input VAR6 ;
input VAR12 ;
input VAR20;
input VAR10;
input VAR8 ;
input VAR13 ;
wire VAR17 ;
wire VAR11 ;
wire VAR19 ;
wire VAR16;
nand VAR4 (VAR17 , VAR14, VAR9, VAR3 );
nand... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/edfxtp/sky130_fd_sc_ls__edfxtp.symbol.v | 1,424 | module MODULE1 (
input VAR7 ,
output VAR6 ,
input VAR4 ,
input VAR3
);
supply1 VAR1;
supply0 VAR8;
supply1 VAR5 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/a22oi/sky130_fd_sc_ms__a22oi.symbol.v | 1,371 | module MODULE1 (
input VAR8,
input VAR1,
input VAR4,
input VAR3,
output VAR9
);
supply1 VAR5;
supply0 VAR7;
supply1 VAR6 ;
supply0 VAR2 ;
endmodule | apache-2.0 |
Darkin47/Zynq-TX-UTT | Vivado/Hist_Stretch/Hist_Stretch.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_data_fifo_v2_1/hdl/verilog/axi_data_fifo_v2_1_ndeep_srl.v | 5,193 | module MODULE1 #
(
parameter VAR11 = "VAR14", parameter VAR5 = 1 )
(
input wire VAR21, input wire [VAR5-1:0] VAR32, input wire VAR4, input wire VAR12, output wire VAR34 );
localparam integer VAR7 = 5;
localparam integer VAR18 = 32;
localparam integer VAR17 = (VAR5>VAR7) ? (2**(VAR5-VAR7)) : 1;
localparam integer VAR23 ... | gpl-3.0 |
Fabeltranm/FPGA-Game-D1 | HW/RTL/08ULTRASONIDO/Version_01/02 verilog/ultrasonido_modulo_1/Periferico/dpram.v | 1,486 | module MODULE1 #(
parameter VAR4 = 13,
parameter VAR12 = 16,
parameter VAR13 = "none"
) (
input VAR1,
input VAR6,
input VAR3,
input [VAR4-1:0] VAR15,
input [VAR12-1:0] VAR9,
input VAR11,
input [VAR4-1:0] VAR7,
output reg [VAR12-1:0] VAR8,
output reg [VAR12-1:0] VAR14,
input VAR5
);
parameter VAR10 = (1 << VAR4);
reg [V... | gpl-3.0 |
combinatorylogic/soc | backends/small1/hw/soc/atlys/spi.v | 5,215 | module MODULE1(
input VAR39,
input reset,
input VAR23,
output VAR38,
input [31:0] VAR40,
output reg VAR8, output reg VAR36, input VAR9,
output reg [31:0] VAR33,
output reg VAR26, input VAR10 );
reg [7:0] VAR20;
reg VAR17;
wire VAR37;
wire [7:0] VAR19;
wire VAR2;
reg VAR3;
VAR29
VAR11 (
.clk(VAR39),
.rst(~reset),
.VAR7(... | mit |
sukinull/vivado_zed_pieces | axigpio_w_linux_uio/project_uio/project_uio.srcs/sources_1/ipshared/xilinx.com/processing_system7_bfm_v2_0/e69044ca/hdl/processing_system7_bfm_v2_0_fmsw_gp.v | 6,423 | module MODULE1(
VAR81,
VAR18,
VAR85,
VAR103,
VAR89,
VAR70,
VAR74,
VAR31,
VAR92,
VAR23,
VAR6,
VAR51,
VAR61,
VAR63,
VAR26,
VAR22,
VAR40,
VAR80,
VAR1,
VAR52,
VAR82,
VAR4,
VAR94,
VAR35,
VAR39,
VAR60,
VAR19,
VAR68,
VAR69,
VAR41,
VAR38,
VAR98,
VAR87,
VAR50,
VAR71,
VAR53,
VAR5,
VAR72,
VAR56,
VAR96,
VAR34,
VAR13,
VAR24,
VAR100... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/xor3/sky130_fd_sc_hd__xor3.behavioral.v | 1,406 | module MODULE1 (
VAR6,
VAR4,
VAR1,
VAR9
);
output VAR6;
input VAR4;
input VAR1;
input VAR9;
supply1 VAR10;
supply0 VAR11;
supply1 VAR2 ;
supply0 VAR5 ;
wire VAR7;
xor VAR3 (VAR7, VAR4, VAR1, VAR9 );
buf VAR8 (VAR6 , VAR7 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/and2/sky130_fd_sc_hd__and2.blackbox.v | 1,233 | module MODULE1 (
VAR4,
VAR6,
VAR3
);
output VAR4;
input VAR6;
input VAR3;
supply1 VAR5;
supply0 VAR2;
supply1 VAR1 ;
supply0 VAR7 ;
endmodule | apache-2.0 |
SI-RISCV/e200_opensource | rtl/e203/core/e203_exu_csr.v | 26,682 | module MODULE1(
input VAR160,
output VAR217,
input VAR98,
input VAR233,
input VAR39,
input [12-1:0] VAR156,
output VAR121,
output VAR97,
output VAR91,
output VAR173,
output VAR17,
output VAR228,
output [VAR203-1:0] VAR46,
input [VAR203-1:0] VAR31,
input [VAR20-1:0] VAR107,
input VAR139,
input VAR155,
input VAR2,
output... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/inv/sky130_fd_sc_lp__inv_16.v | 2,001 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR5,
VAR8,
VAR6 ,
VAR7
);
output VAR3 ;
input VAR4 ;
input VAR5;
input VAR8;
input VAR6 ;
input VAR7 ;
VAR2 VAR1 (
.VAR3(VAR3),
.VAR4(VAR4),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR6(VAR6),
.VAR7(VAR7)
);
endmodule
module MODULE1 (
VAR3,
VAR4
);
output VAR3;
input VAR4;
supply1 VAR5;
supply0 VAR8;... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/fah/sky130_fd_sc_hs__fah.behavioral.pp.v | 2,494 | module MODULE1 (
VAR22,
VAR23 ,
VAR16 ,
VAR3 ,
VAR18 ,
VAR10,
VAR19
);
output VAR22;
output VAR23 ;
input VAR16 ;
input VAR3 ;
input VAR18 ;
input VAR10;
input VAR19;
wire VAR7 ;
wire VAR6 ;
wire VAR21 ;
wire VAR17 ;
wire VAR8 ;
wire VAR14 ;
wire VAR24;
xor VAR15 (VAR7 , VAR16, VAR3, VAR18 );
VAR20 VAR2 (VAR6 , VAR7, V... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/sdfrtp/sky130_fd_sc_hdll__sdfrtp.blackbox.v | 1,452 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR9 ,
VAR10 ,
VAR4 ,
VAR2
);
output VAR8 ;
input VAR6 ;
input VAR9 ;
input VAR10 ;
input VAR4 ;
input VAR2;
supply1 VAR7;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR5 ;
endmodule | apache-2.0 |
tmatsuya/milkymist-ml401 | cores/pfpu/rtl/pfpu_faddsub.v | 3,603 | module MODULE1(
input VAR34,
input VAR33,
input [31:0] VAR4,
input [31:0] VAR27,
input VAR15,
input VAR10,
output [31:0] VAR28,
output reg VAR19
);
wire VAR37 = VAR4[31];
wire [7:0] VAR7 = VAR4[30:23];
wire [22:0] VAR3 = VAR4[22:0];
wire VAR30 = VAR27[31] ^ VAR15;
wire [7:0] VAR18 = VAR27[30:23];
wire [22:0] VAR8 = VAR... | lgpl-3.0 |
cr1901/HDMI2USB-litex-firmware | gateware/encoder/verilog/wb_async_reg.v | 7,782 | module MODULE1 #
(
parameter VAR21 = 32, parameter VAR28 = 32, parameter VAR34 = (VAR21/8) )
(
input wire VAR27,
input wire VAR8,
input wire [VAR28-1:0] VAR38, input wire [VAR21-1:0] VAR47, output wire [VAR21-1:0] VAR54, input wire VAR15, input wire [VAR34-1:0] VAR49, input wire VAR20, output wire VAR33, output wire VA... | bsd-2-clause |
flycrow/pyxdl | logicanalyzer/serial_wb_program.v | 52,629 | module MODULE1(VAR1, VAR2, VAR3);
input VAR1;
input [9:0] VAR2;
output [15:0] VAR3;
wire VAR1;
wire [9:0] VAR2;
reg [15:0] VAR3;
always @(posedge VAR1)
case(VAR2)
10'h000: VAR3 <= 16'h4f00; 10'h001: VAR3 <= 16'hffff; 10'h002: VAR3 <= 16'hffff; 10'h003: VAR3 <= 16'h4000; 10'h004: VAR3 <= 16'h4100; 10'h005: VAR3 <= 16'h4... | gpl-2.0 |
Obijuan/open-fpga-verilog-tutorial | tutorial/Alhambra_II/T30-microbio/microbio.v | 5,415 | module MODULE1 (input wire clk, input wire VAR35, output wire [3:0] VAR13, output wire VAR32);
parameter VAR26 = VAR1;
parameter VAR33 = "VAR30.VAR9";
localparam VAR21 = 6; localparam VAR22 = 8;
localparam VAR6 = 2'b00;
localparam VAR19 = 2'b01;
localparam VAR10 = 2'b10;
localparam VAR34 = 2'b11;
wire [VAR22-1: 0] VAR5... | gpl-2.0 |
UGent-HES/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/multless_consts/verilog/mult_120.v | 1,435 | module MODULE1 (
VAR7,
VAR1
);
input [31:0] VAR7;
output [31:0]
VAR1;
wire [31:0]
VAR4,
VAR10,
VAR9,
VAR8,
VAR5,
VAR3,
VAR6;
assign VAR4 = VAR7;
assign VAR5 = VAR8 - VAR9;
assign VAR8 = VAR9 << 6;
assign VAR9 = VAR10 - VAR4;
assign VAR6 = VAR3 - VAR5;
assign VAR3 = VAR4 << 15;
assign VAR10 = VAR4 << 2;
assign VAR1 = VA... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a211o/sky130_fd_sc_lp__a211o.pp.blackbox.v | 1,389 | module MODULE1 (
VAR3 ,
VAR4 ,
VAR7 ,
VAR6 ,
VAR9 ,
VAR5,
VAR8,
VAR1 ,
VAR2
);
output VAR3 ;
input VAR4 ;
input VAR7 ;
input VAR6 ;
input VAR9 ;
input VAR5;
input VAR8;
input VAR1 ;
input VAR2 ;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/dlygate4sd1/sky130_fd_sc_hd__dlygate4sd1_1.v | 2,119 | module MODULE2 (
VAR6 ,
VAR2 ,
VAR5,
VAR8,
VAR3 ,
VAR4
);
output VAR6 ;
input VAR2 ;
input VAR5;
input VAR8;
input VAR3 ;
input VAR4 ;
VAR1 VAR7 (
.VAR6(VAR6),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR8(VAR8),
.VAR3(VAR3),
.VAR4(VAR4)
);
endmodule
module MODULE2 (
VAR6,
VAR2
);
output VAR6;
input VAR2;
supply1 VAR5;
supply0 VAR8;... | apache-2.0 |
marqs85/de2-vd | rtl/scanconverter.v | 20,588 | module MODULE1 (
input [7:0] VAR16,
input [7:0] VAR98,
input [7:0] VAR160,
input VAR34,
input VAR61,
input VAR40,
input VAR90,
input [31:0] VAR32,
input [31:0] VAR97,
output reg [7:0] VAR153,
output reg [7:0] VAR151,
output reg [7:0] VAR96,
output reg VAR25,
output reg VAR41,
output VAR125,
output reg VAR133,
output [1... | gpl-3.0 |
antmicro/yosys | techlibs/ice40/brams_map.v | 8,116 | module \VAR2 (
output [15:0] VAR12,
input VAR25, VAR50, VAR57,
input [10:0] VAR3,
input VAR41, VAR44, VAR10,
input [10:0] VAR16,
input [15:0] VAR43, VAR13
);
parameter [1:0] VAR56 = 0;
parameter [1:0] VAR39 = 0;
parameter [0:0] VAR53 = 0;
parameter [0:0] VAR38 = 0;
parameter [255:0] VAR6 = 256'h000000000000000000000000... | isc |
EliasVansteenkiste/ConnectionRouter | vtr_flow/benchmarks/arithmetic/generated_circuits/adder_trees/verilog/adder_tree_3L_023bits.v | 1,917 | module MODULE2 (
clk,
VAR15, VAR8, VAR21, VAR25, VAR2, VAR19, VAR20, VAR22,
sum,
);
input clk;
input [VAR27+0-1:0] VAR15, VAR8, VAR21, VAR25, VAR2, VAR19, VAR20, VAR22;
output [VAR27 :0] sum;
reg [VAR27 :0] sum;
wire [VAR27+3-1:0] VAR28;
wire [VAR27+2-1:0] VAR34, VAR10;
wire [VAR27+1-1:0] VAR11, VAR3, VAR14, VAR30;
reg... | mit |
danbone/core | riscv_core_if.v | 2,365 | module MODULE1 (
input clk,
input VAR22,
output [31:0] VAR11;
output VAR19;
output
output [31:0] VAR13;
input [5:0] VAR18,
input [31:0] VAR9,
input [1:0] VAR5,
input [31:0] VAR17,
input [31:0] VAR2
);
localparam VAR7 = 7'b0000000;
localparam VAR10 = 7'b0000001;
localparam VAR15 = 7'b0000010;
localparam VAR1 = 7'b000010... | mit |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/db/ip/tracking_camera_system/submodules/tracking_camera_system_nios2_qsys_0_jtag_debug_module_tck.v | 8,885 | module MODULE1 (
VAR1,
VAR9,
VAR30,
VAR39,
VAR16,
VAR11,
VAR19,
VAR27,
VAR25,
VAR32,
VAR2,
VAR36,
VAR28,
VAR8,
VAR40,
VAR35,
VAR24,
VAR18,
VAR38,
VAR5,
VAR37,
VAR22,
VAR21,
VAR31,
VAR3,
VAR14,
VAR29,
VAR34,
VAR10,
VAR15,
VAR6
)
;
output [ 1: 0] VAR29;
output VAR34;
output [ 37: 0] VAR10;
output VAR15;
output VAR6;
inpu... | gpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/inv/sky130_fd_sc_hs__inv_2.v | 1,868 | module MODULE2 (
VAR6 ,
VAR4 ,
VAR2,
VAR5
);
output VAR6 ;
input VAR4 ;
input VAR2;
input VAR5;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR4(VAR4),
.VAR2(VAR2),
.VAR5(VAR5)
);
endmodule
module MODULE2 (
VAR6,
VAR4
);
output VAR6;
input VAR4;
supply1 VAR2;
supply0 VAR5;
VAR1 VAR3 (
.VAR6(VAR6),
.VAR4(VAR4)
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/a2111oi/sky130_fd_sc_lp__a2111oi.functional.v | 1,503 | module MODULE1 (
VAR5 ,
VAR8,
VAR9,
VAR7,
VAR11,
VAR10
);
output VAR5 ;
input VAR8;
input VAR9;
input VAR7;
input VAR11;
input VAR10;
wire VAR4 ;
wire VAR3;
and VAR6 (VAR4 , VAR8, VAR9 );
nor VAR2 (VAR3, VAR7, VAR11, VAR10, VAR4);
buf VAR1 (VAR5 , VAR3 );
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/a21boi/sky130_fd_sc_ls__a21boi_1.v | 2,332 | module MODULE2 (
VAR3 ,
VAR7 ,
VAR8 ,
VAR2,
VAR5,
VAR6,
VAR1 ,
VAR10
);
output VAR3 ;
input VAR7 ;
input VAR8 ;
input VAR2;
input VAR5;
input VAR6;
input VAR1 ;
input VAR10 ;
VAR9 VAR4 (
.VAR3(VAR3),
.VAR7(VAR7),
.VAR8(VAR8),
.VAR2(VAR2),
.VAR5(VAR5),
.VAR6(VAR6),
.VAR1(VAR1),
.VAR10(VAR10)
);
endmodule
module MODULE2 ... | apache-2.0 |
eda-globetrotter/MarcheProcessor | processor/spare/build2/alu.v | 168,962 | module MODULE1 (VAR2,VAR3,VAR4,VAR8,VAR1,VAR5,VAR6);
output [0:127] VAR5;
input [0:127] VAR2;
input [0:127] VAR3;
input [0:2] VAR4;
input [0:1] VAR8;
input [0:4] VAR1;
input [15:0] VAR6;
parameter VAR7 = 128'hffffffffffffffffffffffffffffffff;
reg [0:127] VAR5;
always @(VAR2 or VAR3 or VAR4 or VAR8 or VAR1 or VAR6)
begi... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/decap/sky130_fd_sc_lp__decap.pp.symbol.v | 1,200 | module MODULE1 (
input VAR2 ,
input VAR1,
input VAR4,
input VAR3
);
endmodule | apache-2.0 |
fallen/milkymist-mmu | cores/uart/rtl/uart_transceiver.v | 3,956 | module MODULE1(
input VAR18,
input VAR13,
input VAR2,
output reg VAR11,
input [15:0] VAR23,
output reg [7:0] VAR4,
output reg VAR15,
input [7:0] VAR6,
input VAR7,
output reg VAR1,
output reg break
);
reg [15:0] VAR5;
wire VAR10;
assign VAR10 = (VAR5 == 16'd0);
always @(posedge VAR13) begin
if(VAR18)
VAR5 <= VAR23 - 16'... | lgpl-3.0 |
AngelTerrones/ADA | rtl/ada_memwb_stage.v | 1,836 | module MODULE1(
input clk, input rst, input [31:0] VAR8, input [4:0] VAR2, input VAR4, input VAR1, input VAR3, input VAR5, output reg [31:0] VAR9, output reg [4:0] VAR6, output reg VAR7 );
always @(posedge clk) begin
VAR9 <= (rst) ? 31'b0 : ((VAR5) ? VAR9 : VAR8);
VAR6 <= (rst) ? 5'b0 : ((VAR5) ? VAR6 :((VAR3 | VAR1) ?... | mit |
asicguy/gplgpu | hdl/altera_ddr3_128/alt_mem_ddrx_ecc_decoder_64_syn.v | 57,948 | module MODULE3
(
VAR160,
VAR33) ;
input [6:0] VAR160;
output [127:0] VAR33;
tri0 [6:0] VAR160;
wire [5:0] VAR182;
wire VAR69;
wire VAR125;
wire [127:0] VAR192;
wire [63:0] VAR120;
wire [63:0] VAR196;
wire [3:0] VAR64;
wire [3:0] VAR208;
wire [3:0] VAR214;
wire [3:0] VAR195;
wire [3:0] VAR3;
wire [3:0] VAR142;
wire [3:0... | gpl-3.0 |
Elphel/x353 | control/camsync.v | 21,262 | module MODULE1 (VAR101, VAR20, VAR10, VAR44, VAR37, VAR78, VAR29, VAR25, VAR24, VAR40, VAR89, VAR56, VAR3, VAR21, VAR96, VAR60, VAR13, VAR12, VAR72, VAR46, VAR63); parameter VAR52= 6'b110100;
parameter VAR61=6'b001101;
input VAR101;
input VAR20;
input [15:0] VAR10;
input [ 1:0] VAR44;
input VAR37;
input VAR78; input VA... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/a21bo/sky130_fd_sc_hd__a21bo.blackbox.v | 1,383 | module MODULE1 (
VAR2 ,
VAR4 ,
VAR5 ,
VAR6
);
output VAR2 ;
input VAR4 ;
input VAR5 ;
input VAR6;
supply1 VAR7;
supply0 VAR3;
supply1 VAR8 ;
supply0 VAR1 ;
endmodule | apache-2.0 |
ultraembedded/riscv | core/riscv/riscv_decode.v | 6,185 | module MODULE1
parameter VAR8 = 1
,parameter VAR41 = 0
)
(
input VAR4
,input VAR29
,input VAR37
,input [ 31:0] VAR10
,input [ 31:0] VAR18
,input VAR36
,input VAR17
,input VAR12
,input VAR32
,output VAR27
,output VAR5
,output [ 31:0] VAR24
,output [ 31:0] VAR28
,output VAR21
,output VAR6
,output VAR40
,output VAR38
,out... | bsd-3-clause |
google/skywater-pdk-libs-sky130_fd_sc_hvl | models/udp_dff_p_pp_pg_n/sky130_fd_sc_hvl__udp_dff_p_pp_pg_n.symbol.v | 1,417 | module MODULE1 (
input VAR4 ,
output VAR5 ,
input VAR6 ,
input VAR3,
input VAR2 ,
input VAR1
);
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ms | cells/o211a/sky130_fd_sc_ms__o211a.pp.blackbox.v | 1,389 | module MODULE1 (
VAR8 ,
VAR6 ,
VAR5 ,
VAR7 ,
VAR9 ,
VAR4,
VAR1,
VAR2 ,
VAR3
);
output VAR8 ;
input VAR6 ;
input VAR5 ;
input VAR7 ;
input VAR9 ;
input VAR4;
input VAR1;
input VAR2 ;
input VAR3 ;
endmodule | apache-2.0 |
rhalstea/cidr_15_fpga_join | build_engine/verilog/sync_2_fifo.v | 1,380 | module MODULE1 (
input clk,
input rst,
output [1:0] VAR4,
input [1:0] VAR6,
input [63:0] VAR1,
input [63:0] VAR9,
output VAR3,
input VAR8,
output [63:0] VAR7,
output [63:0] VAR5
);
wire [1:0] VAR12;
VAR2 VAR17 (
.clk (clk),
.rst (rst),
.din (VAR9),
.VAR15 (VAR6[0]),
.VAR11 (VAR8),
.dout (VAR5),
.VAR10 (),
.VAR14 (VAR12... | bsd-3-clause |
CospanDesign/nysa-verilog | verilog/axi/slave/axi_nes/rtl/wram.v | 2,336 | module MODULE1(
input VAR8, input VAR10, input VAR9, input [10:0] VAR14, input [ 7:0] din, output [ 7:0] dout );
wire VAR11;
wire [7:0] VAR2;
VAR7 #(.VAR13(11),
.VAR5(8)) VAR6(
.clk(VAR8),
.VAR12(VAR11),
.VAR4(VAR14),
.VAR3(din),
.VAR1(VAR2)
);
assign VAR11 = (VAR10) ? ~VAR9 : 1'b0;
assign dout = (VAR10) ? VAR2 : 8'h00... | mit |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/xnor3/gf180mcu_fd_sc_mcu7t5v0__xnor3_2.functional.pp.v | 1,611 | module MODULE1( VAR18, VAR10, VAR12, VAR9, VAR7, VAR14 );
input VAR10, VAR18, VAR12;
inout VAR7, VAR14;
output VAR9;
wire VAR6;
not VAR16( VAR6, VAR12 );
wire VAR17;
and VAR19( VAR17, VAR6, VAR10, VAR18 );
wire VAR1;
not VAR2( VAR1, VAR18 );
wire VAR3;
and VAR15( VAR3, VAR1, VAR10, VAR12 );
wire VAR21;
not VAR4( VAR21,... | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/o21bai/sky130_fd_sc_lp__o21bai.functional.v | 1,558 | module MODULE1 (
VAR1 ,
VAR2 ,
VAR9 ,
VAR7
);
output VAR1 ;
input VAR2 ;
input VAR9 ;
input VAR7;
wire VAR10 ;
wire VAR5 ;
wire VAR3;
not VAR11 (VAR10 , VAR7 );
or VAR6 (VAR5 , VAR9, VAR2 );
nand VAR4 (VAR3, VAR10, VAR5 );
buf VAR8 (VAR1 , VAR3 );
endmodule | apache-2.0 |
andrewandrepowell/axiplasma | hdl/projects/Nexys4/bd/mig_wrap/ip/mig_wrap_mig_7series_0_0/mig_wrap_mig_7series_0_0/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v | 15,167 | module MODULE1 #
(
parameter VAR32 = 100, parameter VAR49 = "VAR7", parameter VAR66 = 5000, parameter VAR15 = 10000000 )
(
input clk, input VAR70,
input rst, input [11:0] VAR92, output [11:0] VAR11 );
function integer VAR91 (input integer VAR17, input integer VAR36);
begin
VAR91 = (VAR17/VAR36) + (((VAR17%VAR36)>0) ? 1... | mit |
bargei/NoC264 | NoC264_2x2/mkInputArbiter.v | 8,265 | module MODULE1(VAR28,
VAR41,
VAR21,
select,
VAR27);
input VAR28;
input VAR41;
input [4 : 0] VAR21;
output [4 : 0] select;
input VAR27;
wire [4 : 0] select;
reg [4 : 0] VAR14;
wire [4 : 0] VAR7;
wire VAR43;
wire [1 : 0] VAR10,
VAR18,
VAR6,
VAR1,
VAR26,
VAR37,
VAR39,
VAR9,
VAR2,
VAR5;
wire VAR49,
VAR22,
VAR51,
VAR46,
VAR... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/nor2/sky130_fd_sc_lp__nor2_lp.v | 2,094 | module MODULE1 (
VAR9 ,
VAR7 ,
VAR2 ,
VAR1,
VAR8,
VAR5 ,
VAR3
);
output VAR9 ;
input VAR7 ;
input VAR2 ;
input VAR1;
input VAR8;
input VAR5 ;
input VAR3 ;
VAR4 VAR6 (
.VAR9(VAR9),
.VAR7(VAR7),
.VAR2(VAR2),
.VAR1(VAR1),
.VAR8(VAR8),
.VAR5(VAR5),
.VAR3(VAR3)
);
endmodule
module MODULE1 (
VAR9,
VAR7,
VAR2
);
output VAR9;
... | apache-2.0 |
zhangry868/MultiCycleCPU | Multiple_Cycles_CPU/Ram_Real.v | 7,122 | module MODULE1 (
address,
VAR41,
VAR51,
VAR22,
VAR10,
VAR40);
input [9:0] address;
input [3:0] VAR41;
input VAR51;
input [31:0] VAR22;
input VAR10;
output [31:0] VAR40;
tri1 [3:0] VAR41;
tri1 VAR51;
wire [31:0] VAR16;
wire [31:0] VAR40 = VAR16[31:0];
VAR36 VAR49 (
.VAR52 (address),
.VAR12 (VAR41),
.VAR20 (VAR51),
.VAR4... | gpl-3.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/nor3/gf180mcu_fd_sc_mcu7t5v0__nor3_4.behavioral.pp.v | 1,328 | module MODULE1( VAR5, VAR4, VAR8, VAR2, VAR1, VAR9 );
input VAR2, VAR5, VAR8;
inout VAR1, VAR9;
output VAR4;
VAR6 VAR7(.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1),.VAR9(VAR9));
VAR6 VAR3(.VAR5(VAR5),.VAR4(VAR4),.VAR8(VAR8),.VAR2(VAR2),.VAR1(VAR1),.VAR9(VAR9)); | apache-2.0 |
alanachtenberg/CSCE-350 | Lab 7/lab7_3.v | 1,579 | module MODULE1 (VAR3,VAR21,VAR8,VAR22);
output VAR3, VAR21;
input VAR8, VAR22;
wire VAR19, VAR16;
wire VAR5, VAR11;
wire VAR17, VAR1;
wire VAR15, VAR6;
not (VAR19, VAR22);
not (VAR16, VAR8);
nand VAR13(VAR5,VAR8, VAR22);
nand VAR10(VAR11,VAR8, VAR19);
nand VAR7(VAR6,VAR11,VAR15);
nand VAR14(VAR15,VAR5,VAR6);
nand VAR4(... | gpl-2.0 |
vad-rulezz/megabot | fusesoc/orpsoc-cores/trunk/systems/de1/rtl/verilog/wb_intercon.v | 14,926 | module MODULE1
(input VAR34,
input VAR148,
input [31:0] VAR126,
input [31:0] VAR191,
input [3:0] VAR158,
input VAR106,
input VAR53,
input VAR30,
input [2:0] VAR156,
input [1:0] VAR3,
output [31:0] VAR37,
output VAR149,
output VAR75,
output VAR96,
input [31:0] VAR43,
input [31:0] VAR153,
input [3:0] VAR68,
input VAR52,
... | gpl-2.0 |
queq/just-stuff | pov/TopMobile/LEDS/control_leds.v | 3,261 | module MODULE1(
input clk,
input VAR21,
output reg VAR10,
output reg VAR3
);
reg [6:0] VAR11;
reg [6:0] VAR15;
parameter VAR4=7'b0000000, VAR2=7'b0000001, VAR19=7'b0000010, VAR12=7'b0000011, VAR6=7'b0000100, VAR22=7'b0000101;
always @(VAR14 or VAR7 or VAR1 or VAR10 or VAR13 or VAR11)begin
case(VAR11)
VAR4: begin
VAR5=1... | mit |
google/skywater-pdk-libs-sky130_fd_sc_lp | cells/dfsbp/sky130_fd_sc_lp__dfsbp.behavioral.v | 2,273 | module MODULE1 (
VAR18 ,
VAR7 ,
VAR16 ,
VAR14 ,
VAR20
);
output VAR18 ;
output VAR7 ;
input VAR16 ;
input VAR14 ;
input VAR20;
supply1 VAR11;
supply0 VAR15;
supply1 VAR17 ;
supply0 VAR4 ;
wire VAR1 ;
wire VAR13 ;
reg VAR21 ;
wire VAR9 ;
wire VAR23;
wire VAR5 ;
wire VAR19 ;
wire VAR8 ;
wire VAR10 ;
not VAR2 (VAR13 , VAR... | apache-2.0 |
bigeagle/riffa | fpga/riffa_hdl/tx_multiplexer_64.v | 18,527 | module MODULE1
parameter VAR100 = 128,
parameter VAR114 = 12,
parameter VAR36 = 5, parameter VAR48 = "VAR19"
)
(
input VAR32,
input VAR88,
input [VAR114-1:0] VAR42, input [(VAR114*VAR109)-1:0] VAR51, input [(VAR114*VAR117)-1:0] VAR50, input [(VAR114*VAR100)-1:0] VAR66, output [VAR114-1:0] VAR67, output [VAR114-1:0] VAR... | bsd-3-clause |
bargei/NoC264 | NoC264_2x2/mkInputQueue.v | 9,174 | module MODULE1(VAR8,
VAR4,
VAR12,
VAR25,
VAR40,
VAR7,
VAR33,
VAR11);
input VAR8;
input VAR4;
input [131 : 0] VAR12;
input VAR25;
input VAR40;
output [131 : 0] VAR7;
output VAR33;
output VAR11;
wire [131 : 0] VAR7;
wire VAR33, VAR11;
wire [2 : 0] VAR6,
VAR16;
reg [2 : 0] VAR19;
wire [2 : 0] VAR37;
wire VAR1;
reg VAR23;
... | mit |
google/skywater-pdk-libs-sky130_fd_sc_hdll | cells/probec_p/sky130_fd_sc_hdll__probec_p.behavioral.v | 1,373 | module MODULE1 (
VAR5,
VAR6
);
output VAR5;
input VAR6;
supply1 VAR8;
supply0 VAR1;
supply1 VAR9 ;
supply0 VAR2 ;
wire VAR3;
buf VAR4 (VAR3, VAR6 );
buf VAR7 (VAR5 , VAR3 );
endmodule | apache-2.0 |
google/globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0 | cells/clkbuf/gf180mcu_fd_sc_mcu7t5v0__clkbuf_1.behavioral.pp.v | 1,174 | module MODULE1( VAR4, VAR1, VAR7, VAR5 );
input VAR4;
inout VAR7, VAR5;
output VAR1;
VAR6 VAR2(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5));
VAR6 VAR3(.VAR4(VAR4),.VAR1(VAR1),.VAR7(VAR7),.VAR5(VAR5)); | apache-2.0 |
unsignedzero/verilogLabs | labs/lab11/sram/sram.v | 1,101 | module MODULE1(read, write, address, VAR4, VAR5, clk );
parameter VAR1 = 8;
parameter VAR3 = 3;
parameter VAR2 = 1<<VAR3;
input read;
input write;
input [VAR3-1:0] address;
input [VAR1-1:0] VAR4;
output [VAR1-1:0] VAR5;
reg [VAR1-1:0] VAR5;
input clk;
reg [VAR1-1:0] VAR6 [VAR2-1:0];
always @(posedge clk) begin
if(write... | mit |
alan4186/ParCNN | Hardware/v/mult_adder_ctrl.v | 2,149 | module MODULE1(
input VAR5,
input reset,
input VAR13,
output [VAR14:0] VAR2,
output [VAR3:0] VAR6,
output VAR1 );
reg VAR9;
reg VAR10 [VAR11-1:0];
reg [VAR14:0] VAR4;
reg [VAR3:0] VAR7;
assign VAR1 = VAR10[0];
assign VAR2 = VAR4;
assign VAR6 = VAR7;
always@(posedge VAR5 or negedge reset) begin
if(reset == 1'b0) begin
V... | mit |
SiLab-Bonn/basil | basil/firmware/modules/i2c/i2c.v | 1,606 | module MODULE1 #(
parameter VAR14 = 16'h0000,
parameter VAR8 = 16'h0000,
parameter VAR5 = 16,
parameter VAR11 = 1,
parameter VAR9 = 0
) (
input wire VAR25,
input wire VAR22,
input wire [VAR5-1:0] VAR17,
inout wire [7:0] VAR13,
input wire VAR4,
input wire VAR12,
input wire VAR7,
inout wire VAR16,
inout wire VAR19
);
wir... | bsd-3-clause |
himingway/PIC16C5x | src/ALU.v | 2,852 | module MODULE1 (
input [ VAR16-1:0] VAR9 , input [ VAR16-1:0] VAR2 , input [ VAR16-1:0] VAR12 , input [ VAR14-1:0] VAR10 , input [ 2:0] VAR8 , input VAR4 , input [VAR5-1:0] VAR11 , output [VAR5-1:0] VAR13, output [ VAR16-1:0] VAR3 );
reg VAR7;
reg VAR6;
reg [VAR16-1:0] VAR1;
assign VAR3 = VAR1;
always @ begin
case (VAR... | mit |
hanw/sonic-lite | hw/verilog/enc_dec/encoder.v | 59,925 | module MODULE1 (clk, VAR118, VAR29, VAR85, VAR96, VAR134, enable);
input clk;
input[63:0] VAR118;
input[7:0] VAR29;
output[65:0] VAR85;
reg[65:0] VAR85;
output [2:0] VAR96;
reg [2:0] VAR96;
input VAR134;
input enable;
reg VAR46;
reg VAR34;
reg VAR12;
reg VAR33;
reg VAR116;
reg VAR117;
reg VAR7;
reg VAR76;
reg VAR129;
r... | mit |
spacemonkeydelivers/mor1kx | rtl/verilog/mor1kx_cache_lru.v | 9,337 | module MODULE1(
VAR3, VAR11, VAR12,
VAR4, VAR9
);
parameter VAR2 = 2;
localparam VAR8 = VAR2*(VAR2-1) >> 1;
input [VAR8-1:0] VAR4;
output reg [VAR8-1:0] VAR3;
input [VAR2-1:0] VAR9;
output reg [VAR2-1:0] VAR11;
output reg [VAR2-1:0] VAR12;
reg [VAR2-1:0] VAR7 [0:VAR2-1];
integer VAR10, VAR6;
integer VAR5;
always @(*) b... | mpl-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/o2111ai/sky130_fd_sc_hd__o2111ai.behavioral.pp.v | 2,086 | module MODULE1 (
VAR7 ,
VAR8 ,
VAR6 ,
VAR11 ,
VAR10 ,
VAR13 ,
VAR4,
VAR14,
VAR9 ,
VAR16
);
output VAR7 ;
input VAR8 ;
input VAR6 ;
input VAR11 ;
input VAR10 ;
input VAR13 ;
input VAR4;
input VAR14;
input VAR9 ;
input VAR16 ;
wire VAR12 ;
wire VAR2 ;
wire VAR1;
or VAR15 (VAR12 , VAR6, VAR8 );
nand VAR17 (VAR2 , VAR10, V... | apache-2.0 |
revaldinho/opc | copro/src/Tube/hp_reg3.v | 4,799 | module MODULE1 (
input VAR19,
input VAR21,
input VAR2,
input VAR31,
input [7:0] VAR16,
input VAR1,
input VAR24,
input VAR10,
input VAR25,
output [7:0] VAR13,
output VAR27,
output VAR7,
output VAR15
);
wire [1:0] VAR18;
wire [1:0] VAR14;
reg [7:0] VAR20 ;
reg [7:0] VAR22 ;
wire [7:0] VAR9 ;
wire [7:0] VAR17 ;
assign VAR... | gpl-3.0 |
google/skywater-pdk-libs-sky130_fd_sc_hd | cells/clkdlybuf4s25/sky130_fd_sc_hd__clkdlybuf4s25.blackbox.v | 1,322 | module MODULE1 (
VAR4,
VAR2
);
output VAR4;
input VAR2;
supply1 VAR5;
supply0 VAR3;
supply1 VAR1 ;
supply0 VAR6 ;
endmodule | apache-2.0 |
vad-rulezz/megabot | minsoc/prj/src/blackboxes/or1200_top.v | 3,896 | module MODULE1(
VAR7, VAR23, VAR68, VAR12,
VAR20, VAR28, VAR21, VAR34, VAR37, VAR26,
VAR52, VAR18, VAR8, VAR65, VAR19, VAR33,
VAR41,
VAR10, VAR13,
VAR42, VAR17, VAR1, VAR2, VAR44, VAR62,
VAR14, VAR57, VAR54, VAR3, VAR32, VAR43,
VAR24,
VAR39, VAR56,
VAR29, VAR47, VAR48, VAR25, VAR61, VAR11,
VAR63, VAR6, VAR5, VAR22, VAR... | gpl-2.0 |
lokisz/openzcore | pippo-0.9/rtl/verilog/dsu_tx.v | 3,068 | module MODULE1(clk, rst, VAR13, VAR4, VAR1, VAR8);
input clk, rst, VAR13;
input [7:0] VAR4;
output VAR1, VAR8;
parameter VAR7 = 115200;
parameter VAR6 = 1;
parameter VAR10 = 16;
reg [VAR10:0] VAR11;
wire [VAR10:0] VAR2 = 17'h00097; VAR9
wire [VAR10:0] VAR2 = 17'h000ec; VAR9
wire [VAR10:0] VAR2 = 17'h00076; VAR9
wire VA... | gpl-2.0 |
olajep/oh | src/adi/hdl/library/common/ad_pnmon.v | 3,972 | module MODULE1 #(
parameter VAR14 = 16) (
input VAR13,
input VAR8,
input [(VAR14-1):0] VAR7,
input [(VAR14-1):0] VAR12,
output VAR4,
output VAR11);
reg VAR15 = 'd0;
reg VAR6 = 'd0;
reg VAR16 = 'd0;
reg VAR9 = 'd0;
reg VAR18 = 'd0;
reg [ 3:0] VAR17 = 'd0;
wire VAR1;
wire VAR2;
wire VAR10;
wire VAR5;
wire VAR3;
assign VA... | mit |
ammelto/FPGAdventure | Adventure/videosyncs.v | 2,264 | module MODULE1 (
input wire clk,
input wire [2:0] VAR18,
input wire [2:0] VAR5,
input wire [1:0] VAR22,
output reg [2:0] VAR4,
output reg [2:0] VAR16,
output reg [1:0] VAR6,
output reg VAR20,
output reg VAR2,
output wire [10:0] hc,
output wire [10:0] VAR11
);
/* VAR19:
parameter VAR8 = 800;
parameter VAR13 = 524;
param... | mit |
ShepardSiegel/ocpi | coregen/ddr3_s4_uniphy/ddr3_s4_uniphy/ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_rom.v | 4,351 | module MODULE1 (
address,
VAR9,
VAR34,
clk,
VAR11,
VAR3,
reset,
write,
VAR26,
VAR13
)
;
parameter VAR22 = "VAR23.VAR25";
output [ 31: 0] VAR13;
input [ 11: 0] address;
input [ 3: 0] VAR9;
input VAR34;
input clk;
input VAR11;
input VAR3;
input reset;
input write;
input [ 31: 0] VAR26;
wire [ 31: 0] VAR13;
wire VAR8;
ass... | lgpl-3.0 |
cpulabs/mist1032isa | src/core/execute/execute_load_store.v | 6,178 | module MODULE1(
input wire VAR21,
input wire VAR45,
input wire VAR43,
input wire VAR10,
input wire VAR32,
input wire VAR35,
input wire VAR61,
input wire VAR2,
input wire VAR49,
input wire VAR1,
input wire VAR26,
input wire VAR54,
input wire VAR48,
input wire [31:0] VAR8,
input wire [31:0] VAR59,
input wire VAR5,
input ... | bsd-2-clause |
google/skywater-pdk-libs-sky130_fd_sc_hs | cells/or3/sky130_fd_sc_hs__or3.symbol.v | 1,232 | module MODULE1 (
input VAR4,
input VAR6,
input VAR3,
output VAR5
);
supply1 VAR2;
supply0 VAR1;
endmodule | apache-2.0 |
google/skywater-pdk-libs-sky130_fd_sc_ls | cells/fill/sky130_fd_sc_ls__fill_2.v | 1,840 | module MODULE1 (
VAR4,
VAR2,
VAR3 ,
VAR6
);
input VAR4;
input VAR2;
input VAR3 ;
input VAR6 ;
VAR5 VAR1 (
.VAR4(VAR4),
.VAR2(VAR2),
.VAR3(VAR3),
.VAR6(VAR6)
);
endmodule
module MODULE1 ();
supply1 VAR4;
supply0 VAR2;
supply1 VAR3 ;
supply0 VAR6 ;
VAR5 VAR1 ();
endmodule | apache-2.0 |
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