text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```yaml
vendor: intel
comment: "Intel Atom SoC"
socs:
- name: atom
``` | /content/code_sandbox/soc/intel/atom/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
#
if SOC_LAKEMONT
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
# Can be enabled once UART is defined in board
# configuration.
config X86_VERY_EARLY_CONSOLE
default n
# Target platforms are usually not PC-compatible
# (e.g. without BIOS, ACPI, etc.).
config X86_PC_COMPATIBLE
default n
endif
``` | /content/code_sandbox/soc/intel/lakemont/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
# ATOM SoC configuration options
if SOC_ATOM
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 25000000 if HPET_TIMER
endif
``` | /content/code_sandbox/soc/intel/atom/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config SOC_ATOM
select X86
select CPU_ATOM
imply X86_MMU
select ARCH_HAS_RESERVED_PAGE_FRAMES
``` | /content/code_sandbox/soc/intel/atom/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the ia32 platform
*
* This header file is used to specify and describe board-level aspects for
* the 'ia32' platform.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <zephyr/device.h>
#... | /content/code_sandbox/soc/intel/atom/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 306 |
```unknown
config SOC_FAMILY_INTEL_SOCFPGA
bool
config SOC_FAMILY
default "intel_socfpga" if SOC_FAMILY_INTEL_SOCFPGA
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/intel/intel_socfpga/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```linker script
/*
*
*/
#include <zephyr/arch/x86/memory.ld>
#ifdef CONFIG_X86_64
#include <zephyr/arch/x86/intel64/linker.ld>
#else
#include <zephyr/arch/x86/ia32/linker.ld>
#endif
``` | /content/code_sandbox/soc/intel/atom/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
if SOC_FAMILY_INTEL_SOCFPGA
rsource "*/Kconfig.defconfig.series"
endif # SOC_FAMILY_INTEL_SOCFPGA
``` | /content/code_sandbox/soc/intel/intel_socfpga/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
if SOC_FAMILY_INTEL_SOCFPGA
rsource "*/Kconfig"
endif # SOC_FAMILY_INTEL_SOCFPGA
``` | /content/code_sandbox/soc/intel/intel_socfpga/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```yaml
family:
- name: intel_socfpga
series:
- name: agilex
socs:
- name: agilex
- name: agilex5
socs:
- name: agilex5
``` | /content/code_sandbox/soc/intel/intel_socfpga/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
config SOC_SERIES_AGILEX5
bool
select SOC_FAMILY_INTEL_SOCFPGA
help
Intel SoC FPGA Agilex5 Series
config SOC_SERIES
default "agilex5" if SOC_SERIES_AGILEX5
config SOC_AGILEX5
bool
select SOC_SERIES_AGILEX5
help
Intel SoC FPGA Agilex5
config SOC
default "agilex5" if SOC_AGILEX5
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex5/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```unknown
if SOC_SERIES_AGILEX5
rsource "Kconfig.defconfig.agilex5*"
endif # SOC_SERIES_AGILEX5
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
config SOC_SERIES_AGILEX5
select ARM64
select CPU_CORTEX_A76_A55
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex5/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
if SOC_AGILEX5
# must be >= the highest interrupt number used
# - include the UART interrupts 173 or 204
config NUM_IRQS
int
default 205
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 400000000
config KERNEL_VM_SIZE
default 0x400000
endif
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/arm64/arm_mmu.h>
static const struct arm_mmu_region mmu_regions[] = {
/* System manager register that required by clock driver */
MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER",
DT_REG_ADDR(DT_NODELABEL(sysmgr)),
DT_REG_SIZE(DT_NODELABEL(s... | /content/code_sandbox/soc/intel/intel_socfpga/agilex5/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 389 |
```objective-c
/*
*
*/
#ifndef SOCFPGA_SYSTEMMANAGER_H
#define SOCFPGA_SYSTEMMANAGER_H
/* System Manager Register Map */
#define SOCFPGA_SYSMGR_REG_BASE DT_REG_ADDR(DT_NODELABEL(sysmgr))
#define SOCFPGA_SYSMGR_SDMMC 0x28
#define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c
#define SOCFPGA_SYSMGR_EMAC_0 ... | /content/code_sandbox/soc/intel/intel_socfpga/common/socfpga_system_manager.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 558 |
```objective-c
/*
*
*/
#ifndef HANDOFF_H
#define HANDOFF_H
#include <stdint.h>
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
#define HANDOFF_MAGIC_FPGA 0x465047... | /content/code_sandbox/soc/intel/intel_socfpga/common/socfpga_handoff.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 842 |
```unknown
config SOC_SERIES_AGILEX
bool
select SOC_FAMILY_INTEL_SOCFPGA
help
Intel SoC FPGA Agilex Series
config SOC_SERIES
default "agilex" if SOC_SERIES_AGILEX
config SOC_AGILEX
bool
select SOC_SERIES_AGILEX
help
Intel SoC FPGA Agilex
config SOC
default "agilex" if SOC_AGILEX
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
if SOC_SERIES_AGILEX
rsource "Kconfig.defconfig.agilex*"
endif # SOC_SERIES_AGILEX
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
if SOC_AGILEX
# must be >= the highest interrupt number used
# - include the UART interrupts 173 or 204
config NUM_IRQS
int
default 205
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 25000000
config KERNEL_VM_SIZE
default 0x180000
endif
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*/
#include <zephyr/arch/arm64/arm_mmu.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
static const struct arm_mmu_region mmu_regions[] = {
/* System manager register that required by clock driver */
MMU_REGION_FLAT_ENTRY("SYSTEM_MANAGER",
DT_REG_ADDR(DT_NODELABEL(sysmgr)),
... | /content/code_sandbox/soc/intel/intel_socfpga/agilex/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 388 |
```unknown
config SOC_SERIES_AGILEX
select ARM64
select CPU_CORTEX_A53
``` | /content/code_sandbox/soc/intel/intel_socfpga/agilex/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```objective-c
/*
*
*/
struct gpio_acpi_res {
uintptr_t reg_base;
uint32_t len;
uint32_t pad_base;
uint8_t num_pins;
uint32_t host_owner_reg;
uint32_t pad_owner_reg;
uint32_t intr_stat_reg;
uint16_t base_num;
uint16_t irq;
uint32_t irq_flags;
};
/**
* @brief Retrieve current resource settings of a gpio d... | /content/code_sandbox/soc/intel/common/soc_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 192 |
```unknown
config SOC_ALDER_LAKE
bool
config SOC
default "alder_lake" if SOC_ALDER_LAKE
``` | /content/code_sandbox/soc/intel/alder_lake/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```c
/*
*/
#include <zephyr/kernel.h>
uint8_t x86_cpu_loapics[] = { 0x00, 0x02, 0x04, 0x06 };
``` | /content/code_sandbox/soc/intel/alder_lake/cpu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
vendor: intel
comment: "Intel Alder Lake SoC"
socs:
- name: alder_lake
``` | /content/code_sandbox/soc/intel/alder_lake/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```c
/*
*
*/
#include <errno.h>
#include <zephyr/acpi/acpi.h>
#include "soc.h"
#include "soc_gpio.h"
#define GET_GPIO_BASE_NUM ("\\_SB.GINF")
static int gpio_info_acpi_get(uint32_t bank_idx, uint32_t field_idx, uint32_t *ret_val)
{
int status;
ACPI_OBJECT args[2];
ACPI_OBJECT_LIST arg_list;
ACPI_OBJECT gpio_ob... | /content/code_sandbox/soc/intel/common/soc_gpio.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 720 |
```objective-c
/*
*
*/
/**
* @file
* @brief GPIO macros for the Alder Lake SoC
*
* This header file is used to specify the GPIO macros for
* the Alder Lake SoC.
*/
#ifndef __SOC_GPIO_H_
#define __SOC_GPIO_H_
#define GPIO_INTEL_NR_SUBDEVS 10
#define REG_PAD_OWNER_BASE 0x0020
#define REG_GPI_INT... | /content/code_sandbox/soc/intel/alder_lake/soc_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 380 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the Alder Lake SoC
*
* This header file is used to specify and describe soc-level aspects for
* the 'Alder Lake' SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <zephyr/device.h>
#... | /content/code_sandbox/soc/intel/alder_lake/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```unknown
# Alder Lake SoC configuration options
if SOC_ALDER_LAKE
config PCIE_MMIO_CFG
default y
config X86_DYNAMIC_IRQ_STUBS
default 16
depends on DYNAMIC_INTERRUPTS
endif # SOC_ALDER_LAKE
``` | /content/code_sandbox/soc/intel/alder_lake/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
config SOC_ALDER_LAKE
select X86
select X86_64
select CPU_ATOM
select PCIE
select PCIE_MSI
select DYNAMIC_INTERRUPTS
select X86_MMU
``` | /content/code_sandbox/soc/intel/alder_lake/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
config SOC_ELKHART_LAKE
bool
config SOC
default "elkhart_lake" if SOC_ELKHART_LAKE
``` | /content/code_sandbox/soc/intel/elkhart_lake/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```linker script
/*
*
*/
#include <zephyr/arch/x86/memory.ld>
#ifdef CONFIG_X86_64
#include <zephyr/arch/x86/intel64/linker.ld>
#else
#include <zephyr/arch/x86/ia32/linker.ld>
#endif /* CONFIG_X86_64 */
``` | /content/code_sandbox/soc/intel/alder_lake/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```yaml
vendor: intel
comment: "Intel Elkhart Lake SoC"
socs:
- name: elkhart_lake
``` | /content/code_sandbox/soc/intel/elkhart_lake/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```c
/*
*/
#include <zephyr/kernel.h>
uint8_t x86_cpu_loapics[] = { 0x00, 0x02, 0x04, 0x06 };
``` | /content/code_sandbox/soc/intel/elkhart_lake/cpu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the Elkhart Lake SoC
*
* This header file is used to specify and describe soc-level aspects for
* the 'Elkhart Lake' SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <zephyr/device.... | /content/code_sandbox/soc/intel/elkhart_lake/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 205 |
```objective-c
/*
*
*/
/**
* @file
* @brief GPIO macros for the Elkhart Lake SoC
*
* This header file is used to specify the GPIO macros for
* the ELkhart Lake SoC.
*/
#ifndef __SOC_GPIO_H_
#define __SOC_GPIO_H_
#define GPIO_INTEL_NR_SUBDEVS 15
#define REG_PAD_OWNER_BASE 0x0020
#define REG_GPI... | /content/code_sandbox/soc/intel/elkhart_lake/soc_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 382 |
```unknown
config SOC_ELKHART_LAKE
select X86
select X86_64
select CPU_ATOM
select PCIE
select PCIE_MSI
select DYNAMIC_INTERRUPTS
select X86_MMU
``` | /content/code_sandbox/soc/intel/elkhart_lake/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
# Elkhart Lake SoC configuration options
if SOC_ELKHART_LAKE
config PCIE_MMIO_CFG
default y
config X86_DYNAMIC_IRQ_STUBS
default 16
depends on DYNAMIC_INTERRUPTS
endif # SOC_ELKHART_LAKE
``` | /content/code_sandbox/soc/intel/elkhart_lake/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```linker script
/*
*
*/
#include <zephyr/arch/x86/memory.ld>
#ifdef CONFIG_X86_64
#include <zephyr/arch/x86/intel64/linker.ld>
#else
#include <zephyr/arch/x86/ia32/linker.ld>
#endif /* CONFIG_X86_64 */
``` | /content/code_sandbox/soc/intel/elkhart_lake/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```unknown
# Intel ISH family selection
#
#
config SOC_FAMILY_INTEL_ISH
bool
config SOC_FAMILY
default "intel_ish" if SOC_FAMILY_INTEL_ISH
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/intel/intel_ish/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```yaml
family:
- name: intel_ish
series:
- name: intel_ish5
socs:
- name: intel_ish_5_4_1
- name: intel_ish_5_6_0
- name: intel_ish_5_8_0
``` | /content/code_sandbox/soc/intel/intel_ish/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
# Intel ISH family configuration options
#
#
config SOC_FAMILY_INTEL_ISH
select X86
select X86_NO_SPECULATIVE_VULNERABILITIES
select IOAPIC
select LOAPIC
select CPU_HAS_FPU
select INTEL_HAL
select HAS_PM
select HAS_COVERAGE_SUPPORT
``` | /content/code_sandbox/soc/intel/intel_ish/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# Intel ISH family default configuration options
#
#
if SOC_FAMILY_INTEL_ISH
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if HPET_TIMER
default 96000000 if APIC_TIMER_TSC && SOC_INTEL_ISH_5_4_1
default 100000000 if APIC_TIMER_TSC && !SOC_INTEL_ISH_5_4_1
config X86_VERY_EARLY_CONSOLE
default n
con... | /content/code_sandbox/soc/intel/intel_ish/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```unknown
#
#
if SOC_SERIES_INTEL_ISH5
rsource "pm/Kconfig.pm"
endif # SOC_SERIES_INTEL_ISH5
``` | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
#
config SOC_SERIES_INTEL_ISH5
bool
select SOC_FAMILY_INTEL_ISH
config SOC_SERIES
default "intel_ish5" if SOC_SERIES_INTEL_ISH5
config SOC_INTEL_ISH_5_4_1
bool
select SOC_SERIES_INTEL_ISH5
config SOC_INTEL_ISH_5_6_0
bool
select SOC_SERIES_INTEL_ISH5
config SOC_INTEL_ISH_5_8_0
bool
select SOC_SE... | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 197 |
```c
/*
*
*/
#include <zephyr/init.h>
#include "soc.h"
#if defined(CONFIG_HPET_TIMER)
#include "sedi_driver_hpet.h"
#endif
static int intel_ish_init(void)
{
#if defined(CONFIG_HPET_TIMER)
sedi_hpet_set_min_delay(HPET_CMP_MIN_DELAY);
#endif
return 0;
}
SYS_INIT(intel_ish_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_P... | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```linker script
/*
*
*/
#include <zephyr/arch/x86/memory.ld>
#include <zephyr/arch/x86/ia32/linker.ld>
``` | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```objective-c
/*
*
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <zephyr/device.h>
#include <zephyr/random/random.h>
#ifdef CONFIG_HPET_TIMER
#include "sedi_driver_hpet.h"
#define HPET_USE_CUSTOM_REG_ACCESS_FUNCS
/* COUNTER_CLK_PERIOD (CLK_PERIOD_REG) is in pic... | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 214 |
```perl6
# Intel ISH family PM default configuration options
#
#
if PM
config GDT_DYNAMIC
default y
config PM_DEVICE
default y
config GDT_RESERVED_NUM_ENTRIES
default 3
config REBOOT
default y
config PM_NEED_ALL_DEVICES_IDLE
default y
endif
``` | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/pm/Kconfig.pm | perl6 | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/policy.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log_core.h>
#include <stdio.h>
#include <zephyr/drivers/interrupt_controller/ioapic.h>
#include <zephyr/logging/log.h>
... | /content/code_sandbox/soc/intel/intel_ish/intel_ish5/pm/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 508 |
```cmake
#
#
if(CONFIG_PM)
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND ${CMAKE_OBJCOPY} -O binary --remove-section=aon
${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} ${PROJECT_BINARY_DIR}/ish_kernel.bin
COMMAND ${CMAKE_OBJCOPY} -O binary --only-section=aon
${ZEPHYR_BINARY_DIR}/${KER... | /content/code_sandbox/soc/intel/intel_ish/utils/build_ish_firmware.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```unknown
config SOC_APOLLO_LAKE
bool
config SOC
default "apollo_lake" if SOC_APOLLO_LAKE
``` | /content/code_sandbox/soc/intel/apollo_lake/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```c
/*
*/
#include <zephyr/kernel.h>
uint8_t x86_cpu_loapics[] = { 0x00, 0x02, 0x04, 0x06 };
``` | /content/code_sandbox/soc/intel/apollo_lake/cpu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
vendor: intel
comment: "Intel Apollo Lake SoC"
socs:
- name: apollo_lake
``` | /content/code_sandbox/soc/intel/apollo_lake/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```python
#!/usr/bin/env python3
# -*- coding: utf-8 -*-"
"""Script to pack EC binary with manifest header.
Package ecos main FW binary (kernel) and AON task binary into final EC binary
image with a manifest header, ISH shim loader will parse this header and load
each binaries into right memory location.
"""
import... | /content/code_sandbox/soc/intel/intel_ish/utils/build_ish_firmware.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 872 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the Apollo Lake SoC
*
* This header file is used to specify and describe soc-level aspects for
* the 'Apollo Lake' SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <zephyr/device.h>... | /content/code_sandbox/soc/intel/apollo_lake/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
# Apollo Lake SoC configuration options
if SOC_APOLLO_LAKE
config PCIE_MMIO_CFG
default y
if APIC_TIMER
config APIC_TIMER_IRQ
default 24
endif # APIC_TIMER
config X86_DYNAMIC_IRQ_STUBS
default 16
depends on DYNAMIC_INTERRUPTS
endif # SOC_APOLLO_LAKE
``` | /content/code_sandbox/soc/intel/apollo_lake/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
config SOC_APOLLO_LAKE
select X86
select X86_64
select CPU_APOLLO_LAKE
select PCIE
select PCIE_MSI
select DYNAMIC_INTERRUPTS
select X86_MMU
select ARCH_HAS_RESERVED_PAGE_FRAMES
``` | /content/code_sandbox/soc/intel/apollo_lake/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```linker script
/*
*
*/
#include <zephyr/arch/x86/memory.ld>
#ifdef CONFIG_X86_64
#include <zephyr/arch/x86/intel64/linker.ld>
#else
#include <zephyr/arch/x86/ia32/linker.ld>
#endif /* CONFIG_X86_64 */
``` | /content/code_sandbox/soc/intel/apollo_lake/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```unknown
config SOC_FAMILY_INTEL_SOCFPGA_STD
bool
config SOC_FAMILY
default "intel_socfpga_std" if SOC_FAMILY_INTEL_SOCFPGA_STD
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```yaml
family:
- name: intel_socfpga_std
series:
- name: cyclonev
socs:
- name: cyclonev
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
if SOC_FAMILY_INTEL_SOCFPGA_STD
rsource "*/Kconfig.defconfig.series"
endif # SOC_FAMILY_INTEL_SOCFPGA_STD
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
if SOC_FAMILY_INTEL_SOCFPGA_STD
rsource "*/Kconfig"
endif # SOC_FAMILY_INTEL_SOCFPGA_STD
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
config SOC_SERIES_CYCLONEV
bool
select SOC_FAMILY_INTEL_SOCFPGA_STD
help
Intel SoC FPGA Cyclone V Series
config SOC_SERIES
default "cyclonev" if SOC_SERIES_CYCLONEV
config SOC_CYCLONEV
bool
select SOC_SERIES_CYCLONEV
help
Intel SoC FPGA Cyclone V
config SOC
default "cyclonev" if SOC_CYCLONE... | /content/code_sandbox/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```unknown
if SOC_SERIES_CYCLONEV
rsource "Kconfig.defconfig.cyclonev*"
endif # SOC_SERIES_CYCLONEV
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
if SOC_CYCLONEV
config NUM_IRQS
int
default 211
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 231250000
endif
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```objective-c
/*
*
*/
/**
* @file
* @brief GPIO macros for the Apollo Lake SoC
*
* This header file is used to specify the GPIO pins and macros for
* the Apollo Lake SoC.
*/
#ifndef __SOC_GPIO_H_
#define __SOC_GPIO_H_
#define REG_PAD_OWNER_BASE 0x0020
#define REG_GPI_INT_STS_BASE 0x0... | /content/code_sandbox/soc/intel/apollo_lake/soc_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,112 |
```c
/*
* Description:
* Adding support for Cyclone V SoC FPGA, buildi mmu table,
* creating function to reserve the vector memory area
*/
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <zephyr/sys/util.h>
#include <mmu.h>
#include <zephyr/arch/arm/mmu/arm_mmu.h>
#inclu... | /content/code_sandbox/soc/intel/intel_socfpga_std/cyclonev/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 571 |
```objective-c
/*
* Description:
* Adding support for Cyclone V SoC FPGA
*/
#ifndef _SOC_H_
#define _SOC_H_
#ifndef _ASMLANGUAGE
#define __CORTEX_A 9U
#endif
#endif /* _SOC_H_ */
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/cyclonev/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config SOC_SERIES_CYCLONEV
select ARM
select CPU_CORTEX_A9
select ARM_AARCH32_MMU
select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
select ARCH_HAS_RESERVED_PAGE_FRAMES
``` | /content/code_sandbox/soc/intel/intel_socfpga_std/cyclonev/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```unknown
# Intel CAVS SoC series selection
#
config SOC_FAMILY_INTEL_ADSP
bool
config SOC_FAMILY
default "intel_adsp" if SOC_FAMILY_INTEL_ADSP
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/intel/intel_adsp/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```yaml
family:
- name: intel_adsp
series:
- name: intel_adsp_ace
socs:
- name: ace15_mtpm
- name: ace20_lnl
- name: ace30_ptl
- name: intel_adsp_cavs
socs:
- name: cavs25
``` | /content/code_sandbox/soc/intel/intel_adsp/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
# Intel CAVS SoC family default configuration options
#
if SOC_FAMILY_INTEL_ADSP
rsource "*/Kconfig.defconfig.series"
# A workaround for HWMv2 to recover SOF arch/xtensa defaults overridden by arch/host.
if SOF
config CORE_COUNT
int
default MP_MAX_NUM_CPUS
endif
config XTENSA_RPO_CACHE
def_bool y
# c... | /content/code_sandbox/soc/intel/intel_adsp/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 231 |
```unknown
#
config SOC_SERIES_INTEL_ADSP_CAVS
bool
select SOC_FAMILY_INTEL_ADSP
help
Intel ADSP CAVS
config SOC_SERIES
default "intel_adsp_cavs" if SOC_SERIES_INTEL_ADSP_CAVS
config SOC_INTEL_CAVS_V25
bool
select SOC_SERIES_INTEL_ADSP_CAVS
help
Intel Tiger Lake
config SOC
default "cavs25" if SOC_INTE... | /content/code_sandbox/soc/intel/intel_adsp/cavs/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 133 |
```unknown
#
if SOC_SERIES_INTEL_ADSP_CAVS
config INTEL_ADSP_CAVS
def_bool y
rsource "Kconfig.defconfig.cavs*"
config DMA_INTEL_ADSP_GPDMA
default y
depends on DMA
config XTENSA_CCOUNT_HZ
default 400000000
config SYS_CLOCK_TICKS_PER_SEC
default 50000
config SMP
default y
config XTENSA_TIMER
default n
co... | /content/code_sandbox/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 166 |
```unknown
# Intel CAVS SoC family configuration options
#
config SOC_FAMILY_INTEL_ADSP
select WINSTREAM
select ARCH_SUPPORTS_COREDUMP
select CPU_HAS_DCACHE
select ARCH_HAS_USERSPACE if XTENSA_MMU
imply XTENSA_MMU_DOUBLE_MAP
select CPU_CACHE_INCOHERENT
if SOC_FAMILY_INTEL_ADSP
rsource "*/Kconfig"
DT_COMPAT_IN... | /content/code_sandbox/soc/intel/intel_adsp/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 906 |
```objective-c
*/
#ifndef __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__
#define __ZEPHYR_CAVS_LIB_ASM_LDO_MANAGEMENT_H__
#ifdef _ASMLANGUAGE
#define SHIM_BASE 0x00071F00
#define SHIM_LDOCTL 0xA4
#define SHIM_LDOCTL_HPSRAM_MASK (3 << 0 | 3 << 16)
#define SHIM_LDOCTL_LPSRAM_MASK (3 << 2)
#define SHIM_LDOCTL_HPSRAM_LDO... | /content/code_sandbox/soc/intel/intel_adsp/cavs/asm_ldo_management.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,084 |
```c
*/
#include <zephyr/kernel.h>
#include <cavs-idc.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
#include <zephyr/irq.h>
#include <zephyr/pm/pm.h>
#include <zephyr/cache.h>
#include <ipi.h>
/* IDC power up message to the ROM firmware. This isn't documented
* anywhere, it's basically just a magic number (exc... | /content/code_sandbox/soc/intel/intel_adsp/cavs/multiprocessing.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,089 |
```unknown
#
config SOC_SERIES_INTEL_ADSP_CAVS
select XTENSA
select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
select XTENSA_RESET_VECTOR
select XTENSA_USE_CORE_CRT1
select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
select ATOM... | /content/code_sandbox/soc/intel/intel_adsp/cavs/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```c
*/
#include <zephyr/device.h>
#include <xtensa/xtruntime.h>
#include <zephyr/irq_nextlevel.h>
#include <xtensa/hal.h>
#include <zephyr/init.h>
#include <zephyr/logging/log.h>
#include <zephyr/irq.h>
#include <adsp_shim.h>
#include <cavs-idc.h>
#include <adsp_interrupt.h>
#include "soc.h"
#ifdef CONFIG_DYNAMIC_... | /content/code_sandbox/soc/intel/intel_adsp/cavs/irq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,349 |
```unknown
*/
#include "asm_ldo_management.h"
#include "asm_memory_management.h"
#include "adsp_memory.h"
#define IPC_HOST_BASE 0x00071E00
#define IPC_DIPCIDD 0x18
#define IPC_DIPCIDR 0x10
.section .text, "ax"
.align 64
power_down_literals:
.literal_position
set_dx_reply:
/* BUSY (bit31), MODULE_MSG (bit30),... | /content/code_sandbox/soc/intel/intel_adsp/cavs/power_down_cavs.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,145 |
```objective-c
*/
#ifndef __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
#define __ZEPHYR_CAVS_LIB_ASM_MEMORY_MANAGEMENT_H__
#ifdef _ASMLANGUAGE
#define HSPGCTL0 0x71D10
#define HSRMCTL0 0x71D14
#define HSPGISTS0 0x71D18
#define LSPGCTL 0x71D50
#define LSRMCTL 0x71D54
#define LSPGISTS 0x71D58
#define SHIM_HS... | /content/code_sandbox/soc/intel/intel_adsp/cavs/asm_memory_management.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 705 |
```unknown
if SOC_INTEL_CAVS_V25
# For backward compatibility, to be removed
config SOC_SERIES_INTEL_CAVS_V25
def_bool y
# Hardware has four cores, limited to two pending test fixes
config MP_MAX_NUM_CPUS
default 2
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 400000000 if XTENSA_TIMER
default 38400000 if INTEL_AD... | /content/code_sandbox/soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 329 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <xtensa/xtruntime.h>
#include <zephyr/irq_nextlevel.h>
#include <xtensa/hal.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <zephyr/device.h>
#include <zephyr/cache.h>
#include <cpu_init.h>
#include <adsp_memory.h>
#include <... | /content/code_sandbox/soc/intel/intel_adsp/cavs/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,429 |
```c
*/
#include <stddef.h>
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <soc_util.h>
#include <zephyr/cache.h>
#include <adsp_shim.h>
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"
#define DELAY_COUNT 256
#define LPSRAM_MASK(x) 0x00000003
#define PLATFORM_INIT_HPSRAM
#define... | /content/code_sandbox/soc/intel/intel_adsp/cavs/sram.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,220 |
```objective-c
/*
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one fla... | /content/code_sandbox/soc/intel/intel_adsp/cavs/_soc_inthandlers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,929 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
/* macros related to interrupt handling */
#define XTENSA_IRQ_NUM_SHIFT 0
#define CAVS_IRQ_NUM_SHIFT 8
#define XTENSA_IRQ_NUM_MASK 0xff
#define CAVS_IRQ_NUM_MASK 0xff
/*
* IRQs are mapped on 2 levels... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/adsp_interrupt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 412 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_TGL_IMR_LAYOUT_H_
#define ZEPHYR_SOC_INTEL_ADSP_TGL_IMR_LAYOUT_H_
/* These structs and macros are from the ROM code header
* on cAVS platforms, please keep them immutable.
*
* The ROM structs and code is lifted from:
* path_to_url
* 6c0db22c65 - platform: cavs: con... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/cavs25/adsp_imr_layout.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 255 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the intel_apl_adsp platform
*/
OUTPUT_ARCH(xtensa)
#include <zephyr/devicetree.h>
#include <xtensa/config/core-isa.h>
#include <zephyr/linker/sections.h>
#include <adsp-vectors.h>
#include <adsp_memory.h>
#include ... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/xtensa-cavs-linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,128 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <adsp-vectors.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(sram0)))
#define LP_SRAM_BASE (DT_REG_ADDR(DT_NODELABE... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/cavs25/adsp_memory.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,153 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_IPC_REGS_H_
#define ZEPHYR_SOC_INTEL_ADSP_IPC_REGS_H_
#include <intel_adsp_ipc_devtree.h>
#include <stdint.h>
/**
* @brief IPC registers layout for Intel ADSP cAVS TGL SoCs.
*/
struct intel_adsp_ipc {
uint32_t tdr;
uint32_t tda;
uint32_t tdd;
uint32_t unused0;
u... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/cavs25/adsp_ipc_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 206 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_H__
/* DMIC timestamping registers */
#define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000
#define TS_DMIC_LOCAL_OFFS_OFFSET 0x004
#define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008
... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/cavs25/dmic_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,447 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
/* The "shim" block contains most of the general system control
* registers on cAVS platforms. While the base address changes, it
* has remained largely, but not perfectly, compatible between
* versions.
*/
#ifnd... | /content/code_sandbox/soc/intel/intel_adsp/cavs/include/cavs25/adsp_shim.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,662 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/kernel_structs.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/sys_io.h>
#include <xtensa/config/core-isa.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc_mp... | /content/code_sandbox/soc/intel/intel_adsp/common/multiprocessing.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,211 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/linker/section_tags.h>
extern void power_init(void);
extern void adsp_clock_init(void);
#if CONFIG_MP_MAX_NUM_CPUS > 1
extern void soc_mp_init(void);
#endif
static __imr int soc_init(void)
{
power_init();
#ifdef CONFIG_ADSP_CLOCK
adsp_clock_init();
#endif
... | /content/code_sandbox/soc/intel/intel_adsp/common/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```c
*/
#include <stddef.h>
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc_util.h>
#include <zephyr/cache.h>
#include <adsp_shim.h>
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"
/* Important note about linkage:
*
* The C... | /content/code_sandbox/soc/intel/intel_adsp/common/boot.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,248 |
```c
*/
#include <zephyr/spinlock.h>
#include <intel_adsp_ipc.h>
#include <adsp_ipc_regs.h>
#include <adsp_interrupt.h>
#include <zephyr/irq.h>
#include <zephyr/pm/state.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/device.h>
#include <zephyr/pm/policy.h>
#include <errno.h>
void intel_adsp_ipc_set_message_handle... | /content/code_sandbox/soc/intel/intel_adsp/common/ipc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,667 |
```c
*/
#include <manifest.h>
#include <adsp_memory.h>
#include <zephyr/toolchain.h>
/* These two modules defined here aren't runtime data used by Zephyr or
* SOF with IPC3, but instead are inserted to *MANIFEST* of the final
* firmware binary by rimage and later will be used by ROM loader on the
* DSP. As it happ... | /content/code_sandbox/soc/intel/intel_adsp/common/rimage_modules.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 531 |
```c
*/
#include <zephyr/arch/xtensa/arch.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
#include <errno.h>
#include <zephyr/cache.h>
#include <mem_window.h>
int boot_complete(void)
{
uint32_t *win;
const struct mem_win_config *config;
const struct device *dev = DEVICE_DT_G... | /content/code_sandbox/soc/intel/intel_adsp/common/boot_complete.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 186 |
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