text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```linker script
/*
*
*/
/*
* Respect for CONFIG_ROM_START_OFFSET is mandatory
* for MCUboot support, so .reset.* and .exception.*
* must come after that offset from ROM_BASE.
*/
#ifdef CONFIG_BOOTLOADER_MCUBOOT
/*
* For CONFIG_BOOTLOADER_MCUBOOT, the vector table is located at the
* end of the image heade... | /content/code_sandbox/soc/openisa/rv32m1/vector_table.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 195 |
```yaml
socs:
- name: openisa_rv32m1
cpuclusters:
- name: zero_riscy
- name: ri5cy
``` | /content/code_sandbox/soc/openisa/rv32m1/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```objective-c
/*
*
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_ZERO_RISCY_H_
/* Control and Status Registers (CSRs) available for ZERO_RISCY. */
#define ZERO_RISCY_MSTATUS 0x300U
#define ZERO_RISCY_MTVEC 0x305U
#define ZERO_RISCY_MEPC 0x341U
#define ZERO_RISC... | /content/code_sandbox/soc/openisa/rv32m1/soc_zero_riscy.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 365 |
```objective-c
/*
*
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
#include <fsl_device_registers.h>
#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/*
* Ensure ... | /content/code_sandbox/soc/openisa/rv32m1/soc_offsets.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 425 |
```unknown
/*
*
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <soc.h>
/* Exports */
GTEXT(__soc_handle_irq)
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
#endif
/*
* With a0 == irq_num, this is equivalent to:
*
* EVENT_UNIT->INTPTPENDCLEAR =... | /content/code_sandbox/soc/openisa/rv32m1/soc_irq.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 780 |
```objective-c
/*
*
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE.
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_CONTEXT_H_
#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
/* Extra state for RI5CY hardware loop registers. */
#define SOC_ESF_MEMBERS ... | /content/code_sandbox/soc/openisa/rv32m1/soc_context.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```linker script
/*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#include <zephyr/linker/sections.h>
#include <zephyr/devicetree.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#define RAMABLE_REGION RAM :sram0_phdr
#define R... | /content/code_sandbox/soc/cdns/xtensa_sample_controller/include/xtensa-sample-controller.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 6,812 |
```unknown
/*
*
*/
#include <zephyr/linker/sections.h>
#include <zephyr/toolchain.h>
#include <zephyr/arch/cpu.h>
/* Exports */
GTEXT(_WdogInit)
/* WDOG instance base address. */
#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
#define WDOG_BASE 0x4002A000 /* WDOG0 */
#else
#define WDOG_BASE 0x41026000 /* WDOG1 */
#endif
/... | /content/code_sandbox/soc/openisa/rv32m1/wdog.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 447 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <fsl_clock.h>
#include <zephyr/sys/util.h>
#if defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
#include <errno.h>
#include <zephyr/irq_nextlevel.h>
#endif
#include <soc.h>
#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
#include <... | /content/code_sandbox/soc/openisa/rv32m1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,841 |
```objective-c
/*
*
*/
/*
* @file
* OpenISA RV32M1 SOC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_RISCV_OPENISA_RV32M1_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RISCV_OPENISA_RV32M1_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef ui... | /content/code_sandbox/soc/openisa/rv32m1/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 420 |
```objective-c
/*
*
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_H_
#ifndef _ASMLANGUAGE
#include "fsl_device_registers.h"
#include <zephyr/types.h>
/*
* Helpers related to interrupt handling. This SoC has two levels of
* interrupts.
*
* Level 1 interrupts go straight to... | /content/code_sandbox/soc/openisa/rv32m1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 892 |
```unknown
# RV32M1 SoC RISC-V core default configuration values
if SOC_OPENISA_RV32M1
# 32 from event unit + 32 * (1 + max enabled INTMUX channel)
config NUM_IRQS
default 288 if RV32M1_INTMUX_CHANNEL_7
default 256 if RV32M1_INTMUX_CHANNEL_6
default 224 if RV32M1_INTMUX_CHANNEL_5
default 192 if RV32M1_INTMUX_CHA... | /content/code_sandbox/soc/openisa/rv32m1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 733 |
```unknown
config SOC_OPENISA_RV32M1
select RISCV
select XIP
select HAS_RV32M1_LPUART
select HAS_RV32M1_LPI2C
select HAS_RV32M1_LPSPI
select HAS_RV32M1_TPM
select ATOMIC_OPERATIONS_C
select VEGA_SDK_HAL
select RISCV_SOC_INTERRUPT_INIT
select CLOCK_CONTROL
select HAS_RV32M1_FTFX
select HAS_FLASH_LOAD_OFFSET... | /content/code_sandbox/soc/openisa/rv32m1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```objective-c
/*
*
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_RI5CY_H_
/* Control and Status Registers (CSRs) available for RI5CY. */
#define RI5CY_USTATUS 0x000
#define RI5CY_UTVEC 0x005
#define RI5CY_UHARTID 0x014
#define RI5CY_UEPC 0x041
#define RI5CY_... | /content/code_sandbox/soc/openisa/rv32m1/soc_ri5cy.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 499 |
```unknown
config SOC_SERIES_STARFIVE_JH71XX
bool
help
Starfive JH71XX series
config SOC_JH7100
bool
select SOC_SERIES_STARFIVE_JH71XX
help
Starfive JH7100
config SOC_JH7110
bool
select SOC_SERIES_STARFIVE_JH71XX
help
Starfive JH7110
config SOC_SERIES
default "starfive_jh71xx" if SOC_SERIES_STARFI... | /content/code_sandbox/soc/starfive/jh71xx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```yaml
series:
- name: starfive_jh71xx
socs:
- name: jh7100
- name: jh7110
``` | /content/code_sandbox/soc/starfive/jh71xx/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
if SOC_SERIES_STARFIVE_JH71XX
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 6250000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config NUM_IRQS
default 139
endif
``` | /content/code_sandbox/soc/starfive/jh71xx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```unknown
config SOC_SERIES_STARFIVE_JH71XX
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_JH7100
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
selec... | /content/code_sandbox/soc/starfive/jh71xx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 202 |
```unknown
config SOC_FAMILY_RENESAS_RA
bool
config SOC_FAMILY
default "renesas_ra" if SOC_FAMILY_RENESAS_RA
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/renesas/ra/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```yaml
family:
- name: renesas_ra
series:
- name: ra2a1
socs:
- name: r7fa2a1ab3cfm
- name: ra4m1
socs:
- name: r7fa4m1ab3cfm
- name: ra6m1
socs:
- name: r7fa6m1ad3cfp
- name: ra6m2
socs:
- name: r7fa6m2af3cfb
-... | /content/code_sandbox/soc/renesas/ra/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 348 |
```linker script
/*
*
* This file is based on:
*
* - include/arch/arm/cortex_m/scripts/linker.ld
* - include/arch/riscv/common/linker.ld
* - include/arch/riscv/pulpino/linker.ld
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/linker/sections.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/link... | /content/code_sandbox/soc/openisa/rv32m1/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,794 |
```unknown
if SOC_FAMILY_RENESAS_RA
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_RENESAS_RA
``` | /content/code_sandbox/soc/renesas/ra/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
config SOC_FAMILY_RENESAS_RA
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_RENESAS_RA
config SERIES_SPECIFIC_SOC_INIT
bool "Use series specific initialize"
rsource "*/Kconfig"
endif # SOC_FAMILY_RENESAS_RA
``` | /content/code_sandbox/soc/renesas/ra/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
config SOC_SERIES_RA6M5
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6M5 series
config SOC_R7FA6M5BH3CFC
bool
select SOC_SERIES_RA6M5
help
R7FA6M5BH3CFC
config SOC_SERIES
default "ra6m5" if SOC_SERIES_RA6M5
config SOC
default "r7fa6m5bh3cfc" if SOC_R7FA6M5BH3CFC
``` | /content/code_sandbox/soc/renesas/ra/ra6m5/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6M5 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6m5/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 454 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6M5 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6M5_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6m5/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA6M5
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6M5
``` | /content/code_sandbox/soc/renesas/ra/ra6m5/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6m5/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```unknown
config SOC_SERIES_RA6M5
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6m5/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
config SOC_SERIES_RA8M1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA8M1 series
config SOC_R7FA8M1AHECBD
bool
select SOC_SERIES_RA8M1
help
R7FA8M1AHECBD
config SOC_SERIES
default "ra8m1" if SOC_SERIES_RA8M1
config SOC
default "r7fa8m1ahecbd" if SOC_R7FA8M1AHECBD
``` | /content/code_sandbox/soc/renesas/ra/ra8m1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA8M1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.... | /content/code_sandbox/soc/renesas/ra/ra8m1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 249 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA8M1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA8M1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA8M1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA8M1_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra8m1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA8M1
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA8M1
``` | /content/code_sandbox/soc/renesas/ra/ra8m1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra8m1/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```unknown
config SOC_SERIES_RA8M1
select ARM
select CPU_CORTEX_M85
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_HAS_ARM_SAU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select HAS_RENESAS_RA_FSP
help
Enable support for Renesas RA8M... | /content/code_sandbox/soc/renesas/ra/ra8m1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```unknown
config SOC_SERIES_RA6M4
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6M4 series
config SOC_R7FA6M4AF3CFB
bool
select SOC_SERIES_RA6M4
help
R7FA6M4AF3CFB
config SOC_SERIES
default "ra6m4" if SOC_SERIES_RA6M4
config SOC
default "r7fa6m4af3cfb" if SOC_R7FA6M4AF3CFB
``` | /content/code_sandbox/soc/renesas/ra/ra6m4/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6M4 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6m4/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 454 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6m4/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6M4 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6M4_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6m4/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA6M4
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6M4
``` | /content/code_sandbox/soc/renesas/ra/ra6m4/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config SOC_SERIES_RA6M4
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6m4/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cmsis_core_m_defaults.h>
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/common/ra_common_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
config SOC_SERIES_RA8T1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA8T1 series
config SOC_SERIES
default "ra8t1" if SOC_SERIES_RA8T1
config SOC_R7FA8T1AHECBD
bool
select SOC_SERIES_RA8T1
help
R7FA8T1AHECBD
config SOC
default "r7fa8t1ahecbd" if SOC_R7FA8T1AHECBD
``` | /content/code_sandbox/soc/renesas/ra/ra8t1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_PINCTRL_SOC_H_
enum {
PmnPFS_PODR_POS,
PmnPFS_PIDR_POS,
PmnPFS_PDR_POS,
PmnPFS_RSV3_POS,
PmnPFS_PCR_POS,
PmnPFS_RSV5_POS,
PmnPFS_NCODR_POS,
PmnPFS_RSV7_POS,
PmnPFS_RSV8_POS,
PmnPFS... | /content/code_sandbox/soc/renesas/ra/common/pinctrl_ra.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 703 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra8t1/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA8T1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA8T1_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra8t1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA8T1
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA8T1
``` | /content/code_sandbox/soc/renesas/ra/ra8t1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA8T1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.... | /content/code_sandbox/soc/renesas/ra/ra8t1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 249 |
```unknown
config SOC_SERIES_RA8D1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA8D1 series
config SOC_SERIES
default "ra8d1" if SOC_SERIES_RA8D1
config SOC_R7FA8D1BHECBD
bool
select SOC_SERIES_RA8D1
help
R7FA8D1BHECBD
config SOC
default "r7fa8d1bhecbd" if SOC_R7FA8D1BHECBD
``` | /content/code_sandbox/soc/renesas/ra/ra8d1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```unknown
config SOC_SERIES_RA8T1
select ARM
select CPU_CORTEX_M85
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_HAS_ARM_SAU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select HAS_RENESAS_RA_FSP
``` | /content/code_sandbox/soc/renesas/ra/ra8t1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA8D1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.... | /content/code_sandbox/soc/renesas/ra/ra8d1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 249 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA8D1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA8D1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA8D1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA8D1_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra8d1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA8D1
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA8D1
``` | /content/code_sandbox/soc/renesas/ra/ra8d1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config SOC_SERIES_RA8D1
select ARM
select CPU_CORTEX_M85
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select CPU_HAS_ARM_SAU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select HAS_RENESAS_RA_FSP
``` | /content/code_sandbox/soc/renesas/ra/ra8d1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra8d1/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```unknown
config SOC_SERIES_RA6M2
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6M2 series
config SOC_R7FA6M2AF3CFB
bool
select SOC_SERIES_RA6M2
help
R7FA6M2AF3CFB
config SOC_SERIES
default "ra6m2" if SOC_SERIES_RA6M2
config SOC
default "r7fa6m2af3cfb" if SOC_R7FA6M2AF3CFB
``` | /content/code_sandbox/soc/renesas/ra/ra6m2/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6m2/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```linker script
/*
*
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;
``` | /content/code_sandbox/soc/renesas/ra/ra6m2/opt_set_mem.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6M2 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6M2_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6m2/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA6M2
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6M2
``` | /content/code_sandbox/soc/renesas/ra/ra6m2/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6M2 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6m2/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 259 |
```unknown
config SOC_SERIES_RA6M2
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6m2/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
config SOC_SERIES_RA6M3
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6M3 series
config SOC_R7FA6M3AH3CFC
bool
select SOC_SERIES_RA6M3
help
R7FA6M3AH3CFC
config SOC_SERIES
default "ra6m3" if SOC_SERIES_RA6M3
config SOC
default "r7fa6m3ah3cfc" if SOC_R7FA6M3AH3CFC
``` | /content/code_sandbox/soc/renesas/ra/ra6m3/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6m3/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```linker script
/*
*
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;
``` | /content/code_sandbox/soc/renesas/ra/ra6m3/opt_set_mem.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6M3 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6M3_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6m3/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6M3 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6m3/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 259 |
```unknown
if SOC_SERIES_RA6M3
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6M3
``` | /content/code_sandbox/soc/renesas/ra/ra6m3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config SOC_SERIES_RA6E1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6E1 series
config SOC_R7FA6E10F2CFP
bool
select SOC_SERIES_RA6E1
help
R7FA6E10F2CFP
config SOC_SERIES
default "ra6e1" if SOC_SERIES_RA6E1
config SOC
default "r7fa6e10f2cfp" if SOC_R7FA6E10F2CFP
``` | /content/code_sandbox/soc/renesas/ra/ra6e1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```unknown
config SOC_SERIES_RA6M3
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6m3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6E1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6e1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 454 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6E1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6E1_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6e1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6e1/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 768 |
```unknown
if SOC_SERIES_RA6E1
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6E1
``` | /content/code_sandbox/soc/renesas/ra/ra6e1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
config SOC_SERIES_RA6E1
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6e1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
config SOC_SERIES_RA6E2
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6E2 series
config SOC_R7FA6E2BB3CFM
bool
select SOC_SERIES_RA6E2
help
R7FA6E2BB3CFM
config SOC_SERIES
default "ra6e2" if SOC_SERIES_RA6E2
config SOC
default "r7fa6e2bb3cfm" if SOC_R7FA6E2BB3CFM
``` | /content/code_sandbox/soc/renesas/ra/ra6e2/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6E2 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6e2/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 454 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6E2 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6E2_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6e2/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA6E2
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6E2
``` | /content/code_sandbox/soc/renesas/ra/ra6e2/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6e2/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 793 |
```unknown
config SOC_SERIES_RA6E2
select ARM
select CPU_CORTEX_M33
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select ARMV8_M_DSP
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6e2/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```objective-c
/*
*
*/
/* Keep for bsp_api.h */
#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_VECTOR_DATA_H_
#define ZEPHYR_SOC_RENESAS_RA_COMMON_VECTOR_DATA_H_
#endif /* ZEPHYR_SOC_RENESAS_RA_COMMON_VECTOR_DATA_H_ */
``` | /content/code_sandbox/soc/renesas/ra/common_fsp/vector_data.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
config SOC_SERIES_RA6M1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA6M1 series
config SOC_R7FA6M1AD3CFP
bool
select SOC_SERIES_RA6M1
help
R7FA6M1AD3CFP
config SOC_SERIES
default "ra6m1" if SOC_SERIES_RA6M1
config SOC
default "r7fa6m1ad3cfp" if SOC_R7FA6M1AD3CFP
``` | /content/code_sandbox/soc/renesas/ra/ra6m1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K align... | /content/code_sandbox/soc/renesas/ra/ra6m1/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```linker script
/*
*
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;
``` | /content/code_sandbox/soc/renesas/ra/ra6m1/opt_set_mem.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
/**
* @brief Type to hold a renesas ra pin's pinctrl configuration.
*... | /content/code_sandbox/soc/renesas/ra/common_fsp/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 619 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA6M1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA6M1_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra6m1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA6M1
config NUM_IRQS
default 96
config PINCTRL
default y
endif # SOC_SERIES_RA6M1
``` | /content/code_sandbox/soc/renesas/ra/ra6m1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA6M1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFI... | /content/code_sandbox/soc/renesas/ra/ra6m1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 259 |
```unknown
config SOC_SERIES_RA6M1
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU
select HAS_SWO
select XIP
``` | /content/code_sandbox/soc/renesas/ra/ra6m1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```linker script
/*
*
*
*/
. = 0x400;
FILL(0xFF)
KEEP(*(.opt_set_mem*))
. = 0x500;
``` | /content/code_sandbox/soc/renesas/ra/ra4m1/opt_set_mem.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config SOC_SERIES_RA4M1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA4M1
config SOC_R7FA4M1AB3CFM
bool
select SOC_SERIES_RA4M1
help
R7FA4M1AB3CFM
config SOC_SERIES
default "ra4m1" if SOC_SERIES_RA4M1
config SOC
default "r7fa4m1ab3cfm" if SOC_R7FA4M1AB3CFM
``` | /content/code_sandbox/soc/renesas/ra/ra4m1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 120 |
```objective-c
/*
*
*/
#include "../common/pinctrl_ra.h"
``` | /content/code_sandbox/soc/renesas/ra/ra4m1/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```objective-c
/*
*
*/
#include "../common/ra_common_soc.h"
``` | /content/code_sandbox/soc/renesas/ra/ra4m1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
if SOC_SERIES_RA4M1
config NUM_IRQS
default 32
endif # SOC_SERIES_RA4M1
``` | /content/code_sandbox/soc/renesas/ra/ra4m1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
config SOC_SERIES_RA4M1
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_SYSTICK
select DYNAMIC_INTERRUPTS
select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
select XIP
if SOC_SERIES_RA4M1
config SOC_OPTION_SETTING_MEMORY
bool "Option Setting Memory"
default y
endif
``` | /content/code_sandbox/soc/renesas/ra/ra4m1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
config SOC_SERIES_RA2A1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA2A1 series
config SOC_R7FA2A1AB3CFM
bool
select SOC_SERIES_RA2A1
help
R7FA2A1AB3CFM
config SOC_SERIES
default "ra2a1" if SOC_SERIES_RA2A1
config SOC
default "r7fa2a1ab3cfm" if SOC_R7FA2A1AB3CFM
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#define HOCO_FREQ DT_PROP(DT_PATH(clocks, hoco), clock_frequency)
#if HOCO_FREQ == MHZ(24)
#define OFS1_HOCO_FREQ 0
#elif HOCO_FREQ == MHZ(32)
#define OFS1_HOCO_FREQ 2
#elif HOCO_FREQ == MHZ(48)
#define OFS1_HOCO_FREQ 4
#elif HOCO_FREQ == MHZ(64)
#define OFS1_HOCO_FREQ 5
... | /content/code_sandbox/soc/renesas/ra/ra4m1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,275 |
```linker script
/*
*
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/rom_start.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for Renesas RA2A1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.... | /content/code_sandbox/soc/renesas/ra/ra2a1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 254 |
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