text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```c
/*
*
*/
#include <errno.h>
#include <zephyr/device.h>
#include <zephyr/kernel.h>
#include <zephyr/spinlock.h>
#include <zephyr/sys/util.h>
#include <adsp_clk.h>
#include <adsp_shim.h>
static struct adsp_cpu_clock_info platform_cpu_clocks[CONFIG_MP_MAX_NUM_CPUS];
static struct k_spinlock lock;
int adsp_clock... | /content/code_sandbox/soc/intel/intel_adsp/common/clk.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,250 |
```objective-c
/*
*
*/
#ifndef _ADSP_MEMORY_WINDOW_H_
#define _ADSP_MEMORY_WINDOW_H_
#define WIN_SIZE(N) (CONFIG_MEMORY_WIN_##N##_SIZE)
#define MEM_WINDOW_NODE(n) DT_NODELABEL(mem_window##n)
#define WIN0_OFFSET DT_PROP(MEM_WINDOW_NODE(0), offset)
#define WIN1_OFFSET WIN0_OFFSET + WIN_SIZE(0)
#define WIN2_OFFSET W... | /content/code_sandbox/soc/intel/intel_adsp/common/include/mem_window.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 316 |
```c
*/
#include <zephyr/cache.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/arch/cpu.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
#include <mem_window.h>
#include <soc_util.h>
/* host windows */
#define DMWBA(win_base) (win_base + 0x0)
#define DMWLO(win_base) (win_base + 0x4)
... | /content/code_sandbox/soc/intel/intel_adsp/common/mem_window.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 583 |
```objective-c
*/
#ifndef _ZEPHYR_SOC_INTEL_ADSP_DEBUG_WINDOW
#define _ZEPHYR_SOC_INTEL_ADSP_DEBUG_WINDOW
#include <mem_window.h>
#include <zephyr/debug/sparse.h>
#include <zephyr/cache.h>
/*
* SRAM window for debug info (window 2) is organized in slots,
* described in the descriptors available on page 0.
*
* --... | /content/code_sandbox/soc/intel/intel_adsp/common/include/adsp_debug_window.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 656 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_COMMON_UTIL_H_
#define ZEPHYR_SOC_INTEL_ADSP_COMMON_UTIL_H_
#include <zephyr/cache.h>
/* memcopy used by boot loader */
static ALWAYS_INLINE void bmemcpy(void *dest, void *src, size_t bytes)
{
volatile uint32_t *d = (uint32_t *)dest;
volatile uint32_t *s = (uin... | /content/code_sandbox/soc/intel/intel_adsp/common/include/soc_util.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 237 |
```objective-c
*/
#ifndef ZEPHYR_INCLUDE_INTEL_ADSP_IPC_H
#define ZEPHYR_INCLUDE_INTEL_ADSP_IPC_H
#include <intel_adsp_ipc_devtree.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/pm/device.h>
struct intel_adsp_ipc_config {
volatile struct intel_adsp_ipc *regs;
};
/**
* @brief Intel ADSP ... | /content/code_sandbox/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,753 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_
#define ZEPHYR_SOC_INTEL_ADSP_CAVS_IDC_H_
#include <intel_adsp_ipc_devtree.h>
/*
* (I)ntra (D)SP (C)ommunication is the facility for sending
* interrupts directly between DSP cores. The interface
* is... somewhat needlessly complicated.
*
* Each... | /content/code_sandbox/soc/intel/intel_adsp/common/include/cavs-idc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,918 |
```objective-c
*/
#ifndef __INTEL_ADSP_CPU_INIT_H
#define __INTEL_ADSP_CPU_INIT_H
#include <zephyr/arch/arch_inlines.h>
#include <zephyr/arch/xtensa/arch.h>
#include <xtensa/config/core-isa.h>
#include <xtensa/corebits.h>
#include <adsp_memory.h>
#define MEMCTL_VALUE (MEMCTL_INV_EN | MEMCTL_ICWU_MASK | MEMCTL_DCW... | /content/code_sandbox/soc/intel/intel_adsp/common/include/cpu_init.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,050 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_
#define ZEPHYR_SOC_INTEL_ADSP_DEBUG_HELPERS_H_
#include <adsp_memory.h>
#include <zephyr/linker/linker-defs.h>
extern char _imr_start[];
extern char _imr_end[];
extern char _end[];
extern char _heap_sentry[];
extern char _cached_start[];
extern char ... | /content/code_sandbox/soc/intel/intel_adsp/common/include/debug_helpers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 256 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_IPC_REGS_H
#define ZEPHYR_SOC_INTEL_ADSP_IPC_REGS_H
#include <zephyr/devicetree.h>
#include <stdint.h>
/**
* @brief Retrieve node identifier for Intel ADSP host IPC.
*/
#define INTEL_ADSP_IPC_HOST_DTNODE DT_NODELABEL(adsp_host_ipc)
/** @brief Host IPC device pointer... | /content/code_sandbox/soc/intel/intel_adsp/common/include/intel_adsp_ipc_devtree.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 290 |
```objective-c
/*
*
*
* Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
*/
#ifndef __INCLUDE_UAPI_USER_MANIFEST_H__
#define __INCLUDE_UAPI_USER_MANIFEST_H__
#include <stdint.h>
/* start offset for base FW module */
#define SOF_MAN_ELF_TEXT_OFFSET 0x2000
/* FW Extended Manifest Header id = $AE1 */
#defi... | /content/code_sandbox/soc/intel/intel_adsp/common/include/manifest.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,416 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_CAVS_CLK_H_
#define ZEPHYR_SOC_INTEL_ADSP_CAVS_CLK_H_
#include <stdint.h>
#include <adsp_shim.h>
struct adsp_cpu_clock_info {
uint32_t default_freq;
uint32_t current_freq;
uint32_t lowest_freq;
};
void adsp_clock_init(void);
/** @brief Set cAVS clock frequen... | /content/code_sandbox/soc/intel/intel_adsp/common/include/adsp_clk.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 757 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_
#define ZEPHYR_SOC_INTEL_ADSP_COMMON_SOC_H_
#include <string.h>
#include <errno.h>
#include <zephyr/linker/sections.h>
#include <adsp_interrupt.h>
/* DSP Wall Clock Timers (0 and 1) */
#define DSP_WCT_IRQ(x) \
SOC_AGGREGATE_IRQ((22 + x), CAVS_L2_A... | /content/code_sandbox/soc/intel/intel_adsp/common/include/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 434 |
```objective-c
*/
#ifndef ZEPHYR_INCLUDE_CAVS_TEST_H
#define ZEPHYR_INCLUDE_CAVS_TEST_H
/* The cavstool.py script that launched us listens for a very simple
* set of IPC commands to help test. Pass one of the following values
* as the "data" argument to intel_adsp_ipc_send_message(INTEL_ADSP_IPC_HOST_DEV, ...):
... | /content/code_sandbox/soc/intel/intel_adsp/common/include/cavstool.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 426 |
```objective-c
*/
#ifndef _ZEPHYR_SOC_INTEL_ADSP_VECTORS
#define _ZEPHYR_SOC_INTEL_ADSP_VECTORS
#include <xtensa/config/core-isa.h>
/* This is the base address of all the vectors defined in SRAM */
#define VECBASE_RESET_PADDR_SRAM \
(L2_SRAM_BASE + CONFIG_HP_SRAM_RESERVE)
#define MEM_VECBASE_LIT_SIZE ... | /content/code_sandbox/soc/intel/intel_adsp/common/include/adsp-vectors.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 493 |
```python
#!/usr/bin/env python3
import asyncio
import cavstool
if __name__ == "__main__":
try:
asyncio.run(cavstool.main())
except KeyboardInterrupt:
start_output = False
``` | /content/code_sandbox/soc/intel/intel_adsp/tools/acetool.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```objective-c
*/
#ifndef ZEPHYR_INCLUDE_INTEL_ADSP_HDA_H
#define ZEPHYR_INCLUDE_INTEL_ADSP_HDA_H
#include <zephyr/cache.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
#include <adsp_shim.h>
#include <adsp_memory.h>
#include <adsp_shim.h>
/**
* @brief HDA stream functionality... | /content/code_sandbox/soc/intel/intel_adsp/common/include/intel_adsp_hda.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,576 |
```python
#!/usr/bin/env python3
import os
import sys
import logging
import time
import argparse
import socket
import struct
import hashlib
from urllib.parse import urlparse
RET = 0
HOST = None
PORT = 0
PORT_LOG = 9999
PORT_REQ = PORT_LOG + 1
BUF_SIZE = 4096
# Define the command and its
# possible max size
CMD_LOG_ST... | /content/code_sandbox/soc/intel/intel_adsp/tools/cavstool_client.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,113 |
```shell
#!/bin/sh
set -e
# Twister integration tool for a remote ssh-accessible cAVS audio DSP
# host (e.g. an Up Squared board running Linux). Can be used as the
# hook for both --device-serial-pty and --west-flash, for example:
#
# export CAVS_OLD_FLASHER=1
# export CAVS_HOST=tgl2
# export CAVS_KEY=$HOME/otc_pri... | /content/code_sandbox/soc/intel/intel_adsp/tools/cavstwist.sh | shell | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,482 |
```python
#!/usr/bin/env python3
import os
import sys
import struct
import logging
import time
import subprocess
import argparse
import socketserver
import threading
import hashlib
import queue
from urllib.parse import urlparse
# Global variable use to sync between log and request services.
runner = None
# pylint: di... | /content/code_sandbox/soc/intel/intel_adsp/tools/remote-fw-service.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,358 |
```unknown
#
config SOC_SERIES_INTEL_ADSP_ACE
bool
select SOC_FAMILY_INTEL_ADSP
help
Intel ADSP ACE
config SOC_INTEL_ACE15_MTPM
bool
select SOC_SERIES_INTEL_ADSP_ACE
help
ACE 1.5 Meteor Lake PCH M
config SOC_INTEL_ACE20_LNL
bool
select SOC_SERIES_INTEL_ADSP_ACE
help
ACE 2.0 Lunar Lake PCH
config S... | /content/code_sandbox/soc/intel/intel_adsp/ace/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 287 |
```unknown
if SOC_SERIES_INTEL_ADSP_ACE
config SMP
default y
config POWER_DOMAIN
default y
# MTL leaves the upper mapping in the same spot as cAVS, but moves the
# lower one inexplicably.
config XTENSA_UNCACHED_REGION
default 2
# Parameters for gen_isr_tables.py:
config 2ND_LVL_INTR_00_OFFSET
default 4
confi... | /content/code_sandbox/soc/intel/intel_adsp/ace/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 387 |
```unknown
if SOC_INTEL_ACE20_LNL
config MP_MAX_NUM_CPUS
default 5
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 393216000 if XTENSA_TIMER
default 38400000 if INTEL_ADSP_TIMER
config XTENSA_CCOUNT_HZ
default 393216000
endif
``` | /content/code_sandbox/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```c
/*
*
*/
#include <zephyr/arch/xtensa/xtensa_mmu.h>
#include <zephyr/linker/linker-defs.h>
#include <adsp_memory.h>
#include <adsp_imr_layout.h>
#include <inttypes.h>
extern char _cached_start[];
extern char _cached_end[];
extern char _imr_start[];
extern char _imr_end[];
extern char __common_rom_region_start[... | /content/code_sandbox/soc/intel/intel_adsp/ace/mmu_ptl.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,520 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/check.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/arch/xtensa/arch.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/device_runtime.h>
#include <soc.h>
#include <adsp_boot.h>
#include <adsp_power.... | /content/code_sandbox/soc/intel/intel_adsp/ace/multiprocessing.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,088 |
```c
/*
*
*/
#include <errno.h>
#include <stdbool.h>
#include <stdint.h>
#include "comm_widget.h"
#include "pmc_interface.h"
/*
* Report number of used HP-SRAM memory banks to the PMC, unit is 32 KB.
*/
int adsp_comm_widget_pmc_send_ipc(uint16_t banks)
{
if (!cw_upstream_ready()) {
return -EBUSY;
}
uint32_... | /content/code_sandbox/soc/intel/intel_adsp/ace/comm_widget_messages.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 179 |
```unknown
if SOC_INTEL_ACE30_PTL
config MP_MAX_NUM_CPUS
default 5
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 442368000 if XTENSA_TIMER
default 38400000 if INTEL_ADSP_TIMER
config XTENSA_CCOUNT_HZ
default 442368000
config CPU_HAS_MMU
def_bool y
config XTENSA_MMU
def_bool y
config XTENSA_MMU_NUM_L2_TABLES
... | /content/code_sandbox/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30_ptl | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 147 |
```c
*/
#include <stddef.h>
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/cache.h>
#include <adsp_shim.h>
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"
#ifdef CONFIG_PM
#ifdef CONFIG_ADSP_IMR_CONTEXT_S... | /content/code_sandbox/soc/intel/intel_adsp/ace/boot.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 400 |
```python
#!/usr/bin/env python3
import os
import sys
import struct
import logging
import asyncio
import time
import subprocess
import ctypes
import mmap
import argparse
import pty
start_output = True
logging.basicConfig(level=logging.INFO)
log = logging.getLogger("cavs-fw")
PAGESZ = 4096
HUGEPAGESZ = 2 * 1024 * 102... | /content/code_sandbox/soc/intel/intel_adsp/tools/cavstool.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10,976 |
```c
/*
*
*/
#include <stdint.h>
#include <stdbool.h>
#include <zephyr/spinlock.h>
#include <zephyr/devicetree.h>
#include <adsp_shim.h>
#include <adsp_timestamp.h>
#define TTS_BASE_ADDR DT_REG_ADDR(DT_NODELABEL(tts))
#define TSCTRL_ADDR (TTS_BASE_ADDR + ADSP_TSCTRL_OFFSET)
#define ISCS_ADDR (TTS_BASE_... | /content/code_sandbox/soc/intel/intel_adsp/ace/timestamp.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 835 |
```unknown
#
config SOC_SERIES_INTEL_ADSP_ACE
select XTENSA
select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
select ARCH_HAS_COHERENCE
select SCHED_IPI_SUPPORTED
select ARCH_... | /content/code_sandbox/soc/intel/intel_adsp/ace/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 209 |
```c
/*
*
*/
#include <zephyr/drivers/interrupt_controller/dw_ace.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(ace_v1x_soc, CONFIG_SOC_LOG_LEVEL);
void z_soc_irq_enable(uint32_t irq)
{
const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(ace_intc));
const struct dw_ace_v1_ictl_driver_api *api;
... | /content/code_sandbox/soc/intel/intel_adsp/ace/irq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 354 |
```unknown
*/
#include "asm_memory_management.h"
.section .text, "ax"
.align 64
power_down_literals:
.literal_position
ipc_flag:
.word 0x80000000 // IPC_DIPCTDR_BUSY
sram_dis_loop_cnt:
.word 4096
.global power_down
.type power_down, @function
/**
* @brief Perform power down.
*
* Depending on arguments,... | /content/code_sandbox/soc/intel/intel_adsp/ace/power_down.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,251 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the intel_apl_adsp platform
*/
OUTPUT_ARCH(xtensa)
#include <zephyr/devicetree.h>
#include <xtensa/config/core-isa.h>
#include <zephyr/linker/sections.h>
#include <adsp-vectors.h>
#include <adsp_memory.h>
#include ... | /content/code_sandbox/soc/intel/intel_adsp/ace/ace-link.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,089 |
```objective-c
*/
#ifndef COMM_WIDGET_PMC_IPC_H
#define COMM_WIDGET_PMC_IPC_H
#define CW_PMC_MAILBOX3_DATA0_ADDRESS 0x68
#define CW_PMC_MAILBOX3_DATA1_ADDRESS 0x6c
#define CW_PMC_MAILBOX3_DATA2_ADDRESS 0x70
#define CW_PMC_MAILBOX3_DATA3_ADDRESS 0x74
#define CW_PMC_MAILBOX3_INTERFACE_ADDRESS 0x78
#define CW_PMC_... | /content/code_sandbox/soc/intel/intel_adsp/ace/pmc_interface.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 657 |
```objective-c
*/
/**
* @brief Macros for power gating memory banks specific for ACE 1.0
*/
#ifndef __ZEPHYR_ACE_LIB_ASM_MEMORY_MANAGEMENT_H__
#define __ZEPHYR_ACE_LIB_ASM_MEMORY_MANAGEMENT_H__
#ifdef _ASMLANGUAGE
/* These definitions should be placed elsewhere, but I can't find a good place for them. */
#define... | /content/code_sandbox/soc/intel/intel_adsp/ace/asm_memory_management.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 787 |
```linker script
*/
#include <zephyr/linker/devicetree_regions.h>
#include <ace-link.ld>
MEMORY
{
LINKER_DT_REGIONS()
}
SECTIONS
{
LINKER_DT_SECTIONS()
}
``` | /content/code_sandbox/soc/intel/intel_adsp/ace/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```objective-c
*/
#ifndef INTEL_COMM_WIDGET_H
#define INTEL_COMM_WIDGET_H
#include <zephyr/cache.h>
#include <zephyr/kernel.h>
#define CW_DT_NODE DT_NODELABEL(ace_comm_widget)
#define CW_BASE DT_REG_ADDR(CW_DT_NODE)
/*
* @brief DSP Communication Widget for Intel ADSP
*
* These registers control the DSP Com... | /content/code_sandbox/soc/intel/intel_adsp/ace/comm_widget.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,502 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <zephyr/pm/device_runtime.h>
#include <zephyr/device.h>
#include <zephyr/debug/sparse.h>
#include <zephyr/cache.h>
#include <cpu_init.h>
#include <soc_util.h>
#include <adsp_boot.h>
#include <adsp_power.h>
#include <adsp_memory.h>
#include <a... | /content/code_sandbox/soc/intel/intel_adsp/ace/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,088 |
```c
*/
#include <stddef.h>
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <soc_util.h>
#include <zephyr/cache.h>
#include <adsp_shim.h>
#include <adsp_memory.h>
#include <cpu_init.h>
#include "manifest.h"
#define DELAY_COUNT 256
__imr void hp_sram_init(uint32_t memory_size)
{
ARG_UNUSED(memory_siz... | /content/code_sandbox/soc/intel/intel_adsp/ace/sram.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 375 |
```c
/*
*
*/
#include "comm_widget.h"
/*
* Operation codes
*/
#define CW_OPCODE_CRRD 0x06
#define CW_OPCODE_CRWR 0x07
void cw_sb_write(uint32_t dest, uint32_t func, uint16_t address, uint32_t data)
{
cw_upstream_set_attr(dest, func, CW_OPCODE_CRWR, 0, 0);
cw_upstream_set_address16(address);
cw_upstream_set_da... | /content/code_sandbox/soc/intel/intel_adsp/ace/comm_widget.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```unknown
if SOC_INTEL_ACE15_MTPM
config MP_MAX_NUM_CPUS
default 3
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 393216000 if XTENSA_TIMER
default 38400000 if INTEL_ADSP_TIMER
config XTENSA_CCOUNT_HZ
default 393216000
endif
``` | /content/code_sandbox/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_TIMESTAMP_H_
#define ZEPHYR_SOC_INTEL_ADSP_ACE_TIMESTAMP_H_
#include <stdint.h>
/* Captured timestamp data - contains a copy of all DfTTS snapshot registers. */
struct intel_adsp_timestamp {
uint32_t iscs; /* copy of DfISCS register */
uint64_t lscs; /* ... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/adsp_timestamp.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 241 |
```objective-c
*/
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagge... | /content/code_sandbox/soc/intel/intel_adsp/ace/_soc_inthandlers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 958 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_REGIONS_H_
/* Define amount of regions other than core heaps that virtual memory will be split to
* currently includes shared heap and oma region and one regions set to 0 as for table
* iterator end value.
*/... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/adsp_memory_regions.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 210 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_IMR_LAYOUT_H_
#define ZEPHYR_SOC_INTEL_ADSP_ACE_IMR_LAYOUT_H_
/* These structs and macros are from the ROM code header
* on cAVS platforms, please keep them immutable
*/
/*
* A magic that tells ROM to jump to imr_restore_vector instead of normal boot
*/
#define... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/adsp_imr_layout.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 253 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#define ZEPHYR_SOC_INTEL_ADSP_MEMORY_H_
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
#include <adsp-vectors.h>
#include <mem_window.h>
#define L2_SRAM_BASE (DT_REG_ADDR(DT_NODELABEL(sram0)))
#define L2_SRAM_SIZE (DT_REG_SIZE(DT_NODELABEL(... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/adsp_memory.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,866 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_H__
/* DMIC timestamping registers */
#define TS_DMIC_LOCAL_TSCTRL_OFFSET 0x000
#define TS_DMIC_LOCAL_OFFS_OFFSET 0x004
#define TS_DMIC_LOCAL_SAMPLE_OFFSET 0x008
... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/dmic_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,566 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE1X_H__
/* Digital Mic Shim Registers */
/* Digital Microphone Link Capability */
#define DMICLCAP_OFFSET 0x00
/* Link Count */
#define DMICLCAP_LCOU... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/dmic_regs_ace1x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,026 |
```objective-c
/*
*/
/* Report number of used HP-SRAM memory banks to the PMC, unit is 32 KB. */
int adsp_comm_widget_pmc_send_ipc(uint16_t banks);
``` | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_comm_widget.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
#define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
#define DSPCS_REG 0x178d00
struct dspcs {
/*
* DSPCSx
* DSP Core Shim
*
* These registers are added by Intel outside of the Tensilica Core for general operation
* control, such as reset, stall, power gati... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_boot.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 455 |
```objective-c
/*
*/
#include <stdint.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util_macro.h>
#include <adsp_shim.h>
#ifndef ZEPHYR_SOC_INTEL_ADSP_POWER_H_
#define ZEPHYR_SOC_INTEL_ADSP_POWER_H_
/* Value used as delay when waiting for hw register state change. */
#define HW_STATE_CHECK_DELAY 64
/* Powe... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_power.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 818 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_WATCHDOG_H_
#define ZEPHYR_SOC_INTEL_ADSP_WATCHDOG_H_
/**
* @brief Pause watchdog operation
*
* Sets the pause signal to stop the watchdog timing
*
* @param dev Pointer to the device structure
* @param ch... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_watchdog.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 180 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
#include <stdint.h>
/* Low priority interrupt indices */
#define ACE_INTL_HIPC 0
#define ACE_INTL_SBIPC 1
#define ACE_INTL_ML 2
#define ACE_INTL_IDCA 3
#define ACE_INTL_LPVML 4
#define ACE_INTL_SHA ... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_interrupt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 918 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H
#define ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H
#include <intel_adsp_ipc.h>
#include <intel_adsp_ipc_devtree.h>
/**
* @file
*
* Inter Processor Communication - used for sending interrupts to and receiving
* them from another device. ACE uses it to talk ... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_ipc_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 612 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
#define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
#define DSPCS_REG 0x178d00
struct dspcs {
/*
* DSPCSx
* DSP Core Shim
*
* These registers are added by Intel outside of the Tensilica Core for general operation
* control, such as reset, stall, power gati... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_boot.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 481 |
```objective-c
/*
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE3X_H__
/* DMIC Link Synchronization */
#define DMICSYNC_OFFSET 0x1C
/* Sync Period */
#define DMICSYNC_SYNCPRD GENMASK(19, 0)
/* Sync Period Update */
#define DMICSYNC_SYNCPU BIT(20)
/* Sync Go */
#define... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace30_ptl/dmic_regs_ace3x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 423 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
/**
* DfPMCCH
* Power Management / Clock Control (HST) Registers
*
* These registers block (HST domain) are for general power management
* and clock control oper... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace15_mtpm/adsp_shim.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,814 |
```objective-c
/*
*/
#include <stdint.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util_macro.h>
#include <adsp_shim.h>
#ifndef ZEPHYR_SOC_INTEL_ADSP_POWER_H_
#define ZEPHYR_SOC_INTEL_ADSP_POWER_H_
/* Value used as delay when waiting for hw register state change. */
#define HW_STATE_CHECK_DELAY 64
/* Powe... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_power.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 851 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
/* Low priority interrupt indices */
#define ACE_INTL_HIPC 0
#define ACE_INTL_SBIPC 1
#define ACE_INTL_ML 2
#define ACE_INTL_IDCA 3
#define ACE_INTL_LPVML 4
#define ACE_INTL_SHA 5
#define ACE_INTL_L... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_interrupt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 913 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H
#define ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H
#include <intel_adsp_ipc.h>
#include <intel_adsp_ipc_devtree.h>
/**
* @file
*
* Inter Processor Communication - used for sending interrupts to and receiving
* them from another device. ACE uses it to talk ... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_ipc_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 612 |
```objective-c
/*
*
* Author: Adrian Warecki <adrian.warecki@intel.com>
*/
#ifndef __INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__
#define __INTEL_DAI_DRIVER_DMIC_REGS_ACE2X_H__
/* DMIC Link Synchronization */
#define DMICSYNC_OFFSET 0x1C
/* Sync Period */
#define DMICSYNC_SYNCPRD GENMASK(19, 0)
/* Sync Period Update */... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace20_lnl/dmic_regs_ace2x.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 440 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
#define ZEPHYR_SOC_INTEL_ADSP_BOOT_H_
#define DSPCS_REG 0x178d00
struct dspcs {
/*
* DSPCSx
* DSP Core Shim
*
* These registers are added by Intel outside of the Tensilica Core for general operation
* control, such as reset, stall, power gati... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_boot.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 481 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
/**
* DfPMCCH
* Power Management / Clock Control (HST) Registers
*
* These registers block (HST domain) are for general power management
* and clock control opera... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace30_ptl/adsp_shim.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,662 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_POWER_H_
#define ZEPHYR_SOC_INTEL_ADSP_POWER_H_
#include <stdint.h>
#include <zephyr/toolchain.h>
#include <zephyr/sys/util_macro.h>
/* Value used as delay when waiting for hw register state change. */
#define HW_STATE_CHECK_DELAY 64
struct ace_pwrctl {
uint16_... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_power.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 736 |
```objective-c
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H
#define ZEPHYR_SOC_INTEL_ADSP_ACE_IPC_REGS_H
#include <intel_adsp_ipc.h>
#include <intel_adsp_ipc_devtree.h>
/**
* @file
*
* Inter Processor Communication - used for sending interrupts to and receiving
* them from another device. ACE uses it to talk ... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_ipc_regs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 612 |
```objective-c
/*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
#define ZEPHYR_SOC_INTEL_ADSP_INTERRUPT_H_
/* Low priority interrupt indices */
#define ACE_INTL_HIPC 0
#define ACE_INTL_SBIPC 1
#define ACE_INTL_ML 2
#define ACE_INTL_IDCA 3
#define ACE_INTL_LPVML 4
#define ACE_INTL_SHA 5
#define ACE_INTL_L... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_interrupt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 913 |
```unknown
#
config SOC_FAMILY_INTEL_NIOSV
bool
config SOC_FAMILY
default "intel_niosv" if SOC_FAMILY_INTEL_NIOSV
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/intel/intel_niosv/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```yaml
family:
- name: intel_niosv
series:
- name: niosv
socs:
- name: niosv_g
- name: niosv_m
``` | /content/code_sandbox/soc/intel/intel_niosv/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
#
if SOC_FAMILY_INTEL_NIOSV
rsource "*/Kconfig.defconfig.series"
endif
``` | /content/code_sandbox/soc/intel/intel_niosv/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
#
if SOC_FAMILY_INTEL_NIOSV
rsource "*/Kconfig"
endif # SOC_FAMILY_INTEL_NIOSV
``` | /content/code_sandbox/soc/intel/intel_niosv/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
#
config SOC_SERIES_NIOSV
bool
select SOC_FAMILY_INTEL_NIOSV
help
Intel FPGA NIOSV
config SOC_SERIES
default "niosv" if SOC_SERIES_NIOSV
config SOC_NIOSV_M
bool
select SOC_SERIES_NIOSV
help
Intel FPGA NIOSV Microcontroller Core Processor
config SOC_NIOSV_G
bool
select SOC_SERIES_NIOSV
hel... | /content/code_sandbox/soc/intel/intel_niosv/niosv/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
#
if SOC_SERIES_NIOSV
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS # Platform interrupts IRQs index start from index 16
default 32
config RISCV_GP
default y
config RISCV_SOC_INTERRUPT_INIT
default y
endif # SOC_SERIES_NIOSV
``` | /content/code_sandbox/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```unknown
#
config SOC_SERIES_NIOSV
select RISCV
select RISCV_PRIVILEGED
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
config SOC_NIOSV_M
help
Intel FPGA NIOSV Microcontroller Core Proces... | /content/code_sandbox/soc/intel/intel_niosv/niosv/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 127 |
```linker script
/*
*
*/
#include <zephyr/linker/linker-tool.h>
#include <zephyr/arch/riscv/common/linker.ld>
``` | /content/code_sandbox/soc/intel/intel_niosv/niosv/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#define ZEPHYR_SOC_INTEL_ADSP_SHIM_H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
/**
* DfPMCCH
* Power Management / Clock Control (HST) Registers
*
* These registers block (HST domain) are for general power management
* and clock control oper... | /content/code_sandbox/soc/intel/intel_adsp/ace/include/ace20_lnl/adsp_shim.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,740 |
```yaml
vendor: intel
comment: "Intel Raptor Lake SoC"
socs:
- name: raptor_lake
``` | /content/code_sandbox/soc/intel/raptor_lake/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
config SOC_RAPTOR_LAKE
bool
config SOC
default "raptor_lake" if SOC_RAPTOR_LAKE
``` | /content/code_sandbox/soc/intel/raptor_lake/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```objective-c
/*
*/
/**
* @file
* @brief Board configuration macros for the Raptor Lake SoC
*
* This header file is used to specify and describe soc-level aspects for
* the 'Raptor Lake' SoC.
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <zephyr/device.h>
#i... | /content/code_sandbox/soc/intel/raptor_lake/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 218 |
```objective-c
/*
*
*/
/**
* @file
* @brief GPIO macros for the Raptor Lake SoC
*
* This header file is used to specify the GPIO macros for
* the Raptor Lake SoC.
*/
#ifndef __SOC_GPIO_H_
#define __SOC_GPIO_H_
#if defined(CONFIG_BOARD_INTEL_RPL_S_CRB)
#define GPIO_INTEL_NR_SUBDEVS 13
#define REG_PAD_OWNER_B... | /content/code_sandbox/soc/intel/raptor_lake/soc_gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 459 |
```unknown
# Raptor Lake SoC configuration options
if SOC_RAPTOR_LAKE
config PCIE_MMIO_CFG
default y
config X86_DYNAMIC_IRQ_STUBS
default 16
depends on DYNAMIC_INTERRUPTS
endif # SOC_RAPTOR_LAKE
``` | /content/code_sandbox/soc/intel/raptor_lake/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
config SOC_RAPTOR_LAKE
select X86
select X86_64
select CPU_ATOM
select PCIE
select PCIE_MSI
select DYNAMIC_INTERRUPTS
select X86_MMU
``` | /content/code_sandbox/soc/intel/raptor_lake/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```linker script
/*
*/
#include <zephyr/arch/x86/memory.ld>
#ifdef CONFIG_X86_64
#include <zephyr/arch/x86/intel64/linker.ld>
#else
#include <zephyr/arch/x86/ia32/linker.ld>
#endif /* CONFIG_X86_64 */
``` | /content/code_sandbox/soc/intel/raptor_lake/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```yaml
socs:
- name: efinix_sapphire
``` | /content/code_sandbox/soc/efinix/sapphire/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
config SOC_EFINIX_SAPPHIRE
bool
help
Efinix Sapphire VexRiscv system implementation
config SOC
default "efinix_sapphire" if SOC_EFINIX_SAPPHIRE
``` | /content/code_sandbox/soc/efinix/sapphire/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config SOC_EFINIX_SAPPHIRE
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
``` | /content/code_sandbox/soc/efinix/sapphire/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```unknown
if SOC_EFINIX_SAPPHIRE
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
config RISCV_SOC_INTERRUPT_INIT
bool
default y
config NUM_IRQS
int
default 36
config 2ND_LVL_INTR_00_OFFSET
default 11
endif # SOC_EFINIX_SAPPHIRE
``` | /content/code_sandbox/soc/efinix/sapphire/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```yaml
series:
- name: dc233c
socs:
- name: dc233c
``` | /content/code_sandbox/soc/cdns/dc233c/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
#
config SOC_XTENSA_DC233C
bool
config SOC
default "dc233c" if SOC_XTENSA_DC233C
config SOC_TOOLCHAIN_NAME
string
default "dc233c" if SOC_XTENSA_DC233C
``` | /content/code_sandbox/soc/cdns/dc233c/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
#
if SOC_XTENSA_DC233C
config SOC_XTENSA_DC233C
select XTENSA_GEN_HANDLERS
config XTENSA_MMU_NUM_L2_TABLES
int
default 48 if XTENSA_MMU
# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB.
# This is to allow VECBASE to be mapped permanently
# via TLB way 4 (which covers 1MB).
config SRAM_OFFSET
he... | /content/code_sandbox/soc/cdns/dc233c/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 143 |
```unknown
#
config SOC_XTENSA_DC233C
select XTENSA
select XTENSA_HAL
select ARCH_HAS_THREAD_LOCAL_STORAGE
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CPU_HAS_MMU
select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU
select ARCH_HAS_USERSPACE if XTENSA_MMU
select XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP i... | /content/code_sandbox/soc/cdns/dc233c/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```c
/*
*
*/
#include <stdint.h>
#include <xtensa/config/core-isa.h>
#include <zephyr/devicetree.h>
#include <zephyr/arch/xtensa/xtensa_mmu.h>
#include <zephyr/sys/util.h>
const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
{
.start = (uint32_t)XCHAL_VECBASE_RESET_VADDR,
.end = (uint32_t)CONFIG_SRAM_... | /content/code_sandbox/soc/cdns/dc233c/mmu.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```objective-c
*/
#ifndef ZEPHYR_SOC_XTENSA_DC233C_BACKTRACE_HELPERS_H_
#define ZEPHYR_SOC_XTENSA_DC233C_BACKTRACE_HELPERS_H_
#include <zephyr/linker/linker-defs.h>
#include <xtensa/config/core-isa.h>
static inline bool xtensa_dc233c_ptr_executable(const void *p)
{
bool in_text = ((p >= (void *)__text_region_sta... | /content/code_sandbox/soc/cdns/dc233c/include/backtrace_helpers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```unknown
config SOC_XTENSA_SAMPLE_CONTROLLER
bool
config SOC
default "xtensa_sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER
config SOC_TOOLCHAIN_NAME
string
default "sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER
``` | /content/code_sandbox/soc/cdns/xtensa_sample_controller/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```yaml
series:
- name: xtensa_sample_controller
socs:
- name: xtensa_sample_controller
``` | /content/code_sandbox/soc/cdns/xtensa_sample_controller/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
config SOC_XTENSA_SAMPLE_CONTROLLER
select XTENSA
select XTENSA_HAL
select ARCH_SUPPORTS_COREDUMP
``` | /content/code_sandbox/soc/cdns/xtensa_sample_controller/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Xtensa platform.
*/
#include <xtensa/config/core-isa.h>
#include <zephyr/linker/sections.h>
#include <zephyr/devicetree.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#define ... | /content/code_sandbox/soc/cdns/dc233c/include/xtensa-dc233c.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,029 |
```objective-c
/*
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
*
* Functions here are designed to produce efficient code to
* search an Xtensa bitmask of interrupts, inspecting only those bits
* declared to be associated with a given interrupt level. Each
* dispatcher will handle exactly one flagged in... | /content/code_sandbox/soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,243 |
```unknown
config SOC_OPENISA_RV32M1
bool
help
Enable support for OpenISA RV32M1 RISC-V processors. Choose
this option to target the RI5CY or ZERO-RISCY core. This
option should not be used to target either Arm core.
config SOC_OPENISA_RV32M1_RI5CY
bool
select SOC_OPENISA_RV32M1
help
OpenISA RV32M1 R... | /content/code_sandbox/soc/openisa/rv32m1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```unknown
/*
*
*/
#include <zephyr/toolchain.h>
/* Imports */
GTEXT(__initialize)
GTEXT(_isr_wrapper)
/* Exports */
GTEXT(__start)
/*
* Interrupts work the same way for both the RI5CY and ZERO-RISCY cores
* in this SoC; the only difference is the location of the vectors section
* on flash. We thus reuse this ... | /content/code_sandbox/soc/openisa/rv32m1/vector.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 703 |
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