text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```linker script
/*
*
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
SECTION_PROLOGUE(.id_code,,)
{
KEEP(*(.id_code*))
} GROUP_LINK_IN(ID_CODE)
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
SECTION_PROLOGUE(.option_setting_ofs,,)
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option... | /content/code_sandbox/soc/renesas/ra/ra2a1/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,051 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the Renesas RA2A1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
if SOC_SERIES_RA2A1
config NUM_IRQS
default 32
config PINCTRL
default y
endif # SOC_SERIES_RA2A1
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```linker script
/*
*
*/
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
*(.fsp_dtc_vector_table)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/ram_sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```linker script
/*
*
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/data_sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
config SOC_SERIES_RA2A1
select ARM
select CPU_CORTEX_M23
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_VTOR
select CPU_CORTEX_M_HAS_SYSTICK
select HAS_SWO
select XIP
select HAS_RENESAS_RA_FSP
``` | /content/code_sandbox/soc/renesas/ra/ra2a1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```yaml
family:
- name: renesas_smartbond
series:
- name: da1469x
socs:
- name: da14695
- name: da14699
``` | /content/code_sandbox/soc/renesas/smartbond/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```unknown
if SOC_FAMILY_RENESAS_SMARTBOND
rsource "*/Kconfig.defconfig"
config PINCTRL
default y
endif # SOC_FAMILY_RENESAS_SMARTBOND
``` | /content/code_sandbox/soc/renesas/smartbond/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
if SOC_FAMILY_RENESAS_SMARTBOND
rsource "*/Kconfig"
endif # SOC_FAMILY_RENESAS_SMARTBOND
``` | /content/code_sandbox/soc/renesas/smartbond/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config SOC_FAMILY_RENESAS_SMARTBOND
bool
config SOC_FAMILY
default "renesas_smartbond" if SOC_FAMILY_RENESAS_SMARTBOND
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/renesas/smartbond/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
config SOC_SERIES_DA1469X
bool
select SOC_FAMILY_RENESAS_SMARTBOND
help
Renesas SmartBond(tm) DA1469x series MCU
config SOC_DA14695
bool
select SOC_SERIES_DA1469X
help
DA14695
config SOC_DA14699
bool
select SOC_SERIES_DA1469X
help
DA14699
config SOC_SERIES
default "da1469x" if SOC_SERI... | /content/code_sandbox/soc/renesas/smartbond/da1469x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_SMARTBOND_DA1469X_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_SMARTBOND_DA1469X_PINCTRL_SOC_H_
#include <zephyr/dt-bindings/pinctrl/smartbond-pinctrl.h>
struct smartbond_pinctrl_soc_pin {
uint32_t func : 6;
uint32_t port : 1;
uint32_t pin : 5;
uint32_t bi... | /content/code_sandbox/soc/renesas/smartbond/da1469x/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 482 |
```objective-c
/*
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifdef __cplusplus
extern "C" {
#endif
#include <DA1469xAB.h>
#ifdef __cplusplus
}
#endif
#endif /* _SOC__H_ */
``` | /content/code_sandbox/soc/renesas/smartbond/da1469x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
if SOC_SERIES_DA1469X
config SMARTBOND_TIMER
default y if PM && !$(dt_nodelabel_enabled,timer2)
config CORTEX_M_SYSTICK
default n if SMARTBOND_TIMER
config NUM_IRQS
default 40
DT_LPCLK_PATH := $(dt_nodelabel_path,lp_clk)
DT_CLOCK_SRC_PATH := $(dt_node_ph_prop_path,$(DT_LPCLK_PATH),clock-src)
config ... | /content/code_sandbox/soc/renesas/smartbond/da1469x/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/logging/log.h>
#include <string.h>
#include <DA1469xAB.h>
#include <da1469x_clock.h>
#include <da1469x_otp.h>
#include <da1469x_pd.h>
#include <da1469x_pdc.h>
#include <da1469x_trimv.h>
#include <da1469x_sleep.h>
LOG_MODUL... | /content/code_sandbox/soc/renesas/smartbond/da1469x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,576 |
```linker script
/*
*
*/
SECTION_PROLOGUE(.da1469x_intvect_reserved,(NOLOAD),)
{
/* Access to addresses in range 0x0-0x1ff is remapped to sram to allow rw
* access to interrupt vector which is located at 0x0 where flash is remapped.
* This means first 512 bytes of sram has to be reserved so remapped ac... | /content/code_sandbox/soc/renesas/smartbond/da1469x/intvect_reserved.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```unknown
config SOC_SERIES_DA1469X
select ARM
select CPU_CORTEX_M33
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_SYSTICK
select ARMV8_M_DSP
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select HAS_PM
select CLOCK_CONTROL
select CLOCK_CONTROL_SMARTBOND
select PLATFORM_SPECIFIC_INIT
se... | /content/code_sandbox/soc/renesas/smartbond/da1469x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
config SOC_RENESAS_RZT2M
bool
config SOC_PART_NUMBER_R9A07G075
bool
config SOC
default "renesas_rzt2m" if SOC_RENESAS_RZT2M
config SOC_PART_NUMBER
default "R9A07G075" if SOC_PART_NUMBER_R9A07G075
``` | /content/code_sandbox/soc/renesas/rzt2m/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```yaml
socs:
- name: renesas_rzt2m
``` | /content/code_sandbox/soc/renesas/rzt2m/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/pm/pm.h>
#include <zephyr/logging/log.h>
#include <DA1469xAB.h>
#include <da1469x_clock.h>
#include <da1469x_sleep.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
void pm_state_set(enum pm_state state, uint8_t substate_id)
{
ARG_UNUSED(substate_id);
switc... | /content/code_sandbox/soc/renesas/smartbond/da1469x/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 338 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RZT2M_PINCTRL_H_
#define ZEPHYR_SOC_ARM_RENESAS_RZT2M_PINCTRL_H_
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct pinctrl_soc_pin_t {
uint32_t port;
uint32_t pin;
uint32_t func;
uint32_t input_enable: 1;
uint32_t output_enab... | /content/code_sandbox/soc/renesas/rzt2m/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 536 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <stdint.h>
#include <zephyr/drivers/syscon.h>
#include "soc.h"
#include <zephyr/sys/util_macro.h>
static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
static ... | /content/code_sandbox/soc/renesas/rzt2m/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 848 |
```unknown
if SOC_RENESAS_RZT2M
config NUM_IRQS
default 994
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 20000000
config FPU
default y
config FLASH_SIZE
default 0
config FLASH_BASE_ADDRESS
default 0
endif # SOC_RENESAS_RZT2M
``` | /content/code_sandbox/soc/renesas/rzt2m/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
config SOC_RENESAS_RZT2M
select ARM
select CPU_CORTEX_R52
select CPU_HAS_ARM_MPU
select GIC_SINGLE_SECURITY_STATE
select ARM_ARCH_TIMER
select SYSCON
``` | /content/code_sandbox/soc/renesas/rzt2m/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```linker script
/*
*
*/
#include <zephyr/arch/arm/cortex_r/scripts/linker.ld>
``` | /content/code_sandbox/soc/renesas/rzt2m/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
# Renesas R-Car SoC line
config SOC_FAMILY_RENESAS_RCAR
bool
config SOC_FAMILY
default "renesas_rcar" if SOC_FAMILY_RENESAS_RCAR
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/renesas/rcar/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```objective-c
/*
*
*/
#ifndef _SOC__H_
#define _SOC__H_
/* Do not let CMSIS to handle GIC and Timer */
#include <stdint.h>
#define __GIC_PRESENT 0
#define __TIM_PRESENT 0
/* Global system counter */
#define CNTCR_EN BIT(0)
#define CNTCR_HDBG BIT(1)
/* Safety area protect register */
#define PRCRS_CLK BIT... | /content/code_sandbox/soc/renesas/rzt2m/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 574 |
```yaml
family:
- name: renesas_rcar
series:
- name: rcar_gen3
socs:
- name: r8a77951
cpuclusters:
- name: r7
- name: a57
- name: r8a77961
- name: rcar_gen4
socs:
- name: r8a779f0
cpuclusters:
... | /content/code_sandbox/soc/renesas/rcar/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```unknown
if SOC_FAMILY_RENESAS_RCAR
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_RENESAS_RCAR
``` | /content/code_sandbox/soc/renesas/rcar/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
# Renesas R-Car SoC line
if SOC_FAMILY_RENESAS_RCAR
rsource "*/Kconfig"
endif # SOC_FAMILY_RENESAS_RCAR
``` | /content/code_sandbox/soc/renesas/rcar/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
config SOC_SERIES_RCAR_GEN3
bool
select SOC_FAMILY_RENESAS_RCAR
config SOC_R8A77951_R7
bool
select SOC_SERIES_RCAR_GEN3
help
R8A77951 R7
config SOC_R8A77951_A57
bool
select SOC_SERIES_RCAR_GEN3
help
R8A77951 A57
config SOC_R8A77961
bool
select SOC_SERIES_RCAR_GEN3
help
R8A77961
confi... | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 181 |
```unknown
# Renesas R-Car Gen3 SoC line
if SOC_SERIES_RCAR_GEN3
config NUM_IRQS
default 512
config PINCTRL
default y
endif # SOC_SERIES_RCAR_GEN3
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```c
/*
*
*/
#include <zephyr/arch/arm64/arm_mmu.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
MT_DEVI... | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 212 |
```unknown
config SOC_SERIES_RCAR_GEN3
select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
config SOC_R8A77951_R7
select ARM
select CPU_CORTEX_R7
select PLATFORM_SPECIFIC_INIT
select CPU_HAS_DCLS
config SOC_R8A77951_A57
select ARM64
select CPU_CORTEX_A57
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
config SOC_... | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```c
/*
*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/sys/barrier.h>
void z_arm_platform_init(void)
{
L1C_DisableCaches();
L1C_DisableBTAC();
/* Invalidate instruction cache and flush branch target cache */
__set_ICIALLU(0);
barrier_dsync_fence_full();
barrier_isync_fence_ful... | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/r7/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```objective-c
/*
*
*
*/
#ifndef _SOC__H_
#define _SOC__H_
/* Define CMSIS configurations */
#define __CR_REV 1U
/* Do not let CMSIS to handle GIC and Timer */
#define __GIC_PRESENT 0
#define __TIM_PRESENT 0
#endif /* _SOC__H_ */
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/r7/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_
#include <zephyr/drivers/pinctrl/pinctrl_rcar_common.h>
#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_
#include <zephyr/drivers/pinctrl/pinctrl_rcar_common.h>
#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN3_PINCTRL_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
config SOC_SERIES_RCAR_GEN4
bool
select SOC_FAMILY_RENESAS_RCAR
config SOC_R8A779F0_R52
bool
select SOC_SERIES_RCAR_GEN4
help
r8a779f0 r52
config SOC_R8A779F0_A55
bool
select SOC_SERIES_RCAR_GEN4
help
r8a779f0 a55
config SOC_SERIES
default "rcar_gen4" if SOC_SERIES_RCAR_GEN4
config SOC
d... | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```unknown
if SOC_SERIES_RCAR_GEN4
config NUM_IRQS
default 1216 #960 SPI + 256 LPI
config PINCTRL
default y
endif # SOC_SERIES_RCAR_GEN4
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
# Renesas R-Car Gen4 SoC line
if SOC_SERIES_RCAR_GEN4
rsource "Kconfig.defconfig.r8a779*"
endif # SOC_SERIES_RCAR_GEN4
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
config SOC_R8A779F0_R52
select ARM
select CPU_CORTEX_R52
select GIC_SINGLE_SECURITY_STATE
select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
select ARM_ARCH_TIMER
config SOC_R8A779F0_A55
select ARM64
select CPU_CORTEX_A55
select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
select ARM_ARCH_TIMER
... | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```objective-c
/*
*
*
*/
#ifndef _SOC__H_
#define _SOC__H_
/* Define CMSIS configurations */
#define __CR_REV 1U
/* Do not let CMSIS to handle GIC and Timer */
#define __GIC_PRESENT 0
#define __TIM_PRESENT 0
#endif /* _SOC__H_ */
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/r52/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
#include <zephyr/drivers/pinctrl/pinctrl_rcar_common.h>
#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/r52/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```objective-c
/*
*
*
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
#include <zephyr/drivers/pinctrl/pinctrl_rcar_common.h>
#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */
``` | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/a55/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```c
/*
*
*/
#include <zephyr/arch/arm64/arm_mmu.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
MT_DEVI... | /content/code_sandbox/soc/renesas/rcar/rcar_gen4/a55/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 212 |
```yaml
family:
- name: telink_tlsr
series:
- name: tlsr951x
socs:
- name: tlsr9518
``` | /content/code_sandbox/soc/telink/tlsr/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
if SOC_FAMILY_TELINK_TLSR
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_TELINK_TLSR
``` | /content/code_sandbox/soc/telink/tlsr/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
if SOC_FAMILY_TELINK_TLSR
rsource "*/Kconfig"
endif # SOC_FAMILY_TELINK_TLSR
``` | /content/code_sandbox/soc/telink/tlsr/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
config SOC_FAMILY_TELINK_TLSR
bool
config SOC_FAMILY
default "telink_tlsr" if SOC_FAMILY_TELINK_TLSR
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/telink/tlsr/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
config SOC_SERIES_TLSR951X
bool
select SOC_FAMILY_TELINK_TLSR
help
Telink TLSR951X
config SOC_TLSR9518
bool
select SOC_SERIES_TLSR951X
help
Telink TLSR9518
config SOC_SERIES
default "tlsr951x" if SOC_SERIES_TLSR951X
config SOC
default "tlsr9518" if SOC_TLSR9518
``` | /content/code_sandbox/soc/telink/tlsr/tlsr951x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```linker script
/*
*
*/
KEEP(*(.init.*))
``` | /content/code_sandbox/soc/telink/tlsr/tlsr951x/init.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10 |
```objective-c
/*
*
*/
#ifndef SOC_RISCV_TELINK_B91_SOC_OFFSETS_H
#define SOC_RISCV_TELINK_B91_SOC_OFFSETS_H
#ifdef CONFIG_RISCV_SOC_OFFSETS
/* Telink B91 specific registers. */
#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp)
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, mxstatus... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/soc_offsets.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 205 |
```unknown
/*
*
*/
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <soc.h>
#define NDS_MXSTATUS 0x7C4
/* Exports */
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
#endif
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
SECTION_FUNC(exception.ot... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/soc_irq.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 308 |
```unknown
/*
*
*/
#define NDS_MCACHE_CTL 0x7CA
#define NDS_MMISC_CTL 0x7D0
#include <zephyr/toolchain.h>
.option push
.option norelax
.org 0x0
/* exports */
GTEXT(entry)
SECTION_FUNC(init, init)
entry:
j start
.org 0x20
.word ('T'<<24 | 'L'<<16 | 'N'<<8 | 'K')
.org 0x26
.... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/start.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 580 |
```objective-c
/*
*
*/
#ifndef SOC_RISCV_TELINK_B91_SOC_CONTEXT_H
#define SOC_RISCV_TELINK_B91_SOC_CONTEXT_H
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Telink B91 specific registers. */
#if defined(CONFIG_TELINK_B91_PFT_ARCH) && defined(__riscv_dsp)
#define SOC_ESF_MEMBERS \
uint32_t mxstatus; \
uint32_t ucode \
... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/soc_context.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 307 |
```objective-c
/*
*
*/
#ifndef SOC_RISCV_TELINK_B91_PINCTRL_SOC_H
#define SOC_RISCV_TELINK_B91_PINCTRL_SOC_H
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
/**
* @brief Telink B91 pin type.
*/
typedef uint32_t pinctrl_soc_pin_t;
/**
* @brief Utility macro... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 333 |
```objective-c
/*
*
*/
#ifndef RISCV_TELINK_B91_SOC_H
#define RISCV_TELINK_B91_SOC_H
#endif /* RISCV_TELINK_B91_SOC_H */
``` | /content/code_sandbox/soc/telink/tlsr/tlsr951x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
if SOC_SERIES_TLSR951X
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 32000
config RISCV_SOC_INTERRUPT_INIT
bool
default y
config RISCV_GP
bool
default y
config NUM_IRQS
int
default 64
config PINCTRL
default y
config XIP
bool
default n
config MAIN_STACK_SIZE
int
default 2048
config IDLE... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
config SOC_SERIES_TLSR951X
bool
select RISCV
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select HAS_TELINK_DRIVERS
select ATOMIC_OPERATIONS_BUILT... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 193 |
```c
/*
*
*/
#include "sys.h"
#include "clock.h"
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
/* Software reset defines */
#define reg_reset REG_ADDR8(0x1401ef)
#define SOFT_RESET 0x20u
/* List of supported CCLK frequencies */
#define CLK_16MHZ 160000... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,057 |
```unknown
config SOC_LITEX_VEXRISCV
bool
help
LiteX VexRiscv system implementation
config SOC
default "litex_vexriscv" if SOC_LITEX_VEXRISCV
``` | /content/code_sandbox/soc/litex/litex_vexriscv/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```c
/*
*
*/
#define DT_DRV_COMPAT litex_soc_controller
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/reboot.h>
#include <soc.h>
#define LITEX_CTRL_RESET DT_INST_REG_ADDR_BY_NAME(0, reset)
void sys_arch_reboot(int type)
{
ARG_UNUSED(type);
/* SoC Reset on BIT(0)*/
litex_write8(B... | /content/code_sandbox/soc/litex/litex_vexriscv/reboot.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```yaml
socs:
- name: litex_vexriscv
``` | /content/code_sandbox/soc/litex/litex_vexriscv/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```linker script
/*
*
*/
/**
* @brief Linker script for the Telink B91 SoC
*/
#include <zephyr/devicetree.h>
#include <zephyr/linker/linker-tool.h>
MEMORY
{
RAM_ILM (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_ilm))
}
#include <zephyr/arch/riscv/common/linker.ld>
... | /content/code_sandbox/soc/telink/tlsr/tlsr951x/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 393 |
```unknown
if SOC_LITEX_VEXRISCV
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config NUM_IRQS
default 12
config REBOOT
depends on DT_HAS_LITEX_SOC_CONTROLLER_ENABLED
default y
endif # SOC_LITEX_VEXRISCV
``` | /content/code_sandbox/soc/litex/litex_vexriscv/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```unknown
config SOC_LITEX_VEXRISCV
select RISCV
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
if SOC_LITEX_VEXRISCV
config LITEX_CSR_DATA_WIDTH
int "Select Control/Status register width"
default... | /content/code_sandbox/soc/litex/litex_vexriscv/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```unknown
config SOC_FAMILY_ITE_EC
bool
config SOC_FAMILY
default "ite_ec" if SOC_FAMILY_ITE_EC
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/ite/ec/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
family:
- name: ite_ec
series:
- name: it8xxxx
socs:
- name: it81202bx
- name: it81202cx
- name: it81202dx
- name: it81302bx
- name: it81302cx
- name: it81302dx
- name: it82002aw
- name: it82002bw
- nam... | /content/code_sandbox/soc/ite/ec/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```unknown
if SOC_FAMILY_ITE_EC
rsource "*/Kconfig.defconfig.series"
endif # SOC_FAMILY_ITE_EC
``` | /content/code_sandbox/soc/ite/ec/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
if SOC_FAMILY_ITE_EC
rsource "*/Kconfig"
endif # SOC_FAMILY_ITE_EC
``` | /content/code_sandbox/soc/ite/ec/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```objective-c
/*
*
*/
#ifndef __RISCV32_LITEX_VEXRISCV_SOC_H_
#define __RISCV32_LITEX_VEXRISCV_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/arch/riscv/sys_io.h>
#ifndef _ASMLANGUAGE
/* CSR access helpers */
static inline unsigned char litex_read8(unsigned long addr)
{
#if CONFIG_LITEX_CSR_DATA_WIDTH >=... | /content/code_sandbox/soc/litex/litex_vexriscv/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,275 |
```objective-c
/*
*
*/
/**
* @file configuration macros for riscv SOCs supporting the riscv
* privileged architecture specification
*/
#ifndef __SOC_COMMON_H_
#define __SOC_COMMON_H_
#include "chip_chipregs.h"
#ifndef _ASMLANGUAGE
#ifdef CONFIG_HAS_ITE_INTC
/*
* Save current interrupt state of soc-leve... | /content/code_sandbox/soc/ite/ec/common/soc_common.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 335 |
```unknown
/*
* Jyunlin Chen <jyunlin.chen@ite.com.tw>
*
*/
#include "chip_chipregs.h"
#include <zephyr/toolchain.h>
/* exports */
GTEXT(__start)
/* imports */
GTEXT(__initialize)
GTEXT(_isr_wrapper)
SECTION_FUNC(vectors, __start)
#ifdef CONFIG_RISCV_GP
.option push
.option norelax
/* Configure the GP registe... | /content/code_sandbox/soc/ite/ec/common/vector.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 985 |
```objective-c
/*
*
*/
#ifndef _ITE_IT8XXX2_SOC_DT_H_
#define _ITE_IT8XXX2_SOC_DT_H_
/*
* For it8xxx2 wake-up controller (WUC)
*/
#define IT8XXX2_DEV_WUC(idx, inst) \
DEVICE_DT_GET(DT_PHANDLE(IT8XXX2_DT_INST_WUCCTRL(inst, idx), wucs))
#define IT8XXX2_DEV_WUC_MASK(idx, inst) \
DT_PHA(IT8XXX2_DT_INST_WUCC... | /content/code_sandbox/soc/ite/ec/common/soc_dt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 767 |
```unknown
/*
*
*/
/*
* common interrupt management code for riscv SOCs supporting the riscv
* privileged architecture specification
*/
#include <zephyr/kernel_structs.h>
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <soc.h>
/* exports */
GTEXT(__soc_handl... | /content/code_sandbox/soc/ite/ec/common/soc_irq.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 143 |
```c
/*
*
*/
/**
* @file
* @brief interrupt management code for riscv SOCs supporting the riscv
privileged architecture specification
*/
#include <zephyr/irq.h>
#include <soc_common.h>
void arch_irq_enable(unsigned int irq)
{
if (IS_ENABLED(CONFIG_HAS_ITE_INTC)) {
ite_intc_irq_enable(irq);
}
}
void arch... | /content/code_sandbox/soc/ite/ec/common/soc_common_irq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 209 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_RISCV_ITE_IT8XXX2_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_RISCV_ITE_IT8XXX2_COMMON_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
#include <zephyr/types.h>
/**
* @brief ITE IT8XXX2 pin type.
*/
struct pinctrl_soc_pi... | /content/code_sandbox/soc/ite/ec/common/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,918 |
```objective-c
/*
*
*/
#ifndef _ITE_IT8XXX2_SOC_ESPI_H_
#define _ITE_IT8XXX2_SOC_ESPI_H_
#include <zephyr/device.h>
#include <zephyr/sys/util.h>
#ifdef __cplusplus
extern "C" {
#endif
#define ESPI_IT8XXX2_SOC_DEV DEVICE_DT_GET(DT_NODELABEL(espi0))
/**
* @brief eSPI input pad gating
*
* @param dev pointer to e... | /content/code_sandbox/soc/ite/ec/common/soc_espi.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 198 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <soc.h>
/* SMFI register structure check */
IT8XXX2_REG_SIZE_CHECK(smfi_it8xxx2_regs, 0xd1);
IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDAR0, 0x3b);
IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs, SMFI_ECINDAR1, 0x3c);
IT8XXX2_REG_OFFSET_CHECK(smfi_it8xxx2_regs... | /content/code_sandbox/soc/ite/ec/common/check_regs.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,915 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/policy.h>
#include <soc.h>
__weak const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
{
const struct pm_state_info *cpu_states;
uint8_t num_cpu_states;
num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
for (int16_t i =... | /content/code_sandbox/soc/ite/ec/common/policy.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 247 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
/* Handle when enter deep doze mode. */
static void ite_power_soc_deep_doze(void)
{
/* Enter deep doze mode */
riscv_idle(CHIP_PLL_DEEP_DOZE, MSTATUS_IEN);
}
/* Invoke Low Power/System Off specific Tasks */
void pm_state_set(enum ... | /content/code_sandbox/soc/ite/ec/common/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 190 |
```unknown
config SOC_SERIES_IT8XXX2
bool
select SOC_FAMILY_ITE_EC
help
Enable support for ITE IT8XXX2
config SOC_IT8XXX2
bool
select SOC_SERIES_IT8XXX2
config SOC_IT81302BX
bool
select SOC_IT8XXX2
config SOC_IT81202BX
bool
select SOC_IT8XXX2
config SOC_IT81302CX
bool
select SOC_IT8XXX2
config SOC... | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 434 |
```unknown
if SOC_SERIES_IT8XXX2
config RISCV_GP
default y
config ARCH_HAS_CUSTOM_BUSY_WAIT
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config SYS_CLOCK_TICKS_PER_SEC
default 4096
config UART_NS16550_WA_ISR_REENABLE_INTERRUPT
default y
depends on UART_NS16550
config FLASH_INIT_PRIORITY
defa... | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.series | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 227 |
```unknown
if SOC_IT81202CX
config ILM_MAX_SIZE
default 60
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
if SOC_IT82002AW
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_IT81202BX
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_IT82302AX
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default n
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302ax | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_IT81302CX
config ILM_MAX_SIZE
default 60
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default n
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```c
/*
*
*/
#include <stdbool.h>
#include <stdint.h>
#include <zephyr/device.h>
#include <zephyr/devicetree.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
#include <zephyr/sys/__assert.h>
LOG_MODULE_REGISTER(soc_it8xxx2_ilm, CONFIG_LOG_DEFAULT_LEVEL);
/*
* Instruction Local Memory (ILM) support for I... | /content/code_sandbox/soc/ite/ec/it8xxx2/ilm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,210 |
```unknown
if SOC_IT82202AX
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_IT82002BW
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002bw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_IT81302BX
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default n
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_IT82202BW
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202bw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```c
/*
*
*
*/
#include <zephyr/arch/riscv/csr.h>
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include "ilm.h"
#include <soc_common.h>
#include "soc_espi.h"
#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
/*
* This define gets the total number of USBPD ports availa... | /content/code_sandbox/soc/ite/ec/it8xxx2/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,611 |
```unknown
if SOC_IT81302DX
config ILM_MAX_SIZE
default 60
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default n
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302dx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
if SOC_IT81202DX
config ILM_MAX_SIZE
default 60
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default y
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202dx | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```objective-c
#ifndef __RISCV_ITE_SOC_H_
#define __RISCV_ITE_SOC_H_
/*
*
*
*/
#include <soc_common.h>
#endif /* __RISCV_ITE_SOC_H_ */
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```unknown
if SOC_IT82302BW
config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
default n
endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82302bw | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```objective-c
/*
*
*/
#include <stdbool.h>
/* Places code in the section that gets mapped into ILM */
#define __soc_ram_code __attribute__((section(".__ram_code")))
#ifndef _ASMLANGUAGE
bool it8xxx2_is_ilm_configured(void);
#endif
``` | /content/code_sandbox/soc/ite/ec/it8xxx2/ilm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.