text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```linker script
/*
*
*/
/**
* @brief Linker script for the Nios II/e CPU with timer and 16550 UART
*/
#include <layout.h>
#include <zephyr/devicetree.h>
#define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_fla... | /content/code_sandbox/soc/altr/zephyr_nios2f/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```objective-c
/*
*
*/
#ifndef _NUVOTON_NPCX_REG_DEF_H
#define _NUVOTON_NPCX_REG_DEF_H
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/__assert.h>
#include <zephyr/sys/util_macro.h>
#include <zephyr/toolchain.h>
/*
* NPCX register structure size/offset checking macro function to mitigate
... | /content/code_sandbox/soc/nuvoton/npcx/common/reg/reg_def.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21,764 |
```unknown
#**************************************************************
# Create Clock
#**************************************************************
derive_pll_clocks
# JTAG Signal Constraints constrain the TCK port, assuming a 10MHz JTAG clock and 3ns delays
create_clock -name {altera_reserved_tck} -period 41.6... | /content/code_sandbox/soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 337 |
```unknown
# your_sha256_hash---------- #
#
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation... | /content/code_sandbox/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 233 |
```unknown
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element a_16550_uart_0
{
datum _sortIndex... | /content/code_sandbox/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25,495 |
```unknown
# your_sha256_hash---------- #
#
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation... | /content/code_sandbox/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11,932 |
```verilog
module ghrd_10m50da_top (
//Clock and Reset
input wire clk_50,
//input wire clk_ddr3_100_p,
input wire fpga_reset_n,
//QSPI
output wire qspi_clk,
inout wire[3:0] qspi_io,
output wire qspi_csn,
//ddr3
//output wire [13:0] mem_a,
//output wire [2:0]... | /content/code_sandbox/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v | verilog | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,593 |
```unknown
These files are a Nios II/F CPU design provided by Altera for evaluating
Zephyr on Nios II. This design is intended for the Altera MAX10 10M50 Rec C
development board. You can find more information about this board here:
path_to_url
You will need the Quartus SDK in order to modify this CPU or flash it onto... | /content/code_sandbox/soc/altr/zephyr_nios2f/cpu/README | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 175 |
```objective-c
/*
* system.h - SOPC Builder system and BSP software package information
*
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Tue Dec 05 14:41:17 SGT 2017
*/
/*
* DO NOT MODIFY THIS FILE
*
* Ch... | /content/code_sandbox/soc/altr/zephyr_nios2f/include/system.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 5,254 |
```objective-c
/*
* linker.h - Linker script mapping information
*
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Tue Dec 05 14:42:02 SGT 2017
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will h... | /content/code_sandbox/soc/altr/zephyr_nios2f/include/linker.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 756 |
```objective-c
/*
*
*/
#include <system.h>
#define _RESET_VECTOR ALT_CPU_RESET_ADDR
#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR
``` | /content/code_sandbox/soc/altr/zephyr_nios2f/include/layout.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config SOC_QEMU_NIOS2
bool
config SOC
default "qemu_nios2" if SOC_QEMU_NIOS2
``` | /content/code_sandbox/soc/altr/qemu_nios2/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```yaml
socs:
- name: qemu_nios2
``` | /content/code_sandbox/soc/altr/qemu_nios2/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```objective-c
/*
*
*/
#ifndef __SOC_H_
#define __SOC_H_
#include <system.h>
#endif
``` | /content/code_sandbox/soc/altr/qemu_nios2/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
if SOC_QEMU_NIOS2
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
endif
``` | /content/code_sandbox/soc/altr/qemu_nios2/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
config SOC_QEMU_NIOS2
select NIOS2
select HAS_MUL_INSTRUCTION
select HAS_DIV_INSTRUCTION
select HAS_MULX_INSTRUCTION
``` | /content/code_sandbox/soc/altr/qemu_nios2/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```linker script
/*
*
*/
/**
* @brief Linker script for the Nios II/e CPU with timer and 16550 UART
*/
#include <layout.h>
#include <zephyr/devicetree.h>
#define _RAM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_sram))
#define _RAM_SIZE DT_REG_SIZE(DT_CHOSEN(zephyr_sram))
#define _ROM_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_fla... | /content/code_sandbox/soc/altr/qemu_nios2/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 126 |
```objective-c
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will have subtle consequences
* which will almost certainly lead to a nonfunctioning
* system. If you do modify this file, be aware that your
* changes will be overwritten and lost when this file
* is generated again.
*
* DO NOT MODIFY THIS FIL... | /content/code_sandbox/soc/altr/qemu_nios2/include/system.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,684 |
```objective-c
/*
* linker.h - Linker script mapping information
*
* Machine generated for CPU 'nios2_gen2_0' in SOPC Builder design 'ghrd_10m50da'
* SOPC Builder design path: ../../ghrd_10m50da.sopcinfo
*
* Generated: Tue May 03 11:35:27 MYT 2016
*/
/*
* DO NOT MODIFY THIS FILE
*
* Changing this file will h... | /content/code_sandbox/soc/altr/qemu_nios2/include/linker.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 727 |
```objective-c
/*
*
*/
#include <system.h>
/* To simulate XIP on QEMU, we split RAM into two chunks, with the
* higher-addressed chunk considered "ROM"
*/
#define _RESET_VECTOR _ROM_ADDR
#define _EXC_VECTOR ALT_CPU_EXCEPTION_ADDR
``` | /content/code_sandbox/soc/altr/qemu_nios2/include/layout.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```unknown
config SOC_FAMILY_NXP_S32
bool
config SOC_FAMILY
default "nxp_s32" if SOC_FAMILY_NXP_S32
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/nxp/s32/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```yaml
family:
- name: nxp_s32
series:
- name: s32k1
socs:
- name: s32k116
- name: s32k118
- name: s32k142
- name: s32k142w
- name: s32k144
- name: s32k144w
- name: s32k146
- name: s32k148
- name: s32k3
socs:
- name: s32k344
- name: s32ze
socs:
- name: s32z27... | /content/code_sandbox/soc/nxp/s32/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```unknown
if SOC_FAMILY_NXP_S32
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_NXP_S32
``` | /content/code_sandbox/soc/nxp/s32/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
if SOC_FAMILY_NXP_S32
rsource "*/Kconfig"
endif # SOC_FAMILY_NXP_S32
``` | /content/code_sandbox/soc/nxp/s32/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
# NXP S32ZE MCUs series
config SOC_SERIES_S32ZE
bool
select SOC_FAMILY_NXP_S32
config SOC_SERIES
default "s32ze" if SOC_SERIES_S32ZE
config SOC_S32Z270
bool
select SOC_SERIES_S32ZE
config SOC_S32Z270_RTU0
bool
select SOC_S32Z270
config SOC_S32Z270_RTU1
bool
select SOC_S32Z270
config SOC
defa... | /content/code_sandbox/soc/nxp/s32/s32ze/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```c
/*
*
*/
#include <zephyr/linker/linker-defs.h>
#include <zephyr/arch/arm/mpu/arm_mpu.h>
#define DEVICE_REGION_START 0x40000000UL
#define DEVICE_REGION_END 0x76FFFFFFUL
static const struct arm_mpu_region mpu_regions[] = {
MPU_REGION_ENTRY("vector",
(uintptr_t)_vector_start,
REGION_RAM_TEXT_ATTR((uin... | /content/code_sandbox/soc/nxp/s32/s32ze/mpu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 253 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <cmsis_core.h>
#include <zephyr/sys/barrier.h>
#include <OsIf.h>
void z_arm_platform_init(void)
{
/* enable peripheral port access at EL1 and EL0 */
__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
__asm__ vola... | /content/code_sandbox/soc/nxp/s32/s32ze/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 375 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_NXP_S32_S32ZE_PINCTRL_SOC_H_
#define ZEPHYR_SOC_NXP_S32_S32ZE_PINCTRL_SOC_H_
#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
#include <zephyr/sys/util.h>
#include "../common/siul2_pinctrl.h"
/* SIUL2 Multiplexed Signal Configuration */
#define SIUL2_MSCR_SSS_MASK ... | /content/code_sandbox/soc/nxp/s32/s32ze/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 971 |
```objective-c
/*
*
*/
#ifndef _NXP_S32_S32ZE_SOC_H_
#define _NXP_S32_S32ZE_SOC_H_
/* Do not let CMSIS to handle GIC */
#define __GIC_PRESENT 0
#if defined(CONFIG_SOC_S32Z270)
#include <S32Z2.h>
#else
#error "SoC not supported"
#endif
#if defined(CONFIG_CMSIS_RTOS_V2)
#include <cmsis_rtos_v2_adapt.h>
#endif
/* A... | /content/code_sandbox/soc/nxp/s32/s32ze/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 326 |
```unknown
# NXP S32ZE MCUs series
if SOC_SERIES_S32ZE
config NUM_IRQS
# must be >= the highest interrupt number used
default 991
config FPU
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 2000000
config MAIN_STACK_SIZE
default 1024
if ETH_DRIVER && NET_L2_ETHERNET
# NETC drops TCP/UDP packets with in... | /content/code_sandbox/soc/nxp/s32/s32ze/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```unknown
# NXP S32ZE MCUs series
config SOC_SERIES_S32ZE
select ARM
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
select CPU_CORTEX_R52
select CPU_HAS_DCLS
select CPU_HAS_ARM_MPU
select GIC_SINGLE_SECURITY_STATE
select VFP_DP_D16
select PLATFORM_SPECIFIC_INIT
select CLOCK_CONTROL
select HAS_NXP_S32_HAL
selec... | /content/code_sandbox/soc/nxp/s32/s32ze/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 183 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_S32_COMMON_CMSIS_RTOS_V2_ADAPT_H_
#define ZEPHYR_SOC_ARM_NXP_S32_COMMON_CMSIS_RTOS_V2_ADAPT_H_
/*
* The HAL is defining these symbols already. To avoid interference
* between HAL and the CMSIS RTOS wrapper, redefine them under an enum.
*/
#undef TRUE
#undef FALSE... | /content/code_sandbox/soc/nxp/s32/common/cmsis_rtos_v2_adapt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_mc_me
#include <zephyr/kernel.h>
#if defined(CONFIG_REBOOT)
#include <zephyr/sys/reboot.h>
#endif /* CONFIG_REBOOT */
/* Control Key Register */
#define MC_ME_CTL_KEY 0x0
#define MC_ME_CTL_KEY_KEY_MASK GENMASK(15, 0)
#define MC_ME_CTL_KEY_KEY(v)... | /content/code_sandbox/soc/nxp/s32/common/mc_me.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,855 |
```c
/*
*
*/
#include <soc.h>
#include <OsIf.h>
#include <OsIf_Cfg_TypesDef.h>
#if defined(CONFIG_SOC_SERIES_S32K1)
/* Aliases needed to build with different SoC-specific HAL versions */
#define CPXNUM CPxNUM
#define MSCM_CPXNUM_CPN_MASK MSCM_CPxNUM_CPN_MASK
#endif
/* Required by OsIf timer ini... | /content/code_sandbox/soc/nxp/s32/common/osif.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 195 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_NXP_S32_COMMON_SIUL2_PINCTRL_H_
#define ZEPHYR_SOC_NXP_S32_COMMON_SIUL2_PINCTRL_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
/** @cond INTERNAL_HIDDEN */
struct pinctrl_soc_reg {
uint8_t inst;
uint16_t idx;
uint32_t val;
};
/** @brief Type for NXP SIUL2... | /content/code_sandbox/soc/nxp/s32/common/siul2_pinctrl.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 324 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32_mc_rgm
#include <zephyr/kernel.h>
#include <zephyr/init.h>
/* Destructive Event Status Register */
#define MC_RGM_DES 0x0
#define MC_RGM_DES_F_POR_MASK BIT(0)
#define MC_RGM_DES_F_POR(v) FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v))
/* ... | /content/code_sandbox/soc/nxp/s32/common/mc_rgm.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,357 |
```unknown
# NXP S32K1XX MCUs series
config SOC_SERIES_S32K1
bool
select SOC_FAMILY_NXP_S32
config SOC_SERIES
default "s32k1" if SOC_SERIES_S32K1
config SOC_S32K116
bool
select SOC_SERIES_S32K1
config SOC_S32K118
bool
select SOC_SERIES_S32K1
config SOC_S32K142
bool
select SOC_SERIES_S32K1
config SOC_S32... | /content/code_sandbox/soc/nxp/s32/s32k1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,632 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/linker/sections.h>
uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
/* Backdoor Comparison Key (unused) */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected */
0xFF, ... | /content/code_sandbox/soc/nxp/s32/s32k1/flash_configuration.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 262 |
```c
/*
*
* Based on zephyr/soc/soc_legacy/arm/nxp_kinetis/ke1xf/soc.c, which is:
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/sys/barrier.h>
#include <cmsis_core.h>
#include <OsIf.h>
#if defined(CONFIG_HAS_MCUX_CACHE)
#include <fsl_cache.h>
#endif
#if def... | /content/code_sandbox/soc/nxp/s32/s32k1/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 566 |
```objective-c
/*
*
*/
/*
* @file
* NXP S32K1 SOC specific helpers for pinctrl driver
*/
#ifndef ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_S32_S32K1_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HI... | /content/code_sandbox/soc/nxp/s32/s32k1/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 391 |
```objective-c
/*
*
*/
#ifndef _NXP_S32_S32K1_SOC_H_
#define _NXP_S32_S32K1_SOC_H_
#include <fsl_port.h>
#if defined(CONFIG_SOC_S32K116)
#include <S32K116.h>
#elif defined(CONFIG_SOC_S32K118)
#include <S32K118.h>
#elif defined(CONFIG_SOC_S32K142)
#include <S32K142.h>
#elif defined(CONFIG_SOC_S32K142W)
#include <S3... | /content/code_sandbox/soc/nxp/s32/s32k1/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 250 |
```unknown
# NXP S32K1XX MCU series
if SOC_SERIES_S32K1
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
config NUM_IRQS
default 239 if CPU_CORTEX_M4
default 47 if CPU_CORTEX_M0PLUS
config FPU
default y if CPU_HAS_FPU
# The S32K1xx have 8 MPU r... | /content/code_sandbox/soc/nxp/s32/s32k1/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 158 |
```unknown
# NXP S32K1XX MCUs series
config SOC_SERIES_S32K1
select ARM
select HAS_NXP_S32_HAL
select HAS_MCUX
select CPU_HAS_NXP_MPU
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select MPU_ALLOW_FLASH_WRITE if !XIP
select CLOCK_CONTROL
select HAS_MCUX_LPUART
select HAS_MCUX_LPI2C
select HAS_MCUX_LPSPI
sele... | /content/code_sandbox/soc/nxp/s32/s32k1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 804 |
```c
/*
*
* Based on soc/soc_legacy/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c, which is:
*
*/
#include <soc.h>
#include <zephyr/arch/arm/mpu/nxp_mpu.h>
static const struct nxp_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("DEBUGGER",
0,
0xFFFFFFFF,
REGION_DEBUGGER_AND_DEVICE_ATTR),
/*... | /content/code_sandbox/soc/nxp/s32/s32k1/nxp_mpu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 373 |
```linker script
/*
*
*/
. = CONFIG_NXP_S32_FLASH_CONFIG_OFFSET;
KEEP(*(.kinetis_flash_config))
KEEP(*(".kinetis_flash_config.*"))
``` | /content/code_sandbox/soc/nxp/s32/s32k1/flash_config.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# NXP S32K3XX MCU series
config SOC_SERIES_S32K3
bool
select SOC_FAMILY_NXP_S32
config SOC_SERIES
default "s32k3" if SOC_SERIES_S32K3
config SOC_S32K344
bool
select SOC_SERIES_S32K3
config SOC
default "s32k344" if SOC_S32K344
config SOC_PART_NUMBER_PS32K344EHVPBS
bool
config SOC_PART_NUMBER
de... | /content/code_sandbox/soc/nxp/s32/s32k3/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 128 |
```linker script
/*
*
*/
#ifdef CONFIG_XIP
.ivt_header : {
KEEP(*(.ivt_header));
} > IVT_HEADER
#else
#define _NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE (1 << 17)
#define _RO_Msk (7 << 24)
/* ROM region size order for MPU configuration */
_rom_region_order = ((LOG2CEIL(__rom_region_end - __rom_region_start... | /content/code_sandbox/soc/nxp/s32/s32k3/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
#if !defined(CONFIG_XIP)
extern char _rom_attr[];
#endif
static struct arm_mpu_region mpu_regions[] = {
/* Keep before CODE region so it can be overlapped by SRAM CODE i... | /content/code_sandbox/soc/nxp/s32/s32k3/mpu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 243 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <cmsis_core.h>
#include <OsIf.h>
#ifdef CONFIG_XIP
/* Image Vector Table structure definition for S32K3XX */
struct ivt {
uint32_t header;
uint32_t boot_configure;
const uint32_t reserv... | /content/code_sandbox/soc/nxp/s32/s32k3/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 389 |
```c
/*
*
*/
#define DT_DRV_COMPAT nxp_s32k3_pmc
#include <zephyr/kernel.h>
#include <zephyr/init.h>
/* Low Voltage Status and Control Register */
#define PMC_LVSC 0x0
#define PMC_LVSC_HVDAF_MASK BIT(0)
#define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v))
#define PMC_LVSC_HVDB... | /content/code_sandbox/soc/nxp/s32/s32k3/pmc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,010 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_NXP_S32_S32K3_PINCTRL_SOC_H_
#define ZEPHYR_SOC_NXP_S32_S32K3_PINCTRL_SOC_H_
#include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h>
#include <zephyr/sys/util.h>
#include "../common/siul2_pinctrl.h"
/* SIUL2 Multiplexed Signal Configuration */
#define SIUL2_MSCR_SSS_MASK ... | /content/code_sandbox/soc/nxp/s32/s32k3/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 919 |
```unknown
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#define MC_RGM_BASE 0x4028C000
#define MC_RGM_DES 0x0
#define MC_RGM_FES 0x8
_ASM_FILE_PROLOGUE
GTEXT(z_arm_platform_init)
SECTION_FUNC(TEXT, z_arm_platform_init)
/*
* On destructive reset, S... | /content/code_sandbox/soc/nxp/s32/s32k3/s32k3xx_startup.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 580 |
```objective-c
/*
*
*/
#ifndef _NXP_S32_S32K_SOC_H_
#define _NXP_S32_S32K_SOC_H_
#include <S32K344.h>
#include <core_cm7.h>
#if defined(CONFIG_CMSIS_RTOS_V2)
#include <cmsis_rtos_v2_adapt.h>
#endif
#endif /* _NXP_S32_S32K_SOC_H_ */
``` | /content/code_sandbox/soc/nxp/s32/s32k3/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
# NXP S32K3XX MCU series
if SOC_SERIES_S32K3
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 2000000
config NUM_IRQS
# must be >= the highest interrupt number used
default 239
config FPU
default y
if ETH_DRIVER && NET_L2_ETHERNET
config NET_TCP_CHECKSUM
default n
config NET_UDP_CHECKSUM
default n
e... | /content/code_sandbox/soc/nxp/s32/s32k3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```unknown
# NXP S32K3XX MCU series
config SOC_SERIES_S32K3
select ARM
select CPU_CORTEX_M7
select HAS_NXP_S32_HAL
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
select PLATFORM_SPECIFIC_INIT if XIP
select USE_DT_CODE_PARTITI... | /content/code_sandbox/soc/nxp/s32/s32k3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 260 |
```linker script
/*
*
*/
#ifdef CONFIG_XIP
MEMORY
{
IVT_HEADER (r) : ORIGIN = CONFIG_FLASH_BASE_ADDRESS + CONFIG_IVT_HEADER_OFFSET,
LENGTH = CONFIG_IVT_HEADER_SIZE
}
#endif
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
``` | /content/code_sandbox/soc/nxp/s32/s32k3/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
#
#
#
config SOC_FAMILY_NXP_LAYERSCAPE
bool
config SOC_FAMILY
default "nxp_layerscape" if SOC_FAMILY_NXP_LAYERSCAPE
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/nxp/layerscape/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```yaml
family:
- name: nxp_layerscape
series:
- name: ls1046a
socs:
- name: ls1046a
``` | /content/code_sandbox/soc/nxp/layerscape/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
#
#
#
if SOC_FAMILY_NXP_LAYERSCAPE
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_NXP_LAYERSCAPE
``` | /content/code_sandbox/soc/nxp/layerscape/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
#
#
#
#
if SOC_FAMILY_NXP_LAYERSCAPE
rsource "*/Kconfig"
endif # SOC_FAMILY_NXP_LAYERSCAPE
``` | /content/code_sandbox/soc/nxp/layerscape/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
#
#
#
config SOC_SERIES_LS1046A
bool
select SOC_FAMILY_NXP_LAYERSCAPE
config SOC_LS1046A
bool
select SOC_SERIES_LS1046A
help
NXP Layerscape ls1046a
config SOC
default "ls1046a" if SOC_LS1046A
config SOC_SERIES
default "ls1046a" if SOC_SERIES_LS1046A
config SOC_PART_NUMBER_LS1046A
bool
config... | /content/code_sandbox/soc/nxp/layerscape/ls1046a/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 151 |
```c
/*
*
*/
#include <zephyr/arch/arm64/arm_mmu.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
MT_DEV... | /content/code_sandbox/soc/nxp/layerscape/ls1046a/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 224 |
```unknown
#
#
#
if SOC_LS1046A
config NUM_IRQS
int
default 240
config FLASH_SIZE
default 0
config FLASH_BASE_ADDRESS
default 0
endif
``` | /content/code_sandbox/soc/nxp/layerscape/ls1046a/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
#
#
#
config SOC_LS1046A
select ARM64
select CPU_CORTEX_A72
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
``` | /content/code_sandbox/soc/nxp/layerscape/ls1046a/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
config SOC_FAMILY_NXP_RW
bool
config SOC_FAMILY
default "nxp_rw" if SOC_FAMILY_NXP_RW
config SOC_SERIES_RW6XX
bool
select SOC_FAMILY_NXP_RW
config SOC_SERIES
default "rw6xx" if SOC_SERIES_RW6XX
config SOC_RW610
bool
select SOC_SERIES_RW6XX
config SOC_RW612
bool
select SOC_SERIES_RW6XX
config ... | /content/code_sandbox/soc/nxp/rw/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 346 |
```linker script
/*
*
*/
#define TXQ23_SIZE 0x1080
#define SMU1_SIZE DT_REG_SIZE(DT_NODELABEL(smu1_data))
#define SMU2_SIZE DT_REG_SIZE(DT_NODELABEL(smu2_data))
.SMU1 (NOLOAD) :
{
. = ALIGN(4);
/* CPU3 <-> CPU1 mailbox */
*(.smu_cpu13_mbox)
KEEP (*(.smu_cpu13_mbox))
/* CPU3 -> CPU1 TXQ */
... | /content/code_sandbox/soc/nxp/rw/sections.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 294 |
```objective-c
/*
*/
#ifndef _FLEXSPI_CLOCK_SETUP_H_
#define _FLEXSPI_CLOCK_SETUP_H_
#include "fsl_common.h"
void set_flexspi_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider);
#endif /* _FLEXSPI_CLOCK_SETUP_H_ */
``` | /content/code_sandbox/soc/nxp/rw/flexspi_clock_setup.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```c
/*
*/
#include <zephyr/devicetree.h>
#include "flexspi_clock_setup.h"
#ifdef CONFIG_MEMC
#include <fsl_flexspi.h>
#include <fsl_clock.h>
#endif
#ifdef CONFIG_MEMC
/**
* @brief Set flexspi clock to given frequency
*
* This function differs from the above function in that it will not configure
* the FlexSPI w... | /content/code_sandbox/soc/nxp/rw/flexspi_clock_setup.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 547 |
```yaml
family:
- name: nxp_rw
series:
- name: rw61x
socs:
- name: rw612
- name: rw610
runners:
run_once:
'--erase':
- run: first
runners:
- all
groups:
- qualifiers:
- rw612
- qualifiers:
- rw610
'--reset':
- run: last
runners:
... | /content/code_sandbox/soc/nxp/rw/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```linker script
/*
*
*/
. = CONFIG_FLASH_CONFIG_OFFSET;
KEEP(*(.flash_conf))
. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
KEEP(*(.boot_hdr.ivt))
``` | /content/code_sandbox/soc/nxp/rw/boot_header.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_DEFS_H_
/* Internal macros to pack and extract pin configuration data. */
/* GPIO configuration packing macros */
#define IOMUX_OFFSET_ENABLE(offset, enable, shift) \
((((offset) << 1) | (enable... | /content/code_sandbox/soc/nxp/rw/pinctrl_defs.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 9,689 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/device.h>
#include <zephyr/drivers/uart.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/linker/sections.h>
#include <zephyr/sys/util_macro.h>
#include <cortex_m/exception.h>
#include <fsl_power.h>
#include <fsl_clock.h>
#include <fsl... | /content/code_sandbox/soc/nxp/rw/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,407 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RW6XX_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include "pinctrl_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t... | /content/code_sandbox/soc/nxp/rw/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 363 |
```objective-c
/*
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
#include <fsl_common.h>
#include "fsl_power.h"
/* Add include for DTS generated information */
#include <zephyr/devicetree.h>
#endif /* !_ASMLANGUAGE */
#define ble_hci_handler BLE_MCI_WAKEUP0_DriverIR... | /content/code_sandbox/soc/nxp/rw/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```unknown
if SOC_SERIES_RW6XX
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT
default 0x1300 if NXP_RW6XX_BOOT_HEADER
config NUM_IRQS
default 129
if MCUX_OS_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
endif # MCUX_OS_TIMER
if CORTEX_M_SYSTICK
config SYS_CLOCK_HW_CYCLES_PER_SEC
defa... | /content/code_sandbox/soc/nxp/rw/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 756 |
```linker script
/*
*
*/
/* For RW612, fw_cpu1 is used for wifi firmware.
* Place the wifi and ble firmwares in rodata section. If both binaries
* are placed next to each other, the firmware loader will detect the
* second binary as part of the first one, leading to initialization
* issue, so add a padding of on... | /content/code_sandbox/soc/nxp/rw/firmwares.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 133 |
```unknown
config SOC_SERIES_RW6XX
select ARM
select CPU_CORTEX_M33
select CPU_CORTEX_M_HAS_DWT
select CLOCK_CONTROL
select PLATFORM_SPECIFIC_INIT
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select HAS_MCUX_OS_TIMER
select ARM_TRUSTZONE_M
select CPU_CORTEX_M_HAS_SYSTICK
select HAS_MCUX... | /content/code_sandbox/soc/nxp/rw/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 668 |
```objective-c
/*
* All rights reserved.
*
*/
#ifndef __FLASH_CONFIG__
#define __FLASH_CONFIG__
#include <stdint.h>
#include <stdbool.h>
#include "fsl_common.h"
#define FC_BLOCK_TAG (0x42464346)
#define FC_BLOCK_VERSION (0x00000000)
#define FC_CMD_SDR 0x01
#define FC_CMD_DDR 0x21
#define FC_RA... | /content/code_sandbox/soc/nxp/rw/flash_config.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,471 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
#include <zephyr/init.h>
#include <zephyr/drivers/pinctrl.h>
#include "fsl_power.h"
#include <zephyr/logging/log.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
/* Active mode */
#define POWER_MODE0 0
/* Idle mode */
#define POWER_MODE1 1
/* Sta... | /content/code_sandbox/soc/nxp/rw/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,278 |
```unknown
config SOC_FAMILY_NXP_IMXRT
bool
config SOC_FAMILY
default "nxp_imxrt" if SOC_FAMILY_NXP_IMXRT
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/nxp/imxrt/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```objective-c
/*
*
* refer to hal_nxp board file
*
*/
#ifndef __FLEXSPI_NOR_CONFIG__
#define __FLEXSPI_NOR_CONFIG__
#include <zephyr/types.h>
#include "fsl_common.h"
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL)
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL)
#define FLEXSPI_CFG_BLK_SIZE (512)
#define FLEXSPI_FEAT... | /content/code_sandbox/soc/nxp/imxrt/flexspi_nor_config.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,886 |
```c
/*
*
*/
#define SDRAM_BASE_ADDR 0x80000000
#include <zephyr/devicetree.h>
#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
static const struct arm_mpu_region mpu_regions[] = {
/* Region 0 */
MPU_REGION_ENTRY("FLASH_0",
CONFIG_FLASH_BASE_ADDRESS,
REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
/* Region... | /content/code_sandbox/soc/nxp/imxrt/mpu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 233 |
```yaml
family:
- name: nxp_imxrt
series:
- name: imxrt10xx
socs:
- name: mimxrt1011
- name: mimxrt1015
- name: mimxrt1021
- name: mimxrt1024
- name: mimxrt1042
- name: mimxrt1051
- name: mimxrt1052
- name: mimxrt1061
- name: mimxrt1062
- name: mimxrt1064
- name: imxrt1... | /content/code_sandbox/soc/nxp/imxrt/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 571 |
```linker script
/*
*
*/
#if defined(CONFIG_SOC_SERIES_IMXRT118X)
__VECTOR_TABLE = CONFIG_ROM_START_OFFSET;
__Vectors = __VECTOR_TABLE;
#endif
. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X)
KEEP(*(.boot... | /content/code_sandbox/soc/nxp/imxrt/boot_header.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 272 |
```unknown
if SOC_FAMILY_NXP_IMXRT
# Source series Kconfig files first, so SOCs
# can override the defaults given here
rsource "*/Kconfig.defconfig"
if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
config SERIAL_INIT_PRIORITY
default 55 if SERIAL
depends on SERIAL
config ROM_START_OFFSET
... | /content/code_sandbox/soc/nxp/imxrt/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,111 |
```unknown
config SOC_FAMILY_NXP_IMXRT
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_NXP_IMXRT
# Source series Kconfig files first, so SOCs
# can override the defaults given here
rsource "*/Kconfig"
# Used for default value in FLASH_MCUX_FLEXSPI_XIP
DT_CHOSEN_Z_FLASH := zephyr,flash
DT_COMPAT_FLEXSPI... | /content/code_sandbox/soc/nxp/imxrt/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,044 |
```linker script
/*
*
*/
#if defined(CONFIG_SOC_SERIES_IMXRT118X) && CONFIG_NXP_IMXRT_BOOT_HEADER
__CONTAINER_IMG_OFFSET = CONFIG_CONTAINER_USER_IMAGE_OFFSET;
__CONTAINER_IMG_SIZE = _flash_used;
#endif
``` | /content/code_sandbox/soc/nxp/imxrt/container.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```linker script
/*
*
*/
GROUP_START(USB_BDT)
SECTION_PROLOGUE(_USB_BDT_SECTION_NAME,(NOLOAD),)
{
. = ALIGN(512);
*(m_usb_bdt)
} GROUP_LINK_IN(SRAM1)
GROUP_END(USB_BDT)
GROUP_START(USB_GLOBAL)
SECTION_PROLOGUE(_USB_GLOBAL_SECTION_NAME,(NOLOAD),)
{
*(m_usb_global)
} GROUP_LINK_IN(SRAM1)
GROUP_END(USB... | /content/code_sandbox/soc/nxp/imxrt/usb.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```unknown
config SOC_SERIES_IMXRT118X
bool
select SOC_FAMILY_NXP_IMXRT
config SOC_SERIES
default "imxrt118x" if SOC_SERIES_IMXRT118X
config SOC_MIMXRT1189
bool
select SOC_SERIES_IMXRT118X
config SOC_MIMXRT1189_CM33
bool
select SOC_MIMXRT1189
config SOC_MIMXRT1189_CM7
bool
select SOC_MIMXRT1189
config SO... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 542 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/linker/sections.h>
#include <zephyr/linker/linker-defs.h>
#if defined(CONFIG_SOC_MIMXRT1189_CM7)
#include <zephyr/cache.h>
#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
#include <fsl_cache.h... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,745 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_
#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_RT118X_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include "fsl_common.h"
#ifdef __cplusplus
extern "C" {
#endif
#define MCUX_IMX_ODE_SHIFT 4
#define MCUX_IMX_PUS_SHIFT 3
#define M... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,490 |
```objective-c
/*
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <fsl_common.h>
/* Add include for DTS generated information */
#include <zephyr/devicetree.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* !_ASMLANGUAGE */
#endi... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```unknown
if SOC_SERIES_IMXRT118X
config NUM_IRQS
default 239
config GPIO
default y
if CORTEX_M_SYSTICK
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 240000000 if SOC_MIMXRT1189_CM33
default 792000000 if SOC_MIMXRT1189_CM7
endif # CORTEX_M_SYSTICK
config DCDC_VALUE
default 0x13
config FLEXSPI_CONFIG_BLOCK_OF... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 168 |
```unknown
config SOC_SERIES_IMXRT118X
select CPU_CORTEX_M_HAS_DWT
select PLATFORM_SPECIFIC_INIT
select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
select ARM
select CLOCK_CONTROL
select HAS_MCUX_CACHE
select ARMV8_M_DSP if SOC_MIMXRT1189_CM33
select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
select HAS_MCUX
sel... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 414 |
```linker script
/*
*
*/
#include <zephyr/devicetree.h>
#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram)))
MEMORY
{
#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0)
SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_... | /content/code_sandbox/soc/nxp/imxrt/imxrt118x/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 135 |
```unknown
# i.MX RT5XX Series
config SOC_SERIES_IMXRT5XX
bool
select SOC_FAMILY_NXP_IMXRT
config SOC_MIMXRT595S
bool
select SOC_SERIES_IMXRT5XX
config SOC_MIMXRT595S_CM33
bool
select SOC_MIMXRT595S
help
NXP RT5xx CM33 core
config SOC_MIMXRT595S_F1
bool
select SOC_MIMXRT595S
help
NXP RT5xx ADSP Ser... | /content/code_sandbox/soc/nxp/imxrt/imxrt5xx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 431 |
```unknown
if SOC_MIMXRT595S_CM33
config ROM_START_OFFSET
default 0x1200 if NXP_IMXRT_BOOT_HEADER
# The PVT Sensor uses IRQ #75. For more details, see
# path_to_url
config NUM_IRQS
default 76
config ZTEST_NO_YIELD
default y if (PM && ZTEST)
# Code relocation is needed for flash clock setup
config CODE_DATA_REL... | /content/code_sandbox/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 578 |
```unknown
config SOC_MIMXRT595S_CM33
select CPU_CORTEX_M33
select CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select ARM
select HAS_PM
select HAS_POWEROFF
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select PLATFORM_SPECIFIC_INIT
select ARMV8_M_DSP
select ARM_TRUSTZONE_M
select CPU_CORT... | /content/code_sandbox/soc/nxp/imxrt/imxrt5xx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 588 |
```linker script
/*
*
*/
OUTPUT_ARCH(xtensa)
#include <soc/memory.h>
#include <xtensa/config/core-isa.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#include <zephyr/linker/sections.h>
#define RAMABLE_REGION sdram0 :sdram0_phdr
#define ROMABLE_REGION sdram0 :sdram0_phdr
MEMORY
{... | /content/code_sandbox/soc/nxp/imxrt/imxrt5xx/f1/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,149 |
```objective-c
/*
*
*/
#include <string.h>
#include <errno.h>
#include <zephyr/sys/sys_io.h>
#include <adsp/cache.h>
#ifndef __INC_IMX_SOC_H
#define __INC_IMX_SOC_H
/* Macros related to interrupt handling */
#define XTENSA_IRQ_NUM_SHIFT 0
#define XTENSA_IRQ_NUM_MASK 0xff
/*
* IRQs are mapped on levels. 2nd... | /content/code_sandbox/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 188 |
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