text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef __COMMON_ADSP_CACHE_H__
#define __COMMON_ADSP_CACHE_H__
#include <xtensa/hal.h>
#endif
``` | /content/code_sandbox/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
config SOC_FAMILY_LPC
bool
config SOC_FAMILY
default "lpc" if SOC_FAMILY_LPC
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/nxp/lpc/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```objective-c
/*
*
*/
#ifndef __INCLUDE_IO__
#define __INCLUDE_IO__
#include <stdint.h>
#include <soc/memory.h>
#include <zephyr/sys/sys_io.h>
#include <zephyr/arch/common/sys_io.h>
static inline uint32_t io_reg_read(uint32_t reg)
{
return sys_read32(reg);
}
static inline void io_reg_write(uint32_t reg, uint32_... | /content/code_sandbox/soc/nxp/imx/imx8x/adsp/include/adsp/io.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 188 |
```unknown
if SOC_FAMILY_LPC
config SERIAL_INIT_PRIORITY
default 55 if SERIAL
config BUILD_WITH_TFM
default y if TRUSTED_EXECUTION_NONSECURE
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_LPC
``` | /content/code_sandbox/soc/nxp/lpc/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
config SOC_FAMILY_LPC
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select CLOCK_CONTROL
select ARM
if SOC_FAMILY_LPC
rsource "*/Kconfig"
endif # SOC_FAMILY_LPC
``` | /content/code_sandbox/soc/nxp/lpc/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```yaml
family:
- name: lpc
series:
- name: lpc11u6x
socs:
- name: lpc11u66
- name: lpc11u67
- name: lpc11u68
- name: lpc51u68
socs:
- name: lpc51u68
- name: lpc54xxx
socs:
- name: lpc54114
cpuclusters:
- name: m4
- name: m0
- name: lpc55xxx
socs:
- na... | /content/code_sandbox/soc/nxp/lpc/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 403 |
```unknown
# LPC LPC54XXX MCU line
config SOC_SERIES_LPC54XXX
bool
select SOC_FAMILY_LPC
config SOC_SERIES
default "lpc54xxx" if SOC_SERIES_LPC54XXX
config SOC_LPC54114
bool
select SOC_SERIES_LPC54XXX
config SOC_LPC54114_M4
bool
select SOC_LPC54114
config SOC_LPC54114_M0
bool
select SOC_LPC54114
# The N... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 240 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_LPC_54xxx_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_LPC_54xxx_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_IOCON_... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 745 |
```c
/*
*
*/
/**
* @file
* @brief System/hardware module for nxp_lpc54114 platform
*
* This module provides routines to initialize and support board-level
* hardware for the nxp_lpc54114 platform.
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zeph... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,376 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the nxp_lpc54114 platform
*
* This header file is used to specify and describe board-level aspects for the
* 'nxp_lpc54114' platform.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
#include <fsl... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 340 |
```unknown
# NXP LPC54114 M0 platform configuration options
if SOC_SERIES_LPC54XXX
config GPIO
default n if SOC_LPC54114_M0
config NUM_IRQS
# must be >= the highest interrupt number used
default 40
endif # SOC_SERIES_LPC54XXX
``` | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/
/* The SDK CMIS SystemInit function sets VTOR equal to &__Vectors,
* so we create an alias for the symbol to Zephyr's vector table
*/
__Vectors = _vector_tabl... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# LPC LPC54XXX MCU line
config SOC_SERIES_LPC54XXX
select ARM
select HAS_MCUX
select HAS_MCUX_FLEXCOMM
select HAS_MCUX_SYSCON
select CPU_CORTEX_M_HAS_SYSTICK
select PLATFORM_SPECIFIC_INIT
config SOC_LPC54114_M4
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HA... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 497 |
```unknown
# NXP LPC11U6x series
#
#
config SOC_SERIES_LPC11U6X
bool
select SOC_FAMILY_LPC
config SOC_SERIES
default "lpc11u6x" if SOC_SERIES_LPC11U6X
config SOC_LPC11U68
bool
select SOC_SERIES_LPC11U6X
config SOC_LPC11U67
bool
select SOC_SERIES_LPC11U6X
config SOC_LPC11U66
bool
select SOC_SERIES_LPC11U... | /content/code_sandbox/soc/nxp/lpc/lpc11u6x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 449 |
```unknown
/*
* All rights reserved.
*
*
*/
#include <zephyr/toolchain.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#if defined(CONFIG_PLATFORM_SPECIFIC_INIT) && defined(CONFIG_SOC_LPC54114_M4)
.syntax unified
.arch armv7-m
.text
.thumb
rel_vals:
.long 0xE000ED00 /... | /content/code_sandbox/soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 959 |
```objective-c
/*
*
*/
/**
* @file Describe the IAP commands interface on NXP LPC11U6x MCUs.
*
* The IAP (In-Application Programming) commands are located in the boot ROM
* code. Mostly they provide access to the on-chip flash and EEPROM devices.
*
* @note For details about IAP see the UM10732 LPC11U6x/E6x use... | /content/code_sandbox/soc/nxp/lpc/lpc11u6x/iap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 612 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_LPC_11U6X_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_LPC_11U6X_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#include <soc.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define... | /content/code_sandbox/soc/nxp/lpc/lpc11u6x/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 760 |
```unknown
# LPC LPC11U6X MCU line
#
#
#
if SOC_SERIES_LPC11U6X
config NUM_IRQS
# must be >= the highest interrupt number used
default 40
endif # SOC_SERIES_LPC11U6X
``` | /content/code_sandbox/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
# LPC LPC11U6X MCU line
#
#
#
config SOC_SERIES_LPC11U6X
select ARM
select CPU_CORTEX_M0PLUS
select CPU_CORTEX_M_HAS_SYSTICK
select PINCTRL
select CLOCK_CONTROL
``` | /content/code_sandbox/soc/nxp/lpc/lpc11u6x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the nxp_lpc11u6x platform
*
* This header file is used to specify and describe board-level aspects for the
* 'nxp_lpc11u6x' platform.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
#include <cm... | /content/code_sandbox/soc/nxp/lpc/lpc11u6x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 858 |
```unknown
config SOC_SERIES_LPC55XXX
bool
select SOC_FAMILY_LPC
config SOC_SERIES
default "lpc55xxx" if SOC_SERIES_LPC55XXX
config SOC_LPC55S06
bool
select SOC_SERIES_LPC55XXX
config SOC_LPC55S16
bool
select SOC_SERIES_LPC55XXX
config SOC_LPC55S26
bool
select SOC_SERIES_LPC55XXX
config SOC_LPC55S28
boo... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 662 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_LPC_55xxx_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_LPC_55xxx_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#ifdef CONFIG_SOC_LPC55S... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 913 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the nxp_lpc55s69 platform
*
* This header file is used to specify and describe board-level aspects for the
* 'nxp_lpc55s69' platform.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <fsl_common.h>
#endif /* !_ASML... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 552 |
```unknown
if SOC_SERIES_LPC55XXX
config NUM_IRQS
# must be >= the highest interrupt number used
default 60
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 144000000 if INIT_PLL1
default 96000000
# Indicates the second core will be enabled, and the part will run
# in dual core mode.
config SECOND_CORE_MCUX
depends ... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 653 |
```unknown
config SOC_SERIES_LPC55XXX
select HAS_MCUX
select HAS_MCUX_FLEXCOMM
select HAS_MCUX_SYSCON
select HAS_MCUX_WWDT
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_DWT
select PLATFORM_SPECIFIC_INIT
config SOC_LPC55S06
select CPU_CORTEX_M33
select CPU_HAS_ARM_SAU
select CPU_HAS_ARM_MPU
select... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 852 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* This is the linker script for both standard images and XIP images.
*/
/* The SDK CMIS SystemInit function sets VTOR equal to &__Vectors,
* so we create an alias for the symbol to Zephyr's vector table
*/
__Vectors = _vector_tabl... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/pm/pm.h>
void pm_state_set(enum pm_state state, uint8_t id)
{
ARG_UNUSED(id);
switch (state) {
case PM_STATE_RUNTIME_IDLE:
k_cpu_idle();
break;
default:
break;
}
}
void pm_state_exit_post_ops(enum pm_state state, uint8_t id)
{
ARG_UNUSED(state)... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```c
*
*/
/**
* @file
* @brief System/hardware module for nxp_lpc55s69 platform
*
* This module provides routines to initialize and support board-level
* hardware for the nxp_lpc55s69 platform.
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <zephyr/... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,099 |
```linker script
/*
*
*/
GROUP_START(USB_BDT)
SECTION_PROLOGUE(_USB_BDT_SECTION_NAME,(NOLOAD),)
{
. = ALIGN(512);
*(m_usb_bdt)
} GROUP_LINK_IN(USB_SRAM)
GROUP_END(USB_BDT)
GROUP_START(USB_GLOBAL)
SECTION_PROLOGUE(_USB_GLOBAL_SECTION_NAME,(NOLOAD),)
{
*(m_usb_global)
} GROUP_LINK_IN(USB_SRAM)
GROUP_E... | /content/code_sandbox/soc/nxp/lpc/lpc55xxx/usb.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```unknown
# LPC LPC51U68 MCU line
config SOC_SERIES_LPC51U68
bool
select SOC_FAMILY_LPC
config SOC_SERIES
default "lpc51u68" if SOC_SERIES_LPC51U68
config SOC_LPC51U68
bool
select SOC_SERIES_LPC51U68
config SOC
default "lpc51u68" if SOC_LPC51U68
config SOC_PART_NUMBER_LPC51U68JBD48
bool
config SOC_PART_N... | /content/code_sandbox/soc/nxp/lpc/lpc51u68/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <soc.h>
#include <fsl_power.h>
#include <fsl_clock.h>
int soc_init(void)
{
POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);
CLOCK_SetupFROClocking(12000000U);
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
CLOCK_SetFLASHAccessCycl... | /content/code_sandbox/soc/nxp/lpc/lpc51u68/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 439 |
```objective-c
/*
*
*/
#ifndef _SOC_H_
#define _SOC_H_
#ifndef _ASMLANGUAGE
#include <zephyr/sys/util.h>
#include <fsl_common.h>
#endif /* !_ASMLANGUAGE*/
#define IOCON_PIO_DIGITAL_EN 0x80u
#define IOCON_PIO_FUNC0 0x00u
#define IOCON_PIO_FUNC1 0x01u
#define IOCON_PIO_FUNC2 0x02u
#define IOCON_PIO_FUNC3 0x03u... | /content/code_sandbox/soc/nxp/lpc/lpc51u68/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 287 |
```unknown
# LPC51U68 series configuration options
if SOC_SERIES_LPC51U68
config NUM_IRQS
# must be >= the highest interrupt number used.
default 32
config SOC_FLASH_LPC
default y
depends on FLASH
endif # SOC_SERIES_LPC51U86
``` | /content/code_sandbox/soc/nxp/lpc/lpc51u68/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_NXP_LPC_51U68_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_NXP_LPC_51U68_PINCTRL_SOC_H_
#include <zephyr/devicetree.h>
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_IOCON_... | /content/code_sandbox/soc/nxp/lpc/lpc51u68/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 749 |
```unknown
# LPC51U68 series configuration options
#
#
#
config SOC_SERIES_LPC51U68
select ARM
select CPU_CORTEX_M0PLUS
select HAS_MCUX
select HAS_MCUX_FLEXCOMM
select HAS_MCUX_SYSCON
select HAS_MCUX_SCTIMER
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_CORTEX_M_HAS_VTOR
select PLATFORM_SPECIFIC_INIT
config SOC... | /content/code_sandbox/soc/nxp/lpc/lpc51u68/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```linker script
/*
*
*/
/* The SDK CMIS SystemInit function sets VTOR equal to &__Vectors,
* so we create an alias for the symbol to Zephyr's vector table
*/
__Vectors = _vector_table;
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
``` | /content/code_sandbox/soc/nxp/lpc/lpc51u68/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```yaml
socs:
- name: neorv32
``` | /content/code_sandbox/soc/neorv32/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
config SOC_NEORV32
bool
help
NEORV32 Processor (SoC).
The NEORV32 CPU implementation must have the following RISC-V ISA
extensions enabled in order to support Zephyr:
- M (Integer Multiplication and Division)
- Zicsr (Control and Status Register (CSR) Instructions)
The following NEORV3... | /content/code_sandbox/soc/neorv32/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 160 |
```c
/*
*
*/
#include <zephyr/irq.h>
#include <soc.h>
#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void)
{
(void)arch_irq_lock();
csr_write(mie, 0);
}
#endif
``` | /content/code_sandbox/soc/neorv32/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
/*
*
*/
#include <zephyr/toolchain.h>
GTEXT(__soc_handle_irq)
/*
* SOC-specific function to handle pending IRQ number generating the interrupt.
* Exception number is given as parameter via register a0.
*/
SECTION_FUNC(exception.other, __soc_handle_irq)
/*
* The MIP CSR on the NEORV32 is read-only ... | /content/code_sandbox/soc/neorv32/soc_irq.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```unknown
if SOC_NEORV32
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER
config NUM_IRQS
default 32
config RISCV_GP
default y
config SYSCON
default y
config SERIAL_INIT_PRIORITY
default 55
depends on SERIAL
config ENTROPY_INIT_PRIORITY
... | /content/code_sandbox/soc/neorv32/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```unknown
config SOC_NEORV32
select RISCV
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_PRIVILEGED
if SOC_NEORV32
config SOC_NEORV32_V1_8_6
bool "v1.8.6"
# NEORV32 RISC-V ISA A extension implements only LR/SC, not ... | /content/code_sandbox/soc/neorv32/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 272 |
```objective-c
/*
*
*/
#ifndef RISCV_NEORV32_SOC_H
#define RISCV_NEORV32_SOC_H
/* System information (SYSINFO) register offsets */
#define NEORV32_SYSINFO_CLK 0x00U
#define NEORV32_SYSINFO_CPU 0x04U
#define NEORV32_SYSINFO_FEATURES 0x08U
#define NEORV32_SYSINFO_CACHE 0x0cU
#define NEORV32_S... | /content/code_sandbox/soc/neorv32/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 721 |
```linker script
/*
*
*/
#include <zephyr/linker/linker-tool.h>
MEMORY
{
IO (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512
}
SECTIONS
{
SECTION_PROLOGUE(io, (NOLOAD),)
{
PROVIDE(__io_start = ORIGIN(IO));
PROVIDE(__io_end = ORIGIN(IO) + LENGTH(IO));
} GROUP_LINK_IN(IO)
}
#include <zephyr/arch/riscv/common/link... | /content/code_sandbox/soc/neorv32/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```unknown
config SOC_FAMILY_QEMU_VIRT_RISCV
bool
config SOC_FAMILY
default "qemu_virt_riscv" if SOC_FAMILY_QEMU_VIRT_RISCV
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/qemu/virt_riscv/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
/*
*
*/
#include <zephyr/toolchain.h>
/* exports */
GTEXT(__reset)
/* imports */
GTEXT(__initialize)
SECTION_FUNC(reset, __reset)
/* Zerorize zero register */
lui x0, 0
/* Disable interrupts */
csrw mstatus, x0
csrw mie, x0
#ifdef CONFIG_USERSPACE
/* Disable counter access outside M-mode */
cs... | /content/code_sandbox/soc/neorv32/reset.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 419 |
```yaml
family:
- name: qemu_virt_riscv
socs:
- name: qemu_virt_riscv32
- name: qemu_virt_riscv32e
- name: qemu_virt_riscv64
``` | /content/code_sandbox/soc/qemu/virt_riscv/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
if SOC_FAMILY_QEMU_VIRT_RISCV
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 10000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 52
config NUM_IRQS
defau... | /content/code_sandbox/soc/qemu/virt_riscv/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```c
/*
*
*/
/**
* @file
* @brief QEMU RISC-V virt machine hardware depended interface
*/
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/sys/util.h>
#define SIFIVE_SYSCON_TEST 0x00100000
/*
* Exit QEMU and tell error number.
* Higher 16bits: indicates error number.
* Lower 16bi... | /content/code_sandbox/soc/qemu/virt_riscv/common/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 193 |
```unknown
config SOC_QEMU_VIRT_RISCV32E
bool
select SOC_FAMILY_QEMU_VIRT_RISCV
config SOC
default "qemu_virt_riscv32e" if SOC_QEMU_VIRT_RISCV32E
``` | /content/code_sandbox/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```unknown
config SOC_QEMU_VIRT_RISCV32E
select RISCV_ISA_RV32E
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
``` | /content/code_sandbox/soc/qemu/virt_riscv/qemu_virt_riscv32e/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
config SOC_FAMILY_QEMU_VIRT_RISCV
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
if SOC_FAMILY_QEMU_VIRT_RISCV
rsource "*/Kconfig"
endif # SOC_FAMILY_QEMU_... | /content/code_sandbox/soc/qemu/virt_riscv/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
config SOC_QEMU_VIRT_RISCV64
bool
select SOC_FAMILY_QEMU_VIRT_RISCV
config SOC
default "qemu_virt_riscv64" if SOC_QEMU_VIRT_RISCV64
``` | /content/code_sandbox/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config SOC_QEMU_VIRT_RISCV32
bool
select SOC_FAMILY_QEMU_VIRT_RISCV
config SOC
default "qemu_virt_riscv32" if SOC_QEMU_VIRT_RISCV32
``` | /content/code_sandbox/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config SOC_QEMU_VIRT_RISCV64
select 64BIT
select CPU_HAS_FPU_DOUBLE_PRECISION
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
``` | /content/code_sandbox/soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
#
config SOC_QEMU_MALTA
bool
config SOC
default "qemu_malta" if SOC_QEMU_MALTA
``` | /content/code_sandbox/soc/qemu/malta/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
config SOC_QEMU_VIRT_RISCV32
select CPU_HAS_FPU
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
``` | /content/code_sandbox/soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
/*
*
*/
#include <zephyr/toolchain.h>
#include <mips/regdef.h>
/* Imports */
GTEXT(__initialize)
/* Exports */
GTEXT(__start)
SECTION_FUNC(vectors, __start)
/* Call into Zephyr initialization. */
la v0, __initialize
jal v0
``` | /content/code_sandbox/soc/qemu/malta/vector.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```yaml
socs:
- name: qemu_malta
``` | /content/code_sandbox/soc/qemu/malta/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 12 |
```unknown
#
if SOC_QEMU_MALTA
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 200000000
config NUM_IRQS
default 8
endif # SOC_QEMU_MALTA
``` | /content/code_sandbox/soc/qemu/malta/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```objective-c
/*
*
*/
#ifndef __QEMU_MALTA_SOC_H__
#define __QEMU_MALTA_SOC_H__
#define MIPS_MACHINE_TIMER_IRQ 7 /* Machine Timer Interrupt */
#endif /* __QEMU_MALTA_SOC_H__ */
``` | /content/code_sandbox/soc/qemu/malta/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
#
config SOC_QEMU_MALTA
select MIPS
``` | /content/code_sandbox/soc/qemu/malta/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 13 |
```unknown
config SOC_POSIX
bool
help
SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast
clock. That means the CPU will always run in zero time until completion after
each wake reason (e.g. interrupts), before going back to idle. Note that an
infinite loop in the code which does n... | /content/code_sandbox/soc/native/inf_clock/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```c
/*
*
*/
/**
* @brief Run the set of special native tasks corresponding to the given level
*
* @param level One of _NATIVE_*_LEVEL as defined in soc.h
*/
void run_native_tasks(int level)
{
extern void (*__native_PRE_BOOT_1_tasks_start[])(void);
extern void (*__native_PRE_BOOT_2_tasks_start[])(void);
exter... | /content/code_sandbox/soc/native/inf_clock/native_tasks.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 263 |
```yaml
family:
- name: native
socs:
- name: native
``` | /content/code_sandbox/soc/native/inf_clock/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```objective-c
/*
*
*/
#ifndef _POSIX_SOC_INF_CLOCK_POSIX_NATIVE_TASK_H
#define _POSIX_SOC_INF_CLOCK_POSIX_NATIVE_TASK_H
#include <zephyr/toolchain.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* NATIVE_TASK
*
* For native targets (POSIX arch based), register a function to be called at particular moments
* du... | /content/code_sandbox/soc/native/inf_clock/posix_native_task.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 452 |
```objective-c
/*
*
*/
#ifndef _POSIX_CORE_BOARD_PROVIDED_IF_H
#define _POSIX_CORE_BOARD_PROVIDED_IF_H
#include <zephyr/types.h>
#include <zephyr/toolchain.h>
/*
* This file lists the functions the posix "inf_clock" soc
* expect the board to provide
*
* All functions listed here must be provided by the implemen... | /content/code_sandbox/soc/native/inf_clock/posix_board_if.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 160 |
```objective-c
/*
*
*/
#ifndef _POSIX_SOC_INF_CLOCK_SOC_H
#define _POSIX_SOC_INF_CLOCK_SOC_H
#include <zephyr/toolchain.h>
#include "board_soc.h"
#include "posix_soc.h"
#include "posix_native_task.h"
#ifdef __cplusplus
extern "C" {
#endif
void posix_soc_clean_up(void);
#ifdef __cplusplus
}
#endif
#endif /* _POS... | /content/code_sandbox/soc/native/inf_clock/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```objective-c
/*
*
*/
#ifndef _SOC_IRQ_H
#define _SOC_IRQ_H
#include "board_irq.h"
/*
* This SOC relies on the boards providing all the IRQ support
*/
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
#endif /* _SOC_IRQ_H */
``` | /content/code_sandbox/soc/native/inf_clock/soc_irq.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 62 |
```objective-c
/*
*
*/
#ifndef _POSIX_POSIX_SOC_INF_CLOCK_H
#define _POSIX_POSIX_SOC_INF_CLOCK_H
#include <zephyr/arch/posix/posix_soc_if.h>
#ifdef __cplusplus
extern "C" {
#endif
void posix_interrupt_raised(void);
void posix_boot_cpu(void);
int posix_is_cpu_running(void);
void posix_change_cpu_state_and_wait(bo... | /content/code_sandbox/soc/native/inf_clock/posix_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```c
/*
*
*/
/**
* For all purposes, Zephyr threads see a CPU running at an infinitely high
* clock.
*
* Therefore, the code will always run until completion after each interrupt,
* after which arch_cpu_idle() will be called releasing the execution back to
* the HW models.
*
* The HW models raising an interr... | /content/code_sandbox/soc/native/inf_clock/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 910 |
```unknown
config SOC_MT8195_ADSP
bool
config SOC
default "mt8195_adsp" if SOC_MT8195_ADSP
``` | /content/code_sandbox/soc/mediatek/mtk_adsp/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
config SOC_POSIX
select ARCH_POSIX
select CPU_HAS_FPU
if SOC_POSIX
config NATIVE_SIMULATOR_MCU_N
int "CPU Number this image targets"
range 0 15
default 0
depends on NATIVE_LIBRARY
help
Which native simulator microcontroller/CPU number is this image targeting.
This option is only applicable fo... | /content/code_sandbox/soc/native/inf_clock/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 453 |
```yaml
family:
- name: mtk_adsp
series:
- name: mtk_adsp
socs:
- name: mt8195_adsp
``` | /content/code_sandbox/soc/mediatek/mtk_adsp/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```c
*/
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
/* Be warned: the interface here is poorly understood. I did the best
* I could to transcribe it (with a little clarification and
* optimization) from the SOF mt8195 source, but without docs this
* needs to be treated with great care.
*
* Notes... | /content/code_sandbox/soc/mediatek/mtk_adsp/cpuclk.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,390 |
```c
*/
#include <zephyr/devicetree.h>
#include <string.h>
#include <kernel_internal.h>
extern char _mtk_adsp_sram_end[];
#define SRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
#define SRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
#define SRAM_END (SRAM_START + SRAM_SIZE)
extern char _mtk_adsp_dram_end[];
#define DR... | /content/code_sandbox/soc/mediatek/mtk_adsp/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,933 |
```objective-c
*/
#ifndef ZEPHYR_SOC_MTK_ADSP_SOC_H
#define ZEPHYR_SOC_MTK_ADSP_SOC_H
#include <zephyr/device.h>
void mtk_adsp_cpu_freq_init(void);
void mtk_adsp_set_cpu_freq(int mhz);
/* Mailbox Driver: */
/* Hardware defines multiple "channel" bits that can be independently
* signaled and cleared. An interrup... | /content/code_sandbox/soc/mediatek/mtk_adsp/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 306 |
```python
#!/usr/bin/env python
import ctypes
import sys
import mmap
import time
import struct
# MT8195 audio firmware load/debug gadget
# Note that the hardware handling here is only partial: in practice
# the audio DSP depends on clock and power well devices whose drivers
# live elsewhere in the kernel. Those aren... | /content/code_sandbox/soc/mediatek/mtk_adsp/mtk_adsp_load.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,393 |
```unknown
orsource "*/Kconfig.defconfig"
if SOC_FAMILY_MTK_ADSP
config SOC_FAMILY
default "mtk_adsp"
config INTC_MTK_ADSP
default y
config XTENSA_SMALL_VECTOR_TABLE_ENTRY
default y
config XTENSA_USE_CORE_CRT1
default n
config MULTI_LEVEL_INTERRUPTS
default y
config 2ND_LEVEL_INTERRUPTS
default y
config MA... | /content/code_sandbox/soc/mediatek/mtk_adsp/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 439 |
```unknown
config SOC_FAMILY_MTK_ADSP
bool
select XTENSA
select XTENSA_GEN_HANDLERS
help
Mediatek MT8xxx Series Audio DSPs
config SOC_SERIES_MT8195_ADSP
bool
select SOC_FAMILY_MTK_ADSP
help
Mediatek MT8195 Audio DSP
config SOC_MT8195_ADSP
bool
select SOC_SERIES_MT8195_ADSP
``` | /content/code_sandbox/soc/mediatek/mtk_adsp/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```c
*/
#include <zephyr/irq.h>
#include <zephyr/devicetree.h>
#include <zephyr/device.h>
bool intc_mtk_adsp_get_enable(const struct device *dev, int irq);
void intc_mtk_adsp_set_enable(const struct device *dev, int irq, bool val);
/* Sort of annoying: assumes there are exactly two controller devices
* and that th... | /content/code_sandbox/soc/mediatek/mtk_adsp/irq.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 459 |
```c
*/
#include <zephyr/device.h>
#include <zephyr/irq.h>
#include <zephyr/devicetree.h>
#include <soc.h>
#define DT_DRV_COMPAT mediatek_mbox
/* Mailbox: a simple interrupt source. Each direction has a 5-bit
* command register and will latch an interrupt if any of the bits are
* non-zero. The interrupt bits ge... | /content/code_sandbox/soc/mediatek/mtk_adsp/mbox.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,072 |
```python
#!/usr/bin/env python3
import sys
import struct
import elftools.elf.elffile
import elftools.elf.sections
# Converts a zephyr.elf file into an extremely simple "image format"
# for device loading. Really we should just load the ELF file
# directly, but the python ChromeOS test image lacks elftools. Longer
#... | /content/code_sandbox/soc/mediatek/mtk_adsp/gen_img.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 566 |
```unknown
if SOC_SERIES_MT8195_ADSP
config SOC
default "mt8195_adsp"
config SOC_SERIES
default "mt8195_adsp"
config NUM_2ND_LEVEL_AGGREGATORS
default 2
config 2ND_LVL_INTR_00_OFFSET
default 1
config 2ND_LVL_INTR_01_OFFSET
default 23
endif # SOC_SERIES_MT8195_ADSP
``` | /content/code_sandbox/soc/mediatek/mtk_adsp/mt8195_adsp/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```linker script
*/
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
#define SRAM_START DT_REG_ADDR(DT_NODELABEL(sram0))
#define SRAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0))
#define DRAM_START DT_REG_ADDR(DT_NODELABEL(dram0))
#define DRAM_SIZE DT_REG_SIZE(DT_NODELABEL(dram0))
MEMORY {
... | /content/code_sandbox/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 979 |
```unknown
config SOC_RISCV_VIRTUAL_RENODE
bool
help
Renode RISCV32 Virtual system implementation
config SOC
default "riscv_virtual_renode" if SOC_RISCV_VIRTUAL_RENODE
``` | /content/code_sandbox/soc/renode/riscv_virtual/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```yaml
socs:
- name: riscv_virtual_renode
``` | /content/code_sandbox/soc/renode/riscv_virtual/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```objective-c
*/
#ifndef ZEPHYR_SOC_MT8195_ADSP_SOC_H
#define ZEPHYR_SOC_MT8195_ADSP_SOC_H
#include "../soc.h"
#endif /* ZEPHYR_SOC_MT8195_ADSP_SOC_H */
``` | /content/code_sandbox/soc/mediatek/mtk_adsp/mt8195_adsp/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
config SOC_RISCV_VIRTUAL_RENODE
select RISCV
select RISCV_PRIVILEGED
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_HAS_P... | /content/code_sandbox/soc/renode/riscv_virtual/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```unknown
config SOC_XENVM
bool
config SOC
default "xenvm" if SOC_XENVM
``` | /content/code_sandbox/soc/xen/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```yaml
series:
- name: xenvm
socs:
- name: xenvm
``` | /content/code_sandbox/soc/xen/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#include <zephyr/arch/arm64/arm_mmu.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
MT_DEV... | /content/code_sandbox/soc/xen/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 220 |
```unknown
if SOC_XENVM
config NUM_IRQS
int
default 500
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 8320000
# We need at least 16M of virtual address space to map memory of Xen node
# 32M should be enough for basic use-cases
config KERNEL_VM_SIZE
default 0x2000000
endif
``` | /content/code_sandbox/soc/xen/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
config SOC_XENVM
select ARM64
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
select CPU_CORTEX_A72
``` | /content/code_sandbox/soc/xen/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
#
config SOC_FAMILY_ASPEED
bool
config SOC_FAMILY
default "aspeed" if SOC_FAMILY_ASPEED
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/aspeed/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```yaml
family:
- name: aspeed
series:
- name: ast10x0
socs:
- name: ast1030
``` | /content/code_sandbox/soc/aspeed/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
if SOC_RISCV_VIRTUAL_RENODE
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 4000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 1ST_LEVEL_INTERRUPT_BITS
default 4
config NUM_2ND_LEVEL_AGGREGATORS
default 2
config 2ND_LEVEL_INTERRUPT_BITS
default 11
config 2ND_LVL_ISR_T... | /content/code_sandbox/soc/renode/riscv_virtual/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 161 |
```unknown
#
if SOC_FAMILY_ASPEED
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_ASPEED
``` | /content/code_sandbox/soc/aspeed/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
#
config SOC_FAMILY_ASPEED
select PLATFORM_SPECIFIC_INIT
if SOC_FAMILY_ASPEED
rsource "*/Kconfig"
endif # SOC_FAMILY_ASPEED
``` | /content/code_sandbox/soc/aspeed/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
#
config SOC_SERIES_AST10X0
bool
select SOC_FAMILY_ASPEED
help
Enable support for ASPEED AST10X0 series
config SOC_AST1030
bool
select SOC_SERIES_AST10X0
help
AST1030
config SOC_SERIES
default "ast10x0" if SOC_SERIES_AST10X0
config SOC
default "ast1030" if SOC_AST1030
``` | /content/code_sandbox/soc/aspeed/ast10x0/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
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