text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_ASPEED_UTIL_H_
#define ZEPHYR_SOC_ARM_ASPEED_UTIL_H_
#include <zephyr/sys/util.h>
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
/* gcc.h doesn't define __section but checkpatch.pl will complain for this. so
* temporarily add a macro here.
*/
#ifndef __se... | /content/code_sandbox/soc/aspeed/aspeed_util.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 470 |
```linker script
/*
*
*/
.bss_nc (NOLOAD) :
{
__bss_nc_start__ = .;
*(.nocache.bss*)
. = ALIGN(4);
__bss_nc_end__ = .;
} > SRAM_NC
``` | /content/code_sandbox/soc/aspeed/ast10x0/nocache.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```linker script
/*
*
*/
KEEP(*(.sboot))
``` | /content/code_sandbox/soc/aspeed/ast10x0/sboot.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_
#define ZEPHYR_SOC_ARM_ASPEED_AST10X0_SOC_H_
#include <aspeed_util.h>
#define __VTOR_PRESENT 1U
#define __FPU_PRESENT CONFIG_CPU_HAS_FPU
#define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU
#define PHY_SRAM_ADDR 0x80000000UL
#define TO_PHY_ADDR(ad... | /content/code_sandbox/soc/aspeed/ast10x0/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 263 |
```unknown
#
if SOC_SERIES_AST10X0
rsource "Kconfig.defconfig.ast10*0"
config ICACHE_LINE_SIZE
default 32
config DCACHE_LINE_SIZE
default 32
choice CACHE_TYPE
default EXTERNAL_CACHE
endchoice
endif # SOC_SERIES_AST10X0
``` | /content/code_sandbox/soc/aspeed/ast10x0/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
#
config SOC_SERIES_AST10X0
select ARM
select CPU_CORTEX_M4
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SYSCON
select CACHE
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CACHE_MANAGEMENT
select CACHE_ASPEED
if SOC_SERIES_AST10X0
config SRAM_NC_SIZE
int "noncached SRAM Size in kB"
hel... | /content/code_sandbox/soc/aspeed/ast10x0/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 224 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <stdint.h>
#include <string.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/device.h>
#include <zephyr/cache.h>
#include <soc.h>
extern char __bss_nc_start__[];
extern char __bss_nc_end__[];
/* SCU registers */
#define JTAG_PINMUX... | /content/code_sandbox/soc/aspeed/ast10x0/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,340 |
```unknown
#
if SOC_AST1030
config NUM_IRQS
default 240
DT_NODE_SRAM := /memory@0
config SRAM_NC_SIZE
default $(dt_node_reg_size_int,$(DT_NODE_SRAM),1,K)
config SRAM_NC_BASE_ADDRESS
default $(dt_node_reg_addr_hex,$(DT_NODE_SRAM),1)
endif # SOC_AST1030
``` | /content/code_sandbox/soc/aspeed/ast10x0/Kconfig.defconfig.ast1030 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```linker script
/*
*
*/
MEMORY
{
SRAM_NC (wx) : ORIGIN = CONFIG_SRAM_NC_BASE_ADDRESS, LENGTH = CONFIG_SRAM_NC_SIZE * 1024
}
#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
``` | /content/code_sandbox/soc/aspeed/ast10x0/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```python
#!/usr/bin/env python3
#
#
#
import sys
if __name__ == "__main__":
src = sys.argv[1]
dst = sys.argv[2]
with open(src,'rb') as r:
src_image = r.read()
# get src size and round up to 4-byte align
src_len = len(src_image)
src_len_align = (src_len + 3) & (~3)
src_len_byte =... | /content/code_sandbox/soc/aspeed/ast10x0/tools/gen_uart_booting_image.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 143 |
```unknown
#
#
#
config SOC_FAMILY_ROCKCHIP
bool
config SOC_FAMILY
default "rockchip" if SOC_FAMILY_ROCKCHIP
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/rockchip/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```unknown
#
#
#
if SOC_FAMILY_ROCKCHIP
rsource "*/Kconfig.defconfig"
endif
``` | /content/code_sandbox/soc/rockchip/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
family:
- name: rockchip
series:
- name: rk3399
socs:
- name: rk3399
- name: rk3568
socs:
- name: rk3568
``` | /content/code_sandbox/soc/rockchip/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```unknown
#
#
#
if SOC_FAMILY_ROCKCHIP
rsource "*/Kconfig"
endif # SOC_FAMILY_ROCKCHIP
``` | /content/code_sandbox/soc/rockchip/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```unknown
config SOC_SERIES_RK3568
bool
select SOC_FAMILY_ROCKCHIP
config SOC_RK3568
bool
select SOC_SERIES_RK3568
config SOC
default "rk3568" if SOC_RK3568
config SOC_SERIES
default "rk3568" if SOC_RK3568
``` | /content/code_sandbox/soc/rockchip/rk3568/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
if SOC_RK3568
config FLASH_SIZE
default 0
config FLASH_BASE_ADDRESS
default 0
config NUM_IRQS
int
default 240
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 24000000
endif
``` | /content/code_sandbox/soc/rockchip/rk3568/Kconfig.defconfig.rk3568 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#include <zephyr/arch/arm64/arm_mmu.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
MT_DEVICE_... | /content/code_sandbox/soc/rockchip/rk3568/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 206 |
```unknown
if SOC_SERIES_RK3568
rsource "Kconfig.defconfig.rk3568"
endif # SOC_SERIES_RK3568
``` | /content/code_sandbox/soc/rockchip/rk3568/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
#
#
#
config SOC_RK3399
bool
select SOC_SERIES_RK3399
config SOC_SERIES_RK3399
bool
select SOC_FAMILY_ROCKCHIP
config SOC
default "rk3399" if SOC_RK3399
config SOC_SERIES
default "rk3399" if SOC_SERIES_RK3399
``` | /content/code_sandbox/soc/rockchip/rk3399/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
config SOC_SERIES_RK3568
select ARM64
select CPU_CORTEX_A55
select ARM_ARCH_TIMER
config SOC_PART_NUMBER
default "RK3568" if SOC_SERIES_RK3568
``` | /content/code_sandbox/soc/rockchip/rk3568/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
#
#
#
if SOC_RK3399
config NUM_IRQS
int
default 240
config FLASH_SIZE
default 0
config FLASH_BASE_ADDRESS
default 0
endif
``` | /content/code_sandbox/soc/rockchip/rk3399/Kconfig.defconfig.rk3399 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
#
#
#
if SOC_SERIES_RK3399
rsource "Kconfig.defconfig.rk3399"
endif # SOC_SERIES_RK3399
``` | /content/code_sandbox/soc/rockchip/rk3399/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```c
/*
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#include <zephyr/arch/arm64/arm_mmu.h>
static const struct arm_mmu_region mmu_regions[] = {
MMU_REGION_FLAT_ENTRY("GIC",
DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
MT_DEV... | /content/code_sandbox/soc/rockchip/rk3399/mmu_regions.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 224 |
```unknown
#
#
#
config SOC_RK3399
select ARM64
select CPU_CORTEX_A53
select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
config SOC_PART_NUMBER
default "RK3399" if SOC_SERIES_RK3399
``` | /content/code_sandbox/soc/rockchip/rk3399/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
config SOC_FAMILY_ANDES_V5
bool
config SOC_FAMILY
default "andes_v5" if SOC_FAMILY_ANDES_V5
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/andestech/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
if SOC_FAMILY_ANDES_V5
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_ANDES_V5
``` | /content/code_sandbox/soc/andestech/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```yaml
family:
- name: andes_v5
series:
- name: ae350
socs:
- name: ae350
``` | /content/code_sandbox/soc/andestech/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config SOC_SERIES_ANDES_AE350
bool
select SOC_FAMILY_ANDES_V5
help
Andes V5 AE350 SoC Series Implementation"
config SOC_ANDES_AE350
bool
select SOC_SERIES_ANDES_AE350
help
Andes AE350 SoC implementation"
config SOC_SERIES
default "ae350" if SOC_SERIES_ANDES_AE350
config SOC
default "ae350" ... | /content/code_sandbox/soc/andestech/ae350/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
if SOC_FAMILY_ANDES_V5
rsource "*/Kconfig"
endif # SOC_FAMILY_ANDES_V5
``` | /content/code_sandbox/soc/andestech/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```objective-c
/*
*
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
*/
#ifndef SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_
#define SOC_RISCV_ANDES_V5_SOC_OFFSETS_H_
#ifdef CONFIG_RISCV_SOC_OFFSETS
/* Andes V5 specific registers. */
#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDES_V5_HWDSP... | /content/code_sandbox/soc/andestech/ae350/soc_offsets.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 230 |
```unknown
/*
*
*/
#include "soc_v5.h"
#include <zephyr/toolchain.h>
/* exports */
GTEXT(entry)
SECTION_FUNC(init, entry)
/* Disable linker relaxation before GP register initialization. */
.option push
.option norelax
#ifdef CONFIG_SOC_ANDES_V5_EXECIT
/* Initialize EXECIT table */
la t0, _ITB_BASE_
csrw ND... | /content/code_sandbox/soc/andestech/ae350/start.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 418 |
```unknown
/*
*
*/
#include "soc_v5.h"
#include <zephyr/offsets.h>
#include <zephyr/toolchain.h>
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Exports */
GTEXT(__soc_save_context)
GTEXT(__soc_restore_context)
SECTION_FUNC(exception.other, __soc_save_context)
#ifdef CONFIG_SOC_ANDES_V5_PFT
csrr t0, NDS_MXSTATUS
#endi... | /content/code_sandbox/soc/andestech/ae350/soc_irq.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 297 |
```c
/*
*
*/
#include "soc_v5.h"
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/arch/riscv/csr.h>
#ifndef CONFIG_ASSERT
#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(pma_init, ... | /content/code_sandbox/soc/andestech/ae350/pma.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,764 |
```objective-c
/*
*
*/
#ifndef __RISCV_ANDES_V5_SOC_V5_H_
#define __RISCV_ANDES_V5_SOC_V5_H_
/* Control and Status Registers (CSRs) available for Andes V5 SoCs */
#define NDS_MMISC_CTL 0x7D0
#define NDS_MCACHE_CTL 0x7CA
#define NDS_MXSTATUS 0x7C4
#define NDS_MCCTLBEGINAD... | /content/code_sandbox/soc/andestech/ae350/soc_v5.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 543 |
```objective-c
/*
*
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_CONTEXT_SAVE.
*/
#ifndef SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_
#define SOC_RISCV_ANDES_V5_SOC_CONTEXT_H_
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
/* Andes V5 specific registers. */
#if defined(CONFIG_SOC_ANDES_V5_PFT) && defined(CONFIG_SOC_ANDE... | /content/code_sandbox/soc/andestech/ae350/soc_context.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 243 |
```unknown
if SOC_ANDES_AE350
config SYS_CLOCK_TICKS_PER_SEC
default 100 if (!ICACHE || XIP)
config MAIN_STACK_SIZE
default 2048
config IDLE_STACK_SIZE
default 1536
config PRIVILEGED_STACK_SIZE
default 2048 if 64BIT
config TEST_EXTRA_STACK_SIZE
default 2048 if 64BIT
config MP_MAX_NUM_CPUS
default 1
range ... | /content/code_sandbox/soc/andestech/ae350/Kconfig.defconfig.ae350 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```unknown
if SOC_SERIES_ANDES_AE350
# Kconfig picks the first default with a satisfied condition.
# SoC defaults should be parsed before SoC Series defaults, because SoCs usually
# overrides SoC Series values.
rsource "Kconfig.defconfig.ae*"
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 60000000
config KERNEL_ENTRY
... | /content/code_sandbox/soc/andestech/ae350/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 206 |
```unknown
config SOC_SERIES_ANDES_AE350
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
config SOC_ANDES_AE350
select ATOMIC_OPERATIONS_BUILTIN
select INCLUDE_RESET_VECTOR
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CAC... | /content/code_sandbox/soc/andestech/ae350/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 825 |
```linker script
/*
*
*/
. = ALIGN(4);
KEEP(*(.exec.itable))
``` | /content/code_sandbox/soc/andestech/ae350/common_linker/execit.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 17 |
```linker script
/*
*
*/
KEEP(*(.init.*))
``` | /content/code_sandbox/soc/andestech/ae350/common_linker/init.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10 |
```linker script
/*
*
*/
/*
* Workaround for RAM_BASE is zero in XIP system, kernel object
* address maybe zero(NULL) and break some test case assertions.
* ex: tests/kernel/queue, k_queue_get() return k_queue address
* 0x0, but treat as NULL fail.
*/
SECTION_DATA_PROLOGUE(ram_start_nonzero,(NOLOAD),)
{
. = AB... | /content/code_sandbox/soc/andestech/ae350/common_linker/ram_start_nonzero.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 110 |
```unknown
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
config SOC_FAMILY_INFINEON_XMC
bool
config SOC_FAMILY
default "infineon_xmc" if SOC_FAMILY_INFINEON_XMC
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/infineon/cat3/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```yaml
family:
- name: infineon_xmc
series:
- name: xmc4xxx
socs:
- name: xmc4500
- name: xmc4700
``` | /content/code_sandbox/soc/infineon/cat3/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```unknown
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
if SOC_FAMILY_INFINEON_XMC
rsource "*/Kconfig.defconfig"
config PINCTRL
default y
endif # SOC_FAMILY_INFINEON_XMC
``` | /content/code_sandbox/soc/infineon/cat3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
config SOC_FAMILY_INFINEON_XMC
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select PLATFORM_SPECIFIC_INIT
if SOC_FAMILY_INFINEON_XMC
rsource "*/Kconfig"
endif # SOC_FAMILY_INFINEON_XMC
``` | /content/code_sandbox/soc/infineon/cat3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
# XMC 4xxx MCU line
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
config SOC_SERIES_XMC4XXX
bool
select SOC_FAMILY_INFINEON_XMC
help
XMC 4xxx Series MCU
config SOC_XMC4500
bool
select SOC_SERIES_XMC4XXX
help
SOC_XMC4500
config SOC_XMC4700
bool
select SOC_SERIES_XMC4XXX
help
SO... | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 233 |
```linker script
/*
*
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*
* Extracted from: infineon/XMCLib/devices/XMC4500/Source/GCC/XMC4500x1024.ld
*/
/* .no_init section contains chipid, SystemCoreClock and trimming data */
KEEP(*(.no_init))
``` | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/noinit.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
# Infineon XMC4700 relax kit platform configuration options
#
if SOC_XMC4700
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 144000000
config NUM_IRQS
default 112
endif # SOC_XMC4700
``` | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/Kconfig.defconfig.xmc4700 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```c
/*
*
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*
*/
#include <xmc_scu.h>
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc.h>
#ifdef CONFIG_SOC_XMC4500
#define PMU_FLASH_WS (0x3U)
#elif CONFIG_SOC_XMC4700
#define PMU_FLASH_WS (0x4U)
#endif
void z_arm_platform_init(void)
{
ui... | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 315 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_XMC_4XXX_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_XMC_4XXX_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetree.h>
#include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
typedef uint32_t pinctrl_soc_pin_t;
#define Z_PINCTRL_STATE_PIN_INIT(no... | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 434 |
```objective-c
/*
*
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*
*/
#include <xmc_device.h>
``` | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the ae350 platform
*/
#include <zephyr/devicetree.h>
#include <zephyr/linker/sections.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/linker/linker-defs.h>
#include <zephyr/linker/linker-tool.h>
... | /content/code_sandbox/soc/andestech/ae350/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,242 |
```unknown
#
# XMC 4xxx series configuration options
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
if SOC_SERIES_XMC4XXX
config NUM_IRQS
default 112
rsource "Kconfig.defconfig.xmc*"
endif # SOC_SERIES_XMC4XXX
``` | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
# Infineon XMC4500 relax kit platform configuration options
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
if SOC_XMC4500
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 120000000
config NUM_IRQS
default 110
endif # SOC_XMC4500
``` | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/Kconfig.defconfig.xmc4500 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
# XMC 4xxx MCU line
#
# Author: Parthiban Nallathambi <parthiban@linumiz.com>
config SOC_SERIES_XMC4XXX
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select HAS_XMCLIB
select HAS_XMCLIB_UART
select HAS_XMCLIB_FLASH
select HAS_XMCLIB_ERU
selec... | /content/code_sandbox/soc/infineon/cat3/xmc4xxx/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# MPNs definitions
rsource "*/Kconfig.soc"
# Infineon CAT1A devices
# Category definitions
config SOC_FAMILY_INFINEON_CAT1
bool
config SOC_FAMILY_INFINEON_CAT1A
bool
# Family definitions
config SOC_FAMILY_PSOC6
bool
config SOC_FAMILY_PSOC6_LEGACY
... | /content/code_sandbox/soc/infineon/cat1a/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 404 |
```unknown
# PSOC CAT1A Configuration
if SOC_FAMILY_INFINEON_CAT1A
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_INFINEON_CAT1A
``` | /content/code_sandbox/soc/infineon/cat1a/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon CAT1A devices
# Family definitions
config SOC_FAMILY_PSOC6
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select DYNAMIC_INTERRUPTS
select CPU_HAS_FPU
select SOC_FAMILY_INFINEON_CAT1
config SOC_FAMILY_PSOC6_LEGACY
select ARM
se... | /content/code_sandbox/soc/infineon/cat1a/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 466 |
```yaml
family:
- name: cat1a
series:
- name: psoc6
socs:
- name: cy8c6036bzi_f04
- name: cy8c6016bzi_f04
- name: cy8c6116bzi_f54
- name: cy8c6136bzi_f14
- name: cy8c6136bzi_f34
- name: cy8c6137bzi_f14
- name: cy8c6137bzi_f34
- name: cy8c6137bzi_f54
- name: cy8c6117bzi_f34
... | /content/code_sandbox/soc/infineon/cat1a/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,742 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon PSoC6 (legacy) series MCUs
config SOC_CY8C6247_M0
bool
select SOC_SERIES_PSOC6_62
select SOC_FAMILY_PSOC6_LEGACY
select SOC_FAMILY_PSOC6_LEGACY_M0
config SOC_CY8C6247_M4
bool
select SOC_SERIES_PSOC6_62
select SOC_FAMILY_PSOC6_LEGACY
sel... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 347 |
```linker script
/*
* Extracted from:
* ext/hal/cypress/.../devices/psoc6/linker/gcc/cy8c6xx6_cm0plus.ld
*
* Size of sections are calculated in the startup scripts,
* so they don't have to be specified here.
*/
. = ALIGN(8);
KEEP(*(.ram_vectors))
. = ALIGN(4);
KEEP(*(.heap))
. = ALIGN(4);
KEEP(*(.stack))
. = ... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/noinit.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```linker script
/*
* Extracted from:
* ext/hal/cypress/.../devices/psoc6/linker/gcc/cy8c6xx6_cm0plus.ld
*/
KEEP(*(.cy_ramfunc))
``` | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/rwdata.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```objective-c
/*
*
*/
/** @file
* @brief Cypress PSoC-6 MCU family devicetree helper macros
*/
#ifndef _CYPRESS_PSOC6_DT_H_
#define _CYPRESS_PSOC6_DT_H_
#include <zephyr/devicetree.h>
#include <zephyr/irq.h>
/*
* Devicetree macros related to interrupt
*
* The main "API" macro is CY_PSOC6_IRQ_CONFIG. It is a... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/cypress_psoc6_dt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,590 |
```c
/*
*
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/irq.h>
#include "cy_syslib.h"
#include "cy_gpio.h"
#include "cy_scb_uart.h"
#include "cy_syslib.h"
#include "cy_syspm.h"
#include "cy_sysclk.h"
#define CY_CFG_SYSCLK_CLKFAST_ENABLED 1
#define CY_CFG_SYSCL... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,030 |
```objective-c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetr... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,068 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon PSoC6 (Legacy) based MCU default configuration
if SOC_FAMILY_PSOC6_LEGACY
config NUM_IRQS
default 32 if CPU_CORTEX_M0PLUS
default 147 if CPU_CORTEX_M4
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 50000000
# add additional die specific param... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros
*
* This header file is used to specify and describe board-level aspects
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#include "cypress_psoc6_dt.h"
#endif /* !_ASM... | /content/code_sandbox/soc/infineon/cat1a/psoc6_legacy/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 91 |
```linker script
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
. = ALIGN(4);
KEEP(*(.cy_sharedmem))
``` | /content/code_sandbox/soc/infineon/cat1a/common/noinit.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```linker script
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/* Cortex-M0+ application ram image area */
SECTION_PROLOGUE(.ram_m0p_image,(NOLOAD),)
{
. = CONFIG_SOC_PSOC6_CM0P_IMAGE_RAM_SIZE;
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
``` | /content/code_sandbox/soc/infineon/cat1a/common/ram_cm0image.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```linker script
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/* Cortex-M0+ application flash image area */
. = ALIGN(4);
__cy_m0p_code_start = . ;
KEEP(*(.cy_m0p_image))
. = CONFIG_SOC_PSOC6_CM0P_IMAGE_ROM_SIZE;
__cy_m0p_code_end = . ;
``` | /content/code_sandbox/soc/infineon/cat1a/common/rom_cm0image.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```linker script
/*
*/
KEEP(*(.cy_ramfunc))
``` | /content/code_sandbox/soc/infineon/cat1a/common/ram_func.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 10 |
```linker script
/*
*/
__cy_ble_1_start = .;
KEEP(*(i.*))
__cy_ble_1_end = .;
__arm_vfe_header_start = .;
KEEP(*(.arm_vfe_header))
__arm_vfe_header_end = .;
__constdata_start = .;
KEEP(*(.constdata))
__constdata_end = .;
__conststring_start = .;
KEEP(*(.conststring))
__conststring_end = .;
``` | /content/code_sandbox/soc/infineon/cat1a/common/rom.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Infineon PSoC 6 SOC.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysint.h>
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *config, cy_israddress userIsr)
{
CY_ASSERT_L3(C... | /content/code_sandbox/soc/infineon/cat1a/common/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 478 |
```objective-c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Infineon PSoC 6 SOC.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */
``` | /content/code_sandbox/soc/infineon/cat1a/common/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```objective-c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetr... | /content/code_sandbox/soc/infineon/cat1a/common/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,162 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon PSoC6_02 based MCU default configuration
if SOC_DIE_PSOC6_02
config NUM_IRQS
default 16 if CPU_CORTEX_M0PLUS
default 168 if CPU_CORTEX_M4
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
# add additional die specific params
endif # S... | /content/code_sandbox/soc/infineon/cat1a/psoc6_02/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# SOC die
config SOC_DIE_PSOC6_02
bool
# SOC packages
config SOC_PACKAGE_PSOC6_02_124_BGA
bool
config SOC_PACKAGE_PSOC6_02_100_WLCSP
bool
config SOC_PACKAGE_PSOC6_02_128_TQFP
bool
config SOC_PACKAGE_PSOC6_02_68_QFN
bool
# Infineon PSoC6_02 series... | /content/code_sandbox/soc/infineon/cat1a/psoc6_02/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,642 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon PSoC6_03 based MCU default configuration
if SOC_DIE_PSOC6_03
config NUM_IRQS
default 16 if CPU_CORTEX_M0PLUS
default 174 if CPU_CORTEX_M4
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
# add additional die specific params
endif # S... | /content/code_sandbox/soc/infineon/cat1a/psoc6_03/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# SOC die
config SOC_DIE_PSOC6_03
bool
# SOC packages
config SOC_PACKAGE_PSOC6_03_100_TQFP
bool
config SOC_PACKAGE_PSOC6_03_68_QFN
bool
config SOC_PACKAGE_PSOC6_03_49_WLCSP
bool
# Infineon PSoC6_03 series MCUs
config SOC_CY8C6245AZI_S3D72
bool
se... | /content/code_sandbox/soc/infineon/cat1a/psoc6_03/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,197 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon PSoC6_04 based MCU default configuration
if SOC_DIE_PSOC6_04
config NUM_IRQS
default 16 if CPU_CORTEX_M0PLUS
default 175 if CPU_CORTEX_M4
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
# add additional die specific params
endif # S... | /content/code_sandbox/soc/infineon/cat1a/psoc6_04/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# SOC die
config SOC_DIE_PSOC6_04
bool
# SOC packages
config SOC_PACKAGE_PSOC6_04_64_TQFP
bool
config SOC_PACKAGE_PSOC6_04_68_QFN
bool
config SOC_PACKAGE_PSOC6_04_80_TQFP
bool
config SOC_PACKAGE_PSOC6_04_80_M_CSP
bool
# Infineon PSoC6_04 series M... | /content/code_sandbox/soc/infineon/cat1a/psoc6_04/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,911 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon PSoC6_01 based MCU default configuration
if SOC_DIE_PSOC6_01
config NUM_IRQS
default 32 if CPU_CORTEX_M0PLUS
default 147 if CPU_CORTEX_M4
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
# add additional die specific params
endif # S... | /content/code_sandbox/soc/infineon/cat1a/psoc6_01/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Family definitions
config SOC_FAMILY_INFINEON_CAT1
bool
config SOC_FAMILY_INFINEON_CAT1B
bool
select SOC_FAMILY_INFINEON_CAT1
# MPNs definitions
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/infineon/cat1b/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```yaml
family:
- name: cat1b
series:
- name: cyw20829
socs:
- name: cyw20829a0lkml
- name: cyw20829a0kml
- name: cyw89829a0kml
- name: cyw20829b0lkml
- name: cyw20829b0kml
- name: cyw89829b0kml
- name: cyw89829b01mksbg
``` | /content/code_sandbox/soc/infineon/cat1b/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```unknown
# PSOC CAT1B Configuration
if SOC_FAMILY_INFINEON_CAT1B
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_INFINEON_CAT1B
``` | /content/code_sandbox/soc/infineon/cat1b/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
if SOC_FAMILY_INFINEON_CAT1B
rsource "*/Kconfig"
endif # SOC_FAMILY_INFINEON_CAT1B
``` | /content/code_sandbox/soc/infineon/cat1b/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```objective-c
/*
* an affiliate of Cypress Semiconductor Corporation
*
*
*/
/**
* @brief Infineon CAT1 SoC specific helpers for pinctrl driver.
*/
#ifndef ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_INFINEON_CAT1_COMMON_PINCTRL_SOC_H_
#include <stdint.h>
#include <zephyr/devicetr... | /content/code_sandbox/soc/infineon/cat1b/common/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,162 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon CYW20829 series MCUs
# SOC series
config SOC_SERIES_CYW20829
bool
config SOC_SERIES
default "cyw20829" if SOC_SERIES_CYW20829
# SOC die
config SOC_DIE_CYW20829
bool
select SOC_FAMILY_INFINEON_CAT1B
# SOC packages
config SOC_PACKAGE_CYW20... | /content/code_sandbox/soc/infineon/cat1b/cyw20829/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 593 |
```c
* an affiliate of Cypress Semiconductor Corporation
*
*/
#include <zephyr/devicetree.h>
#include <zephyr/toolchain.h>
#include <stdint.h>
struct toc2_data {
uint32_t toc2_size;
uint32_t l1_app_descr_addr;
uint32_t service_app_descr_addr;
uint32_t debug_cert_addr;
} __packed;
struct l1_desc {
uint32_t l1... | /content/code_sandbox/soc/infineon/cat1b/cyw20829/app_header.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 324 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# SOC die
config SOC_DIE_PSOC6_01
bool
# SOC packages
config SOC_PACKAGE_PSOC6_01_124_BGA
bool
config SOC_PACKAGE_PSOC6_01_116_BGA_BLE
bool
config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE
bool
config SOC_PACKAGE_PSOC6_01_80_WLCSP
bool
config SOC_PACKAG... | /content/code_sandbox/soc/infineon/cat1a/psoc6_01/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,933 |
```c
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Infineon CYW920829 soc.
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <cy_sysint.h>
#include <system_cat1b.h>
#include "cy_pdl.h"
cy_en_sysint_status_t Cy_SysInt_Init(const cy_stc_sysint_t *c... | /content/code_sandbox/soc/infineon/cat1b/cyw20829/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 759 |
```objective-c
* an affiliate of Cypress Semiconductor Corporation
*
*/
/**
* @brief Infineon CYW20829 soc.
*/
#ifndef _SOC__H_
#define _SOC__H_
#ifndef _ASMLANGUAGE
#include <cy_device_headers.h>
#endif /* !_ASMLANGUAGE */
#endif /* _SOC__H_ */
``` | /content/code_sandbox/soc/infineon/cat1b/cyw20829/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon CYW20829 based MCU default configuration
if SOC_DIE_CYW20829
config NUM_IRQS
default 70
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 48000000
# add additional die specific params
endif # SOC_DIE_CYW20829
``` | /content/code_sandbox/soc/infineon/cat1b/cyw20829/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
# an affiliate of Cypress Semiconductor Corporation
# Infineon CAT1B devices
# Series definitions
config SOC_SERIES_CYW20829
select ARM
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M33
select CPU_HAS_FPU
select DYNAMIC_INTERRUPTS
``` | /content/code_sandbox/soc/infineon/cat1b/cyw20829/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```linker script
* an affiliate of Cypress Semiconductor Corporation
*
*/
SECTIONS
{
.app_header :
{
KEEP(*(.app_header))
} > APP_HEADER_FLASH
/* Cortex-M33 bootstrap code area */
.bootstrapText :
{
. = ALIGN(4);
__bootstrapText_begin = .;
/* Located in generate... | /content/code_sandbox/soc/infineon/cat1b/cyw20829/bootstrap.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,081 |
```unknown
config SOC_OPENTITAN
bool
config SOC
default "opentitan" if SOC_OPENTITAN
``` | /content/code_sandbox/soc/lowrisc/opentitan/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
socs:
- name: opentitan
``` | /content/code_sandbox/soc/lowrisc/opentitan/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11 |
```c
/*
*
*/
#include <zephyr/arch/cpu.h>
#include <zephyr/devicetree.h>
#include <zephyr/init.h>
/* OpenTitan power management regs. */
#define PWRMGR_BASE (DT_REG_ADDR(DT_NODELABEL(pwrmgr)))
#define PWRMGR_CFG_CDC_SYNC_REG_OFFSET 0x018
#define PWRMGR_RESET_EN_REG_OFFSET 0x02c
#define PWRMGR_RESET_EN_WDOG_SR... | /content/code_sandbox/soc/lowrisc/opentitan/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 442 |
```linker script
/*
*
*/
KEEP(*(.rom_header.*))
``` | /content/code_sandbox/soc/lowrisc/opentitan/rom_header.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11 |
```unknown
/*
*
*/
#include <zephyr/toolchain.h>
/* exports */
GTEXT(__rom_header)
/* OpenTitan manifest consists of 1024 bytes (256 words) of manifest
* containing signature, device ID, version info, etc. The test ROM
* ignores all of these fields except for entry point.
*
* The layout below conforms to manif... | /content/code_sandbox/soc/lowrisc/opentitan/rom_header.S | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 183 |
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