text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163
values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751
values | repo_full_name stringclasses 752
values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
if SOC_OPENTITAN
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 1000000
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 32
config 2ND_LVL_INTR_00_OFFSET
default 11
config NUM_IRQS
default 256
endif # SOC_OPENTITAN
``` | /content/code_sandbox/soc/lowrisc/opentitan/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```unknown
config SOC_OPENTITAN
select ATOMIC_OPERATIONS_C
select INCLUDE_RESET_VECTOR
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_ISA_EXT_ZBA
select RISCV_ISA_EXT_ZBB
select RISCV_ISA_EXT_ZBC
select RISCV_ISA_EXT... | /content/code_sandbox/soc/lowrisc/opentitan/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 169 |
```unknown
config SOC_KB1200
bool
help
ENE KB1200
config SOC
default "kb1200" if SOC_KB1200
``` | /content/code_sandbox/soc/ene/kb1200/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
socs:
- name: kb1200
``` | /content/code_sandbox/soc/ene/kb1200/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 11 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <reg/pmu.h>
#include <reg/gcfg.h>
#define PMU_BASE DT_REG_ADDR(DT_NODELABEL(pmu))
#define GCFG_BASE DT_REG_ADDR(DT_NODELABEL(gcfg))
static void pmu_init(void)
{
struct pmu_regs *pmu = ((struct pmu_regs *)PMU_BASE);
/* Interrupt Event ... | /content/code_sandbox/soc/ene/kb1200/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 390 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_KB1200_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_KB1200_PINCTRL_SOC_H_
#include <zephyr/dt-bindings/pinctrl/ene-kb1200-pinctrl.h>
#ifdef __cplusplus
extern "C" {
#endif
/** @cond INTERNAL_HIDDEN */
typedef uint32_t pinctrl_soc_pin_t;
/* initialize pinmux member fields o... | /content/code_sandbox/soc/ene/kb1200/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 545 |
```objective-c
/*
*
*/
#ifndef _KB1200_SOC_H_
#define _KB1200_SOC_H_
#include <cmsis_core_m_defaults.h>
#endif /* _KB1200_SOC_H_ */
``` | /content/code_sandbox/soc/ene/kb1200/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
if SOC_KB1200
config NUM_IRQS
default 64
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config BUILD_OUTPUT_BIN
default y
config BUILD_OUTPUT_HEX
default y
endif # SOC_KB1200
``` | /content/code_sandbox/soc/ene/kb1200/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config SOC_KB1200
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
``` | /content/code_sandbox/soc/ene/kb1200/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```linker script
/*
*
*/
/**
* @file
* @brief Linker command/script file
*
* Linker script for the Cortex-M platforms.
*/
#include <zephyr/linker/sections.h>
#include <zephyr/devicetree.h>
#include <zephyr/toolchain/common.h>
#include <zephyr/linker/devicetree_regions.h>
#include <zephyr/linker/linker-defs.h>... | /content/code_sandbox/soc/infineon/cat1b/cyw20829/linker.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,358 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_GPIO_H
#define ENE_KB1200_GPIO_H
/**
* Structure type to access General Purpose Input/Output (GPIO).
*/
struct gpio_regs {
volatile uint32_t GPIOFS; /*Function Selection Register */
volatile uint32_t Reserved1[3];
volatile uint32_t GPIOOE; /*Output Enable Register */
... | /content/code_sandbox/soc/ene/kb1200/reg/gpio.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 500 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_ADC_H
#define ENE_KB1200_ADC_H
/**
* Structure type to access Analog to Digital Converter (ADC).
*/
struct adc_regs {
volatile uint32_t ADCCFG; /* Configuration Register */
volatile uint32_t Reserved[3]; /* Reserved */
volatile uint32_t ADCDAT[14];... | /content/code_sandbox/soc/ene/kb1200/reg/adc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 191 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_GCFG_H
#define ENE_KB1200_GCFG_H
/**
* Structure type to access General Configuration (GCFG).
*/
struct gcfg_regs {
volatile uint8_t IDV; /*Version ID Register */
volatile uint8_t Reserved0; /*Reserved */
volatile uint16_t IDC; /*Chip ID Regi... | /content/code_sandbox/soc/ene/kb1200/reg/gcfg.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 550 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_WDT_H
#define ENE_KB1200_WDT_H
/**
* brief Structure type to access Watch Dog Timer (WDT).
*/
struct wdt_regs {
volatile uint8_t WDTCFG; /*Configuration Register */
volatile uint8_t WDTCFG_T; /*Configuration Reset Type Register */
volatile uint16_t Reser... | /content/code_sandbox/soc/ene/kb1200/reg/wdt.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 340 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_PWM_H
#define ENE_KB1200_PWM_H
/**
* Structure type to access Pulse Width Modulation (PWM).
*/
struct pwm_regs {
volatile uint16_t PWMCFG; /*Configuration Register */
volatile uint16_t Reserved0; /*Reserved */
volatile uint16_t PWMHIGH; /*High Length R... | /content/code_sandbox/soc/ene/kb1200/reg/pwm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 294 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_PMU_H
#define ENE_KB1200_PMU_H
/**
* Structure type to access Power Management Unit (PMU).
*/
struct pmu_regs {
volatile uint8_t PMUIDLE; /*IDLE wakeup by Interrupt Register */
volatile uint8_t Reserved0[3]; /*Reserved */
volatile uint32_t PMUSTOP; /*STOP Wak... | /content/code_sandbox/soc/ene/kb1200/reg/pmu.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 469 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_FSMBM_H
#define ENE_KB1200_FSMBM_H
/**
* Structure type to access Flexible SMBus Master (FSMBM).
*/
struct fsmbm_regs {
volatile uint32_t FSMBMCFG; /* Configuration Register */
volatile uint8_t FSMBMIE; /* Interrupt Enable Register */
volatile uint8_t Rese... | /content/code_sandbox/soc/ene/kb1200/reg/fsmbm.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,287 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_GPTD_H
#define ENE_KB1200_GPTD_H
/**
* Structure type to access GPIO Trigger Detector (GPTD).
*/
struct gptd_regs {
volatile uint32_t GPTDIE; /*Interrupt Enable Register */
volatile uint32_t Reserved1[3];
volatile uint32_t GPTDPF; /*Event Pending Flag Register */
vo... | /content/code_sandbox/soc/ene/kb1200/reg/gptd.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 208 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_TACHO_H
#define ENE_KB1200_TACHO_H
/**
* brief Structure type to access TACHO.
*/
struct tacho_regs {
volatile uint16_t TACHOCFG; /*Configuration Register */
volatile uint16_t Reserved0; /*Reserved */
volatile uint8_t TACHOIE; /*Interrupt Enable Registe... | /content/code_sandbox/soc/ene/kb1200/reg/tacho.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 319 |
```unknown
config SOC_FAMILY_SIFIVE_FREEDOM
bool
config SOC_FAMILY
default "sifive_freedom" if SOC_FAMILY_SIFIVE_FREEDOM
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/sifive/sifive_freedom/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```yaml
family:
- name: sifive_freedom
series:
- name: fe300
socs:
- name: fe310
- name: fu500
socs:
- name: fu540
- name: fu700
socs:
- name: fu740
``` | /content/code_sandbox/soc/sifive/sifive_freedom/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```objective-c
/*
*
*/
#ifndef ENE_KB1200_SER_H
#define ENE_KB1200_SER_H
/**
* Structure type to access Serial Port Interface (SER).
*/
struct serial_regs {
volatile uint32_t SERCFG; /*Configuration Register */
volatile uint32_t SERIE; /*Interrupt Enable Register */
volatile uint32_t SERPF; /*Pending fla... | /content/code_sandbox/soc/ene/kb1200/reg/ser.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 447 |
```unknown
if SOC_FAMILY_SIFIVE_FREEDOM
rsource "*/Kconfig"
endif # SOC_FAMILY_SIFIVE_FREEDOM
``` | /content/code_sandbox/soc/sifive/sifive_freedom/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
if SOC_FAMILY_SIFIVE_FREEDOM
rsource "*/Kconfig.defconfig"
endif # SOC_FAMILY_SIFIVE_FREEDOM
``` | /content/code_sandbox/soc/sifive/sifive_freedom/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config SOC_SERIES_SIFIVE_FREEDOM_FU500
bool
select SOC_FAMILY_SIFIVE_FREEDOM
config SOC_SERIES
default "fu500" if SOC_SERIES_SIFIVE_FREEDOM_FU500
config SOC_SIFIVE_FREEDOM_FU540
bool
select SOC_SERIES_SIFIVE_FREEDOM_FU500
config SOC
default "fu540" if SOC_SIFIVE_FREEDOM_FU540
``` | /content/code_sandbox/soc/sifive/sifive_freedom/fu500/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the SiFive Freedom processor
*/
#ifndef __RISCV_SIFIVE_FREEDOM_U500_SOC_H_
#define __RISCV_SIFIVE_FREEDOM_U500_SOC_H_
/*
* On FE310 and FU540, peripherals such as SPI, UART, I2C and PWM are clocked
* by TLCLK, which is derived from CORECLK.
*/
#d... | /content/code_sandbox/soc/sifive/sifive_freedom/fu500/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 192 |
```objective-c
/*
*
*/
#ifndef _SIFIVE_FU540_PRCI_H
#define _SIFIVE_FU540_PRCI_H
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10000000UL
#define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
/* Register offsets */
#define PRCI_HFXOSCCFG (... | /content/code_sandbox/soc/sifive/sifive_freedom/fu500/prci.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 465 |
```unknown
if SOC_SERIES_SIFIVE_FREEDOM_FU500
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 52
config NUM_IRQS
def... | /content/code_sandbox/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```unknown
config SOC_SERIES_SIFIVE_FREEDOM_FU500
bool
# RISC-V options
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select 64BIT
select INCL... | /content/code_sandbox/soc/sifive/sifive_freedom/fu500/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_SIFIVE_FREEDOM_PINCTRL_H_
#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_SIFIVE_FREEDOM_PINCTRL_H_
#include <zephyr/types.h>
typedef struct pinctrl_soc_pin_t {
uint8_t pin;
uint8_t iof;
} pinctrl_soc_pin_t;
#define SIFIVE_DT_PIN(node_id) \
{ ... | /content/code_sandbox/soc/sifive/sifive_freedom/common/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#include "prci.h"
BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
"Unsupported CORECLK frequency");
BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 2,
"Unsupported TLCLK divider");
... | /content/code_sandbox/soc/sifive/sifive_freedom/fu500/clock.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 359 |
```unknown
config SOC_SERIES_SIFIVE_FREEDOM_FU700
bool
select SOC_FAMILY_SIFIVE_FREEDOM
config SOC_SERIES
default "fu700" if SOC_SERIES_SIFIVE_FREEDOM_FU700
config SOC_SIFIVE_FREEDOM_FU740
bool
select SOC_SERIES_SIFIVE_FREEDOM_FU700
config SOC
default "fu740" if SOC_SIFIVE_FREEDOM_FU740
``` | /content/code_sandbox/soc/sifive/sifive_freedom/fu700/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the SiFive Freedom processor
*/
#ifndef __RISCV_SIFIVE_FREEDOM_U700_SOC_H_
#define __RISCV_SIFIVE_FREEDOM_U700_SOC_H_
/* On FU740, peripherals are clocked by PCLK. */
#define SIFIVE_PERIPHERAL_CLOCK_FREQUENCY \
DT_PROP(DT_NODELABEL(pclk), clock_fre... | /content/code_sandbox/soc/sifive/sifive_freedom/fu700/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```unknown
if SOC_SERIES_SIFIVE_FREEDOM_FU700
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 52
config NUM_IRQS
def... | /content/code_sandbox/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```unknown
config SOC_SERIES_SIFIVE_FREEDOM_FU700
bool
# RISC-V options
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select INCLUDE_RESET_VECT... | /content/code_sandbox/soc/sifive/sifive_freedom/fu700/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 117 |
```objective-c
/*
*
*/
#ifndef _SIFIVE_FU740_PRCI_H
#define _SIFIVE_FU740_PRCI_H
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10000000UL
#define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
/* Register offsets */
#define PRCI_HFXOSCCFG (... | /content/code_sandbox/soc/sifive/sifive_freedom/fu700/prci.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 887 |
```unknown
config SOC_SERIES_SIFIVE_FREEDOM_FE300
bool
select SOC_FAMILY_SIFIVE_FREEDOM
config SOC_SERIES
default "fe300" if SOC_SERIES_SIFIVE_FREEDOM_FE300
config SOC_SIFIVE_FREEDOM_FE310
bool
select SOC_SERIES_SIFIVE_FREEDOM_FE300
config SOC
default "fe310" if SOC_SIFIVE_FREEDOM_FE310
``` | /content/code_sandbox/soc/sifive/sifive_freedom/fe300/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/sys/util.h>
#include "prci.h"
BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
"Unsupported CORECLK frequency");
BUILD_ASSERT(KHZ(125125) == DT_PROP(DT_NODELABEL(pclk), clock_frequency),
"Unsupported P... | /content/code_sandbox/soc/sifive/sifive_freedom/fu700/clock.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,086 |
```objective-c
/*
*
*/
#ifndef _SIFIVE_PRCI_H
#define _SIFIVE_PRCI_H
/* Clock controller. */
#define PRCI_BASE_ADDR 0x10008000UL
#define Z_REG32(p, i) (*(volatile uint32_t *) ((p) + (i)))
#define PRCI_REG(offset) Z_REG32(PRCI_BASE_ADDR, offset)
/* Register offsets */
#define PRCI_HFROSCCFG (0x0000)
#define PRC... | /content/code_sandbox/soc/sifive/sifive_freedom/fe300/prci.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 729 |
```unknown
if SOC_SERIES_SIFIVE_FREEDOM_FE300
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_GP
default y
config 2ND_LVL_ISR_TBL_OFFSET
default 12
config 2ND_LVL_INTR_00_OFFSET
default 11
config MAX_IRQ_PER_AGGREGATOR
default 52
config NUM_IRQS
def... | /content/code_sandbox/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```objective-c
/*
*
*/
/**
* @file SoC configuration macros for the SiFive Freedom processor
*/
#ifndef __RISCV_SIFIVE_FREEDOM_FE300_SOC_H_
#define __RISCV_SIFIVE_FREEDOM_FE300_SOC_H_
/*
* On FE310 and FU540, peripherals such as SPI, UART, I2C and PWM are clocked
* by TLCLK, which is derived from CORECLK.
*/
... | /content/code_sandbox/soc/sifive/sifive_freedom/fe300/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 192 |
```unknown
config SOC_SERIES_SIFIVE_FREEDOM_FE300
bool
# RISC-V options
select RISCV
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_PMP
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select... | /content/code_sandbox/soc/sifive/sifive_freedom/fe300/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```unknown
#
config SOC_FAMILY_AMBIQ
bool
config SOC_FAMILY
default "ambiq" if SOC_FAMILY_AMBIQ
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/ambiq/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
family:
- name: ambiq
series:
- name: apollo4x
socs:
- name: apollo4p
- name: apollo4p_blue
- name: apollo3x
socs:
- name: apollo3_blue
- name: apollo3p_blue
``` | /content/code_sandbox/soc/ambiq/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include "prci.h"
#define CORECLK_HZ (DT_PROP(DT_NODELABEL(coreclk), clock_frequency))
BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 1,
"Unsupported TLCLK divider");
static int fe310_clock_init(void)
{
/*
* HFXOSC (16 MHz) is used ... | /content/code_sandbox/soc/sifive/sifive_freedom/fe300/clock.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 566 |
```unknown
#
if SOC_FAMILY_AMBIQ
rsource "*/Kconfig"
endif # SOC_FAMILY_AMBIQ
``` | /content/code_sandbox/soc/ambiq/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```unknown
#
if SOC_FAMILY_AMBIQ
rsource "*/Kconfig.defconfig"
config CORTEX_M_SYSTICK
default n if AMBIQ_STIMER_TIMER
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768 if AMBIQ_STIMER_TIMER
config SYS_CLOCK_TICKS_PER_SEC
default 1024
endif # SOC_FAMILY_AMBIQ
``` | /content/code_sandbox/soc/ambiq/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
#
config SOC_SERIES_APOLLO3X
bool
select SOC_FAMILY_AMBIQ
help
Apollo3 Series MCU
config SOC_APOLLO3P_BLUE
bool
select SOC_SERIES_APOLLO3X
help
Apollo3P Blue
config SOC_APOLLO3_BLUE
bool
select SOC_SERIES_APOLLO3X
help
Apollo3 Blue
config SOC_SERIES
default "apollo3x" if SOC_SERIES_APO... | /content/code_sandbox/soc/ambiq/apollo3x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
#
if SOC_APOLLO3_BLUE
config NUM_IRQS
default 31
config MAIN_STACK_SIZE
default 2048 if BT
if BT
config BT_BUF_ACL_TX_COUNT
default 4
config BT_BUF_CMD_TX_SIZE
default $(UINT8_MAX)
config BT_BUF_EVT_RX_SIZE
default $(UINT8_MAX)
config BT_BUF_ACL_TX_SIZE
default 251
config BT_BUF_ACL_RX_SIZE
d... | /content/code_sandbox/soc/ambiq/apollo3x/Kconfig.defconfig.apollo3_blue | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 165 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <am_mcu_apollo.h>
static int arm_apollo3_init(void)
{
/* Set the clock frequency. */
am_hal_clkgen_control(AM_HAL_CLKGEN_CONTROL_SYSCLK_MAX, 0);
/* Enable Flash cache.*/
am_hal_cachectrl_config(&am_hal_cachectrl_defaults);
am_hal_cachectrl_enable();
/* Initial... | /content/code_sandbox/soc/ambiq/apollo3x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```objective-c
/*
*
*/
#ifndef __SOC_H__
#define __SOC_H__
#if defined(CONFIG_SOC_APOLLO3P_BLUE)
#include <apollo3p.h>
#elif defined(CONFIG_SOC_APOLLO3_BLUE)
#include <apollo3.h>
#endif
#endif /* __SOC_H__ */
``` | /content/code_sandbox/soc/ambiq/apollo3x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
#
if SOC_SERIES_APOLLO3X
rsource "Kconfig.defconfig.apollo3*"
# Need to enlarge the IDLE stack size because the power
# management operations are executed in the idle task
config IDLE_STACK_SIZE
default 2048 if PM
endif # SOC_SERIES_APOLLO3X
``` | /content/code_sandbox/soc/ambiq/apollo3x/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
#
config SOC_SERIES_APOLLO3X
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_SWO
select AMBIQ_HAL
select HAS_PM
``` | /content/code_sandbox/soc/ambiq/apollo3x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_AMBIQ_APOLLO3_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_AMBIQ_APOLLO3_PINCTRL_SOC_H_
#include <zephyr/dt-bindings/pinctrl/ambiq-apollo3-pinctrl.h>
/**
* @brief Type to hold a pin's pinctrl configuration.
*/
struct apollo3_pinctrl_soc_pin {
/** Pin number 0..74 */
uint3... | /content/code_sandbox/soc/ambiq/apollo3x/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 813 |
```unknown
#
if SOC_APOLLO3P_BLUE
config NUM_IRQS
default 33
config MAIN_STACK_SIZE
default 2048 if BT
if BT
config BT_BUF_ACL_TX_COUNT
default 4
config BT_BUF_CMD_TX_SIZE
default $(UINT8_MAX)
config BT_BUF_EVT_RX_SIZE
default $(UINT8_MAX)
config BT_BUF_ACL_TX_SIZE
default 251
config BT_BUF_ACL_RX_SIZE
... | /content/code_sandbox/soc/ambiq/apollo3x/Kconfig.defconfig.apollo3p_blue | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 167 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/pm.h>
#include <zephyr/init.h>
/* ambiq-sdk includes */
#include <am_mcu_apollo.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
void pm_state_set(enu... | /content/code_sandbox/soc/ambiq/apollo3x/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 766 |
```linker script
/*
*
*/
#if CONFIG_DT_HAS_AMBIQ_MSPI_CONTROLLER_ENABLED
SECTION_PROLOGUE (mspi_buff, CONFIG_SRAM_BASE_ADDRESS + CONFIG_MSPI_AMBIQ_BUFF_RAM_LOCATION (NOLOAD),)
{
__mspi_buff_start = .;
KEEP(*(SORT_BY_NAME(".mspi_buff*")))
. = ALIGN(CONFIG_MSPI_AMBIQ_BUFF_ALIGNMENT);
... | /content/code_sandbox/soc/ambiq/apollo3x/shared_ram.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
#
if SOC_APOLLO4P
config NUM_IRQS
default 83
endif # SOC_APOLLO4P
``` | /content/code_sandbox/soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
#
config SOC_SERIES_APOLLO4X
bool
select SOC_FAMILY_AMBIQ
help
Apollo4 Series MCU
config SOC_APOLLO4P
bool
select SOC_SERIES_APOLLO4X
help
Apollo4P
config SOC_APOLLO4P_BLUE
bool
select SOC_SERIES_APOLLO4X
help
Apollo4 Blue Plus
config SOC_SERIES
default "apollo4x" if SOC_SERIES_APOLLO4... | /content/code_sandbox/soc/ambiq/apollo4x/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <am_mcu_apollo.h>
static int arm_apollo4_init(void)
{
/* Initialize for low power in the power control block */
am_hal_pwrctrl_low_power_init();
/* Enable SIMOBUCK for the Apollo4 Family */
am_hal_pwrctrl_control(AM_HAL_PWRCTRL_CONTROL_SIMOBUCK_INIT, 0);
/* Di... | /content/code_sandbox/soc/ambiq/apollo4x/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 129 |
```objective-c
/*
*
*/
#ifndef __SOC_H__
#define __SOC_H__
#include <apollo4p.h>
#endif /* __SOC_H__ */
``` | /content/code_sandbox/soc/ambiq/apollo4x/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```unknown
#
if SOC_SERIES_APOLLO4X
rsource "Kconfig.defconfig.apollo4*"
# Need to enlarge the IDLE stack size because the power
# management operations are executed in the idle task
config IDLE_STACK_SIZE
default 2048 if PM
endif # SOC_SERIES_APOLLO4X
``` | /content/code_sandbox/soc/ambiq/apollo4x/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
#
config SOC_SERIES_APOLLO4X
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select HAS_SWO
select AMBIQ_HAL
select HAS_PM
``` | /content/code_sandbox/soc/ambiq/apollo4x/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_AMBIQ_APOLLO4_PINCTRL_SOC_H_
#define ZEPHYR_SOC_ARM_AMBIQ_APOLLO4_PINCTRL_SOC_H_
#include <zephyr/dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
/**
* @brief Type to hold a pin's pinctrl configuration.
*/
struct apollo4_pinctrl_soc_pin {
/** Pin number 0..128 */
uint... | /content/code_sandbox/soc/ambiq/apollo4x/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 812 |
```unknown
#
if SOC_APOLLO4P_BLUE
config NUM_IRQS
default 83
endif # SOC_APOLLO4P_BLUE
``` | /content/code_sandbox/soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
config SOC_EOS_S3
bool
help
QuickLogic EOS S3 SoC
config SOC
default "quicklogic_eos_s3" if SOC_EOS_S3
``` | /content/code_sandbox/soc/quicklogic/eos_s3/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```objective-c
/*
*
*/
#ifndef _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_
#define _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_
#include <soc.h>
#endif /* _QUICKLOGIC_EOS_S3_SOC_PINMAP_H_ */
``` | /content/code_sandbox/soc/quicklogic/eos_s3/soc_pinmap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```yaml
socs:
- name: quicklogic_eos_s3
``` | /content/code_sandbox/soc/quicklogic/eos_s3/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```c
/*
*
*/
#include <soc.h>
#include <zephyr/drivers/interrupt_controller/gic.h>
#include <zephyr/kernel.h>
#include <zephyr/logging/log.h>
#include <zephyr/pm/pm.h>
#include <zephyr/init.h>
/* ambiq-sdk includes */
#include <am_mcu_apollo.h>
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
void pm_state_set(enu... | /content/code_sandbox/soc/ambiq/apollo4x/power.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 772 |
```c
/*
*
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <soc.h>
#include <soc_pinmap.h>
#include <cmsis_core.h>
void eos_s3_lock_enable(void)
{
MISC_CTRL->LOCK_KEY_CTRL = MISC_LOCK_KEY;
}
void eos_s3_lock_disable(void)
{
MISC_CTRL->LOCK_KEY_CTRL = 1;
}
static void eos_s3_cru_init(void)
{
/* S... | /content/code_sandbox/soc/quicklogic/eos_s3/soc.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 464 |
```objective-c
/*
*
*/
#ifndef ZEPHYR_SOC_ARM_QUICKLOGIC_EOS_S3_PINCTRL_H_
#define ZEPHYR_SOC_ARM_QUICKLOGIC_EOS_S3_PINCTRL_H_
#include <zephyr/types.h>
#ifdef __cplusplus
extern "C" {
#endif
typedef struct pinctrl_soc_pin_t {
uint32_t pin;
uint32_t iof;
uint32_t input_enable: 1;
uint32_t output_enable: 1;
u... | /content/code_sandbox/soc/quicklogic/eos_s3/pinctrl_soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 491 |
```unknown
if SOC_EOS_S3
config NUM_IRQS
default 52
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 61440000
if SERIAL
config UART_INTERRUPT_DRIVEN
default y
endif # SERIAL
endif # SOC_EOS_S3
``` | /content/code_sandbox/soc/quicklogic/eos_s3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
config SOC_EOS_S3
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_SYSTICK
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select EOS_S3_HAL
``` | /content/code_sandbox/soc/quicklogic/eos_s3/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```objective-c
/*
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#include <eoss3_dev.h>
/* Available frequencies */
#define HSOSC_1MHZ 1024000
#define HSOSC_2MHZ (2*HSOSC_1MHZ)
#define HSOSC_3MHZ (3*HSOSC_1MHZ)
#define HSOSC_4MHZ (4*HSOSC_1MHZ)
#define HSOSC_5MHZ (5*HSOSC_1MHZ)
#define HSOSC_6... | /content/code_sandbox/soc/quicklogic/eos_s3/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 678 |
```unknown
config SOC_FAMILY
default "silabs_s0" if SOC_FAMILY_SILABS_S0
default "silabs_s1" if SOC_FAMILY_SILABS_S1
default "silabs_s2" if SOC_FAMILY_SILABS_S2
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/silabs/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
rsource "*/*/Kconfig.defconfig"
if SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2
config SOC_GECKO_EMU
default y
select SOC_GECKO_CORE
depends on PM
config CORTEX_M_SYSTICK
default n if GECKO_BURTC_TIMER
# With sl_power_manager, pm_state_set()'s stack footrpting is noticeably
#... | /content/code_sandbox/soc/silabs/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```yaml
family:
- name: silabs_s0
series:
- name: efm32wg
socs:
- name: efm32wg990f256
- name: efm32hg
socs:
- name: efm32hg322f64
- name: silabs_s1
series:
- name: efm32pg1b
socs:
- name: efm32pg1b200f256gm48
- name: efr32fg1p
... | /content/code_sandbox/soc/silabs/soc.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 582 |
```unknown
config SOC_FAMILY_SILABS_S1
bool
rsource "*/Kconfig.soc"
``` | /content/code_sandbox/soc/silabs/silabs_s1/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
#
config SOC_FAMILY_SILABS_S1
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
select BUILD_OUTPUT_HEX
if SOC_FAMILY_SILABS_S1
rsource "*/Kconfig"
endif # SOC_FAMILY_SILABS_S1
``` | /content/code_sandbox/soc/silabs/silabs_s1/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 57 |
```unknown
# EFM32PG1B (Pearl Gecko) MCU line
config SOC_SERIES_EFM32PG1B
bool
select SOC_FAMILY_SILABS_S1
help
EFM32PG1B Series MCU
config SOC_PART_NUMBER_EFM32PG1B200F256GM48
bool
select SOC_SERIES_EFM32PG1B
config SOC_SERIES
default "efm32pg1b" if SOC_SERIES_EFM32PG1B
config SOC
default "efm32pg1b200f... | /content/code_sandbox/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 172 |
```objective-c
/*
*/
/** @file
* @brief Silabs EFM32PG1B MCU pin definitions.
*
* This file contains pin configuration data required by different MCU
* modules to correctly configure GPIO controller.
*/
#ifndef _SILABS_EFM32PG1B_SOC_PINMAP_H_
#define _SILABS_EFM32PG1B_SOC_PINMAP_H_
#include <zephyr/devicetree.... | /content/code_sandbox/soc/silabs/silabs_s1/efm32pg1b/soc_pinmap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 301 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the efm32pg1b soc
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_bus.h>
#include <em_common.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
#endif /* !_ASMLANGUAGE *... | /content/code_sandbox/soc/silabs/silabs_s1/efm32pg1b/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
# EFM32PG1B series configuration options
if SOC_SERIES_EFM32PG1B
config NUM_IRQS
# must be >= the highest interrupt number used
default 34
endif # SOC_SERIES_EFM32PG1B
``` | /content/code_sandbox/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
# EFM32PG1B (Pearl Gecko) MCU line
config SOC_SERIES_EFM32PG1B
select ARM
select HAS_SILABS_GECKO
select HAS_SWO
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_HAS_HFRCO_FREQRANGE
select SOC_... | /content/code_sandbox/soc/silabs/silabs_s1/efm32pg1b/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```unknown
# EFM32JG12B (Jade Gecko) MCU line
config SOC_SERIES_EFM32JG12B
bool
select SOC_FAMILY_SILABS_S1
help
EFM32JG12B Series MCU
config SOC_PART_NUMBER_EFM32JG12B500F1024GL125
bool
select SOC_SERIES_EFM32JG12B
config SOC_SERIES
default "efm32jg12b" if SOC_SERIES_EFM32JG12B
config SOC
default "efm32... | /content/code_sandbox/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 188 |
```objective-c
/*
*/
/** @file
* @brief Silabs EFM32JG12B MCU pin definitions.
*
* This file contains pin configuration data required by different MCU
* modules to correctly configure GPIO controller.
*/
#ifndef _SILABS_EFM32JG12B_SOC_PINMAP_H_
#define _SILABS_EFM32JG12B_SOC_PINMAP_H_
#include <zephyr/devicetr... | /content/code_sandbox/soc/silabs/silabs_s1/efm32jg12b/soc_pinmap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 305 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the efm32jg12b soc
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_bus.h>
#include <em_common.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
#endif /* !_ASMLANGUAGE ... | /content/code_sandbox/soc/silabs/silabs_s1/efm32jg12b/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
# EFM32JG12B series configuration options
if SOC_SERIES_EFM32JG12B
config NUM_IRQS
# must be >= the highest interrupt number used
default 50
endif # SOC_SERIES_EFM32JG12B
``` | /content/code_sandbox/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
# EFM32JG12B (Jade Gecko) MCU line
config SOC_SERIES_EFM32JG12B
select ARM
select HAS_SILABS_GECKO
select HAS_SWO
select CPU_CORTEX_M3
select CPU_HAS_ARM_MPU
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_HAS_HFRCO_FREQRANGE
select SOC_GECKO_CMU
select SOC_GECKO_EMU
select SOC_GECK... | /content/code_sandbox/soc/silabs/silabs_s1/efm32jg12b/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 145 |
```unknown
# EFR32FG13P (Flex Gecko) MCU line
config SOC_SERIES_EFR32FG13P
bool
select SOC_FAMILY_SILABS_S1
help
EFR32FG13P Series MCU
config SOC_PART_NUMBER_EFR32FG13P233F512GM48
bool
select SOC_SERIES_EFR32FG13P
config SOC_SERIES
default "efr32fg13p" if SOC_SERIES_EFR32FG13P
config SOC
default "efr32fg... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```unknown
if SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2
rsource "*/Kconfig"
config SOC_GECKO_SDID
int
help
Gecko SDK sometime refere to the chipset using the internal ID. This
entry reflects this ID.
config SOC_GECKO_BURTC
bool
help
Set if the Back-Up Real Time Counter (BURTC... | /content/code_sandbox/soc/silabs/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,231 |
```objective-c
/*
*/
/** @file
* @brief Silabs EFR32FG13P MCU pin definitions.
*
* This file contains pin configuration data required by different MCU
* modules to correctly configure GPIO controller.
*/
#ifndef _SILABS_EFR32FG13P_SOC_PINMAP_H_
#define _SILABS_EFR32FG13P_SOC_PINMAP_H_
#include <zephyr/devicetr... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg13p/soc_pinmap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 301 |
```unknown
# EFR32FG13P series configuration options
if SOC_SERIES_EFR32FG13P
config NUM_IRQS
# must be >= the highest interrupt number used
default 45
endif # SOC_SERIES_EFR32FG13P
``` | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the efr32fg13p soc
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_bus.h>
#include <em_common.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
#endif /* !_ASMLANGUAGE ... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg13p/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
# EFR32FG13P (Flex Gecko) MCU line
config SOC_SERIES_EFR32FG13P
select ARM
select HAS_SILABS_GECKO
select HAS_SWO
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select CPU_HAS_ARM_MPU
select SOC_GECKO_HAS_RADIO
select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
select SOC_GECKO_HAS... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg13p/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 161 |
```unknown
# EFR32FG1P (Flex Gecko) MCU line
config SOC_SERIES_EFR32FG1P
bool
select SOC_FAMILY_SILABS_S1
help
EFR32FG1P Series MCU
config SOC_PART_NUMBER_EFR32FG1P133F256GM48
bool
select SOC_SERIES_EFR32FG1P
config SOC_SERIES
default "efr32fg1p" if SOC_SERIES_EFR32FG1P
config SOC
default "efr32fg1p133f2... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```objective-c
/*
*
*/
/**
* @file
* @brief Board configuration macros for the efr32fg1p soc
*
*/
#ifndef _SOC__H_
#define _SOC__H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#include <em_bus.h>
#include <em_common.h>
#include "soc_pinmap.h"
#include "../common/soc_gpio.h"
#endif /* !_ASMLANGUAGE *... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg1p/soc.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```objective-c
/*
*/
/** @file
* @brief Silabs EFR32FG1P MCU pin definitions.
*
* This file contains pin configuration data required by different MCU
* modules to correctly configure GPIO controller.
*/
#ifndef _SILABS_EFR32FG1P_SOC_PINMAP_H_
#define _SILABS_EFR32FG1P_SOC_PINMAP_H_
#include <zephyr/devicetree.... | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg1p/soc_pinmap.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 301 |
```unknown
# EFR32FG1P series configuration options
if SOC_SERIES_EFR32FG1P
config NUM_IRQS
# must be >= the highest interrupt number used
default 33
endif # SOC_SERIES_EFR32FG1P
``` | /content/code_sandbox/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
# EFM32GG12B (Giant Gecko) MCU line
config SOC_SERIES_EFM32GG12B
bool
select SOC_FAMILY_SILABS_S1
help
EFM32GG12B Series MCU
config SOC_PART_NUMBER_EFM32GG12B810F1024GM64
bool
select SOC_SERIES_EFM32GG12B
config SOC_SERIES
default "efm32gg12b" if SOC_SERIES_EFM32GG12B
config SOC
default "efm32g... | /content/code_sandbox/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 177 |
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