text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1010_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1011dae5a-pinctrl.dtsi>
&pinctrl {
/* ADC Channels 1 and 2, exposed as pins 10 and 12 on J26 of EVK */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_01_adc1_in1>,
<&iomuxc_gpio_ad_02_adc1_in2>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_01_lpi2c1_sda>, <&iomuxc_gpio_02_lpi2c1_scl>;
drive-strength = "r0-4";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_ad_06_lpspi1_sck>,
<&iomuxc_gpio_ad_05_lpspi1_pcs0>,
<&iomuxc_gpio_ad_04_lpspi1_sdo>,
<&iomuxc_gpio_ad_03_lpspi1_sdi>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* MCUX SDK sets the drive strength of pins on RT1010 to 4 by default */
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_09_lpuart1_rxd>,
<&iomuxc_gpio_10_lpuart1_txd>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_09_gpiomux_io09>;
drive-strength = "r0-4";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_10_lpuart1_txd>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with adc1 */
pinmux_lpuart4: pinmux_lpuart4 {
group0 {
pinmux = <&iomuxc_gpio_ad_01_lpuart4_rxd>,
<&iomuxc_gpio_ad_02_lpuart4_txd>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with adc1 */
pinmux_lpuart4_sleep: pinmux_lpuart4_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_01_gpiomux_io15>;
drive-strength = "r0-4";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_02_lpuart4_txd>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_sai1: pinmux_sai1 {
group0 {
pinmux = <&iomuxc_gpio_08_sai1_mclk>,
<&iomuxc_gpio_03_sai1_rx_data0>,
<&iomuxc_gpio_04_sai1_tx_data0>,
<&iomuxc_gpio_07_sai1_tx_sync>,
<&iomuxc_gpio_06_sai1_tx_bclk>;
drive-strength = "r0-4";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,067 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```c
/*
*
*/
#include <soc.h>
void SystemInitHook(void)
{
#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(zephyr_flash)))
/* AT25SF128A SPI Flash on the RT1010-EVK requires special alignment
* considerations, so set the READADDROPT bit in the FlexSPI so it
* will fetch more data than each AHB burst requires to meet alignment
* requirements
*
* Without this, the FlexSPI will return corrupted data during early
* boot, causing a hardfault. This can also be resolved by enabling
* the instruction cache in very early boot.
*/
FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK;
#endif
}
``` | /content/code_sandbox/boards/nxp/mimxrt1010_evk/init.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 170 |
```yaml
board:
name: mimxrt1010_evk
vendor: nxp
socs:
- name: mimxrt1011
``` | /content/code_sandbox/boards/nxp/mimxrt1010_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```yaml
#
#
#
identifier: mimxrt1010_evk
name: NXP MIMXRT1010-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 16384
supported:
- arduino_gpio
- arduino_i2c
- arduino_serial
- arduino_spi
- i2c
- counter
- dma
- usb_device
- spi
- adc
- gpio
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 132 |
```unknown
config BOARD_MIMXRT1050_EVK
select SOC_PART_NUMBER_MIMXRT1052DVL6B
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```cmake
if (NOT DEFINED BOARD_REVISION)
set(BOARD_REVISION "hyperflash")
else ()
if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi"))
message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi")
endif()
endif()
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/revision.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```cmake
#
#
#
board_runner_args(jlink "--device=MCIMXRT1052")
if("${BOARD_REVISION}" STREQUAL "qspi")
board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI")
board_runner_args(pyocd "--target=mimxrt1050_quadspi")
else()
board_runner_args(pyocd "--target=mimxrt1050_hyperflash")
board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
endif()
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 172 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,flash-controller = &s26ks512s0;
zephyr,flash = &s26ks512s0;
zephyr,code-partition = &slot0_partition;
};
};
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
pinctrl-0 = <&pinmux_flexspi1>;
pinctrl-names = "default";
ahb-bufferable;
ahb-cacheable;
sck-differential-clock;
combination-mode;
rx-clock-source = <3>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>;
s26ks512s0: s26ks512s@0 {
compatible = "nxp,imx-flexspi-hyperflash";
size = <DT_SIZE_M(64*8)>;
reg = <0>;
spi-max-frequency = <166000000>;
word-addressable;
cs-interval-unit = <1>;
cs-interval = <2>;
cs-hold-time = <0>;
cs-setup-time = <3>;
data-valid-time = <1>;
column-space = <3>;
ahb-write-wait-unit = <2>;
ahb-write-wait-interval = <20>;
status = "okay";
erase-block-size = <4096>;
write-block-size = <16>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 14 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(56))>;
};
slot1_partition: partition@32E000 {
label = "image-1";
reg = <0x0032E000 DT_SIZE_M(3)>;
};
storage_partition: partition@62E000 {
label = "storage";
reg = <0x0062E000 (DT_SIZE_M(58) - DT_SIZE_K(184))>;
};
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 561 |
```unknown
/*
*
*/
/ {
chosen {
zephyr,flash-controller = &is25wp064;
zephyr,flash = &is25wp064;
zephyr,code-partition = &slot0_partition;
};
};
&flexspi {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
is25wp064: is25wp064@0 {
compatible = "nxp,imx-flexspi-nor";
size = <67108864>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
};
slot1_partition: partition@322000 {
label = "image-1";
reg = <0x00322000 DT_SIZE_M(3)>;
};
storage_partition: partition@622000 {
label = "storage";
reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
};
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 434 |
```restructuredtext
.. _mimxrt1010_evk:
NXP MIMXRT1010-EVK
##################
Overview
********
The i.MX RT1010 offer a new entry-point into the i.MX RT crossover processor
series by providing the lowest-cost LQFP package option, combined with the
high performance and ease-of-use known throughout the entire i.MX RT series.
This device is fully supported by NXPs MCUXpresso Software and Tools.
.. image:: mimxrt1010_evk.jpg
:align: center
:alt: MIMXRT1010-EVK
Hardware
********
- MIMXRT1011DAE5A MCU
- Memory
- 128 Mbit QSPI Flash
- Connectivity
- Micro USB host and OTG connectors
- Arduino interface
- Audio
- Audio Codec
- 4-pole audio headphone jack
- External speaker connection
- Microphone
- Debug
- JTAG 10-pin connector
- OpenSDA with DAPLink
For more information about the MIMXRT1010 SoC and MIMXRT1010-EVK board, see
these references:
- `i.MX RT1010 Website`_
- `i.MX RT1010 Datasheet`_
- `i.MX RT1010 Reference Manual`_
- `MIMXRT1010-EVK Website`_
- `MIMXRT1010-EVK User Guide`_
- `MIMXRT1010-EVK Design Files`_
External Memory
===============
This platform has the following external memories:
+--------------------+------------+-------------------------------------+
| Device | Controller | Status |
+====================+============+=====================================+
| AT25SF128A | FLEXSPI | Enabled via flash configurationn |
| | | block, which sets up FLEXSPI at |
| | | boot time. |
+--------------------+------------+-------------------------------------+
Supported Features
==================
The mimxrt1010_evk board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1064_evk board may have additional features
already supported, which can also be re-used on this mimxrt1010_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| PIT | on-chip | pit |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1010 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_11 | GPIO | LED |
+---------------+-----------------+---------------------------+
| GPIO_SD_05 | GPIO | SW4 |
+---------------+-----------------+---------------------------+
| GPIO_10 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_09 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_01 | LPI2C1_SDA | I2C SDA |
+---------------+-----------------+---------------------------+
| GPIO_02 | LPI2C1_CLK | I2C SCL |
+---------------+-----------------+---------------------------+
| GPIO_AD_03 | LPSPI1_SDI | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_04 | LPSPI1_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_05 | LPSPI1_PCS0 | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_06 | LPSPI1_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_01 | ADC | ADC1 Channel 1 |
+---------------+-----------------+---------------------------+
| GPIO_AD_02 | ADC | ADC1 Channel 2 |
+---------------+-----------------+---------------------------+
System Clock
============
The MIMXRT1010 SoC is configured to use SysTick as the system clock source,
running at 500MHz.
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1010 SoC has four UARTs. ``LPUART1`` is configured for the console,
and the remaining are not used.
Programming and Debugging
*************************
This board supports 3 debug host tools. Please install your preferred host
tool, then follow the instructions in `Configuring a Debug Probe`_ to
configure the board appropriately.
* :ref:`linkserver-debug-host-tools` (Default, Supported by NXP)
* :ref:`jlink-debug-host-tools` (Supported by NXP)
* :ref:`pyocd-debug-host-tools` (Not supported by NXP)
Once the host tool and board are configured, build and flash applications
as usual (see :ref:`build_an_application` and :ref:`application_run` for more
details).
Configuring a Debug Probe
=========================
For the RT1010, J61/J62 are the SWD isolation jumpers, J22 is the DFU
mode jumper, and J16 is the 10 pin JTAG/SWD header.
.. include:: ../../common/rt1xxx-lpclink2-debug.rst
:start-after: rt1xxx-lpclink2-probes
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers J31 and J32 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J41.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1010_evk
:goals: flash
Open a serial terminal, reset the board (press the SW9 button), and you should
see the following message in the terminal:
.. code-block:: console
Hello World! mimxrt1010_evk
.. _MIMXRT1010-EVK Website:
path_to_url
.. _MIMXRT1010-EVK User Guide:
path_to_url
.. _MIMXRT1010-EVK Design Files:
path_to_url
.. _i.MX RT1010 Website:
path_to_url
.. _i.MX RT1010 Datasheet:
path_to_url
.. _i.MX RT1010 Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1010_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,927 |
```yaml
#
#
#
identifier: mimxrt1050_evk
name: NXP MIMXRT1050-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32768
flash: 65536
supported:
- arduino_gpio
- arduino_serial
- counter
- display
- dma
- gpio
- i2c
- netif:eth
- sdhc
- spi
- usb_device
- usbd
- watchdog
- adc
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 144 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt1050.dtsi>
#include "mimxrt1050_evk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP MIMXRT1050-EVK board";
compatible = "nxp,mimxrt1052";
aliases {
led0 = &green_led;
sw0 = &user_button;
watchdog0 = &wdog0;
magn0 = &fxos8700;
accel0 = &fxos8700;
sdhc0 = &usdhc1;
};
chosen {
zephyr,sram = &sdram0;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
};
sdram0: memory@80000000 {
/* Micron MT48LC16M16A2B4-6AIT:G */
device_type = "memory";
reg = <0x80000000 DT_SIZE_M(32)>;
};
/*
* This node describes the GPIO pins of the parallel FPC interface,
* This interface is standard to several NXP EVKs, and is used with
* several parallel LCD displays (available as zephyr shields)
*/
nxp_parallel_lcd_connector: parallel-connector {
compatible = "nxp,parallel-lcd-connector";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio2 31 0>; /* Pin 1, BL+ */
};
/*
* This node describes the GPIO pins of the I2C display FPC interface,
* This interface is standard to several NXP EVKs, and is used with
* several parallel LCD displays (available as zephyr shields)
*/
nxp_i2c_touch_fpc: i2c-touch-connector {
compatible = "nxp,i2c-tsc-fpc";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <1 0 &gpio1 2 0>, /* Pin 2, LCD touch RST */
<2 0 &gpio1 11 0>; /* Pin 3, LCD touch INT */
};
leds {
compatible = "gpio-leds";
green_led: led_0 {
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
label = "User SW8";
gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio1 26 0>, /* A0 */
<1 0 &gpio1 27 0>, /* A1 */
<2 0 &gpio1 20 0>, /* A2 */
<3 0 &gpio1 21 0>, /* A3 */
<4 0 &gpio1 17 0>, /* A4 */
<5 0 &gpio1 16 0>, /* A5 */
<6 0 &gpio1 23 0>, /* D0 */
<7 0 &gpio1 22 0>, /* D1 */
<8 0 &gpio1 11 0>, /* D2 */
<9 0 &gpio1 24 0>, /* D3 */
<10 0 &gpio1 9 0>, /* D4 */
<11 0 &gpio1 10 0>, /* D5 */
<12 0 &gpio1 18 0>, /* D6 */
<13 0 &gpio1 19 0>, /* D7 */
<14 0 &gpio1 3 0>, /* D8 */
<15 0 &gpio1 2 0>, /* D9 */
<16 0 &gpio3 13 0>, /* D10 */
<17 0 &gpio3 14 0>, /* D11 */
<18 0 &gpio3 15 0>, /* D12 */
<19 0 &gpio3 12 0>, /* D13 */
<20 0 &gpio1 1 0>, /* D14 */
<21 0 &gpio1 0 0>; /* D15 */
};
};
arduino_serial: &lpuart3 {
pinctrl-0 = <&pinmux_lpuart3>;
pinctrl-1 = <&pinmux_lpuart3_sleep>;
pinctrl-names = "default", "sleep";
};
&adc1 {
status = "okay";
pinctrl-0 = <&pinmux_adc1>;
pinctrl-names = "default";
};
nxp_touch_i2c: &lpi2c1 {};
zephyr_lcdif: &lcdif {
pinctrl-0 = <&pinmux_lcdif>;
pinctrl-names = "default";
};
&lpi2c1 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c1>;
pinctrl-names = "default";
fxos8700: fxos8700@1f {
compatible = "nxp,fxos8700";
reg = <0x1f>;
/* Two zero ohm resistors (R263 and R264) isolate sensor
* interrupt gpios from the soc and are unpopulated by default.
* Note that if you populate them, they conflict with LCD and
* Ethernet interrupt gpios.
*/
int1-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
};
&lpspi1 {
status = "okay";
/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
dmas = <&edma0 0 13>, <&edma0 1 14>;
dma-names = "rx", "tx";
pinctrl-0 = <&pinmux_lpspi1>;
pinctrl-names = "default";
};
&lpspi3 {
status = "okay";
/* DMA channels 2 and 3, muxed to LPSPI3 RX and TX */
dmas = <&edma0 2 15>, <&edma0 3 16>;
dma-names = "rx", "tx";
pinctrl-0 = <&pinmux_lpspi3>;
pinctrl-names = "default";
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rmii";
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
reset-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
int-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
microchip,interface-type = "rmii";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&usdhc1 {
status = "okay";
pwr-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&wdog0 {
status = "okay";
};
&edma0 {
status = "okay";
};
&pxp {
status = "okay";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,165 |
```yaml
#
#
#
identifier: mimxrt1050_evk@qspi
name: NXP MIMXRT1050-EVK-QSPI
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32768
flash: 8192
supported:
- arduino_gpio
- arduino_serial
- counter
- display
- dma
- gpio
- i2c
- netif:eth
- sdhc
- spi
- usb_device
- usbd
- watchdog
- adc
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```yaml
board:
name: mimxrt1050_evk
vendor: nxp
socs:
- name: mimxrt1052
revision:
format: "custom"
default: "hyperflash"
revisions:
- name: "hyperflash"
- name: "qspi"
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
# MIMXRT1050-EVK board
if BOARD_MIMXRT1050_EVK
config DEVICE_CONFIGURATION_DATA
default y
config NXP_IMX_EXTERNAL_SDRAM
default y
if NETWORKING
config NET_L2_ETHERNET
default y
if ETH_MCUX
config ETH_MCUX_PHY_RESET
default y
endif # ETH_MCUX
endif # NETWORKING
endif # BOARD_MIMXRT1050_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1050_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1052dvl6b-pinctrl.dtsi>
&pinctrl {
/* ADC1 inputs 0 and 15 */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_11_adc1_in0>,
<&iomuxc_gpio_ad_b1_10_adc1_in15>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with lpuart3 and flexcan1 */
pinmux_csi: pinmux_csi {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>;
drive-strength = "r0-6";
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_04_csi_pixclk>,
<&iomuxc_gpio_ad_b1_05_csi_mclk>,
<&iomuxc_gpio_ad_b1_06_csi_vsync>,
<&iomuxc_gpio_ad_b1_07_csi_hsync>,
<&iomuxc_gpio_ad_b1_08_csi_data09>,
<&iomuxc_gpio_ad_b1_09_csi_data08>,
<&iomuxc_gpio_ad_b1_10_csi_data07>,
<&iomuxc_gpio_ad_b1_11_csi_data06>,
<&iomuxc_gpio_ad_b1_12_csi_data05>,
<&iomuxc_gpio_ad_b1_13_csi_data04>,
<&iomuxc_gpio_ad_b1_14_csi_data03>,
<&iomuxc_gpio_ad_b1_15_csi_data02>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_b1_10_enet_ref_clk>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "50-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_b1_04_enet_rx_data0>,
<&iomuxc_gpio_b1_05_enet_rx_data1>,
<&iomuxc_gpio_b1_06_enet_rx_en>,
<&iomuxc_gpio_b1_07_enet_tx_data0>,
<&iomuxc_gpio_b1_08_enet_tx_data1>,
<&iomuxc_gpio_b1_09_enet_tx_en>,
<&iomuxc_gpio_b1_11_enet_rx_er>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <&iomuxc_gpio_emc_40_enet_mdc>,
<&iomuxc_gpio_emc_41_enet_mdio>,
<&iomuxc_gpio_ad_b0_10_gpio1_io10>,
<&iomuxc_gpio_ad_b0_09_gpio1_io09>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
pinmux_ptp: pinmux_ptp {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_02_enet_1588_event2_out>,
<&iomuxc_gpio_ad_b1_03_enet_1588_event2_in>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with SAI1 */
pinmux_flexcan1: pinmux_flexcan1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_08_flexcan1_tx>,
<&iomuxc_gpio_ad_b1_09_flexcan1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_flexcan2: pinmux_flexcan2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_14_flexcan2_tx>,
<&iomuxc_gpio_ad_b0_15_flexcan2_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* flexpwm output for board LED */
pinmux_flexpwm2: pinmux_flexpwm2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_09_flexpwm2_pwma3>;
drive-strength = "r0-4";
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_flexspi1: pinmux_flexspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_05_flexspi_a_dqs>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-down;
bias-pull-down-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_sd_b1_03_flexspi_b_data0>,
<&iomuxc_gpio_sd_b1_00_flexspi_b_data3>,
<&iomuxc_gpio_sd_b1_01_flexspi_b_data2>,
<&iomuxc_gpio_sd_b1_02_flexspi_b_data1>,
<&iomuxc_gpio_sd_b1_04_flexspi_b_sclk>,
<&iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b>,
<&iomuxc_gpio_sd_b1_07_flexspi_a_sclk>,
<&iomuxc_gpio_sd_b1_08_flexspi_a_data0>,
<&iomuxc_gpio_sd_b1_09_flexspi_a_data1>,
<&iomuxc_gpio_sd_b1_10_flexspi_a_data2>,
<&iomuxc_gpio_sd_b1_11_flexspi_a_data3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "200-mhz";
input-enable;
};
};
/* FLEXSPI A is connected to external flash */
pinmux_flexspia: pinmux_flexspia {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_05_flexspi_a_dqs>,
<&iomuxc_gpio_sd_b1_06_flexspi_a_ss0_b>,
<&iomuxc_gpio_sd_b1_07_flexspi_a_sclk>,
<&iomuxc_gpio_sd_b1_08_flexspi_a_data0>,
<&iomuxc_gpio_sd_b1_09_flexspi_a_data1>,
<&iomuxc_gpio_sd_b1_10_flexspi_a_data2>,
<&iomuxc_gpio_sd_b1_11_flexspi_a_data3>;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* Configures pin routing and optionally pin electrical features. */
pinmux_lcdif: pinmux_lcdif {
group0 {
pinmux = <&iomuxc_gpio_b0_00_lcdif_clk>,
<&iomuxc_gpio_b0_01_lcdif_enable>,
<&iomuxc_gpio_b0_02_lcdif_hsync>,
<&iomuxc_gpio_b0_03_lcdif_vsync>,
<&iomuxc_gpio_b0_04_lcdif_data00>,
<&iomuxc_gpio_b0_05_lcdif_data01>,
<&iomuxc_gpio_b0_06_lcdif_data02>,
<&iomuxc_gpio_b0_07_lcdif_data03>,
<&iomuxc_gpio_b0_08_lcdif_data04>,
<&iomuxc_gpio_b0_09_lcdif_data05>,
<&iomuxc_gpio_b0_10_lcdif_data06>,
<&iomuxc_gpio_b0_11_lcdif_data07>,
<&iomuxc_gpio_b0_12_lcdif_data08>,
<&iomuxc_gpio_b0_13_lcdif_data09>,
<&iomuxc_gpio_b0_14_lcdif_data10>,
<&iomuxc_gpio_b0_15_lcdif_data11>,
<&iomuxc_gpio_b1_00_lcdif_data12>,
<&iomuxc_gpio_b1_01_lcdif_data13>,
<&iomuxc_gpio_b1_02_lcdif_data14>,
<&iomuxc_gpio_b1_03_lcdif_data15>;
drive-strength = "r0-6";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_02_gpio1_io02>,
<&iomuxc_gpio_b1_15_gpio2_io31>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_01_lpi2c1_sda>,
<&iomuxc_gpio_ad_b1_00_lpi2c1_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* Conflicts with USDHC pins. Connect R278, R279, R280, and R281 on evk board */
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_lpspi1_pcs0>,
<&iomuxc_gpio_sd_b0_00_lpspi1_sck>,
<&iomuxc_gpio_sd_b0_03_lpspi1_sdi>,
<&iomuxc_gpio_sd_b0_02_lpspi1_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with lcdif pins */
pinmux_lpspi3: pinmux_lpspi3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_03_lpspi3_pcs0>,
<&iomuxc_gpio_ad_b0_00_lpspi3_sck>,
<&iomuxc_gpio_ad_b0_02_lpspi3_sdi>,
<&iomuxc_gpio_ad_b0_01_lpspi3_sdo>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_lpuart1_rx>,
<&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_13_gpio1_io13>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_12_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3: pinmux_lpuart3 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
<&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* Flow control for lpuart3 */
pinmux_lpuart3_flow_control: pinmux_lpuart3_flow_control {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_lpuart3_tx>,
<&iomuxc_gpio_ad_b1_07_lpuart3_rx>,
<&iomuxc_gpio_ad_b1_04_lpuart3_cts_b>,
<&iomuxc_gpio_ad_b1_05_lpuart3_rts_b>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>;
drive-strength = "r0";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_07_lpuart3_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_sai1: pinmux_sai1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_sai1_mclk>,
<&iomuxc_gpio_ad_b1_13_sai1_tx_data0>,
<&iomuxc_gpio_ad_b1_12_sai1_rx_data0>,
<&iomuxc_gpio_ad_b1_14_sai1_tx_bclk>,
<&iomuxc_gpio_ad_b1_15_sai1_tx_sync>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_b1_12_gpio2_io28>,
<&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_b1_14_usdhc1_vselect>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* fast pinmux settings for USDHC (over 100 Mhz) */
pinmux_usdhc1_fast: pinmux_usdhc1_fast {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* medium pinmux settings for USDHC (under 100 Mhz) */
pinmux_usdhc1_med: pinmux_usdhc1_med {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* slow pinmux settings for USDHC (under 50 Mhz) */
pinmux_usdhc1_slow: pinmux_usdhc1_slow {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_01_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_00_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_02_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_03_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
pinmux_qdec1: pinmux_qdec1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_09_xbar1_xbar_in21>,
<&iomuxc_gpio_ad_b0_10_xbar1_xbar_in22>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,912 |
```cmake
#
#
#
board_runner_args(linkserver "--device=MKE17Z512xxx9:FRDM-KE17Z512")
board_runner_args(jlink "--device=MKE17Z512xxx9" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
config BOARD_FRDM_KE17Z512
select SOC_MKE17Z9
select SOC_PART_NUMBER_MKE17Z512VLL9
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/Kconfig.frdm_ke17z512 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
#include <nxp/kinetis/MKE17Z512VLL9-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE0_PTE9>;
drive-strength = "low";
slew-rate = "slow";
};
};
/* Configures pin routing and optionally pin electrical features. */
lpuart2_default: lpuart2_default {
group0 {
pinmux = <LPUART2_TX_PTE12>,
<LPUART2_RX_PTD17>;
drive-strength = "low";
slew-rate = "slow";
};
};
ftm2_default: ftm2_default {
group0 {
pinmux = <FTM2_CH0_PTD10>,
<FTM2_CH2_PTD12>,
<FTM2_CH3_PTD5>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpi2c0_default: lpi2c0_default {
group0 {
pinmux = <LPI2C0_SDA_PTA2>,
<LPI2C0_SCL_PTA3>;
bias-pull-up;
drive-strength = "low";
slew-rate = "slow";
};
};
lpi2c1_default: lpi2c1_default {
group0 {
pinmux = <LPI2C1_SDA_PTE0>,
<LPI2C1_SCL_PTE1>;
bias-pull-up;
drive-strength = "low";
slew-rate = "slow";
};
};
uart1_default: uart1_default {
group0 {
pinmux = <SCI1_RX_PTC16>,
<SCI1_TX_PTC17>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpspi0_default: lpspi0_default {
group0 {
pinmux = <LPSPI0_SCK_PTE0>,
<LPSPI0_SIN_PTE1>,
<LPSPI0_SOUT_PTE2>,
<LPSPI0_PCS2_PTE6>;
bias-pull-up;
drive-strength = "low";
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/frdm_ke17z512-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 539 |
```yaml
#
#
#
identifier: frdm_ke17z512
name: NXP FRDM-KE17Z512
type: mcu
arch: arm
ram: 64
flash: 512
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- counter
- gpio
- adc
- uart
- pwm
- i2c
- spi
- dma
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 110 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 26 |
```yaml
board:
name: frdm_ke17z512
vendor: nxp
socs:
- name: mke17z9
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ke17z512.dtsi>
#include "frdm_ke17z512-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
/ {
model = "NXP Freedom KE17Z512 board";
compatible = "nxp,ke17z512", "nxp,mke17z9", "nxp,ke1xz";
chosen {
zephyr,sram = &sram_u;
zephyr,flash = &flash0;
zephyr,console = &lpuart2;
zephyr,shell-uart = &lpuart2;
};
aliases {
watchdog0 = &wdog;
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
pwm-led0 = &red_pwm_led;
pwm-led1 = &green_pwm_led;
pwm-led2 = &blue_pwm_led;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiod 10 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
green_led: led_1 {
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
blue_led: led_2 {
gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: led_pwm_0 {
pwms = <&ftm2 0 PWM_HZ(20) PWM_POLARITY_INVERTED>;
label = "RED RGB PWM LED";
};
green_pwm_led: led_pwm_1 {
pwms = <&ftm2 3 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "GREEN RGB PWM LED";
};
blue_pwm_led: led_pwm_2 {
pwms = <&ftm2 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "BLUE RGB PWM LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpioe 14 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
};
&idle {
min-residency-us = <1>;
};
&stop {
min-residency-us = <20000>;
exit-latency-us = <13>;
};
&lpuart2 {
dmas = <&edma 5 6>, <&edma 6 7>;
dma-names = "rx", "tx";
status = "okay";
pinctrl-0 = <&lpuart2_default>;
pinctrl-names = "default";
current-speed = <115200>;
};
&adc0 {
status = "okay";
sample-time = <12>;
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&gpiod {
status = "okay";
};
&scg {
bus_clk {
clock-div = <2>;
};
};
&gpioe {
status = "okay";
};
&rtc {
status = "okay";
clock-source = "LPO";
};
&lpi2c0 {
status = "okay";
pinctrl-0 = <&lpi2c0_default>;
pinctrl-names = "default";
};
&lpi2c1 {
status = "okay";
pinctrl-0 = <&lpi2c1_default>;
pinctrl-names = "default";
};
&ftm2 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
clocks = <&scg KINETIS_SCG_SIRC_CLK>;
prescaler = <128>;
pinctrl-0 = <&ftm2_default>;
pinctrl-names = "default";
clock-source = "system";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 (DT_SIZE_K(202) + DT_SIZE_K(4))>;
};
slot1_partition: partition@43800 {
label = "image-1";
reg = <0x00043800 DT_SIZE_K(202)>;
};
storage_partition: partition@76000 {
label = "storage";
reg = <0x00076000 DT_SIZE_K(40)>;
};
};
};
&lpspi0 {
dmas = <&edma 0 14>, <&edma 1 15>;
dma-names = "rx", "tx";
status = "okay";
pinctrl-0 = <&lpspi0_default>;
pinctrl-names = "default";
};
&edma {
status = "okay";
};
&wdog {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/frdm_ke17z512.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,319 |
```restructuredtext
.. _mimxrt1050_evk:
NXP MIMXRT1050-EVK
##################
Overview
********
The i.MX RT1050 is a new processor family featuring NXP's advanced
implementation of the ARM Cortex-M7 Core. It provides high CPU performance and
real-time response.
The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND
FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other
interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays,
and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich
audio and video features, including LCD display, basic 2D graphics, camera
interface, SPDIF, and I2S audio interface.
.. image:: mimxrt1050_evk.jpg
:align: center
:alt: MIMXRT1050-EVK
Hardware
********
- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM)
- Memory
- 256 KB SDRAM
- 64 Mbit QSPI Flash
- 512 Mbit Hyper Flash
- Display
- LCD connector
- Touch connector
- Ethernet
- 10/100 Mbit/s Ethernet PHY
- USB
- USB 2.0 OTG connector
- USB 2.0 host connector
- Audio
- 3.5 mm audio stereo headphone jack
- Board-mounted microphone
- Left and right speaker out connectors
- Power
- 5 V DC jack
- Debug
- JTAG 20-pin connector
- OpenSDA with DAPLink
- Sensor
- FXOS8700CQ 6-axis e-compass
- CMOS camera sensor interface
- Expansion port
- Arduino interface
- CAN bus connector
For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see
these references:
- `i.MX RT1050 Website`_
- `i.MX RT1050 Datasheet`_
- `i.MX RT1050 Reference Manual`_
- `MIMXRT1050-EVK Website`_
- `MIMXRT1050-EVK User Guide`_
- `MIMXRT1050-EVK Schematics`_
External Memory
===============
This platform has the following external memories:
+--------------------+------------+-------------------------------------+
| Device | Controller | Status |
+====================+============+=====================================+
| IS42S16160J | SEMC | Enabled via device configuration |
| | | data block, which sets up SEMC at |
| | | boot time |
+--------------------+------------+-------------------------------------+
| S26KS512SDPBHI020 | FLEXSPI | Enabled via flash configurationn |
| | | block, which sets up FLEXSPI at |
| | | boot time. |
+--------------------+------------+-------------------------------------+
Supported Features
==================
The mimxrt1050_evk board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1064_evk board may have additional features
already supported, which can also be re-used on this mimxrt1050_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | eLCDIF. Tested with |
| | | :ref:`rk043fn02h_ct`, and |
| | | :ref:`rk043fn66hs_ctg` shields |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SDHC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_AD_B0_00 | LPSPI1_SCK | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_01 | LPSPI1_SDO | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_05 | GPIO | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | GPIO/ENET_RST | LED |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_11 | GPIO | Touch Interrupt |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_00 | LPI2C1_SCL | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_01 | LPI2C1_SDA | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_11 | ADC | ADC1 channel 0 |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW0 |
+---------------+-----------------+---------------------------+
| GPIO_B0_00 | LCD_CLK | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_01 | LCD_ENABLE | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_02 | LCD_HSYNC | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_03 | LCD_VSYNC | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_04 | LCD_DATA00 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_05 | LCD_DATA01 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_06 | LCD_DATA02 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_07 | LCD_DATA03 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_08 | LCD_DATA04 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_09 | LCD_DATA05 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_10 | LCD_DATA06 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_11 | LCD_DATA07 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_12 | LCD_DATA08 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_13 | LCD_DATA09 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_14 | LCD_DATA10 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B0_15 | LCD_DATA11 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_00 | LCD_DATA12 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_01 | LCD_DATA13 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_02 | LCD_DATA14 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_03 | LCD_DATA15 | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_06 | ENET_RX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_09 | ENET_TX_EN | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_10 | ENET_REF_CLK | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_11 | ENET_RX_ER | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_B1_12 | GPIO | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_B1_14 | USDHC1_VSELECT | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display |
+---------------+-----------------+---------------------------+
| GPIO_EMC_40 | ENET_MDC | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_41 | ENET_MDIO | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | ENET_RST | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | ENET_INT | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 |
+---------------+-----------------+---------------------------+
.. note::
In order to use the SPI peripheral on this board, resistors R278,
R279, R280, and R281 must be populated with zero ohm resistors
System Clock
============
The MIMXRT1050 SoC is configured to use SysTick as the system clock source,
running at 600MHz.
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console,
``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the
remaining are not used.
USB
===
The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both
device and host functions through its micro USB connectors.
Only USB device function is supported in Zephyr at the moment.
Programming and Debugging
*************************
.. note::
Newer revisions of this board use :ref:`lpc-link2-onboard-debug-probe`,
while older revisions use the :ref:`opensda-onboard-debug-probe`.
Schematic revisions A/A1 use the K20 OpenSDA probe, and B/B1 use the
LPC-Link2 LPC4322 probe.
This board supports 3 debug host tools. Please install your preferred host
tool, then follow the instructions in `Configuring a Debug Probe
(Schematic A/A1)`_ or `Configuring a Debug Probe (Schematic B/B1)`_,
depending on board schematic revision to configure the board appropriately.
* :ref:`linkserver-debug-host-tools` (Default, NXP Supported)
* :ref:`jlink-debug-host-tools` (NXP Supported)
* :ref:`pyocd-debug-host-tools` (Not supported by NXP)
Once the host tool and board are configured, build and flash applications
as usual (see :ref:`build_an_application` and :ref:`application_run` for more
details).
Configuring a Debug Probe (Schematic A/A1)
==========================================
For the RT1050 Schematic Rev A, J32/J33 are the SWD isolation jumpers, SW4 is
the reset button, and J21 is the 20 pin JTAG/SWD header.
.. include:: ../../common/opensda-debug.rst
:start-after: nxp-opensda-probes
Configuring a Debug Probe (Schematic B/B1)
==========================================
For the RT1050 Schematic Rev B, J47/J48 are the SWD isolation jumpers, J42 is
the DFU mode jumper, and J21 is the 20 pin JTAG/SWD header.
.. include:: ../../common/rt1xxx-lpclink2-debug.rst
:start-after: rt1xxx-lpclink2-probes
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers J30 and J31 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J28.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1050_evk
:goals: flash
Open a serial terminal, reset the board (press the SW4 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1050_evk
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1050_evk
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1050_evk
Troubleshooting
===============
If the debug probe fails to connect with the following error, it's possible
that the boot header in HyperFlash is invalid or corrupted. The boot header is
configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`.
.. code-block:: console
Remote debugging using :2331
Remote communication error. Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.
You can fix it by erasing and reprogramming the HyperFlash with the following
steps:
#. Set the SW7 DIP switches to ON-ON-ON-OFF to prevent booting from HyperFlash.
#. Reset by pressing SW4
#. Run ``west debug`` or ``west flash`` again with a known working Zephyr
application.
#. Set the SW7 DIP switches to OFF-ON-ON-OFF to boot from HyperFlash.
#. Reset by pressing SW4
Board Revisions
***************
The original MIMXRT1050-EVK (rev A0) board was updated with a newer
MIMXRT1050-EVKB (rev A1) board, with these major hardware differences:
- SoC changed from MIMXRT1052DVL6\ **A** to MIMXRT1052DVL6\ **B**
- Hardware bug fixes for: power, interfaces, and memory
- Arduino headers included
For more details, please see the following `NXP i.MXRT1050 A0 to A1 Migration Guide`_.
Current Zephyr build supports the new MIMXRT1050-EVKB
.. _MIMXRT1050-EVK Website:
path_to_url
.. _MIMXRT1050-EVK User Guide:
path_to_url
.. _MIMXRT1050-EVK Schematics:
path_to_url
.. _i.MX RT1050 Website:
path_to_url
.. _i.MX RT1050 Datasheet:
path_to_url
.. _i.MX RT1050 Reference Manual:
path_to_url
.. _OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware:
path_to_url
.. _NXP i.MXRT1050 A0 to A1 Migration Guide:
path_to_url
.. _Enable QSPI flash support in SEGGER JLink:
path_to_url#QSPI_flash
``` | /content/code_sandbox/boards/nxp/mimxrt1050_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,464 |
```restructuredtext
.. _frdm_ke17z512:
NXP FRDM-KE17Z512
##################
Overview
********
The FRDM-KE17Z512 is a development board for NXP Kinetis KE1xZ 32-bit
MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter,
running an open source bootloader, offers options for serial
communication, flash programming, and run-control debugging.
.. figure:: frdm_ke17z512.webp
:align: center
:alt: FRDM-KE17Z512
FRDM-KE17Z512 (Credit: NXP)
Hardware
********
- MKE17Z512VLL9 MCU (up to 96 MHz, 512 KB flash memory, 96 KB RAM,
and 100 Low profile Quad Flat Package (LQFP))
- 3.3 V or 5 V MCU operation
- 6-axis FXOS8700CQ digital accelerometer and magnetometer
- RGB LED
- Two user push-buttons
- Thermistor
- Arduino compatible I/O pin header
- OpenSDA on-board debugger
- Two Touch Electrodes
For more information about the KE1xZ SoC and the FRDM-KE17Z512 board, see
these NXP reference documents:
- `KE1xZ Website`_
- `KE1xZ Fact Sheet`_
- `KE1xZ Reference Manual`_
- `FRDM-KE17Z512 Website`_
- `FRDM-KE17Z512 Quick Start Guide`_
- `FRDM-KE17Z512 Reference Manual`_
Supported Features
==================
The frdm_ke17z512 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| LPTMR | on-chip | counter |
+-----------+------------+-------------------------------------+
| UART | on-chip | uart polling; |
| | | uart interrupt |
+-----------+------------+-------------------------------------+
| FTM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| I2C | on-chip | I2C |
+-----------+------------+-------------------------------------+
| RTC | on-chip | counter |
+-----------+------------+-------------------------------------+
| ACMP | on-chip | sensor |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
``boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig``.
Other hardware features are not currently supported by the port.
System Clock
============
The KE17Z9 SoC is configured to run at 48 MHz using the FIRC.
Serial Port
===========
The KE17Z9 SoC has three LPUARTs. UART2 is configured for the console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use Linkserver.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
Option 1: Linkserver
--------------------
Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
search path. LinkServer works with the default CMSIS-DAP firmware included in
the on-board debugger.
Linkserver is the default for this board, ``west flash`` and ``west debug`` will
call the linkserver runner.
Option 2: :ref:`opensda-jlink-onboard-debug-probe`
--------------------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `Segger J-Link OpenSDA V2.1 Firmware`_.
Use the ``-r jlink`` option with west to use the jlink runner.
.. code-block:: console
west flash -r jlink
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J10.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_ke17z512
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-xxxx-gxxxxxxxxxxxx ***
Hello World! frdm_ke17z512/mke17z9
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_ke17z512
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-xxxx-gxxxxxxxxxxxx ***
Hello World! frdm_ke17z512/mke17z9
.. _FRDM-KE17Z512 Website:
path_to_url
.. _FRDM-KE17Z512 Quick Start Guide:
path_to_url
.. _FRDM-KE17Z512 Reference Manual:
path_to_url
.. _KE1xZ Website:
path_to_url
.. _KE1xZ Fact Sheet:
path_to_url
.. _KE1xZ Reference Manual:
path_to_url
.. _linkserver-debug-host-tools:
path_to_url
.. _Segger J-Link OpenSDA V2.1 Firmware:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _jlink-debug-host-tools:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_ke17z512/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,581 |
```cmake
board_runner_args(jlink "--device=MKW24D512xxx5" "--speed=4000")
board_runner_args(pyocd "--target=kw24d5" "--frequency=4000000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 78 |
```unknown
config BOARD_USB_KW24D512
select SOC_MKW24D5
select SOC_PART_NUMBER_MKW24D512VHA5
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
board:
name: usb_kw24d512
vendor: nxp
socs:
- name: mkw24d5
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MKW24D512VHA5/signal_configuration.xml
*
*/
#include <nxp/kinetis/MKW24D512VHA5-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTA1>,
<UART0_TX_PTA2>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/usb_kw24d512-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 125 |
```unknown
CONFIG_CONSOLE=y
CONFIG_RTT_CONSOLE=y
CONFIG_USE_SEGGER_RTT=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_OSC_EXTERNAL=y
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```yaml
identifier: usb_kw24d512
name: NXP USB-KW24D512
type: mcu
arch: arm
ram: 32
flash: 512
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- usb_device
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/usb_kw24d512.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
# USB-KW24D512 board
if BOARD_USB_KW24D512
config OSC_XTAL0_FREQ
# The MCU is configured to use 4 MHz external
# clock from the transceiver provided at the CLK_OUT output.
# CLK_OUT is internally connected to the input pin EXTAL0
# of the MCU.
default 4000000
config MCG_PRDIV0
default 0x1
config MCG_VDIV0
default 0x0
config MCG_FCRDIV
default 2
config MCR20A_IS_PART_OF_KW2XD_SIP
default y
depends on IEEE802154_MCR20A
endif # BOARD_USB_KW24D512
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```unknown
/dts-v1/;
#include <nxp/nxp_kw2xd.dtsi>
#include "usb_kw24d512-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP USB-KW24D512 board";
compatible = "nxp,usb-kw24d512", "nxp,kw24d512", "nxp,kw2xd";
aliases {
led0 = &led_0;
led1 = &led_1;
sw0 = &user_button_1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-pipe = &uart0;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led_0: led_0 {
gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
led_1: led_1 {
gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "User SW1";
gpios = <&gpioc 4 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&cpu0 {
clock-frequency = <48000000>;
};
&adc0 {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
zephyr_udc0: &usbd {
compatible = "nxp,kinetis-usbd";
status = "okay";
num-bidir-endpoints = <8>;
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&ieee802154 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 0x00070000>;
};
storage_partition: partition@700000 {
label = "storage";
reg = <0x00070000 0x00010000>;
};
};
};
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/usb_kw24d512.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 674 |
```cmake
#
#
#
board_runner_args(pyocd "--target=mimxrt1024")
board_runner_args(jlink "--device=MIMXRT1024xxx5A")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt1024.dtsi>
#include "mimxrt1024_evk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP MIMXRT1024-EVK board";
compatible = "nxp,mimxrt1024";
aliases {
led0 = &green_led;
sw0 = &user_button;
watchdog0 = &wdog0;
magn0 = &fxos8700;
accel0 = &fxos8700;
sdhc0 = &usdhc1;
};
chosen {
zephyr,flash-controller = &w25q32jvwj0;
zephyr,flash = &w25q32jvwj0;
zephyr,code-partition = &slot0_partition;
zephyr,sram = &sdram0;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,canbus = &flexcan1;
};
sdram0: memory@80000000 {
/* ISSI IS42S16160J-6TLI */
device_type = "memory";
reg = <0x80000000 DT_SIZE_M(32)>;
};
leds {
compatible = "gpio-leds";
green_led: led-1 {
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button-1 {
label = "User SW4";
gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio1 26 0>, /* A0 */
<1 0 &gpio1 27 0>, /* A1 */
<2 0 &gpio1 28 0>, /* A2 */
<3 0 &gpio1 29 0>, /* A3 */
<4 0 &gpio1 31 0>, /* A4 */
<5 0 &gpio1 30 0>, /* A5 */
<6 0 &gpio1 25 0>, /* D0 */
<7 0 &gpio1 24 0>, /* D1 */
<8 0 &gpio1 9 0>, /* D2 */
<9 0 &gpio1 7 0>, /* D3 */
<10 0 &gpio1 5 0>, /* D4 */
<11 0 &gpio1 6 0>, /* D5 */
<12 0 &gpio1 14 0>, /* D6 */
<13 0 &gpio1 22 0>, /* D7 */
<14 0 &gpio1 23 0>, /* D8 */
<15 0 &gpio1 15 0>, /* D9 */
<16 0 &gpio1 11 0>, /* D10 */
<17 0 &gpio1 12 0>, /* D11 */
<18 0 &gpio1 13 0>, /* D12 */
<19 0 &gpio1 10 0>, /* D13 */
<20 0 &gpio3 23 0>, /* D14 */
<21 0 &gpio3 22 0>; /* D15 */
};
};
arduino_serial: &lpuart2 {
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&w25q32jvwj0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_K(1920) + DT_SIZE_K(8))>;
};
slot1_partition: partition@202000 {
label = "image-1";
reg = <0x00202000 DT_SIZE_K(1920)>;
};
storage_partition: partition@3E2000 {
label = "storage";
reg = <0x003E2000 DT_SIZE_K(120)>;
};
};
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rmii";
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
int-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
microchip,interface-type = "rmii";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
};
&lpuart2 {
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&flexcan1 {
status = "okay";
pinctrl-0 = <&pinmux_flexcan1>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <5000000>;
};
};
&wdog0 {
status = "okay";
};
&lpi2c4 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c4>;
pinctrl-names = "default";
scl-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
fxos8700: fxos8700@1f {
compatible = "nxp,fxos8700";
reg = <0x1f>;
};
};
&edma0 {
status = "okay";
};
&lpspi1 {
status = "okay";
/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
dmas = <&edma0 0 13>, <&edma0 1 14>;
dma-names = "rx", "tx";
pinctrl-0 = <&pinmux_lpspi1>;
pinctrl-names = "default";
};
&adc1 {
status = "okay";
pinctrl-0 = <&pinmux_adc1>;
pinctrl-names = "default";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&usdhc1 {
status = "okay";
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pwr-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
no-1-8-v;
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,035 |
```restructuredtext
.. _usb_kw24d512:
NXP USB-KW24D512
################
Overview
********
The USB-KW24D512 is an evaluation board in a convenient USB dongle
form factor based on the NXP MKW24D512 System-in-Package (SiP) device
(KW2xD wireless MCU series).
MKW24D512 wireless MCU provides a low-power, compact device with
integrated IEEE 802.15.4 radio. The board can be used as a packet sniffer,
network node, border router or as a development board.
Hardware
********
- Kinetis KW2xD-2.4 GHz 802.15.4 Wireless Radio Microcontroller
(50 MHz, 512 KB flash memory, 64 KB RAM, low-power, crystal-less USB)
- USB Type A Connector
- Two blue LEDs
- One user push button
- One reset button
- Integrated PCB Folded F-type antenna
- 10-pin (0.05) JTAG debug port for target MCU
For more information about the KW2xD SiP and USB-KW24D512 board:
- `KW2xD Website`_
- `KW2xD Datasheet`_
- `KW2xD Reference Manual`_
- `USB-KW24D512 Website`_
- `USB-KW24D512 Hardware Reference Manual`_
Supported Features
==================
The USB-KW24D512 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| RNGA | on-chip | entropy; |
| | | random |
+-----------+------------+-------------------------------------+
| FTFL | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/usb_kw24d512/usb_kw24d512_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The KW2xD SoC has five pairs of pinmux/gpio controllers.
+-------+-----------------+--------------------------------------+
| Name | Function | Usage |
+=======+=================+======================================+
| PTA1 | UART0_RX | UART Console |
+-------+-----------------+--------------------------------------+
| PTA2 | UART0_TX | UART Console |
+-------+-----------------+--------------------------------------+
| PTC4 | GPIO | SW1 |
+-------+-----------------+--------------------------------------+
| PTD4 | GPIO | Blue LED (D2) |
+-------+-----------------+--------------------------------------+
| PTD5 | GPIO | Blue LED (D3) |
+-------+-----------------+--------------------------------------+
| PTB10 | SPI1_PCS0 | internal connected to MCR20A |
+-------+-----------------+--------------------------------------+
| PTB11 | SPI1_SCK | internal connected to MCR20A |
+-------+-----------------+--------------------------------------+
| PTB16 | SPI1_SOUT | internal connected to MCR20A |
+-------+-----------------+--------------------------------------+
| PTB17 | SPI1_SIN | internal connected to MCR20A |
+-------+-----------------+--------------------------------------+
| PTB19 | GPIO | internal connected to MCR20A (Reset) |
+-------+-----------------+--------------------------------------+
| PTB3 | GPIO | internal connected to MCR20A (IRQ_B) |
+-------+-----------------+--------------------------------------+
| PTC0 | GPIO | internal connected to MCR20A (GPIO5) |
+-------+-----------------+--------------------------------------+
System Clock
============
USB-KW24D512 contains 32 MHz oscillator crystal, which is connected to the
clock pins of the radio transceiver. The MCU is configured to
use the 4 MHz external clock from the transceiver with the on-chip PLL
to generate a 48 MHz system clock.
Serial Port
===========
The KW2xD SoC has three UARTs. One is configured and can be used for the
console, but it uses the same pins as the JTAG interface and is only
accessible via the JTAG SWD connector.
USB
===
The KW2xD SoC has a USB OTG (USBOTG) controller that supports both
device and host functions. Only USB device function is supported in Zephyr
at the moment. The USB-KW24D512 board has a USB Type A connector and
can only be used in device mode.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`jlink-external-debug-probe`.
:ref:`jlink-external-debug-probe`
---------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Attach a J-Link 10-pin connector to J1.
Configuring a Console
=====================
The console is available using `Segger RTT`_.
Connect a USB cable from your PC to J5.
Once you have started a debug session, run telnet:
.. code-block:: console
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
SEGGER J-Link V6.44 - Real time terminal output
SEGGER J-Link ARM V10.1, SN=600111924
Process: JLinkGDBServerCLExe
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: usb_kw24d512
:goals: flash
The Segger RTT console is only available during a debug session. Use ``attach``
to start one:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: usb_kw24d512
:goals: attach
Run telnet as shown earlier, and you should see the following message in the
terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! usb_kw24d512
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: usb_kw24d512
:goals: debug
Run telnet as shown earlier, step through the application in your debugger, and
you should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! usb_kw24d512
.. _USB-KW24D512 Website:
path_to_url
.. _USB-KW24D512 Hardware Reference Manual:
path_to_url
.. _KW2xD Website:
path_to_url
.. _KW2xD Datasheet:
path_to_url
.. _KW2xD Reference Manual:
path_to_url
.. _Segger RTT:
path_to_url
``` | /content/code_sandbox/boards/nxp/usb_kw24d512/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,837 |
```yaml
#
#
#
identifier: mimxrt1024_evk
name: NXP MIMXRT1024-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32768
flash: 4096
supported:
- arduino_gpio
- arduino_serial
- can
- dma
- hwinfo
- netif:eth
- watchdog
- spi
- sdhc
- adc
- usb_device
- pwm
- gpio
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```unknown
config BOARD_MIMXRT1024_EVK
select SOC_PART_NUMBER_MIMXRT1024DAG5A
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```yaml
board:
name: mimxrt1024_evk
vendor: nxp
socs:
- name: mimxrt1024
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# MIMXRT1024-EVK board
if BOARD_MIMXRT1024_EVK
config DEVICE_CONFIGURATION_DATA
default y
config NXP_IMX_EXTERNAL_SDRAM
default y
config I2C_MCUX_LPI2C_BUS_RECOVERY
default y
depends on I2C_MCUX_LPI2C && PINCTRL
if NETWORKING
config NET_L2_ETHERNET
default y
if ETH_MCUX
config ETH_MCUX_PHY_RESET
default y
endif # ETH_MCUX
endif # NETWORKING
endif # BOARD_MIMXRT1024_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 129 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1024_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1024dag5a-pinctrl.dtsi>
&pinctrl {
/* ADC1 inputs 10 and 11 */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_10_adc1_in10>,
<&iomuxc_gpio_ad_b1_11_adc1_in11>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_08_enet_ref_clk>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "50-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_09_enet_rx_data1>,
<&iomuxc_gpio_ad_b0_11_enet_rx_en>,
<&iomuxc_gpio_ad_b0_14_enet_tx_data0>,
<&iomuxc_gpio_ad_b0_15_enet_tx_data1>,
<&iomuxc_gpio_ad_b0_13_enet_tx_en>,
<&iomuxc_gpio_ad_b0_12_enet_rx_er>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_ad_b0_10_enet_rx_data0>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <&iomuxc_gpio_emc_40_enet_mdio>,
<&iomuxc_gpio_emc_41_enet_mdc>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
pinmux_ptp: pinmux_ptp {
/* Intentionally empty */
};
pinmux_flexcan1: pinmux_flexcan1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_00_flexcan1_tx>,
<&iomuxc_gpio_sd_b1_01_flexcan1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_14_lpi2c1_scl>,
<&iomuxc_gpio_ad_b1_15_lpi2c1_sda>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c4: pinmux_lpi2c4 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_03_lpi2c4_sda>,
<&iomuxc_gpio_sd_b1_02_lpi2c4_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* conflicts with enet pinmux */
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_10_lpspi1_sck>,
<&iomuxc_gpio_ad_b0_11_lpspi1_pcs0>,
<&iomuxc_gpio_ad_b0_12_lpspi1_sdo>,
<&iomuxc_gpio_ad_b0_13_lpspi1_sdi>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_07_lpuart1_rx>,
<&iomuxc_gpio_ad_b0_06_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_07_gpio1_io07>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_06_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with user led */
pinmux_lpuart2: pinmux_lpuart2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_lpuart2_rx>,
<&iomuxc_gpio_ad_b1_08_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with user led */
pinmux_lpuart2_sleep: pinmux_lpuart2_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_gpio1_io25>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_08_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_sai3: pinmux_sai3 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_06_sai3_tx_bclk>,
<&iomuxc_gpio_sd_b1_07_sai3_tx_sync>,
<&iomuxc_gpio_sd_b1_08_sai3_tx_data>,
<&iomuxc_gpio_sd_b1_11_sai3_rx_data>,
<&iomuxc_gpio_emc_28_sai3_mclk>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>,
<&iomuxc_gpio_sd_b0_06_gpio3_io19>;
drive-strength = "r0";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_ad_b1_07_usdhc1_vselect>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_sd_b1_10_gpio3_io30>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* fast pinmux settings for USDHC (over 100 Mhz) */
pinmux_usdhc1_fast: pinmux_usdhc1_fast {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* medium pinmux settings for USDHC (under 100 Mhz) */
pinmux_usdhc1_med: pinmux_usdhc1_med {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* slow pinmux settings for USDHC (under 50 Mhz) */
pinmux_usdhc1_slow: pinmux_usdhc1_slow {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
pinmux_flexpwm1: pinmux_flexpwm1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_10_flexpwm1_pwma2>;
drive-strength = "r0-4";
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,208 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mimx93_a55.dtsi>
#include "imx93_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX93 A55";
compatible = "fsl,mimx93";
chosen {
zephyr,console = &lpuart2;
zephyr,shell-uart = &lpuart2;
zephyr,sram = &sram0;
};
cpus {
cpu@0 {
status = "disabled";
};
};
sram0: memory@d0000000 {
reg = <0xd0000000 DT_SIZE_M(1)>;
};
aliases {
led0 = &led_r;
led1 = &led_g;
sw0 = &btn_1;
};
leds {
compatible = "gpio-leds";
led_r: led_r {
label = "LED_R";
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
};
led_g: led_g {
label = "LED_G";
gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>;
};
led_b: led_b {
label = "LED_B";
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
btn_1: btn_1{
label = "BTN1";
gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
};
btn_2: btn_2{
label = "BTN2";
gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
};
};
board_exp_sel: board-exp-sel {
compatible = "imx93evk-exp-sel";
mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>;
mux = "A";
};
};
&enet {
status = "okay";
};
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rgmii";
status = "okay";
};
&enet_mdio {
pinctrl-0 = <&pinmux_mdio>;
pinctrl-names = "default";
status = "okay";
phy: phy@0 {
compatible = "realtek,rtl8211f";
reg = <2>;
status = "okay";
};
};
&lpuart1 {
status = "disabled";
current-speed = <115200>;
/* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&lpuart2 {
status = "okay";
current-speed = <115200>;
/* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
};
&lpi2c1 {
status = "disabled";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
};
&lpi2c2 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
pinctrl-0 = <&i2c2_default>;
pinctrl-names = "default";
mfd0:adp5585@34 {
compatible = "adi,adp5585";
reg = <0x34>;
status = "okay";
gpio_exp0: adp5585_gpio {
compatible = "adi,adp5585-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <13>;
gpio-reserved-ranges = <5 3>;
status = "okay";
/*
* This device has non-contiguous gpio range:
* GPIO Pin R0~R4 are gpio0~4
* GPIO Pin C0~C4 are gpio8~12
*/
};
};
};
&lpspi3 {
status = "disabled";
clock-frequency = <1000000>;
pinctrl-0 = <&spi3_default>;
pinctrl-names = "default";
};
&gpio1{
status = "okay";
};
&gpio2{
status = "okay";
};
&gpio3{
status = "okay";
};
&gpio4{
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,015 |
```cmake
``` | /content/code_sandbox/boards/nxp/imx93_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1 |
```unknown
#
#
# ARM Options
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_ARMV8_A_NS=y
# MMU Options
CONFIG_MAX_XLAT_TABLES=64
# Cache Options
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE_LINE_SIZE_DETECT=y
CONFIG_ICACHE_LINE_SIZE_DETECT=y
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_KERNEL_DIRECT_MAP=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```restructuredtext
.. _mimxrt1024_evk:
NXP MIMXRT1024-EVK
##################
Overview
********
The i.MX RT1024 expands the i.MX RT crossover processor families by providing
high-performance feature set in low-cost LQFP packages, further simplifying
board design and layout for customers. The i.MX RT1024 runs on the Arm
Cortex-M7 core at 500 MHz.
.. image:: mimxrt1024_evk.jpg
:align: center
:alt: MIMXRT1024-EVK
Hardware
********
- MIMXRT1024DAG5A MCU (600 MHz, 256 KB on-chip memory, 4096KB on-chip QSPI
flash)
- Memory
- 256 Mbit SDRAM
- 32 Mbit QSPI Flash
- TF socket for SD card
- Connectivity
- 10/100 Mbit/s Ethernet PHY
- Micro USB host and OTG connectors
- CAN transceivers
- Arduino interface
- Audio
- Audio Codec
- 4-pole audio headphone jack
- Microphone
- External speaker connection
- Power
- 5 V DC jack
- Debug
- JTAG 10-pin connector
- OpenSDA with DAPLink
- Sensor
- 6-axis FXOS8700CQ digital accelerometer and magnetometer
For more information about the MIMXRT1024 SoC and MIMXRT1024-EVK board, see
these references:
- `i.MX RT1024 Website`_
- `i.MX RT1024 Datasheet`_
- `i.MX RT1024 Reference Manual`_
- `MIMXRT1024-EVK Website`_
- `MIMXRT1024-EVK User Guide`_
- `MIMXRT1024-EVK Design Files`_
External Memory
===============
This platform has the following external memories:
+----------------+------------+-------------------------------------+
| Device | Controller | Status |
+================+============+=====================================+
| MT48LC16M16A2P | SEMC | Enabled via device configuration |
| | | data block, which sets up SEMC at |
| | | boot time |
+----------------+------------+-------------------------------------+
Supported Features
==================
The mimxrt1024_evk board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1064_evk board may have additional features
already supported, which can also be re-used on this mimxrt1024_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | QSPI flash |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| HWINFO | on-chip | reset cause |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_AD_B1_08 | GPIO | LED |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_06 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_07 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW4 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_04 | ENET_RST | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_08 | ENET_REF_CLK | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | ENET_RX_DATA00/LPSPI1_SCK | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_11 | ENET_RX_EN/LPSPI1_PCS0 | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | ENET_RX_ER/LPSPI1_SDO | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | ENET_TX_EN/LPSPI1_SDI | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_15 | ENET_TX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | ENET_INT | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_41 | ENET_MDC | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_40 | ENET_MDIO | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_00 | FLEXCAN1_TX | CAN TX |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_01 | FLEXCAN1_RX | CAN RX |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_02 | LPI2C4_SCL | I2C SCL |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_03 | LPI2C4_SDA | I2C SDA |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_05 | DQS | QSPI flash |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_11 | ADC1 | ADC1 Channel 11 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_10 | ADC1 | ADC1 Channel 10 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_10 | FLEXPWM1 | FLEXPWM1 Channel A2 |
+---------------+-----------------+---------------------------+
System Clock
============
The MIMXRT1024 SoC is configured to use SysTick as the system clock source,
running at 500MHz.
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1024 SoC has eight UARTs. One is configured for the console and the
remaining are not used.
Programming and Debugging
*************************
This board supports 2 debug host tools. Please install your preferred host
tool, then follow the instructions in `Configuring a Debug Probe`_ to
configure the board appropriately.
* :ref:`jlink-debug-host-tools` (Default, Supported by NXP)
* :ref:`pyocd-debug-host-tools` (Not supported by NXP)
Configuring a Debug Probe
=========================
For the RT1024, J47/J48 are the SWD isolation jumpers, J42 is the DFU
mode jumper, and J55 is the 10 pin JTAG/SWD header.
.. include:: ../../common/rt1xxx-lpclink2-debug.rst
:start-after: rt1xxx-lpclink2-probes
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers J50 and J46 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J23.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1024_evk
:goals: flash
Open a serial terminal, reset the board (press the SW9 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.4.0-rc1 *****
Hello World! mimxrt1024_evk
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1024_evk
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.4.0-rc1 *****
Hello World! mimxrt1024_evk
.. _MIMXRT1024-EVK Website:
path_to_url
.. _MIMXRT1024-EVK User Guide:
path_to_url
.. _MIMXRT1024-EVK Design Files:
path_to_url
.. _i.MX RT1024 Website:
path_to_url
.. _i.MX RT1024 Datasheet:
path_to_url
.. _i.MX RT1024 Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1024_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,560 |
```c
/**
*/
#include <zephyr/kernel.h>
#include <zephyr/init.h>
#include <zephyr/devicetree.h>
#include <zephyr/logging/log.h>
#include <zephyr/drivers/gpio.h>
LOG_MODULE_REGISTER(board_control, CONFIG_BOARD_MIMX93_EVK_LOG_LEVEL);
#if DT_HAS_COMPAT_STATUS_OKAY(imx93evk_exp_sel) && IS_ENABLED(CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT)
#define BOARD_EXP_SEL_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(imx93evk_exp_sel)
#define BOARD_EXP_SEL_MUX_A (0U)
#define BOARD_EXP_SEL_MUX_B (1U)
static int board_init_exp_sel(void)
{
int rc = 0;
const struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(BOARD_EXP_SEL_NODE, mux_gpios);
uint32_t pin_state = DT_ENUM_IDX(BOARD_EXP_SEL_NODE, mux);
if (!gpio_is_ready_dt(&mux)) {
LOG_ERR("EXP_SEL Pin port is not ready");
return -ENODEV;
}
#if defined(CONFIG_CAN)
if (pin_state != BOARD_EXP_SEL_MUX_A) {
LOG_WRN("CAN is enabled, EXP_SEL overrides to A");
pin_state = BOARD_EXP_SEL_MUX_A;
}
#endif /* CONFIG_CAN */
rc = gpio_pin_configure_dt(&mux, pin_state);
if (rc) {
LOG_ERR("Write EXP_SEL Pin error %d", rc);
return rc;
}
LOG_INF("EXP_SEL mux %c with priority %d", pin_state ? 'B' : 'A',
CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO);
return 0;
}
SYS_INIT(board_init_exp_sel, POST_KERNEL, CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO);
#endif
/*
* DT_HAS_COMPAT_STATUS_OKAY(imx93evk_exp_sel) && \
* IS_ENABLED(CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT)
*/
``` | /content/code_sandbox/boards/nxp/imx93_evk/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 409 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/mimx9352cvuxk-pinctrl.dtsi>
&pinctrl {
uart1_default: uart1_default {
group0 {
pinmux = <&iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx>,
<&iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx>;
bias-pull-up;
slew-rate = "slightly_fast";
drive-strength = "x5";
};
};
uart2_default: uart2_default {
group0 {
pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>,
<&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>;
bias-pull-up;
slew-rate = "slightly_fast";
drive-strength = "x5";
};
};
i2c1_default: i2c1_default {
group0 {
pinmux = <&iomuxc1_i2c1_scl_lpi2c_scl_lpi2c1_scl>,
<&iomuxc1_i2c1_sda_lpi2c_sda_lpi2c1_sda>;
drive-strength = "x5";
drive-open-drain;
slew-rate = "fast";
input-enable;
};
};
i2c2_default: i2c2_default {
group0 {
pinmux = <&iomuxc1_i2c2_scl_lpi2c_scl_lpi2c2_scl>,
<&iomuxc1_i2c2_sda_lpi2c_sda_lpi2c2_sda>;
drive-strength = "x5";
drive-open-drain;
slew-rate = "fast";
input-enable;
};
};
i2c3_default: i2c3_default {
group0 {
pinmux = <&iomuxc1_gpio_io01_lpi2c_scl_lpi2c3_scl>,
<&iomuxc1_gpio_io00_lpi2c_sda_lpi2c3_sda>;
drive-strength = "x5";
drive-open-drain;
slew-rate = "fast";
input-enable;
};
};
i2c4_default: i2c4_default {
group0 {
pinmux = <&iomuxc1_gpio_io03_lpi2c_scl_lpi2c4_scl>,
<&iomuxc1_gpio_io02_lpi2c_sda_lpi2c4_sda>;
drive-strength = "x5";
drive-open-drain;
slew-rate = "fast";
input-enable;
};
};
spi3_default: spi3_default {
group0 {
pinmux = <&iomuxc1_gpio_io07_lpspi_pcs_lpspi3_pcs1>,
<&iomuxc1_gpio_io08_lpspi_pcs_lpspi3_pcs0>,
<&iomuxc1_gpio_io09_lpspi_sin_lpspi3_sin>,
<&iomuxc1_gpio_io10_lpspi_sout_lpspi3_sout>,
<&iomuxc1_gpio_io11_lpspi_sck_lpspi3_sck>;
slew-rate = "fast";
drive-strength = "x5";
};
};
pinmux_mdio: pinmux_mdio {
group0 {
pinmux = <&iomuxc1_enet2_mdc_enet_mdc_enet1_mdc>,
<&iomuxc1_enet2_mdio_enet_mdio_enet1_mdio>;
bias-pull-down;
slew-rate = "slightly_fast";
drive-strength = "x6";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc1_enet2_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
<&iomuxc1_enet2_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
<&iomuxc1_enet2_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
<&iomuxc1_enet2_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
<&iomuxc1_enet2_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>,
<&iomuxc1_enet2_td0_enet_rgmii_td_enet1_rgmii_td0>,
<&iomuxc1_enet2_td1_enet_rgmii_td_enet1_rgmii_td1>,
<&iomuxc1_enet2_td2_enet_rgmii_td_enet1_rgmii_td2>,
<&iomuxc1_enet2_td3_enet_rgmii_td_enet1_rgmii_td3>,
<&iomuxc1_enet2_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
bias-pull-down;
slew-rate = "slightly_fast";
drive-strength = "x6";
};
group1 {
pinmux = <&iomuxc1_enet2_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
<&iomuxc1_enet2_txc_enet_rgmii_txc_enet1_rgmii_txc>;
bias-pull-down;
slew-rate = "fast";
drive-strength = "x6";
};
};
};
``` | /content/code_sandbox/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,294 |
```unknown
config BOARD_IMX93_EVK
select SOC_MIMX9352_A55 if BOARD_IMX93_EVK_MIMX9352_A55
select SOC_PART_NUMBER_MIMX9352DVVXM
``` | /content/code_sandbox/boards/nxp/imx93_evk/Kconfig.imx93_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```yaml
board:
name: imx93_evk
vendor: nxp
socs:
- name: mimx9352
``` | /content/code_sandbox/boards/nxp/imx93_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```yaml
#
#
#
identifier: imx93_evk/mimx9352/a55
name: NXP i.MX93 EVK A55
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
supported:
- gpio
- uart
- i2c
- spi
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
# i.MX 93 EVK board configuration
config BOARD_MIMX93_EVK_EXP_SEL_INIT
bool "Configure i.MX 93 EVK board mux control during init"
default n
config BOARD_MIMX93_EVK_EXP_SEL_INIT_PRIO
int "i.MX 93 EVK board mux control init priority"
default 60
module = BOARD_MIMX93_EVK
module-str = Board Control
source "subsys/logging/Kconfig.template.log_config"
``` | /content/code_sandbox/boards/nxp/imx93_evk/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
if BOARD_IMX93_EVK
if BOARD_IMX93_EVK_MIMX9352_A55
if BOARD_MIMX93_EVK_EXP_SEL_INIT
# Enable I2C, MFD, MFD_APD5585 and GPIO_ADP5585
config GPIO
default y
config MFD_ADP5585_INIT_PRIORITY
default 55
config GPIO_ADP5585_INIT_PRIORITY
default 56
endif # BOARD_MIMX93_EVK_EXP_SEL_INIT
if NETWORKING
config NET_L2_ETHERNET
default y
config NET_TX_STACK_SIZE
default 8192
config NET_RX_STACK_SIZE
default 8192
if NET_TCP
config NET_TCP_WORKQ_STACK_SIZE
default 8192
endif # NET_TCP
if NET_MGMT_EVENT
config NET_MGMT_EVENT_STACK_SIZE
default 8192
endif # NET_MGMT_EVENT
if NET_SOCKETS_SERVICE
config NET_SOCKETS_SERVICE_STACK_SIZE
default 8192
endif # NET_SOCKETS_SERVICE
endif # NETWORKING
endif # BOARD_IMX93_EVK_MIMX9352_A55
endif # BOARD_IMX93_EVK
``` | /content/code_sandbox/boards/nxp/imx93_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 246 |
```yaml
description: |
The i.MX 93 EVK boards has a series of MUXes that selects between 2 pin
functions. They are controlled by EXP_SEL signal from gpio_exp0, an
ADP5585 GPIO expander.
compatible: "imx93evk-exp-sel"
include: base.yaml
properties:
mux-gpios:
type: phandle-array
required: true
description: Pin used to select the MUX
mux:
type: string
required: true
enum:
- "A"
- "B"
description: MUX choice
``` | /content/code_sandbox/boards/nxp/imx93_evk/dts/bindings/imx93evk-exp-sel.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 135 |
```cmake
#
#
#
if(CONFIG_SOC_MCXN947_CPU0)
board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load")
board_runner_args(linkserver "--device=MCXN947:FRDM-MCXN947")
board_runner_args(linkserver "--core=cm33_core0")
board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx")
board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000")
# Linkserver v1.4.85 and earlier do not include the secure regions in the
# MCXN947 memory map, so we add them here
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
\"size\":\"0x00060000\",\"type\":\"RAM\"\}")
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30060000\",\
\"size\":\"0x00008000\",\"type\":\"RAM\"\}")
# Define region for peripherals
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
\"size\":\"0x00140000\",\"type\":\"RAM\"\}")
else()
message(FATAL_ERROR "Support for cpu1 not available yet")
endif()
# Pyocd support added with the NXP.MCXN947_DFP.17.0.0.pack CMSIS Pack
board_runner_args(pyocd "--target=mcxn947")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 387 |
```yaml
#
#
#
identifier: frdm_mcxn947/mcxn947/cpu0
name: NXP FRDM MCXN947 (CPU0)
type: mcu
arch: arm
ram: 320
flash: 2048
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- can
- dma
- gpio
- spi
- dac
- i2c
- watchdog
- pwm
- counter
- sdhc
- regulator
- adc
- usb_device
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 137 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```restructuredtext
.. _imx93_evk:
NXP i.MX93 EVK (Cortex-A55)
############################
Overview
********
The i.MX93 Evaluation Kit (MCIMX93-EVK board) is a platform designed to show
the most commonly used features of the i.MX 93 Applications Processor in a
small and low cost package. The MCIMX93-EVK board is an entry-level development
board, which helps developers to get familiar with the processor before
investing a large amount of resources in more specific designs.
i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single
Cortex-M33 core. Zephyr OS is ported to run on one of the Cortex-A55 core.
- Board features:
- RAM: 2GB LPDDR4
- Storage:
- SanDisk 16GB eMMC5.1
- microSD Socket
- Wireless:
- Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC,
which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2,
and 802.15.4
- USB:
- Two USB 2.0 Type C connectors
- Ethernet
- PCI-E M.2
- Connectors:
- 40-Pin Dual Row Header
- LEDs:
- 1x Power status LED
- 2x UART LED
- Debug
- JTAG 20-pin connector
- MicroUSB for UART debug, two COM ports for A55 and M33
Supported Features
==================
The Zephyr mimx93_evk board Cortex-A Core configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| GIC-v4 | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | GPIO |
+-----------+------------+-------------------------------------+
| TPM | on-chip | TPM Counter |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet port |
+-----------+------------+-------------------------------------+
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 24 MHz.
Cortex-A55 Core runs up to 1.7 GHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART4.
Board MUX Control
-----------------
This board configuration uses a series of digital multiplexers to switch between
different board functions. The multiplexers are controlled by a GPIO signal called
``EXP_SEL`` from onboard GPIO expander ADP5585. It can be configured to select
function set "A" or "B" by dts configuration if board control module is enabled.
The following dts node is defined:
.. code-block:: dts
board_exp_sel: board-exp-sel {
compatible = "imx93evk-exp-sel";
mux-gpios = <&gpio_exp0 4 GPIO_ACTIVE_HIGH>;
mux = "A";
};
Following steps are required to configure the ``EXP_SEL`` signal:
1. Enable Kconfig option ``CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT``.
2. Select ``mux="A";`` or ``mux="B";`` in ``&board_exp_sel`` devicetree node.
Kconfig option ``CONFIG_BOARD_MIMX93_EVK_EXP_SEL_INIT`` is enabled if a board
function that requires configuring the mux is enabled. The MUX option is
automatically selected if certain board function is enabled, and takes precedence
over dts config. For instance, if ``CONFIG_CAN`` is enabled, MUX A is selected
even if ``mux="B";`` is configured in dts, and an warning would be reported in
the log.
Programming and Debugging
*************************
Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
.. code-block:: console
fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000
Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
.. code-block:: console
fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: mimx93_evk/mimx9352/a55
:goals: run
This will build an image with the synchronization sample app, boot it and
display the following ram console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v3.2.0-8-g1613870534a0 ***
thread_a: Hello World from cpu 0 on mimx93_evk_a55!
thread_b: Hello World from cpu 0 on mimx93_evk_a55!
thread_a: Hello World from cpu 0 on mimx93_evk_a55!
thread_b: Hello World from cpu 0 on mimx93_evk_a55!
References
==========
More information can refer to NXP official website:
`NXP website`_.
.. _NXP website:
path_to_url
Using the SOF-specific variant
******************************
Purpose
=======
Since this board doesn't have a DSP, an alternative for people who might be interested
in running SOF on this board had to be found. The alternative consists of running SOF
on an A55 core using Jailhouse as a way to "take away" one A55 core from Linux and
assign it to Zephyr with `SOF`_.
.. _SOF:
path_to_url
What is Jailhouse?
==================
Jailhouse is a light-weight hypervisor that allows the partitioning of hardware resources.
For more details on how this is done and, generally, about Jailhouse, please see: `1`_,
`2`_ and `3`_. The GitHub repo can be found `here`_.
.. _1:
path_to_url
.. _2:
path_to_url
.. _3:
path_to_url
.. _here:
path_to_url
How does it work?
=================
Firstly, we need to explain a few Jailhouse concepts that will be referred to later on:
* **Cell**: refers to a set of hardware resources that the OS assigned to this
cell can utilize.
* **Root cell**: refers to the cell in which Linux is running. This is the main cell which
will contain all the hardware resources that Linux will utilize and will be used to assign
resources to the inmates. The inmates CANNOT use resources such as the CPU that haven't been
assigned to the root cell.
* **Inmate**: refers to any other OS that runs alongside Linux. The resources an inmate will
use are taken from the root cell (the cell Linux is running in).
SOF+Zephyr will run as an inmate, alongside Linux, on core 1 of the board. This means that
said core will be taken away from Linux and will only be utilized by Zephyr.
The hypervisor restricts inmate's/root's access to certain hardware resources using
the second-stage translation table which is based on the memory regions described in the
configuration files. Please consider the following scenario:
Root cell wants to use the **UART** which let's say has its registers mapped in
the **[0x0 - 0x42000000]** region. If the inmate wants to use the same **UART** for
some reason then we'd need to also add this region to inmate's configuration
file and add the **JAILHOUSE_MEM_ROOTSHARED** flag. This flag means that the inmate
is allowed to share this region with the root. If this region is not set in
the inmate's configuration file and Zephyr (running as an inmate here) tries
to access this region this will result in a second stage translation fault.
Notes:
* Linux and Zephyr are not aware that they are running alongside each other.
They will only be aware of the cores they have been assigned through the config
files (there's a config file for the root and one for each inmate).
Architecture overview
=====================
The architecture overview can be found at this `location`_. (latest status update as of now
and the only one containing diagrams).
.. _location:
path_to_url
How to use this board?
======================
This board has been designed for SOF so it's only intended to be used with SOF.
TODO: document the SOF build process for this board. For now, the support for
i.MX93 is still in review and has yet to merged on SOF side.
``` | /content/code_sandbox/boards/nxp/imx93_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,126 |
```unknown
/*
*/
#include <nxp/mcx/MCXN947VDF-pinctrl.h>
&pinctrl {
pinmux_flexcomm1_lpspi: pinmux_flexcomm1_lpspi {
group0 {
pinmux = <FC1_P0_PIO0_24>,
<FC1_P1_PIO0_25>,
<FC1_P2_PIO0_26>,
<FC1_P3_PIO0_27>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c {
group0 {
pinmux = <FC2_P0_PIO4_0>,
<FC2_P1_PIO4_1>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};
pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart {
group0 {
pinmux = <FC2_P2_PIO4_2>,
<FC2_P3_PIO4_3>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
group0 {
pinmux = <FC4_P0_PIO1_8>,
<FC4_P1_PIO1_9>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexspi: pinmux_flexspi {
group0 {
pinmux = <FLEXSPI0_A_SS0_b_PIO3_0>,
<FLEXSPI0_A_SCLK_PIO3_7>,
<FLEXSPI0_A_DQS_PIO3_6>,
<FLEXSPI0_A_DATA0_PIO3_8>,
<FLEXSPI0_A_DATA1_PIO3_9>;
input-enable;
slew-rate = "fast";
drive-strength = "low";
};
group1 {
pinmux = <FLEXSPI0_A_DATA2_PIO3_10>,
<FLEXSPI0_A_DATA3_PIO3_11>;
input-enable;
slew-rate = "fast";
drive-strength = "low";
bias-pull-up;
};
};
pinmux_dac0: pinmux_dac0 {
group0 {
pinmux = <DAC0_OUT_PIO4_2>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_enet_qos: pinmux_enet_qos {
mdio_group {
pinmux = <ENET0_MDC_PIO1_20>,
<ENET0_MDIO_PIO1_21>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
mac_group {
pinmux = <ENET0_RXDV_PIO1_13>,
<ENET0_RXD0_PIO1_14>,
<ENET0_RXD1_PIO1_15>,
<ENET0_TX_CLK_PIO1_4>,
<ENET0_TXEN_PIO1_5>,
<ENET0_TXD0_PIO1_6>,
<ENET0_TXD1_PIO1_7>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 {
group0 {
pinmux = <PWM1_A0_PIO2_6>,
<PWM1_B0_PIO2_7>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 {
group0 {
pinmux = <PWM1_A1_PIO2_4>,
<PWM1_B1_PIO2_5>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 {
group0 {
pinmux = <PWM1_A2_PIO2_2>,
<PWM1_B2_PIO2_3>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_usdhc0: pinmux_usdhc0 {
group0 {
pinmux = <SDHC0_CMD_PIO2_5>,
<SDHC0_D0_PIO2_3>,
<SDHC0_D1_PIO2_2>,
<SDHC0_D2_PIO2_7>,
<SDHC0_D3_PIO2_6>;
slew-rate = "fast";
drive-strength = "low";
bias-pull-up;
input-enable;
};
group1 {
pinmux = <SDHC0_CLK_PIO2_4>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_lpadc0: pinmux_lpadc0 {
group0 {
pinmux = <ADC0_A2_PIO4_23>,
<ADC0_A1_PIO4_15>,
<ADC0_B1_PIO4_19>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_lpcmp0: pinmux_lpcmp0 {
group0 {
pinmux = <CMP0_IN0_PIO1_0>;
drive-strength = "low";
slew-rate = "fast";
bias-pull-up;
};
};
pinmux_flexcan0: pinmux_flexcan0 {
group0 {
pinmux = <CAN0_TXD_PIO1_10>,
<CAN0_RXD_PIO1_11>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexio_lcd: pinmux_flexio_lcd {
group0 {
pinmux = <FLEXIO0_D16_PIO2_8>,
<FLEXIO0_D17_PIO2_9>,
<FLEXIO0_D18_PIO2_10>,
<FLEXIO0_D19_PIO2_11>,
<FLEXIO0_D20_PIO4_12>,
<FLEXIO0_D21_PIO4_13>,
<FLEXIO0_D22_PIO4_14>,
<FLEXIO0_D23_PIO4_15>,
<FLEXIO0_D24_PIO4_16>,
<FLEXIO0_D25_PIO4_17>,
<FLEXIO0_D26_PIO4_18>,
<FLEXIO0_D27_PIO4_19>,
<FLEXIO0_D28_PIO4_20>,
<FLEXIO0_D29_PIO4_21>,
<FLEXIO0_D30_PIO4_22>,
<FLEXIO0_D31_PIO4_23>,
<PIO0_7>,
<PIO0_12>,
<PIO4_7>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
group1 {
pinmux = <FLEXIO0_D0_PIO0_8>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
};
group2 {
pinmux = <FLEXIO0_D1_PIO0_9>;
slew-rate = "slow";
drive-strength = "low";
input-enable;
bias-pull-up;
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,858 |
```unknown
config BOARD_FRDM_MCXN947
select SOC_MCXN947_CPU0 if BOARD_FRDM_MCXN947_MCXN947_CPU0
select SOC_MCXN947_CPU1 if BOARD_FRDM_MCXN947_MCXN947_CPU1
select SOC_PART_NUMBER_MCXN947VDF
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/Kconfig.frdm_mcxn947 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```yaml
board:
name: frdm_mcxn947
vendor: nxp
socs:
- name: mcxn947
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
if BOARD_FRDM_MCXN947
config NET_L2_ETHERNET
default y if NETWORKING
if SD_STACK
# SD stack requires larger main stack size
config MAIN_STACK_SIZE
default 1536
endif
if BOOTLOADER_MCUBOOT
choice MCUBOOT_BOOTLOADER_MODE
# Board only supports MCUBoot via "upgrade only" method:
default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY
endchoice
endif #BOOTLOADER_MCUBOOT
endif
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```unknown
/*
*
*/
#include "frdm_mcxn947-pinctrl.dtsi"
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases{
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
sdhc0 = &usdhc0;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
label = "Green LED";
status = "disabled";
};
blue_led: led_2 {
gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
label = "Blue LED";
status = "disabled";
};
red_led: led_3 {
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
label = "Red LED";
status = "disabled";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpio0 23 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
status = "disabled";
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_1>;
status = "disabled";
};
};
/*
* This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface.
*/
nxp_lcd_8080_connector: lcd-8080-connector {
compatible = "nxp,lcd-8080";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <9 0 &gpio4 6 0>, /* Pin 9, LCD touch INT */
<10 0 &gpio4 5 0>, /* Pin 10, LCD backlight control */
<11 0 &gpio4 7 0>; /* Pin 11, LCD and touch reset */
};
};
&flexcomm1_lpspi1 {
pinctrl-0 = <&pinmux_flexcomm1_lpspi>;
pinctrl-names = "default";
};
nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
pinctrl-0 = <&pinmux_flexcomm2_lpi2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
&flexcomm2_lpuart2 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm2_lpuart>;
pinctrl-names = "default";
};
&flexcomm4_lpuart4 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
pinctrl-names = "default";
};
/*
* MCXN947 board uses OS timer as the kernel timer
* In case we need to switch to SYSTICK timer, then
* replace &os_timer with &systick
*/
&os_timer {
status = "disabled";
};
&systick {
status = "okay";
};
&flash {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
/* For the MCUBoot "upgrade only" method,
* the slot sizes must be equal.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(992)>;
};
slot1_partition: partition@108000 {
label = "image-1";
reg = <0x00108000 DT_SIZE_K(992)>;
};
/* storage_partition is placed in WINBOND flash memory*/
};
};
&flexspi {
pinctrl-0 = <&pinmux_flexspi>;
pinctrl-names = "default";
ahb-prefetch;
ahb-bufferable;
ahb-cacheable;
ahb-read-addr-opt;
combination-mode;
rx-clock-source = <1>;
/* WINBOND flash memory*/
w25q64jvssiq: w25q64jvssiq@0 {
compatible = "nxp,imx-flexspi-nor";
status = "disabled";
size = <67108864>;
reg = <0>;
spi-max-frequency = <133000000>;
jedec-id = [ef 40 17];
erase-block-size = <4096>;
write-block-size = <1>;
cs-interval-unit = <1>;
cs-interval = <2>;
cs-hold-time = <3>;
cs-setup-time = <3>;
data-valid-time = <2>;
column-space = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
label = "storage";
reg = <0x0 DT_SIZE_M(8)>;
};
};
};
};
&dac0 {
pinctrl-0 = <&pinmux_dac0>;
pinctrl-names = "default";
};
&enet {
pinctrl-0 = <&pinmux_enet_qos>;
pinctrl-names = "default";
};
&enet_mac {
phy-connection-type = "rmii";
zephyr,random-mac-address;
phy-handle = <&phy>;
};
&enet_mdio {
phy: ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0>;
status = "okay";
};
};
&flexpwm1_pwm0 {
pinctrl-0 = <&pinmux_flexpwm1_pwm0>;
pinctrl-names = "default";
};
&usdhc0 {
pinctrl-0 = <&pinmux_usdhc0>;
pinctrl-1 = <&pinmux_usdhc0>;
pinctrl-2 = <&pinmux_usdhc0>;
cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "slow", "med";
no-1-8-v;
};
&lpadc0 {
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};
nxp_flexio_lcd: &flexio0_lcd {
/* DMA channels 0, muxed to FlexIO TX */
dmas = <&edma0 0 61>;
dma-names = "tx";
shifters-count = <8>;
timers-count = <1>;
enwr-pin = <1>;
rd-pin = <0>;
data-pin-start = <16>;
reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
rs-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pinmux_flexio_lcd>;
pinctrl-names = "default";
};
&lpcmp0 {
pinctrl-0 = <&pinmux_lpcmp0>;
pinctrl-names = "default";
};
&flexcan0 {
pinctrl-0 = <&pinmux_flexcan0>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,758 |
```unknown
config BOARD_INIT_PRIORITY
int "Board initialization priority"
default 1
help
Board initialization priority.
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```c
/*
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <fsl_spc.h>
#include <soc.h>
#if CONFIG_USB_DC_NXP_EHCI
#include "usb_phy.h"
#include "usb.h"
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x04U)
#define BOARD_USB_PHY_TXCAL45DP (0x07U)
#define BOARD_USB_PHY_TXCAL45DM (0x07U)
#endif
/* Board xtal frequency in Hz */
#define BOARD_XTAL0_CLK_HZ 24000000U
/* Core clock frequency: 150MHz */
#define CLOCK_INIT_CORE_CLOCK 150000000U
/* System clock frequency. */
extern uint32_t SystemCoreClock;
__ramfunc static void enable_lpcac(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK |
SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK);
}
/* Update Active mode voltage for OverDrive mode. */
void power_mode_od(void)
{
/* Set the DCDC VDD regulator to 1.2 V voltage level */
spc_active_mode_dcdc_option_t opt = {
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
};
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
spc_active_mode_core_ldo_option_t ldo_opt = {
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
};
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
spc_sram_voltage_config_t cfg = {
.operateVoltage = kSPC_sramOperateAt1P2V,
.requestVoltageUpdate = true,
};
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
}
static int frdm_mcxn947_init(void)
{
enable_lpcac();
power_mode_od();
/* Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
/* FRO OSC setup - begin, enable the FRO for safety switching */
/* Switch to FRO 12M first to ensure we can change the clock setting */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
/* Enable FRO HF(48MHz) output */
CLOCK_SetupFROHFClocking(48000000U);
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
/* Call function flexspi_clock_safe_config() to move FleXSPI clock to a stable
* clock source when updating the PLL if in XIP (execute code from FlexSPI memory
*/
flexspi_clock_safe_config();
#endif
/* Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
/* Configure PLL0 to the desired values */
CLOCK_SetPLL0Freq(&pll0Setup);
/* PLL0 Monitor is disabled */
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
/* Switch MAIN_CLK to PLL0 */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
/* Set AHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan0), okay)
/* Set up PLL1 for 80 MHz FlexCAN clock */
const pll_setup_t pll1Setup = {
.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) |
SCG_SPLLCTRL_SELP(13U),
.pllndiv = SCG_SPLLNDIV_NDIV(3U),
.pllpdiv = SCG_SPLLPDIV_PDIV(1U),
.pllmdiv = SCG_SPLLMDIV_MDIV(10U),
.pllRate = 80000000U
};
/* Configure PLL1 to the desired values */
CLOCK_SetPLL1Freq(&pll1Setup);
/* PLL1 Monitor is disabled */
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);
/* Set PLL1 CLK0 divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay)
CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
CLOCK_EnableClock(kCLOCK_Gpio0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
CLOCK_EnableClock(kCLOCK_Gpio1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
CLOCK_EnableClock(kCLOCK_Gpio2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
CLOCK_EnableClock(kCLOCK_Gpio3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
CLOCK_EnableClock(kCLOCK_Gpio4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
CLOCK_EnableClock(kCLOCK_Gpio5);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(dac0), okay)
SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0);
CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u);
CLOCK_AttachClk(kFRO_HF_to_DAC0);
CLOCK_EnableClock(kCLOCK_Dac0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(dac1), okay)
SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac1);
CLOCK_SetClkDiv(kCLOCK_DivDac1Clk, 1u);
CLOCK_AttachClk(kFRO_HF_to_DAC1);
CLOCK_EnableClock(kCLOCK_Dac1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
CLOCK_AttachClk(kNONE_to_ENETRMII);
CLOCK_EnableClock(kCLOCK_Enet);
SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK;
SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK;
/* rmii selection for this board */
SYSCON->ENET_PHY_INTF_SEL = SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(wwdt0), okay)
CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan0), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay)
CLOCK_SetClkDiv(kCLOCK_DivUSdhcClk, 1u);
CLOCK_AttachClk(kFRO_HF_to_USDHC);
#endif
#if CONFIG_FLASH_MCUX_FLEXSPI_NOR
/* We downclock the FlexSPI to 50MHz, it will be set to the
* optimum speed supported by the Flash device during FLEXSPI
* Init
*/
flexspi_clock_set_freq(MCUX_FLEXSPI_CLK, MHZ(50));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(vref), okay)
CLOCK_EnableClock(kCLOCK_Vref);
SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay)
CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1U);
CLOCK_AttachClk(kFRO_HF_to_ADC0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
usb_phy_config_struct_t usbPhyConfig = {
BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
};
SPC0->ACTIVE_VDELAY = 0x0500;
/* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default,
* CORELDO is 1.0V)
*/
SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
/* Wait until it is done */
while (SPC0->SC & SPC_SC_BUSY_MASK) {
};
if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
SCG0->TRIM_LOCK = 0x5a5a0001U;
SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
/* wait LDO ready */
while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {
};
}
SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |
SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
/* xtal = 20 ~ 30MHz */
SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
while (1) {
if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
break;
}
}
SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |
SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
CLOCK_EnableClock(kCLOCK_UsbHs);
CLOCK_EnableClock(kCLOCK_UsbHsPhy);
CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
CLOCK_EnableUsbhsClock();
USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpcmp0), okay)
CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U);
CLOCK_AttachClk(kFRO12M_to_CMP0F);
SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac));
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(lptmr0), okay)
CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVsys);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio0), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1u);
CLOCK_AttachClk(kPLL0_to_FLEXIO);
#endif
/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
return 0;
}
SYS_INIT(frdm_mcxn947_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,366 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mcxn94x.dtsi>
#include "frdm_mcxn947.dtsi"
/ {
model = "NXP FRDM_N94 board";
compatible = "nxp,mcxn947", "nxp,mcx";
cpus {
/delete-node/ cpu@1;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash;
zephyr,flash-controller = &fmu;
zephyr,code-partition = &slot0_partition;
zephyr,console = &flexcomm4_lpuart4;
zephyr,shell-uart = &flexcomm4_lpuart4;
zephyr,canbus = &flexcan0;
};
aliases{
watchdog0 = &wwdt0;
pwm-0 = &flexpwm1_pwm0;
};
};
/*
* Default for this board is to allocate SRAM0-5 to cpu0 but the
* application can have an application specific device tree to
* allocate the SRAM0-7 differently.
*
* For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
* for cpu1. This would require the value of sram0 to have a DT_SIZE_K
* of 384. You would have to make updates to cpu1 sram settings as well.
*/
&sram0 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(320)>;
};
&gpio4 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&edma0 {
status = "okay";
};
&flexcomm1 {
status = "okay";
};
&flexcomm1_lpspi1 {
status = "okay";
};
&flexcomm2 {
status = "okay";
};
&flexcomm2_lpi2c2 {
status = "okay";
};
/*
*LPFLEXCOMM supports UART and I2C on the same instance, enable this for
* LFLEXCOMM2
*/
&flexcomm2_lpuart2 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&flexcomm4_lpuart4 {
status = "okay";
};
&flexspi {
status = "okay";
};
&w25q64jvssiq {
status = "okay";
};
&dac0 {
status = "okay";
};
&enet {
status = "okay";
};
&enet_mac {
status = "okay";
};
&enet_mdio {
status = "okay";
};
&wwdt0 {
status = "okay";
};
&flexpwm1_pwm0 {
status = "okay";
};
&flexcan0 {
status = "okay";
};
&ctimer0 {
status = "okay";
};
&usdhc0 {
status = "okay";
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&vref {
status = "okay";
};
&lpadc0 {
status = "okay";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&lpcmp0 {
status = "okay";
};
&lptmr0 {
status = "okay";
};
&flexio0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 775 |
```cmake
#
#
#
board_runner_args(linkserver "--device=MKE15Z256xxx7:FRDM-KE15Z")
board_runner_args(jlink "--device=MKE15Z256xxx7" "--reset-after-load")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
/*
*/
#include <nxp/kinetis/MKE15Z256VLL7-pinctrl.h>
&pinctrl {
lpuart1_default: lpuart1_default {
group0 {
pinmux = <LPUART1_RX_PTC6>,
<LPUART1_TX_PTC7>;
drive-strength = "low";
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/frdm_ke15z-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```yaml
identifier: frdm_ke15z
name: NXP FRDM-KE15Z
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
flash: 256
ram: 24
supported:
- gpio
- uart
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/frdm_ke15z.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Clock Control
CONFIG_CLOCK_CONTROL=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/frdm_ke15z_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 53 |
```yaml
board:
name: frdm_ke15z
vendor: nxp
socs:
- name: mke15z7
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ke1xz.dtsi>
#include "frdm_ke15z-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP Freedom KE15Z board";
compatible = "nxp,ke15z", "nxp,mke15z7";
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
sw0 = &user_button_0;
sw1 = &user_button_1;
};
chosen {
zephyr,sram = &sram_u;
zephyr,flash = &flash0;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpiod 0 GPIO_ACTIVE_LOW>;
label = "RED LED";
};
green_led: led_1 {
gpios = <&gpiod 16 GPIO_ACTIVE_LOW>;
label = "GREEN LED";
};
blue_led: led_2 {
gpios = <&gpiod 15 GPIO_ACTIVE_LOW>;
label = "BLUE LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: button_0 {
label = "User SW3";
gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_1: button_1 {
label = "User SW2";
gpios = <&gpiob 11 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&lpuart1_default>;
pinctrl-names = "default";
};
&gpiob {
status = "okay";
};
&gpiod {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/frdm_ke15z.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 486 |
```unknown
config BOARD_FRDM_KE15Z
select SOC_MKE15Z7
select SOC_PART_NUMBER_MKE15Z256VLL7
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/Kconfig.frdm_ke15z | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _frdm_mcxn947:
NXP FRDM-MCXN947
################
Overview
********
FRDM-MCXN947 are compact and scalable development boards for rapid prototyping of
MCX N94 and N54 MCUs. They offer industry standard headers for easy access to the
MCUs I/Os, integrated open-standard serial interfaces, external flash memory and
an on-board MCU-Link debugger. MCX N Series are high-performance, low-power
microcontrollers with intelligent peripherals and accelerators providing multi-tasking
capabilities and performance efficiency.
.. image:: frdm_mcxn947.webp
:align: center
:alt: FRDM-MCXN947
Hardware
********
- MCX-N947 Dual Arm Cortex-M33 microcontroller running at 150 MHz
- 2MB dual-bank on chip Flash
- 512 KB RAM
- External Quad SPI flash over FlexSPI
- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors
- 10x LP Flexcomms each supporting SPI, I2C, UART
- 2x FlexCAN with FD, 2x I3Cs, 2x SAI
- 1x Ethernet with QoS
- On-board MCU-Link debugger with CMSIS-DAP
- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS
For more information about the MCX-N947 SoC and FRDM-MCXN947 board, see:
- `MCX-N947 SoC Website`_
- `MCX-N947 Datasheet`_
- `MCX-N947 Reference Manual`_
- `FRDM-MCXN947 Website`_
- `FRDM-MCXN947 User Guide`_
- `FRDM-MCXN947 Board User Manual`_
- `FRDM-MCXN947 Schematics`_
Supported Features
==================
The FRDM-MCXN947 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
| DAC | on-chip | dac |
+-----------+------------+-------------------------------------+
| ENET QOS | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| CTIMER | on-chip | counter |
+-----------+------------+-------------------------------------+
| USDHC | on-chip | sdhc |
+-----------+------------+-------------------------------------+
| VREF | on-chip | regulator |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| USBHS | on-chip | USB device |
+-----------+------------+-------------------------------------+
| LPCMP | on-chip | sensor(comparator) |
+-----------+------------+-------------------------------------+
| FLEXCAN | on-chip | CAN |
+-----------+------------+-------------------------------------+
| LPTMR | on-chip | counter |
+-----------+------------+-------------------------------------+
| FLEXIO | on-chip | flexio |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | flexio; MIPI-DBI. Tested with |
| | | :ref:`lcd_par_s035` |
+-----------+------------+-------------------------------------+
Targets available
==================
The default configuration file
:zephyr_file:`boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig`
only enables the first core.
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The MCX-N947 SoC has 6 gpio controllers and has pinmux registers which
can be used to configure the functionality of a pin.
+------------+-----------------+----------------------------+
| Name | Function | Usage |
+============+=================+============================+
| P0_PIO1_8 | UART | UART RX |
+------------+-----------------+----------------------------+
| P1_PIO1_9 | UART | UART TX |
+------------+-----------------+----------------------------+
System Clock
============
The MCX-N947 SoC is configured to use PLL0 running at 150MHz as a source for
the system clock.
Serial Port
===========
The FRDM-MCXN947 SoC has 10 FLEXCOMM interfaces for serial communication.
Flexcomm 4 is configured as UART for the console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
Using LinkServer
----------------
Linkserver is the default runner for this board, and supports the factory
default MCU-Link firmware. Follow the instructions in
:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
firmware. This only needs to be done if the default onboard debug circuit
firmware was changed. To put the board in ``DFU mode`` to program the firmware,
short jumper J21.
Using J-Link
------------
There are two options. The onboard debug circuit can be updated with Segger
J-Link firmware by following the instructions in
:ref:`mcu-link-jlink-onboard-debug-probe`.
To be able to program the firmware, you need to put the board in ``DFU mode``
by shortening the jumper J21.
The second option is to attach a :ref:`jlink-external-debug-probe` to the
10-pin SWD connector (J23) of the board. Additionally, the jumper J19 must
be shortened.
For both options use the ``-r jlink`` option with west to use the jlink runner.
.. code-block:: console
west flash -r jlink
Configuring a Console
=====================
Connect a USB cable from your PC to J17, and use the serial terminal of your choice
(minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_mcxn947/mcxn947/cpu0
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_mcxn947/mcxn947/cpu0
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
Hello World! frdm_mcxn947/mcxn947/cpu0
.. _MCX-N947 SoC Website:
path_to_url
.. _MCX-N947 Datasheet:
path_to_url
.. _MCX-N947 Reference Manual:
path_to_url
.. _FRDM-MCXN947 Website:
path_to_url
.. _FRDM-MCXN947 User Guide:
path_to_url
.. _FRDM-MCXN947 Board User Manual:
path_to_url
.. _FRDM-MCXN947 Schematics:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_mcxn947/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,050 |
```restructuredtext
.. _frdm_ke15z:
NXP FRDM-KE15Z
##############
Overview
********
The FRDM-KE15Z is a development board for NXP Kinetis KE1xZ 32-bit
MCU-based platforms. The FRDM-KE15Z contains a robust TSI module
with up to 50 channels which makes this board highly flexible
for touch keys. Offers options for serial
communication, flash programming, and run-control debugging.
.. figure:: frdm_ke15z.webp
:align: center
:alt: FRDM-KE15Z
Hardware
********
- MKE15Z256VLL7 MCU (up to 72 MHz, 256 KB flash memory, 32 KB RAM)
- OpenSDA Debug Circuit with a virtual serial port
- Touch electrodes in the self-capacitive mode
- Compatible with FRDM-TOUCH, FRDM-MC-LVBLDC, and Arduino boards
- User Components such as Reset; RGB LED and two user buttons
- 6-axis FXOS8700CQ digital accelerometer and magnetometer
For more information about the KE1xZ SoC and the FRDM-KE15Z board, see
these NXP reference documents:
- `KE1XZ SOC Website`_
- `FRDM-KE15Z Datasheet`_
- `FRDM-KE15Z Reference Manual`_
- `FRDM-KE15Z Website`_
- `FRDM-KE15Z User Guide`_
- `FRDM-KE15Z Schematics`_
Supported Features
==================
The frdm_ke15z board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | uart polling; |
| | | uart interrupt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/frdm_ke15z/frdm_ke15z_defconfig`.
Other hardware features are not currently supported by the port.
System Clock
============
The KE15 SoC is configured to run at 48 MHz using the FIRC.
Serial Port
===========
The KE15 SoC has three UARTs. UART1 is configured for the console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use Linkserver.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
Option 1: Linkserver
-------------------------------------------------------
Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
search path. LinkServer works with the default CMSIS-DAP firmware included in
the on-board debugger.
Linkserver is the default for this board, ``west flash`` and ``west debug`` will
call the linkserver runner.
Option 2: :ref:`opensda-jlink-onboard-debug-probe`
--------------------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `OpenSDA J-Link Firmware for FRDM-KE15Z`_.
Use the ``-r jlink`` option with west to use the jlink runner.
.. code-block:: console
west flash -r jlink
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J5.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_ke15z
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-3478-gb923667860b1 ***
Hello World! frdm_ke15z/mke15z7
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_ke15z
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v3.6.0-xxx-gxxxxxxxxxxxx *****
Hello World! frdm_ke15z
.. _KE1XZ SoC Website:
path_to_url
.. _FRDM-KE15Z Datasheet:
path_to_url
.. _FRDM-KE15Z Reference Manual:
path_to_url
.. _FRDM-KE15Z Website:
path_to_url
.. _FRDM-KE15Z User Guide:
path_to_url
.. _FRDM-KE15Z Schematics:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _OpenSDA J-Link Firmware for FRDM-KE15Z:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_ke15z/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,354 |
```cmake
#
#
#
set(RT1180_BOARD_DIR
"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180")
# Note1: Suggest developers use Secure Provisioning Tool(SPT) to download RT1180 image
# SPT can be downloaded on NXP web: path_to_url
# Details about the usage of SPT on MIMXRT1180-EVK board can be referred on chapter 7 of getting start with Mcuxpresso SDK for MIMXRT1180-EVK doc in SDK package.
if(CONFIG_SOC_MIMXRT1189_CM33)
board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK")
board_runner_args(jlink "--device=MIMXRT1189xxx8_M33" "--reset-after-load" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm33.jlinkscript")
elseif(CONFIG_SOC_MIMXRT1189_CM7)
# Note: Only support run cm7 image when debugging due to default boot core on board is cm33 core
board_runner_args(linkserver "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK")
board_runner_args(linkserver "--core=cm7")
board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir")
endif()
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 387 |
```yaml
#
#
#
identifier: mimxrt1180_evk/mimxrt1189/cm33
name: NXP MIMXRT1180-EVK CM33
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 128
flash: 16384
supported:
- gpio
- uart
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 93 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
CONFIG_NXP_IMXRT_BOOT_HEADER=n
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt118x_cm7.dtsi>
#include "mimxrt1180_evk.dtsi"
/ {
model = "NXP MIMXRT1180-EVK board";
compatible = "nxp,mimxrt1189";
chosen {
zephyr,sram = &dtcm;
zephyr,flash-controller = &w25q128jw;
zephyr,flash = &itcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
};
&systick {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 169 |
```yaml
board:
name: mimxrt1180_evk
vendor: nxp
socs:
- name: mimxrt1189
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/rt/mimxrt1189cvm8b-pinctrl.dtsi>
&pinctrl {
pinmux_lpspi3: pinmux_lpspi3 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_00_lpspi3_pcs0>,
<&iomuxc_gpio_sd_b1_01_lpspi3_sck>,
<&iomuxc_gpio_sd_b1_02_lpspi3_sout>,
<&iomuxc_gpio_sd_b1_03_lpspi3_sin>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_aon_gpio_aon_09_lpuart1_rxd>,
<&iomuxc_aon_gpio_aon_08_lpuart1_txd>;
drive-strength = "high";
slew-rate = "fast";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_aon_gpio_aon_09_gpio1_io09>;
drive-strength = "high";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <&iomuxc_aon_gpio_aon_08_lpuart1_txd>;
drive-strength = "high";
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 362 |
```unknown
/*
*
*/
#include "mimxrt1180_evk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases {
led0 = &green_led;
sw0 = &user_button;
};
leds {
compatible = "gpio-leds";
green_led: led-1 {
gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
label = "User LED D6";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button-1 {
label = "User SW8";
gpios = <&gpio1 4 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
};
&user_button {
status = "okay";
};
&green_led {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio4 {
status = "okay";
};
&flexspi1 {
status = "okay";
ahb-prefetch;
ahb-read-addr-opt;
rx-clock-source = <1>;
w25q128jw: w25q128jw@0 {
compatible = "nxp,imx-flexspi-nor";
size = <134217728>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [ef 80 18];
erase-block-size = <4096>;
write-block-size = <1>;
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 406 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt118x_cm33.dtsi>
#include "mimxrt1180_evk.dtsi"
/ {
model = "NXP MIMXRT1180-EVK board";
compatible = "nxp,mimxrt1189";
chosen {
zephyr,sram = &dtcm;
zephyr,flash-controller = &w25q128jw;
zephyr,flash = &w25q128jw;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
};
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
};
&systick {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 173 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 54 |
```yaml
#
#
#
identifier: mimxrt1180_evk/mimxrt1189/cm7
name: NXP MIMXRT1180-EVK CM7
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 256
supported:
- gpio
- uart
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 92 |
```unknown
# MIMXRT1180-EVK board
if BOARD_MIMXRT1180_EVK
endif # BOARD_MIMXRT1180_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
#
#
#
config BOARD_MIMXRT1180_EVK
select SOC_PART_NUMBER_MIMXRT1189CVM8B
select SOC_MIMXRT1189_CM33 if BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33
select SOC_MIMXRT1189_CM7 if BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/Kconfig.mimxrt1180_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```cmake
#
#
#
board_runner_args(jlink "--device=MCXN236" "--reset-after-load")
board_runner_args(linkserver "--device=MCXN236:FRDM-MCXN236")
board_runner_args(linkserver "--core=cm33_core0")
board_runner_args(linkserver "--override=/device/memory/1/flash-driver=MCXNxxx_S.cfx")
board_runner_args(linkserver "--override=/device/memory/1/location=0x10000000")
# Linkserver v1.4.85 and earlier do not include the secure regions in the
# MCXN236 memory map, so we add them here
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
\"size\":\"0x00040000\",\"type\":\"RAM\"\}")
# Define region for peripherals
board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
\"size\":\"0x00140000\",\"type\":\"RAM\"\}")
# Pyocd support added with the NXP.MCXN236_DFP.17.0.0.pack CMSIS Pack
board_runner_args(pyocd "--target=mcxn236")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 306 |
```unknown
/*
*
*/
#include "frdm_mcxn236-pinctrl.dtsi"
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
aliases{
led0 = &red_led;
led1 = &green_led;
led2 = &blue_led;
sw0 = &user_button_2;
sw1 = &user_button_3;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
label = "Green LED";
};
blue_led: led_2 {
gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
label = "Blue LED";
};
red_led: led_3 {
gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
label = "Red LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpio0 20 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_WAKEUP>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&flexcomm2_lpuart2 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm2_lpuart>;
pinctrl-names = "default";
};
&flexcomm2_lpi2c2 {
pinctrl-0 = <&pinmux_flexcomm2_lpi2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
&flexcomm3_lpspi3 {
pinctrl-0 = <&pinmux_flexcomm3_lpspi>;
pinctrl-names = "default";
};
&flexcomm4_lpuart4 {
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
pinctrl-names = "default";
};
&flexcomm5_lpi2c5 {
pinctrl-0 = <&pinmux_flexcomm5_lpi2c>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_STANDARD>;
};
/*
* MCXN236 board uses OS timer as the kernel timer
* In case we need to switch to SYSTICK timer, then
* replace &os_timer with &systick
*/
&os_timer {
status = "disabled";
};
&systick {
status = "okay";
};
&flash {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
/* Note slot 0 has one additional sector,
* this is intended for use with the swap move algorithm
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 DT_SIZE_K(480)>;
};
slot1_partition: partition@80000 {
label = "image-1";
reg = <0x0088000 DT_SIZE_K(472)>;
};
};
};
&flexpwm1_pwm0 {
pinctrl-0 = <&pinmux_flexpwm1_pwm0>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 832 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```restructuredtext
.. _mimxrt1180_evk:
NXP MIMXRT1180-EVK
##################
Overview
********
The dual core i.MX RT1180 runs on the Cortex-M33 core at 240 MHz and on the
Cortex-M7 at 792 MHz. The i.MX RT1180 MCU offers support over a wide
temperature range and is qualified for consumer, industrial and automotive
markets.
.. image:: mimxrt1180_evk.webp
:align: center
:alt: MIMXRT1180-EVK
Hardware
********
- MIMXRT1189CVM8B MCU
- 240MHz Cortex-M33 & 792Mhz Cortex-M7
- 1.5MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4
- Memory
- 512 Mbit SDRAM
- 128 Mbit QSPI Flash
- 512 Mbit HYPER RAM
- TF socket for SD card
- Ethernet
- 1000 Mbit/s Ethernet PHY
- USB
- 2* USB 2.0 OTG connector
- Audio
- 3.5 mm audio stereo headphone jack
- Board-mounted microphone
- Left and right speaker out connectors
- Power
- 5 V DC jack
- Debug
- JTAG 20-pin connector
- MCU-Link with DAPLink
- Expansion port
- Arduino interface
- CAN bus connector
For more information about the MIMXRT1180 SoC and MIMXRT1180-EVK board, see
these references:
- `i.MX RT1180 Website`_
- `MIMXRT1180-EVK Website`_
External Memory
===============
This platform has the following external memories:
+--------------------+------------+-------------------------------------+
| Device | Controller | Status |
+====================+============+=====================================+
| W9825G6KH | SEMC | Enabled via device configuration |
| | | data block, which sets up SEMC at |
| | | boot time |
+--------------------+------------+-------------------------------------+
| W25Q128JWSIQ | FLEXSPI | Enabled via flash configurationn |
| | | block, which sets up FLEXSPI at |
| | | boot time. |
+--------------------+------------+-------------------------------------+
Supported Features
==================
The mimxrt1180_evk board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1170_evk board may have additional features
already supported, which can also be re-used on this mimxrt1180_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | counter |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_AON_04 | GPIO | SW8 |
+---------------+-----------------+---------------------------+
| GPIO_AD_27 | GPIO | LED |
+---------------+-----------------+---------------------------+
| GPIO_AON_08 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AON_09 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
System Clock
============
The MIMXRT1180 SoC is configured to use SysTick as the system clock source,
running at 240MHz. When targeting the M7 core, SysTick will also be used,
running at 792MHz
Serial Port
===========
The MIMXRT1180 SoC has 12 UARTs. One is configured for the console and the
remaining are not used.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`,
however the :ref:`pyocd-debug-host-tools` do not yet support programming the
external flashes on this board so you must reconfigure the board for one of the
following debug probes instead.
.. _Using J-Link RT1180:
Using J-Link
------------
Please ensure used JLINK above V7.94g and jumper JP5 installed if using
external jlink plus on J37 as debugger.
When debugging cm33 core, need to ensure the SW5 on "0100" mode.
When debugging cm7 core, need to ensure the SW5 on "0001" mode.
(Only support run cm7 image when debugging due to default boot core on board is cm33 core)
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
There are two options: the onboard debug circuit can be updated with Segger
J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the
EVK.
Using Linkserver
----------------
Please ensure used linkserver above V1.5.30 and jumper JP5 uninstalled.
When debugging cm33 core, need to ensure the SW5 on "0100" mode.
When debugging cm7 core, need to ensure the SW5 on "0001" mode.
(Only support run cm7 image when debugging due to default boot core on board is cm33 core)
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the MCU-Link
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers JP5 and JP3 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the MCU-Link microcontroller.
Connect a USB cable from your PC to J53.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application on cm33 core.
Before power on the board, make sure SW5 is set to 0100b
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1180_evk/mimxrt1189/cm33
:goals: flash
Power off the board, then power on the board and
open a serial terminal, reset the board (press the SW3 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
Hello World! mimxrt1180_evk/mimxrt1189/cm33
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1180_evk/mimxrt1189/cm33
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
Hello World! mimxrt1180_evk/mimxrt1189/cm33
.. _MIMXRT1180-EVK Website:
path_to_url
.. _i.MX RT1180 Website:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1180_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,970 |
```unknown
/*
*/
#include <nxp/mcx/MCXN236VDF-pinctrl.h>
&pinctrl {
pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart {
group0 {
pinmux = <FC2_P2_PIO4_2>,
<FC2_P3_PIO4_3>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c {
group0 {
pinmux = <FC2_P0_PIO4_0>,
<FC2_P1_PIO4_1>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};
pinmux_flexcomm3_lpspi: pinmux_flexcomm3_lpspi {
group0 {
pinmux = <FC3_P0_PIO1_0>,
<FC3_P1_PIO1_1>,
<FC3_P2_PIO1_2>,
<FC3_P3_PIO1_3>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
group0 {
pinmux = <FC4_P0_PIO1_8>,
<FC4_P1_PIO1_9>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
};
};
pinmux_flexcomm5_lpi2c: pinmux_flexcomm5_lpi2c {
group0 {
pinmux = <FC5_P0_PIO1_16>,
<FC5_P1_PIO1_17>;
slew-rate = "fast";
drive-strength = "low";
input-enable;
bias-pull-up;
drive-open-drain;
};
};
pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 {
group0 {
pinmux = <PWM1_A0_PIO3_12>,
<PWM1_B0_PIO2_7>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 {
group0 {
pinmux = <PWM1_A1_PIO3_14>,
<PWM1_B1_PIO3_15>;
slew-rate = "fast";
drive-strength = "low";
};
};
pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 {
group0 {
pinmux = <PWM1_A2_PIO3_16>,
<PWM1_B2_PIO3_17>;
slew-rate = "fast";
drive-strength = "low";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/frdm_mcxn236-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 710 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mcxn23x.dtsi>
#include "frdm_mcxn236.dtsi"
/ {
model = "NXP FRDM_N236 board";
compatible = "nxp,mcxn236", "nxp,mcx";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash;
zephyr,flash-controller = &fmu;
zephyr,code-partition = &slot0_partition;
zephyr,console = &flexcomm4_lpuart4;
zephyr,shell-uart = &flexcomm4_lpuart4;
};
aliases{
watchdog0 = &wwdt0;
pwm-0 = &flexpwm1_pwm0;
};
};
&sram0 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(192)>;
};
&gpio4 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio0 {
status = "okay";
};
&green_led {
status = "okay";
};
&red_led {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&edma0 {
status = "okay";
};
&flexcomm2 {
status = "okay";
};
/*
* LPFLEXCOMM supports UART and I2C on the same instance, enable this for
* LFLEXCOMM2
*/
&flexcomm2_lpuart2 {
status = "okay";
};
&flexcomm2_lpi2c2 {
status = "okay";
};
&flexcomm3 {
status = "okay";
};
&flexcomm3_lpspi3 {
status = "okay";
};
&flexcomm4 {
status = "okay";
};
&flexcomm4_lpuart4 {
status = "okay";
};
&flexcomm5 {
status = "okay";
};
&flexcomm5_lpi2c5 {
status = "okay";
};
&wwdt0 {
status = "okay";
};
&flexpwm1_pwm0 {
status = "okay";
};
&ctimer0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/frdm_mcxn236.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 473 |
```unknown
config BOARD_FRDM_MCXN236
select SOC_MCXN236
select SOC_PART_NUMBER_MCXN236VDF
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/Kconfig.frdm_mcxn236 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 29 |
```yaml
board:
name: frdm_mcxn236
vendor: nxp
socs:
- name: mcxn236
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
config BOARD_INIT_PRIORITY
int "Board initialization priority"
default 1
help
Board initialization priority.
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```yaml
#
#
#
identifier: frdm_mcxn236
name: NXP FRDM MCXN236
type: mcu
arch: arm
ram: 256
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- dma
- gpio
- spi
- i2c
- watchdog
- pwm
- counter
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```c
/*
*/
#include <zephyr/init.h>
#include <zephyr/device.h>
#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
#include <fsl_clock.h>
#include <fsl_spc.h>
#include <soc.h>
/* Board xtal frequency in Hz */
#define BOARD_XTAL0_CLK_HZ 24000000U
/* Core clock frequency: 150MHz */
#define CLOCK_INIT_CORE_CLOCK 150000000U
/* System clock frequency. */
extern uint32_t SystemCoreClock;
static void enable_lpcac(void)
{
SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK;
SYSCON->LPCAC_CTRL &= ~(SYSCON_LPCAC_CTRL_CLR_LPCAC_MASK |
SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK);
}
/* Update Active mode voltage for OverDrive mode. */
void power_mode_od(void)
{
/* Set the DCDC VDD regulator to 1.2 V voltage level */
spc_active_mode_dcdc_option_t opt = {
.DCDCVoltage = kSPC_DCDC_OverdriveVoltage,
.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
};
SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
spc_active_mode_core_ldo_option_t ldo_opt = {
.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage,
.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
};
SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
spc_sram_voltage_config_t cfg = {
.operateVoltage = kSPC_sramOperateAt1P2V,
.requestVoltageUpdate = true,
};
SPC_SetSRAMOperateVoltage(SPC0, &cfg);
}
static int frdm_mcxn236_init(void)
{
enable_lpcac();
power_mode_od();
/* Enable SCG clock */
CLOCK_EnableClock(kCLOCK_Scg);
/* FRO OSC setup - begin, enable the FRO for safety switching */
/* Switch to FRO 12M first to ensure we can change the clock setting */
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
/* Enable FRO HF(48MHz) output */
CLOCK_SetupFROHFClocking(48000000U);
/* Set up PLL0 */
const pll_setup_t pll0Setup = {
.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
SCG_APLLCTRL_SELP(13U),
.pllndiv = SCG_APLLNDIV_NDIV(8U),
.pllpdiv = SCG_APLLPDIV_PDIV(1U),
.pllmdiv = SCG_APLLMDIV_MDIV(50U),
.pllRate = 150000000U
};
/* Configure PLL0 to the desired values */
CLOCK_SetPLL0Freq(&pll0Setup);
/* PLL0 Monitor is disabled */
CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
/* Switch MAIN_CLK to PLL0 */
CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
/* Set AHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
CLOCK_SetClkDiv(kCLOCK_DivFlexcom5Clk, 1u);
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer), okay)
CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
CLOCK_EnableClock(kCLOCK_Gpio0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
CLOCK_EnableClock(kCLOCK_Gpio1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
CLOCK_EnableClock(kCLOCK_Gpio2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
CLOCK_EnableClock(kCLOCK_Gpio3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
CLOCK_EnableClock(kCLOCK_Gpio4);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
CLOCK_EnableClock(kCLOCK_Gpio5);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(wwdt0), okay)
CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER0);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER1);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER2);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER3);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U);
CLOCK_AttachClk(kPLL0_to_CTIMER4);
#endif
/* Set SystemCoreClock variable. */
SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
return 0;
}
SYS_INIT(frdm_mcxn236_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,693 |
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