text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```cmake
board_runner_args(jlink "--device=MKE18F512xxx16")
board_runner_args(pyocd "--target=ke18f16")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake)
``` | /content/code_sandbox/boards/nxp/twr_ke18f/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```yaml
identifier: twr_ke18f
name: NXP TWR-KE18F
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
flash: 512
supported:
- adc
- can
- counter
- dac
- dma
- i2c
- pwm
- spi
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/twr_ke18f/twr_ke18f.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_PINCTRL=y
CONFIG_GPIO=y
# Enable MPU
CONFIG_ARM_MPU=y
``` | /content/code_sandbox/boards/nxp/twr_ke18f/twr_ke18f_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MKE18F512VLL16/signal_configuration.xml
*
*/
#include <nxp/kinetis/MKE18F512VLL16-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE0_PTA0>,
<ADC0_SE1_PTA1>,
<ADC0_SE12_PTC14>;
drive-strength = "low";
slew-rate = "slow";
};
};
dac0_default: dac0_default {
group0 {
pinmux = <DAC0_OUT_PTE9>;
drive-strength = "low";
slew-rate = "slow";
};
};
flexcan0_default: flexcan0_default {
group0 {
pinmux = <CAN0_RX_PTE4>,
<CAN0_TX_PTE5>;
drive-strength = "low";
slew-rate = "slow";
};
};
/* Route FLEXIO CLOCKOUT pin */
flexio_clockout: flexio_clockout {
group0 {
pinmux = <CLKOUT_PTE10>;
drive-strength = "low";
slew-rate = "slow";
};
};
ftm0_default: ftm0_default {
group0 {
pinmux = <FTM0_CH0_PTD15>,
<FTM0_CH1_PTD16>,
<FTM0_CH5_PTB5>;
drive-strength = "low";
slew-rate = "slow";
};
};
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH4_PTC10>,
<FTM3_CH5_PTC11>,
<FTM3_CH6_PTC12>,
<FTM3_CH7_PTC13>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpi2c0_default: lpi2c0_default {
group0 {
pinmux = <LPI2C0_SCL_PTA3>,
<LPI2C0_SDA_PTA2>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpi2c1_default: lpi2c1_default {
group0 {
pinmux = <LPI2C1_SCL_PTD9>,
<LPI2C1_SDA_PTD8>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpspi0_default: lpspi0_default {
group0 {
pinmux = <LPSPI0_SCK_PTE0>,
<LPSPI0_SIN_PTE1>,
<LPSPI0_SOUT_PTE2>;
drive-strength = "low";
slew-rate = "slow";
};
};
/* Enable PCS2 for SPI0 */
lpspi0_pcs2: lpspi0_pcs2 {
group0 {
pinmux = <LPSPI0_SCK_PTE0>,
<LPSPI0_SIN_PTE1>,
<LPSPI0_SOUT_PTE2>,
<LPSPI0_PCS2_PTE6>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpspi1_default: lpspi1_default {
group0 {
pinmux = <LPSPI1_SCK_PTD0>,
<LPSPI1_SIN_PTD1>,
<LPSPI1_SOUT_PTD2>;
drive-strength = "low";
slew-rate = "slow";
};
};
/* select PCS0 for lpspi1 */
lpspi1_pcs0: lpspi1_pcs0 {
group0 {
pinmux = <LPSPI1_SCK_PTD0>,
<LPSPI1_SIN_PTD1>,
<LPSPI1_SOUT_PTD2>,
<LPSPI1_PCS0_PTD3>;
drive-strength = "low";
slew-rate = "slow";
};
};
/* select PCS0 and PCS2 for lpspi1 */
lpspi1_pcs0_pcs2: lpspi1_pcs0_pcs2 {
group0 {
pinmux = <LPSPI1_SCK_PTD0>,
<LPSPI1_SIN_PTD1>,
<LPSPI1_SOUT_PTD2>,
<LPSPI1_PCS2_PTA16>,
<LPSPI1_PCS0_PTD3>;
drive-strength = "low";
slew-rate = "slow";
};
};
/* select PCS2 for lpspi1 */
lpspi1_pcs2: lpspi1_pcs2 {
group0 {
pinmux = <LPSPI1_SCK_PTD0>,
<LPSPI1_SIN_PTD1>,
<LPSPI1_SOUT_PTD2>,
<LPSPI1_PCS2_PTA16>;
drive-strength = "low";
slew-rate = "slow";
};
};
lpuart0_default: lpuart0_default {
group0 {
pinmux = <LPUART0_RX_PTB0>,
<LPUART0_TX_PTB1>;
drive-strength = "low";
slew-rate = "slow";
};
};
};
``` | /content/code_sandbox/boards/nxp/twr_ke18f/twr_ke18f-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,259 |
```yaml
board:
name: twr_ke18f
vendor: nxp
socs:
- name: mke18f16
``` | /content/code_sandbox/boards/nxp/twr_ke18f/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _frdm_mcxn236:
NXP FRDM-MCXN236
################
Overview
********
FRDM-MCXN236 are compact and scalable development boards for rapid prototyping of
MCX N23X MCUs. They offer industry standard headers for easy access to the
MCUs I/Os, integrated open-standard serial interfaces, external flash memory and
an on-board MCU-Link debugger. MCX N Series are high-performance, low-power
microcontrollers with intelligent peripherals and accelerators providing multi-tasking
capabilities and performance efficiency.
.. image:: frdm_mcxn236.webp
:align: center
:alt: FRDM-MCXN236
Hardware
********
- MCX-N236 Arm Cortex-M33 microcontroller running at 150 MHz
- 1MB dual-bank on chip Flash
- 352 KB RAM
- USB high-speed (Host/Device) with on-chip HS PHY. HS USB Type-C connectors
- 8x LP Flexcomms each supporting SPI, I2C, UART
- 2x FlexCAN with FD, 2x I3Cs, 2x SAI
- On-board MCU-Link debugger with CMSIS-DAP
- Arduino Header, FlexIO/LCD Header, SmartDMA/Camera Header, mikroBUS
For more information about the MCX-N236 SoC and FRDM-MCXN236 board, see:
- `MCX-N236 SoC Website`_
- `MCX-N236 Datasheet`_
- `MCX-N236 Reference Manual`_
- `FRDM-MCXN236 Website`_
- `FRDM-MCXN236 User Guide`_
- `FRDM-MCXN236 Board User Manual`_
- `FRDM-MCXN236 Schematics`_
Supported Features
==================
The FRDM-MCXN236 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
Targets available
==================
The default configuration file
:zephyr_file:`boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The MCX-N236 SoC has 6 gpio controllers and has pinmux registers which
can be used to configure the functionality of a pin.
+------------+-----------------+----------------------------+
| Name | Function | Usage |
+============+=================+============================+
| P0_PIO1_8 | UART | UART RX |
+------------+-----------------+----------------------------+
| P1_PIO1_9 | UART | UART TX |
+------------+-----------------+----------------------------+
System Clock
============
The MCX-N236 SoC is configured to use PLL0 running at 150MHz as a source for
the system clock.
Serial Port
===========
The FRDM-MCXN236 SoC has 8 FLEXCOMM interfaces for serial communication.
Flexcomm 4 is configured as UART for the console.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
Using LinkServer
----------------
Linkserver is the default runner for this board, and supports the factory
default MCU-Link firmware. Follow the instructions in
:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
firmware. This only needs to be done if the default onboard debug circuit
firmware was changed. To put the board in ``DFU mode`` to program the firmware,
short jumper JP5.
Using J-Link
------------
There are two options. The onboard debug circuit can be updated with Segger
J-Link firmware by following the instructions in
:ref:`mcu-link-jlink-onboard-debug-probe`.
To be able to program the firmware, you need to put the board in ``DFU mode``
by shortening the jumper JP5.
The second option is to attach a :ref:`jlink-external-debug-probe` to the
10-pin SWD connector (J12) of the board. Additionally, the jumper JP7 must
be shortened.
For both options use the ``-r jlink`` option with west to use the jlink runner.
.. code-block:: console
west flash -r jlink
Configuring a Console
=====================
Connect a USB cable from your PC to J10, and use the serial terminal of your choice
(minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_mcxn236
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxn236/mcxn236
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_mcxn236/mcxn236
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
Hello World! frdm_mcxn236/mcxn236
.. _MCX-N236 SoC Website:
path_to_url
.. _MCX-N236 Datasheet:
path_to_url
.. _MCX-N236 Reference Manual:
path_to_url
.. _FRDM-MCXN236 Website:
path_to_url
.. _FRDM-MCXN236 User Guide:
path_to_url
.. _FRDM-MCXN236 Board User Manual:
path_to_url
.. _FRDM-MCXN236 Schematics:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_mcxn236/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,665 |
```c
/*
*
*/
#include <zephyr/init.h>
#include <zephyr/drivers/pinctrl.h>
static int twr_ke18f_pinmux_init(void)
{
int err; /* Used by pinctrl functions */
/* Declare pin configuration state for flexio pin here */
PINCTRL_DT_DEFINE(DT_NODELABEL(flexio));
/* Apply pinctrl state directly, since there is no flexio device driver */
err = pinctrl_apply_state(PINCTRL_DT_DEV_CONFIG_GET(DT_NODELABEL(flexio)),
PINCTRL_STATE_DEFAULT);
if (err) {
return err;
}
return 0;
}
SYS_INIT(twr_ke18f_pinmux_init, PRE_KERNEL_1, 0);
``` | /content/code_sandbox/boards/nxp/twr_ke18f/pinmux.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 154 |
```unknown
config BOARD_TWR_KE18F
select SOC_MKE18F16
select SOC_PART_NUMBER_MKE18F512VLL16
``` | /content/code_sandbox/boards/nxp/twr_ke18f/Kconfig.twr_ke18f | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# TWR-KE18F board
if BOARD_TWR_KE18F
config I2C_MCUX_LPI2C_BUS_RECOVERY
default y
depends on I2C_MCUX_LPI2C && PINCTRL
# The KE1xF has 8 MPU regions, which is not enough for both HW stack protection
# and userspace. Only enable HW stack protection if userspace is not enabled.
config HW_STACK_PROTECTION
default y if !USERSPACE
endif # BOARD_TWR_KE18F
``` | /content/code_sandbox/boards/nxp/twr_ke18f/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 114 |
```unknown
# TWR-KE18F board configuration
if BOARD_TWR_KE18F
config BOARD_TWR_KE18F_FLEXIO_CLKOUT
bool "CLKOUT signal on FlexIO header"
help
Enable the CLKOUT signal on FlexIO header pin 7 (PTE10).
endif # BOARD_TWR_KE18F
``` | /content/code_sandbox/boards/nxp/twr_ke18f/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
/*
*/
#include "../twr_ke18f-pinctrl.dtsi"
&lpspi1 {
pinctrl-0 = <&lpspi1_pcs0_pcs2>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 51 |
```unknown
/*
*/
#include "../twr_ke18f-pinctrl.dtsi"
&lpspi0 {
pinctrl-0 = <&lpspi0_pcs2>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/twr_ke18f/dts/lpspi0_pcs2.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
/*
*/
#include "../twr_ke18f-pinctrl.dtsi"
&lpspi1 {
pinctrl-0 = <&lpspi1_pcs2>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/twr_ke18f/dts/lpspi1_pcs2.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
/*
*/
#include "../twr_ke18f-pinctrl.dtsi"
&lpspi1 {
pinctrl-0 = <&lpspi1_pcs0>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/twr_ke18f/dts/lpspi1_pcs0.overlay | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 48 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ke18f512vlx16.dtsi>
#include <zephyr/dt-bindings/clock/kinetis_scg.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include "twr_ke18f-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP Kinetis KE18 MCU Tower System Module";
compatible = "nxp,mke18f16", "nxp,ke18f", "nxp,ke1xf";
aliases {
led0 = &orange_led;
led1 = &yellow_led;
led2 = &green_led;
led3 = &red_led;
led4 = &tri_red_led;
led5 = &tri_green_led;
led6 = &tri_blue_led;
pwm-led0 = &orange_pwm_led;
pwm-led1 = &yellow_pwm_led;
pwm-led2 = &green_pwm_led;
pwm-led3 = &red_pwm_led;
red-pwm-led = &tri_red_pwm_led;
green-pwm-led = &tri_green_pwm_led;
blue-pwm-led = &tri_blue_pwm_led;
sw0 = &user_button_3;
sw1 = &user_button_2;
magn0 = &fxos8700;
accel0 = &fxos8700;
};
chosen {
/*
* Note: when using DMA, the SRAM region must be set to
* a memory region that is not cached by the chip. If the chosen
* sram region is changed and DMA is in use, you will
* encounter issues!
*/
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,console = &lpuart0;
zephyr,shell-uart = &lpuart0;
zephyr,uart-pipe = &lpuart0;
zephyr,canbus = &flexcan0;
};
leds {
compatible = "gpio-leds";
orange_led: led_0 {
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
label = "User LED D9";
};
yellow_led: led_1 {
gpios = <&gpioc 12 GPIO_ACTIVE_LOW>;
label = "User LED D8";
};
green_led: led_2 {
gpios = <&gpioc 11 GPIO_ACTIVE_LOW>;
label = "User LED D7";
};
red_led: led_3 {
gpios = <&gpioc 10 GPIO_ACTIVE_LOW>;
label = "User LED D6";
};
tri_red_led: led_4 {
gpios = <&gpiod 16 GPIO_ACTIVE_LOW>;
label = "User Tricolor LED D5 (Red)";
};
tri_green_led: led_5 {
gpios = <&gpiod 15 GPIO_ACTIVE_LOW>;
label = "User Tricolor LED D5 (Green)";
};
tri_blue_led: led_6 {
gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
label = "User Tricolor LED D5 (Blue)";
};
};
pwmleds {
compatible = "pwm-leds";
orange_pwm_led: led_pwm_0 {
pwms = <&ftm3 7 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User PWM LED D9";
};
yellow_pwm_led: led_pwm_1 {
pwms = <&ftm3 6 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User PWM LED D8";
};
green_pwm_led: led_pwm_2 {
pwms = <&ftm3 5 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User PWM LED D7";
};
red_pwm_led: led_pwm_3 {
pwms = <&ftm3 4 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User PWM LED D6";
};
tri_red_pwm_led: led_pwm_4 {
pwms = <&ftm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User Tricolor PWM LED D5 (Red)";
};
tri_green_pwm_led: led_pwm_5 {
pwms = <&ftm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User Tricolor PWM LED D5 (Green)";
};
tri_blue_pwm_led: led_pwm_6 {
pwms = <&ftm0 5 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
label = "User Tricolor PWM LED D5 (Blue)";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
};
&cpu0 {
clock-frequency = <120000000>;
};
&idle {
min-residency-us = <1>;
};
&stop {
min-residency-us = <20000>;
exit-latency-us = <13>;
};
&sim {
clkout-source = <1>;
clkout-divider = <0>;
};
&scg {
sosc-mode = <KINETIS_SCG_SOSC_MODE_LOW_POWER>;
sosc_clk {
status = "okay";
clock-frequency = <8000000>;
};
pll {
clock-mult = <30>;
};
core_clk {
clocks = <&spll_clk>;
};
bus_clk {
clock-div = <2>;
};
slow_clk {
clock-div = <5>;
};
clkout_clk {
status = "okay";
};
splldiv1_clk {
clock-div = <1>;
};
splldiv2_clk {
clock-div = <2>;
};
sircdiv1_clk {
clock-div = <1>;
};
sircdiv2_clk {
clock-div = <2>;
};
fircdiv1_clk {
clock-div = <1>;
};
fircdiv2_clk {
clock-div = <1>;
};
soscdiv1_clk {
clock-div = <1>;
};
soscdiv2_clk {
clock-div = <1>;
};
};
&lpuart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
};
&ftm0 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm0_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
&ftm3 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm3_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
&lpi2c0 {
status = "okay";
pinctrl-0 = <&lpi2c0_default>;
pinctrl-names = "default";
scl-gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
fxos8700: fxos8700@1d {
compatible = "nxp,fxos8700";
reg = <0x1d>;
reset-gpios = <&gpioc 15 GPIO_ACTIVE_HIGH>;
};
};
&lpi2c1 {
status = "okay";
pinctrl-0 = <&lpi2c1_default>;
pinctrl-names = "default";
scl-gpios = <&gpiod 9 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
};
&lpspi0 {
dmas = <&edma 0 14>, <&edma 1 15>;
dma-names = "rx", "tx";
status = "okay";
pinctrl-0 = <&lpspi0_default>;
pinctrl-names = "default";
};
&lpspi1 {
status = "okay";
pinctrl-0 = <&lpspi1_default>;
pinctrl-names = "default";
};
&dac0 {
status = "okay";
pinctrl-0 = <&dac0_default>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
sample-time = <12>;
pinctrl-0 = <&adc0_default>;
pinctrl-names = "default";
};
&temp0 {
status = "okay";
};
&flexcan0 {
status = "okay";
pinctrl-0 = <&flexcan0_default>;
pinctrl-names = "default";
can-transceiver {
max-bitrate = <1000000>;
};
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&edma {
status = "okay";
};
&flexio1 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 (DT_SIZE_K(200) + DT_SIZE_K(8))>;
};
slot1_partition: partition@44000 {
label = "image-1";
reg = <0x00044000 DT_SIZE_K(200)>;
};
storage_partition: partition@76000 {
label = "storage";
reg = <0x00076000 DT_SIZE_K(40)>;
};
};
};
``` | /content/code_sandbox/boards/nxp/twr_ke18f/twr_ke18f.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,434 |
```unknown
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y
CONFIG_NXP_IMXRT_BOOT_HEADER=n
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```cmake
#
#
#
board_runner_args(jlink "--device=MIMXRT595S_M33" "--reset-after-load")
board_runner_args(linkserver "--device=MIMXRT595S:EVK-MIMXRT595")
board_runner_args(linkserver "--override=/device/memory/5/flash-driver=MIMXRT500_SFDP_MXIC_OSPI_S.cfx")
board_runner_args(linkserver "--override=/device/memory/5/location=0x18000000")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```restructuredtext
.. _twr_ke18f:
NXP TWR-KE18F
#############
Overview
********
The TWR-KE18F is a development board for NXP Kinetis KE1xF 32-bit
MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter,
running an open source bootloader, offers options for serial
communication, flash programming, and run-control debugging.
.. figure:: TWR-KE18F-DEVICE.jpg
:align: center
:alt: TWR-KE18F
TWR-KE18F (Credit: NXP)
Hardware
********
- MKE18F512VLL16 MCU (up to 168 MHz, 512 KB flash memory, 64 KB RAM,
and 100 Low profile Quad Flat Package (LQFP))
- 3.3 V or 5 V MCU operation
- 6-axis FXOS8700CQ digital accelerometer and magnetometer
- RGB LED
- Four user LEDs
- Two user push-buttons
- Potentiometer
- Thermistor
- Infrared port (IrDA)
- CAN pin header
- Flex I/O pin header
For more information about the KE1xF SoC and the TWR-KE18F board, see
these NXP reference documents:
- `KE1xF Website`_
- `KE1xF Datasheet`_
- `KE1xF Reference Manual`_
- `TWR-KE18F Website`_
- `TWR-KE18F User Guide`_
- `TWR-KE18F Schematics`_
Supported Features
==================
The twr_ke18f board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
| I2C(M) | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | trigger supported with H/W mods |
| | | explained below; |
+-----------+------------+-------------------------------------+
| SPI(M) | on-chip | spi |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| DAC | on-chip | dac |
+-----------+------------+-------------------------------------+
| ACMP | on-chip | analog comparator |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/twr_ke18f/twr_ke18f_defconfig`.
Other hardware features are not currently supported by the port.
System Clock
============
The KE18 SoC is configured to use the 8 MHz external oscillator on the
board with the on-chip PLL to generate a 120 MHz system clock.
Serial Port
===========
The KE18 SoC has three UARTs. UART0 is configured for the console. The
remaining UARTs are not used.
Accelerometer and magnetometer
==============================
The TWR-KE18F board by default only supports polling the FXOS8700
accelerometer and magnetometer for sensor values
(``CONFIG_FXOS8700_TRIGGER_NONE=y``).
In order to support FXOS8700 triggers (interrupts) the 0 ohm resistors
``R47`` and ``R57`` must be mounted on the TWR-KE18F board. The
devicetree must also be modified to describe the FXOS8700 interrupt
GPIOs:
.. code-block:: devicetree
/dts-v1/;
&fxos8700 {
int1-gpios = <&gpioa 14 0>;
int2-gpios = <&gpioc 17 0>;
};
Finally, a trigger option must be enabled in Kconfig (either
``FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or
``FXOS8700_TRIGGER_OWN_THREAD=y``).
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended)
your_sha256_hash--
Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program
the `OpenSDA DAPLink TWR-KE18F Firmware`_.
Option 2: :ref:`opensda-jlink-onboard-debug-probe`
--------------------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `OpenSDA J-Link Firmware for TWR-KE18F`_.
Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and
``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the
default runner from pyOCD to J-Link:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: twr_ke18f
:gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink
:goals: build
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J2.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: twr_ke18f
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx *****
Hello World! twr_ke18f
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: twr_ke18f
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx *****
Hello World! twr_ke18f
.. _TWR-KE18F Website:
path_to_url
.. _TWR-KE18F User Guide:
path_to_url
.. _TWR-KE18F Schematics:
path_to_url
.. _KE1xF Website:
path_to_url
.. _KE1xF Datasheet:
path_to_url
.. _KE1xF Reference Manual:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _OpenSDA DAPLink TWR-KE18F Firmware:
path_to_url#TWR-KE18F
.. _OpenSDA J-Link Firmware for TWR-KE18F:
path_to_url
``` | /content/code_sandbox/boards/nxp/twr_ke18f/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,990 |
```linker script
/*
*
*/
#include <zephyr/linker/linker-tool.h>
GROUP_START(FLEXSPI2)
SECTION_PROLOGUE(.flexspi2_bss,(NOLOAD),SUBALIGN(4))
{
__flexspi2_start = .;
*(.lvgl_buf);
__flexspi2_end = .;
} GROUP_LINK_IN(FLEXSPI2)
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/dc_ram.ld | linker script | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```c
/*
*/
#include <zephyr/init.h>
#include "fsl_power.h"
#include <zephyr/pm/policy.h>
#include "board.h"
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
#include "flash_clock_setup.h"
#endif
/* OTP fuse index. */
#define FRO_192MHZ_SC_TRIM 0x2C
#define FRO_192MHZ_RD_TRIM 0x2B
#define FRO_96MHZ_SC_TRIM 0x2E
#define FRO_96MHZ_RD_TRIM 0x2D
#define OTP_FUSE_READ_API ((void (*)(uint32_t addr, uint32_t *data))0x1300805D)
#define PMIC_MODE_BOOT 0U
#define PMIC_MODE_DEEP_SLEEP 1U
#define PMIC_MODE_FRO192M_900MV 2U
#define PMIC_MODE_FRO96M_800MV 3U
#define PMIC_SETTLING_TIME 2000U /* in micro-seconds */
static uint32_t sc_trim_192, rd_trim_192, sc_trim_96, rd_trim_96;
#if CONFIG_REGULATOR
#include <zephyr/drivers/regulator.h>
#define NODE_PCA9420 DT_NODELABEL(pca9420)
#define NODE_SW1 DT_NODELABEL(pca9420_sw1)
#define NODE_SW2 DT_NODELABEL(pca9420_sw2)
#define NODE_LDO1 DT_NODELABEL(pca9420_ldo1)
#define NODE_LDO2 DT_NODELABEL(pca9420_ldo2)
static const struct device *pca9420 = DEVICE_DT_GET(NODE_PCA9420);
static const struct device *sw1 = DEVICE_DT_GET(NODE_SW1);
static const struct device *sw2 = DEVICE_DT_GET(NODE_SW2);
static const struct device *ldo1 = DEVICE_DT_GET(NODE_LDO1);
static const struct device *ldo2 = DEVICE_DT_GET(NODE_LDO2);
static int current_power_profile;
#define MEGA (1000000U)
/* Core frequency levels number. */
#define POWER_FREQ_LEVELS_NUM (5U)
/* Invalid voltage level. */
#define POWER_INVALID_VOLT_LEVEL (0xFFFFFFFFU)
static const uint32_t power_freq_level[POWER_FREQ_LEVELS_NUM] = {
275U * MEGA,
230U * MEGA,
192U * MEGA,
100U * MEGA,
60U * MEGA
};
/* System clock frequency. */
extern uint32_t SystemCoreClock;
static const int32_t sw1_volt[] = {1100000, 1000000, 900000, 800000, 700000};
static int32_t board_calc_volt_level(void)
{
uint32_t i;
uint32_t volt;
for (i = 0U; i < POWER_FREQ_LEVELS_NUM; i++) {
if (SystemCoreClock > power_freq_level[i]) {
break;
}
}
/* Frequency exceed max supported */
if (i == 0U) {
volt = POWER_INVALID_VOLT_LEVEL;
} else {
volt = sw1_volt[i - 1U];
}
return volt;
}
static int board_config_pmic(void)
{
uint32_t volt;
int ret = 0;
volt = board_calc_volt_level();
ret = regulator_set_voltage(sw1, volt, volt);
if (ret != 0) {
return ret;
}
ret = regulator_set_voltage(sw2, 1800000, 1800000);
if (ret != 0) {
return ret;
}
ret = regulator_set_voltage(ldo1, 1800000, 1800000);
if (ret != 0) {
return ret;
}
ret = regulator_set_voltage(ldo2, 3300000, 3300000);
if (ret != 0) {
return ret;
}
/* We can enter deep low power modes */
pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
return ret;
}
static int board_pmic_change_mode(uint8_t pmic_mode)
{
int ret;
if (pmic_mode >= 4) {
return -ERANGE;
}
ret = regulator_parent_dvs_state_set(pca9420, pmic_mode);
if (ret != -EPERM) {
return ret;
}
POWER_SetPmicMode(pmic_mode, kCfg_Run);
k_busy_wait(PMIC_SETTLING_TIME);
return 0;
}
/* Changes power-related config to preset profiles, like clocks and VDDCORE voltage */
__ramfunc int32_t power_manager_set_profile(uint32_t power_profile)
{
bool voltage_changed = false;
int32_t current_uv, future_uv;
int ret;
if (power_profile == current_power_profile) {
return 0;
}
/* Confirm valid power_profile, and read the new VDDCORE voltage */
switch (power_profile) {
case POWER_PROFILE_AFTER_BOOT:
future_uv = DT_PROP(NODE_SW1, nxp_mode0_microvolt);
break;
case POWER_PROFILE_FRO192M_900MV:
future_uv = DT_PROP(NODE_SW1, nxp_mode2_microvolt);
break;
case POWER_PROFILE_FRO96M_800MV:
future_uv = DT_PROP(NODE_SW1, nxp_mode3_microvolt);
break;
default:
return -EINVAL;
}
if (current_power_profile == POWER_PROFILE_AFTER_BOOT) {
/* One-Time optimization after boot */
POWER_DisableLVD();
CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK);
/* Set SYSCPUAHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U);
/* Other clock optimizations */
#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
flexspi_setup_clock(FLEXSPI0, 0U, 1U); /* main_clk div by 1 */
#endif
/* Disable the PFDs of SYSPLL */
CLKCTL0->SYSPLL0PFD |= CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK |
CLKCTL0_SYSPLL0PFD_PFD1_CLKGATE_MASK |
CLKCTL0_SYSPLL0PFD_PFD2_CLKGATE_MASK;
POWER_EnablePD(kPDRUNCFG_PD_SYSPLL_LDO);
POWER_EnablePD(kPDRUNCFG_PD_SYSPLL_ANA);
POWER_EnablePD(kPDRUNCFG_PD_AUDPLL_LDO);
POWER_EnablePD(kPDRUNCFG_PD_AUDPLL_ANA);
POWER_EnablePD(kPDRUNCFG_PD_SYSXTAL);
/* Configure MCU that PMIC supplies will be powered in all
* PMIC modes
*/
PMC->PMICCFG = 0xFF;
}
/* Get current and future PMIC voltages to determine DVFS sequence */
ret = regulator_get_voltage(sw1, ¤t_uv);
if (ret) {
return ret;
}
if (power_profile == POWER_PROFILE_FRO192M_900MV) {
/* check if voltage or frequency change is first */
if (future_uv > current_uv) {
/* Increase voltage first before frequencies */
ret = board_pmic_change_mode(PMIC_MODE_FRO192M_900MV);
if (ret) {
return ret;
}
voltage_changed = true;
}
/* Trim FRO to 192MHz */
CLKCTL0->FRO_SCTRIM = sc_trim_192;
CLKCTL0->FRO_RDTRIM = rd_trim_192;
/* Reset the EXP_COUNT. */
CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK;
CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK);
/* Set SYSCPUAHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U);
if (voltage_changed == false) {
ret = board_pmic_change_mode(PMIC_MODE_FRO192M_900MV);
if (ret) {
return ret;
}
}
} else if (power_profile == POWER_PROFILE_FRO96M_800MV) {
/* This PMIC mode is the lowest voltage used for DVFS,
* Reduce frequency first, and then reduce voltage
*/
/* Trim the FRO to 96MHz */
CLKCTL0->FRO_SCTRIM = sc_trim_96;
CLKCTL0->FRO_RDTRIM = rd_trim_96;
/* Reset the EXP_COUNT. */
CLKCTL0->FRO_CONTROL &= ~CLKCTL0_FRO_CONTROL_EXP_COUNT_MASK;
CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK);
/* Set SYSCPUAHBCLKDIV divider to value 1 */
CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U);
ret = board_pmic_change_mode(PMIC_MODE_FRO96M_800MV);
if (ret) {
return ret;
}
}
current_power_profile = power_profile;
return 0;
}
#endif /* CONFIG_REGULATOR */
static int mimxrt595_evk_init(void)
{
/* Set the correct voltage range according to the board. */
power_pad_vrange_t vrange = {
.Vdde0Range = kPadVol_171_198,
.Vdde1Range = kPadVol_171_198,
.Vdde2Range = kPadVol_171_198,
.Vdde3Range = kPadVol_300_360,
.Vdde4Range = kPadVol_171_198
};
POWER_SetPadVolRange(&vrange);
/* Do not enter deep low power modes until the PMIC modes have been initialized */
pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
#ifdef CONFIG_I2S
/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm3 */
SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(3) |
SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(3);
#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
/* Select Data in from Transmit I2S - Flexcomm 3 */
SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(3);
/* Enable Transmit I2S - Flexcomm 3 for Shared Data Out */
SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC3DATAOUTEN(1);
#endif
/* Set Receive I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
SYSCTL1_FCCTRLSEL_WSINSEL(1);
/* Set Transmit I2S - Flexcomm 3 SCK, WS from shared signal set 0 */
SYSCTL1->FCCTRLSEL[3] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
SYSCTL1_FCCTRLSEL_WSINSEL(1);
#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
/* Select Receive I2S - Flexcomm 1 Data in from shared signal set 0 */
SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
/* Select Transmit I2S - Flexcomm 3 Data out to shared signal set 0 */
SYSCTL1->FCCTRLSEL[3] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
#endif
#endif
#ifdef CONFIG_REBOOT
/*
* The sys_reboot API calls NVIC_SystemReset. On the RT595, the warm
* reset will not complete correctly unless the ROM toggles the
* flash reset pin. We can control this behavior using the OTP shadow
* register for OPT word BOOT_CFG1
*
* Set FLEXSPI_RESET_PIN_ENABLE=1, FLEXSPI_RESET_PIN= PIO4_5
*/
OCOTP0->OTP_SHADOW[97] = 0x164000;
#endif /* CONFIG_REBOOT */
/* Read 192M FRO clock Trim settings from fuses.
* NOTE: Reading OTP fuses requires a VDDCORE voltage of at least 1.0V
*/
OTP_FUSE_READ_API(FRO_192MHZ_SC_TRIM, &sc_trim_192);
OTP_FUSE_READ_API(FRO_192MHZ_RD_TRIM, &rd_trim_192);
/* Read 96M FRO clock Trim settings from fuses. */
OTP_FUSE_READ_API(FRO_96MHZ_SC_TRIM, &sc_trim_96);
OTP_FUSE_READ_API(FRO_96MHZ_RD_TRIM, &rd_trim_96);
/* Check if the 96MHz fuses have been programmed.
* Production devices have 96M trim values programmed in OTP fuses.
* However, older EVKs may have pre-production silicon.
*/
if ((rd_trim_96 == 0) && (sc_trim_96 == 0)) {
/* If not programmed then use software to calculate the trim values */
CLOCK_FroTuneToFreq(96000000u);
rd_trim_96 = CLKCTL0->FRO_RDTRIM;
sc_trim_96 = sc_trim_192;
}
return 0;
}
#ifdef CONFIG_LV_Z_VBD_CUSTOM_SECTION
extern char __flexspi2_start[];
extern char __flexspi2_end[];
static int init_psram_framebufs(void)
{
/*
* Framebuffers will be stored in PSRAM, within FlexSPI2 linker
* section. Zero out BSS section.
*/
memset(__flexspi2_start, 0, __flexspi2_end - __flexspi2_start);
return 0;
}
#endif /* CONFIG_LV_Z_VBD_CUSTOM_SECTION */
#if CONFIG_REGULATOR
/* PMIC setup is dependent on the regulator API */
SYS_INIT(board_config_pmic, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
#endif
#ifdef CONFIG_LV_Z_VBD_CUSTOM_SECTION
/* Framebuffers should be setup after PSRAM is initialized but before
* Graphics framework init
*/
SYS_INIT(init_psram_framebufs, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
#endif
SYS_INIT(mimxrt595_evk_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,193 |
```yaml
identifier: mimxrt595_evk/mimxrt595s/f1
name: i.MXRT595 Fusion F1 DSP
type: mcu
arch: xtensa
toolchain:
- zephyr
testing:
only_tags:
- kernel
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt5xx.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi"
/ {
model = "NXP MIMXRT595-EVK board";
compatible = "nxp,mimxrt595";
aliases {
sw0 = &user_button_1;
sw1 = &user_button_2;
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
usart-0 = &flexcomm0;
watchdog0 = &wwdt0;
magn0 = &fxos8700;
accel0 = &fxos8700;
sdhc0 = &usdhc0;
pwm-0 = &sc_timer;
dmic-dev = &dmic0;
};
chosen {
zephyr,flash-controller = &mx25um51345g;
zephyr,flash = &mx25um51345g;
zephyr,code-partition = &slot0_partition;
zephyr,sram = &sram0;
zephyr,console = &flexcomm0;
zephyr,shell-uart = &flexcomm0;
zephyr,display = &lcdif;
};
gpio_keys {
compatible = "gpio-keys";
user_button_1: button_0 {
label = "User SW1";
gpios = <&gpio0 25 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_2: button_1 {
label = "User SW2";
gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpio1 0 0>;
label = "User LED_GREEN";
};
blue_led: led_2 {
gpios = <&gpio3 17 0>;
label = "User LED_BLUE";
};
red_led: led_3 {
gpios = <&gpio0 14 0>;
label = "User LED_RED";
};
};
arduino_header: arduino-connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 5 0>, /* A0 */
<1 0 &gpio0 6 0>, /* A1 */
<2 0 &gpio0 19 0>, /* A2 */
<3 0 &gpio0 13 0>, /* A3 */
<4 0 &gpio4 22 0>, /* A4 */
<5 0 &gpio4 21 0>, /* A5 */
<6 0 &gpio4 31 0>, /* D0 */
<7 0 &gpio4 30 0>, /* D1 */
<8 0 &gpio4 20 0>, /* D2 */
<9 0 &gpio4 23 0>, /* D3 */
<10 0 &gpio4 24 0>, /* D4 */
<11 0 &gpio4 25 0>, /* D5 */
<12 0 &gpio4 26 0>, /* D6 */
<13 0 &gpio4 27 0>, /* D7 */
<14 0 &gpio4 28 0>, /* D8 */
<15 0 &gpio4 29 0>, /* D9 */
<16 0 &gpio5 0 0>, /* D10 */
<17 0 &gpio5 1 0>, /* D11 */
<18 0 &gpio5 2 0>, /* D12 */
<19 0 &gpio5 3 0>, /* D13 */
<20 0 &gpio4 22 0>, /* D14 */
<21 0 &gpio4 21 0>; /* D15 */
};
/*
* This node describes the GPIO pins of the MIPI FPC interface,
* J44 on the EVK. This interface is standard to several
* NXP EVKs, and is used with several MIPI displays
* (available as zephyr shields)
*/
nxp_mipi_connector: mipi-connector {
compatible = "gpio-nexus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 12 0>, /* Pin 1, LEDK */
<21 0 &gpio3 21 0>, /* Pin 21, RESET */
<22 0 &gpio3 18 0>, /* Pin 22, LPTE */
<26 0 &gpio0 30 0>, /* Pin 26, CTP_I2C SDA */
<27 0 &gpio0 29 0>, /* Pin 27, CTP_I2C SCL */
<28 0 &gpio4 4 0>, /* Pin 28, CTP_RST */
<29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */
<32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */
<34 0 &gpio0 12 0>; /* Pin 34, BL_PWM */
};
en_mipi_display: enable-mipi-display {
compatible = "regulator-fixed";
regulator-name = "en_mipi_display";
enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
};
/*
* RT595 EVK board uses OS timer as the kernel timer
* In case we need to switch to SYSTICK timer, then
* replace &os_timer with &systick
*/
&os_timer {
status = "okay";
wakeup-source;
};
&rtc {
status = "okay";
};
&flexcomm0 {
compatible = "nxp,lpc-usart";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm0_usart>;
pinctrl-names = "default";
dmas = <&dma0 0>, <&dma0 1>;
dma-names = "rx", "tx";
};
arduino_i2c: &flexcomm4 {
compatible = "nxp,lpc-i2c";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pinmux_flexcomm4_i2c>;
pinctrl-names = "default";
fxos8700: fxos8700@1e {
compatible = "nxp,fxos8700";
reg = <0x1e>;
int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
};
nxp_mipi_i2c: &arduino_i2c {};
zephyr_mipi_dsi: &mipi_dsi {};
zephyr_lcdif: &lcdif {};
hs_spi1: &hs_lspi1 {
compatible = "nxp,lpc-spi";
pinctrl-0 = <&pinmux_flexcomm16_spi>;
pinctrl-names = "default";
dmas = <&dma0 28>, <&dma0 29>;
dma-names = "rx", "tx";
status = "okay";
};
/* I2S RX */
i2s0: &flexcomm1 {
compatible = "nxp,lpc-i2s";
pinctrl-0 = <&pinmux_flexcomm1_i2s>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dma0 2>;
dma-names = "rx";
status = "disabled";
};
/* I2S TX */
i2s1: &flexcomm3 {
compatible = "nxp,lpc-i2s";
pinctrl-0 = <&pinmux_flexcomm3_i2s>;
pinctrl-names = "default";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dma0 7>;
dma-names = "tx";
status = "disabled";
};
arduino_serial: &flexcomm12 {
compatible = "nxp,lpc-usart";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_flexcomm12_usart>;
pinctrl-names = "default";
dmas = <&dma0 34>, <&dma0 35>;
dma-names = "rx", "tx";
};
/* PCA9420 PMIC */
&pmic_i2c {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&pinmux_pmic_i2c>;
pinctrl-names = "default";
pca9420: pca9420@61 {
compatible = "nxp,pca9420";
reg = <0x61>;
nxp,enable-modesel-pins;
pca9420_sw1: BUCK1 {
regulator-boot-on;
nxp,mode0-microvolt = <1100000>;
nxp,mode1-microvolt = <600000>;
nxp,mode2-microvolt = <900000>;
nxp,mode3-microvolt = <800000>;
};
pca9420_sw2: BUCK2 {
regulator-boot-on;
nxp,mode0-microvolt = <1800000>;
nxp,mode1-microvolt = <1800000>;
nxp,mode2-microvolt = <1800000>;
nxp,mode3-microvolt = <1800000>;
};
pca9420_ldo1: LDO1 {
regulator-boot-on;
nxp,mode0-microvolt = <1800000>;
nxp,mode1-microvolt = <1800000>;
nxp,mode2-microvolt = <1800000>;
nxp,mode3-microvolt = <1800000>;
};
pca9420_ldo2: LDO2 {
regulator-boot-on;
nxp,mode0-microvolt = <3300000>;
nxp,mode1-microvolt = <3300000>;
nxp,mode2-microvolt = <3300000>;
nxp,mode3-microvolt = <3300000>;
};
};
};
&lpadc0 {
status = "okay";
pinctrl-0 = <&pinmux_lpadc0>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
/*
* GPIO module interrupts are shared between all GPIO devices on this
* SOC, but Zephyr does not currently support sharing interrupts between
* devices. The user can select GPIO modules to support interrupts by
* setting the appropriate `int-source` and `interrupt` property for
* a given module. On this board, GPIO3 and GPIO4 are configured to support
* interrupts.
*/
&gpio3 {
status = "okay";
int-source = "int-a";
interrupts = <2 0>;
};
&gpio4 {
status = "okay";
int-source = "int-b";
interrupts = <3 0>;
};
&gpio5 {
status = "okay";
};
&gpio6 {
status = "okay";
};
&user_button_1 {
status = "okay";
};
&user_button_2 {
status = "okay";
};
&green_led {
status = "okay";
};
&blue_led {
status = "okay";
};
&red_led {
status = "okay";
};
&dma0 {
status = "okay";
};
zephyr_udc0: &usbhs {
status = "okay";
};
&ctimer0 {
status = "okay";
};
&ctimer1 {
status = "okay";
};
&ctimer2 {
status = "okay";
};
&ctimer3 {
status = "okay";
};
&ctimer4 {
status = "okay";
};
&usdhc0 {
status = "okay";
pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
mmc {
compatible = "zephyr,mmc-disk";
status = "okay";
};
pinctrl-0 = <&pinmux_usdhc>;
pinctrl-names = "default";
mmc-hs200-1_8v;
mmc-hs400-1_8v;
};
&wwdt0 {
status = "okay";
};
&flexspi {
status = "okay";
pinctrl-0 = <&pinmux_flexspi>;
pinctrl-1 = <&pinmux_flexspi_sleep>;
pinctrl-names = "default", "sleep";
mx25um51345g: mx25um51345g@0 {
compatible = "nxp,imx-flexspi-mx25um51345g";
/* MX25UM51245G is 64MB, 512MBit flash part */
size = <DT_SIZE_M(64 * 8)>;
reg = <0>;
spi-max-frequency = <200000000>;
status = "okay";
jedec-id = [c2 81 3a];
erase-block-size = <4096>;
write-block-size = <16>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 98 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(98 * 4))>;
};
slot1_partition: partition@382000 {
label = "image-1";
reg = <0x00382000 DT_SIZE_M(3)>;
};
storage_partition: partition@682000 {
label = "storage";
reg = <0x00682000 (DT_SIZE_M(58) - DT_SIZE_K(520))>;
};
};
};
};
&flexspi2 {
status = "okay";
pinctrl-0 = <&pinmux_flexspi2>;
pinctrl-names = "default";
rx-clock-source = <3>;
ahb-prefetch;
ahb-bufferable;
ahb-cacheable;
ahb-read-addr-opt;
aps6408l: aps6408l@0 {
compatible = "nxp,imx-flexspi-aps6408l";
/* APS6408L is 8MB, 64MBit pSRAM */
size = <DT_SIZE_M(8 * 8)>;
reg = <0>;
spi-max-frequency = <198000000>;
status = "okay";
cs-interval-unit = <1>;
cs-interval = <5>;
cs-hold-time = <3>;
cs-setup-time = <3>;
data-valid-time = <1>;
column-space = <0>;
ahb-write-wait-unit = <2>;
ahb-write-wait-interval = <0>;
};
};
&sc_timer {
pinctrl-0 = <&pinmux_sctimer_default>;
pinctrl-names = "default";
status = "okay";
};
&i3c0 {
pinctrl-0 = <&pinmux_i3c>;
pinctrl-names = "default";
status = "okay";
};
&mbox {
status = "okay";
};
/* Disable this node if not using USB and need another MPU region */
&sram1 {
status = "okay";
};
/* Enable smartDMA controller */
&smartdma {
status = "okay";
};
/* Add smartDMA to mipi DSI */
&mipi_dsi {
dmas = <&smartdma>;
dma-names = "smartdma";
};
&dmic0 {
status = "okay";
pinctrl-0 = <&pinmux_dmic0>;
pinctrl-names = "default";
use2fs;
};
/* Configure pdm channels 0 and 1 with gain, and cutoff settings
* appropriate for the attached MEMS microphones.
*/
&pdmc0 {
status = "okay";
gainshift = <3>;
dc-cutoff = "155hz";
dc-gain = <1>;
};
&pdmc1 {
status = "okay";
gainshift = <3>;
dc-cutoff = "155hz";
dc-gain = <1>;
};
&mrt_channel0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,961 |
```unknown
#
#
#
config BOARD_MIMXRT595_EVK
select SOC_PART_NUMBER_MIMXRT595SFFOC
select SOC_MIMXRT595S_CM33 if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33
select SOC_MIMXRT595S_F1 if BOARD_MIMXRT595_EVK_MIMXRT595S_F1
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```yaml
board:
name: mimxrt595_evk
vendor: nxp
socs:
- name: mimxrt595s
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```objective-c
/*
*/
#define POWER_PROFILE_FRO192M_900MV 0xFF
#define POWER_PROFILE_FRO96M_800MV 0x1
#define POWER_PROFILE_AFTER_BOOT 0x0
__ramfunc int32_t power_manager_set_profile(uint32_t power_profile);
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/board.h | objective-c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 60 |
```yaml
#
#
#
identifier: mimxrt595_evk/mimxrt595s/cm33
name: NXP MIMXRT595-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 4608
flash: 65536
supported:
- arduino_gpio
- arduino_i2c
- arduino_serial
- counter
- dma
- gpio
- i2c
- spi
- usb_device
- watchdog
- sdhc
- pwm
- i2s
- dmic
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 153 |
```unknown
/*
*/
/dts-v1/;
#include <mem.h>
#include <xtensa/xtensa.dtsi>
/ {
model = "nxp_adsp_rt595";
compatible = "nxp";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx6";
reg = <0>;
};
};
sram0: memory@0 {
#address-cells = <1>;
#size-cells = <1>;
device_type = "memory";
compatible = "mmio-sram";
/* Reserve first 512kB of shared memory for ADSP. */
reg = <0x0 DT_SIZE_K(512)>;
/* Reset section must always be at 0 and at least 1kB. */
adsp_reset: memory@0 {
reg = <0x0 DT_SIZE_K(1)>;
};
/* Code and data sections can be moved around and resized if needed. */
adsp_text: memory@400 {
reg = <0x400 DT_SIZE_K(255)>;
};
/* On RT595 ADSP shared RAM is mapped at offset 0 on the code bus and at
* offset 0x800000 on the data bus.
*/
adsp_data: memory@840000 {
reg = <0x840000 DT_SIZE_K(256)>;
};
};
chosen {
zephyr,sram = &adsp_data;
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 359 |
```unknown
# MIMXRT595-EVK board
if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33
config FLASH_MCUX_FLEXSPI_MX25UM51345G
default y if FLASH
choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
endchoice
config FXOS8700_DRDY_INT1
default y
depends on FXOS8700_TRIGGER
if DMA_MCUX_LPC
# Memory from the heap pool is used to allocate DMA descriptors for
# channels that use multiple blocks for a DMA transfer.
# Adjust HEAP_MEM_POOL_MIN_SIZE in case you need more memory.
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 4096
endif # DMA_MCUX_LPC
# Turn on Device Level Power Management as we wish
# to reconfigure the FlexSPI pins for power savings
# when transitioning the SoC to Deep Low Power modes.
config PM_DEVICE
default y if PM
config REGULATOR
default y if PM || POWEROFF
endif # BOARD_MIMXRT595_EVK_MIMXRT595S_CM33
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```unknown
/*
* NOTE: File generated by gen_board_pinctrl.py
* from MIMXRT595-EVK.mex
*
*/
#include <nxp/nxp_imx/rt/MIMXRT595SFFOC-pinctrl.h>
&pinctrl {
pinmux_flexcomm0_usart: pinmux_flexcomm0_usart {
group0 {
pinmux = <FC0_RXD_SDA_MOSI_DATA_PIO0_2>;
input-enable;
slew-rate = "normal";
drive-strength = "normal";
};
group1 {
pinmux = <FC0_TXD_SCL_MISO_WS_PIO0_1>;
slew-rate = "normal";
drive-strength = "normal";
};
};
/* RX */
pinmux_flexcomm1_i2s: pinmux_flexcomm1_i2s {
group0 {
pinmux = <FC1_RXD_SDA_MOSI_DATA_PIO0_9>,
<FC1_TXD_SCL_MISO_WS_PIO0_8>,
<FC1_SCK_PIO0_7>;
slew-rate = "normal";
input-enable;
drive-strength = "high";
};
};
/* TX */
pinmux_flexcomm3_i2s: pinmux_flexcomm3_i2s {
group0 {
pinmux = <FC3_RXD_SDA_MOSI_DATA_PIO0_23>;
input-enable;
slew-rate = "normal";
drive-strength = "high";
};
};
pinmux_dmic0: pinmux_dmic0 {
group0 {
pinmux = <DMIC0_DATA23_PIO3_1>, <DMIC0_DATA01_PIO5_8>,
<DMIC0_CLK01_PIO5_4>;
slew-rate = "normal";
drive-strength = "normal";
input-enable;
};
};
pinmux_flexcomm4_i2c: pinmux_flexcomm4_i2c {
group0 {
pinmux = <FC4_TXD_SCL_MISO_WS_PIO0_29>,
<FC4_RXD_SDA_MOSI_DATA_PIO0_30>;
input-enable;
slew-rate = "normal";
drive-strength = "high";
drive-open-drain;
};
};
pinmux_flexcomm12_usart: pinmux_flexcomm12_usart {
group0 {
pinmux = <FC12_RXD_SDA_MOSI_PIO4_31>;
input-enable;
slew-rate = "normal";
drive-strength = "normal";
};
group1 {
pinmux = <FC12_TXD_SCL_MISO_PIO4_30>;
slew-rate = "normal";
drive-strength = "normal";
};
};
pinmux_flexcomm16_spi: pinmux_flexcomm16_spi {
group0 {
pinmux = <HS_SPI1_SCK_PIO1_3>,
<HS_SPI1_MISO_PIO1_4>,
<HS_SPI1_MOSI_PIO1_5>,
<HS_SPI1_SSELN0_PIO1_6>;
input-enable;
slew-rate = "normal";
drive-strength = "normal";
};
};
pinmux_pmic_i2c: pinmux_pmic_i2c {
group0 {
pinmux = <PMIC_I2C_SCL>,
<PMIC_I2C_SDA>;
bias-pull-up;
input-enable;
slew-rate = "normal";
drive-strength = "normal";
drive-open-drain;
};
};
pinmux_flexspi2: pinmux_flexspi2 {
group0 {
pinmux =
<FLEXSPI1_SCLK_PIO4_11>,
<FLEXSPI1_DATA0_PIO4_12>,
<FLEXSPI1_DATA1_PIO4_13>,
<FLEXSPI1_DATA2_PIO4_14>,
<FLEXSPI1_DATA3_PIO4_15>,
<FLEXSPI1_DATA4_PIO5_15>,
<FLEXSPI1_DATA5_PIO5_16>,
<FLEXSPI1_DATA6_PIO5_17>,
<FLEXSPI1_DATA7_PIO5_18>,
<FLEXSPI1_SS0_N_PIO4_18>;
slew-rate = "normal";
input-enable;
drive-strength = "high";
};
group1 {
pinmux = <FLEXSPI1_DQS_PIO4_16>;
slew-rate = "normal";
input-enable;
drive-strength = "high";
bias-pull-down;
};
};
pinmux_flexspi: pinmux_flexspi {
group0 {
pinmux = <FLEXSPI0_SCLK_PIO1_18>,
<FLEXSPI0_SS0_N_PIO1_19>,
<FLEXSPI0_DATA0_PIO1_20>,
<FLEXSPI0_DATA1_PIO1_21>,
<FLEXSPI0_DATA2_PIO1_22>,
<FLEXSPI0_DATA3_PIO1_23>,
<FLEXSPI0_DATA4_PIO1_24>,
<FLEXSPI0_DATA5_PIO1_25>,
<FLEXSPI0_DATA6_PIO1_26>,
<FLEXSPI0_DATA7_PIO1_27>;
input-enable;
slew-rate = "normal";
drive-strength = "high";
};
};
pinmux_flexspi_sleep: pinmux_flexspi_sleep {
group0 {
pinmux = <FLEXSPI0_SCLK_PIO1_18>,
<FLEXSPI0_SS0_N_PIO1_19>;
slew-rate = "normal";
drive-strength = "high";
};
group1 {
pinmux = <FLEXSPI0_DATA0_PIO1_20>,
<FLEXSPI0_DATA1_PIO1_21>,
<FLEXSPI0_DATA2_PIO1_22>,
<FLEXSPI0_DATA3_PIO1_23>,
<FLEXSPI0_DATA4_PIO1_24>,
<FLEXSPI0_DATA5_PIO1_25>,
<FLEXSPI0_DATA6_PIO1_26>,
<FLEXSPI0_DATA7_PIO1_27>;
input-enable;
slew-rate = "normal";
drive-strength = "high";
bias-pull-up;
};
};
pinmux_lpadc0: pinmux_lpadc0 {
group0 {
pinmux = <ADC0_CH0_PIO0_5>,
<ADC0_CH8_PIO0_6>,
<ADC0_CH2_PIO0_19>;
slew-rate = "normal";
drive-strength = "normal";
nxp,analog-mode;
};
};
pinmux_usdhc: pinmux_usdhc {
group0 {
pinmux = <SD0_CMD_PIO1_31>,
<USDHC0_USDHC_DATA0_PIO2_0>,
<USDHC0_USDHC_DATA1_PIO2_1>,
<USDHC0_USDHC_DATA2_PIO2_2>,
<USDHC0_USDHC_DATA3_PIO2_3>,
<USDHC0_USDHC_DATA4_PIO2_5>,
<USDHC0_USDHC_DATA5_PIO2_6>,
<USDHC0_USDHC_DATA6_PIO2_7>,
<USDHC0_USDHC_DATA7_PIO2_8>,
<SD0_CARD_DET_N_PIO2_9>;
bias-pull-up;
input-enable;
slew-rate = "normal";
drive-strength = "normal";
};
group1 {
pinmux = <SD0_CLK_PIO1_30>;
bias-pull-down;
input-enable;
slew-rate = "normal";
drive-strength = "normal";
};
group2 {
pinmux = <GPIO_PIO210_PIO2_10>;
bias-pull-down;
slew-rate = "normal";
drive-strength = "normal";
};
group3 {
pinmux = <SD0_DS_PIO2_4>;
bias-pull-down;
input-enable;
slew-rate = "slow";
drive-strength = "normal";
};
};
pinmux_sctimer_default: pinmux_sctimer_default {
group0 {
pinmux = <SCT0_OUT0_PIO0_5>,
<SCT0_OUT1_PIO0_6>;
slew-rate = "normal";
drive-strength = "normal";
};
};
pinmux_i3c: pinmux_i3c {
group0 {
pinmux = <I3C0_SCL_PIO2_29>,
<I3C0_SDA_PIO2_30>;
input-enable;
slew-rate = "slow";
drive-strength = "high";
};
group1 {
pinmux = <I3C0_PUR_PIO2_31>;
slew-rate = "normal";
drive-strength = "normal";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,131 |
```unknown
config BOARD_INIT_PRIORITY
int "Board initialization priority"
default 45
help
Board initialization priority.
DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset)
DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data)
DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text)
if BOARD_MIMXRT595_EVK_MIMXRT595S_F1
config RT595_ADSP_STACK_SIZE
hex "Boot time stack size"
default 0x1000
help
Stack space is reserved at the end of the RT595_ADSP_DATA_MEM
region, starting at RT595_ADSP_DATA_MEM_ADDR - RT595_ADSP_STACK_SIZE
config RT595_ADSP_RESET_MEM_ADDR
hex
default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM))
config RT595_ADSP_RESET_MEM_SIZE
hex
default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM))
config RT595_ADSP_DATA_MEM_ADDR
hex
default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM))
config RT595_ADSP_DATA_MEM_SIZE
hex
default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM))
config RT595_ADSP_TEXT_MEM_ADDR
hex
default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM))
config RT595_ADSP_TEXT_MEM_SIZE
hex
default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM))
endif # BOARD_MIMXRT595_EVK_RT595_F1
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 332 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_PINCTRL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_GPIO=y
# Enable TrustZone-M
CONFIG_TRUSTED_EXECUTION_SECURE=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```cmake
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/mimx8mn6dvtjz-pinctrl.dtsi>
&pinctrl {
uart2_default: uart2_default {
group0 {
pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>,
<&iomuxc_uart2_txd_uart_tx_uart2_tx>;
slew-rate = "fast";
drive-strength = "x6";
};
};
uart4_default: uart4_default {
group0 {
pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
slew-rate = "fast";
drive-strength = "x6";
};
};
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_enet_td0_enet_rgmii_td_enet1_rgmii_td0>,
<&iomuxc_enet_td1_enet_rgmii_td_enet1_rgmii_td1>,
<&iomuxc_enet_td2_enet_rgmii_td_enet1_rgmii_td2>,
<&iomuxc_enet_td3_enet_rgmii_td_enet1_rgmii_td3>,
<&iomuxc_enet_txc_enet_rgmii_txc_enet1_rgmii_txc>,
<&iomuxc_enet_tx_ctl_enet_rgmii_tx_ctl_enet1_rgmii_tx_ctl>;
slew-rate = "fast";
drive-strength = "x6";
};
group1 {
pinmux = <&iomuxc_enet_rd0_enet_rgmii_rd_enet1_rgmii_rd0>,
<&iomuxc_enet_rd1_enet_rgmii_rd_enet1_rgmii_rd1>,
<&iomuxc_enet_rd2_enet_rgmii_rd_enet1_rgmii_rd2>,
<&iomuxc_enet_rd3_enet_rgmii_rd_enet1_rgmii_rd3>,
<&iomuxc_enet_rxc_enet_rgmii_rxc_enet1_rgmii_rxc>,
<&iomuxc_enet_rx_ctl_enet_rgmii_rx_ctl_enet1_rgmii_rx_ctl>;
slew-rate = "fast";
drive-strength = "x1";
};
group2 {
pinmux = <&iomuxc_sai2_rxc_gpio_io_gpio4_io22>;
slew-rate = "fast";
drive-strength = "x1";
};
};
pinmux_mdio: pinmux_mdio {
group0 {
pinmux = <&iomuxc_enet_mdc_enet_mdc_enet1_mdc>,
<&iomuxc_enet_mdio_enet_mdio_enet1_mdio>;
slew-rate = "slow";
drive-strength = "x6";
};
};
};
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 682 |
```unknown
config BOARD_IMX8MN_EVK
select SOC_MIMX8MN6_A53 if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP
select SOC_PART_NUMBER_MIMX8MN6DVTJZ if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mimx8mn_a53.dtsi>
#include "imx8mn_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX8MN A53";
compatible = "fsl,mimx8mn";
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
zephyr,sram = &sram0;
};
cpus {
cpu@0 {
status = "disabled";
};
cpu@1 {
status = "disabled";
};
cpu@2 {
status = "disabled";
};
};
sram0: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>;
};
};
&enet {
status = "okay";
};
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rgmii";
status = "okay";
};
&enet_mdio {
pinctrl-0 = <&pinmux_mdio>;
pinctrl-names = "default";
status = "okay";
phy: phy@0 {
compatible = "qca,ar8031";
reg = <0>;
status = "okay";
};
};
&uart4 {
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 358 |
```unknown
# ARM Options
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_ARMV8_A_NS=y
CONFIG_ARM64_VA_BITS_36=y
CONFIG_ARM64_PA_BITS_36=y
# Cache Options
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE_LINE_SIZE_DETECT=y
CONFIG_ICACHE_LINE_SIZE_DETECT=y
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_KERNEL_DIRECT_MAP=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 123 |
```yaml
#
#
#
identifier: imx8mn_evk/mimx8mn6/a53
name: NXP i.MX8M Nano EVK A53
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```yaml
#
#
#
identifier: imx8mn_evk/mimx8mn6/a53/smp
name: NXP i.MX8M Nano EVK A53 with SMP kernel
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
supported:
- smp
testing:
ignore_tags:
- net
- bluetooth
vendor: nxp
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```yaml
board:
name: imx8mn_evk
vendor: nxp
socs:
- name: mimx8mn6
variants:
- name: smp
cpucluster: a53
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```unknown
if BOARD_IMX8MN_EVK
if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP
if NETWORKING
config NET_L2_ETHERNET
default y
config NET_TX_STACK_SIZE
default 8192
config NET_RX_STACK_SIZE
default 8192
if NET_TCP
config NET_TCP_WORKQ_STACK_SIZE
default 8192
endif # NET_TCP
if NET_MGMT_EVENT
config NET_MGMT_EVENT_STACK_SIZE
default 8192
endif # NET_MGMT_EVENT
if NET_SOCKETS_SERVICE
config NET_SOCKETS_SERVICE_STACK_SIZE
default 8192
endif # NET_SOCKETS_SERVICE
endif # NETWORKING
endif # BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP
endif # BOARD_IMX8MN_EVK
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 208 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_mimx8mn_a53.dtsi>
#include "imx8mn_evk-pinctrl.dtsi"
/ {
model = "NXP i.MX8MN A53";
compatible = "fsl,mimx8mn";
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
zephyr,sram = &sram0;
};
cpus {
cpu@0 {
status = "disabled";
};
cpu@1 {
status = "disabled";
};
};
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
sram0: memory@93c00000 {
reg = <0x93c00000 DT_SIZE_M(1)>;
};
};
&enet {
status = "okay";
};
&enet_mac {
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rgmii";
status = "okay";
};
&enet_mdio {
pinctrl-0 = <&pinmux_mdio>;
pinctrl-names = "default";
status = "okay";
phy: phy@0 {
compatible = "qca,ar8031";
reg = <0>;
status = "okay";
};
};
&uart4 {
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 370 |
```restructuredtext
.. _mimxrt595_evk:
NXP MIMXRT595-EVK
##################
Overview
********
i.MX RT500 crossover MCUs are part of the edge computing family and are optimized
for low-power HMI applications by combining a graphics engine and a streamlined
Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33
core. These devices are designed to unlock the potential of display-based applications
with a secure, power-optimized embedded processor.
i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces
to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly
decryption engine.
.. image:: mimxrt595_evk.jpg
:align: center
:alt: MIMXRT595-EVK
Hardware
********
- MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP
- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only)
- USB2.0 high-speed host and device with micro USB connector and external crystal
- Octal/Quad/pSRAM external memories via FlexSPI
- 5 MB system SRAM
- Full size SD card slot (SDIO)
- On-board eMMC chip
- On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V
- User LEDs
- Reset and User buttons
- MIPI-DSI connector
- Single row headers for ARDUINO signals and MikroBus connector
- FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display
- One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ
- Stereo audio codec with line-In/ line-Out/ and Microphone
- Pmod/host expansion connector
- NXP TFA9896 audio digital amplifier
- Support for up to eight off-board digital microphones via 12-pin header
- Two on-board digital microphones
For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see
these references:
- `i.MX RT595 Website`_
- `i.MX RT595 Datasheet`_
- `i.MX RT595 Reference Manual`_
- `MIMXRT595-EVK Website`_
- `MIMXRT595-EVK User Guide`_
- `MIMXRT595-EVK Schematics`_
- `MIMXRT595-EVK Debug Firmware`_
Supported Features
==================
NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx
family of MCUs. This board is a focus for NXP's Full Platform Support for
Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling
this board with new support for Zephyr features. The mimxrt595_evk board
configuration supports the hardware features below. Another very similar
board is the :ref:`mimxrt685_evk`, and that board may have additional features
already supported, which can also be re-used on this mimxrt595_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| OS_TIMER | on-chip | os timer |
+-----------+------------+-------------------------------------+
| IOCON | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| USART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| CTIMER | on-chip | counter |
+-----------+------------+-------------------------------------+
| WDT | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | OctalSPI Flash |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
| RTC | on-chip | counter |
+-----------+------------+-------------------------------------+
| PM | on-chip | power management; uses SoC sleep, |
| | | deep sleep and deep-powerdown modes |
+-----------+------------+-------------------------------------+
| SDHC | on-chip | disk access (works with eMMC & SD) |
+-----------+------------+-------------------------------------+
| I2S | on-chip | i2s |
+-----------+------------+-------------------------------------+
| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with |
| | | :ref:`rk055hdmipi4m`, |
| | | :ref:`rk055hdmipi4ma0`, and |
| | | :ref:`g1120b0mipi` display shields |
+-----------+------------+-------------------------------------+
| DMIC | on-chip | dmic |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The MIMXRT595 SoC has IOCON registers, which can be used to configure the
functionality of a pin.
+---------+-----------------+----------------------------+
| Name | Function | Usage |
+=========+=================+============================+
| PIO0_2 | USART0 | USART RX |
+---------+-----------------+----------------------------+
| PIO0_1 | USART0 | USART TX |
+---------+-----------------+----------------------------+
| PIO0_14 | GPIO | GREEN LED |
+---------+-----------------+----------------------------+
| PIO0_25 | GPIO | SW0 |
+---------+-----------------+----------------------------+
| PIO0_10 | GPIO | SW1 |
+---------+-----------------+----------------------------+
| PIO4_30 | USART12 | USART TX |
+---------+-----------------+----------------------------+
| PIO4_31 | USART12 | USART RX |
+---------+-----------------+----------------------------+
| PIO0_29 | I2C | I2C SCL |
+---------+-----------------+----------------------------+
| PIO0_30 | I2C | I2C SDA |
+---------+-----------------+----------------------------+
| PIO0_22 | GPIO | FXOS8700 TRIGGER |
+---------+-----------------+----------------------------+
| PIO1_5 | SPI | SPI MOSI |
+---------+-----------------+----------------------------+
| PIO1_4 | SPI | SPI MISO |
+---------+-----------------+----------------------------+
| PIO1_3 | SPI | SPI SCK |
+---------+-----------------+----------------------------+
| PIO1_6 | SPI | SPI SSEL |
+---------+-----------------+----------------------------+
| PIO0_5 | SCT0 | SCT0 GPI0 |
+---------+-----------------+----------------------------+
| PIO0_6 | SCT0 | SCT0 GPI1 |
+---------+-----------------+----------------------------+
System Clock
============
The MIMXRT595 EVK is configured to use the OS Event timer
as a source for the system clock.
Serial Port
===========
The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is
configured as USART for the console and the remaining are not used.
Fusion F1 DSP Core
==================
You can build a Zephyr application for the RT500 DSP core by targeting the F1
SOC. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK.
To build the hello_world sample for the RT500 DSP core:
.. code-block:: shell
$ west build -b mimxrt595_evk/mimxrt595s/f1 samples/hello_world
For detailed instructions on how to debug DSP firmware, please refer to
this document: `Getting Started with Xplorer for EVK-MIMXRT595`_
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the LPC-Link2.
.. tabs::
.. group-tab:: LPCLink2 JLink Onboard
1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19,
if not already done (these jumpers are installed by default).
3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the
J-Link firmware. Please make sure you have the latest firmware for this board.
.. group-tab:: JLink External
1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18,
and J19 (these are installed by default).
3. Connect the J-Link probe to J2 10-pin header.
See :ref:`jlink-external-debug-probe` for more information.
.. group-tab:: Linkserver
1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path.
2. To update the debug firmware, please follow the instructions on `MIMXRT595-EVK Debug Firmware`
Configuring a Console
=====================
Connect a USB cable from your PC to J40, and use the serial terminal of your choice
(minicom, putty, etc.) with the following settings:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application. This example uses the
:ref:`jlink-debug-host-tools` as default.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt595_evk/mimxrt595s/cm33
:goals: flash
Open a serial terminal, reset the board (press the RESET button), and you should
see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS v2.7 ***
Hello World! mimxrt595_evk
Debugging
=========
Here is an example for the :ref:`hello_world` application. This example uses the
:ref:`jlink-debug-host-tools` as default.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt595_evk/mimxrt595s/cm33
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
*** Booting Zephyr OS v2.7 ***
Hello World! mimxrt595_evk
Troubleshooting
===============
If the debug probe fails to connect with the following error, it's possible
that the image in flash is interfering and causing this issue.
.. code-block:: console
Remote debugging using :2331
Remote communication error. Target disconnected.: Connection reset by peer.
"monitor" command not supported by this target.
"monitor" command not supported by this target.
You can't do that when your target is `exec'
(gdb) Could not connect to target.
Please check power, connection and settings.
You can fix it by erasing and reprogramming the flash with the following
steps:
#. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash.
#. Reset by pressing SW3
#. Run ``west debug`` or ``west flash`` again with a known working Zephyr
application (example "Hello World").
#. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash.
#. Reset by pressing SW3
.. _MIMXRT595-EVK Website:
path_to_url
.. _MIMXRT595-EVK User Guide:
path_to_url
.. _MIMXRT595-EVK Debug Firmware:
path_to_url
.. _MIMXRT595-EVK Schematics:
path_to_url
.. _i.MX RT595 Website:
path_to_url
.. _i.MX RT595 Datasheet:
path_to_url
.. _i.MX RT595 Reference Manual:
path_to_url
.. _Getting Started with Xplorer for EVK-MIMXRT595:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt595_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,064 |
```unknown
# ARM Options
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_ARMV8_A_NS=y
CONFIG_ARM64_VA_BITS_36=y
CONFIG_ARM64_PA_BITS_36=y
# Cache Options
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE_LINE_SIZE_DETECT=y
CONFIG_ICACHE_LINE_SIZE_DETECT=y
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_KERNEL_DIRECT_MAP=y
# SMP
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=2
CONFIG_PM_CPU_OPS=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 147 |
```cmake
#
#
#
if(CONFIG_SOC_MIMX8UD7_ADSP)
board_set_flasher_ifnset(misc-flasher)
board_finalize_runner_args(misc-flasher)
board_set_rimage_target(imx8ulp)
endif()
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```yaml
identifier: imx8ulp_evk/mimx8ud7/adsp
name: NXP i.MX 8ULP Audio DSP
type: mcu
arch: xtensa
toolchain:
- zephyr
testing:
only_tags:
- kernel
- sof
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
#
#
config BOARD_IMX8ULP_EVK
select SOC_MIMX8UD7_ADSP if BOARD_IMX8ULP_EVK_MIMX8UD7_ADSP
select SOC_PART_NUMBER_MIMX8UD7DVK08
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx8ulp.dtsi>
#include "imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi"
/ {
model = "NXP i.MX 8ULP Audio DSP";
compatible = "nxp";
chosen {
zephyr,sram = &sram0;
zephyr,console = &lpuart7;
zephyr,shell-uart = &lpuart7;
};
};
&lpuart7 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&lpuart7_default>;
pinctrl-names = "default";
};
&sai5 {
rx-dataline = <3>;
};
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 172 |
```yaml
board:
name: imx8ulp_evk
vendor: nxp
socs:
- name: mimx8ud7
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_DYNAMIC_INTERRUPTS=y
CONFIG_LOG=y
CONFIG_CLOCK_CONTROL=y
# serial-related configurations
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```unknown
/*
*
*/
&iomuxc1 {
iomuxc1_ptf22_lpuart7_tx: IOMUXC_PTF22_LPUART7_TX {
pinmux = <0x298c0158 0x4 0x298c09e0 0x3 0x298c0158>;
};
iomuxc1_ptf23_lpuart7_rx: IOMUXC_PTF23_LPUART7_RX {
pinmux = <0x298c015c 0x4 0x298c09dc 0x3 0x298c015c>;
};
};
&pinctrl {
lpuart7_default: lpuart7_default {
group0 {
pinmux = <&iomuxc1_ptf22_lpuart7_tx>, <&iomuxc1_ptf23_lpuart7_rx>;
};
};
};
``` | /content/code_sandbox/boards/nxp/imx8ulp_evk/imx8ulp_evk_mimx8ud7_adsp-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```restructuredtext
.. _imx8mn_evk:
NXP i.MX8MN EVK (Cortex-A53)
############################
Overview
********
i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications
processor, composed of a quad Cortex-A53 cluster and a single Cortex-M7 core.
Zephyr OS is ported to run on the Cortex-A53 core.
- Board features:
- RAM: 2GB LPDDR4
- Storage:
- SanDisk 16GB eMMC5.1
- Micron 32MB QSPI NOR
- microSD Socket
- Wireless:
- WiFi: 2.4/5GHz IEEE 802.11b/g/n
- Bluetooth: v4.1
- USB:
- OTG - 2x type C
- Ethernet
- PCI-E M.2
- Connectors:
- 40-Pin Dual Row Header
- LEDs:
- 1x Power status LED
- 1x UART LED
- Debug
- JTAG 20-pin connector
- MicroUSB for UART debug, two COM ports for A53 and M7
More information about the board can be found at the
`NXP website`_.
Supported Features
==================
The Zephyr mimx8mn_evk board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| GIC-v3 | on-chip | interrupt controller |
+-----------+------------+-------------------------------------+
| ARM TIMER | on-chip | system clock |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | clock_control |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RDC | on-chip | Resource Domain Controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPT | on-chip | timer |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet port |
+-----------+------------+-------------------------------------+
Devices
========
System Clock
------------
This board configuration uses a system clock frequency of 8 MHz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
CPU's UART4.
Programming and Debugging
*************************
Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
plug the SD card into the board. Power it up and stop the u-boot execution at
prompt.
Use U-Boot to load and kick zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000
Or kick SMP zephyr.bin:
.. code-block:: console
fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000
Use this configuration to run basic Zephyr applications and kernel tests,
for example, with the :zephyr:code-sample:`synchronization` sample:
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: imx8mn_evk/mimx8mn6/a53
:goals: run
This will build an image with the synchronization sample app, boot it and
display the following ram console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 ***
thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_b: Hello World from cpu 0 on mimx8mn_evk_a53!
thread_a: Hello World from cpu 0 on mimx8mn_evk_a53!
Use Jailhouse hypervisor, after root cell linux is up:
.. code-block:: console
#jailhouse enable imx8mn.cell
#jailhouse cell create imx8mn-zephyr.cell
#jailhouse cell load 1 zephyr.bin -a 0x93c00000
#jailhouse cell start 1
References
==========
.. _NXP website:
path_to_url
.. _i.MX 8M Applications Processor Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/imx8mn_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,079 |
```cmake
board_runner_args(jlink "--device=MK22FN512xxx12")
board_runner_args(pyocd "--target=k22f")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/frdm_k22f/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MK22FN512VLH12/signal_configuration.xml
*
*/
#include <nxp/kinetis/MK22FN512VLH12-pinctrl.h>
&pinctrl {
ftm0_default: ftm0_default {
group0 {
pinmux = <FTM0_CH6_PTA1>,
<FTM0_CH7_PTA2>;
drive-strength = "low";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <FTM0_CH5_PTD5>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTB2>,
<I2C0_SDA_PTB3>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
spi0_default: spi0_default {
group0 {
pinmux = <SPI0_PCS4_PTC0>,
<SPI0_SCK_PTD1>,
<SPI0_SIN_PTD3>,
<SPI0_SOUT_PTD2>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart1_default: uart1_default {
group0 {
pinmux = <UART1_RX_PTE1>,
<UART1_TX_PTE0>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart2_default: uart2_default {
group0 {
pinmux = <UART2_RX_PTD2>,
<UART2_TX_PTD3>;
drive-strength = "low";
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_k22f/frdm_k22f-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 439 |
```yaml
board:
name: frdm_k22f
vendor: nxp
socs:
- name: mk22f51212
``` | /content/code_sandbox/boards/nxp/frdm_k22f/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
config BOARD_FRDM_K22F
select SOC_MK22F51212
select SOC_PART_NUMBER_MK22FN512VLH12
``` | /content/code_sandbox/boards/nxp/frdm_k22f/Kconfig.frdm_k22f | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# FRDM-K22F board
if BOARD_FRDM_K22F
config OSC_XTAL0_FREQ
default 8000000
config MCG_PRDIV0
default 0x3
config MCG_VDIV0
default 0xc
config MCG_FCRDIV
default 0
endif # BOARD_FRDM_K22F
``` | /content/code_sandbox/boards/nxp/frdm_k22f/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```yaml
identifier: frdm_k22f
name: NXP FRDM-K22F
type: mcu
arch: arm
ram: 64
toolchain:
- zephyr
- gnuarmemb
supported:
- adc
- arduino_gpio
- arduino_i2c
- arduino_spi
- dac
- gpio
- i2c
- nvs
- pwm
- spi
- usb_device
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/frdm_k22f/frdm_k22f.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
CONFIG_OSC_LOW_POWER=y
``` | /content/code_sandbox/boards/nxp/frdm_k22f/frdm_k22f_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```ini
source [find interface/cmsis-dap.cfg]
source [find target/k20.cfg]
``` | /content/code_sandbox/boards/nxp/frdm_k22f/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_k22fn512.dtsi>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include "frdm_k22f-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP Freedom MK22F board";
compatible = "nxp,mk22f12", "nxp,k22f", "nxp,k2x";
aliases {
led0 = &green_led;
led1 = &blue_led;
led2 = &red_led;
sw0 = &user_button_3;
sw1 = &user_button_2;
pwm-led0 = &green_pwm_led;
green-pwm-led = &green_pwm_led;
blue-pwm-led = &blue_pwm_led;
red-pwm-led = &red_pwm_led;
magn0 = &fxos8700;
accel0 = &fxos8700;
};
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,uart-pipe = &uart1;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpioa 1 0>;
label = "User LD1";
};
green_led: led_1 {
gpios = <&gpioa 2 0>;
label = "User LD2";
};
blue_led: led_2 {
gpios = <&gpiod 5 0>;
label = "User LD3";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: red_pwm_led {
label = "red_led";
pwms = <&ftm0 6 15625000 PWM_POLARITY_INVERTED>;
};
green_pwm_led: green_pwm_led {
label = "green_led";
pwms = <&ftm0 7 15625000 PWM_POLARITY_INVERTED>;
};
blue_pwm_led: blue_pwm_led {
label = "blue_led";
pwms = <&ftm0 5 15625000 PWM_POLARITY_INVERTED>;
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_2: button_0 {
label = "User SW2";
gpios = <&gpioc 1 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_3: button_1 {
label = "User SW3";
gpios = <&gpiob 17 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpiob 0 0>, /* A0 */
<1 0 &gpiob 1 0>, /* A1 */
<2 0 &gpioc 1 0>, /* A2 */
<3 0 &gpioc 2 0>, /* A3 */
<4 0 &gpiob 3 0>, /* A4 */
<5 0 &gpiob 2 0>, /* A5 */
<6 0 &gpiod 2 0>, /* D0 */
<7 0 &gpiod 3 0>, /* D1 */
<8 0 &gpiob 16 0>, /* D2 */
<9 0 &gpioa 2 0>, /* D3 */
<10 0 &gpioa 4 0>, /* D4 */
<11 0 &gpiob 18 0>, /* D5 */
<12 0 &gpioc 3 0>, /* D6 */
<13 0 &gpioc 6 0>, /* D7 */
<14 0 &gpiob 19 0>, /* D8 */
<15 0 &gpioa 1 0>, /* D9 */
<16 0 &gpiod 4 0>, /* D10 */
<17 0 &gpiod 6 0>, /* D11 */
<18 0 &gpiod 7 0>, /* D12 */
<19 0 &gpiod 5 0>, /* D13 */
<20 0 &gpioe 0 0>, /* D14 */
<21 0 &gpioe 1 0>; /* D15 */
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&adc0 {
status = "okay";
};
&dac0 {
status = "okay";
voltage-reference = <2>;
};
arduino_i2c: &i2c0 {
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
fxos8700: fxos8700@1c {
compatible = "nxp,fxos8700";
reg = <0x1c>;
int1-gpios = <&gpiod 0 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
};
};
arduino_spi: &spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
};
&ftm0 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm0_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
&uart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&uart2 {
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
};
zephyr_udc0: &usbotg {
compatible = "nxp,kinetis-usbd";
status = "okay";
num-bidir-endpoints = <8>;
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* The MCUBoot swap-move algorithm uses the last 3 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 (DT_SIZE_K(180) + DT_SIZE_K(6))>;
};
slot1_partition: partition@3E800 {
label = "image-1";
reg = <0x0003E800 DT_SIZE_K(180)>;
};
storage_partition: partition@6B800 {
label = "storage";
reg = <0x0006B800 DT_SIZE_K(82)>;
};
};
};
``` | /content/code_sandbox/boards/nxp/frdm_k22f/frdm_k22f.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,814 |
```cmake
board_runner_args(jlink "--device=MK66FN2M0xxx18")
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```yaml
identifier: rddrone_fmuk66
name: NXP RDDRONE-FMUK66
type: mcu
arch: arm
ram: 256
flash: 2048
toolchain:
- zephyr
- gnuarmemb
supported:
- can
- counter
- gpio
- i2c
- nvs
- pwm
- spi
- usb_device
- watchdog
vendor: nxp
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=160000000
CONFIG_OSC_EXTERNAL=y
# Enable MPU
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
# Enable Regulators
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_INIT_PRIORITY=75
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 80 |
```yaml
board:
name: rddrone_fmuk66
vendor: nxp
socs:
- name: mk66f18
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MK66FN2M0VMD18/signal_configuration.xml
*
*/
#include <nxp/kinetis/MK66FN2M0VMD18-pinctrl.h>
&pinctrl {
mdio_default: mdio_default {
group0 {
pinmux = <RMII0_MDIO_PTB0>;
drive-strength = "low";
drive-open-drain;
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <RMII0_MDC_PTB1>;
drive-strength = "low";
slew-rate = "fast";
};
};
enet_default: enet_default {
group0 {
pinmux = <RMII0_RXER_PTA5>,
<RMII0_RXD1_PTA12>,
<RMII0_RXD0_PTA13>,
<RMII0_CRS_DV_PTA14>,
<RMII0_TXEN_PTA15>,
<RMII0_TXD1_PTA17>,
<RMII0_TXD0_PTA16>;
drive-strength = "low";
slew-rate = "fast";
};
};
flexcan0_default: flexcan0_default {
group0 {
pinmux = <CAN0_RX_PTB19>,
<CAN0_TX_PTB18>;
drive-strength = "low";
slew-rate = "fast";
};
};
flexcan1_default: flexcan1_default {
group0 {
pinmux = <CAN1_RX_PTC16>,
<CAN1_TX_PTC17>;
drive-strength = "low";
slew-rate = "fast";
};
};
ftm0_default: ftm0_default {
group0 {
pinmux = <FTM0_CH0_PTC1>,
<FTM0_CH3_PTA6>,
<FTM0_CH4_PTD4>,
<FTM0_CH5_PTD5>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* conflicts with UART2 */
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH1_PTD1>,
<FTM3_CH4_PTC8>,
<FTM3_CH5_PTC9>,
<FTM3_CH6_PTE11>,
<FTM3_CH7_PTE12>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTE24>;
drive-strength = "low";
slew-rate = "fast";
};
group1 {
pinmux = <I2C0_SDA_PTE25>;
drive-strength = "low";
slew-rate = "fast";
drive-open-drain;
};
};
i2c1_default: i2c1_default {
group0 {
pinmux = <I2C1_SCL_PTC10>;
drive-strength = "low";
slew-rate = "fast";
};
group1 {
pinmux = <I2C1_SDA_PTC11>;
drive-strength = "low";
slew-rate = "fast";
drive-open-drain;
};
};
lpuart0_default: lpuart0_default {
group0 {
pinmux = <LPUART0_RX_PTD8>;
drive-strength = "low";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <LPUART0_TX_PTD9>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi0_default: spi0_default {
group0 {
pinmux = <SPI0_PCS2_PTC2>,
<SPI0_SCK_PTC5>,
<SPI0_SIN_PTC7>,
<SPI0_SOUT_PTC6>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi1_default: spi1_default {
group0 {
pinmux = <SPI1_PCS0_PTB10>,
<SPI1_PCS1_PTB9>,
<SPI1_SCK_PTB11>,
<SPI1_SIN_PTB17>,
<SPI1_SOUT_PTB16>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi2_default: spi2_default {
group0 {
pinmux = <SPI2_PCS0_PTB20>,
<SPI2_SCK_PTB21>,
<SPI2_SIN_PTB23>,
<SPI2_SOUT_PTB22>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTA1>,
<UART0_TX_PTA2>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart1_default: uart1_default {
group0 {
pinmux = <UART1_RX_PTC3>,
<UART1_TX_PTC4>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* conflicts with FTM3 */
uart2_default: uart2_default {
group0 {
pinmux = <UART2_RX_PTD2>,
<UART2_TX_PTD3>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart4_default: uart4_default {
group0 {
pinmux = <UART4_CTS_b_PTC13>,
<UART4_RTS_b_PTE27>,
<UART4_RX_PTC14>,
<UART4_TX_PTC15>;
drive-strength = "low";
slew-rate = "fast";
};
};
};
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,426 |
```unknown
# RDDRONE-FMUK66 board
if BOARD_RDDRONE_FMUK66
config OSC_XTAL0_FREQ
default 16000000
config MCG_PRDIV0
default 0x0
config MCG_VDIV0
default 0x4
config MCG_FCRDIV
default 1
if NETWORKING
config NET_L2_ETHERNET
default y if !MODEM
endif # NETWORKING
endif # BOARD_RDDRONE_FMUK66
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```restructuredtext
.. _frdm_k22f:
NXP FRDM-K22F
##############
Overview
********
The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22
MCUs.
- Form-factor compatible with the Arduino R3 pin layout
- Peripherals enable rapid prototyping, including a 6-axis digital
accelerometer and magnetometer to create full eCompass capabilities, a
tri-colored LED and 2 user push-buttons for direct interaction, a optional
microSD card slot, and headers for use with Bluetooth* and 2.4 GHz radio
add-on modules
- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter
running an open source bootloader, offers options for serial communication,
flash programming, and run-control debugging
.. image:: frdm_k22f.jpg
:align: center
:alt: FRDM-K22F
Hardware
********
- MK22FN512VLH12 (120 MHz, 512 KB flash memory, 128 KB RAM, low-power,
crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP))
- Dual role USB interface with micro-B USB connector
- RGB LED
- FXOS8700CQ accelerometer and magnetometer
- Two user push buttons
- Flexible power supply option - OpenSDAv2 USB, Kinetis K22 USB, and external source
- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors
- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface
software that provides:
- Mass storage device (MSD) flash programming interface
- CMSIS-DAP debug interface over a driver-less USB HID connection providing
run-control debugging and compatibility with IDE tools
- Virtual serial port interface
- Open source CMSIS-DAP software project
- Optional SDHC
For more information about the K22F SoC and FRDM-K22F board:
- `K22F Website`_
- `K22F Datasheet`_
- `K22F Reference Manual`_
- `FRDM-K22F Website`_
- `FRDM-K22F User Guide`_
- `FRDM-K22F Schematics`_
Supported Features
==================
The frdm_k22f board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the frdm_k64f board may have additional features
already supported, which can also be re-used on this frdm_k22f board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| SENSOR | off-chip | fxos8700 polling; |
| | | fxos8700 trigger |
+-----------+------------+-------------------------------------+
| RNGA | on-chip | entropy; |
| | | random |
+-----------+------------+-------------------------------------+
| FTFE | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/nxp/frdm_k22f/frdm_k22f_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
The K22F SoC has five pairs of pinmux/gpio controllers.
+-------+-----------------+---------------------------+
| Name | Function | Usage |
+=======+=================+===========================+
| PTA1 | GPIO | Red LED |
+-------+-----------------+---------------------------+
| PTA2 | GPIO | Green LED |
+-------+-----------------+---------------------------+
| PTD5 | GPIO | Blue LED |
+-------+-----------------+---------------------------+
| PTC1 | GPIO | SW2 |
+-------+-----------------+---------------------------+
| PTD0 | GPIO | FXOS8700 INT1 |
+-------+-----------------+---------------------------+
| PTD1 | GPIO | FXOS8700 INT2 |
+-------+-----------------+---------------------------+
| PTB17 | GPIO | SW3 |
+-------+-----------------+---------------------------+
| PTE1 | UART1_RX | UART Console |
+-------+-----------------+---------------------------+
| PTE0 | UART1_TX | UART Console |
+-------+-----------------+---------------------------+
| PTD2 | UART2_RX | UART BT HCI |
+-------+-----------------+---------------------------+
| PTD3 | UART2_TX | UART BT HCI |
+-------+-----------------+---------------------------+
| PTC4 | SPI0_PCS0 | SPI |
+-------+-----------------+---------------------------+
| PTD1 | SPI0_SCK | SPI |
+-------+-----------------+---------------------------+
| PTD2 | SPI0_SOUT | SPI |
+-------+-----------------+---------------------------+
| PTD3 | SPI0_SIN | SPI |
+-------+-----------------+---------------------------+
| PTB2 | I2C0_SCL | I2C / FXOS8700 |
+-------+-----------------+---------------------------+
| PTB3 | I2C0_SDA | I2C / FXOS8700 |
+-------+-----------------+---------------------------+
System Clock
============
The K22F SoC is configured to use the 8 MHz crystal oscillator on the board
with the on-chip PLL to generate a 72 MHz system clock in its RUN mode. This
clock was selected to allow for the maximum number of peripherals to be used
with the crystal and PLL clocks. Other clock configurations are possible
through NXP SDK currently.
Serial Port
===========
The K22F SoC has three UARTs. One is configured for the console, another for BT
HCI, and the remaining are not used.
USB
===
The K22F SoC has a USB OTG (USBOTG) controller that supports both
device and host functions through its micro USB connector (K22F USB).
Only USB device function is supported in Zephyr at the moment.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`.
Early versions of this board have an outdated version of the OpenSDA bootloader
and require an update. Please see the `DAPLink Bootloader Update`_ page for
instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader.
Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended)
your_sha256_hash--
Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program
the `OpenSDA DAPLink FRDM-K22F Firmware`_.
Option 2: :ref:`opensda-jlink-onboard-debug-probe`
--------------------------------------------------
Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
path.
Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program
the `Segger J-Link OpenSDA V2.1 Firmware`_. Note that Segger
does provide an OpenSDA J-Link Board-Specific Firmware for this board, however
it is not compatible with the DAPLink bootloader.
Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and
``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the
default runner from pyOCD to J-Link:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_k22f
:gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink
:goals: build
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console.
Connect a USB cable from your PC to J26.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_k22f
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.0.0 *****
Hello World! frdm_k22f
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: frdm_k22f
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.0.0 *****
Hello World! frdm_k22f
.. _FRDM-K22F Website:
path_to_url
.. _FRDM-K22F User Guide:
path_to_url
.. _FRDM-K22F Schematics:
path_to_url
.. _K22F Website:
path_to_url
.. _K22F Datasheet:
path_to_url
.. _K22F Reference Manual:
path_to_url
.. _OpenSDA DAPLink FRDM-K22F Firmware:
path_to_url
.. _DAPLink Bootloader Update:
path_to_url
.. _Segger J-Link OpenSDA V2.1 Firmware:
path_to_url
``` | /content/code_sandbox/boards/nxp/frdm_k22f/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,575 |
```unknown
config BOARD_RDDRONE_FMUK66
select SOC_MK66F18
select SOC_PART_NUMBER_MK66FN2M0VLQ18
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_k66.dtsi>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include "rddrone_fmuk66-pinctrl.dtsi"
#include <freq.h>
/ {
model = "NXP RDDRONE FMUK66 board";
compatible = "nxp,mk66f18", "nxp,k66f", "nxp,k6x";
aliases {
led0 = &amber_led;
led1 = &green_led;
pwm-led0 = &red_pwm_led;
pwm-led1 = &green_pwm_led;
pwm-led2 = &blue_pwm_led;
magn0 = &bmm150;
red-pwm-led = &red_pwm_led;
green-pwm-led = &green_pwm_led;
blue-pwm-led = &blue_pwm_led;
};
chosen {
/*
* Note: when using DMA, the SRAM region must be set to
* a memory region that is not cached by the chip. If the chosen
* sram region is changed and DMA is in use, you will
* encounter issues!
*/
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,console = &lpuart0;
zephyr,shell-uart = &lpuart0;
zephyr,uart-pipe = &lpuart0;
zephyr,canbus = &flexcan0;
};
leds {
compatible = "gpio-leds";
amber_led: led_0 {
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
label = "LED_AMB";
};
green_led: led_1 {
gpios = <&gpiod 14 GPIO_ACTIVE_LOW>;
label = "LED_GRN";
};
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: red_pwm_led {
pwms = <&ftm3 1 15625000 PWM_POLARITY_INVERTED>;
};
blue_pwm_led: blue_pwm_led {
pwms = <&ftm3 4 15625000 PWM_POLARITY_INVERTED>;
};
green_pwm_led: green_pwm_led {
pwms = <&ftm3 5 15625000 PWM_POLARITY_INVERTED>;
};
};
transceiver0: can-phy0 {
compatible = "nxp,tja1042", "can-transceiver-gpio";
max-bitrate = <5000000>;
standby-gpios = <&gpioc 19 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};
transceiver1: can-phy1 {
compatible = "nxp,tja1042", "can-transceiver-gpio";
max-bitrate = <5000000>;
standby-gpios = <&gpioc 18 GPIO_ACTIVE_HIGH>;
#phy-cells = <0>;
};
/* This regulator enables the 3V3_S line, which powers sensors on-board. */
reg-3v3-s {
compatible = "regulator-fixed";
regulator-name = "reg-3v3-s";
enable-gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>;
startup-delay-us = <2000>;
regulator-always-on;
status = "okay";
};
/* This regulator enables the onboard Ethernet PHY */
reg-3v3-neth {
compatible = "regulator-fixed";
regulator-name = "reg-3v3-neth";
enable-gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
regulator-always-on;
status = "okay";
};
/* This regulator enables the onboard SD card support */
reg-3v3-sd {
compatible = "regulator-fixed";
regulator-name = "reg-3v3-sd";
enable-gpios = <&gpiod 6 GPIO_ACTIVE_HIGH>;
regulator-always-on;
status = "okay";
};
};
&sim {
pllfll-select = <KINETIS_SIM_PLLFLLSEL_MCGPLLCLK>;
er32k-select = <KINETIS_SIM_ER32KSEL_RTC>;
};
&cpu0 {
clock-frequency = <160000000>;
};
&adc0 {
status = "okay";
};
&adc1 {
status = "okay";
};
&temp1 {
status = "okay";
};
&dac0 {
status = "okay";
voltage-reference = <2>;
};
/* PWM header is powered by FlexTimer 0 for channels 1 to 4 */
&ftm0 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm0_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
/* RGB LED powered by FlexTimer 3, and PWM headers for channel 5 and 6 */
&ftm3 {
status = "okay";
compatible = "nxp,kinetis-ftm-pwm";
#pwm-cells = <3>;
pinctrl-0 = <&ftm3_default>;
pinctrl-names = "default";
clock-source = "fixed";
};
/* LPUART connected to debug header */
&lpuart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&lpuart0_default>;
pinctrl-names = "default";
};
zephyr_udc0: &usbotg {
compatible = "nxp,kinetis-usbd";
status = "okay";
num-bidir-endpoints = <8>;
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&uart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&uart2 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
};
&uart4 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
};
&usbotg {
compatible = "nxp,kinetis-usbd";
status = "okay";
num-bidir-endpoints = <8>;
};
&gpioa {
status = "okay";
};
&gpiob {
status = "okay";
};
&gpioc {
status = "okay";
};
&gpiod {
status = "okay";
};
&gpioe {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 (DT_SIZE_K(928) + DT_SIZE_K(8))>;
};
slot1_partition: partition@FA000 {
label = "image-1";
reg = <0x000FA000 DT_SIZE_K(928)>;
};
storage_partition: partition@1E2000 {
label = "storage";
reg = <0x001E2000 DT_SIZE_K(120)>;
};
};
};
&enet_mac {
status = "okay";
pinctrl-0 = <&enet_default>;
pinctrl-names = "default";
phy-connection-type = "rmii";
phy-handle = <&phy>;
zephyr,random-mac-address;
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&mdio_default>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "ethernet-phy";
reg = <0>;
status = "okay";
};
};
&flexcan0 {
status = "okay";
pinctrl-0 = <&flexcan0_default>;
pinctrl-names = "default";
phys = <&transceiver0>;
};
&flexcan1 {
status = "okay";
pinctrl-0 = <&flexcan1_default>;
pinctrl-names = "default";
phys = <&transceiver1>;
};
/* external i2c port */
&i2c0 {
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
/* magnetometer (bmm150), barometer (bmp280), pressure (mpl3115),
* secure element (a7102ch) i2c bus
*/
&i2c1 {
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
/*
* This board does not have a BME280, it has a BMP280.
* The two parts are incredibly similar, so the BME280 driver works for
* BMP280 as well.
*/
bme280@76 {
compatible = "bosch,bme280";
status = "okay";
reg = <0x76>;
};
bmm150: bmm150@10 {
compatible = "bosch,bmm150";
status = "okay";
reg = <0x10>;
};
};
/* f-ram spi port */
&spi0 {
status = "okay";
pinctrl-0 = <&spi0_default>;
pinctrl-names = "default";
};
/* flash (w25x40), accel, magneto (fxos8700), gyro (fxas2100) */
&spi1 {
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-names = "default";
/*
* cs-gpios needs to be populated as per the schematics
* fxos8700 - CS#0
* fxas21002 - CS#1
*/
cs-gpios = <&gpiob 10 GPIO_ACTIVE_LOW>,
<&gpiob 9 GPIO_ACTIVE_LOW>;
clock-frequency = <DT_FREQ_M(1)>;
fxos8700@0 {
compatible = "nxp,fxos8700";
reg = <0>;
spi-max-frequency = <DT_FREQ_M(1)>;
reset-gpios = <&gpioa 25 GPIO_ACTIVE_HIGH>;
int1-gpios = <&gpioe 9 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpioe 10 GPIO_ACTIVE_LOW>;
status = "okay";
};
fxas21002@1 {
compatible = "nxp,fxas21002";
reg = <1>;
spi-max-frequency = <DT_FREQ_M(1)>;
reset-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
int1-gpios = <&gpioe 7 GPIO_ACTIVE_LOW>;
int2-gpios = <&gpioe 6 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
/* external spi */
&spi2 {
status = "okay";
pinctrl-0 = <&spi2_default>;
pinctrl-names = "default";
};
&edma0 {
status = "okay";
};
&pit0 {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,610 |
```restructuredtext
.. _rddrone_fmuk66:
NXP RDDRONE-FMUK66
##################
Overview
********
The RDDRONE FMUK66 is an drone control board with commonly used peripheral
connectors and a Kinetis K66 on board.
- Comes with a J-Link Edu Mini for programming and UART console.
.. image:: rddrone_fmuk66.jpg
:align: center
:alt: RDDRONE-FMUK66
Hardware
********
- MK66FN2MOVLQ18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power,
crystal-less USB, and 144 Low profile Quad Flat Package (LQFP))
- Dual role USB interface with micro-B USB connector
- RGB LED
- FXOS8700CQ accelerometer and magnetometer
- FXAS21002CQ gyro
- BMM150 magnetometer
- ML3114A2 barometer
- BMP280 barometer
- Connector for PWM servo/motor controls
- Connector for UART GPS/GLONASS
- SDHC
For more information about the K64F SoC and FRDM-K64F board:
- `K66F Website`_
- `K66F Datasheet`_
- `K66F Reference Manual`_
- `RDDRONE-FMUK66 Website`_
- `RDDRONE-FMUK66 User Guide`_
- `RDDRONE-FMUK66 Schematics`_
Supported Features
==================
The rddrone-fmuk66 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| DAC | on-chip | dac |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | soc flash |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| CAN | on-chip | can |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
| DMA | on-chip | dma |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig`
Other hardware features are not currently supported by the port.
System Clock
============
The K66F SoC is configured to use the 16 MHz external oscillator on the board
with the on-chip PLL to generate a 160 MHz system clock.
Serial Port
===========
The K66F SoC has six UARTs. LPUART0 is configured for the console, UART0 is labeled Serial 2,
UART2 is labeled GPS, UART4 is labeled Serial 1. Any of these UARTs may be used as the console by
overlaying the board device tree.
USB
===
The K66F SoC has a USB OTG (USBOTG) controller that supports both
device and host functions through its micro USB connector (K66F USB).
Only USB device function is supported in Zephyr at the moment.
Programming and Debugging
*************************
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Configuring a Debug Probe
=========================
A debug probe is used for both flashing and debugging the board. This board is
configured by default to use jlink. The board package
with accessories comes with a jlink mini edu and cable specifically for this board
along with a usb to uart that connects directly to the jlink mini edu. This is the expected
default configuration for programming and getting a console.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: rddrone-fmuk66
:gen-args:
:goals: build
Configuring a Console
=====================
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: rddrone-fmuk66
:goals: flash
Open a serial terminal, reset the board (press the SW1 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.7.0 *****
Hello World! rddrone-fmuk66
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: rddrone-fmuk66
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v2.7.0 *****
Hello World! rddrone-fmuk66
.. _RDDRONE-FMUK66 Website:
path_to_url
.. _RDDRONE-FMUK66 User Guide:
path_to_url
.. _RDDRONE-FMUK66 Schematics:
path_to_url
.. _K66F Website:
path_to_url
.. _K66F Datasheet:
path_to_url
.. _K66F Reference Manual:
path_to_url
``` | /content/code_sandbox/boards/nxp/rddrone_fmuk66/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,474 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ls1046a.dtsi>
/ {
model = "NXP ls1046a RDB";
compatible = "nxp,ls1046ardb";
chosen {
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,sram = &sram0;
};
cpus {
/delete-node/ cpu@0;
/delete-node/ cpu@1;
/delete-node/ cpu@2;
};
};
/delete-node/ &psci;
&uart1 {
status = "okay";
current-speed = <115200>;
};
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 149 |
```cmake
``` | /content/code_sandbox/boards/nxp/ls1046ardb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1 |
```unknown
# Platform Configuration
CONFIG_ARM64_VA_BITS_40=y
CONFIG_ARM64_PA_BITS_40=y
# 25 MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_AARCH64_IMAGE_HEADER=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Zephyr Kernel Configuration
CONFIG_MAX_THREAD_BYTES=5
CONFIG_MAX_XLAT_TABLES=10
# SMP support
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=2
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ARMV8_A_NS=y
# PSCI is supported
CONFIG_PM_CPU_OPS=y
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 162 |
```unknown
# Platform Configuration
CONFIG_ARM64_VA_BITS_40=y
CONFIG_ARM64_PA_BITS_40=y
# 25 MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_AARCH64_IMAGE_HEADER=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 94 |
```yaml
identifier: ls1046ardb/ls1046a/smp/4cores
name: NXP LS1046ARDB SMP on four CPU Cores
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
vendor: nxp
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
#
#
config BOARD_LS1046ARDB
select SOC_LS1046A
select SOC_PART_NUMBER_LS1046A
``` | /content/code_sandbox/boards/nxp/ls1046ardb/Kconfig.ls1046ardb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# Platform Configuration
CONFIG_ARM64_VA_BITS_40=y
CONFIG_ARM64_PA_BITS_40=y
# 25 MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000
# Zephyr Kernel Configuration
CONFIG_XIP=n
CONFIG_AARCH64_IMAGE_HEADER=y
CONFIG_MAX_THREAD_BYTES=5
CONFIG_MAX_XLAT_TABLES=10
# SMP support
CONFIG_SMP=y
CONFIG_MP_MAX_NUM_CPUS=4
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ARMV8_A_NS=y
# PSCI is supported
CONFIG_PM_CPU_OPS=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# Enable Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 155 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ls1046a.dtsi>
/ {
model = "NXP ls1046a RDB";
compatible = "nxp,ls1046ardb";
chosen {
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,sram = &sram0;
};
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 110 |
```yaml
board:
name: ls1046ardb
vendor: nxp
socs:
- name: ls1046a
variants:
- name: smp
variants:
- name: 4cores
``` | /content/code_sandbox/boards/nxp/ls1046ardb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 52 |
```yaml
identifier: ls1046ardb/ls1046a/smp
name: NXP LS1046ARDB SMP on CPU Core2 and Core3
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
vendor: nxp
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_ls1046a.dtsi>
/ {
model = "NXP ls1046a RDB";
compatible = "nxp,ls1046ardb";
chosen {
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,sram = &sram0;
};
cpus {
/delete-node/ cpu@0;
/delete-node/ cpu@1;
};
};
&uart1 {
status = "okay";
current-speed = <115200>;
};
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 133 |
```yaml
identifier: ls1046ardb
name: NXP LS1046ARDB on single CPU Core (NON-SMP)
type: mcu
arch: arm64
toolchain:
- zephyr
- cross-compile
ram: 1024
vendor: nxp
``` | /content/code_sandbox/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```cmake
#
#
#
board_runner_args(pyocd "--target=mimxrt1020")
board_runner_args(jlink "--device=MIMXRT1021xxx5A")
board_runner_args(linkserver "--device=MIMXRT1021xxxxx:EVK-MIMXRT1020")
include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 111 |
```unknown
config BOARD_MIMXRT1020_EVK
select SOC_PART_NUMBER_MIMXRT1021DAG5A
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```yaml
#
#
#
identifier: mimxrt1020_evk
name: NXP MIMXRT1020-EVK
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32768
flash: 8192
supported:
- arduino_gpio
- arduino_serial
- counter
- dma
- gpio
- i2c
- netif:eth
- spi
- usb_device
- adc
- sdhc
vendor: nxp
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```unknown
#
#
#
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_GPIO=y
CONFIG_ARM_MPU=y
CONFIG_HW_STACK_PROTECTION=y
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```restructuredtext
.. _nxp_ls1046ardb:
NXP LS1046A RDB
#################################
Overview
********
The LS1046A reference design board (RDB) is a high-performance computing,
evaluation, and development platform that supports the Layerscape LS1046A
architecture processor. The LS1046ARDB board supports the Layerscape LS1046A
processor and is optimized to support the DDR4 memory and a full complement
of high-speed SerDes ports.
The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
cores with packet processing acceleration and high-speed peripherals. The
impressive performance of more than 32,000 CoreMarks, paired with 10 Gb
Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an
excellent combination for a range of enterprise and service provider
networking, storage, security and industrial applications.
Hardware
********
LS1046A RDB boards supports the following features:
- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
- Supports 8 GB DDR4 SDRAM memory
- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
memory device
- One 512 MB SLC NAND flash with ECC support (1.8 V)
- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
- Support two 64 MB onboard QSPI NOR flash memories
- USB:
- Two USB 3.0 controllers with integrated PHYs.
- One USB1 3.0 port is connected to a Type A host connector.
- One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector.
- One USB2.0 is connected to miniPCIe connector .
- Ethernet:
- Supports SGMII 1G PHYs at Lane 2 and Lane 3
- Supports SFP+module with XFI retimers
- Supports AQR106/107 10G PHY with XFI/2.5G SGMII
- PCIe and SATA:
- Mini PCIe express x1 (Gen1/2/3)card
- Standard PCIe x1 (Gen1/2/3) card
- Standard PCIe x1 (Gen1/2/3) card
- One SATA 3.0 connector
Supported Features
==================
NXP LS1046A RDB board default configuration supports the following
hardware features:
+-----------+------------+--------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================================+
| GIC-400 | on-chip | GICv2 interrupt controller |
+-----------+------------+--------------------------------------+
| ARM TIMER | on-chip | System Clock |
+-----------+------------+--------------------------------------+
| UART | on-chip | NS16550 compatible serial port |
+-----------+------------+--------------------------------------+
Other hardware features have not been enabled yet for this board.
The default configuration can be found in the defconfig file for NON-SMP:
:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig`
Or for SMP running on all four CPU Cores:
:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig`
Or for SMP running on 2 CPU Cores (Core2 and Core3):
:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig`
There are two serial port on the board: uart1 and uart2, Zephyr is using
uart2 as serial console.
Programming and Debugging
*************************
Use the following configuration to run basic Zephyr applications and
kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample:
1. Non-SMP mode
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: ls1046ardb
:goals: build
This will build an image with the synchronization sample app.
Use u-boot to load and kick Zephyr.bin to CPU Core0:
.. code-block:: console
tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000;
Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3:
.. code-block:: console
tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000;
It will display the following console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 ***
thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
thread_b: Hello World from cpu 0 on nxp_ls1046ardb!
thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
2. SMP mode running on 4 CPU Cores
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: ls1046ardb/ls1046a/smp/4cores
:goals: build
This will build an image with the synchronization sample app.
Use u-boot to load and kick Zephyr.bin to CPU Core0:
.. code-block:: console
tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000;
It will display the following console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 ***
Secondary CPU core 1 (MPID:0x1) is up
Secondary CPU core 2 (MPID:0x2) is up
Secondary CPU core 3 (MPID:0x3) is up
thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
3. SMP mode running on 2 CPU Cores: Core2 and Core3
.. zephyr-app-commands::
:zephyr-app: samples/synchronization
:host-os: unix
:board: ls1046ardb/ls1046a/smp
:goals: build
This will build an image with the synchronization sample app.
Use u-boot to load and kick Zephyr.bin to CPU Core2:
.. code-block:: console
tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000;
It will display the following console output:
.. code-block:: console
*** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 ***
Secondary CPU core 1 (MPID:0x3) is up
thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
thread_a: Hello World from cpu 0 on nxp_ls1046ardb!
4. Running Zephyr on Jailhouse inmate Cell
Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse
inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3
for Zephyr SMP 2cores image.
1) Use root Cell dts to boot root Cell Linux.
2) Install Jailhouse module:
.. code-block:: console
modprobe jailhouse
3) Run Zephyr demo in inmate Cell:
.. code-block:: console
jailhouse enable ls1046a-rdb.cell
jailhouse cell create ls1046a-rdb-inmate-demo.cell
jailhouse cell load 1 zephyr.bin --address 0xc0000000
jailhouse cell start 1
Flashing
========
Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card,
EMMC, QSPI Flash or downloaded from network in uboot.
Debugging
=========
LS1046A RDB board includes one JTAG connector on board, connect it to
CodeWarrior TAP for debugging.
References
==========
`Layerscape LS1046A Reference Design Board <path_to_url`_
`LS1046A Reference Manual <path_to_url`_
``` | /content/code_sandbox/boards/nxp/ls1046ardb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,985 |
```yaml
board:
name: mimxrt1020_evk
vendor: nxp
socs:
- name: mimxrt1021
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# MIMXRT1020-EVK board
if BOARD_MIMXRT1020_EVK
config DEVICE_CONFIGURATION_DATA
default y
config NXP_IMX_EXTERNAL_SDRAM
default y
if NETWORKING
config NET_L2_ETHERNET
default y
config ETH_MCUX_PHY_RESET
default y
endif # NETWORKING
endif # BOARD_MIMXRT1020_EVK
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_rt1020.dtsi>
#include "mimxrt1020_evk-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "NXP MIMXRT1020-EVK board";
compatible = "nxp,mimxrt1021";
aliases {
led0 = &green_led;
sw0 = &user_button;
sdhc0 = &usdhc1;
};
chosen {
zephyr,flash-controller = &is25wp064;
zephyr,flash = &is25wp064;
zephyr,code-partition = &slot0_partition;
zephyr,sram = &sdram0;
zephyr,itcm = &itcm;
zephyr,dtcm = &dtcm;
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
};
sdram0: memory@80000000 {
/* ISSI IS42S16160J-6TLI */
device_type = "memory";
reg = <0x80000000 DT_SIZE_M(32)>;
};
leds {
compatible = "gpio-leds";
green_led: led-1 {
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button-1 {
label = "User SW4";
gpios = <&gpio5 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
zephyr,code = <INPUT_KEY_0>;
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio1 26 0>, /* A0 */
<1 0 &gpio1 27 0>, /* A1 */
<2 0 &gpio1 28 0>, /* A2 */
<3 0 &gpio1 29 0>, /* A3 */
<4 0 &gpio1 31 0>, /* A4 */
<5 0 &gpio1 30 0>, /* A5 */
<6 0 &gpio1 25 0>, /* D0 */
<7 0 &gpio1 24 0>, /* D1 */
<8 0 &gpio1 9 0>, /* D2 */
<9 0 &gpio1 7 0>, /* D3 */
<10 0 &gpio1 5 0>, /* D4 */
<11 0 &gpio1 6 0>, /* D5 */
<12 0 &gpio1 14 0>, /* D6 */
<13 0 &gpio1 22 0>, /* D7 */
<14 0 &gpio1 23 0>, /* D8 */
<15 0 &gpio1 15 0>, /* D9 */
<16 0 &gpio1 11 0>, /* D10 */
<17 0 &gpio1 12 0>, /* D11 */
<18 0 &gpio1 13 0>, /* D12 */
<19 0 &gpio1 10 0>, /* D13 */
<20 0 &gpio3 23 0>, /* D14 */
<21 0 &gpio3 22 0>; /* D15 */
};
};
arduino_serial: &lpuart2 {
pinctrl-0 = <&pinmux_lpuart2>;
pinctrl-1 = <&pinmux_lpuart2_sleep>;
pinctrl-names = "default", "sleep";
};
&flexspi {
status = "okay";
reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
is25wp064: is25wp064@0 {
compatible = "nxp,imx-flexspi-nor";
size = <67108864>;
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [9d 70 17];
erase-block-size = <4096>;
write-block-size = <1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(128)>;
};
/* The MCUBoot swap-move algorithm uses the last 2 sectors
* of the primary slot0 for swap status and move.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
};
slot1_partition: partition@322000 {
label = "image-1";
reg = <0x00322000 DT_SIZE_M(3)>;
};
storage_partition: partition@622000 {
label = "storage";
reg = <0x00622000 (DT_SIZE_M(2) - DT_SIZE_K(136))>;
};
};
};
};
&enet_mac {
status = "okay";
pinctrl-0 = <&pinmux_enet>;
pinctrl-names = "default";
phy-handle = <&phy>;
zephyr,random-mac-address;
phy-connection-type = "rmii";
};
&enet_mdio {
status = "okay";
pinctrl-0 = <&pinmux_enet_mdio>;
pinctrl-names = "default";
phy: phy@0 {
compatible = "microchip,ksz8081";
reg = <0>;
status = "okay";
reset-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
int-gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
microchip,interface-type = "rmii";
};
};
&enet_ptp_clock {
status = "okay";
pinctrl-0 = <&pinmux_ptp>;
pinctrl-names = "default";
};
&lpi2c1 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c1>;
pinctrl-names = "default";
};
&lpi2c4 {
status = "okay";
pinctrl-0 = <&pinmux_lpi2c4>;
pinctrl-names = "default";
};
&lpuart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&pinmux_lpuart1>;
pinctrl-1 = <&pinmux_lpuart1_sleep>;
pinctrl-names = "default", "sleep";
};
&lpspi1 {
status = "okay";
/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
dmas = <&edma0 0 13>, <&edma0 1 14>;
dma-names = "rx", "tx";
pinctrl-0 = <&pinmux_lpspi1>;
pinctrl-names = "default";
};
zephyr_udc0: &usb1 {
status = "okay";
};
&usdhc1 {
status = "okay";
no-1-8-v;
pinctrl-0 = <&pinmux_usdhc1>;
pinctrl-1 = <&pinmux_usdhc1_slow>;
pinctrl-2 = <&pinmux_usdhc1_med>;
pinctrl-3 = <&pinmux_usdhc1_fast>;
pinctrl-names = "default", "slow", "med", "fast";
cd-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pwr-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
sdmmc {
compatible = "zephyr,sdmmc-disk";
status = "okay";
};
};
&adc1 {
status = "okay";
pinctrl-0 = <&pinmux_adc1>;
pinctrl-names = "default";
};
&sai3 {
pinctrl-0 = <&pinmux_sai3>;
pinctrl-names = "default";
};
&edma0 {
status = "okay";
};
/* GPT and Systick are enabled. If power management is enabled, the GPT
* timer will be used instead of systick, as allows the core clock to
* be gated.
*/
&gpt_hw_timer {
status = "okay";
};
&systick {
status = "okay";
};
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,987 |
```unknown
/*
*
* Note: File generated by gen_board_pinctrl.py
* from mimxrt1020_evk.mex
*/
#include <nxp/nxp_imx/rt/mimxrt1021dag5a-pinctrl.dtsi>
&pinctrl {
/* ADC1 inputs 10 and 11 */
pinmux_adc1: pinmux_adc1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_10_adc1_in10>,
<&iomuxc_gpio_ad_b1_11_adc1_in11>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* Note: USER_LED conflicts with ENET_RST */
pinmux_enet: pinmux_enet {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_08_enet_ref_clk>;
bias-disable;
drive-strength = "r0-6";
slew-rate = "fast";
nxp,speed = "50-mhz";
input-enable;
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_09_enet_rx_data1>,
<&iomuxc_gpio_ad_b0_11_enet_rx_en>,
<&iomuxc_gpio_ad_b0_14_enet_tx_data0>,
<&iomuxc_gpio_ad_b0_15_enet_tx_data1>,
<&iomuxc_gpio_ad_b0_13_enet_tx_en>,
<&iomuxc_gpio_ad_b0_12_enet_rx_er>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_ad_b0_10_enet_rx_data0>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <&iomuxc_gpio_emc_40_enet_mdio>,
<&iomuxc_gpio_emc_41_enet_mdc>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_06_gpio1_io22>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_ad_b0_04_gpio1_io04>;
drive-strength = "r0-5";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
pinmux_ptp: pinmux_ptp {
/* Intentionally empty */
};
pinmux_flexcan1: pinmux_flexcan1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_00_flexcan1_tx>,
<&iomuxc_gpio_sd_b1_01_flexcan1_rx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c1: pinmux_lpi2c1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_14_lpi2c1_scl>,
<&iomuxc_gpio_ad_b1_15_lpi2c1_sda>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
pinmux_lpi2c4: pinmux_lpi2c4 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_03_lpi2c4_sda>,
<&iomuxc_gpio_sd_b1_02_lpi2c4_scl>;
drive-strength = "r0-6";
drive-open-drain;
slew-rate = "slow";
nxp,speed = "100-mhz";
input-enable;
};
};
/* conflicts with enet pinmux */
pinmux_lpspi1: pinmux_lpspi1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_10_lpspi1_sck>,
<&iomuxc_gpio_ad_b0_11_lpspi1_pcs0>,
<&iomuxc_gpio_ad_b0_12_lpspi1_sdo>,
<&iomuxc_gpio_ad_b0_13_lpspi1_sdi>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1: pinmux_lpuart1 {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_07_lpuart1_rx>,
<&iomuxc_gpio_ad_b0_06_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_lpuart1_sleep: pinmux_lpuart1_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b0_07_gpio1_io07>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_06_lpuart1_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with user led */
pinmux_lpuart2: pinmux_lpuart2 {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_lpuart2_rx>,
<&iomuxc_gpio_ad_b1_08_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* conflicts with user led */
pinmux_lpuart2_sleep: pinmux_lpuart2_sleep {
group0 {
pinmux = <&iomuxc_gpio_ad_b1_09_gpio1_io25>;
drive-strength = "r0-6";
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b1_08_lpuart2_tx>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_sai3: pinmux_sai3 {
group0 {
pinmux = <&iomuxc_gpio_sd_b1_06_sai3_tx_bclk>,
<&iomuxc_gpio_sd_b1_07_sai3_tx_sync>,
<&iomuxc_gpio_sd_b1_08_sai3_tx_data>,
<&iomuxc_gpio_sd_b1_11_sai3_rx_data>,
<&iomuxc_gpio_emc_28_sai3_mclk>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
pinmux_usdhc1: pinmux_usdhc1 {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>,
<&iomuxc_gpio_sd_b0_06_gpio3_io19>;
drive-strength = "r0";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group2 {
pinmux = <&iomuxc_gpio_ad_b1_07_usdhc1_vselect>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group3 {
pinmux = <&iomuxc_gpio_sd_b1_04_gpio3_io24>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
/* fast pinmux settings for USDHC (over 100 Mhz) */
pinmux_usdhc1_fast: pinmux_usdhc1_fast {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "200-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "200-mhz";
};
};
/* medium pinmux settings for USDHC (under 100 Mhz) */
pinmux_usdhc1_med: pinmux_usdhc1_med {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "100-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "100-mhz";
};
};
/* slow pinmux settings for USDHC (under 50 Mhz) */
pinmux_usdhc1_slow: pinmux_usdhc1_slow {
group0 {
pinmux = <&iomuxc_gpio_sd_b0_03_usdhc1_clk>;
bias-disable;
drive-strength = "r0-7";
input-schmitt-enable;
slew-rate = "fast";
nxp,speed = "50-mhz";
};
group1 {
pinmux = <&iomuxc_gpio_sd_b0_02_usdhc1_cmd>,
<&iomuxc_gpio_sd_b0_04_usdhc1_data0>,
<&iomuxc_gpio_sd_b0_05_usdhc1_data1>,
<&iomuxc_gpio_sd_b0_00_usdhc1_data2>,
<&iomuxc_gpio_sd_b0_01_usdhc1_data3>;
drive-strength = "r0-7";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "47k";
slew-rate = "fast";
nxp,speed = "50-mhz";
};
};
/* user led and board SW0 */
pinmux_user: pinmux_user {
group0 {
pinmux = <&iomuxc_snvs_wakeup_gpio5_io00>;
drive-strength = "r0-4";
input-schmitt-enable;
bias-pull-up;
bias-pull-up-value = "100k";
slew-rate = "slow";
};
group1 {
pinmux = <&iomuxc_gpio_ad_b0_05_gpio1_io05>;
drive-strength = "r0-6";
slew-rate = "slow";
nxp,speed = "100-mhz";
};
};
};
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,270 |
```cmake
#
#
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
/*
*/
#include <zephyr/dt-bindings/pinctrl/lpc11u6x-pinctrl.h>
&pinctrl {
uart0_default: uart0_default {
group0 {
pinmux = <U0_RXD_PIO0_18>,
<U0_TXD_PIO0_19>;
nxp,disable-analog-filter;
};
};
uart4_default: uart4_default {
group0 {
pinmux = <U4_RXD_PIO2_11>,
<U4_TXD_PIO2_12>;
nxp,disable-analog-filter;
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PIO0_4>,
<I2C0_SDA_PIO0_5>;
nxp,i2c-mode;
nxp,i2c-filter = "slow";
nxp,disable-analog-filter;
};
};
i2c0_fast: i2c0_fast{
group0 {
pinmux = <I2C0_SCL_PIO0_4>,
<I2C0_SDA_PIO0_5>;
nxp,i2c-mode;
nxp,i2c-filter = "fast";
nxp,disable-analog-filter;
};
};
syscon_default: syscon_default {
group0 {
pinmux = <XTALOUT_PIO2_1>,
<XTALIN_PIO2_0>;
nxp,analog-mode;
};
};
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 353 |
```unknown
CONFIG_UART_INTERRUPT_DRIVEN=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
CONFIG_GPIO=y
CONFIG_BUILD_OUTPUT_HEX=y
# Since the board has little memory (32k), stack sizes are lowered
# so that the application has more RAM for itself.
CONFIG_MAIN_STACK_SIZE=512
CONFIG_ISR_STACK_SIZE=768
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1=y
CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_USB_RAM=y
CONFIG_CLOCK_CONTROL_LPC11U6X_PLL_SRC_SYSOSC=y
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```yaml
identifier: lpcxpresso11u68
name: NXP LPCxpresso 11U68
type: mcu
arch: arm
ram: 32
flash: 256
toolchain:
- zephyr
supported:
- arduino_serial
- clock_controller
- gpio
- i2c
- serial
- eeprom
vendor: nxp
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```restructuredtext
.. _mimxrt1020_evk:
NXP MIMXRT1020-EVK
##################
Overview
********
The i.MX RT1020 expands the i.MX RT crossover processor families by providing
high-performance feature set in low-cost LQFP packages, further simplifying
board design and layout for customers. The i.MX RT1020 runs on the Arm
Cortex-M7 core at 500 MHz.
.. image:: mimxrt1020_evk.jpg
:align: center
:alt: MIMXRT1020-EVK
Hardware
********
- MIMXRT1021DAG5A MCU
- Memory
- 256 Mbit SDRAM
- 64 Mbit QSPI Flash
- TF socket for SD card
- Connectivity
- 10/100 Mbit/s Ethernet PHY
- Micro USB host and OTG connectors
- CAN transceivers
- Arduino interface
- Audio
- Audio Codec
- 4-pole audio headphone jack
- Microphone
- External speaker connection
- Power
- 5 V DC jack
- Debug
- JTAG 20-pin connector
- OpenSDA with DAPLink
For more information about the MIMXRT1020 SoC and MIMXRT1020-EVK board, see
these references:
- `i.MX RT1020 Website`_
- `i.MX RT1020 Datasheet`_
- `i.MX RT1020 Reference Manual`_
- `MIMXRT1020-EVK Website`_
- `MIMXRT1020-EVK User Guide`_
- `MIMXRT1020-EVK Design Files`_
External Memory
===============
This platform has the following external memories:
+----------------+------------+-------------------------------------+
| Device | Controller | Status |
+================+============+=====================================+
| MT48LC16M16A2P | SEMC | Enabled via device configuration |
| | | data block, which sets up SEMC at |
| | | boot time |
+----------------+------------+-------------------------------------+
| IS25LP064A | FLEXSPI | Enabled via flash configurationn |
| | | block, which sets up FLEXSPI at |
| | | boot time |
+----------------+------------+-------------------------------------+
Supported Features
==================
The mimxrt1020_evk board configuration supports the hardware features listed
below. For additional features not yet supported, please also refer to the
:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
NXP prioritizes enabling the superset board with NXP's Full Platform Support for
Zephyr. Therefore, the mimxrt1064_evk board may have additional features
already supported, which can also be re-used on this mimxrt1020_evk board:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | QSPI flash |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SDHC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| ENET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| USB | on-chip | USB device |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| GPT | on-chip | gpt |
+-----------+------------+-------------------------------------+
| TRNG | on-chip | entropy |
+-----------+------------+-------------------------------------+
| FLEXSPI | on-chip | flash programming |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig`
Other hardware features are not currently supported by the port.
Connections and I/Os
====================
The MIMXRT1020 SoC has five pairs of pinmux/gpio controllers.
+---------------+-----------------+---------------------------+
| Name | Function | Usage |
+===============+=================+===========================+
| GPIO_AD_B0_05 | GPIO | LED |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_06 | LPUART1_TX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_07 | LPUART1_RX | UART Console |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_08 | LPUART2_TX | UART BT HCI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_09 | LPUART2_RX | UART BT HCI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_14 | LPI2C1_SCL | I2C |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_15 | LPI2C1_SDA | I2C |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_02 | LPI2C4_SCL | I2C |
+---------------+-----------------+---------------------------+
| GPIO_SD_B1_03 | LPI2C4_SDA | I2C |
+---------------+-----------------+---------------------------+
| WAKEUP | GPIO | SW0 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_04 | ENET_RST | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_08 | ENET_REF_CLK | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_09 | ENET_RX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_10 | ENET_RX_DATA00/LPSPI1_SCK | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_11 | ENET_RX_EN/LPSPI1_PCS0 | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_12 | ENET_RX_ER/LPSPI1_SDO | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_13 | ENET_TX_EN/LPSPI1_SDI | Ethernet/SPI |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_14 | ENET_TX_DATA00 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B0_15 | ENET_TX_DATA01 | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_06 | ENET_INT | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_41 | ENET_MDC | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_EMC_40 | ENET_MDIO | Ethernet |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_07 | USDHC1_VSELECT | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_02 | USDHC1_CMD | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_03 | USDHC1_CLK | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_04 | USDHC1_DATA0 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_05 | USDHC1_DATA1 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_00 | USDHC1_DATA2 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_01 | USDHC1_DATA3 | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_SD_B0_06 | USDHC1_CD_B | SD Card |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_10 | ADC | ADC1 Channel 10 |
+---------------+-----------------+---------------------------+
| GPIO_AD_B1_11 | ADC | ADC1 Channel 11 |
+---------------+-----------------+---------------------------+
System Clock
============
The MIMXRT1020 SoC is configured to use SysTick as the system clock source,
running at 500MHz.
When power management is enabled, the 32 KHz low frequency
oscillator on the board will be used as a source for the GPT timer to
generate a system clock. This clock enables lower power states, at the
cost of reduced resolution
Serial Port
===========
The MIMXRT1020 SoC has eight UARTs. ``LPUART1`` is configured for the console,
``LPUART2`` for the Bluetooth Host Controller Interface (BT HCI), and the
remaining are not used.
Programming and Debugging
*************************
This board supports 3 debug host tools. Please install your preferred host
tool, then follow the instructions in `Configuring a Debug Probe`_ to
configure the board appropriately.
* :ref:`linkserver-debug-host-tools` (Default, Supported by NXP)
* :ref:`jlink-debug-host-tools` (Supported by NXP)
* :ref:`pyocd-debug-host-tools` (Not supported by NXP)
Once the host tool and board are configured, build and flash applications
as usual (see :ref:`build_an_application` and :ref:`application_run` for more
details).
Configuring a Debug Probe
=========================
For the RT1020, J47/J48 are the SWD isolation jumpers, J42 is the DFU
mode jumper, and J16 is the 20 pin JTAG/SWD header.
.. include:: ../../common/rt1xxx-lpclink2-debug.rst
:start-after: rt1xxx-lpclink2-probes
Configuring a Console
=====================
Regardless of your choice in debug probe, we will use the OpenSDA
microcontroller as a usb-to-serial adapter for the serial console. Check that
jumpers J25 and J26 are **on** (they are on by default when boards ship from
the factory) to connect UART signals to the OpenSDA microcontroller.
Connect a USB cable from your PC to J23.
Use the following settings with your serial terminal of choice (minicom, putty,
etc.):
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
Flashing
========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1020_evk
:goals: flash
Open a serial terminal, reset the board (press the SW5 button), and you should
see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1020_evk
Debugging
=========
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: mimxrt1020_evk
:goals: debug
Open a serial terminal, step through the application in your debugger, and you
should see the following message in the terminal:
.. code-block:: console
***** Booting Zephyr OS v1.14.0-rc1 *****
Hello World! mimxrt1020_evk
.. _MIMXRT1020-EVK Website:
path_to_url
.. _MIMXRT1020-EVK User Guide:
path_to_url
.. _MIMXRT1020-EVK Design Files:
path_to_url
.. _i.MX RT1020 Website:
path_to_url
.. _i.MX RT1020 Datasheet:
path_to_url
.. _i.MX RT1020 Reference Manual:
path_to_url
.. _OpenSDA J-Link MIMXRT1020-EVK Firmware:
path_to_url
``` | /content/code_sandbox/boards/nxp/mimxrt1020_evk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,850 |
```yaml
board:
name: lpcxpresso11u68
vendor: nxp
socs:
- name: lpc11u68
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_lpc11u68.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include "lpcxpresso11u68-pinctrl.dtsi"
/ {
model = "NXP LPCXPRESSO11U68 board";
compatible = "nxp,lpcxpresso11u68", "nxp,lpc";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart0;
};
/* These aliases are provided for compatibility with samples. */
aliases {
led0 = &led0;
led1 = &led1;
led2 = &led2;
sw0 = &isp_button;
sw1 = &wake_up_button;
eeprom-0 = &eeprom0;
};
gpio_keys {
compatible = "gpio-keys";
isp_button: button_0 {
gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
label = "ISP enable button";
zephyr,code = <INPUT_KEY_0>;
};
wake_up_button: button_1 {
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
label = "Wake-up button";
zephyr,code = <INPUT_KEY_WAKEUP>;
};
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
label = "Green LED 0";
};
led1: led_1 {
gpios = <&gpio2 17 GPIO_ACTIVE_LOW>;
label = "Red LED 1";
};
led2: led_2 {
gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
label = "Blue LED 2";
};
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio1 9 0>, /* A0 */
<1 0 &gpio0 14 0>, /* A1 */
<2 0 &gpio0 13 0>, /* A2 */
<3 0 &gpio0 12 0>, /* A3 */
<4 0 &gpio0 23 0>, /* A4 */
<5 0 &gpio0 11 0>, /* A5 */
<6 0 &gpio2 11 0>, /* D0 */
<7 0 &gpio2 12 0>, /* D1 */
<8 0 &gpio1 18 0>, /* D2 */
<9 0 &gpio1 24 0>, /* D3 */
<10 0 &gpio1 19 0>, /* D4 */
<11 0 &gpio1 26 0>, /* D5 */
<12 0 &gpio1 27 0>, /* D6 */
<13 0 &gpio1 25 0>, /* D7 */
<14 0 &gpio1 28 0>, /* D8 */
<15 0 &gpio2 3 0>, /* D9 */
<16 0 &gpio0 2 0>, /* D10 */
<17 0 &gpio0 9 0>, /* D11 */
<18 0 &gpio0 9 0>, /* D12 */
<19 0 &gpio1 29 0>, /* D13 */
<20 0 &gpio0 5 0>, /* D14 */
<21 0 &gpio0 4 0>; /* D15 */
};
};
&uart0 {
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
arduino_serial: &uart4 {
pinctrl-0 = <&uart4_default>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
arduino_i2c: &i2c0 {
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_fast>;
pinctrl-names = "default", "fast-plus";
status = "okay";
};
&cpu0 {
clock-frequency = <48000000>;
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&gpio2 {
status = "okay";
};
&syscon {
pinctrl-0 = <&syscon_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,091 |
```unknown
#
config BOARD_LPCXPRESSO11U68
select SOC_LPC11U68
select SOC_PART_NUMBER_LPC11U68JBD100
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```ini
#
# NXP LPCXpresso11U68 (evaluation board OM13058)
#
# path_to_url
# path_to_url
# path_to_url
#
# The on-board LPC-Link2 debug probe (based on a NXP LPC43xx MCU) provides
# either a CMSIS-DAP or a J-Link interface. It depends on the version of the
# embedded firmware. Uncomment the line corresponding to yours.
source [find interface/cmsis-dap.cfg]
# source [find interface/jlink.cfg]
# NXP LPC11U68 Cortex-M0 with 256kB flash and 32kB + 4kB SRAM.
set WORKAREASIZE 0x5000
source [find target/lpc11xx.cfg]
# This ensures that the interrupt vectors (0x0000-0x0200) are re-mapped to
# flash after the "reset halt" command. Else the load/verify functions won't
# work correctly.
#
# Table 8. System memory remap register (SYSMEMREMAP, address 0x40048000) bit
# description
# Bit Symbol Value Description
# 1:0 MAP System memory remap
# 0x0 Boot Loader Mode. Interrupt vectors are re-mapped to
# Boot ROM.
# 0x1 User RAM Mode. Interrupt vectors are re-mapped to
# Static RAM.
# 0x2 User Flash Mode. Interrupt vectors are not re-mapped
# and reside in Flash.
# 31:2 - - Reserved.
$_TARGETNAME configure -event reset-end {
mww 0x40048000 0x02
}
# Enable Zephyr thread awareness.
$_TARGETNAME configure -rtos Zephyr
adapter speed 100
``` | /content/code_sandbox/boards/nxp/lpcxpresso11u68/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 386 |
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