text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/hardkernel/odroid_go/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
# required to enable LCD backlight
CONFIG_REGULATOR=y
``` | /content/code_sandbox/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```yaml
board:
name: odroid_go
vendor: hardkernel
socs:
- name: esp32
``` | /content/code_sandbox/boards/hardkernel/odroid_go/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```unknown
# ODROID-GO Game Kit configuration
config BOARD_ODROID_GO
select SOC_ESP32_WROVER_E_N16R4
select SOC_ESP32_PROCPU if BOARD_ODROID_GO_ESP32_PROCPU
select SOC_ESP32_APPCPU if BOARD_ODROID_GO_ESP32_APPCPU
``` | /content/code_sandbox/boards/hardkernel/odroid_go/Kconfig.odroid_go | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```unknown
# ODROID-GO Game Kit configuration
if BOARD_ODROID_GO_ESP32_PROCPU
config DISK_DRIVER_SDMMC
default y if DISK_ACCESS
config SPI
default y if DISK_DRIVER_SDMMC
config ESP_SPIRAM
default y if !MCUBOOT
choice SPIRAM_TYPE
default SPIRAM_TYPE_ESPPSRAM32
endchoice
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
endif # BOARD_ODROID_GO_ESP32_PROCPU
if BOARD_ODROID_GO_ESP32_APPCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
default 4096
endif # BOARD_ODROID_GO_ESP32_APPCPU
``` | /content/code_sandbox/boards/hardkernel/odroid_go/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 164 |
```restructuredtext
.. _boards-ct:
CTHINGS.CO
##########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/ct/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# CTHINGS.CO Connectivity Card board configuration
config BOARD_CTCC
select SOC_NRF52840_QIAA if BOARD_CTCC_NRF52840
``` | /content/code_sandbox/boards/ct/ctcc/Kconfig.ctcc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
board_runner_args(nrfjprog "--softreset")
board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000")
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/ct/ctcc/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 68 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/ct/ctcc/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: ctcc
socs:
- name: nrf52840
``` | /content/code_sandbox/boards/ct/ctcc/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
identifier: ctcc/nrf52840
name: CTHINGS.CO Connectivity Card nRF52840
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- ble
- gpio
- usb_cdc
- usb_device
- watchdog
vendor: ct
``` | /content/code_sandbox/boards/ct/ctcc/ctcc_nrf52840.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52840_qiaa.dtsi>
/ {
model = "CTHINGS.CO Connectivity Card nRF52840";
compatible = "ct,ctcc-nrf52840";
chosen {
zephyr,console = &cdc_acm_uart;
zephyr,shell-uart = &cdc_acm_uart;
zephyr,uart-mcumgr = &cdc_acm_uart;
zephyr,bt-mon-uart = &cdc_acm_uart;
zephyr,bt-c2h-uart = &cdc_acm_uart;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
led1: led_1 {
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
label = "LED 1";
};
led2: led_2 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "LED 2";
};
};
aliases {
led0 = &led1;
led1 = &led2;
mcuboot-led0 = &led1;
watchdog0 = &wdt0;
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00012000>;
};
slot0_partition: partition@12000 {
label = "image-0";
reg = <0x00012000 0x00076000>;
};
slot1_partition: partition@87000 {
label = "image-1";
reg = <0x00088000 0x00074000>;
};
storage_partition: partition@fc000 {
label = "storage";
reg = <0x000fc000 0x00004000>;
};
};
};
®1 {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&ieee802154 {
status = "okay";
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
cdc_acm_uart: cdc_acm_uart {
compatible = "zephyr,cdc-acm-uart";
};
};
``` | /content/code_sandbox/boards/ct/ctcc/ctcc_nrf52840.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 606 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote
# wakeup by default. It needs to be disabled here, because the USB nrfx
# driver always overwrites option from Kconfig mentioned above with the
# imply from CONFIG_USB_NRFX.
CONFIG_USB_DEVICE_REMOTE_WAKEUP=n
``` | /content/code_sandbox/boards/ct/ctcc/ctcc_nrf52840_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```restructuredtext
.. _odroid_go:
ODROID-GO
#########
Overview
********
ODROID-GO Game Kit is a "Do it yourself" ("DIY") portable game console by
HardKernel. It features a custom ESP32-WROVER with 16 MB flash and it operates
from 80 MHz - 240 MHz [1]_.
The features include the following:
- Dual core Xtensa microprocessor (LX6), running at 80 - 240MHz
- 4 MB of PSRAM
- 802.11b/g/n/e/i
- Bluetooth v4.2 BR/EDR and BLE
- 2.4 inch 320x240 TFT LCD
- Speaker
- Micro SD card slot
- Micro USB port (battery charging and USB_UART data communication
- Input Buttons (Menu, Volume, Select, Start, A, B, Direction Pad)
- Expansion port (I2C, GPIO, SPI)
- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES)
.. figure:: img/odroid_go.jpg
:align: center
:alt: ODROID-GO
ODROID-Go Game Kit
External Connector
==================
+-------+------------------+-------------------------+
| PIN # | Signal Name | ESP32-WROVER Functions |
+=======+==================+=========================+
| 1 | GND | GND |
+-------+------------------+-------------------------+
| 2 | VSPI.SCK (IO18) | GPIO18, VSPICLK |
+-------+------------------+-------------------------+
| 3 | IO12 | GPIO12 |
+-------+------------------+-------------------------+
| 4 | IO15 | GPIO15, ADC2_CH3 |
+-------+------------------+-------------------------+
| 5 | IO4 | GPIO4, ADC2_CH0 |
+-------+------------------+-------------------------+
| 6 | P3V3 | 3.3 V |
+-------+------------------+-------------------------+
| 7 | VSPI.MISO (IO19) | GPIO19, VSPIQ |
+-------+------------------+-------------------------+
| 8 | VSPI.MOSI (IO23) | GPIO23, VSPID |
+-------+------------------+-------------------------+
| 9 | N.C | N/A |
+-------+------------------+-------------------------+
| 10 | VBUS | USB VBUS (5V) |
+-------+------------------+-------------------------+
Supported Features
==================
The Zephyr odroid_go board configuration supports the following hardware
features:
+------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+============+============+=====================================+
| UART | on-chip | serial port |
+------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+------------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+------------+------------+-------------------------------------+
| SPI | on-chip | spi |
+------------+------------+-------------------------------------+
System requirements
*******************
Prerequisites
=============
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
*******************
ESP-IDF bootloader
==================
The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
It is build as a subproject at each application build. No further attention
is expected from the user.
MCUboot bootloader
==================
User may choose to use MCUboot bootloader instead. In that case the bootloader
must be build (and flash) at least once.
There are two options to be used when building an application:
1. Sysbuild
2. Manual build
.. note::
User can select the MCUboot bootloader by adding the following line
to the board default configuration file.
.. code:: cfg
CONFIG_BOOTLOADER_MCUBOOT=y
Sysbuild
========
The sysbuild makes possible to build and flash all necessary images needed to
bootstrap the board with the ESP32 SoC.
To build the sample application using sysbuild use the command:
.. zephyr-app-commands::
:tool: west
:app: samples/hello_world
:board: odroid_go
:goals: build
:west-args: --sysbuild
:compact:
By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
images. But it can be configured to create other kind of images.
Build directory structure created by sysbuild is different from traditional
Zephyr build. Output is structured by the domain subdirectories:
.. code-block::
build/
hello_world
zephyr
zephyr.elf
zephyr.bin
mcuboot
zephyr
zephyr.elf
zephyr.bin
domains.yaml
.. note::
With ``--sysbuild`` option the bootloader will be re-build and re-flash
every time the pristine build is used.
For more information about the system build please read the :ref:`sysbuild` documentation.
Manual build
============
During the development cycle, it is intended to build & flash as quickly possible.
For that reason, images can be build one at a time using traditional build.
The instructions following are relevant for both manual build and sysbuild.
The only difference is the structure of the build directory.
.. note::
Remember that bootloader (MCUboot) needs to be flash at least once.
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: odroid_go/esp32/procpu
:goals: build
The usual ``flash`` target will work with the ``odroid_go`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: odroid_go/esp32/procpu
:goals: flash
Open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! odroid_go
Debugging
*********
As with much custom hardware, the ESP32 modules require patches to
OpenOCD that are not upstreamed yet. Espressif maintains their own fork of
the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_
The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the
``-DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>``
parameter when building.
Here is an example for building the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: odroid_go/esp32/procpu
:goals: build flash
:gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: odroid_go/esp32/procpu
:goals: debug
References
**********
.. target-notes::
.. [1] path_to_url
.. _`OpenOCD ESP32`: path_to_url
``` | /content/code_sandbox/boards/hardkernel/odroid_go/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,783 |
```unknown
# CTHINGS.CO Connectivity Card board configuration
config BOARD_SERIAL_BACKEND_CDC_ACM
bool "USB CDC"
default y
depends on BOARD_CTCC_NRF52840
``` | /content/code_sandbox/boards/ct/ctcc/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
# CTHINGS.CO Connectivity Card board configuration
if BOARD_CTCC_NRF52840
if BOARD_SERIAL_BACKEND_CDC_ACM
config USB_DEVICE_STACK
default y
config USB_CDC_ACM
default SERIAL
config CONSOLE
default y
config UART_CONSOLE
default CONSOLE
config USB_DEVICE_INITIALIZE_AT_BOOT
default y if !MCUBOOT && CONSOLE
config USB_DEVICE_REMOTE_WAKEUP
default n
if LOG
# Turn off logging for USB CDC ACM
choice USB_CDC_ACM_LOG_LEVEL_CHOICE
default USB_CDC_ACM_LOG_LEVEL_OFF
endchoice
# Turn off logging for USB Device
choice USB_DEVICE_LOG_LEVEL_CHOICE
default USB_DEVICE_LOG_LEVEL_OFF
endchoice
# Wait 5s at startup for logging
config LOG_PROCESS_THREAD_STARTUP_DELAY_MS
default 5000
endif # LOG
if USB_DEVICE_STACK
config SERIAL
default y
endif # USB_DEVICE_STACK
endif # BOARD_SERIAL_BACKEND_CDC_ACM
config BT_CTLR
default BT
endif # BOARD_CTCC_NRF52840
``` | /content/code_sandbox/boards/ct/ctcc/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```unknown
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=13000000
``` | /content/code_sandbox/boards/mediatek/mt8195_adsp/mt8195_adsp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```unknown
*/
#include <mem.h>
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
sram0: memory@40000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x40000000 DT_SIZE_K(256)>;
};
dram0: memory@60000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x60000000 DT_SIZE_M(17)>;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
cpuclk: cpuclk@10000000 {
compatible = "mediatek,mt8195_cpuclk";
reg = <0x10000000 380>;
cg_reg = <0x10720180>;
pll_ctrl_reg = <0x1000c7e0>;
freqs_mhz = <26 370 540 720>;
};
core_intc: core_intc@0 {
compatible = "cdns,xtensa-core-intc";
reg = <0 4>;
interrupt-controller;
#interrupt-cells = <3>;
};
intc1: intc@10680130 {
compatible = "mediatek,adsp_intc";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x10680130 4>;
status-reg = <0x10680150>;
interrupts = <1 0 0>;
mask = <0x3ffffff0>;
interrupt-parent = <&core_intc>;
};
intc23: intc@108030f4 {
compatible = "mediatek,adsp_intc";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x108030f4 4>;
status-reg = <0x108030fc>;
interrupts = <23 0 0>;
mask = <0xffff>;
interrupt-parent = <&core_intc>;
};
ostimer64: ostimer64@1080d080 {
compatible = "mediatek,ostimer64";
reg = <0x1080d080 28>;
};
ostimer0: ostimer@1080d000 {
compatible = "mediatek,ostimer";
reg = <0x1080d000 16>;
interrupt-parent = <&intc23>;
interrupts = <11 0 0>;
};
mbox0: mbox@10816000 {
compatible = "mediatek,mbox";
reg = <0x10816000 56>;
interrupt-parent = <&intc23>;
interrupts = <0 0 0>;
};
mbox1: mbox@10817000 {
compatible = "mediatek,mbox";
reg = <0x10817000 56>;
interrupt-parent = <&intc23>;
interrupts = <1 0 0>;
};
}; /* soc */
chosen { };
aliases { };
};
``` | /content/code_sandbox/boards/mediatek/mt8195_adsp/mt8195_adsp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 686 |
```unknown
config BOARD_MT8195_ADSP
select SOC_MT8195_ADSP
help
Board with Mediatek MT8195 Audio DSP
``` | /content/code_sandbox/boards/mediatek/mt8195_adsp/Kconfig.mt8195_adsp | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
boards:
- name: mt8195_adsp
vendor: mediatek
socs:
- name: mt8195_adsp
``` | /content/code_sandbox/boards/mediatek/mt8195_adsp/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
if BOARD_MT8195_ADSP
config BOARD
default "mt8195_adsp"
endif # BOARD_MT8195_ADSP
``` | /content/code_sandbox/boards/mediatek/mt8195_adsp/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```restructuredtext
.. _boards-amd:
Advanced Micro Devices (AMD), Inc.
##################################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/amd/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
CONFIG_XIP=n
CONFIG_ISR_STACK_SIZE=512
CONFIG_THREAD_STACK_INFO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable serial port
CONFIG_UART_XLNX_PS=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_ARM_MPU=y
``` | /content/code_sandbox/boards/amd/kv260_r5/kv260_r5_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```cmake
#
``` | /content/code_sandbox/boards/amd/kv260_r5/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2 |
```restructuredtext
.. _ctcc_nrf52840:
CTHINGS.CO Connectivity Card nRF52840
#####################################
Overview
********
The Connectivity Card nRF52840 enables BLE and IEEE 802.15.4 connectivity
over mPCIe or M.2 using USB port with on-board nRF52840 SoC.
This board has following features:
* CLOCK
* FLASH
* :abbr:`GPIO (General Purpose Input Output)`
* :abbr:`MPU (Memory Protection Unit)`
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
* RADIO (Bluetooth Low Energy and 802.15.4)
* :abbr:`RTC (nRF RTC System Clock)`
* :abbr:`USB (Universal Serial Bus)`
* :abbr:`WDT (Watchdog Timer)`
.. figure:: img/ctcc_nrf52840_mpcie.webp
:align: center
:alt: CTCC nRF52840 mPCIe
ctcc/nrf52840 mPCie board
.. figure:: img/ctcc_nrf52840_m2.webp
:align: center
:alt: CTCC nRF52840 M.2
ctcc/nrf52840 M.2 board
More information about the board can be found at the
`ctcc_nrf52840 Website`_ and for SoC information: `Nordic Semiconductor Infocenter`_.
Hardware
********
The ``ctcc/nrf52840`` board target has one external oscillator of the 32.768 kHz.
Supported Features
==================
The ``ctcc/nrf52840`` board target supports the following
hardware features:
+-----------+------------+----------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================+
| CLOCK | on-chip | clock_control |
+-----------+------------+----------------------+
| FLASH | on-chip | flash |
+-----------+------------+----------------------+
| GPIO | on-chip | gpio |
+-----------+------------+----------------------+
| MPU | on-chip | arch/arm |
+-----------+------------+----------------------+
| NVIC | on-chip | arch/arm |
+-----------+------------+----------------------+
| RADIO | on-chip | Bluetooth, |
| | | ieee802154 |
+-----------+------------+----------------------+
| RTC | on-chip | system clock |
+-----------+------------+----------------------+
| USB | on-chip | usb |
+-----------+------------+----------------------+
| WDT | on-chip | watchdog |
+-----------+------------+----------------------+
Connections and IOs
===================
LED
---
Note that board does not have on-board LEDs, however it exposes
LED signals on mPCIe/M.2 pins.
* LED1 = P0.23
* LED2 = P0.22
Programming and Debugging
*************************
Applications for the ``ctcc/nrf52840`` board target can be
built in the usual way (see :ref:`build_an_application` for more details).
Flashing
========
The board supports the following programming options:
1. Using an external :ref:`debug probe <debug-probes>`
2. Using MCUboot with DFU support
Option 1: Using an External Debug Probe
---------------------------------------
Connectivity Card can be programmed using an external debug probe (Segger J-Link) by connecting
to on-board SWD test pads.
For Segger J-Link debug probes, follow the instructions in the
:ref:`nordic_segger` page to install and configure all the necessary
software. Further information can be found in :ref:`nordic_segger_flashing`.
Then build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Here is an example for the :zephyr:code-sample:`usb-cdc-acm-console` application which prints out
logs on emulated USB port.
.. zephyr-app-commands::
:zephyr-app: samples/subsys/usb/console
:board: ctcc/nrf52840
:goals: build flash
Debugging
=========
The ``ctcc/nrf52840`` board target does not have an on-board J-Link debug IC, however
instructions from the :ref:`nordic_segger` page also apply to this board,
with the additional step of connecting an external debugger.
Option 2: Using MCUboot with DFU support
----------------------------------------
It is also possible to use the MCUboot bootloader with DFU support to flash
Zephyr applications. You need to flash MCUboot with DFU support and fill in slot0 with
some application one-time using Option 1. Then you can re-flash an application using DFU utility
by loading images to slot1. Note, it's not possible to have only MCUboot and load directly
software to slot0 due to DFU implementation in Zephyr, which for present slot0 and slot1 in flash
map, it assumes only slot1 partition as writeable.
Install ``dfu-util`` first and make sure MCUboot's ``imgtool`` is
available for signing your binary for MCUboot as described on :ref:`west-sign`.
Next, do the **one-time setup** to flash MCUboot with DFU support.
We'll assume you've cloned the `MCUboot`_ as a submodule when initializing
Zephyr repositories using :ref:`west` tool.
#. Compile MCUboot as a Zephyr application with DFU support.
.. zephyr-app-commands::
:app: mcuboot/boot/zephyr
:board: ctcc/nrf52840
:build-dir: mcuboot
:goals: build
:gen-args: -DCONFIG_BOOT_USB_DFU_WAIT=y
#. Flash it onto the board as described in Option 1.
#. Flash other Zephyr application to fill in slot0 e.g:
.. zephyr-app-commands::
:app: samples/subsys/usb/dfu
:board: ctcc/nrf52840
:build-dir: dfu
:goals: build
:gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\"
You can now flash a Zephyr application to the board using DFU util.
As an example we'll use the :zephyr:code-sample:`usb-cdc-acm-console` sample.
.. zephyr-app-commands::
:zephyr-app: samples/subsys/usb/console
:board: ctcc/nrf52840
:goals: build flash
:gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"path/to/mcuboot/boot/root-rsa-2048.pem\"
.. note::
In all examples it is assumed to use default `root-rsa-2048.pem` file from ``mcuboot/boot``
directory. Providing certificate in build args produces signed binary automatically.
Do not use this certificate in your production firmware!
#. Plug in ``ctcc/nrf52840`` card to mPCIe/M.2 slot or use mPCIe/M.2 adapter to USB
and plug such adapter to USB port.
You should see ``NordicSemiconductor MCUBOOT`` or ``NordicSemiconductor Zephyr DFU sample``
(if you flashed `dfu` sample to slot0) device once plugging it into host
USB port. You can check that on Linux system by entering ``lsusb`` command.
To check if DFU device is visible you can enter ``sudo dfu-util -l`` command. Once the
device is visible you can flash Zephyr image using DFU util: ``sudo dfu-util --alt 1 --download build/zephyr/zephyr.signed.bin``
References
**********
.. target-notes::
.. _ctcc_nrf52840 Website:
path_to_url
.. _Nordic Semiconductor Infocenter:
path_to_url
.. _MCUboot:
path_to_url
``` | /content/code_sandbox/boards/ct/ctcc/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,776 |
```unknown
config BOARD_KV260_R5
select SOC_XILINX_ZYNQMP_RPU
``` | /content/code_sandbox/boards/amd/kv260_r5/Kconfig.kv260_r5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
identifier: kv260_r5
name: Xilinx KV260 Development board for Cortex-R5
arch: arm
toolchain:
- zephyr
ram: 65536
flash: 32768
testing:
ignore_tags:
- net
- bluetooth
vendor: xlnx
``` | /content/code_sandbox/boards/amd/kv260_r5/kv260_r5.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 66 |
```yaml
board:
name: kv260_r5
vendor: amd
socs:
- name: zynqmp_rpu
``` | /content/code_sandbox/boards/amd/kv260_r5/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
/*
*
*
*/
/dts-v1/;
#include <arm/xilinx/zynqmp_rpu.dtsi>
/ {
model = "KV260 Cortex-R5";
compatible = "xlnx,zynqmp-r5";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,ocm = &ocm;
};
};
&uart1 {
status = "okay";
current-speed = <115200>;
clock-frequency = <99999901>;
};
&ttc0 {
status = "okay";
clock-frequency = <5000000>;
};
&psgpio {
status = "okay";
};
``` | /content/code_sandbox/boards/amd/kv260_r5/kv260_r5.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 169 |
```unknown
if BOARD_KV260_R5
config BUILD_OUTPUT_BIN
default y
if USERSPACE
config COMPILER_ISA_THUMB2
default n
endif
endif # BOARD_KV260_R5
``` | /content/code_sandbox/boards/amd/kv260_r5/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```restructuredtext
.. _boards-96boards:
96Boards
########
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/96boards/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/argonkey/96b_argonkey_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
identifier: 96b_argonkey
name: 96Boards Argonkey
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 1024
supported:
- gpio
- i2c
- i2s
- hts221
- lps22hb
- lsm6dsl
- counter
- spi
- vl53l0x
``` | /content/code_sandbox/boards/96boards/argonkey/96b_argonkey.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```yaml
board:
name: 96b_argonkey
vendor: 96boards
socs:
- name: stm32f412cx
``` | /content/code_sandbox/boards/96boards/argonkey/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
config BOARD_96B_ARGONKEY
select SOC_STM32F412CX
``` | /content/code_sandbox/boards/96boards/argonkey/Kconfig.96b_argonkey | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
# 96Boards Argonkey Board Configuration
if BOARD_96B_ARGONKEY
if LSM6DSL
choice LSM6DSL_TRIGGER_MODE
default LSM6DSL_TRIGGER_GLOBAL_THREAD
endchoice
config LSM6DSL_SENSORHUB
default y
choice LSM6DSL_EXTERNAL_SENSOR_0
default LSM6DSL_EXT0_LIS2MDL
endchoice
endif # LSM6DSL
endif # BOARD_96B_ARGONKEY
``` | /content/code_sandbox/boards/96boards/argonkey/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 95 |
```restructuredtext
.. _kv260_r5:
Xilinx KV260 Development Board RPU Cortex-R5
############################################
Overview
********
This configuration provides support for the RPU, real-time processing unit on Xilinx
KV260 development board, it can operate as following:
* Two independent R5 cores with their own TCMs (tightly coupled memories)
* Or as a single dual lock step unit with double the TCM size.
This processing unit is based on an ARM Cortex-R5 CPU, it also enables the following devices:
* ARM PL-390 Generic Interrupt Controller
* Xilinx Zynq TTC (Cadence TTC)
* Xilinx Zynq UART
.. figure:: kv260-starter-kit.jpg
:align: center
:alt: Xilinx KV260 Starter Kit
Hardware
********
Supported Features
==================
The following hardware features are supported:
+--------------+------------+----------------------+
| Interface | Controller | Driver/Component |
+==============+============+======================+
| GIC | on-chip | generic interrupt |
| | | controller |
+--------------+------------+----------------------+
| TTC | on-chip | system timer |
+--------------+------------+----------------------+
| UART | on-chip | serial port |
+--------------+------------+----------------------+
The kernel currently does not support other hardware features on this platform.
Devices
========
System Timer
------------
This board configuration uses a system timer tick frequency of 1000 Hz.
Serial Port
-----------
This board configuration uses a single serial communication channel with the
on-chip UART1.
Memories
--------
Although Flash, DDR and OCM memory regions are defined in the DTS file,
all the code plus data of the application will be loaded in the sram0 region,
which points to the DDR memory. The ocm0 memory area is currently available
for usage, although nothing is placed there by default.
Known Problems or Limitations
==============================
The following platform features are unsupported:
* Dual-redundant Core Lock-step (DCLS) execution is not supported yet.
* Only the first core of the R5 subsystem is supported.
* Xilinx Zynq TTC driver does not support tickless mode operation.
* The Cortex-R5 and the Cortex-A53 shares the same UART controller, more details below.
Programming and Debugging
*************************
Currently the best way to run this sample is by loading it through remoteproc
from the APU, running Linux, to the RPU, assuming the target board has a compatible
Linux kernel.
Users can make use of Xilinx's pre-built Petalinux reference images as a starting point to enable
remoteproc support, it is based around 5.15 Xilinx maintained kernel, as described here:
path_to_url#PetaLinux
The other option is to use the reference image from the openAMP project, the link
below points, betweem the options, to the kv260 target:
path_to_url
Select the option ``xilinx-kv260.tar.gz``, and just decompress it to the target rootfs
partition of user's SD card:
.. code-block:: console
$ sudo mount /dev/<user-sd> /media/rootfs
$ sudo tar -C /media/rootfs -xzf xilinx-kv260.tar.gz
$ sudo umount /media/rootfs
Your SD file may be ready for use, just plug it to the slot located in the board.
After getting the Linux image running on the target board, build a Zephyr application,
such as the hello world sample shown below:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:host-os: unix
:board: kv260_r5
:goals: build
Due to a hardware limitation, both Linux and Zephyr share the same UART
controller, meaning when the Zephyr application is started it will takeover the
console from Linux.
To avoid this limitation when accessing the Linux shell, the best approach is to
connect to the board using ``ssh`` over the network (not using the FTDI
USB interface on the board), with the dev board and the host computer
connected to the same network.
Assuming you are using the default ``petalinux`` user from the Xilinx
reference image , open a terminal on the host machine and ssh into the
development board with the board's IP address (found via ``ifconfig``):
.. code-block:: console
$ ssh petalinux@<board-ip-address>
The initial password should be ``petalinux``. On another terminal deploy
the Zephyr application ``.elf`` file using utility like the ``scp`` or ``rsync``,
for example:
.. code-block:: console
$ scp /path/to/zephyr_app_elf_file petalinux@<board-ip-address>:/home/petalinux
After that move the file to ``/lib/firmware`` directory, then you be able to start the firmware
on the desired RPU via remoteproc with:
.. code-block:: console
$ sudo -i # You need to operate the remoteproc as root
$ echo zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware
$ echo start > /sys/class/remoteproc/remoteproc0/state
With another terminal connected to UART1 on the host machine
(available via one of the tty ports with the on-board FTDI chip),
you should see the Zephyr application running:
.. code-block:: console
*** Booting Zephyr OS build v3.4.0 ***
Hello World kv260_r5!
References
**********
1. ARMv7-A and ARMv7-R Architecture Reference Manual (ARM DDI 0406C ID051414)
2. Cortex-R5 and Cortex-R5F Technical Reference Manual (ARM DDI 0460C ID021511)
3. Zynq UltraScale+ Device Technical Reference Manual (UG1085)
4. Kria KV260 Vision AI Starter Kit User Guide (UG1089)
``` | /content/code_sandbox/boards/amd/kv260_r5/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,296 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f412Xg.dtsi>
#include <st/f4/stm32f412c(e-g)ux-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Tocoding Argonkey 96boards";
compatible = "tocoding,argonkey";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green_led_0: led_0 {
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
label = "USR0 LED";
};
green_led_1: led_1 {
gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
label = "USR1 LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_0;
led1 = &green_led_1;
sw0 = &user_button;
accel0 = &lsm6dsl;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <84>;
div-p = <2>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&plli2s {
div-m = <8>;
mul-n = <192>;
div-r = <3>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
/* APB2 clock is fixed at 42MHz to prevent known SPI/I2S bug */
apb2-prescaler = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&spi1_nss_pa4 { slew-rate = "very-high-speed"; };
&spi1 {
pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2_nss_pb12 { slew-rate = "very-high-speed"; };
&spi2 {
pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
&spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
status = "okay";
/* ST Microelectronics LSM6DSL accel/gyro sensor */
lsm6dsl: lsm6dsl@1 {
compatible = "st,lsm6dsl";
reg = <1>;
spi-max-frequency = <1000000>;
irq-gpios = <&gpiob 1 GPIO_ACTIVE_HIGH>;
};
};
&dma2 {
status = "okay";
};
&i2s5 {
status = "okay";
pinctrl-0 = <&i2s5_ck_pb0 &i2s5_sd_pb8>;
pinctrl-names = "default";
mp34dt05@0 {
compatible = "st,mpxxdtyy";
reg = <0>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
hts221@5f {
compatible = "st,hts221";
reg = <0x5f>;
drdy-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
};
lps22hb-press@5d {
compatible = "st,lps22hb-press";
reg = <0x5d>;
};
vl53l0x@29 {
compatible = "st,vl53l0x";
reg = <0x29>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pb4>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
lp3943@60 {
compatible = "ti,lp3943";
reg = <0x60>;
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/argonkey/96b_argonkey.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,215 |
```cmake
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/96boards/avenger96/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```yaml
identifier: 96b_avenger96
name: 96Boards Avenger96
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- shell
testing:
ignore_tags:
- cmsis_rtos_v2
- net
- mpu
- tinycrypt
- crypto
- aes
- cmm
- LED
- nfc
ram: 256
flash: 64
vendor: 96boards
``` | /content/code_sandbox/boards/96boards/avenger96/96b_avenger96.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 128 |
```unknown
config BOARD_96B_AVENGER96
select SOC_STM32MP15_M4
``` | /content/code_sandbox/boards/96boards/avenger96/Kconfig.96b_avenger96 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
board:
name: 96b_avenger96
vendor: 96boards
socs:
- name: stm32mp157cxx
``` | /content/code_sandbox/boards/96boards/avenger96/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/mp1/stm32mp157.dtsi>
#include <st/mp1/stm32mp157aacx-pinctrl.dtsi>
/ {
model = "Arrow Electronics STM32MP157A Avenger96 board";
compatible = "arrow,stm32mp157a-avenger96";
chosen {
/*
* By default, Zephyr console and shell are assigned to
* remoteproc. To enable console and shell over UART, uncomment
* following lines and set the correct config in
* 96b_avenger96_defconfig. Refer "Serial Port" section in
* Zephyr board documentation.
* zephyr,console = &uart7;
* zephyr,shell-uart = &uart7;
*/
zephyr,flash = &retram;
zephyr,sram = &mcusram;
};
leds {
compatible = "gpio-leds";
green_led_0: led_0 {
gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
label = "USR0 LED";
};
green_led_1: led_1 {
gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
label = "USR1 LED";
};
green_led_2: led_2 {
gpios = <&gpiog 1 GPIO_ACTIVE_HIGH>;
label = "USR2 LED";
};
};
aliases {
led0 = &green_led_0;
led1 = &green_led_1;
led2 = &green_led_2;
};
};
&rcc {
clock-frequency = <DT_FREQ_M(209)>;
};
&mailbox {
status = "okay";
};
&uart4 {
pinctrl-0 = <&uart4_tx_pd1 &uart4_rx_pb2>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart7 {
pinctrl-0 = <&uart7_tx_pe8 &uart7_rx_pe7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/avenger96/96b_avenger96.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 481 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
# console (remote proc console by default)
CONFIG_CONSOLE=y
CONFIG_RAM_CONSOLE=y
CONFIG_RAM_CONSOLE_BUFFER_SIZE=1024
# uart console (overrides remote proc console)
CONFIG_UART_CONSOLE=n
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/avenger96/96b_avenger96_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 108 |
```restructuredtext
.. _96b_argonkey:
96Boards Argonkey
#################
Overview
********
96Boards Argonkey board is based on the ST Microelectronics STM32F412CG
Cortex M4 CPU.
This board acts as a sensor hub platform for all 96Boards compliant
family products. It can also be used as a standalone board.
.. figure:: img/96b_argonkey.jpg
:align: center
:alt: 96Boards Argonkey
96Boards Argonkey
Hardware
********
96Boards Argonkey provides the following hardware components:
- STM32F412CG in UFQFPN48 package
- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
- 100 MHz max CPU frequency
- 1.8V work voltage
- 1024 KB Flash
- 256 KB SRAM
- On board sensors:
- Humidity: STMicro HTS221
- Temperature/Pressure: STMicro LPS22HB
- ALS: Intersil ISL29034
- Proximity: STMicro VL53L0X
- Accelerometer/Gyroscope: STMicro LSM6DSL
- Geomagnetic: STMicro LIS2MDL
- AMR Hall sensor: MRMS501A
- Microphone: STMicro MP34DT05
- 2 User LEDs
- 16 General purpose LEDs
- GPIO with external interrupt capability
- UART
- I2C (3)
- SPI (1)
- I2S (1)
Supported Features
==================
The Zephyr 96b_argonkey board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
More information about the board can be found at the
`ARGONKEY website`_.
The default board configuration can be found in
:zephyr_file:`boards/96boards/argonkey/96b_argonkey_defconfig`
Connections and IOs
===================
LED
---
- LED1 / User1 LED = PB2
- LED2 / User2 LED = PC13
Push buttons
------------
- BUTTON = RST (BT1)
- BUTTON = USR (BT2)
System Clock
============
96Boards Argonkey can be driven by an internal oscillator as well as the main
PLL clock. In default board configuration, the 16MHz external oscillator is
used to drive the main PLL clock to generate a System Clock (SYSCLK) at 84MHz.
On the bus side, AHB clock runs at 84MHz, while APB1/APB2 clock runs at 42MHz.
Serial Port
===========
On 96Boards Argonkey, Zephyr console output is assigned to USART1.
Default settings are 115200 8N1.
I2C
---
96Boards Argonkey board has up to 3 I2Cs. The default I2C mapping is:
- I2C1_SCL : PB6
- I2C1_SDA : PB7
- I2C2_SCL : PB10
- I2C2_SDA : PB9
- I2C3_SCL : PA8
- I2C3_SCL : PB4
I2C3 goes to the P2 connector and can be used to attach external sensors.
It goes to 100Kbit maximum.
SPI
---
96Boards Argonkey board has 2 SPIs. SPI1 is used in slave mode as the communication
bus with the AP. SPI2 is used in master mode to control the LSM6DSL sensor.
The default SPI mapping is:
- SPI1_NSS : PA4
- SPI1_SCK : PA5
- SPI1_MISO : PA6
- SPI1_MOSI : PA7
- SPI2_NSS : PB12
- SPI2_SCK : PB13
- SPI2_MISO : PB14
- SPI2_MOSI : PB15
Programming and Debugging
*************************
Building
========
Here is an example for building the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_argonkey
:goals: build
Flashing
========
96Boards Argonkey can be flashed by two methods, one using the ROM
bootloader and another using the SWD debug port (which requires additional
hardware).
Flashing using the ROM bootloader requires a special activation pattern,
which can be triggered by using the BOOT0 pin. The ROM bootloader supports
flashing via USB (DFU), UART, I2C and SPI, but this document describes the
UART case only. You can read more about how to enable and use the ROM
bootloader by checking the application note `AN2606`_ .
Using ROM bootloader:
---------------------
Hereafter the documents describes basic steps to perform ArgonKey firmware
flashing on a Linux PC using UART as communication channel.
1. Connect ArgonKey UART to your Linux PC using, for example, a USB-TTL serial
cable. The flashing procedure has been tested using a `TTL-232RG`_ cable with
FTDI chip. The UART pins on ArgonKey can be found on the P3 low speed
expansion connector on the back of the board.
- GND (black) to ArgonKey GND (P3.1)
- TXD (orange) to ArgonKey UART0_TXD (P3.5)
- RXD (yellow) to ArgonKey UART0_RXD (P3.7)
When the USB cable is inserted to the Linux PC the following device will be
created: /dev/ttyUSBx (x is usually '0').
2. Force STM32F412CG to enter in Bootloader mode
- Connect BOOT0 to 1V8 (link P2.1 to P3.30)
- Press and release the RST button
3. Use stm32flash utility to flash the ArgonKey:
.. code-block:: console
$ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyUSB0
See References section for more info on `stm32flash`_.
Using SWD debugger:
-------------------
Select a commercial JTAG/SWD h/w tool and connect it to ArgonKey P4 connector.
The ArgonKey has been tested using the `ST-LINK/V2`_ tool. Once that the tool
is connected to the PC through USB, it presents itself as a USB composite
device with mass storage capability. The device can be then mounted in linux
and the f/w can be actually copied there and will be automatically flashed by
the ST-LINK onto the ArgonKey.
Example:
.. code-block:: console
$ mount /dev/sdb /mnt
$ cp zephyr.bin /mnt
$ umount /mnt
Debugging
=========
References
**********
.. target-notes::
.. _ARGONKEY website:
path_to_url
.. _AN2606:
path_to_url
.. _stm32flash:
path_to_url
.. _ST-LINK/V2:
path_to_url
.. _TTL-232RG:
path_to_url
``` | /content/code_sandbox/boards/96boards/argonkey/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,768 |
```cmake
board_runner_args(stm32flash "--baud-rate=115200" "--start-addr=0x08000000")
include(${ZEPHYR_BASE}/boards/common/stm32flash.board.cmake)
``` | /content/code_sandbox/boards/96boards/wistrio/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 46 |
```yaml
identifier: 96b_wistrio
name: 96boards WisTrio
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 16
flash: 128
supported:
- gpio
- i2c
- eeprom
- lora
``` | /content/code_sandbox/boards/96boards/wistrio/96b_wistrio.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/l1/stm32l151Xb-a.dtsi>
#include <st/l1/stm32l151c(6-8-b)uxa-pinctrl.dtsi>
#include "96b_lscon.dtsi"
/ {
model = "RAKWireless 96boards WisTrio board";
compatible = "rak,wistrio";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green_led_0: led_0 {
gpios = <&gpioa 12 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
blue_led_0: led_1 {
gpios = <&gpiob 4 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
};
aliases {
led0 = &green_led_0;
eeprom-0 = &eeprom;
lora0 = &lora;
accel0 = &lis3dh;
};
rf_switch: rf-switch {
compatible = "qorvo,rfsw8001";
rf1-gpios = <&gpioa 4 GPIO_PULL_UP>;
rf2-gpios = <&gpiob 6 GPIO_PULL_UP>;
rf3-gpios = <&gpiob 7 GPIO_PULL_UP>;
};
/* regulator controlling SX oscillator enable */
sx-osc-enable {
compatible = "regulator-fixed";
regulator-name = "sx-osc-enable";
enable-gpios = <&gpioh 1 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll {
div = <2>;
mul = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(32)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
lis3dh: lis3dh@32 {
compatible = "st,lis3dh", "st,lis2dh";
reg = <0x32>;
};
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
lora: lora@0 {
compatible = "semtech,sx1276";
reg = <0>;
reset-gpios = <&gpiob 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
dio-gpios = <&gpioa 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
<&gpiob 1 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
<&gpioa 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
<&gpioh 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
<&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
spi-max-frequency = <1000000>;
power-amplifier-output = "pa-boost";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&eeprom {
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/wistrio/96b_wistrio.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 973 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/wistrio/96b_wistrio_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```yaml
board:
name: 96b_wistrio
vendor: 96boards
socs:
- name: stm32l151xba
``` | /content/code_sandbox/boards/96boards/wistrio/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
config BOARD_96B_WISTRIO
select SOC_STM32L151XBA
``` | /content/code_sandbox/boards/96boards/wistrio/Kconfig.96b_wistrio | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
static int rf_init(void)
{
const struct gpio_dt_spec rf1 =
GPIO_DT_SPEC_GET(DT_NODELABEL(rf_switch), rf1_gpios);
const struct gpio_dt_spec rf2 =
GPIO_DT_SPEC_GET(DT_NODELABEL(rf_switch), rf2_gpios);
const struct gpio_dt_spec rf3 =
GPIO_DT_SPEC_GET(DT_NODELABEL(rf_switch), rf3_gpios);
/* configure RFSW8001 GPIOs (110: RF1/RF2 coexistence mode) */
if (!gpio_is_ready_dt(&rf1) ||
!gpio_is_ready_dt(&rf2) ||
!gpio_is_ready_dt(&rf3)) {
return -ENODEV;
}
(void)gpio_pin_configure_dt(&rf1, GPIO_OUTPUT_HIGH);
(void)gpio_pin_configure_dt(&rf2, GPIO_OUTPUT_HIGH);
(void)gpio_pin_configure_dt(&rf3, GPIO_OUTPUT_LOW);
return 0;
}
/* Need to be initialised after GPIO driver */
SYS_INIT(rf_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
``` | /content/code_sandbox/boards/96boards/wistrio/rf.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 244 |
```unknown
# 96boards WisTrio board configuration
if BOARD_96B_WISTRIO
config REGULATOR
default y if LORA
endif # BOARD_96B_WISTRIO
``` | /content/code_sandbox/boards/96boards/wistrio/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 40 |
```restructuredtext
.. _96b_avenger96:
96Boards Avenger96
##################
Overview
********
96Boards Avenger96 board is based on ST Microelectronics STM32MP157A
multi-core processor, composed of a dual Cortex-A7 and a single Cortex-M4
core. Zephyr OS is ported to run on the Cortex-M4 core.
- Board features:
- PMIC: STPMIC1A
- RAM: 1024 Mbyte @ 533MHz
- Storage:
- eMMC: v4.51: 8 Gbyte
- QSPI: 2Mbyte
- EEPROM: 128 byte
- microSD Socket: UHS-1 v3.01
- Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant
- Wireless:
- WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac
- Bluetooth: v4.2 (BR/EDR/BLE)
- USB:
- Host - 2x type A, 2.0 high-speed
- OTG: - 1x type micro-AB, 2.0 high-speed
- HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4
- Connectors:
- 40-Pin Low Speed Header
- 60-Pin High Speed Header
- LEDs:
- 4x Green user LEDs
- 1x Blue Bluetooth LED
- 1x Yellow WiFi LED
- 1x Red power supply LED
.. image:: img/96b_avenger96.jpg
:align: center
:alt: 96Boards Avenger96
More information about the board can be found at the
`96Boards website`_.
Hardware
********
The STM32MP157A SoC provides the following hardware capabilities:
- Core:
- 32-bit dual-core Arm Cortex-A7
- L1 32-Kbyte I / 32-Kbyte D for each core
- 256-Kbyte unified level 2 cache
- Arm NEON
- 32-bit Arm Cortex-M4 with FPU/MPU
- Up to 209 MHz (Up to 703 CoreMark)
- Memories:
- External DDR memory up to 1 Gbyte.
- 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM +
64 KB of AHB SRAM in backup domain.
- Dual mode Quad-SPI memory interface
- Flexible external memory controller with up to 16-bit data bus
- Clock management:
- Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz
LSI oscillator
- External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator
- 6 PLLs with fractional mode
- General-purpose input/outputs:
- Up to 176 I/O ports with interrupt capability
- Interconnect matrix
- 3 DMA controllers
- Communication peripherals:
- 6 I2C FM+ (1 Mbit/s, SMBus/PMBus)
- 4 UART + 4 USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
- 6 SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
- 4 SAI (stereo audio: I2S, PDM, SPDIF Tx)
- SPDIF Rx with 4 inputs
- HDMI-CEC interface
- MDIO Slave interface
- 3 SDMMC up to 8-bit (SD / eMMC / SDIO)
- 2 CAN controllers supporting CAN FD protocol, TTCAN capability
- 2 USB 2.0 high-speed Host+ 1 USB 2.0 full-speed OTG simultaneously
- 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
- 8- to 14-bit camera interface up to 140 Mbyte/s
- 6 analog peripherals
- 2 ADCs with 16-bit max. resolution.
- 1 temperature sensor
- 2 12-bit D/A converters (1 MHz)
- 1 digital filters for sigma delta modulator (DFSDM) with 8 channels/6
filters
- Internal or external ADC/DAC reference VREF+
- Graphics:
- 3D GPU: Vivante - OpenGL ES 2.0
- LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 768) @60 fps
- MIPI DSI 2 data lanes up to 1 GHz each
- Timers:
- 2 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
(incremental) encoder input
- 2 16-bit advanced motor control timers
- 10 16-bit general-purpose timers (including 2 basic timers without PWM)
- 5 16-bit low-power timers
- RTC with sub-second accuracy and hardware calendar
- 2 4 Cortex-A7 system timers (secure, non-secure, virtual, hypervisor)
- 1 SysTick Cortex-M4 timer
- Hardware acceleration:
- HASH (MD5, SHA-1, SHA224, SHA256), HMAC
- 2 true random number generator (3 oscillators each)
- 2 CRC calculation unit
- Debug mode:
- Arm CoreSight trace and debug: SWD and JTAG interfaces
- 8-Kbyte embedded trace buffer
- 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
More information about STM32P157A can be found here:
- `STM32MP157A on www.st.com`_
- `STM32MP157A reference manual`_
Supported Features
==================
The Zephyr 96b_avenger96 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/96boards/avenger96/96b_avenger96_defconfig`
Connections and IOs
===================
96Boards Avenger96 Board schematic is available here:
`Avenger96 board schematics`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console)
- UART_4 TX/RX : PD1/PB2
System Clock
------------
The Cortex-M4 Core is configured to run at a 209 MHz clock speed. This value
must match the configured mlhclk_ck frequency.
Serial Port
-----------
96Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned
by default to the RAM console to be dumped by the Linux Remoteproc Framework
on Cortex-A7 core. Alternatively, Zephyr console output can be assigned to
UART7 which is disabled by default. UART console can be enabled through
board's devicetree and 96b_avenger96_defconfig board file (or prj.conf
project files), and will disable existing RAM console output. Default UART
console settings are 115200 8N1.
Programming and Debugging
*************************
The STM32MP157A doesn't have QSPI flash for the Cortex-M4 and it needs to be
started by the Cortex-A7 core. The Cortex-A7 core is responsible to load the
Cortex-M4 binary application into the RAM, and get the Cortex-M4 out of reset.
The Cortex-A7 can perform these steps at bootloader level or after the Linux
system has booted.
The Cortex-M4 can use up to 2 different RAMs. The program pointer starts at
address 0x00000000 (RETRAM), the vector table should be loaded at this address
These are the memory mappings for Cortex-A7 and Cortex-M4:
+------------+-----------------------+------------------------+----------------+
| Region | Cortex-A7 | Cortex-M4 | Size |
+============+=======================+========================+================+
| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB |
+------------+-----------------------+------------------------+----------------+
| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB |
+------------+-----------------------+------------------------+----------------+
| DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB |
+------------+-----------------------+------------------------+----------------+
Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction
to load and start the Cortex-M4 firmware.
Debugging
=========
You can debug an application using OpenOCD and GDB. The Solution proposed below
is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux
environment. The firmware must first be loaded by the Cortex-A7. Developer
then attaches the debugger to the running Zephyr using OpenOCD.
Prerequisite
------------
install `stm32mp1 developer package`_.
1) start OpenOCD in a dedicated terminal
- Start up the sdk environment::
source <SDK installation directory>/your_sha256_hash-gnueabi
- Start OpenOCD::
${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg
2) run gdb in Zephyr environment
.. code-block:: console
# On Linux
cd $ZEPHYR_BASE/samples/hello_world
mkdir -p build && cd build
# Use cmake to configure a Ninja-based build system:
cmake -GNinja -DBOARD=96b_avenger96 ..
# Now run ninja on the generated build system:
ninja debug
.. _96Boards website:
path_to_url
.. _STM32MP157A on www.st.com:
path_to_url
.. _STM32MP157A reference manual:
path_to_url
.. _Avenger96 board schematics:
path_to_url
.. _stm32mp1 developer package:
path_to_url#Installing_the_SDK
.. _stm32mp157 boot Cortex-M4 firmware:
path_to_url#How_to_use_the_framework
``` | /content/code_sandbox/boards/96boards/avenger96/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,499 |
```yaml
description: |
Qorvo's RFSW8001 is a single pole triple throw (SP3T) RF switch. The RF1,
RF2 and RF3 pins are used to control the behavior of the switch as detailed
in the "Switch Control Logic Table" in the datasheet.
compatible: "qorvo,rfsw8001"
include: base.yaml
properties:
rf1-gpios:
type: phandle-array
required: true
description: Pin used to control the RF1 switch
rf2-gpios:
type: phandle-array
required: true
description: Pin used to control the RF2 switch
rf3-gpios:
type: phandle-array
required: true
description: Pin used to control the RF3 switch
``` | /content/code_sandbox/boards/96boards/wistrio/dts/bindings/qorvo,rfsw8001.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 175 |
```unknown
/*
*
*/
/ {
lscon_96b: connector {
compatible = "linaro,96b-lscon-3v3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <13 0 &gpioa 8 0>, /* GPIO-A */
<14 0 &gpiob 3 0>, /* GPIO-B */
/* GPIO-C not connected */
<16 0 &gpiob 5 0>, /* GPIO-D */
<17 0 &gpioa 13 0>, /* GPIO-E */
<18 0 &gpioa 14 0>, /* GPIO-F */
<19 0 &gpioa 12 0>, /* GPIO-G */
<20 0 &gpiob 4 0>; /* GPIO-H */
};
};
lscon_96b_i2c0: &i2c1 {};
lscon_96b_uart0: &usart1 {};
``` | /content/code_sandbox/boards/96boards/wistrio/96b_lscon.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 243 |
```unknown
#
#
#
# enable uart driver
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# pinctrl
CONFIG_PINCTRL=y
CONFIG_XIP=y
``` | /content/code_sandbox/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
config BOARD_96B_MEERKAT96
select SOC_PART_NUMBER_MCIMX7D5EVM10SC
select SOC_MCIMX7D_M4 if BOARD_96B_MEERKAT96_MCIMX7D_M4
``` | /content/code_sandbox/boards/96boards/meerkat96/Kconfig.96b_meerkat96 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/dts-v1/;
#include <nxp/nxp_imx7d_m4.dtsi>
#include "96b_meerkat96-pinctrl.dtsi"
/ {
model = "Meerkat96 Board";
compatible = "novtech,imx7d-meerkat96";
chosen {
zephyr,flash = &tcml_code;
zephyr,sram = &tcmu_sys;
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
};
leds {
compatible = "gpio-leds";
green_led_0: led_0 {
gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
label = "User LED1";
};
green_led_1: led_1 {
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
label = "User LED2";
};
green_led_2: led_2 {
gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
label = "User LED3";
};
green_led_3: led_3 {
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
label = "User LED4";
};
};
aliases {
led0 = &green_led_0;
led1 = &green_led_1;
led2 = &green_led_2;
led3 = &green_led_3;
};
};
&uart1 {
status = "okay";
current-speed = <115200>;
modem-mode = <0>;
pinctrl-0 = <&uart1_default>;
pinctrl-names = "default";
};
&gpio1 {
status = "okay";
};
&mub {
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 397 |
```yaml
board:
name: 96b_meerkat96
vendor: 96boards
socs:
- name: mcimx7d
``` | /content/code_sandbox/boards/96boards/meerkat96/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```yaml
#
#
#
identifier: 96b_meerkat96/mcimx7d/m4
name: 96Boards Meerkat96
type: mcu
arch: arm
ram: 32
flash: 32
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- shell
testing:
ignore_tags:
- net
- bluetooth
vendor: novtech
``` | /content/code_sandbox/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
/*
*
*/
#include <nxp/nxp_imx/mimx7d-pinctrl.dtsi>
&pinctrl {
uart1_default: uart1_default {
group0 {
pinmux = <&mx7d_pad_uart1_rx_data__uart1_dte_tx>,
<&mx7d_pad_uart1_tx_data__uart1_dte_rx>;
bias-pull-up-value = "100k";
bias-pull-up;
drive-strength = "x1";
slew-rate = "slow";
input-schmitt-enable;
};
};
};
``` | /content/code_sandbox/boards/96boards/meerkat96/96b_meerkat96-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 131 |
```restructuredtext
.. _96b_wistrio:
96Boards WisTrio
#################
Overview
********
96Boards WisTrio LoRa Tracker board is based on the RAK Wireless RAK5205
chipset integrating SX1276 LoRaWAN Modem, STM32L151CB-A MCU and GPS module.
Zephyr applications use the 96b_wistrio configuration to run on these
boards.
.. figure:: img/96b-wistrio.jpg
:align: center
:alt: 96Boards WisTrio
96Boards WisTrio
This board is one of the `96Boards IoT Edition`_ platforms providing LoRa
connectivity.
Hardware
********
96Boards WisTrio provides the following hardware components:
- RAK5205 Chipset
- 3.3V work voltage
- 128 KB Flash
- 16 KB SRAM
- On board sensors:
- Accelerometer: STMicro LIS3DH
- Integrated Environmental sensor: Bosch BME680
- 2 User LEDs
- GPIO with external interrupt capability
- UART (2)
- I2C (1)
- GPS Module
- GPS Antenna
- LoRa Antenna
Supported Features
==================
The Zephyr 96b_wistrio board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
| EEPROM | on-chip | eeprom |
+-----------+------------+-------------------------------------+
The default board configuration can be found in
:zephyr_file:`boards/96boards/wistrio/96b_wistrio_defconfig`
Connections and IOs
===================
LED
---
- LED1 / User1 LED = PA12
- LED2 / User2 LED = PB4
Push buttons
------------
- BUTTON = RST (BT1)
Serial Port
===========
96Boards WisTrio board has 2 UARTs. Zephyr console output is assigned
to USART1 with 115200 8N1 as the default setting and USART3 is used for
GPS module.
I2C
---
96Boards WisTrio board has 1 I2C connected to on-board sensors.
The default I2C mapping is:
- I2C1_SCL : PB8
- I2C1_SDA : PB9
I2C1 also goes to the J22 connector and can be used to attach external
sensors.
SPI
---
96Boards WisTrio board has 1 SPI connected to on-chip LoRa Radio.
The default SPI mapping is:
- SPI1_SCLK : PA5
- SPI1_MISO : PA6
- SPI1_MOSI : PA7
- SPI1_NSS : PB0
Programming and Debugging
*************************
Flashing
========
96Boards WisTrio can be flashed by two methods, one using the ROM
bootloader and another using the SWD debug port (which requires additional
hardware).
Flashing using the ROM bootloader requires a special activation pattern,
which can be triggered by using the BOOT0 pin. The ROM bootloader supports
flashing via UART, and I2C but this document describes the UART case only.
You can read more about how to enable and use the ROM bootloader by
checking the application note `AN2606`_ .
Using ROM bootloader:
---------------------
1. Connect 96Boards WisTrio to your Linux PC using, USB-Micro to USB-A
cable.
2. ROM bootloader can be triggered by the following pattern:
- Connect BOOT0 to VDD (link pin 1 and 2 on J12)
- Press and release the RST button
More detailed information on activating the ROM bootloader can be found in
Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing
via UART, and I2C protocols.
Here is an example for building and flashing the :ref:`hello_world` application using `stm32flash`_ command line utility:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_wistrio
:goals: build flash
Using SWD debugger:
-------------------
Use the `Black Magic Debug Probe`_ as an SWD programmer, which can
be connected to the SWD pins exposed on the J22 header using its flying
leads and its 20 Pin JTAG Adapter Board Kit. When plugged into your host
PC, the Black Magic Debug Probe enumerates as a USB serial device as
documented on its `Getting started page`_.
It also uses the GDB binary provided with the Zephyr SDK,
``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC
ARM Embedded, can be used as well.
.. code-block:: console
$ arm-zephyr-eabi-gdb -q zephyr.elf
(gdb) target extended-remote /dev/ttyACM0
Remote debugging using /dev/ttyACM0
(gdb) monitor swdp_scan
Target voltage: 3.3V
Available Targets:
No. Att Driver
Debugging
=========
After flashing 96Boards WisTrio, it can be debugged using the same
GDB instance. To reattach, just follow the same steps above, till
"attach 1". You can then debug as usual with GDB. In particular, type
"run" at the GDB prompt to restart the program you've flashed.
References
**********
.. _AN2606:
path_to_url
.. _stm32flash:
path_to_url
.. _Black Magic Debug Probe:
path_to_url
.. _Getting started page:
path_to_url
.. _96Boards IoT Edition:
path_to_url
``` | /content/code_sandbox/boards/96boards/wistrio/doc/96b_wistrio.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,436 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f446Xe.dtsi>
#include <st/f4/stm32f446v(c-e)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics 96Boards STM32 Sensor Mezzanine board";
compatible = "st,stm32f446-b96b-f446ve";
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
red_led_0: led_0 {
gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>;
label = "User LD0";
};
green_led_1: led_1 {
gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led_2: led_2 {
gpios = <&gpiod 12 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "Key";
gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &red_led_0;
led1 = &green_led_1;
led2 = &blue_led_2;
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <84>;
div-p = <2>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&plli2s {
div-m = <8>;
mul-n = <192>;
div-r = <3>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&i2s2 {
status = "okay";
mp34dt01@0 {
compatible = "st,mpxxdtyy";
reg = <0>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
/* ST Microelectronics LIS3MDL magnetic field sensor */
lis3mdl-magn@1e {
compatible = "st,lis3mdl-magn";
reg = <0x1e>;
};
/* ST Microelectronics LPS22HB pressure sensor */
lps22hb-press@5d {
compatible = "st,lps22hb-press";
reg = <0x5d>;
};
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pc12>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&dma1 {
status = "okay";
};
&i2s2 {
pinctrl-0 = <&i2s2_ck_pc7 &i2s2_sd_pc1>;
pinctrl-names = "default";
status = "okay";
};
&spi1_nss_pa4 { slew-rate = "very-high-speed"; };
&spi1 {
pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2_nss_pb9 { slew-rate = "very-high-speed"; };
&spi2 {
pinctrl-0 = <&spi2_nss_pb9 &spi2_sck_pd3
&spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
/* Cannot be used together with i2s2. */
/* status = "okay"; */
};
&spi4_nss_pe11 { slew-rate = "very-high-speed"; };
&spi4 {
pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12
&spi4_miso_pe13 &spi4_mosi_pe14>;
pinctrl-names = "default";
status = "okay";
};
&timers3 {
status = "okay";
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch1_pb4 &tim3_ch3_pc8>;
pinctrl-names = "default";
};
};
&timers4 {
status = "okay";
pwm4: pwm {
status = "okay";
pinctrl-0 = <&tim4_ch3_pd14 &tim4_ch4_pd15>;
pinctrl-names = "default";
};
};
&timers9 {
status = "okay";
pwm9: pwm {
status = "okay";
pinctrl-0 = <&tim9_ch1_pe5 &tim9_ch2_pe6>;
pinctrl-names = "default";
};
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart4 {
pinctrl-0 = <&uart4_tx_pc10 &uart4_rx_pc11>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,478 |
```cmake
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```yaml
identifier: 96b_stm32_sensor_mez
name: 96Boards STM32 Sensor Mezzanine
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- uart
- gpio
- i2c
- spi
- counter
vendor: st
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
config BOARD_96B_STM32_SENSOR_MEZ
select SOC_STM32F446XX
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```yaml
board:
name: 96b_stm32_sensor_mez
vendor: st
socs:
- name: stm32f446xx
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
# 96Boards STM32 Sensor Mezzanine board configuration
if BOARD_96B_STM32_SENSOR_MEZ
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_96B_STM32_SENSOR_MEZ
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
set WORKAREASIZE 0x2000
source [find target/stm32f4x.cfg]
# There is only system reset line and JTAG/SWD command can be issued when SRST
reset_config srst_only
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 122 |
```restructuredtext
.. _96b_meerkat96:
96Boards Meerkat96
##################
Overview
********
96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor,
composed of a dual Cortex-A7 and a single Cortex-M4 core.
Zephyr OS is ported to run on the Cortex-M4 core.
- Board features:
- RAM: 512 Mbyte
- Storage:
- microSD Socket
- Wireless:
- WiFi: 2.4GHz IEEE 802.11b/g/n
- Bluetooth: v4.1 (BR/EDR)
- USB:
- Host - 2x type A
- OTG: - 1x type micro-B
- HDMI
- Connectors:
- 40-Pin Low Speed Header
- 60-Pin High Speed Header
- LEDs:
- 4x Green user LEDs
- 1x Blue Bluetooth LED
- 1x Yellow WiFi LED
.. image:: img/96b_meerkat96.jpg
:align: center
:alt: 96Boards Meerkat96
More information about the board can be found at the
`96Boards website`_.
Hardware
********
The i.MX7 SoC provides the following hardware capabilities:
- Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core
- Memory
- External DDR memory up to 1 Gbyte
- Internal RAM -> A7: 256KB SRAM
- Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR)
- Display
- RGB 1920x1080x24bpp
- 4-wire Resistive touch
- Multimedia
- 1x Camera Parallel Interface
- 1x Analog Audio Line in (Stereo)
- 1x Analog Audio Mic in (Mono)
- 1x Analog Audio Headphone out (Stereo)
- Connectivity
- USB 2.0 OTG (High Speed)
- USB 2.0 host (High Speed)
- 10/100 Mbit/s Ethernet PHY
- 4x I2C
- 4x SPI
- 7x UART
- 1x IrDA
- 20x PWM
- Up to 125 GPIO
- 4x Analog Input (12 Bit)
- 2x SDIO/SD/MMC (8 Bit)
- 2x CAN
More information about the i.MX7 SoC can be found here:
- `i.MX 7 Series Website`_
- `i.MX 7 Dual Datasheet`_
- `i.MX 7 Dual Reference Manual`_
Supported Features
==================
The Zephyr 96b_meerkat96 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig`
Other hardware features are not currently supported by the port.
Connections and IOs
===================
96Boards Meerkat96 board was tested with the following pinmux controller
configuration.
+---------------+-----------------+---------------------------+
| Board Name | SoC Name | Usage |
+===============+=================+===========================+
| UART_1 RXD | UART1_TXD | UART Console |
+---------------+-----------------+---------------------------+
| UART_1 TXD | UART1_RXD | UART Console |
+---------------+-----------------+---------------------------+
| LED_R1 | GPIO1_IO04 | LED0 |
+---------------+-----------------+---------------------------+
| LED_R2 | GPIO1_IO05 | LED1 |
+---------------+-----------------+---------------------------+
| LED_R3 | GPIO1_IO06 | LED2 |
+---------------+-----------------+---------------------------+
| LED_R4 | GPIO1_IO07 | LED3 |
+---------------+-----------------+---------------------------+
System Clock
============
The M4 Core is configured to run at a 200 MHz clock speed.
Serial Port
===========
The iMX7D SoC has seven UARTs. UART_1 is configured for the console and
the remaining are not used/tested.
Programming and Debugging
*************************
The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs
to be started by the A7 core. The A7 core is responsible to load the M4 binary
application into the RAM, put the M4 in reset, set the M4 Program Counter and
Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at
bootloader level or after the Linux system has booted.
The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4:
+------------+-----------------------+------------------------+-----------------------+----------------------+
| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size |
+============+=======================+========================+=======================+======================+
| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB |
+------------+-----------------------+------------------------+-----------------------+----------------------+
For more information about memory mapping see the
`i.MX 7 Dual Reference Manual`_ (section 2.1.2 and 2.1.3), and the
`Toradex Wiki`_.
At compilation time you have to choose which RAM will be used. This
configuration is done in the file :zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts`
with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties.
The available configurations are:
.. code-block:: none
"zephyr,flash"
- &ddr_code
- &tcml_code
- &ocram_code
- &ocram_s_code
- &ocram_pxp_code
- &ocram_epdc_code
"zephyr,sram"
- &ddr_sys
- &tcmu_sys
- &ocram_sys
- &ocram_s_sys
- &ocram_pxp_sys
- &ocram_epdc_sys
Below you will find the instructions to load and run Zephyr on M4 from
A7 using u-boot.
Copy the compiled zephyr.bin to the first FAT partition of the SD card and
plug into the board. Power it up and stop the u-boot execution.
Set the u-boot environment variables and run the zephyr.bin from the
appropriated memory configured in the Zephyr compilation:
.. code-block:: console
setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr'
# TCML
setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000'
setenv bootm4tcml 'run m4tcml && run bootm4'
run bootm4tcml
# TCMU
setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000'
setenv bootm4tcmu 'run m4tcmu && run bootm4'
run bootm4tcmu
# OCRAM
setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000'
setenv bootm4ocram 'run m4ocram && run bootm4'
run bootm4ocram
# OCRAM_S
setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000'
setenv bootm4ocrams 'run m4ocrams && run bootm4'
run bootm4ocrams
# DDR
setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000'
setenv bootm4ddr 'run m4ddr && run bootm4'
run bootm4ddr
Debugging
=========
96Boards Meerkat96 board can be debugged by connecting an external JLink
JTAG debugger to the J4 debug connector. Then download and install
`J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_.
To run Zephyr Binary using J-Link create the following script in order to
get the Program Counter and Stack Pointer from zephyr.bin.
get-pc-sp.sh:
.. code-block:: console
#!/bin/sh
firmware=$1
pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}')
sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}')
echo pc=$pc
echo sp=$sp
Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin``
.. code-block:: console
pc=00900f01
sp=00905020
Plug in the J-Link into the board and PC and run the J-Link command line tool:
.. code-block:: console
/usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript
The following steps are necessary to run the zephyr.bin:
1. Put the M4 core in reset
2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR)
3. Set PC (Program Counter)
4. Set SP (Stack Pointer)
5. Get the M4 core out of reset
Issue the following commands inside J-Link commander:
.. code-block:: console
w4 0x3039000C 0xAC
loadfile zephyr.bin,0x00900000
w4 0x00180000 00900f01
w4 0x00180004 00905020
w4 0x3039000C 0xAA
With these mechanisms, applications for the ``96b_meerkat96`` board
configuration can be built and debugged in the usual way (see
:ref:`build_an_application` and :ref:`application_run` for more details).
References
==========
- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_
- `J-Link iMX7D Instructions`_
.. _96Boards website:
path_to_url
.. _i.MX 7 Series Website:
path_to_url
.. _i.MX 7 Dual Datasheet:
path_to_url
.. _i.MX 7 Dual Reference Manual:
path_to_url
.. _J-Link Tools:
path_to_url#J-LinkSoftwareAndDocumentationPack
.. _NXP iMX7D Connect CortexM4.JLinkScript:
path_to_url
.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors:
path_to_url
.. _J-Link iMX7D Instructions:
path_to_url
.. _Toradex Wiki:
path_to_url#Memory_areas
``` | /content/code_sandbox/boards/96boards/meerkat96/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,080 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/aerocore2/96b_aerocore2_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```cmake
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
``` | /content/code_sandbox/boards/96boards/aerocore2/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```yaml
identifier: 96b_aerocore2
name: 96Boards AeroCore 2
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- pwm
- i2c
- spi
- usb_device
- adc
ram: 256
flash: 2048
vendor: 96boards
``` | /content/code_sandbox/boards/96boards/aerocore2/96b_aerocore2.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 100 |
```restructuredtext
.. _96b_stm32_sensor_mez:
96Boards STM32 Sensor Mezzanine
###############################
Overview
********
96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics
STM32F446VE Cortex M4 CPU.
This board acts as a mezzanine platform for all 96Boards CE compliant
boards. It can also be used as a standalone board.
.. figure:: img/96b_stm32_sensor_mez.jpg
:align: center
:alt: 96Boards STM32 Sensor Mezzanine
96Boards STM32 Sensor Mezzanine
Hardware
********
96Boards STM32 Sensor Mezzanine provides the following hardware components:
- STM32F446VE in LQFP100 package
- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
- 180 MHz max CPU frequency
- 1.8V work voltage
- 512 KB Flash
- 128 KB SRAM
- On board sensors:
- Temperature/Pressure: STMicro LPS22HB
- Accelerometer/Gyroscope: STMicro LSM6DS3H
- Magnetometer: STMicro LIS3MDL
- Microphone: STMicro MP34DT01
- 3User LEDs
- GPIO with external interrupt capability
- UART
- I2C (2)
- SPI (3)
- I2S (1)
Supported Features
==================
The Zephyr 96b_stm32_sensor_mez board configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | system clock |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| I2S | on-chip | i2s |
+-----------+------------+-------------------------------------+
The default board configuration can be found in
:zephyr_file:`boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig`
Connections and IOs
===================
LED
---
- LED1 / User1 LED = PD10
- LED2 / User2 LED = PD11
- LED3 / User3 LED = PD12
Push buttons
------------
- BUTTON = RST (BT1)
- BUTTON = USR (BT2)
System Clock
============
96Boards STM32 Sensor Mezzanine can be driven by an internal oscillator as
well as the main PLL clock. In default board configuration, the 16MHz external
oscillator is used to drive the main PLL clock to generate a System Clock
(SYSCLK) at 84MHz. On the bus side, AHB/APB2 clocks runs at 84MHz, while APB1
clock runs at 42MHz.
Serial Port
===========
On 96Boards STM32 Sensor Mezzanine, Zephyr console output is assigned to UART4
exposed via on-board Micro USB connector. Default settings are 115200 8N1.
The default USART mappings for the remaining ones are:
- USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header.
- TX: PA9
- RX: PA10
- USART2: Connected to D0(RX) and D1(TX) on the Arduino Header.
- TX: PD5
- RX: PD6
- USART3: Broken out to Grove connector J10.
- TX: PD8
- RX: PD9
I2C
---
96Boards STM32 Sensor Mezzanine board has up to 3 I2Cs. The default I2C
mapping is:
- I2C1_SCL : PB6
- I2C1_SDA : PB7
- I2C2_SCL : PB10
- I2C2_SDA : PC12
I2C2 goes to the Groove connectors and can be used to attach external sensors.
SPI
---
96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode
as the communication bus with the AP. SPI2 is used in master mode to control
the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5.
The default SPI mapping is:
- SPI1_NSS : PA4
- SPI1_SCK : PA5
- SPI1_MISO : PA6
- SPI1_MOSI : PA7
- SPI2_NSS : PB9
- SPI2_SCK : PD3
- SPI2_MISO : PB14
- SPI2_MOSI : PB15
- SPI4_NSS : PE11
- SPI4_SCK : PE12
- SPI4_MISO : PE13
- SPI4_MOSI : PE14
PWM
---
96Boards STM32 Sensor Mezzanine board exposes 6 PWM channels on the Arduino
connector. The default PWM mapping is:
- PWM3_CH1 : PB4 : D9
- PWM3_CH3 : PC8 : D3
- PWM4_CH3 : PD14 : D6
- PWM4_CH4 : PD15 : D5
- PWM9_CH1 : PE5 : D12
- PWM9_CH2 : PE6 : D11
I2S
---
96Boards STM32 Sensor Mezzanine board exposes 1 I2S port which is connected
to the on-board ST MP34DT01 DMIC. The default I2S mapping is:
- I2S2_SD : PC1
- I2S2_CK : PC7
Programming and Debugging
*************************
Building
========
Here is an example for building the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_stm32_sensor_mez
:goals: build
Flashing
========
96Boards STM32 Sensor Mezzanine board includes an ST-LINK/V2-1 embedded
debug tool interface. This interface is supported by the openocd version
included in the Zephyr SDK.
Flashing an application to 96Boards STM32 Sensor Mezzanine
----------------------------------------------------------
Here is an example for the :ref:`hello_world` application.
Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine
board.
.. code-block:: console
$ minicom -b 115200 -D /dev/ttyACM0
Build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_stm32_sensor_mez
:goals: build flash
You should see the following message on the console:
.. code-block:: console
$ Hello World! 96b_stm32_sensor_mez
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_stm32_sensor_mez
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _96Boards STM32 Sensor Mezzanine website:
path_to_url
.. _STM32F446VE on www.st.com:
path_to_url
.. _STM32F446 reference manual:
path_to_url
``` | /content/code_sandbox/boards/96boards/stm32_sensor_mez/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,802 |
```yaml
board:
name: 96b_aerocore2
vendor: 96boards
socs:
- name: stm32f427xx
``` | /content/code_sandbox/boards/96boards/aerocore2/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
config BOARD_96B_AEROCORE2
select SOC_STM32F427XX
``` | /content/code_sandbox/boards/96boards/aerocore2/Kconfig.96b_aerocore2 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f427vi.dtsi>
#include <st/f4/stm32f427v(g-i)tx-pinctrl.dtsi>
/ {
model = "96Boards Gumstix AeroCore 2";
compatible = "gumstix,aerocore2";
chosen {
zephyr,console = &uart7;
zephyr,shell-uart = &uart7;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,ccm = &ccm0;
};
leds {
compatible = "gpio-leds";
yellow_led_1: led_1 {
gpios = <&gpioe 10 GPIO_ACTIVE_HIGH>;
label = "USR1 LED";
};
blue_led_2: led_2 {
gpios = <&gpioe 9 GPIO_ACTIVE_HIGH>;
label = "USR2 LED";
};
};
aliases {
led0 = &yellow_led_1;
led1 = &blue_led_2;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
};
&pll {
div-m = <24>;
mul-n = <336>;
div-p = <2>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(168)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart7 {
pinctrl-0 = <&uart7_tx_pe8 &uart7_rx_pe7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart8 {
pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&spi1_nss_pa4 { slew-rate = "very-high-speed"; };
&spi1 {
pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2_nss_pb12 { slew-rate = "very-high-speed"; };
&spi2 {
pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
&spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
status = "okay";
};
&spi3 {
pinctrl-0 = <&spi3_sck_pc10 &spi3_miso_pc11 &spi3_mosi_pc12>;
pinctrl-names = "default";
status = "okay";
};
&spi4_nss_pe11 { slew-rate = "very-high-speed"; };
&spi4 {
pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12
&spi4_miso_pe13 &spi4_mosi_pe14>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&timers4 {
status = "okay";
pwm4: pwm {
status = "okay";
pinctrl-0 = <&tim4_ch1_pd12
&tim4_ch2_pd13
&tim4_ch3_pd14
&tim4_ch4_pd15>;
pinctrl-names = "default";
};
};
&timers5 {
status = "okay";
pwm5: pwm {
status = "okay";
pinctrl-0 = <&tim5_ch1_pa0
&tim5_ch2_pa1
&tim5_ch3_pa2
&tim5_ch4_pa3>;
pinctrl-names = "default";
};
};
&adc1 {
pinctrl-0 = <&adc1_in10_pc0 &adc1_in11_pc1
&adc1_in12_pc2 &adc1_in13_pc3>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&rng {
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/aerocore2/96b_aerocore2.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,314 |
```cmake
board_runner_args(pyocd "--target=nrf52832")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/96boards/nitrogen/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# enable GPIO
CONFIG_GPIO=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/96boards/nitrogen/96b_nitrogen_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```yaml
identifier: 96b_nitrogen
name: 96Boards Nitrogen
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- ble
- gpio
- i2c
- spi
ram: 64
flash: 512
vendor: seeed
``` | /content/code_sandbox/boards/96boards/nitrogen/96b_nitrogen.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "96b_lscon.dtsi"
#include "96b_nitrogen-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Seeed Studio Nitrogen 96board";
compatible = "seeed,nitrogen";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &led0;
led1 = &led1;
bt = &led1;
sw0 = &button0;
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
/* green led */
led0: led_0 {
gpios = <&gpio0 29 0>;
label = "USR1 LED";
};
/* blue led */
led1: led_1 {
gpios = <&gpio0 28 0>;
label = "BT LED";
};
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
/* gpio flags need validation */
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
label = "User Push Button";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&uart0 {
compatible = "nordic,nrf-uart";
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
&spi1 {
compatible = "nordic,nrf-spi";
status = "okay";
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xa000>;
};
slot0_partition: partition@a000 {
label = "image-0";
reg = <0x0000a000 0x33000>;
};
slot1_partition: partition@3d000 {
label = "image-1";
reg = <0x0003d000 0x33000>;
};
scratch_partition: partition@70000 {
label = "image-scratch";
reg = <0x00070000 0xa000>;
};
/*
* The flash starting at 0x0007a000 and ending at
* 0x0007ffff (sectors 122-127) is reserved for use
* by the application. If enabled, partition for FCB/LittleFS
* will be created in this area.
*/
storage_partition: partition@7a000 {
label = "storage";
reg = <0x0007a000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/96boards/nitrogen/96b_nitrogen.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 908 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/96boards/nitrogen/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 13)>,
<NRF_PSEL(UART_RX, 0, 15)>,
<NRF_PSEL(UART_RTS, 0, 12)>,
<NRF_PSEL(UART_CTS, 0, 14)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 13)>,
<NRF_PSEL(UART_RX, 0, 15)>,
<NRF_PSEL(UART_RTS, 0, 12)>,
<NRF_PSEL(UART_CTS, 0, 14)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 20)>,
<NRF_PSEL(TWIM_SCL, 0, 22)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 20)>,
<NRF_PSEL(TWIM_SCL, 0, 22)>;
low-power-enable;
};
};
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 26)>,
<NRF_PSEL(SPIM_MOSI, 0, 23)>,
<NRF_PSEL(SPIM_MISO, 0, 25)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 26)>,
<NRF_PSEL(SPIM_MOSI, 0, 23)>,
<NRF_PSEL(SPIM_MISO, 0, 25)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/96boards/nitrogen/96b_nitrogen-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 482 |
```yaml
board:
name: 96b_nitrogen
vendor: 96boards
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/96boards/nitrogen/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# 96Boards NITROGEN board configuration
if BOARD_96B_NITROGEN
config BT_CTLR
default BT
endif # BOARD_96B_NITROGEN
``` | /content/code_sandbox/boards/96boards/nitrogen/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 42 |
```unknown
/*
*
*/
/ {
lscon_96b: connector {
compatible = "linaro,96b-lscon-1v8";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <23 0 &gpio0 2 0>, /* GPIO-A */
<24 0 &gpio0 3 0>, /* GPIO-B */
<25 0 &gpio0 4 0>, /* GPIO-C */
<26 0 &gpio0 5 0>, /* GPIO-D */
<27 0 &gpio0 6 0>, /* GPIO-E */
<28 0 &gpio0 7 0>, /* GPIO-F */
<29 0 &gpio0 8 0>, /* GPIO-G */
<30 0 &gpio0 11 0>, /* GPIO-H */
<31 0 &gpio0 16 0>, /* GPIO-I */
<32 0 &gpio0 17 0>, /* GPIO-J */
<33 0 &gpio0 18 0>, /* GPIO-K */
<34 0 &gpio0 19 0>; /* GPIO-L */
};
};
lscon_96b_spi0: &spi1 {};
lscon_96b_uart0: &uart0 {};
``` | /content/code_sandbox/boards/96boards/nitrogen/96b_lscon.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 318 |
```unknown
# 96Boards NITROGEN board configuration
config BOARD_96B_NITROGEN
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/96boards/nitrogen/Kconfig.96b_nitrogen | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```restructuredtext
.. _96b_aerocore2_board:
96Boards Aerocore2
##################
Overview
********
The 96Boards Aerocore2 Mezzanine is based on the STMicroelectronics
STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones.
This board acts as a mezzanine platform for all 96Boards CE compliant
boards. It can also be used as a standalone board.
.. figure:: img/96b_aerocore2.jpg
:align: center
:alt: 96Boards Aerocore2
96Boards Aerocore2
Hardware
********
96Boards Aerocore2 provides the following hardware components:
- STM32F427VIT6 in LQFP100 package
- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
- 168 MHz max CPU frequency
- VDD from 1.7 V to 3.6 V
- 2048 KB Flash
- 256 KB SRAM
- GPIO with external interrupt capability
- 12-bit ADC with 16 channels
- RTC
- Advanced-control Timers (2)
- General Purpose Timers (10)
- Watchdog Timers (2)
- USART/UART (4)
- I2C (3)
- SPI (3)
- SDIO
- USB 2.0 OTG FS
- DMA Controller
More information about STM32F427VIT6 can be found here:
- `STM32F427 on www.st.com`_
Supported Features
==================
The Zephyr 96b_aerocore2 board configuration supports the following hardware
features:
+------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+============+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+------------+------------+-------------------------------------+
| SYSTICK | on-chip | system clock |
+------------+------------+-------------------------------------+
| UART | on-chip | serial port |
+------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+------------+------------+-------------------------------------+
| FLASH | on-chip | flash |
+------------+------------+-------------------------------------+
| SPI | on-chip | spi |
+------------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+------------+------------+-------------------------------------+
| PWM | on-chip | timers / pwm |
+------------+------------+-------------------------------------+
| USB OTG FS | on-chip | USB device |
+------------+------------+-------------------------------------+
| ADC | on-chip | adc |
+------------+------------+-------------------------------------+
More details about the board can be found at `96Boards website`_.
The default configuration can be found in
:zephyr_file:`boards/96boards/aerocore2/96b_aerocore2_defconfig`
Connections and IOs
===================
LED
---
- LED1 / User1 LED = PE10
- LED2 / User2 LED = PE9
External Connectors
-------------------
Octal PWM Header (J1)
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | Pin # | Signal Name |
+=======+=============+=========================+=======+=============+=======+=============+
| 1 | PWM4_CH1 | PD12 | 2 | 5.0v | 3 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 4 | PWM4_CH2 | PD13 | 5 | 5.0v | 6 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 7 | PWM4_CH3 | PD14 | 8 | 5.0v | 9 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 10 | PWM4_CH4 | PD15 | 11 | 5.0v | 12 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 13 | PWM5_CH1 | PA0 | 14 | 5.0v | 15 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 16 | PWM5_CH2 | PA1 | 17 | 5.0v | 18 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 19 | PWM5_CH3 | PA2 | 20 | 5.0v | 21 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
| 22 | PWM5_CH4 | PA3 | 23 | 5.0v | 24 | GND |
+-------+-------------+-------------------------+-------+-------------+-------+-------------+
IO Header J11
+-------+-------------+-------+-------------+
| PIN # | Signal Name | PIN # | Signal Name |
+=======+=============+=======+=============+
| 1 | PB9 | 2 | PB8* |
+-------+-------------+-------+-------------+
| 3 | PC9 | 4 | PB0 |
+-------+-------------+-------+-------------+
| 5 | PE5 | 6 | NA |
+-------+-------------+-------+-------------+
| 7 | PE6 | 8 | NA |
+-------+-------------+-------+-------------+
| 9 | PC6 | 10 | NA |
+-------+-------------+-------+-------------+
| 11 | PC7 | 12 | NA |
+-------+-------------+-------+-------------+
| 13 | PC8 | 14 | NA |
+-------+-------------+-------+-------------+
| 15 | PA8 | 16 | GND |
+-------+-------------+-------+-------------+
| 17 | PA9 | 18 | 3v3 |
+-------+-------------+-------+-------------+
| 19 | PA10 | 20 | GND |
+-------+-------------+-------+-------------+
* PB8 is connected to a watchdog buzzer, It needs to be pulsed every 10 seconds to keep the buzzer silent.
IO Header J5
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | STM32F427 Functions Pin |
+=======+=============+=========================+=======+=============+=========================+
| 1 | AGND | AGND | 2 | ADC1_13 | PC3 |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 3 | ADC1_12 | PC2 | 4 | ADC1_11 | PC1 |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 5 | I2C_SDA | PB11 | 6 | GND | GND |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 7 | I2C_SCL | PB10 | 8 | VCC 3v3 | VCC 3v3 |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 9 | NC | NC | 10 | NC | NC |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 11 | NC | NC | 12 | NC | NC |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 13 | UART_TX 7 | PE8 | 14 | GND | GND |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 15 | UART_RX 7 | PE7 | 16 | GND | GND |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 17 | UART_TX 2 | PD5 | 18 | GND | GND |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 19 | UART_TX 2 | PD6 | 20 | GND | GND |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 21 | NC | NC | 10 | NC | NC |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 23 | NC | NC | 10 | NC | NC |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 25 | SPI1_NIRQ | PC5 | 26 | GND | GND |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 27 | SPI1_CLK | PA5 | 28 | SPI1_MISO | PA6 |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 29 | SPI1_CS0 | PA4 | 30 | SPI1_MOSI | PA7 |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 31 | CAN_TX | PD1 | 32 | CANH | NC |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
| 33 | CAN_RX | PD0 | 34 | CANL | NC |
+-------+-------------+-------------------------+-------+-------------+-------------------------+
GPS connector J15
+-------+-------------+-------------------------+
| PIN # | Signal Name | STM32F427 Functions Pin |
+=======+=============+=========================+
| 1 | V_OUT 5v | NC |
+-------+-------------+-------------------------+
| 2 | UART1_TX | PB6 |
+-------+-------------+-------------------------+
| 3 | UART1_RX | PB7 |
+-------+-------------+-------------------------+
| 4 | VCC 3v3 | NC |
+-------+-------------+-------------------------+
| 5 | GND | GND |
+-------+-------------+-------------------------+
Spektrum connector J3
+-------+-------------+-------------------------+
| PIN # | Signal Name | STM32F427 Functions Pin |
+=======+=============+=========================+
| 1 | VCC 3v3 | NC |
+-------+-------------+-------------------------+
| 2 | GND | GND |
+-------+-------------+-------------------------+
| 3 | UART8_RX | PE0 |
+-------+-------------+-------------------------+
External Clock Sources
----------------------
STM32F4 has one external oscillator. The frequency of the clock is
32.768 kHz. The internal 16MHz clock is used as the main clock.
Serial Port
-----------
96Boards Aerocore2 board has up to 4 U(S)ARTs. The Zephyr console output is
assigned to USART7. Default settings are 115200 8N1.
I2C
---
96Boards Aerocore2 board has 1 I2C port. The default I2C mapping for Zephyr is:
- I2C1_SCL : PB10
- I2C1_SDA : PB11
SPI
---
96Boards Aerocore2 board has 1 SPI port. The default SPI mapping for Zephyr is:
- SPI1_CS0 : PA4
- SPI1_SCK : PA5
- SPI1_MISO : PA6
- SPI1_MOSI : PA7
USB
===
96Boards Aerocore2 board has a USB OTG dual-role device (DRD) controller that
supports both device and host functions through its mini "OTG" USB connector.
Only USB device functions are supported in Zephyr at the moment.
Programming and Debugging
*************************
There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
bootloader, and another by using the SWD debug port (which requires additional
hardware). Flashing using the ROM bootloader requires a special activation
pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader
supports flashing via USB (DFU), UART, I2C and SPI. You can read more about
how to enable and use the ROM bootloader by checking the application
note `AN2606`_, page 109.
Flashing
========
Installing dfu-util
-------------------
It is recommended to use at least v0.8 of `dfu-util`_. The package available in
debian/ubuntu can be quite old, so you might have to build dfu-util from source.
Flashing an Application to 96Boards Aerocore2
---------------------------------------------
Connect the micro-USB cable to the USB OTG/STM_CONSOLE Aerocore2 port and to your computer.
The board should power ON. Force the board into DFU mode by keeping the BOOT0
switch pressed while pressing and releasing the RST switch.
The BOOT button is located at the back-side of the PCB.
Confirm that the board is in DFU mode:
.. code-block:: console
$ sudo dfu-util -l
dfu-util 0.8
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to dfu-util@lists.gnumonks.org
Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034"
Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034"
Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034"
Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034"
Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN"
You should see following confirmation on your Linux host:
.. code-block:: console
$ dmesg
usb 1-2.1: new full-speed USB device number 14 using xhci_hcd
usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11
usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 1-2.1: Product: STM32 BOOTLOADER
usb 1-2.1: Manufacturer: STMicroelectronics
usb 1-2.1: SerialNumber: 3574364C3034
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_aerocore2
:goals: build flash
Connect a USB-TTL dongle to the UART_7 header port and to your computer.
Run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the board 96Boards Aerocore2
can be found. For example, under Linux, :code:`/dev/ttyUSB0`.
The ``-b`` option sets baud rate ignoring the value from config.
Press the Reset button and you should see the following message in your
terminal:
.. code-block:: console
Hello World! arm
.. _96Boards website:
path_to_url
.. _STM32F427 on www.st.com:
path_to_url
.. _dfu-util:
path_to_url
.. _AN2606:
path_to_url
``` | /content/code_sandbox/boards/96boards/aerocore2/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 3,805 |
```unknown
config BOARD_96B_NEONKEY
select SOC_STM32F411XE
``` | /content/code_sandbox/boards/96boards/neonkey/Kconfig.96b_neonkey | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/neonkey/96b_neonkey_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
identifier: 96b_neonkey
name: 96Boards Neonkey
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 128
flash: 512
supported:
- gpio
- i2c
- spi
- counter
``` | /content/code_sandbox/boards/96boards/neonkey/96b_neonkey.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```yaml
board:
name: 96b_neonkey
vendor: 96boards
socs:
- name: stm32f411xe
``` | /content/code_sandbox/boards/96boards/neonkey/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f411Xe.dtsi>
#include <st/f4/stm32f411c(c-e)ux-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Tocoding Neonkey 96boards";
compatible = "tocoding,neonkey";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green_led_0: led_0 {
gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>;
label = "USR0 LED";
};
green_led_1: led_1 {
gpios = <&gpiob 13 GPIO_ACTIVE_HIGH>;
label = "USR1 LED";
};
green_led_2: led_2 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "USR2 LED";
};
green_led_3: led_3 {
gpios = <&gpiob 15 GPIO_ACTIVE_HIGH>;
label = "USR3 LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
label = "User";
gpios = <&gpiob 2 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_0;
led1 = &green_led_1;
led2 = &green_led_2;
led3 = &green_led_3;
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <16>;
mul-n = <336>;
div-p = <4>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb3>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pa8 &i2c3_sda_pb4>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
lp3943@60 {
compatible = "ti,lp3943";
reg = <0x60>;
};
};
&spi1 {
pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
``` | /content/code_sandbox/boards/96boards/neonkey/96b_neonkey.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 876 |
```unknown
# 96Boards Neonkey Board Configuration
if BOARD_96B_NEONKEY
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_96B_NEONKEY
``` | /content/code_sandbox/boards/96boards/neonkey/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 45 |
```restructuredtext
.. _96b_nitrogen_board:
96Boards Nitrogen
#################
Overview
********
The 96Boards Nitrogen hardware provides support for the Nordic Semiconductor
nRF52832 ARM Cortex-M4F CPU.
.. figure:: img/96b_nitrogen.jpg
:align: center
:alt: 96Boards Nitrogen
96Boards Nitrogen
More information about the board can be found at the `seeed BLE Nitrogen`_
website. The `Nordic Semiconductor Infocenter`_ contains the processor's
information and the datasheet.
Hardware
********
96Boards Nitrogen provides the following hardware components:
- nRF52832 microcontroller with 512kB Flash, 64kB RAM
- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
- Bluetooth LE
- NFC
- LPC11U35 on board SWD debugger
- SWD debugger firmware
- USB to UART
- Drag and Drop firmware upgrade
- 7 LEDs
- USR1, BT, PWR, CDC, DAP, MSD, Battery charge
- SWD debug connectors
- nRF52832 SWD connector
- nRF52832 Uart connector
- On board chip antenna
- 1.8V work voltage
- 2x20pin 2.0mm pitch Low speed connector
Supported Features
==================
The Zephyr 96b_nitrogen board configuration supports the following hardware
features:
+-----------+------------+--------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+======================================+
| NVIC | on-chip | nested vectored interrupt controller |
+-----------+------------+--------------------------------------+
| RTC | on-chip | system clock |
+-----------+------------+--------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+--------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+--------------------------------------+
| FLASH | on-chip | flash |
+-----------+------------+--------------------------------------+
| RADIO | on-chip | Bluetooth |
+-----------+------------+--------------------------------------+
| RTT | on-chip | console |
+-----------+------------+--------------------------------------+
Other hardware features have not been enabled yet for this board.
See `Nordic Semiconductor Infocenter`_ for a complete list of nRF52-based
board hardware features.
The default configuration can be found in
:zephyr_file:`boards/96boards/nitrogen/96b_nitrogen_defconfig`
Pin Mapping
===========
LED
---
- LED1 / User LED (green) = P0.29
- LED2 / BT LED (blue) = P0.28
Push buttons
------------
- BUTTON = SW1 = P0.27
External Connectors
-------------------
Low Speed Header
+--------+-------------+----------------------+
| PIN # | Signal Name | nRF52832 Functions |
+========+=============+======================+
| 1 | GND | GND |
+--------+-------------+----------------------+
| 3 | UART CTS | P.014 / TRACEDATA[3] |
+--------+-------------+----------------------+
| 5 | UART TX | P0.13 |
+--------+-------------+----------------------+
| 7 | UART RX | P0.15 / TRACEDATA[2] |
+--------+-------------+----------------------+
| 9 | UART RTS | P0.12 |
+--------+-------------+----------------------+
| 11 | UART TX | P0.13 |
+--------+-------------+----------------------+
| 13 | UART RX | P0.15 / TRACEDATA[2] |
+--------+-------------+----------------------+
| 15 | P0.22 | P0.22 |
+--------+-------------+----------------------+
| 17 | P0.20 | P0.20 |
+--------+-------------+----------------------+
| 19 | N/A | N/A |
+--------+-------------+----------------------+
| 21 | N/A | N/A |
+--------+-------------+----------------------+
| 23 | P0.02 | P0.02 |
+--------+-------------+----------------------+
| 25 | P0.04 | P0.04 |
+--------+-------------+----------------------+
| 27 | P0.06 | P0.06 |
+--------+-------------+----------------------+
| 29 | P0.08 | P0.08 |
+--------+-------------+----------------------+
| 31 | P0.16 | P0.16 |
+--------+-------------+----------------------+
| 33 | P0.18 | P0.18 |
+--------+-------------+----------------------+
| 35 | VCC | |
+--------+-------------+----------------------+
| 37 | USB5V | |
+--------+-------------+----------------------+
| 39 | GND | GND |
+--------+-------------+----------------------+
+--------+-------------+----------------------+
| PIN # | Signal Name | nRF52832 Functions |
+========+=============+======================+
| 2 | GND | GND |
+--------+-------------+----------------------+
| 4 | PWR BTN | |
+--------+-------------+----------------------+
| 6 | RST BTN | P0.21 / RESET |
+--------+-------------+----------------------+
| 8 | P0.26 | P0.26 |
+--------+-------------+----------------------+
| 10 | P0.25 | P0.25 |
+--------+-------------+----------------------+
| 12 | P0.24 | P0.24 |
+--------+-------------+----------------------+
| 14 | P0.23 | P0.23 |
+--------+-------------+----------------------+
| 16 | N/A | N/A |
+--------+-------------+----------------------+
| 18 | N/A | PC7 |
+--------+-------------+----------------------+
| 20 | N/A | PC9 |
+--------+-------------+----------------------+
| 22 | N/A | PB8 |
+--------+-------------+----------------------+
| 24 | P0.03 | P0.03 |
+--------+-------------+----------------------+
| 26 | P0.05 | P0.05 |
+--------+-------------+----------------------+
| 28 | P0.07 | P0.07 |
+--------+-------------+----------------------+
| 30 | P0.11 | P0.11 |
+--------+-------------+----------------------+
| 32 | P0.17 | P0.17 |
+--------+-------------+----------------------+
| 34 | P0.19 | P0.19 |
+--------+-------------+----------------------+
| 36 | NC | |
+--------+-------------+----------------------+
| 38 | NC | |
+--------+-------------+----------------------+
| 40 | GND | GND |
+--------+-------------+----------------------+
More detailed information about the connectors can be found in
`96Boards IE Specification`_.
System Clock
============
nRF52 has two external oscillators. The frequency of the slow clock is
32.768 kHz. The frequency of the main clock is 32 MHz.
Serial Port
-----------
96Boards Nitrogen has one UART, which is used as Zephyr console.
Default settings is 115200 8N1.
I2C
---
96Boards Nitrogen has one I2C. The default I2C mapping for Zephyr is:
- I2C0_SCL : P0.22
- I2C0_SDA : P0.20
SPI
---
96Boards Nitrogen has one SPI. The default SPI mapping for Zephyr is:
- SPI0_NSS : P0.24
- SPI0_SCK : P0.26
- SPI0_MISO : P0.25
- SPI0_MOSI : P0.23
Flashing Zephyr onto 96Boards Nitrogen
**************************************
The 96Boards Nitrogen board can be flashed via the `CMSIS DAP`_ interface,
which is provided by the micro USB interface to the LPC11U35 chip.
Using the CMSIS-DAP interface, the board can be flashed via the USB storage
interface (drag-and-drop) and also via `pyOCD`_.
To use ``pyOCD``, install the :ref:`pyocd-debug-host-tools` and make sure they
are in your search path.
Common Errors
=============
No connected boards
-------------------
If you don't use sudo when invoking pyocd-flashtool, you might get any of the
following errors:
.. code-block:: console
No available boards are connected
.. code-block:: console
No connected boards
.. code-block:: console
Error: There is no board connected.
To fix the permission issue, simply add the following udev rule for the
NXP LPC1768 interface:
.. code-block:: console
$ echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules
Finally, unplug and plug the board again.
ValueError: The device has no langid
------------------------------------
As described by `pyOCD issue 259`_, you might get the
:code:`ValueError: The device has no langid` error when not running
pyOCD as root (e.g. sudo).
To fix the above error, add the udev rule shown in the previous section
and install a more recent version of pyOCD.
Flashing an Application to 96Boards Nitrogen
============================================
Here is an example for the :ref:`hello_world` application. This
requires installing the :ref:`pyocd-debug-host-tools`.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_nitrogen
:goals: build flash
Run your favorite terminal program to listen for output.
.. code-block:: console
$ minicom -D <tty_device> -b 115200
Replace :code:`<tty_device>` with the port where the board 96Boards Nitrogen
can be found. For example, under Linux, :code:`/dev/ttyACM0`.
The ``-b`` option sets baud rate ignoring the value from config.
Press the Reset button and you should see the following message in your
terminal:
.. code-block:: console
Hello World! arm
Debugging with GDB
==================
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application. This also requires pyOCD.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: 96b_nitrogen
:maybe-skip-config:
:goals: debug
.. _pyOCD:
path_to_url
.. _CMSIS DAP:
path_to_url
.. _Nordic Semiconductor Infocenter:
path_to_url
.. _seeed BLE Nitrogen:
path_to_url
.. _pyOCD issue 259:
path_to_url
.. _96Boards IE Specification:
path_to_url
``` | /content/code_sandbox/boards/96boards/nitrogen/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,571 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```cmake
if(CONFIG_BOARD_96B_CARBON_STM32F401XE)
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
endif()
``` | /content/code_sandbox/boards/96boards/carbon/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```cmake
if("${BOARD_QUALIFIERS}" STREQUAL "/nrf51822")
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & nrf-mpu@40000000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
endif()
``` | /content/code_sandbox/boards/96boards/carbon/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
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