text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RTS, 0, 11)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_CTS, 0, 10)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_RTS, 0, 11)>,
<NRF_PSEL(UART_CTS, 0, 10)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
low-power-enable;
};
};
spi0_default: spi0_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
};
};
spi0_sleep: spi0_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_nrf5340_cpunet-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 499 |
```unknown
# PAN1783 EVB board configuration
config BOARD_PAN1783_EVB
select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783_EVB_NRF5340_CPUAPP
select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783_EVB_NRF5340_CPUNET
``` | /content/code_sandbox/boards/panasonic/pan1783/Kconfig.pan1783_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
/*
* PAN1781 EVB configuration
*
*/
/dts-v1/;
#include <nordic/nrf52820_qdaa.dtsi>
#include "pan1781_evb-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "pan1781-evb";
compatible = "panasonic-industrial-devices-europe-gmbh,pan1781-evb";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
leds {
compatible = "gpio-leds";
evb_led1: evb_led_0 {
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
label = "LED1 on EVB";
};
evb_led2: evb_led_2 {
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
label = "LED2 on EVB";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_evb_led1: pwm_evb_led_1 {
pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
buttons {
compatible = "gpio-keys";
evb_sw1: evb_sw_1 {
gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW1 on EVB";
zephyr,code = <INPUT_KEY_0>;
};
evb_sw2: evb_sw_2 {
gpios = <&gpio0 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW2 on EVB";
zephyr,code = <INPUT_KEY_1>;
};
};
arduino_header: connector {
compatible = "panasonic,reduced-arduino-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 2 0>, /* A0 */
<1 0 &gpio0 3 0>, /* A1 */
<2 0 &gpio0 4 0>, /* A2 */
<3 0 &gpio0 5 0>, /* A3 */
<6 0 &gpio0 6 0>, /* D0 */
<7 0 &gpio0 8 0>, /* D1 */
<8 0 &gpio0 14 0>, /* D2 */
<9 0 &gpio0 15 0>, /* D3 */
<10 0 &gpio0 4 0>, /* D4 */
<11 0 &gpio0 5 0>, /* D5 */
<16 0 &gpio0 3 0>, /* D10 */
<17 0 &gpio0 20 0>, /* D11 */
<18 0 &gpio0 29 0>, /* D12 */
<19 0 &gpio0 28 0>, /* D13 */
<20 0 &gpio0 7 0>, /* D14 */
<21 0 &gpio0 30 0>; /* D15 */
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &evb_led1;
led1 = &evb_led2;
pwm-led0 = &pwm_evb_led1;
sw0 = &evb_sw1;
sw1 = &evb_sw2;
watchdog0 = &wdt0;
};
};
®1 {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&sw_pwm {
status ="okay";
channel-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
clock-prescaler = <8>;
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
arduino_serial: &uart0 {
compatible = "nordic,nrf-uarte";
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_i2c: &i2c0 {
compatible = "nordic,nrf-twi";
status = "okay";
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_spi: &spi1 {
status = "okay";
cs-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; /* D10 */
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x0 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0xc000 0x12000>;
};
slot1_partition: partition@1e000 {
label = "image-1";
reg = <0x1e000 0x12000>;
};
scratch_partition: partition@30000 {
label = "image-scratch";
reg = <0x30000 0xa000>;
};
storage_partition: partition@3a000 {
label = "storage";
reg = <0x3a000 0x6000>;
};
};
};
``` | /content/code_sandbox/boards/panasonic/pan1781_evb/pan1781_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,414 |
```cmake
if(CONFIG_SOC_NRF5340_CPUAPP_QKAA)
board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000")
endif()
if(CONFIG_SOC_NRF5340_CPUNET_QKAA)
board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000")
endif()
include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/panasonic/pan1783/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 110 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Clock config
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```yaml
identifier: pan1783a_evb/nrf5340/cpuapp
name: PAN1783A-EVB-application-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 448
flash: 1024
supported:
- gpio
- i2c
- i2s
- pwm
- watchdog
- usb_device
- netif:openthread
- gpio
vendor: panasonic
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 118 |
```unknown
# PAN1783 EVB board configuration
config BOARD_PAN1783A_PA_EVB
select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP
select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET
``` | /content/code_sandbox/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 77 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
#include "pan1783_nrf5340_cpunet_common.dtsi"
/ {
model = "Panasonic PAN1783 EVB (NRF5340) Network";
compatible = "panasonic,pan1783-evb-cpunet";
chosen {
zephyr,sram = &sram1;
zephyr,flash = &flash1;
zephyr,code-partition = &slot0_partition;
};
};
/* Include shared RAM configuration file */
#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi"
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "pan1783_nrf5340_cpuapp_common.dtsi"
/ {
model = "Panasonic PAN1783A EVB (NRF5340) Application";
compatible = "panasonic,pan1783a-evb-cpuapp";
chosen {
zephyr,sram = &sram0_image;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,sram-secure-partition = &sram0_s;
};
};
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 142 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - flash-controller@39000 & kmu@39000
# - power@5000 & clock@5000
# - /reserved-memory/image@20000000 & /reserved-memory/image_s@20000000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/panasonic/pan1783/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
/*
*
*/
/* Default shared SRAM planning when building for PAN1783 EVB.
* This file is included by both nRF5340 CPUAPP (Application MCU)
* and nRF5340 CPUNET (Network MCU).
* - 64 kB SRAM allocated as Shared memory (sram0_shared)
* - Region defined after the image SRAM of Application MCU
*/
/ {
chosen {
/* shared memory reserved for the inter-processor communication */
zephyr,ipc_shm = &sram0_shared;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram0_shared: memory@20070000 {
/* SRAM allocated to shared memory */
reg = <0x20070000 0x10000>;
};
};
};
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 185 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "pan1783_nrf5340_cpuapp_common.dtsi"
/ {
model = "Panasonic PAN1783 EVB (NRF5340) Application";
compatible = "panasonic,pan1783-evb-cpuapp";
chosen {
zephyr,sram = &sram0_image;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,sram-secure-partition = &sram0_s;
};
};
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 140 |
```yaml
identifier: pan1783a_evb/nrf5340/cpunet
name: PAN1783A-EVB-network-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 64
flash: 256
supported:
- watchdog
- gpio
vendor: panasonic
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpuapp_qkaa.dtsi>
#include "pan1783_nrf5340_cpuapp_common.dtsi"
/ {
model = "Panasonic PAN1783A-PA EVB (NRF5340) Application";
compatible = "panasonic,pan1783a_pa-evb-cpuapp";
chosen {
zephyr,sram = &sram0_image;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,sram-secure-partition = &sram0_s;
};
};
&gpio_fwd {
/delete-node/ uart;
status = "okay";
fem {
gpios = <&gpio0 19 0>, <&gpio0 21 0>;
};
};
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 188 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Clock config
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Clock config
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
/*
*
*/
/*
* Default Flash planning for pan1783_evb CPUAPP (Application MCU).
*
* Secure image will be placed, by default, in flash0
* (or in slot0, if MCUboot is present).
* Secure image will use sram0 for system memory.
*
*/
&slot0_partition {
reg = <0x00010000 0x40000>;
};
&slot1_partition {
reg = <0x00080000 0x40000>;
};
/* Default SRAM planning when building for nRF5340
* - Lowest 448 kB SRAM allocated to Secure image (sram0_s)
* - Upper 64 kB SRAM allocated as Shared memory (sram0_shared)
* (see shared_sram_planning_conf.dtsi)
*/
&sram0_image {
reg = <0x20000000 DT_SIZE_K(448)>;
};
&sram0_s {
reg = <0x20000000 0x70000>;
};
/* Include shared RAM configuration file */
#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi"
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 234 |
```yaml
boards:
- name: pan1783_evb
vendor: panasonic
socs:
- name: nrf5340
- name: pan1783a_evb
vendor: panasonic
socs:
- name: nrf5340
- name: pan1783a_pa_evb
vendor: panasonic
socs:
- name: nrf5340
``` | /content/code_sandbox/boards/panasonic/pan1783/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Clock config
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Clock config
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```yaml
identifier: pan1783a_pa_evb/nrf5340/cpunet
name: PAN1783A-PA-EVB-network-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 64
flash: 256
supported:
- watchdog
- gpio
vendor: panasonic
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```unknown
# PAN1783 EVB board configuration
config BOARD_PAN1783A_EVB
select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783A_EVB_NRF5340_CPUAPP
select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783A_EVB_NRF5340_CPUNET
``` | /content/code_sandbox/boards/panasonic/pan1783/Kconfig.pan1783a_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
/*
*/
&pinctrl {
i2c1_default: i2c1_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
};
};
i2c1_sleep: i2c1_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
<NRF_PSEL(TWIM_SCL, 1, 3)>;
low-power-enable;
};
};
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RTS, 0, 11)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_CTS, 0, 10)>;
bias-pull-up;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 20)>,
<NRF_PSEL(UART_RX, 0, 22)>,
<NRF_PSEL(UART_RTS, 0, 11)>,
<NRF_PSEL(UART_CTS, 0, 10)>;
low-power-enable;
};
};
pwm0_default: pwm0_default {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
};
};
pwm0_sleep: pwm0_sleep {
group1 {
psels = <NRF_PSEL(PWM_OUT0, 0, 28)>;
low-power-enable;
};
};
qspi_default: qspi_default {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
<NRF_PSEL(QSPI_IO0, 0, 13)>,
<NRF_PSEL(QSPI_IO1, 0, 14)>,
<NRF_PSEL(QSPI_IO2, 0, 15)>,
<NRF_PSEL(QSPI_IO3, 0, 16)>,
<NRF_PSEL(QSPI_CSN, 0, 18)>;
nordic,drive-mode = <NRF_DRIVE_H0H1>;
};
};
qspi_sleep: qspi_sleep {
group1 {
psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
<NRF_PSEL(QSPI_IO0, 0, 13)>,
<NRF_PSEL(QSPI_IO1, 0, 14)>,
<NRF_PSEL(QSPI_IO2, 0, 15)>,
<NRF_PSEL(QSPI_IO3, 0, 16)>;
low-power-enable;
};
group2 {
psels = <NRF_PSEL(QSPI_CSN, 0, 18)>;
low-power-enable;
bias-pull-up;
};
};
uart1_default: uart1_default {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>;
};
group2 {
psels = <NRF_PSEL(UART_RX, 1, 0)>;
bias-pull-up;
};
};
uart1_sleep: uart1_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 1, 1)>,
<NRF_PSEL(UART_RX, 1, 0)>;
low-power-enable;
};
};
spi4_default: spi4_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
};
};
spi4_sleep: spi4_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
<NRF_PSEL(SPIM_MISO, 1, 14)>,
<NRF_PSEL(SPIM_MOSI, 1, 13)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,018 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable hardware stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable GPIO
CONFIG_GPIO=y
# Enable UART driver
CONFIG_SERIAL=y
# Enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Clock config
CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
#include "pan1783_nrf5340_cpunet_common.dtsi"
/ {
model = "Panasonic PAN1783A EVB (NRF5340) Network";
compatible = "panasonic,pan1783a-evb-cpunet";
chosen {
zephyr,sram = &sram1;
zephyr,flash = &flash1;
zephyr,code-partition = &slot0_partition;
};
};
/* Include shared RAM configuration file */
#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi"
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```yaml
identifier: pan1783_evb/nrf5340/cpunet
name: PAN1783-EVB-network-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 64
flash: 256
supported:
- watchdog
- gpio
vendor: panasonic
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 82 |
```unknown
# PAN1783 EVB board configuration
if SOC_NRF5340_CPUAPP_QKAA
config BT_HCI_IPC
default y if BT
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 4096 if BT_HCI_IPC
endif # SOC_NRF5340_CPUAPP_QKAA
if SOC_NRF5340_CPUNET_QKAA
config BT_CTLR
default y if BT
endif # SOC_NRF5340_CPUNET_QKAA
``` | /content/code_sandbox/boards/panasonic/pan1783/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 103 |
```unknown
# PAN1783 EVB board configuration
if SOC_NRF5340_CPUAPP_QKAA
config DOMAIN_CPUNET_BOARD
string
default "pan1783_evb/nrf5340/cpunet" if BOARD_PAN1783_EVB_NRF5340_CPUAPP
default "pan1783a_evb/nrf5340/cpunet" if BOARD_PAN1783A_EVB_NRF5340_CPUAPP
default "pan1783a_pa_evb/nrf5340/cpunet" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP
help
The board which will be used for CPUNET domain when creating a multi
image application where one or more images should be located on
another board. For example hci_ipc on the nRF5340_cpunet for
Bluetooth applications.
endif # SOC_NRF5340_CPUAPP_QKAA
config DOMAIN_CPUAPP_BOARD
string
default "pan1783_evb/nrf5340/cpuapp" if BOARD_PAN1783_EVB_NRF5340_CPUNET
default "pan1783a_evb/nrf5340/cpuapp" if BOARD_PAN1783A_EVB_NRF5340_CPUNET
default "pan1783a_pa_evb/nrf5340/cpuapp" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET
help
The board which will be used for CPUAPP domain when creating a multi
image application where one or more images should be located on
another board.
``` | /content/code_sandbox/boards/panasonic/pan1783/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 330 |
```unknown
/*
*
*/
/dts-v1/;
#include <nordic/nrf5340_cpunet_qkaa.dtsi>
#include "pan1783_nrf5340_cpunet_common.dtsi"
/ {
model = "Panasonic PAN1783A-PA EVB (NRF5340) Network";
compatible = "panasonic,pan1783a_pa-evb-cpunet";
chosen {
zephyr,sram = &sram1;
zephyr,flash = &flash1;
zephyr,code-partition = &slot0_partition;
};
nrf_radio_fem: fem_node {
compatible = "skyworks,sky66407-11", "generic-fem-two-ctrl-pins";
ctx-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
crx-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
};
};
&radio {
fem = <&nrf_radio_fem>;
};
/* Include shared RAM configuration file */
#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi"
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 236 |
```yaml
identifier: pan1783_evb/nrf5340/cpuapp
name: PAN1783-EVB-application-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 448
flash: 1024
supported:
- gpio
- i2c
- i2s
- pwm
- watchdog
- usb_device
- netif:openthread
- gpio
vendor: panasonic
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```yaml
identifier: pan1783a_pa_evb/nrf5340/cpuapp
name: PAN1783A-PA-EVB-application-MCU
type: mcu
arch: arm
toolchain:
- gnuarmemb
- xtools
- zephyr
ram: 448
flash: 1024
supported:
- gpio
- i2c
- i2s
- pwm
- watchdog
- usb_device
- netif:openthread
- gpio
vendor: panasonic
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```unknown
/*
*
*/
#include "pan1783_nrf5340_cpunet-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,bt-hci-ipc = &ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
evb_led1: evb_led_1 {
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
label = "LED1 on EVB";
};
evb_led2: evb_led_2 {
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
label = "LED2 on EVB";
};
evb_led3: evb_led_3 {
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
label = "LED3 on EVB";
};
evb_led4: evb_led_4 {
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
label = "LED4 on EVB";
};
};
buttons {
compatible = "gpio-keys";
evb_sw1: evb_sw_1 {
gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW1 on EVB";
zephyr,code = <INPUT_KEY_0>;
};
evb_sw2: evb_sw_2 {
gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW2 on EVB";
zephyr,code = <INPUT_KEY_1>;
};
evb_sw3: evb_sw_3 {
gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW3 on EVB";
zephyr,code = <INPUT_KEY_2>;
};
evb_sw4: evb_sw_4 {
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW4 on EVB";
zephyr,code = <INPUT_KEY_3>;
};
};
mikrobus_header: mikrobus-connector {
compatible = "mikro-bus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 4 0>, /* AN */
/* Not a GPIO*/ /* RST */
<2 0 &gpio1 12 0>, /* CS */
<3 0 &gpio1 15 0>, /* SCK */
<4 0 &gpio1 14 0>, /* MISO */
<5 0 &gpio1 13 0>, /* MOSI */
/* +3.3V */
/* GND */
<6 0 &gpio1 7 0>, /* PWM */
<7 0 &gpio1 4 0>, /* INT */
<8 0 &gpio1 0 0>, /* RX */
<9 0 &gpio1 1 0>, /* TX */
<10 0 &gpio1 3 0>, /* SCL */
<11 0 &gpio1 2 0>; /* SDA */
/* +5V */
/* GND */
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 4 0>, /* A0 */
<1 0 &gpio0 5 0>, /* A1 */
<2 0 &gpio0 6 0>, /* A2 */
<3 0 &gpio0 7 0>, /* A3 */
<4 0 &gpio0 25 0>, /* A4 */
<5 0 &gpio0 26 0>, /* A5 */
<6 0 &gpio1 0 0>, /* D0 */
<7 0 &gpio1 1 0>, /* D1 */
<8 0 &gpio1 4 0>, /* D2 */
<9 0 &gpio1 5 0>, /* D3 */
<10 0 &gpio1 6 0>, /* D4 */
<11 0 &gpio1 7 0>, /* D5 */
<12 0 &gpio1 8 0>, /* D6 */
<13 0 &gpio1 9 0>, /* D7 */
<14 0 &gpio1 10 0>, /* D8 */
<15 0 &gpio1 11 0>, /* D9 */
<16 0 &gpio1 12 0>, /* D10 */
<17 0 &gpio1 13 0>, /* D11 */
<18 0 &gpio1 14 0>, /* D12 */
<19 0 &gpio1 15 0>, /* D13 */
<20 0 &gpio1 2 0>, /* D14 */
<21 0 &gpio1 3 0>; /* D15 */
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &evb_led1;
led1 = &evb_led2;
led2 = &evb_led3;
led3 = &evb_led4;
sw0 = &evb_sw1;
sw1 = &evb_sw2;
sw2 = &evb_sw3;
sw3 = &evb_sw4;
bootloader-led0 = &evb_led1;
mcuboot-button0 = &evb_sw1;
mcuboot-led0 = &evb_led1;
watchdog0 = &wdt0;
};
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&uart0 {
status = "disabled";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_serial: &uart0 {};
arduino_i2c: &i2c0 {
compatible = "nordic,nrf-twim";
/* Cannot be used together with uart0. */
/* status = "okay"; */
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_spi: &spi0 {
compatible = "nordic,nrf-spim";
/* Cannot be used together with uart0. */
/* status = "okay"; */
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
pinctrl-0 = <&spi0_default>;
pinctrl-1 = <&spi0_sleep>;
pinctrl-names = "default", "sleep";
};
&flash1 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x17000>;
};
slot1_partition: partition@23000 {
label = "image-1";
reg = <0x00023000 0x17000>;
};
storage_partition: partition@3a000 {
label = "storage";
reg = <0x0003a000 0x6000>;
};
};
};
&ieee802154 {
status = "okay";
};
/* Include shared RAM configuration file */
#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi"
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,982 |
```unknown
/*
*
*/
#include "pan1783_nrf5340_cpuapp_common-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,uart-mcumgr = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,bt-hci = &bt_hci_ipc0;
nordic,802154-spinel-ipc = &ipc0;
zephyr,ieee802154 = &ieee802154;
};
leds {
compatible = "gpio-leds";
evb_led1: evb_led_1 {
gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
label = "LED1 on EVB";
};
evb_led2: evb_led_2 {
gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
label = "LED2 on EVB";
};
evb_led3: evb_led_3 {
gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
label = "LED3 on EVB";
};
evb_led4: evb_led_4 {
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
label = "LED4 on EVB";
};
};
pwmleds {
compatible = "pwm-leds";
pwm_evb_led1: pwm_evb_led_1 {
pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
};
};
buttons {
compatible = "gpio-keys";
evb_sw1: evb_sw_1 {
gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW1 on EVB";
zephyr,code = <INPUT_KEY_0>;
};
evb_sw2: evb_sw_2 {
gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW2 on EVB";
zephyr,code = <INPUT_KEY_1>;
};
evb_sw3: evb_sw_3 {
gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW3 on EVB";
zephyr,code = <INPUT_KEY_2>;
};
evb_sw4: evb_sw_4 {
gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "SW4 on EVB";
zephyr,code = <INPUT_KEY_3>;
};
};
mikrobus_header: mikrobus-connector {
compatible = "mikro-bus";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 4 0>, /* AN */
/* Not a GPIO*/ /* RST */
<2 0 &gpio1 12 0>, /* CS */
<3 0 &gpio1 15 0>, /* SCK */
<4 0 &gpio1 14 0>, /* MISO */
<5 0 &gpio1 13 0>, /* MOSI */
/* +3.3V */
/* GND */
<6 0 &gpio1 7 0>, /* PWM */
<7 0 &gpio1 4 0>, /* INT */
<8 0 &gpio1 0 0>, /* RX */
<9 0 &gpio1 1 0>, /* TX */
<10 0 &gpio1 3 0>, /* SCL */
<11 0 &gpio1 2 0>; /* SDA */
/* +5V */
/* GND */
};
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpio0 4 0>, /* A0 */
<1 0 &gpio0 5 0>, /* A1 */
<2 0 &gpio0 6 0>, /* A2 */
<3 0 &gpio0 7 0>, /* A3 */
<4 0 &gpio0 25 0>, /* A4 */
<5 0 &gpio0 26 0>, /* A5 */
<6 0 &gpio1 0 0>, /* D0 */
<7 0 &gpio1 1 0>, /* D1 */
<8 0 &gpio1 4 0>, /* D2 */
<9 0 &gpio1 5 0>, /* D3 */
<10 0 &gpio1 6 0>, /* D4 */
<11 0 &gpio1 7 0>, /* D5 */
<12 0 &gpio1 8 0>, /* D6 */
<13 0 &gpio1 9 0>, /* D7 */
<14 0 &gpio1 10 0>, /* D8 */
<15 0 &gpio1 11 0>, /* D9 */
<16 0 &gpio1 12 0>, /* D10 */
<17 0 &gpio1 13 0>, /* D11 */
<18 0 &gpio1 14 0>, /* D12 */
<19 0 &gpio1 15 0>, /* D13 */
<20 0 &gpio1 2 0>, /* D14 */
<21 0 &gpio1 3 0>; /* D15 */
};
arduino_adc: analog-connector {
compatible = "arduino,uno-adc";
#io-channel-cells = <1>;
io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */
<1 &adc 1>, /* A1 = P0.5 = AIN1 */
<2 &adc 2>, /* A2 = P0.6 = AIN2 */
<3 &adc 3>, /* A3 = P0.7 = AIN3 */
<4 &adc 4>, /* A4 = P0.25 = AIN4 */
<5 &adc 5>; /* A5 = P0.26 = AIN5 */
};
gpio_fwd: nrf-gpio-forwarder {
compatible = "nordic,nrf-gpio-forwarder";
status = "disabled";
uart {
gpios = <&gpio0 20 0>, <&gpio0 22 0>, <&gpio0 11 0>, <&gpio0 10 0>;
};
};
/* These aliases are provided for compatibility with samples */
aliases {
led0 = &evb_led1;
led1 = &evb_led2;
led2 = &evb_led3;
led3 = &evb_led4;
pwm-led0 = &pwm_evb_led1;
sw0 = &evb_sw1;
sw1 = &evb_sw2;
sw2 = &evb_sw3;
sw3 = &evb_sw4;
bootloader-led0 = &evb_led1;
mcuboot-button0 = &evb_sw1;
mcuboot-led0 = &evb_led1;
watchdog0 = &wdt0;
};
};
&vregmain {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&vregradio {
regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
};
&vregh {
status = "okay";
};
&adc {
status = "okay";
};
&gpiote {
status = "okay";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&i2c1 {
compatible = "nordic,nrf-twim";
status = "okay";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
pinctrl-names = "default", "sleep";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_default>;
pinctrl-1 = <&pwm0_sleep>;
pinctrl-names = "default", "sleep";
};
&qspi {
status = "okay";
pinctrl-0 = <&qspi_default>;
pinctrl-1 = <&qspi_sleep>;
pinctrl-names = "default", "sleep";
mx25r64: mx25r6435f@0 {
compatible = "nordic,qspi-nor";
reg = <0>;
/* MX25R64 supports only pp and pp4io */
writeoc = "pp4io";
/* MX25R64 supports all readoc options */
readoc = "read4io";
sck-frequency = <8000000>;
jedec-id = [ c2 28 17 ];
sfdp-bfp = [
e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb
ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52
10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44
30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff
];
size = <67108864>;
has-dpd;
t-enter-dpd = <10000>;
t-exit-dpd = <35000>;
};
};
arduino_serial: &uart1 {
compatible = "nordic,nrf-uarte";
current-speed = <115200>;
pinctrl-0 = <&uart1_default>;
pinctrl-1 = <&uart1_sleep>;
pinctrl-names = "default", "sleep";
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi4 {
compatible = "nordic,nrf-spim";
status = "okay";
cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */
pinctrl-0 = <&spi4_default>;
pinctrl-1 = <&spi4_sleep>;
pinctrl-names = "default", "sleep";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
};
slot0_partition: partition@10000 {
label = "image-0";
};
slot1_partition: partition@80000 {
label = "image-1";
};
/* 0xf0000 to 0xf7fff reserved for TF-M partitions */
storage_partition: partition@f8000 {
label = "storage";
reg = <0x000f8000 0x00008000>;
};
};
};
&ieee802154 {
status = "okay";
};
zephyr_udc0: &usbd {
compatible = "nordic,nrf-usbd";
status = "okay";
};
/ {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
sram0_image: image@20000000 {
/* Zephyr image(s) memory */
};
sram0_s: image_s@20000000 {
/* Secure image memory */
};
};
};
/* Include partition configuration file */
#include "pan1783_nrf5340_cpuapp_partition_conf.dtsi"
``` | /content/code_sandbox/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,854 |
```restructuredtext
.. _boards-blues:
Blues
#####
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/blues/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _pan1783_evb:
PAN1783, PAN1783A and PAN1783A-PA Evaluation Boards
###################################################
Overview
********
The PAN1783, PAN1783A and PAN1783A-PA Evaluation Boards (pan1783_evb,
pan1783a_evb, pan1783a_pa_evb) are development tools for the PAN1783,
PAN1783A and PAN1783A-PA Modules which are based on the nRF5340 chipset
from Nordic Semiconductor.
More information about the PAN1783, PAN1783A, PAN1783A-PA Modules and
Evaluation Boards can be found on the `product website`_.
PAN1783 EVB
***********
.. figure:: img/pan1783_evb.webp
:align: center
:alt: PAN1783 EVB
PAN1783 EVB (Credit: Panasonic)
PAN1783A EVB
************
The PAN1783A EVB essentially looks like a PAN1783 EVB, except that it is
equipped with a UFL connector on X4.
PAN1783A-PA EVB
***************
The PAN1783A-PA EVB essentially resembles a PAN1783 EVB, with the addition
of a UFL connector on X4 and a power amplifier.
Usage
*****
For detailed information, you can find the
`pan1783_evb user guide`_ / `pan1783a_evb user guide`_ / `pan1783a_pa_evb user guide`_
for the Evaluation Boards in the `Panasonic Wireless Connectivity Development Hub`_.
The User Guide contains (amongst other things) detailed information about
* pin mapping
* powering options
* breakout pin header interface
* current consumption measurement
* software development
The schematics for the PAN1783/PAN1783A/PAN1783A-PA Evaluation Boards are
available in the `download section PAN1783`_ / `download section PAN1783A`_ / `download section PAN1783A-PA`_
of the `Panasonic Wireless Connectivity Development Hub`_.
Programming and Debugging
*************************
Please use the ``pan1783_evb_cpuapp``, ``pan1783a_evb_cpuapp`` or
``pan1783a_pa_evb_cpuapp`` for application core and ``pan1783_evb_cpunet``,
``pan1783a_evb_cpunet`` or ``pan1783a_pa_evb_cpunet`` board configuration
for network core when :ref:`build_an_application` and :ref:`application_run`.
.. target-notes::
.. _product website: path_to_url
.. _Panasonic Wireless Connectivity Development Hub: path_to_url
.. _pan1783_evb user guide: path_to_url
.. _pan1783a_evb user guide: path_to_url
.. _pan1783a_pa_evb user guide: path_to_url
.. _download section PAN1783: path_to_url
.. _download section PAN1783A: path_to_url
.. _download section PAN1783A-PA: path_to_url
``` | /content/code_sandbox/boards/panasonic/pan1783/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 667 |
```unknown
config BOARD_SWAN_R5
select SOC_STM32L4R5XX
``` | /content/code_sandbox/boards/blues/swan_r5/Kconfig.swan_r5 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```cmake
board_runner_args(jlink "--device=STM32L4R5ZI" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/blues/swan_r5/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
CONFIG_REGULATOR=y
``` | /content/code_sandbox/boards/blues/swan_r5/swan_r5_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 79 |
```c
/*
*
*/
#include <zephyr/drivers/gpio.h>
#include <zephyr/init.h>
static int board_swan_init(void)
{
const struct gpio_dt_spec dischrg =
GPIO_DT_SPEC_GET(DT_PATH(zephyr_user), dischrg_gpios);
if (!gpio_is_ready_dt(&dischrg)) {
return -ENODEV;
}
(void)gpio_pin_configure_dt(&dischrg, GPIO_OUTPUT_INACTIVE);
return 0;
}
SYS_INIT(board_swan_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
``` | /content/code_sandbox/boards/blues/swan_r5/board.c | c | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 116 |
```yaml
board:
name: swan_r5
vendor: blues
socs:
- name: stm32l4r5xx
``` | /content/code_sandbox/boards/blues/swan_r5/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: swan_r5
name: Blues Wireless Swan
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- pwm
- spi
- i2c
- gpio
- usb_device
- nvs
- counter
- adc
ram: 640
flash: 2048
vendor: blues
``` | /content/code_sandbox/boards/blues/swan_r5/swan_r5.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
# Blues Wireless Swan board configuration
if BOARD_SWAN_R5
config SPI_STM32_INTERRUPT
default y
depends on SPI
if NETWORKING
config USB_DEVICE_STACK
default y
config USB_DEVICE_NETWORK_EEM
default y
endif # NETWORKING
endif # BOARD_SWAN_R5
``` | /content/code_sandbox/boards/blues/swan_r5/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/l4/stm32l4r5Xi.dtsi>
#include <st/l4/stm32l4r5z(g-i)yx-pinctrl.dtsi>
#include "feather_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "Blues Wireless Swan board";
compatible = "blues,swan-r5";
chosen {
zephyr,console = &lpuart1;
zephyr,shell-uart = &lpuart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
led0: led_0 {
gpios = <&gpioe 2 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
zephyr,user {
dischrg-gpios = <&gpioe 6 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
};
supply-3v3 {
compatible = "regulator-fixed";
regulator-name = "supply-3v3";
enable-gpios = <&gpioe 4 GPIO_ACTIVE_HIGH>;
regulator-boot-on;
};
aliases {
led0 = &led0;
sw0 = &user_button;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <40>;
div-p = <7>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pg7 &lpuart1_rx_pg8>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
pinctrl-names = "default";
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pc0 &i2c3_sda_pc9>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_pd0 &spi2_sck_pd1
&spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
status = "okay";
};
&spi3 {
pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pc10
&spi3_miso_pc11 &spi3_mosi_pc12>;
pinctrl-names = "default";
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12
&usb_otg_fs_id_pa10>;
pinctrl-names = "default";
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa0>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve last 16KiB for property storage */
storage_partition: partition@1FB000 {
label = "storage";
reg = <0x001FB000 0x00004000>;
};
};
};
&adc1 {
pinctrl-0 = <&adc1_in6_pa1>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/blues/swan_r5/swan_r5.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,346 |
```ini
source [find board/st_nucleo_l4.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/blues/swan_r5/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
/*
*
*/
/ {
feather_header: connector {
compatible = "adafruit-feather-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioa 1 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpioc 1 0>, /* A3 */
<4 0 &gpioc 4 0>, /* A4 */
<5 0 &gpioc 5 0>, /* A5 */
<6 0 &gpioa 5 0>, /* SCK */
<7 0 &gpioa 7 0>, /* MOSI */
<8 0 &gpioa 6 0>, /* MISO */
<9 0 &gpioa 10 0>, /* RX */
<10 0 &gpioa 9 0>, /* TX */
<11 0 &gpioe 3 0>, /* D4 */
<12 0 &gpiob 7 0>, /* SDA */
<13 0 &gpiob 6 0>, /* SCL */
<14 0 &gpioe 11 0>, /* D5 */
<15 0 &gpioe 9 0>, /* D6 */
<16 0 &gpiod 15 0>, /* D9 */
<17 0 &gpioa 4 0>, /* D10 */
<18 0 &gpioa 7 0>, /* D11 */
<19 0 &gpioa 6 0>, /* D12 */
<20 0 &gpioa 5 0>; /* D13 */
};
};
feather_serial: &usart1 {};
feather_i2c: &i2c1 {};
feather_spi: &spi1 {};
``` | /content/code_sandbox/boards/blues/swan_r5/feather_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 501 |
```restructuredtext
.. _boards-aspeed:
ASPEED Technology Inc.
######################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/aspeed/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
#
#
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
CONFIG_MAIN_STACK_SIZE=4096
CONFIG_FLASH_SIZE=0
CONFIG_FLASH_BASE_ADDRESS=0x0
CONFIG_XIP=n
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_HEAP_MEM_POOL_SIZE=50000
CONFIG_CLOCK_CONTROL=y
CONFIG_RESET=y
``` | /content/code_sandbox/boards/aspeed/ast1030_evb/ast1030_evb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```yaml
board:
name: ast1030_evb
vendor: aspeed
socs:
- name: ast1030
``` | /content/code_sandbox/boards/aspeed/ast1030_evb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
/*
*
*/
/dts-v1/;
#include <aspeed/ast10x0.dtsi>
/ {
model = "Aspeed AST1030 Evaluation board";
compatible = "aspeed,ast1030-evb";
chosen {
zephyr,console = &uart5;
zephyr,shell-uart = &uart5;
zephyr,sram = &sram0;
};
};
&sram0 {
reg = <0 DT_SIZE_K(448)>, <0x70000 DT_SIZE_K(320)>;
};
&uart5 {
clock-frequency = <1846153>;
current-speed = <115200>;
status = "okay";
};
``` | /content/code_sandbox/boards/aspeed/ast1030_evb/ast1030_evb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 143 |
```unknown
#
# Aspeed AST1030 evaluation board configuration
#
config BOARD_AST1030_EVB
select SOC_AST1030
``` | /content/code_sandbox/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
identifier: ast1030_evb
name: Aspeed AST1030-EVB
type: mcu
arch: arm
toolchain:
- zephyr
ram: 768
flash: 1024
supported:
- serial
vendor: aspeed
``` | /content/code_sandbox/boards/aspeed/ast1030_evb/ast1030_evb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```restructuredtext
.. _ast1030_evb:
AST1030_EVB
###################
Overview
********
The AST1030_EVB kit is a development platform to evaluate the
Aspeed AST10x0 series SOCs. This board needs to be mated with
part number AST1030.
.. image:: ast1030_evb.jpg
:align: center
:alt: AST1030 Evaluation Board
Hardware
********
- ARM Cortex-M4F Processor
- 768 KB on-chip SRAM for instruction and data memory
- 1 MB on-chip Flash memory for boot ROM and data storage
- SPI interface
- UART interface
- I2C/I3C interface
- FAN PWM interface
- ADC interface
- JTAG interface
- USB interface
- LPC interface
- eSPI interface
Supported Features
==================
The following features are supported:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr (at the moment)
The default configuration can be found in
:zephyr_file:`boards/aspeed/ast1030_evb/ast1030_evb_defconfig`
Connections and IOs
===================
Aspeed to provide the schematic for this board.
System Clock
============
The AST1030 SOC is configured to use external 25MHz clock input to generate 200Mhz system clock by
the on-chip PLL.
Serial Port
===========
UART5 is configured for serial logs. The default serial setup is 115200 8N1.
Programming and Debugging
*************************
This board comes with a JTAG port which facilitates debugging using a single physical connection.
Flashing
========
Build application as usual for the ``ast1030_evb`` board, and flash
using SF100 SPI Flash programmer. See the
`Aspeed Zephyr SDK User Guide`_ for more information.
Debugging
=========
Use JTAG or SWD with a J-Link
References
**********
.. target-notes::
.. _Aspeed Zephyr SDK User Guide:
path_to_url
``` | /content/code_sandbox/boards/aspeed/ast1030_evb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 515 |
```restructuredtext
.. _boards-pine64:
Pine64
######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/pine64/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```yaml
identifier: pinetime_devkit0
name: Pine64 PineTime DevKit0
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 64
flash: 512
supported:
- kscan:touch
vendor: pine64
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```restructuredtext
.. _swan_r5_board:
Blues Wireless Swan
###################
Overview
********
Swan is a low-cost embeddable STM32L4-based microcontroller designed to
accelerate the development and deployment of battery-powered solutions.
It is especially useful for applications requiring large memory or a high
degree of I/O expandability at an affordable cost, such as edge inferencing
and remote monitoring.
Uniquely for Feather-compatible boards, Swan is designed to satisfy
developers' needs that span from early prototyping through high-volume
deployment. Developers may begin to use Swan in conjunction with
Adafruit's myriad sensors and FeatherWing-compatible carriers.
Due to its novel design, for high-volume deployment the low-cost Swan
can also be soldered directly to a parent PCB integrating those sensors,
utilizing the full range of Swan's I/O capabilities.
The board has three independent power options-USB, Battery, or Line power-
and provides a software-switchable 2 Amp regulator for powering external
sensors. When operating in its low-power operating mode, the entire Swan
board commonly draws only about 8uA while retaining all of its memory,
making it quite suitable for battery-powered devices.
The Swan board features an ARM Cortex-M4 based STM32L4R5ZI MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the board:
- STM32 microcontroller in WLCSP144 package
- 2MB of flash and 640KB of RAM
- Two types of extension resources:
- Adafruit Feather-compatible connectivity
- Access to 36 additional STM32 pins (beyond the Feather pins) via 0.05" castellated edge headers
- On-board ST-LINKV3 debugger/programmer with SWD connector
- One Red User LED (LD1)
- Two push-buttons: USER and RESET
- Castellated-edge access to 55 GPIO ports including:
- 8 analog
- 16 digital
- 4x I2C, 3x SPI
- USB OTG full speed
- 1x 14-channel DMA
- tRNG
- 12-bit ADC, 2 x 12-bit DAC
- low-power RTC, and CRC calculation peripherals
.. image:: img/swan.jpg
:align: center
:alt: Blues Wireless Swan
More information about the board can be found at the `Swan Product Page`_.
Hardware
********
The STM32L4R5ZI SoC provides the following hardware IPs:
- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode
and 100 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive
real-time accelerator (ART Accelerator) allowing 0-wait-state
execution from Flash memory, frequency up to 120 MHz, MPU, 150
DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Memories
- 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection
- 640 Kbytes of SRAM including 64 Kbytes with hardware parity check
- External memory interface for static memories supporting SRAM,
PSRAM, NOR, NAND and FRAM memories
- 2 x OctoSPI memory interface
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace
Macrocell (ETM)
More information about Swan can be found here:
- `Swan Quickstart Guide`_
- `Swan Datasheet`_
Supported Features
==================
The Zephyr Swan board configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/blues/swan_r5/swan_r5_defconfig`
Connections and IOs
===================
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- A0 : PA3
- A1 : PA1
- A2 : PC3
- A3 : PC1
- A4 : PC4
- A5 : PC5
- D4 : PE3
- D5 : PE11
- D6 : PE9
- D9 : PD15
- D10 : PA4
- D11 : PA7
- D12 : PA6
- D13 : PA5
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PA2
- UART_2_RX : PD6
- UART_3_TX : PB10
- UART_3_RX : PB11
- LPUART_TX : PG7
- LPUART_RX : PG8
- I2C_1_SCL : PB6
- I2C_1_SDA : PB7
- I2C_2_SCL : PF1
- I2C_2_SDA : PF0
- I2C_3_SCL : PC0
- I2C_3_SDA : PC9
- SPI_1_NSS : PA4
- SPI_1_SCK : PA5
- SPI_1_MISO : PA6
- SPI_1_MOSI : PA7
- SPI_2_NSS : PD0
- SPI_2_SCK : PD1
- SPI_2_MISO : PB14
- SPI_2_MOSI : PB15
- SPI_3_NSS : PA15
- SPI_3_SCK : PC10
- SPI_3_MISO : PC11
- SPI_3_MOSI : PC12
- PWM_2_CH1 : PA0
- USER_PB : PC13
- LD1 : PE2
- USB DM : PA11
- USB DP : PA12
- ADC1 : PA1
System Clock
------------
Swan System Clock could be driven by internal or external
oscillator, as well as main PLL clock. By default, the System clock is
driven by the PLL clock at 80MHz, driven by a 16MHz high speed
internal oscillator.
Serial Port
-----------
Swan has 4 U(S)ARTs. The Zephyr console output is
assigned to LPUART. Default settings are 115200 8N1.
Programming and Debugging
*************************
Connect Swan to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Swan:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: swan_r5
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
References
**********
.. _Swan Product Page:
path_to_url
.. _Swan Quickstart Guide:
path_to_url
.. _Swan Datasheet:
path_to_url
``` | /content/code_sandbox/boards/blues/swan_r5/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,803 |
```cmake
board_runner_args(pyocd "--target=nrf52832")
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 49 |
```unknown
# PineTime DevKit0 board configuration
config BOARD_PINETIME_DEVKIT0
select SOC_NRF52832_QFAA
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 28 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - power@40000000 & clock@40000000 & bprot@40000000
# - acl@4001e000 & flash-controller@4001e000
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```unknown
/*
*/
&pinctrl {
uart0_default: uart0_default {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 11)>,
<NRF_PSEL(UART_RX, 0, 30)>;
};
};
uart0_sleep: uart0_sleep {
group1 {
psels = <NRF_PSEL(UART_TX, 0, 11)>,
<NRF_PSEL(UART_RX, 0, 30)>;
low-power-enable;
};
};
i2c0_default: i2c0_default {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 6)>,
<NRF_PSEL(TWIM_SCL, 0, 7)>;
};
};
i2c0_sleep: i2c0_sleep {
group1 {
psels = <NRF_PSEL(TWIM_SDA, 0, 6)>,
<NRF_PSEL(TWIM_SCL, 0, 7)>;
low-power-enable;
};
};
spi1_default: spi1_default {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 2)>,
<NRF_PSEL(SPIM_MOSI, 0, 3)>,
<NRF_PSEL(SPIM_MISO, 0, 4)>;
};
};
spi1_sleep: spi1_sleep {
group1 {
psels = <NRF_PSEL(SPIM_SCK, 0, 2)>,
<NRF_PSEL(SPIM_MOSI, 0, 3)>,
<NRF_PSEL(SPIM_MISO, 0, 4)>;
low-power-enable;
};
};
};
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 410 |
```yaml
board:
name: pinetime_devkit0
vendor: pine64
socs:
- name: nrf52832
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
CONFIG_ARM_MPU=y
CONFIG_GPIO=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```unknown
# PineTime DevKit0 board configuration
if BOARD_PINETIME_DEVKIT0
config BT_CTLR
default BT
config INPUT
default y if LVGL
if FLASH
config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE
default 4096
endif # FLASH
endif # BOARD_PINETIME_DEVKIT0
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
/*
*
*
* DTS for Pine64 PineTime DevKit-0 board
* Further info: path_to_url
*
*/
/dts-v1/;
#include <nordic/nrf52832_qfaa.dtsi>
#include "pinetime_devkit0-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
model = "Pine64 PineTime DevKit0";
compatible = "pine64,pinetime-devkit0";
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,bt-mon-uart = &uart0;
zephyr,bt-c2h-uart = &uart0;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,display = &st7789v;
};
aliases {
led0 = &blled0; /* backlight low */
led1 = &blled1; /* backlight mid */
led2 = &blled2; /* backlight high */
led3 = &statusled; /* status led, may be not populated */
sw0 = &key_in; /* key in */
watchdog0 = &wdt0;
};
leds {
compatible = "gpio-leds";
blled0: bl_led_0 {
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
label = "Backlight Low";
};
blled1: bl_led_1 {
gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
label = "Backlight Medium";
};
blled2: bl_led_2 {
gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
label = "Backlight High";
};
statusled: led_3 {
gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
label = "Status Led";
};
};
buttons {
compatible = "gpio-keys";
key_in: button_0 {
gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
label = "Key in";
zephyr,code = <INPUT_KEY_0>;
};
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&cst816s>;
};
vbatt {
compatible = "voltage-divider";
io-channels = <&adc 7>;
output-ohms = <1000000>;
full-ohms = <(1000000 + 1000000)>;
};
mipi_dbi {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&spi1>;
dc-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; /* DET */
reset-gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; /* RESX reset */
write-only;
#address-cells = <1>;
#size-cells = <0>;
/* Sitronix ST7789V LCD */
st7789v: st7789v@1 {
compatible = "sitronix,st7789v";
reg = <1>;
mipi-max-frequency = <8000000>; /* 8MHz */
width = <240>;
height = <240>;
x-offset = <0>;
y-offset = <0>;
vcom = <0x19>;
gctrl = <0x35>;
vrhs = <0x12>;
vdvs = <0x20>;
mdac = <0x00>;
gamma = <0x01>;
colmod = <0x05>;
lcm = <0x2c>;
porch-param = [0c 0c 00 33 33];
cmd2en-param = [5a 69 02 01];
pwctrl1-param = [a4 a1];
pvgam-param = [D0 04 0D 11 13 2B 3F 54 4C 18 0D 0B 1F 23];
nvgam-param = [D0 04 0C 11 13 2C 3F 44 51 2F 1F 1F 20 23];
ram-param = [00 F0];
rgb-param = [CD 08 14];
mipi-mode = <MIPI_DBI_MODE_SPI_4WIRE>;
};
};
};
&adc {
status = "okay";
};
&uicr {
gpio-as-nreset;
};
&gpiote {
status = "okay";
};
&uicr {
nfct-pins-as-gpios;
};
&gpio0 {
status = "okay";
key-out {
gpio-hog;
gpios = <15 GPIO_ACTIVE_HIGH>;
output-high;
};
};
&uart0 {
compatible = "nordic,nrf-uart";
current-speed = <115200>;
status = "okay";
pinctrl-0 = <&uart0_default>;
pinctrl-1 = <&uart0_sleep>;
pinctrl-names = "default", "sleep";
};
&i2c0 {
compatible = "nordic,nrf-twim";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>; /* 400KHz */
/* BOSCH BMA421 Triaxial Acceleration Sensor (1000KHz) */
pinctrl-0 = <&i2c0_default>;
pinctrl-1 = <&i2c0_sleep>;
pinctrl-names = "default", "sleep";
bma421: bma421@18 {
compatible = "bosch,bma4xx";
reg = <0x18>;
int1-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
};
/* TianYiHeXin HRS3300 PPG Hear Rate Sensor (800KHz) */
hrs3300: hrs3300@44 {
compatible = "tian-yi-he-xin-hrs3300";
reg = <0x44>;
};
/* Hynitron CST816S Capacitive Touch Controller (400KHz) */
cst816s: cst816s@15 {
compatible = "hynitron,cst816s";
reg = <0x15>;
irq-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
rst-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
};
};
&spi1 {
compatible = "nordic,nrf-spi";
status = "okay";
cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>, <&gpio0 25 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
pinctrl-names = "default", "sleep";
xt25fb32: xt25fb32@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <8000000>; /* 8MHz */
jedec-id = [0b 40 16];
size = <DT_SIZE_M(32)>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* next firmware update */
slot1_partition: partition@0 {
label = "image-1";
reg = <0x00000000 0x74000>;
};
/* to be used in firmware */
storage_partition: partition@300000 {
label = "storage";
reg = <0x00300000 0x00100000>;
};
};
};
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* MCUboot bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0xc000>;
};
/* main firmware partition */
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000C000 0x74000>;
};
};
};
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,892 |
```restructuredtext
.. _boards-m5stack:
M5Stack
#######
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/m5stack/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
# the default ESP32 baud rate is not supported
board_runner_args(esp32 "--esp-baud-rate=1500000")
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 129 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_REGULATOR=y
CONFIG_GPIO=y
CONFIG_I2C=y
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```yaml
identifier: m5stickc_plus/esp32/procpu
name: M5StickC PLUS PROCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- gpio
- i2c
- spi
- watchdog
- uart
- pinmux
- nvs
- regulator
- display
testing:
ignore_tags:
- net
- bluetooth
vendor: m5stack
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _pinetime_devkit0:
Pine64 PineTime DevKit0
#######################
Overview
********
.. figure:: img/PineTime_leaflet.jpg
:align: center
:alt: Pine64 PineTime
PineTime leaflet (Credit: Pine64)
The Pine64 smartwatch, dubbed "PineTime", is a product of a community effort
for an open source smartwatch in collaboration with wearable RTOS and Linux
app developers/communities.
.. figure:: img/PineTime_DevKit0.jpg
:align: center
:alt: Pine64 PineTime
PineTime Dev Kit (Credit: Pine64)
Hardware
********
The PineTime is based on a Nordic NRF52832 chip and features:
- CPU: 64 MHz Cortex-M4 with FPU
- RAM: 64KB SRAM
- Flash: 512KB on board flash with additional 4MB SPI NOR XT25F32B
- Display: 1.3 inches (33mm), 240x240 pixels display with ST7789 driver
- Touchscreen: CST816S Capacitive Touch
- Battery: 170-180mAh 3.8V LiPo
- BMA421 Triaxial Acceleration Sensor
- HRS3300 PPG Heart Rate Sensor
- Vibration motor
PineTime schematics
========================
The `PineTime schematics`_ are available on the pine64 website. Below
is an overview of the NRF52 port assignment.
+----------------------+---------------------------------+-----------+
| NRF52 pins | Function | Direction |
+======================+=================================+===========+
| P0.00/XL1 | 32.768 kHz XL1 | |
+----------------------+---------------------------------+-----------+
| P0.01/XL2 | 32.768 kHz XL2 | |
+----------------------+---------------------------------+-----------+
| P0.02/AIN0 | SPI-SCK, LCD_SCK | OUT |
+----------------------+---------------------------------+-----------+
| P0.03/AIN1 | SPI-MOSI, LCD_SDI | OUT |
+----------------------+---------------------------------+-----------+
| P0.04/AIN2 | SPI-MISO | IN |
+----------------------+---------------------------------+-----------+
| P0.05/AIN3 | SPI-CE# (SPI-NOR) | OUT |
+----------------------+---------------------------------+-----------+
| P0.06 | BMA421-SDA, HRS3300-SDA, TP-SDA | I/O |
+----------------------+---------------------------------+-----------+
| P0.07 | BMA421-SCL, HRS3300-SCL, TP-SCL | OUT |
+----------------------+---------------------------------+-----------+
| P0.08 | BMA421-INT | IN |
+----------------------+---------------------------------+-----------+
| P0.09/NFC1 | LCD_DET | OUT |
+----------------------+---------------------------------+-----------+
| P0.10/NFC2 | TP_RESET | OUT |
+----------------------+---------------------------------+-----------+
| P0.11 | | |
+----------------------+---------------------------------+-----------+
| P0.12 | CHARGE INDICATION | IN |
+----------------------+---------------------------------+-----------+
| P0.13 | PUSH BUTTON_IN | IN |
+----------------------+---------------------------------+-----------+
| P0.14/TRACEDATA3 | LCD_BACKLIGHT_LOW | OUT |
+----------------------+---------------------------------+-----------+
| P0.15/TRACEDATA2 | PUSH BUTTON_OUT | OUT |
+----------------------+---------------------------------+-----------+
| P0.16/TRACEDATA1 | VIBRATOR OUT | OUT |
+----------------------+---------------------------------+-----------+
| P0.17 | | |
+----------------------+---------------------------------+-----------+
| P0.18/TRACEDATA0/SWO | LCD_RS OUT | |
+----------------------+---------------------------------+-----------+
| P0.19 | POWER PRESENCE INDICATION | IN |
+----------------------+---------------------------------+-----------+
| P0.20/TRACECLK | | |
+----------------------+---------------------------------+-----------+
| P0.21/nRESET | | |
+----------------------+---------------------------------+-----------+
| P0.22 | LCD_BACKLIGHT_MID | OUT |
+----------------------+---------------------------------+-----------+
| P0.23 | LCD_BACKLIGHT_HIGH | OUT |
+----------------------+---------------------------------+-----------+
| P0.24 | 3V3 POWER CONTROL | OUT |
+----------------------+---------------------------------+-----------+
| P0.25 | LCD_CS | OUT |
+----------------------+---------------------------------+-----------+
| P0.26 | LCD_RESET | OUT |
+----------------------+---------------------------------+-----------+
| P0.27 | STATUS LED (NOT STAFF) | OUT |
+----------------------+---------------------------------+-----------+
| P0.28/AIN4 | TP_INT | IN |
+----------------------+---------------------------------+-----------+
| P0.29/AIN5 | | |
+----------------------+---------------------------------+-----------+
| P0.30/AIN6 | HRS3300-TEST | IN |
+----------------------+---------------------------------+-----------+
| P0.31/AIN7 | BATTERY VOLTAGE (Analog) | IN |
+----------------------+---------------------------------+-----------+
Building
********
In order to get started with Zephyr on the PineTime, you can use the
basic button sample:
.. zephyr-app-commands::
:zephyr-app: samples/basic/button
:board: pinetime_devkit0
:goals: build
Programming and Debugging
*************************
The PineTime Dev Kit comes with the back not glued down to allow it to be
easily reprogrammed.
The kit does not include a hardware programmer, but existing debuggers
supporting SWD can be used.
These are the necessary steps for debugging:
- Unlock the device
- Upload new software
- Run a debugger
More infos to be found in the `Wiki Reprogramming the PineTime`_ page.
Debugger connection
===================
The dev kits have exposed SWD pins for flashing and debugging.
Only a few devs have soldered to these pins, most just use friction to make
contact with the programming cable.
The pinout is:
.. figure:: img/PineTime_SWD_location.jpg
:align: center
:alt: PineTime SWD location
Unlocking the Flash memory
==========================
Unlocking the device is a one-time action that is needed to enable to debug
port and provide full access to the device. This will erase all existing
software from the internal flash.
**Note: PineTime watches shipped after 20 Sep 2020 do not require unlocking. They are shipped unlocked.**
.. code-block:: console
$ nrfjprog -f NRF52 --recover
Flashing
========
Using nrfjprog, flashing the PineTime is done with the command:
.. code-block:: console
$ nrfjprog -f NRF52 --program firmware.hex --sectorerase
Debugging
=========
Using Segger Ozone debugger, debugging and flashing is made easy.
Simply load the .elf file containing the final firmware and
setup the debugger to use SWD over USB for the chip nRF52832_xxAA.
This setup can be done using the menu Tools/J-Link Settings. or by directly
typing the following in the debugger console:
.. code-block:: console
$ Project.SetDevice ("nRF52832_xxAA");
$ Project.SetHostIF ("USB", "");
$ Project.SetTargetIF ("SWD");
$ Project.SetTIFSpeed ("4 MHz");
$ File.Open ("path/to/your/build/zephyr/zephyr.elf");
References
**********
.. target-notes::
.. _Pine64 PineTime presentation:
path_to_url
.. _Pine64 PineTime wiki page:
path_to_url
.. _Pine64 forum:
path_to_url
.. _PineTime schematics:
path_to_url
.. _Wiki Reprogramming the PineTime:
path_to_url
``` | /content/code_sandbox/boards/pine64/pinetime_devkit0/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,789 |
```unknown
# M5StickC PLUS board configuration
config BOARD_M5STICKC_PLUS
select SOC_ESP32_PICO_D4
select SOC_ESP32_PROCPU if BOARD_M5STICKC_PLUS_ESP32_PROCPU
select SOC_ESP32_APPCPU if BOARD_M5STICKC_PLUS_ESP32_APPCPU
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```yaml
board:
name: m5stickc_plus
vendor: m5stack
socs:
- name: esp32
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```yaml
identifier: m5stickc_plus/esp32/appcpu
name: M5StickC PLUS APPCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- uart
testing:
ignore_tags:
- net
- bluetooth
- flash
- cpp
- posix
- watchdog
- logging
- kernel
- pm
- gpio
- crypto
- eeprom
- heap
- cmsis_rtos
- jwt
- zdsp
vendor: m5stack
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32/esp32_appcpu.dtsi>
/ {
model = "M5StickC Plus APPCPU";
compatible = "espressif,esp32";
chosen {
zephyr,sram = &sram0;
zephyr,ipc_shm = &shm0;
zephyr,ipc = &ipm0;
};
};
&ipm0 {
status = "okay";
};
&trng0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 60kB for the bootloader */
boot_partition: partition@1000 {
label = "mcuboot";
reg = <0x00001000 0x0000F000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 403 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
&pinctrl {
uart0_tx_gpio1: uart0_tx_gpio1 {
pinmux = <UART0_TX_GPIO1>;
output-high;
};
uart0_rx_gpio3: uart0_rx_gpio3 {
pinmux = <UART0_RX_GPIO3>;
bias-pull-up;
};
spim2_miso_gpio12: spim2_miso_gpio12 {
pinmux = <SPIM2_MISO_GPIO12>;
};
spim2_mosi_gpio11: spim2_mosi_gpio11 {
pinmux = <SPIM2_MOSI_GPIO11>;
output-low;
};
spim2_sclk_gpio14: spim2_sclk_gpio14 {
pinmux = <SPIM2_SCLK_GPIO14>;
};
spim2_csel_gpio16: spim2_csel_gpio16 {
pinmux = <SPIM2_CSEL_GPIO16>;
};
spim3_default: spim3_default {
group1 {
pinmux = <SPIM3_MISO_GPIO36>,
<SPIM3_SCLK_GPIO13>,
<SPIM3_CSEL_GPIO5>;
};
group2 {
pinmux = <SPIM3_MOSI_GPIO15>;
output-low;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO21>,
<I2C0_SCL_GPIO22>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
};
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 408 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32/esp32_pico_d4.dtsi>
#include "m5stickc_plus-pinctrl.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/regulator/axp192.h>
#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
/ {
model = "M5StickC Plus PROCPU";
compatible = "m5stack,m5stickc-plus";
aliases {
led0 = &red_led;
sw0 = &user_button_0;
sw1 = &user_button_1;
uart-0 = &uart0;
i2c-0 = &i2c0;
watchdog0 = &wdt0;
accel0 = &mpu6886;
rtc = &bm8563;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,rtc = &bm8563;
zephyr,display = &st7789v;
zephyr,bt-hci = &esp32_bt_hci;
};
leds {
compatible = "gpio-leds";
red_led: led_0 {
gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
label = "Red - LED0";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button_0: button_0 {
label = "User button 0";
gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
user_button_1: button_1 {
label = "User button 1";
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_1>;
};
};
mipi_dbi {
compatible = "zephyr,mipi-dbi-spi";
spi-dev = <&spi3>;
dc-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
write-only;
#address-cells = <1>;
#size-cells = <0>;
st7789v: st7789v@0 {
compatible = "sitronix,st7789v";
reg = <0>;
mipi-max-frequency = <20000000>;
width = <135>;
height = <240>;
x-offset = <53>;
y-offset = <40>;
vcom = <0x28>;
gctrl = <0x35>;
vrhs = <0x10>;
vdvs = <0x20>;
mdac = <0x00>;
gamma = <0x01>;
colmod = <0x55>;
lcm = <0x2c>;
porch-param = [0c 0c 00 33 33];
cmd2en-param = [5a 69 02 00];
pwctrl1-param = [a4 a1];
pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17];
nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e];
ram-param = [00 F0];
rgb-param = [40 02 14];
mipi-mode = <MIPI_DBI_MODE_SPI_4WIRE>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>;
pinctrl-names = "default";
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
/* IMU MPU-6886, RTC BM8563, PMU AXP192 */
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>;
scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>;
pinctrl-0 = <&i2c0_default>;
scl-timeout-us = <0>;
pinctrl-names = "default";
axp192_pmic: axp192@34 {
compatible = "x-powers,axp192";
reg = <0x34>;
status = "okay";
axp192_regulator: axp192_regulator {
compatible = "x-powers,axp192-regulator";
status = "okay";
vdd_mcu: DCDC1 {
regulator-init-microvolt = <3350000>;
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3400000>;
regulator-initial-mode = <AXP192_DCDC_MODE_AUTO>;
regulator-boot-on;
regulator-always-on;
};
lcd_bl: LDO2 {
regulator-init-microvolt = <2800000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
};
lcd_logic: LDO3 {
regulator-init-microvolt = <3000000>;
};
};
axp192_gpio: axp192_gpio {
compatible = "x-powers,axp192-gpio";
gpio-controller;
#gpio-cells = <2>;
ngpios = <6>;
status = "okay";
};
};
mpu6886: mpu6886@68 {
status = "okay";
compatible = "invensense,mpu6050";
reg = <0x68>;
};
bm8563: bm8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
status = "okay";
};
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim2_miso_gpio12 &spim2_mosi_gpio11
&spim2_sclk_gpio14 &spim2_csel_gpio16>;
pinctrl-names = "default";
};
/* LCD TFT 1.14", 135x240 px, ST7789v2 */
&spi3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim3_default>;
pinctrl-names = "default";
};
&timer0 {
status = "okay";
};
&timer1 {
status = "okay";
};
&timer2 {
status = "okay";
};
&timer3 {
status = "okay";
};
&trng0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 60kB for the bootloader */
boot_partition: partition@1000 {
label = "mcuboot";
reg = <0x00001000 0x0000F000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&esp32_bt_hci {
status = "okay";
};
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,920 |
```unknown
# M5StickC PLUS board configuration
if BOARD_M5STICKC_PLUS_ESP32_PROCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
config GPIO_HOGS_INIT_PRIORITY
default 70
config MFD_INIT_PRIORITY
default 70
config REGULATOR_AXP192_INIT_PRIORITY
default 71
config GPIO_AXP192_INIT_PRIORITY
default 72
config REGULATOR_FIXED_INIT_PRIORITY
default 75
endif # BOARD_M5STICKC_PLUS_ESP32_PROCPU
if BOARD_M5STICKC_PLUS_ESP32_APPCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
default 256
endif # BOARD_M5STICKC_PLUS_ESP32_APPCPU
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 176 |
```ini
set ESP_RTOS none
set ESP32_ONLYCPU 1
source [find interface/ftdi/esp32_devkitj_v1.cfg]
source [find target/esp32.cfg]
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO43>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO44>;
bias-pull-up;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO13>,
<I2C0_SCL_GPIO15>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
i2c1_default: i2c1_default {
group1 {
pinmux = <I2C1_SDA_GPIO11>,
<I2C1_SCL_GPIO12>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_SCLK_GPIO6>,
<SPIM2_CSEL_GPIO7>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO5>;
output-low;
};
};
spim3_default: spim3_default {
group1 {
pinmux = <SPIM3_MOSI_GPIO21>;
output-low;
};
};
ledc0_default: ledc0_default {
group1 {
pinmux = <LEDC_CH0_GPIO9>; /* lcd backlight */
output-enable;
};
group2 {
pinmux = <LEDC_CH1_GPIO3>; /* beeper */
output-enable;
};
};
mcpwm0_default: mcpwm0_default {
group1 {
pinmux = <MCPWM0_OUT0A_GPIO9>; /* lcd backlight */
output-enable;
};
group2 {
pinmux = <MCPWM0_OUT1A_GPIO3>;
output-enable;
};
};
};
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 505 |
```unknown
# M5Stack StampS3 board configuration
config BOARD_M5STACK_STAMPS3
select SOC_ESP32S3_FN8
select SOC_ESP32S3_PROCPU if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU
select SOC_ESP32S3_APPCPU if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```restructuredtext
.. _m5stickc_plus:
M5StickC PLUS
#############
Overview
********
M5StickC PLUS, one of the core devices in M5Stacks product series, is an ESP32-based development board.
M5StickC PLUS features the following integrated components:
- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi)
- ST7789v2, LCD TFT 1.14", 135x240 px screen
- IMU MPU-6886
- SPM-1423 microphone
- RTC BM8563
- PMU AXP192
- 120 mAh 3,7 V battery
Some of the ESP32 I/O pins are broken out to the board's pin headers for easy access.
Functional Description
**********************
The following table below describes the key components, interfaces, and controls
of the M5StickC PLUS board.
.. _ST7789v2: path_to_url
.. _MPU-6886: path_to_url
.. _ESP32-PICO-D4: path_to_url
.. _SPM-1423: path_to_url
+------------------+your_sha256_hash---------+
| Key Component | Description |
+==================+=========================================================================+
| 32.768 kHz RTC | External precision 32.768 kHz crystal oscillator serves as a clock with |
| | low-power consumption while the chip is in Deep-sleep mode. |
+------------------+your_sha256_hash---------+
| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth |
| module | functionalities and integrates a 4-MB SPI flash. |
+------------------+your_sha256_hash---------+
| Diagnostic LED | One user LED connected to the GPIO pin. |
+------------------+your_sha256_hash---------+
| USB Port | USB interface. Power supply for the board as well as the |
| | communication interface between a computer and the board. |
| | Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 |
+------------------+your_sha256_hash---------+
| Power Switch | Power on/off button. |
+------------------+your_sha256_hash---------+
| A/B user buttons | Two push buttons intended for any user use. |
+------------------+your_sha256_hash---------+
| LCD screen | Built-in LCD TFT display \(`ST7789v2`_, 1.14", 135x240 px\) controlled |
| | by the SPI interface |
+------------------+your_sha256_hash---------+
| MPU-6886 | The `MPU-6886`_ is a 6-axis MotionTracking device that combines a |
| | 3-axis gyroscope and a 3-axis accelerometer. |
+------------------+your_sha256_hash---------+
| Built-in | The `SPM-1423`_ I2S driven microphone. |
| microphone | |
+------------------+your_sha256_hash---------+
Start Application Development
*****************************
Before powering up your M5StickC PLUS, please make sure that the board is in good
condition with no obvious signs of damage.
System requirements
===================
Prerequisites
-------------
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
*******************
ESP-IDF bootloader
==================
The board is using the ESP-IDF bootloader as the default 2nd stage bootloader.
It is build as a subproject at each application build. No further attention
is expected from the user.
MCUboot bootloader
==================
User may choose to use MCUboot bootloader instead. In that case the bootloader
must be build (and flash) at least once.
There are two options to be used when building an application:
1. Sysbuild
2. Manual build
.. note::
User can select the MCUboot bootloader by adding the following line
to the board default configuration file.
.. code:: cfg
CONFIG_BOOTLOADER_MCUBOOT=y
Sysbuild
========
The sysbuild makes possible to build and flash all necessary images needed to
bootstrap the board with the ESP32 SoC.
To build the sample application using sysbuild use the command:
.. zephyr-app-commands::
:tool: west
:app: samples/hello_world
:board: m5stickc_plus
:goals: build
:west-args: --sysbuild
:compact:
By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
images. But it can be configured to create other kind of images.
Build directory structure created by sysbuild is different from traditional
Zephyr build. Output is structured by the domain subdirectories:
.. code-block::
build/
hello_world
zephyr
zephyr.elf
zephyr.bin
mcuboot
zephyr
zephyr.elf
zephyr.bin
domains.yaml
.. note::
With ``--sysbuild`` option the bootloader will be re-build and re-flash
every time the pristine build is used.
For more information about the system build please read the :ref:`sysbuild` documentation.
Manual build
============
During the development cycle, it is intended to build & flash as quickly possible.
For that reason, images can be build one at a time using traditional build.
The instructions following are relevant for both manual build and sysbuild.
The only difference is the structure of the build directory.
.. note::
Remember that bootloader (MCUboot) needs to be flash at least once.
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: m5stickc_plus/esp32/procpu
:goals: build
The usual ``flash`` target will work with the ``m5stickc_plus`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: m5stickc_plus/esp32/procpu
:goals: flash
The default baud rate for the M5StickC PLUS is set to 1500000bps. If experiencing issues when flashing,
try using different values by using ``--esp-baud-rate <BAUD>`` option during
``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
You can also open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! m5stickc_plus
Debugging
*********
M5StickC PLUS debugging is not supported due to pinout limitations.
Related Documents
*****************
- `M5StickC PLUS schematic <path_to_url`_ (WEBP)
- `ESP32-PICO-D4 Datasheet <path_to_url`_ (PDF)
- `M5StickC PLUS docs <path_to_url`_
- `ESP32 Datasheet <path_to_url`_ (PDF)
- `ESP32 Hardware Reference <path_to_url`_
``` | /content/code_sandbox/boards/m5stack/m5stickc_plus/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,651 |
```yaml
identifier: m5stack_stamps3/esp32s3/procpu
name: M5Stack StampS3 PROCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- gpio
- i2c
- spi
- watchdog
- uart
- pwm
- pinmux
- nvs
testing:
ignore_tags:
- net
- bluetooth
vendor: m5stack
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 105 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32s3/esp32s3_fn8.dtsi>
#include "m5stack_stamps3-pinctrl.dtsi"
#include "m5stack_stamps3_connectors.dtsi"
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <dt-bindings/led/led.h>
#include <dt-bindings/led/worldsemi_ws2812c.h>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "M5Stack StampS3 PROCPU";
compatible = "m5stack,stamps3";
chosen {
zephyr,sram = &sram0;
zephyr,console = &usb_serial;
zephyr,shell-uart = &usb_serial;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,bt-hci = &esp32_bt_hci;
};
aliases {
sw0 = &user_button_0;
watchdog0 = &wdt0;
//pwm-0 = &ledc0;
i2c-0 = &i2c0;
led-strip = &status_rgb_led;
};
gpio_keys {
compatible = "gpio-keys";
/* This is the button that's underneath the LCD display */
user_button_0: button_0 {
label = "User button 0";
gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
};
&usb_serial {
status = "okay";
};
&uart0 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart0_default>;
pinctrl-names = "default";
};
&i2c0 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c0_default>;
pinctrl-names = "default";
};
&i2c1 {
status = "okay";
clock-frequency = <I2C_BITRATE_STANDARD>;
pinctrl-0 = <&i2c1_default>;
pinctrl-names = "default";
};
&trng0 {
status = "okay";
};
&mcpwm0 {
status = "okay";
pinctrl-0 = <&mcpwm0_default>;
pinctrl-names = "default";
prescale = <255>;
prescale-timer0 = <100>;
prescale-timer1 = <100>;
};
&ledc0 {
pinctrl-0 = <&ledc0_default>;
pinctrl-names = "default";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
channel0@0 {
reg = <0x0>;
timer = <0>;
};
channel0@1 {
reg = <0x1>;
timer = <0>;
};
};
&spi2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-0 = <&spim2_default>;
pinctrl-names = "default";
};
&spi3 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
line-idle-low;
pinctrl-0 = <&spim3_default>;
pinctrl-names = "default";
status_rgb_led: ws2812@0 {
compatible = "worldsemi,ws2812-spi";
reg = <0x0>;
spi-max-frequency = <WS2812C_SPI_FREQ>;
chain-length = <1>;
color-mapping = <LED_COLOR_ID_GREEN>,
<LED_COLOR_ID_RED>,
<LED_COLOR_ID_BLUE>;
spi-one-frame = <WS2812C_ONE_FRAME>;
spi-zero-frame = <WS2812C_ZERO_FRAME>;
reset-delay = <250>;
};
};
&gpio0 {
status = "okay";
};
&gpio1 {
status = "okay";
};
&wdt0 {
status = "okay";
};
&timer0 {
status = "okay";
};
&timer1 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x0000F000>;
read-only;
};
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
&esp32_bt_hci {
status = "okay";
};
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,181 |
```unknown
/*
*
*/
/dts-v1/;
#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
/ {
model = "M5Stack StampS3 APPCPU";
compatible = "espressif,esp32s3";
chosen {
zephyr,sram = &sram0;
zephyr,ipc_shm = &shm0;
zephyr,ipc = &ipm0;
};
};
&trng0 {
status = "okay";
};
&ipm0 {
status = "okay";
};
&flash0 {
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Reserve 64kB for the bootloader */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 0x00010000>;
read-only;
};
/* Reserve 1024kB for the application in slot 0 */
slot0_partition: partition@10000 {
label = "image-0";
reg = <0x00010000 0x00100000>;
};
/* Reserve 1024kB for the application in slot 1 */
slot1_partition: partition@110000 {
label = "image-1";
reg = <0x00110000 0x00100000>;
};
/* Reserve 256kB for the scratch partition */
scratch_partition: partition@210000 {
label = "image-scratch";
reg = <0x00210000 0x00040000>;
};
storage_partition: partition@250000 {
label = "storage";
reg = <0x00250000 0x00006000>;
};
};
};
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 408 |
```yaml
board:
name: m5stack_stamps3
vendor: m5stack
socs:
- name: esp32s3
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_GPIO=y
CONFIG_CONSOLE=y
CONFIG_PWM=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```unknown
# M5Stack StampS3 board configuration
if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
config KERNEL_MEM_POOL
default y
endif # BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU
if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU
config HEAP_MEM_POOL_ADD_SIZE_BOARD
default 256
endif # BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CLOCK_CONTROL=y
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 15 |
```unknown
/*
*/
/ {
m5stack_stamps3_header: m5stack_stamps3_header {
compatible = "m5stack,stamps3-header";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map =
<0 0 &gpio0 1 0>, /* GPIO/AIN */
<1 0 &gpio0 2 0>, /* GPIO/AIN */
<2 0 &gpio0 3 0>, /* GPIO/AIN/CLKOUT1-3 */
<3 0 &gpio0 4 0>, /* GPIO/AIN */
<4 0 &gpio0 5 0>, /* GPIO/AIN/SPI2-MOSI */
<5 0 &gpio0 6 0>, /* GPIO/AIN/SPI2-CLK */
<6 0 &gpio0 7 0>, /* GPIO/AIN/SPI2-CS */
<7 0 &gpio0 8 0>, /* GPIO/AIN */
<8 0 &gpio0 9 0>, /* GPIO/AIN/CLKOUT1-4 */
<9 0 &gpio0 10 0>, /* GPIO/AIN */
/* 10 GND */
<11 0 &gpio0 11 0>, /* GPIO/AIN/SDA1 */
/* 11 5V */
<12 0 &gpio0 12 0>, /* GPIO/AIN/SCL1 */
<14 0 &gpio0 13 0>, /* GPIO/AIN/SDA0 */
<15 0 &gpio0 14 0>, /* GPIO/AIN */
<16 0 &gpio0 15 0>, /* GPIO/AIN/SCL0 */
/* 17 GND */
<18 0 &gpio1 7 0>, /* GPIO/CLKOUT0-0 */
<19 0 &gpio0 0 0>, /* GPIO */
<20 0 &gpio1 8 0>, /* GPIO/CLKOUT0-1 */
/* 21 EN */
<22 0 &gpio1 9 0>, /* GPIO/CLKOUT1-0 */
<23 0 &gpio1 12 0>, /* GPIO/CLKOUT1-1/RXD0 */
<24 0 &gpio1 10 0>, /* GPIO */
<25 0 &gpio1 11 0>, /* GPIO/CLKOUT1.2/TXD0 */
<26 0 &gpio1 14 0>; /* GPIO */
/* 27 3V3 */
};
};
m5stack_stamps3_uart0: &uart0 {};
m5stack_stamps3_i2c0: &i2c0 {};
m5stack_stamps3_i2c1: &i2c1 {};
m5stack_stamps3_clkout0: &mcpwm0 {};
m5stack_stamps3_spilcd: &spi2 {};
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_connectors.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 720 |
```yaml
identifier: m5stack_stamps3/esp32s3/appcpu
name: M5Stack StampS3 APPCPU
type: mcu
arch: xtensa
toolchain:
- zephyr
supported:
- uart
testing:
ignore_tags:
- net
- bluetooth
- flash
- cpp
- posix
- watchdog
- logging
- kernel
- pm
- gpio
- crypto
- eeprom
- heap
- cmsis_rtos
- jwt
- zdsp
vendor: m5stack
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```cmake
if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
set(OPENOCD OPENOCD-NOTFOUND)
endif()
find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/m5stack/stamp_c3/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 102 |
```unknown
choice BOOTLOADER
default BOOTLOADER_MCUBOOT
endchoice
choice BOOT_SIGNATURE_TYPE
default BOOT_SIGNATURE_TYPE_NONE
endchoice
``` | /content/code_sandbox/boards/m5stack/stamp_c3/Kconfig.sysbuild | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: stamp_c3
name: M5Stack STAMP-C3
type: mcu
arch: riscv
toolchain:
- zephyr
supported:
- gpio
- i2c
- spi
- uart
- watchdog
testing:
ignore_tags:
- net
- bluetooth
vendor: m5stack
``` | /content/code_sandbox/boards/m5stack/stamp_c3/stamp_c3.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# M5Stack STAMP-C3 board configuration
config BOARD_STAMP_C3
select SOC_ESP32C3_FX4
``` | /content/code_sandbox/boards/m5stack/stamp_c3/Kconfig.stamp_c3 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_GPIO=y
``` | /content/code_sandbox/boards/m5stack/stamp_c3/stamp_c3_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 27 |
```yaml
board:
name: stamp_c3
vendor: m5stack
socs:
- name: esp32c3
``` | /content/code_sandbox/boards/m5stack/stamp_c3/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```unknown
/*
*
*/
#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
#include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
&pinctrl {
uart0_default: uart0_default {
group1 {
pinmux = <UART0_TX_GPIO21>;
output-high;
};
group2 {
pinmux = <UART0_RX_GPIO20>;
bias-pull-up;
};
};
spim2_default: spim2_default {
group1 {
pinmux = <SPIM2_MISO_GPIO5>,
<SPIM2_SCLK_GPIO4>,
<SPIM2_CSEL_GPIO7>;
};
group2 {
pinmux = <SPIM2_MOSI_GPIO6>;
output-low;
};
};
i2c0_default: i2c0_default {
group1 {
pinmux = <I2C0_SDA_GPIO8>,
<I2C0_SCL_GPIO9>;
bias-pull-up;
drive-open-drain;
output-high;
};
};
twai_default: twai_default {
group1 {
pinmux = <TWAI_TX_GPIO0>,
<TWAI_RX_GPIO1>;
};
};
};
``` | /content/code_sandbox/boards/m5stack/stamp_c3/stamp_c3-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 312 |
```unknown
# M5Stack STAMP-C3 board configuration
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 65535 if WIFI && BT
default 51200 if WIFI
default 40960 if BT
default 4096
``` | /content/code_sandbox/boards/m5stack/stamp_c3/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 50 |
```restructuredtext
.. _m5stack_stamps3:
M5Stack StampS3
###############
Overview
********
M5Stack StampS3 is an ESP32-based development board from M5Stack.
It features the following integrated components:
- ESP32-S3FN8 chip (240MHz dual core)
- 512KB SRAM
- 384KB ROM
- 8MB Flash
- Wi-Fi
- Bluetooth
- User-Button
.. figure:: img/m5stack_stamps3.webp
:align: center
:alt: M5Stack StampS3
:width: 400 px
M5Stack StampS3 module
Functional Description
**********************
The following table below describes the key components, interfaces, and controls
of the M5Stack StampS3 module.
+---------------+your_sha256_hash-+-----------+
| Key Component | Description | Status |
+===============+=================================================================+===========+
| ESP32-S3FN8 | This MPU-ESP32S3 module provides complete Wi-Fi and Bluetooth | supported |
| module | functionalities and integrates a 8MB flash. | |
+---------------+your_sha256_hash-+-----------+
| Status LED | One user LED connected via :dtcompatible:`worldsemi,ws2812-spi` | supported |
| | interface (``led-strip``). | |
+---------------+your_sha256_hash-+-----------+
| USB Port | USB interface. Power supply for the board as well as the | supported |
| | communication interface between a computer and the board. | |
+---------------+your_sha256_hash-+-----------+
| User button | User button (``sw0``) | supported |
+---------------+your_sha256_hash-+-----------+
Main connector header
=====================
The Zephyr m5stack_stamps3 board can be used on various applications. It
therefore publishes a header definition to be used in different shields:
:dtcompatible:`m5stack,stamps3-header`.
.. figure:: img/m5stack_stamps3_header.webp
:align: center
:alt: M5Stack StampS3 Header
:width: 400 px
M5Stack StampS3 connector header
Following interfaces are being exported for this header:
- ``m5stack_stamps3_clkout0``: PWM output with 2 channels (0 and 2).
- ``m5stack_stamps3_spilcd``: SPI interface for interfacing LCDs. Consists of a
CLK, MOSI and CS signal.
- ``m5stack_stamps3_i2c0`` and ``m5stack_stamps3_i2c1``: I2C interfaces (SDA, SCL).
- ``m5stack_stamps3_uart0``: UART interface (RXD, TXD).
- ``m5stack_stamps3_header``: All GPIOs are of course accessible via main header
definition.
+-----+-----------------------------------------+-----+---------------------------------+
| Pin | Functions | Pin | Functions |
+=====+=========================================+=====+=================================+
| 1 | | | |
+-----+-----------------------------------------+-----+---------------------------------+
| 2 | | | |
+-----+-----------------------------------------+-----+---------------------------------+
| 3 | ``m5stack_stamps3_clkout0`` - Channel 0 | | |
+-----+-----------------------------------------+-----+---------------------------------+
| 4 | | | |
+-----+-----------------------------------------+-----+---------------------------------+
| 5 | ``m5stack_stamps3_spilcd`` - MOSI | | |
+-----+-----------------------------------------+-----+---------------------------------+
| 6 | ``m5stack_stamps3_spilcd`` - CLK | | |
+-----+-----------------------------------------+-----+---------------------------------+
| 7 | ``m5stack_stamps3_spilcd`` - CS | 28 | **3V3** |
+-----+-----------------------------------------+-----+---------------------------------+
| 8 | | 27 | ``m5stack_stamps3_uart0`` - TXD |
+-----+-----------------------------------------+-----+---------------------------------+
| 9 | ``m5stack_stamps3_clkout0`` - Channel 2 | 26 | |
+-----+-----------------------------------------+-----+---------------------------------+
| 10 | | 25 | ``m5stack_stamps3_uart0`` - RXD |
+-----+-----------------------------------------+-----+---------------------------------+
| 11 | **GND** | 24 | |
+-----+-----------------------------------------+-----+---------------------------------+
| 12 | ``m5stack_stamps3_i2c1`` - SDA | 23 | |
+-----+-----------------------------------------+-----+---------------------------------+
| 13 | **5V** | 22 | **EN** |
+-----+-----------------------------------------+-----+---------------------------------+
| 14 | ``m5stack_stamps3_i2c1`` - SCL | 21 | |
+-----+-----------------------------------------+-----+---------------------------------+
| 15 | ``m5stack_stamps3_i2c0`` - SDA | 20 | |
+-----+-----------------------------------------+-----+---------------------------------+
| 16 | | 19 | |
+-----+-----------------------------------------+-----+---------------------------------+
| 17 | ``m5stack_stamps3_i2c0`` - SCL | 18 | **GND** |
+-----+-----------------------------------------+-----+---------------------------------+
Power supply
============
M5Stack StampS3 requires a single 5V input power supply. The module internally
features a DCDC (MUN3CAD01-SC) to generate the 3.3V needed for the MCU.
The **EN** signal (Pin 22) is an active low signal to enable the **3V3** power
supply. If this pin is pulled low this main 3.3V power supply for the MCU will be
deactivated. It is internally equipped with a pull-up and can hence be left open
if unused.
Start Application Development
*****************************
Before powering up your M5Stack StampS3, please make sure that the board is in good
condition with no obvious signs of damage.
System requirements
===================
Prerequisites
-------------
Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
below to retrieve those files.
.. code-block:: console
west blobs fetch hal_espressif
.. note::
It is recommended running the command above after :file:`west update`.
Building & Flashing
-------------------
Build and flash applications as usual (see :ref:`build_an_application` and
:ref:`application_run` for more details).
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: m5stack_stamps3/esp32s3/procpu
:goals: build
The usual ``flash`` target will work with the ``m5stack_stamps3`` board
configuration. Here is an example for the :ref:`hello_world`
application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: m5stack_stamps3/esp32s3/procpu
:goals: flash
The baud rate of 921600bps is set by default. If experiencing issues when flashing,
try using different values by using ``--esp-baud-rate <BAUD>`` option during
``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
You can also open the serial monitor using the following command:
.. code-block:: shell
west espressif monitor
After the board has automatically reset and booted, you should see the following
message in the monitor:
.. code-block:: console
***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
Hello World! m5stack_stamps3
Debugging
---------
M5Stack StampS3 exports a JTAG-interface via Pins 19 (MTCK), 21 (MTDO), 23
(MTDI), 25 (MTMS).
.. note::
Please note that additional JTAG equipment is needed to utilize JTAG. Refer to
the ESP32S3 datasheet and the M5Stack StampS3 documentation for details.
Related Documents
*****************
- `M5Stack StampS3 schematic <path_to_url`_
- `M5Stack StampS3 <path_to_url`_
- `ESP32 Datasheet <path_to_url`_ (PDF)
- `ESP32 Hardware Reference <path_to_url`_
``` | /content/code_sandbox/boards/m5stack/m5stack_stamps3/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,903 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.