text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```cmake
board_runner_args(jlink "--device=STM32F746NG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32f746g_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f7/stm32f746Xg.dtsi>
#include <st/f7/stm32f746nghx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
/ {
model = "STMicroelectronics STM32F746G DISCOVERY board";
compatible = "st,stm32f746g-disco";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,dtcm = &dtcm;
zephyr,flash-controller = &n25q128a1;
zephyr,display = <dc;
};
leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
lvgl_pointer {
compatible = "zephyr,lvgl-pointer-input";
input = <&ft5336>;
};
sdram1: sdram@c0000000 {
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xc0000000 DT_SIZE_M(16)>;
zephyr,memory-region = "SDRAM1";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
};
aliases {
led0 = &green_led_1;
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&pll {
div-m = <25>;
mul-n = <432>;
div-p = <2>;
div-q = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(216)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_ph7 &i2c3_sda_ph8>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
ft5336: ft5336@38 {
compatible = "focaltech,ft5336";
reg = <0x38>;
int-gpios = <&gpioi 13 0>;
};
};
&spi2 {
pinctrl-0 = <&spi2_sck_pi1 &spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
cs-gpios = <&gpioa 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart6 {
pinctrl-0 = <&usart6_tx_pc6 &usart6_rx_pc7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch1_pb4>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
backup_regs {
status = "okay";
};
};
&sdmmc1 {
status = "okay";
pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
};
&mac {
status = "okay";
pinctrl-0 = <ð_mdc_pc1
ð_rxd0_pc4
ð_rxd1_pc5
ð_ref_clk_pa1
ð_mdio_pa2
ð_crs_dv_pa7
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pg14>;
pinctrl-names = "default";
};
&quadspi {
pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb6
&quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12
&quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>;
pinctrl-names = "default";
status = "okay";
n25q128a1: qspi-nor-flash@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(16)>; /* 128 Mbits */
qspi-max-frequency = <72000000>;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
slot1_partition: partition@0 {
label = "image-1";
reg = <0x00000000 DT_SIZE_K(640)>;
};
storage_partition: partition@a0000 {
label = "storage";
reg = <0x000a0000 DT_SIZE_M(15)>;
};
};
};
};
&fmc {
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke0_pc3
&fmc_sdne0_ph3 &fmc_sdnras_pf11 &fmc_sdncas_pg15
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
&fmc_d15_pd10>;
pinctrl-names = "default";
status = "okay";
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <8>;
mode-register = <0x220>;
/*
* Auto refresh command shall be issued every 15.625 us
* and is calculated as ((15.625 * SDRAM_CLK_MHZ) - 20)
* Note: SDRAM_CLK_MHZ = HCLK_MHZ / 2 (108 MHz)
*/
refresh-rate = <1667>;
bank@0 {
reg = <0>;
st,sdram-control = <STM32_FMC_SDRAM_NC_8
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0>;
st,sdram-timing = <2 6 4 6 2 2 2>;
};
};
};
<dc {
pinctrl-0 = <<dc_r0_pi15 <dc_r1_pj0 <dc_r2_pj1 <dc_r3_pj2
<dc_r4_pj3 <dc_r5_pj4 <dc_r6_pj5 <dc_r7_pj6
<dc_g0_pj7 <dc_g1_pj8 <dc_g2_pj9 <dc_g3_pj10
<dc_g4_pj11 <dc_g5_pk0 <dc_g6_pk1 <dc_g7_pk2
<dc_b0_pe4 <dc_b1_pj13 <dc_b2_pj14 <dc_b3_pj15
<dc_b4_pg12 <dc_b5_pk4 <dc_b6_pk5 <dc_b7_pk6
<dc_de_pk7 <dc_clk_pi14 <dc_hsync_pi10 <dc_vsync_pi9>;
pinctrl-names = "default";
disp-on-gpios = <&gpioi 12 GPIO_ACTIVE_HIGH>;
bl-ctrl-gpios = <&gpiok 3 GPIO_ACTIVE_HIGH>;
ext-sdram = <&sdram1>;
status = "okay";
width = <480>;
height = <272>;
pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
display-timings {
compatible = "zephyr,panel-timing";
de-active = <0>;
pixelclk-active = <0>;
hsync-active = <0>;
vsync-active = <0>;
hsync-len = <1>;
vsync-len = <10>;
hback-porch = <43>;
vback-porch = <12>;
hfront-porch = <8>;
vfront-porch = <4>;
};
def-back-color-red = <0xFF>;
def-back-color-green = <0xFF>;
def-back-color-blue = <0xFF>;
};
``` | /content/code_sandbox/boards/st/stm32f746g_disco/stm32f746g_disco.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,604 |
```restructuredtext
.. _nucleo_l476rg_board:
ST Nucleo L476RG
################
Overview
********
The Nucleo L476RG board features an ARM Cortex-M4 based STM32L476RG MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the Nucleo L476RG board:
- STM32 microcontroller in QFP64 package
- Two types of extension resources:
- Arduino Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- Power management access point
- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3)
- Two push-buttons: USER and RESET
.. image:: img/nucleo_l476rg.jpg
:align: center
:alt: Nucleo L476RG
More information about the board can be found at the `Nucleo L476RG website`_.
Hardware
********
The STM32L476RG SoC provides the following hardware IPs:
- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
- Clock Sources:
- 4 to 48 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 3 PLLs for system clock, USB, audio, ADC
- RTC with HW calendar, alarms and calibration
- LCD 8 x 40 or 4 x 44 with step-up converter
- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- 16x timers:
- 2x 16-bit advanced motor-control
- 2x 32-bit and 5x 16-bit general purpose
- 2x 16-bit basic
- 2x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- SysTick timer
- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
- Memories
- Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection
- Up to 128 KB of SRAM including 32 KB with hardware parity check
- External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories
- Quad SPI memory interface
- 4x digital filters for sigma delta modulator
- Rich analog peripherals (independent supply)
- 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS
- 2x 12-bit DAC, low-power sample and hold
- 2x operational amplifiers with built-in PGA
- 2x ultra-low-power comparators
- 18x communication interfaces
- USB OTG 2.0 full-speed, LPM and BCD
- 2x SAIs (serial audio interface)
- 3x I2C FM+(1 Mbit/s), SMBus/PMBus
- 6x USARTs (ISO 7816, LIN, IrDA, modem)
- 3x SPIs (4x SPIs with the Quad SPI)
- CAN (2.0B Active) and SDMMC interface
- SWPMI single wire protocol master I/F
- 14-channel DMA controller
- True random number generator
- CRC calculation unit, 96-bit unique ID
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
More information about STM32L476RG can be found here:
- `STM32L476RG on www.st.com`_
- `STM32L476 reference manual`_
Supported Features
==================
The Zephyr nucleo_l476rg board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_l476rg/nucleo_l476rg_defconfig`
Connections and IOs
===================
Nucleo L476RG Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/nucleo_l476rg_arduino.jpg
:align: center
:alt: Nucleo L476RG Arduino connectors
.. image:: img/nucleo_l476rg_morpho.jpg
:align: center
:alt: Nucleo L476RG Morpho connectors
For more details please refer to `STM32 Nucleo-64 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- UART_1 TX/RX : PA9/PA10
- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com)
- UART_3 TX/RX : PB10/PB11
- I2C_1 SCL/SDA : PB8/PB9 (Arduino I2C)
- I2C_3 SCL/SDA : PC0/PC1
- SPI_1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI)
- SPI_2 CS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15
- SPI_3 CS/SCK/MISO/MOSI : PA15/PC10/PC11/PC12
- PWM_2_CH1 : PA0
- USER_PB : PC13
- LD2 : PA5
System Clock
------------
Nucleo L476RG System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
driven by 16MHz high speed internal oscillator.
Serial Port
-----------
Nucleo L476RG board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2.
Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``nucleo_l476rg`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool
interface. This interface is supported by the openocd version
included in the Zephyr SDK since v0.9.2.
Flashing an application to Nucleo L476RG
----------------------------------------
Connect the Nucleo L476RG to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l476rg
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_l476rg
:maybe-skip-config:
:goals: debug
.. _Nucleo L476RG website:
path_to_url
.. _STM32 Nucleo-64 board User Manual:
path_to_url
.. _STM32L476RG on www.st.com:
path_to_url
.. _STM32L476 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_l476rg/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,119 |
```yaml
board:
name: stm32f746g_disco
vendor: st
socs:
- name: stm32f746xx
``` | /content/code_sandbox/boards/st/stm32f746g_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
identifier: stm32f746g_disco
name: ST STM32F746G Discovery
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 1024
supported:
- arduino_i2c
- netif:eth
- i2c
- spi
- gpio
- pwm
- counter
- usb_device
- display
- memc
vendor: st
``` | /content/code_sandbox/boards/st/stm32f746g_disco/stm32f746g_disco.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 119 |
```unknown
# STM32F746G DISCOVERY board configuration
if BOARD_STM32F746G_DISCO
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
config INPUT
default y if LVGL
if DISPLAY
# MEMC needs to be enabled in order to store
# display buffer to external SDRAM connected to FMC
config MEMC
default y
endif # DISPLAY
if INPUT
config INPUT_FT5336_INTERRUPT
default y
endif # INPUT
config DISK_DRIVER_SDMMC
default y if DISK_DRIVERS
endif # BOARD_STM32F746G_DISCO
``` | /content/code_sandbox/boards/st/stm32f746g_disco/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 134 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
config BOARD_STM32F746G_DISCO
select SOC_STM32F746XX
``` | /content/code_sandbox/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 0 0>, /* A0 */
<1 0 &gpiof 10 0>, /* A1 */
<2 0 &gpiof 9 0>, /* A2 */
<3 0 &gpiof 8 0>, /* A3 */
<4 0 &gpiof 7 0>, /* A4 */
<5 0 &gpiof 6 0>, /* A5 */
<6 0 &gpioc 7 0>, /* D0 */
<7 0 &gpioc 6 0>, /* D1 */
<8 0 &gpiog 6 0>, /* D2 */
<9 0 &gpiob 4 0>, /* D3 */
<10 0 &gpiog 7 0>, /* D4 */
<11 0 &gpioi 0 0>, /* D5 */
<12 0 &gpioh 6 0>, /* D6 */
<13 0 &gpioi 3 0>, /* D7 */
<14 0 &gpioi 2 0>, /* D8 */
<15 0 &gpioa 15 0>, /* D9 */
<16 0 &gpioa 8 0>, /* D10 */
<17 0 &gpiob 15 0>, /* D11 */
<18 0 &gpiob 14 0>, /* D12 */
<19 0 &gpioi 1 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi2 {};
arduino_serial: &usart6 {};
``` | /content/code_sandbox/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 498 |
```ini
source [find board/stm32f746g-disco.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
if { [info exists _ZEPHYR_BOARD_SERIAL] } {
adapter serial $_ZEPHYR_BOARD_SERIAL
}
# Event reset-init already uses the maximum speed however adapter speed
# inherited from stm32f7x.cfg for reset-start defaults to 2000 kHz, so
# override that speed setting it also to the maximum speed.
$_TARGETNAME configure -event reset-start {
adapter speed 4000
}
``` | /content/code_sandbox/boards/st/stm32f746g_disco/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 159 |
```unknown
config BOARD_NUCLEO_F412ZG
select SOC_STM32F412ZX
``` | /content/code_sandbox/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```cmake
board_runner_args(jlink "--device=STM32F412ZG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f412zg/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f412Xg.dtsi>
#include <st/f4/stm32f412z(e-g)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F412ZG-NUCLEO board";
compatible = "st,stm32f412zg-nucleo";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds: leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led_1: led_2 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led_1: led_3 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_1;
led1 = &blue_led_1;
led2 = &red_led_1;
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <384>;
div-p = <4>;
div-q = <8>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(96)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart6 {
pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa0>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_f412zg/nucleo_f412zg.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 899 |
```yaml
board:
name: nucleo_f412zg
vendor: st
socs:
- name: stm32f412zx
``` | /content/code_sandbox/boards/st/nucleo_f412zg/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# NUCLEO-144 F412ZG board configuration
if BOARD_NUCLEO_F412ZG
if NETWORKING
config USB_DEVICE_STACK
default y
config USB_DEVICE_NETWORK_ECM
default y
endif # NETWORKING
endif # BOARD_NUCLEO_F412ZG
``` | /content/code_sandbox/boards/st/nucleo_f412zg/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 65 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioc 0 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpioc 1 0>, /* A3 */
<4 0 &gpioc 4 0>, /* A4 */
<5 0 &gpioc 5 0>, /* A5 */
<6 0 &gpiog 9 0>, /* D0 */
<7 0 &gpiog 14 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &usart6 {};
``` | /content/code_sandbox/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 500 |
```yaml
identifier: nucleo_f412zg
name: ST Nucleo F412ZG
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 1024
supported:
- arduino_i2c
- arduino_gpio
- arduino_spi
- pwm
- i2c
- spi
- gpio
- usb_device
- counter
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f412zg/nucleo_f412zg.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 115 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```ini
source [find board/st_nucleo_f4.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f412zg/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```restructuredtext
.. _stm32f746g_disco_board:
ST STM32F746G Discovery
#######################
Overview
********
The discovery kit enables a wide diversity of applications taking benefit
from audio, multi-sensor support, graphics, security, security, video,
and high-speed connectivity features. Important board features include:
- STM32F746NGH6 microcontroller featuring 1 Mbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package
- On-board ST-LINK/V2-1 supporting USB re-enumeration capability
- Five power supply options:
- ST LINK/V2-1
- USB FS connector
- USB HS connector
- VIN from Arduino connector
- External 5 V from connector
- Two pushbuttons (user and reset)
- USB functions: virtual COM port, mass storage, debug port
- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen
- SAI audio codec
- Audio line in and line out jack
- Stereo speaker outputs
- Two ST MEMS microphones
- SPDIF RCA input connector
- 128-Mbit Quad-SPI Flash memory
- 128-Mbit SDRAM (64 Mbits accessible)
- Connector for microSD card
- USB OTG HS with Micro-AB connectors
- USB OTG FS with Micro-AB connectors
- Ethernet connector compliant with IEEE-802.3-2002
.. image:: img/stm32f746g_disco.jpg
:align: center
:alt: STM32F746G-DISCO
More information about the board can be found at the `32F746G-DISCO website`_.
Hardware
********
The STM32F746G Discovery kit provides the following hardware components:
- STM32F746NGH6 in BGA216 package
- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU
- 216 MHz max CPU frequency
- VDD from 1.8 V to 3.6 V
- 2 MB Flash
- 384+4 KB SRAM including 64-Kbyte of core coupled memory
- GPIO with external interrupt capability
- LCD parallel interface, 8080/6800 modes
- LCD TFT controller supporting up to XGA resolution
- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution
- 3x12-bit ADC with 24 channels
- 2x12-bit D/A converters
- RTC
- Advanced-control Timer
- General Purpose Timers (17)
- Watchdog Timers (2)
- USART/UART (8)
- I2C (3)
- SPI (6)
- 1xSAI (serial audio interface)
- SDIO
- 2xCAN
- USB 2.0 OTG FS with on-chip PHY
- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI
- 10/100 Ethernet MAC with dedicated DMA
- 8- to 14-bit parallel camera
- CRC calculation unit
- True random number generator
- DMA Controller
More information about STM32F746NGH6 can be found here:
- `STM32F746NGH6 on www.st.com`_
- `STM32F74xxx reference manual`_
Supported Features
==================
The Zephyr stm32f746g_disco board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | Ethernet |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| SDMMC | on-chip | disk access |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| QSPI NOR | on-chip | off-chip flash |
+-----------+------------+-------------------------------------+
| FMC | on-chip | memc (SDRAM) |
+-----------+------------+-------------------------------------+
| LTDC | on-chip | display |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in
:zephyr_file:`boards/st/stm32f746g_disco/stm32f746g_disco_defconfig`
Pin Mapping
===========
STM32F746G Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `32F746G-DISCO board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
The STM32F746G Discovery kit features an Arduino Uno V3 connector. Board is
configured as follows
- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com)
- UART_6 TX/RX : PC6/PC7 (Arduino Serial)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2
- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI)
- PWM_3_CH1 : PB4
- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14
- USER_PB : PI11
- LD1 : PI1
- USB DM : PA11
- USB DP : PA12
- FMC SDRAM :
- D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10
- A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1
- A14/A15 : PG4/PG5
- SDNRAS/SDNCAS : PF11/PG15
- NBL0/NBL1 : PE0/PE1
- SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3
- LTDC :
- R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6
- G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2
- B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6
- DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13
System Clock
============
The STM32F746G System Clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the System clock is driven by the PLL
clock at 216MHz, driven by a 25MHz high speed external clock.
Serial Port
===========
The STM32F746G Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1
which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication
settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``stm32f746g_disco`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
This interface is supported by the openocd version included in the Zephyr SDK.
Flashing an application to STM32F746G
-------------------------------------------
First, connect the STM32F746G Discovery kit to your host computer using
the USB port to prepare it for flashing. Then build and flash your application.
Here is an example for the :ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32f746g_disco
:goals: build flash
Run a serial host program to connect with your board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32f746g_disco
:goals: debug
.. _32F746G-DISCO website:
path_to_url
.. _32F746G-DISCO board User Manual:
path_to_url
.. _STM32F746NGH6 on www.st.com:
path_to_url
.. _STM32F74xxx reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/stm32f746g_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,219 |
```restructuredtext
.. _nucleo_f412zg_board:
ST Nucleo F412ZG
################
Overview
********
The Nucleo F412ZG board features an ARM Cortex-M4 based STM32F412ZG MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the Nucleo F412ZG board:
- STM32 microcontroller in LQFP144 package
- Two types of extension resources:
- ST Zio connector including: support for Arduino* Uno V3 connectivity
(A0 to A5, D0 to D15) and additional signals exposing a wide range of
peripherals
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- 5 V from ST-LINK/V2-1 USB VBUS
- External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho
connectors, 5 V on ST morpho connector
- Three user LEDs
- Two push-buttons: USER and RESET
.. image:: img/nucleo_f412zg.jpg
:align: center
:alt: Nucleo F412ZG
More information about the board can be found at the `Nucleo F412ZG website`_.
Hardware
********
Nucleo F412ZG provides the following hardware components:
- STM32F412ZGT6 in LQFP144 package
- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
- 100 MHz max CPU frequency
- VDD from 1.7 V to 3.6 V
- 1 MB Flash
- 256 KB SRAM
- GPIO with external interrupt capability
- 12-bit ADC with 16 channels, with FIFO and burst support
- RTC
- 14 General purpose timers
- 2 watchdog timers (independent and window)
- SysTick timer
- USART/UART (4)
- I2C (4)
- SPI (5)
- SDIO
- USB 2.0 OTG FS
- DMA Controller
- CRC calculation unit
More information about STM32F412ZG can be found here:
- `STM32F412ZG on www.st.com`_
- `STM32F412 reference manual`_
Supported Features
==================
The Zephyr nucleo_412zg board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/nucleo_f412zg/nucleo_f412zg_defconfig`
Connections and IOs
===================
Nucleo F412ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
Available pins:
---------------
.. image:: img/nucleo_f412zg_zio_left.jpg
:align: center
:alt: Nucleo F412ZG ZIO connectors (left)
.. image:: img/nucleo_f412zg_zio_right.jpg
:align: center
:alt: Nucleo F412ZG ZIO connectors (right)
.. image:: img/nucleo_f412zg_morpho_left.jpg
:align: center
:alt: Nucleo F412ZG Morpho connectors (left)
.. image:: img/nucleo_f412zg_morpho_right.jpg
:align: center
:alt: Nucleo F412ZG Morpho connectors (right)
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
- UART_6 TX/RX : PG14/PG9 (Arduino Serial)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI)
- PWM_2_CH1 : PA0
- USER_PB : PC13
- LD1 : PB0
- LD2 : PB7
- LD3 : PB14
- USB DM : PA11
- USB DP : PA12
System Clock
------------
Nucleo F412ZG System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz,
driven by 8MHz high speed external clock.
Serial Port
-----------
Nucleo F412ZG board has 4 UARTs. The Zephyr console output is assigned to UART3.
Default settings are 115200 8N1.
Network interface
-----------------
Ethernet over USB is configured as the default network interface
Programming and Debugging
*************************
Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is supported by the openocd version included in Zephyr SDK.
.. _Nucleo F412ZG website:
path_to_url
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32F412ZG on www.st.com:
path_to_url
.. _STM32F412 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_f412zg/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,400 |
```cmake
board_runner_args(jlink "--device=STM32H745XI" "--speed=4000")
if(CONFIG_BOARD_STM32H745I_DISCO_STM32H745XX_M7)
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
elseif(CONFIG_BOARD_STM32H745I_DISCO_STM32H745XX_M4)
board_runner_args(openocd --target-handle=_CHIPNAME.cpu1)
endif()
if(CONFIG_STM32_MEMMAP)
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(stm32cubeprogrammer "--extload=MT25TL01G_STM32H745I-DISCO.stldr")
else()
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
endif()
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32h745i_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 238 |
```unknown
# STM32H745XI DISCOVERY board configuration
config BOARD_STM32H745I_DISCO
select SOC_STM32H745XX_M7 if BOARD_STM32H745I_DISCO_STM32H745XX_M7
select SOC_STM32H745XX_M4 if BOARD_STM32H745I_DISCO_STM32H745XX_M4
``` | /content/code_sandbox/boards/st/stm32h745i_disco/Kconfig.stm32h745i_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
# Enable GPIO
CONFIG_GPIO=y
# Enable clock
CONFIG_CLOCK_CONTROL=y
# By default SERIAL peripherals are assigned to m7
# Enable uart driver
#CONFIG_SERIAL=y
# Console
#CONFIG_CONSOLE=y
#CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
# Enable the internal SMPS regulator
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART ( disable to assign to M4 core)
CONFIG_SERIAL=y
# Console ( disable to assign to M4 core)
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clock
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h745Xi_m4.dtsi>
#include "stm32h745i_disco.dtsi"
/ {
model = "STMicroelectronics STM32H745I-DISCO board";
compatible = "st,stm32h745i-disco";
/* HW resources belonging to CM4 */
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram1;
zephyr,flash = &flash1;
};
aliases {
led0 = &green_led;
};
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rcc {
clock-frequency = <DT_FREQ_M(240)>;
};
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 211 |
```unknown
/*
*
*/
#include <st/h7/stm32h745xihx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
leds: leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpioj 2 GPIO_ACTIVE_HIGH>;
label = "User LD7";
};
red_led: led_2 {
gpios = <&gpioi 13 GPIO_ACTIVE_HIGH>;
label = "User LD6";
};
green_led_2: led_3 {
gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
label = "User LD8";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
label = "User SB1";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&rcc {
d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&mailbox {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 296 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h745Xi_m7.dtsi>
#include "stm32h745i_disco.dtsi"
/ {
model = "STMicroelectronics STM32H745I-DISCO board";
compatible = "st,stm32h745i-disco";
/* HW resources belonging to CM7 */
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,dtcm = &dtcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,flash-controller = &mt25ql512ab1;
zephyr,canbus = &fdcan1;
};
pwmleds {
compatible = "pwm-leds";
green_pwm_led: green_pwm_led {
pwms = <&pwm11 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "User LD8 - PWM11";
};
};
/* RM0455 - 23.6 External device address mapping */
sdram2: sdram@d0000000 {
compatible = "zephyr,memory-region", "mmio-sram";
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(16)>; /* 128Mbit */
zephyr,memory-region = "SDRAM2";
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
};
ext_memory: memory@90000000 {
compatible = "zephyr,memory-region";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
zephyr,memory-region = "EXTMEM";
/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
};
aliases {
led0 = &green_led;
pwm-led0 = &green_pwm_led;
sw0 = &user_button;
spi-flash0 = &mt25ql512ab1;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>; /* X1: 25MHz */
status = "okay";
};
&pll {
div-m = <5>;
mul-n = <192>;
div-p = <2>;
div-q = <15>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&pll2 {
div-m = <5>;
mul-n = <192>;
div-p = <2>;
div-q = <12>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(480)>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <57600>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pb10 &usart3_rx_pb11>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&timers1 {
st,prescaler = <10000>;
status = "okay";
pwm11: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch1_pa8>;
pinctrl-names = "default";
};
};
&mac {
status = "okay";
/* MII */
pinctrl-0 = <ð_ref_clk_pa1
ð_crs_dv_pa7
ð_rxd2_pb0
ð_rxd3_pb1
ð_txd2_pc2
ð_tx_clk_pc3
ð_rxd0_pc4
ð_rxd1_pc5
ð_txd3_pe2
ð_tx_en_pg11
ð_txd1_pg12
ð_txd0_pg13
ð_rx_er_pi10>;
pinctrl-names = "default";
};
&mdio {
status = "okay";
pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};
&rng {
status = "okay";
};
&quadspi {
pinctrl-names = "default";
pinctrl-0 = <
&quadspi_bk1_io0_pd11
&quadspi_bk1_io3_pf6
&quadspi_bk1_io2_pf7
&quadspi_bk1_io1_pf9
&quadspi_clk_pf10
&quadspi_bk1_ncs_pg6
&quadspi_bk2_io2_pg9
&quadspi_bk2_io3_pg14
&quadspi_bk2_io0_ph2
&quadspi_bk2_io1_ph3
>;
dual-flash;
status = "okay";
mt25ql512ab1: qspi-nor-flash-1@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
spi-bus-width = <4>;
reset-cmd;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
storage_partition: partition@0 {
reg = <0x0 DT_SIZE_M(64)>;
};
};
};
mt25ql512ab2: qspi-nor-flash-2@90000000 {
compatible = "st,stm32-qspi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
qspi-max-frequency = <72000000>;
status = "okay";
};
};
&i2c4 {
status = "okay";
pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
pinctrl-names = "default";
};
&spi2 {
status = "okay";
pinctrl-0 = <&spi2_nss_pb4 &spi2_mosi_pb15 &spi2_miso_pi2 &spi2_sck_pd3>;
pinctrl-names = "default";
};
&fdcan1 {
status = "okay";
pinctrl-0 = <&fdcan1_tx_ph13 &fdcan1_rx_ph14>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
sample-point = <875>;
sample-point-data = <875>;
can-transceiver {
max-bitrate = <5000000>;
};
};
&fdcan2 {
status = "okay";
pinctrl-0 = <&fdcan2_tx_pb13 &fdcan2_rx_pb5>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
sample-point = <875>;
sample-point-data = <875>;
can-transceiver {
max-bitrate = <5000000>;
};
};
&fmc {
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
&fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
&fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
&fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
&fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
&fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
&fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
&fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
&fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
&fmc_d15_pd10>;
pinctrl-names = "default";
status = "okay";
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <8>;
mode-register = <0x220>;
refresh-rate = <0x603>;
bank@1 {
reg = <1>;
st,sdram-control = <STM32_FMC_SDRAM_NC_8
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_2
STM32_FMC_SDRAM_RBURST_ENABLE
STM32_FMC_SDRAM_RPIPE_0>;
st,sdram-timing = <2 7 4 7 2 2 2>;
};
};
};
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,318 |
```yaml
identifier: stm32h745i_disco/stm32h745xx/m7
name: STM32H745XI Discovery (M7)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 512
flash: 1024
supported:
- arduino_gpio
- arduino_i2c
- uart
- gpio
- counter
- i2c
- pwm
- netif:eth
- qspi
- memc
- spi
- rtc
- can
vendor: st
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 138 |
```yaml
board:
name: stm32h745i_disco
vendor: st
socs:
- name: stm32h745xx
``` | /content/code_sandbox/boards/st/stm32h745i_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```yaml
identifier: stm32h745i_disco/stm32h745xx/m4
name: STM32H745XI Discovery (M4)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 288
flash: 1024
supported:
- arduino_gpio
- gpio
testing:
ignore_tags:
- mpu
- nfc
vendor: st
``` | /content/code_sandbox/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```unknown
# STM32H745XI DISCOVERY board configuration
if BOARD_STM32H745I_DISCO
if NETWORKING
config NET_L2_ETHERNET
default y
config ETH_STM32_HAL_MII
default y
endif # NETWORKING
config MEMC
default y if DISPLAY
endif # BOARD_STM32H745I_DISCO
``` | /content/code_sandbox/boards/st/stm32h745i_disco/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 76 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioc 0 0>, /* A0 */
<1 0 &gpiof 8 0>, /* A1 */
<2 0 &gpioa 0 0>, /* A2 */
<3 0 &gpioa 1 0>, /* A3 */
<4 0 &gpioc 2 0>, /* A4 */
<5 0 &gpioc 3 0>, /* A5 */
<6 0 &gpiob 7 0>, /* D0 */
<7 0 &gpiob 6 0>, /* D1 */
<8 0 &gpiog 3 0>, /* D2 */
<9 0 &gpioa 6 0>, /* D3 */
<10 0 &gpiok 1 0>, /* D4 */
<11 0 &gpioa 8 0>, /* D5 */
<12 0 &gpioe 6 0>, /* D6 */
<13 0 &gpioi 6 0>, /* D7 */
<14 0 &gpioe 3 0>, /* D8 */
<15 0 &gpioh 15 0>, /* D9 */
<16 0 &gpiob 4 0>, /* D10 */
<17 0 &gpiob 15 0>, /* D11 */
<18 0 &gpioi 2 0>, /* D12 */
<19 0 &gpiod 3 0>, /* D13 */
<20 0 &gpiod 13 0>, /* D14 */
<21 0 &gpiod 12 0>; /* D15 */
};
};
arduino_i2c: &i2c4 {};
arduino_spi: &spi2 {};
arduino_serial: &usart1 {};
``` | /content/code_sandbox/boards/st/stm32h745i_disco/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 501 |
```ini
# STM32H745XI DISCOVERY board OpenOCD ST-LINK V3 configuration
#
#
source [find board/stm32h745i-disco.cfg]
# Use connect_assert_srst here to be able to program
# even when core is in sleep mode
reset_config srst_only srst_nogate connect_assert_srst
$_CHIPNAME.cpu0 configure -event gdb-attach {
echo "Debugger attaching: halting execution"
gdb_breakpoint_override hard
}
$_CHIPNAME.cpu0 configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/stm32h745i_disco/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 174 |
```unknown
/*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
/ {
st_morpho_header: st-morpho-header {
compatible = "st-morpho-header";
#gpio-cells = <2>;
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
<ST_MORPHO_L_2 0 &gpioc 11 0>,
<ST_MORPHO_L_3 0 &gpioc 12 0>,
<ST_MORPHO_L_4 0 &gpiod 2 0>,
<ST_MORPHO_L_7 0 &gpioa 14 0>,
<ST_MORPHO_L_9 0 &gpiod 0>,
<ST_MORPHO_L_10 0 &gpiod 1>,
<ST_MORPHO_L_11 0 &gpiod 3>,
<ST_MORPHO_L_13 0 &gpioa 13 0>,
<ST_MORPHO_L_15 0 &gpiod 4 0>,
<ST_MORPHO_L_17 0 &gpioa 15 0>,
<ST_MORPHO_L_21 0 &gpiob 7 0>,
<ST_MORPHO_L_23 0 &gpioc 13 0>,
<ST_MORPHO_L_25 0 &gpioc 14 0>, /* SB23=ON, R31=OFF */
<ST_MORPHO_L_26 0 &gpiod 5 0>,
<ST_MORPHO_L_27 0 &gpioc 15 0>, /* SB24=ON, R32=OFF */
<ST_MORPHO_L_28 0 &gpioa 0 0>,
<ST_MORPHO_L_29 0 &gpiof 0 0>,
<ST_MORPHO_L_30 0 &gpioa 1 0>,
<ST_MORPHO_L_31 0 &gpiof 1 0>,
<ST_MORPHO_L_32 0 &gpioa 4 0>,
<ST_MORPHO_L_34 0 &gpiob 1 0>,
<ST_MORPHO_L_35 0 &gpioc 2 0>,
<ST_MORPHO_L_36 0 &gpiob 11 0>, /* SB4=ON, SB2=OFF */
<ST_MORPHO_L_37 0 &gpioc 3 0>,
<ST_MORPHO_L_38 0 &gpiob 12 0>, /* SB3=ON, SB5=OFF */
<ST_MORPHO_R_1 0 &gpioc 9 0>,
<ST_MORPHO_R_2 0 &gpioc 8 0>,
<ST_MORPHO_R_3 0 &gpiob 8 0>,
<ST_MORPHO_R_4 0 &gpioc 6 0>,
<ST_MORPHO_R_5 0 &gpiob 9 0>,
<ST_MORPHO_R_6 0 &gpioa 3 0>,
<ST_MORPHO_R_10 0 &gpiod 6 0>,
<ST_MORPHO_R_11 0 &gpioa 5 0>,
<ST_MORPHO_R_12 0 &gpioa 12 0>,
<ST_MORPHO_R_13 0 &gpioa 6 0>,
<ST_MORPHO_R_14 0 &gpioa 11 0>,
<ST_MORPHO_R_15 0 &gpioa 7 0>,
<ST_MORPHO_R_16 0 &gpioc 1 0>,
<ST_MORPHO_R_17 0 &gpiob 0 0>,
<ST_MORPHO_R_18 0 &gpioc 0 0>,
<ST_MORPHO_R_19 0 &gpioc 7 0>,
<ST_MORPHO_R_21 0 &gpioa 9 0>,
<ST_MORPHO_R_22 0 &gpiob 2 0>,
<ST_MORPHO_R_23 0 &gpioa 8 0>,
<ST_MORPHO_R_24 0 &gpiob 6 0>,
<ST_MORPHO_R_25 0 &gpiob 14 0>,
<ST_MORPHO_R_26 0 &gpiob 15 0>,
<ST_MORPHO_R_27 0 &gpiob 4 0>,
<ST_MORPHO_R_28 0 &gpiob 10 0>,
<ST_MORPHO_R_29 0 &gpiob 5 0>,
<ST_MORPHO_R_30 0 &gpiob 13 0>,
<ST_MORPHO_R_31 0 &gpiob 3 0>,
<ST_MORPHO_R_33 0 &gpioa 10 0>,
<ST_MORPHO_R_34 0 &gpioa 2 0>,
<ST_MORPHO_R_35 0 &gpioc 4 0>,
<ST_MORPHO_R_36 0 &gpiod 8 0>,
<ST_MORPHO_R_37 0 &gpioc 5 0>,
<ST_MORPHO_R_38 0 &gpiod 9 0>;
};
};
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,367 |
```yaml
identifier: nucleo_g0b1re
name: ST Nucleo G0B1RE
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 144
flash: 512
supported:
- adc
- arduino_gpio
- arduino_i2c
- arduino_spi
- arduino_serial
- can
- uart
- gpio
- i2c
- spi
- nvs
- dma
- usb_device
- lptim
- usbd
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 146 |
```cmake
# keil.stm32g0xx_dfp.1.3.0.pack introduced stm32g0b series, but the target does
# not work with pyocd currently.
board_runner_args(pyocd "--target=stm32g071rbtx")
board_runner_args(pyocd "--flash-opt=-O reset_type=hw")
board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
board_runner_args(jlink "--device=STM32G0B1RE" "--speed=4000")
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 207 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```yaml
board:
name: nucleo_g0b1re
vendor: st
socs:
- name: stm32g0b1xx
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 35 |
```unknown
config BOARD_NUCLEO_G0B1RE
select SOC_STM32G0B1XX
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 25 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 0 0>, /* A0 */
<1 0 &gpioa 1 0>, /* A1 */
<2 0 &gpioa 4 0>, /* A2 */
<3 0 &gpiob 1 0>, /* A3 */
<4 0 &gpiob 11 0>, /* A4 */
<5 0 &gpiob 12 0>, /* A5 */
<6 0 &gpioc 5 0>, /* D0 */
<7 0 &gpioc 4 0>, /* D1 */
<8 0 &gpioa 10 0>, /* D2 */
<9 0 &gpiob 3 0>, /* D3 */
<10 0 &gpiob 5 0>, /* D4 */
<11 0 &gpiob 4 0>, /* D5 */
<12 0 &gpiob 14 0>, /* D6 */
<13 0 &gpioa 8 0>, /* D7 */
<14 0 &gpioa 9 0>, /* D8 */
<15 0 &gpioc 7 0>, /* D9 */
<16 0 &gpiob 0 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &usart1 {};
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 502 |
```restructuredtext
.. _stm32h745i_disco_board:
ST STM32H745I Discovery
#######################
Overview
********
The STM32H745I-DISCO Discovery kit is a complete demonstration and development
platform for STMicroelectronics Arm |reg| Cortex |reg|M7 and Cortex |reg|M4 core-based STM32H745XI microcontroller.
The full range of hardware features available on the board helps users enhance their application
development by an evaluation of almost all peripherals (such as USB OTG FS, Ethernet 10/100Mb/s,
eMMC, USART, SAI audio DAC stereo with audio jack input and output, MEMS digital microphone, SDRAM,
Quad-SPI flash memory, and RGB interface LCD with capacitive multi-touch panel). ARDUINO |reg| Uno V3
connectors provide easy connection to extension shields or daughterboards for specific applications.
STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and programmer for the
STM32 MCU and the USB Virtual COM port bridge
Key Features
- Arm |reg| Cortex |reg| core-based microcontroller with 2 Mbytes of flash memory and 1 Mbyte of RAM, in a TFBGA240+25 package
- 4.3 RGB interface LCD with touch panel connector
- Ethernet compliant with IEEE-802.3-2002, and PoE
- USB OTG FS
- SAI audio codec
- One ST-MEMS digital microphone
- 2 512-Mbit Quad-SPI NOR flash memory
- 128-Mbit SDRAM
- 4-Gbyte on-board eMMC
- 1 user and reset push-button
- Fanout daughterboard
- 2 CAN FDs
- Board connectors:
- USB FS Micro-AB connectors
- ST-LINK Micro-B USB connector
- USB power Micro-B connector
- Ethernet RJ45
- Stereo headset jack including analog microphone input
- Audio header for external speakers
- TagConnect |trade| (TAG) 10-pin footprint
- Arm |reg| Cortex |reg| 10-pin 1.27 mm pitch debug connector over STDC14 footprint
- ARDUINO |reg| Uno V3 expansion connectors
- STMod+
- Flexible power-supply options:
- STLINK-V3E USB connector, USB FS connector
- 5 V delivered by RJ45 (Power over Ethernet)
- 5 V delivered by ARDUINO |reg| or external connector
- USB charger
- USB power
.. image:: img/stm32h745i-disco.jpg
:align: center
:alt: STM32H745I-DISCO
More information about the board can be found at the `STM32H745I-DISCO website`_.
More information about STM32H747XIH6 can be found here:
- `STM32H745XI on www.st.com`_
- `STM32H745xx reference manual`_
- `STM32H745xx datasheet`_
Supported Features
==================
The current Zephyr stm32h745i_disco board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| RTC | on-chip | counter |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| QSPI NOR | on-chip | off-chip flash |
+-----------+------------+-------------------------------------+
| FDCAN | on-chip | fdcan |
+-----------+------------+-------------------------------------+
| FMC | on-chip | memc (SDRAM) |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration per core can be found in the defconfig files:
:zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig` and
:zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig`
For more details please refer to `STM32H745-Disco UM`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- USART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com)
- USART_1 TX/RX : PB6/PB7 (Arduino Serial)
- SPI_2 NSS/SCK/MISO/MOSI : PB4/PD3/PI2/PB15 (Arduino SPI)
- I2C_4 SCL/SDA: PD12, PD13 (Arduino I2C)
- USER_PB : PC13
- LD1 : PI13
- LD2 : PJ2
- LD3 : PD3
System Clock
------------
STM32H745I-DISCO System Clock could be driven by an internal or external
oscillator, as well as the main PLL clock. By default, the System clock is
driven by the PLL clock at 480MHz, driven by an 25MHz high-speed external clock.
Serial Port
-----------
STM32H745I-DISCO board has 4 UARTs and 4 USARTs. The Zephyr console output is
assigned to UART3. Default settings are 115200 8N1.
Resources sharing
-----------------
The dual core nature of STM32H745 SoC requires sharing HW resources between the
two cores. This is done in 3 ways:
- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
has access to bus clock activation and deactivation.
- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
devicetree before compilation. The user must ensure peripherals are not assigned
to both cores at the same time.
- **Run time protection**: Interrupt-controller and GPIO configurations could be
accessed by both cores at run time. Accesses are protected by a hardware semaphore
to avoid potential concurrent access issues.
Programming and Debugging
*************************
Applications for the ``stm32h745i_disco`` board should be built per core target,
using either ``stm32h745i_disco/stm32h745xx/m7`` or ``stm32h745i_disco/stm32h745xx/m4`` as the target
(see :ref:`build_an_application` and :ref:`application_run` for more details).
.. note::
Check if the on-board ST-LINK V3 has the latest firmware version. It can be done with either `STM32CubeIDE`_ or `STM32CubeProgrammer`_
Flashing
========
STM32H745I-DISCO board includes an ST-LINK/V3 embedded debug tool interface.
Flashing operation will depend on the target and the SoC
option bytes configuration.
By default:
- CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
- CPU1 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0)
Also, the out of the box default board configuration enables CM7 and CM4 boot when
board is powered (Option bytes BCM7 and BCM4 are checked).
In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected.
Zephyr flash configuration has been set to meet these default settings.
Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing
it, to flash applications for both cores. The target core is detected automatically.
.. code-block:: console
$ west flash --runner stm32cubeprogrammer
Flashing an application to STM32H745XI M7 Core
----------------------------------------------
First, connect the STM32H745I-DISCO to your host computer using
the USB port to prepare it for flashing. Then build and flash your application.
Here is an example for the :ref:`hello_world` application.
Run a serial host program to connect with your STM32H745I-DISCO board.
.. code-block:: console
$ minicom -b 115200 -D /dev/ttyACM0
or use screen:
.. code-block:: console
$ screen /dev/ttyACM0 115200
Build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h745i_disco/stm32h745xx/m7
:goals: build flash
You should see the following message on the console:
.. code-block:: console
$ Hello World! stm32h745i_disco
.. note::
Sometimes, flashing does not work properly. It is necessary to erase the flash
(with STM32CubeProgrammer for example) to make it work again.
Similarly, you can build and flash samples on the M4 target. For this, please
take care of the resource sharing (UART port used for console for instance).
Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32h745i_disco/stm32h745xx/m7
:goals: build flash
.. note::
Flashing both M4 and M7 and pushing RESTART button on the board leads
to LD1 and LD2 flashing simultaneously.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h745i_disco/stm32h745xx/m7
:maybe-skip-config:
:goals: debug
Debugging with west is currently not available on Cortex M4 side.
In order to debug a Zephyr application on Cortex M4 side, you can use
`STM32CubeIDE`_.
.. _STM32H745I-DISCO website:
path_to_url
.. _STM32H745XI on www.st.com:
path_to_url
.. _STM32H745xx reference manual:
path_to_url
.. _STM32H745xx datasheet:
path_to_url
.. _STM32H745-Disco UM:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _STM32CubeIDE:
path_to_url
``` | /content/code_sandbox/boards/st/stm32h745i_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,441 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32g0x.cfg]
reset_config srst_only
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 34 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/g0/stm32g0b1Xe.dtsi>
#include <st/g0/stm32g0b1r(b-c-e)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include "st_morpho_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32G0B1RE-NUCLEO board";
compatible = "st,stm32g0b1re-nucleo";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,uart-mcumgr = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
zephyr,canbus = &fdcan1;
};
leds: leds {
compatible = "gpio-leds";
green_led_1: led_4 {
gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
label = "User LD4";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_1;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
crs-usb-sof;
};
&pll {
div-m = <1>;
mul-n = <8>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(64)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
zephyr_udc0: &usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&usart1 {
pinctrl-0 = <&usart1_tx_pc4 &usart1_rx_pc5>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&iwdg {
status = "okay";
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch1_pb4>;
pinctrl-names = "default";
};
};
&timers15 {
st,prescaler = <10000>;
status = "okay";
pwm15: pwm {
status = "okay";
pinctrl-0 = <&tim15_ch1_pb14>;
pinctrl-names = "default";
};
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pa11 &i2c2_sda_pa12>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_pb0 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_nss_pd0 &spi2_sck_pd1
&spi2_miso_pd3 &spi2_mosi_pd4>;
pinctrl-names = "default";
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dac1 {
status = "okay";
pinctrl-0 = <&dac1_out1_pa4>;
pinctrl-names = "default";
};
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
<&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
pinctrl-names = "default";
status = "okay";
};
&fdcan2 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
<&rcc STM32_SRC_PLL_Q FDCAN_SEL(1)>;
pinctrl-0 = <&fdcan2_rx_pb0 &fdcan2_tx_pb1>;
pinctrl-names = "default";
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(48)>;
read-only;
};
slot0_partition: partition@C000 {
label = "image-0";
reg = <0x0000C000 DT_SIZE_K(200)>;
};
slot1_partition: partition@3E000 {
label = "image-1";
reg = <0x0003E000 DT_SIZE_K(200)>;
};
/* final 64KiB reserved for app storage partition */
storage_partition: partition@70000 {
label = "storage";
reg = <0x00070000 DT_SIZE_K(64)>;
};
};
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,608 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 47 |
```unknown
#
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/g4/stm32g474Xe.dtsi>
#include <st/g4/stm32g474r(b-c-e)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "B-G474E-DPOW1 Discovery board";
compatible = "st,b-g474e-dpow1";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
blue_led_2: led2 {
gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>;
label = "LED_DOWN_BLUE";
};
orange_led_3: led3 {
gpios = <&gpiob 1 GPIO_ACTIVE_HIGH>;
label = "LED_LEFT_ORANGE";
};
green_led_4: led4 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "LED_RIGHT_GREEN";
};
red_led_5: led5 {
gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>;
label = "LED_UP_RED";
};
};
gpio_keys {
compatible = "gpio-keys";
joystick_sel: button0 {
label = "JOYSTICK_SEL";
gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_ENTER>;
};
joystick_left: button1 {
label = "JOYSTICK_LEFT";
gpios = <&gpioc 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_LEFT>;
};
joystick_down: button2 {
label = "JOYSTICK_DOWN";
gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_DOWN>;
};
joystick_right: button3 {
label = "JOYSTICK_RIGHT";
gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_RIGHT>;
};
joystick_up: button4 {
label = "JOYSTICK_UP";
gpios = <&gpiob 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
zephyr,code = <INPUT_KEY_UP>;
};
};
aliases {
led0 = &blue_led_2;
led1 = &orange_led_3;
led2 = &green_led_4;
led3 = &red_led_5;
sw0 = &joystick_sel;
sw1 = &joystick_left;
sw2 = &joystick_down;
sw3 = &joystick_right;
sw4 = &joystick_up;
watchdog0 = &iwdg;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hsi {
status = "okay";
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <16>;
div-p = <7>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(128)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pc10 &usart3_rx_pc11>;
pinctrl-1 = <&analog_pc10 &analog_pc11>;
pinctrl-names = "default", "sleep";
current-speed = <115200>;
status = "okay";
};
&iwdg {
status = "okay";
};
&adc2 {
pinctrl-0 = <&adc2_in8_pc2>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
channel@8 {
reg = <8>;
zephyr,gain = "ADC_GAIN_1";
zephyr,reference = "ADC_REF_INTERNAL";
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,vref-mv = <3300>;
};
};
&ucpd1 {
status = "okay";
/*
* UCPD is fed directly from HSI which is @ 16MHz. The ucpd_clk goes to
* a prescaler who's output feeds the 'half-bit' divider which is used
* to generate clock for delay counters and BMC Rx/Tx blocks. The rx is
* designed to work in freq ranges of 6 <--> 18 MHz, however recommended
* range is 9 <--> 18 MHz.
*
* +-------+ @ 16 MHz +-------+ @ ~600 kHz +-----------+
* HSI ---->| /psc |--------->| /hbit |--------------->| trans_cnt |
* +-------+ +-------+ | +-----------+
* | +-----------+
* +----------->| ifrgap_cnt|
* +-----------+
* Requirements:
* 1. hbit_clk ~= 600 kHz: 16 MHz / 600 kHz = 26.67
* 2. tTransitionWindow - 12 to 20 uSec
* 3. tInterframGap - uSec
*
* hbit_clk = HSI_clk / 27 = 592.6 kHz = 1.687 uSec period
* tTransitionWindow = 1.687 uS * 8 = 13.5 uS
* tInterFrameGap = 1.687 uS * 17 = 28.68 uS
*/
psc-ucpdclk = <1>;
hbitclkdiv = <27>;
pinctrl-0 = <&ucpd1_cc1_pb6 &ucpd1_cc2_pb4>;
pinctrl-names = "default";
};
zephyr_udc0: &usb {
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,534 |
```yaml
identifier: b_g474e_dpow1
name: ST B-G474E-DPOW1 Discovery
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 128
flash: 512
supported:
- uart
- gpio
- watchdog
- tcpc
- usb
- usbd
vendor: st
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```yaml
board:
name: b_g474e_dpow1
vendor: st
socs:
- name: stm32g474xx
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config BOARD_B_G474E_DPOW1
select SOC_STM32G474XX
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```restructuredtext
.. _nucleo_g0b1re_board:
ST Nucleo G0B1RE
################
Overview
********
The Nucleo G0B1RE board features an ARM Cortex-M0+ based STM32G0B1RE MCU
with a wide range of connectivity support and configurations. Here are
some highlights of the Nucleo G0B1RE board:
- STM32 microcontroller in QFP64 package
- Board connectors:
- Arduino Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector
- Flexible board power supply:
- 5V_USB_STLK from ST-Link USB connector
- VIN (7 - 12V) from ARDUINO connector or ST morpho connector
- E5V from ST morpho connector
- 5V_USB_CHG from ST-LINK USB connector
- 3.3V on ARDUINO connector or ST morpho connector
- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3)
- Two push-buttons: USER and RESET
- 32.768 kHz crystal oscillator
.. image:: img/nucleo_g0b1re.jpg
:align: center
:alt: Nucleo G0B1RE
More information about the board can be found at the `Nucleo G0B1RE website`_.
Hardware
********
Nucleo G0B1RE provides the following hardware components:
- STM32G0B1RE in LQFP64 package
- ARM 32-bit Cortex-M0+ CPU
- 64 MHz max CPU frequency
- Voltage range from 1.7 V to 3.6 V
- 512 KB Flash
- 144 kB SRAM
- 32-bit timers(1)
- 16-bit timers(11)
- watchdogs(2)
- systick(1)
- Calendar RTC with alarm and periodic wakeup
- I2C(3)
- USART(6)
- LPUART(2)
- 32 Mbit/s SPI(3) multiplexed with I2S(2)
- HDMI_CEC(1)
- USB 2.0 FS device (crystal-less) and host controller(1)
- USB Type-C Power Delivery controller
- CAN FD(2)
- GPIO (up to 94) with external interrupt capability
- Tamper Pins(3)
- 12-bit ADC with 16 channels
- 12-bit DAC with 2 channels(2)
- Analog Comparator(3)
- 12-channel DMA
More information about STM32G0B1RE can be found here:
- `G0B1RE on www.st.com`_
- `STM32G0B1 reference manual`_
Supported Features
==================
The Zephyr nucleo_g0b1re board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| MPU | on-chip | arm memory protection unit |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | rtc |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| ADC | on-chip | adc |
+-----------+------------+-------------------------------------+
| DAC | on-chip | dac |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
| FDCAN | on-chip | CAN controller |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig`
Connections and IOs
===================
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PC4/PC5
- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- I2C2 SCL/SDA : PA11/PA12
- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI)
- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15
- USER_PB : PC13
- LD4 : PA5
- PWM : PA6
- ADC1 IN0 : PA0
- ADC1 IN1 : PA1
- DAC1_OUT1 : PA4
- FDCAN1 RX/TX: PA11/PA12
- FDCAN2 RX/TX: PB0/PB1
For more details please refer to `STM32 Nucleo-64 board User Manual`_.
Programming and Debugging
*************************
Applications for the ``nucleo_g0b1re`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is not yet supported by the openocd version included in the Zephyr SDK.
But JLink, STM32CubeProgrammer and Pyocd interfaces are supported.
Pyocd support is currently limited: As the stm32g0b1 target causes issues,
the stm32g071 target is used. For STM32G0 support pyocd needs additional target
information, which can be installed by adding "pack" support with the
following pyocd command:
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32g0
Flashing an application to Nucleo G0B1RE
----------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_g0b1re
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_g0b1re
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _Nucleo G0B1RE website:
path_to_url
.. _STM32G0B1 reference manual:
path_to_url
.. _STM32 Nucleo-64 board User Manual:
path_to_url
.. _G0B1RE on www.st.com:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_g0b1re/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,820 |
```unknown
# STM32H7S78-DK Discovery kit board configuration
#
#
#
config BOARD_STM32H7S78_DK
select SOC_STM32H7S7XX
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/Kconfig.stm32h7s78_dk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 41 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
# FIXME: openocd runner not yet available.
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 90 |
```unknown
# Enable SMPS
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable uart driver
CONFIG_SERIAL=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```yaml
board:
name: stm32h7s78_dk
vendor: st
socs:
- name: stm32h7s7xx
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
identifier: stm32h7s78_dk
name: ST STM32H7S78 Discovery Kit
type: mcu
arch: arm
toolchain:
- zephyr
ram: 640
flash: 64
supported:
- arduino_gpio
- gpio
- uart
- watchdog
- entropy
- adc
vendor: st
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 84 |
```restructuredtext
.. _b_g474e_dpow1_board:
ST B-G474E-DPOW1 Discovery
##########################
Overview
********
The B-G474E-DPOW1 Discovery kit is a digital power solution and a complete
demonstration and development platform for the STMicroelectronics STM32G474RET6
microcontroller. Leveraging the new HRTimer-oriented features, 96 Kbytes of
embedded RAM, math accelerator functions and USB-PD 3.0 offered by STM32G474RET6,
the B-G474E-DPOW1 Discovery kit, based on the USB 2.0 FS Type-C connector
interface, helps the user to prototype applications with digital power such as a
buck-boost converter, RGB power LED lighting or a class-D audio amplifier. The
B-G474E-DPOW1 Discovery kit does not require any separate probe, as it integrates
the STLINK-V3E debugger and programmer.
- STM32G474RET6 Arm Cortex-M4 core-based microcontroller, featuring 512 Kbytes
of Flash memory and 128 Kbytes of SRAM, in LQFP64 package
- USB Type-C with USB 2.0 FS interface compatible with USB-PD 3.0
- RGB power LED for a bright lighting
- Digital power buck-boost converter with internal or external Input voltage and
with onboard resistor loads
- Audio Class-D amplifier capable
- 4 user LEDs
- 3 LEDs for power and ST-LINK communication
- 4-direction joystick with a selection button
- Reset push-button
- Board connectors:
- USB Type-C
- USB Micro-B
- 2 x 32-pin header, 2.54 mm pitch, daughterboard extension connector for breadboard connection
- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C VBUS or external source
- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: mass storage,
Virtual COM port, and debug port
.. image:: img/b_g474e_dpow1.jpg
:align: center
:alt: B-G474E-DPOW1
More information about the board can be found at the `B-G474E-DPOW1 website`_.
More information about STM32G474RE can be found here:
- `G474RE on www.st.com`_
- `STM32G4 reference manual`_
Supported Features
==================
The Zephyr b_g474e_dpow1 board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb |
+-----------+------------+-------------------------------------+
| UCPD | on-chip | ucpd |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig`
Connections and IOs
===================
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com)
- BUTTON (JOY_SEL) : PC13
- BUTTON (JOY_LEFT) : PC4
- BUTTON (JOY_DOWN) : PC5
- BUTTON (JOY_RIGHT) : PB2
- BUTTON (JOY_UP) : PB10
- LED (DOWN BLUE) : PA15
- LED (LEFT ORANGE) : PB1
- LED (UP RED) : PB5
- LED (RIGHT GREEN) : PB7
- USB DM : PA11
- USB DP : PA12
- UCPD CC2 : PB4
- UCPD CC1 : PB6
For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_.
Programming and Debugging
*************************
Applications for the ``b_g474e_dpow1`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface.
.. code-block:: console
$ west flash
Flashing an application to the B_G474E_DPOW1
--------------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: b_g474e_dpow1
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: b_g474e_dpow1
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _B-G474E-DPOW1 website:
path_to_url
.. _STM32G4 reference manual:
path_to_url
.. _B-G474E-DPOW1 Discovery board User Manual:
path_to_url
.. _G474RE on www.st.com:
path_to_url
``` | /content/code_sandbox/boards/st/b_g474e_dpow1/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,366 |
```unknown
# STM32H7S78 DISCOVERY KIT board configuration
#
#
#
if BOARD_STM32H7S78_DK
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_STM32H7S78_DK
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 63 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7rs/stm32h7s7X8.dtsi>
#include <st/h7/stm32h7s7l8hx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32H7S78 DISCOVERY KIT board";
compatible = "st,stm32h7s78-dk";
chosen {
zephyr,console = &uart4;
zephyr,shell-uart = &uart4;
zephyr,flash = &flash0;
zephyr,sram = &sram0;
};
leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpioo 1 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
orange_led: led_2 {
gpios = <&gpioo 5 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
red_led: led_3 {
gpios = <&gpiom 2 GPIO_ACTIVE_LOW>;
label = "User LD3";
};
blue_led: led_4 {
gpios = <&gpiom 3 GPIO_ACTIVE_LOW>;
label = "User LD4";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &blue_led;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
hse-bypass; /* X3 is a 24MHz oscillator on PH0 */
status = "okay";
};
&pll {
div-m = <12>;
mul-n = <250>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
div-s = <2>;
div-t = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(250)>;
dcpre = <1>;
hpre = <1>;
ppre1 = <2>;
ppre2 = <2>;
ppre4 = <2>;
ppre5 = <2>;
};
&uart4 {
pinctrl-0 = <&uart4_tx_pd1 &uart4_rx_pd0>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart7 {
pinctrl-0 = <&uart7_tx_pe8 &uart7_rx_pe7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&timers2 {
st,prescaler = <10000>;
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch4_pa3>;
pinctrl-names = "default";
};
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch2_pb5>;
pinctrl-names = "default";
};
};
&rng {
status = "okay";
};
&iwdg {
status = "okay";
};
&wwdg {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_inp6_pf12>; /* Arduino A3 */
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&adc2 {
pinctrl-0 = <&adc2_inp2_pf13>; /* Arduino A4 */
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&spi4 {
pinctrl-0 = <&spi4_nss_pe4 &spi4_sck_pe12
&spi4_miso_pe13 &spi4_mosi_pe14>;
pinctrl-names = "default";
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb9>;
pinctrl-names = "default";
};
&die_temp {
status = "okay";
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,100 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioc 0 0>, /* A0 */
<1 0 &gpioc 2 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiof 12 0>, /* A3 */
<4 0 &gpiof 13 0>, /* A4 */
<5 0 &gpioc 1 0>, /* A5 */
<6 0 &gpioe 7 0>, /* D0 */
<7 0 &gpioe 8 0>, /* D1 */
<8 0 &gpiof 1 0>, /* D2 */
<9 0 &gpiod 12 0>, /* D3 */
<10 0 &gpiof 2 0>, /* D4 */
<11 0 &gpiod 13 0>, /* D5 */
<12 0 &gpiod 15 0>, /* D6 */
<13 0 &gpiof 3 0>, /* D7 */
<14 0 &gpiof 4 0>, /* D8 */
<15 0 &gpiof 6 0>, /* D9 */
<16 0 &gpiof 8 0>, /* D10 */
<17 0 &gpioe 14 0>, /* D11 */
<18 0 &gpioe 13 0>, /* D12 */
<19 0 &gpioe 12 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 6 0>; /* D15 */
};
};
arduino_spi: &spi4 {};
arduino_i2c: &i2c1 {};
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 490 |
```ini
source [find interface/stlink-dap.cfg]
transport select "dapdirect_swd"
set WORKAREASIZE 0x8000
set CHIPNAME STM32H7S7XX
set BOARDNAME STM32H7S78_DK
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
# reset_config srst_only srst_nogate connect_assert_srst
#set CONNECT_UNDER_RESET 1
#set CORE_RESET 0
source [find target/stm32h7rx.cfg]
$_CHIPNAME.cpu0 configure -event gdb-attach {
echo "Debugger attaching: halting execution"
gdb_breakpoint_override hard
}
$_CHIPNAME.cpu0 configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 257 |
```unknown
/*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
/ {
st_morpho_header: st-morpho-header {
compatible = "st-morpho-header";
#gpio-cells = <2>;
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
<ST_MORPHO_L_2 0 &gpioc 11 0>,
<ST_MORPHO_L_3 0 &gpioc 12 0>,
<ST_MORPHO_L_4 0 &gpiod 2 0>,
/* By default, PA13 and PA14 are used as SWD signals
* (SB40=ON, SB41=ON)
*/
<ST_MORPHO_L_13 0 &gpioa 13 0>,
<ST_MORPHO_L_15 0 &gpioa 14 0>,
<ST_MORPHO_L_17 0 &gpioa 15 0>,
<ST_MORPHO_L_23 0 &gpioc 13 0>,
<ST_MORPHO_L_25 0 &gpioc 14 0>,
<ST_MORPHO_L_27 0 &gpioc 15 0>,
<ST_MORPHO_L_28 0 &gpioa 0 0>,
/* STM32H503xx has no pin PF0 as described in manual (UM3121) */
<ST_MORPHO_L_30 0 &gpioa 1 0>,
/* STM32H503xx has no pin PF1 as described in manual (UM3121) */
<ST_MORPHO_L_32 0 &gpioa 2 0>,
<ST_MORPHO_L_34 0 &gpiob 0 0>,
<ST_MORPHO_L_35 0 &gpioc 2 0>,
<ST_MORPHO_L_36 0 &gpioc 1 0>,
<ST_MORPHO_L_37 0 &gpioc 3 0>,
<ST_MORPHO_L_38 0 &gpioc 0 0>,
<ST_MORPHO_R_2 0 &gpioc 8 0>,
<ST_MORPHO_R_3 0 &gpiob 6 0>,
<ST_MORPHO_R_5 0 &gpiob 7 0>,
<ST_MORPHO_R_6 0 &gpioc 5 0>,
<ST_MORPHO_R_11 0 &gpioa 5 0>,
/* By default, connected to USB connector (SB13=ON, SB17=ON) */
<ST_MORPHO_R_12 0 &gpioa 12 0>,
<ST_MORPHO_R_13 0 &gpioa 6 0>,
/* By default, connected to USB connector (SB13=ON, SB17=ON) */
<ST_MORPHO_R_14 0 &gpioa 11 0>,
<ST_MORPHO_R_15 0 &gpioa 7 0>,
<ST_MORPHO_R_16 0 &gpiob 12 0>,
<ST_MORPHO_R_17 0 &gpioc 9 0>,
<ST_MORPHO_R_19 0 &gpioc 6 0>,
<ST_MORPHO_R_21 0 &gpioc 7 0>,
<ST_MORPHO_R_22 0 &gpiob 2 0>,
<ST_MORPHO_R_23 0 &gpioa 8 0>,
<ST_MORPHO_R_24 0 &gpiob 1 0>,
<ST_MORPHO_R_25 0 &gpiob 10 0>,
<ST_MORPHO_R_26 0 &gpiob 15 0>,
<ST_MORPHO_R_27 0 &gpiob 4 0>,
<ST_MORPHO_R_28 0 &gpiob 14 0>,
<ST_MORPHO_R_29 0 &gpiob 5 0>,
<ST_MORPHO_R_30 0 &gpiob 13 0>,
<ST_MORPHO_R_31 0 &gpiob 3 0>,
<ST_MORPHO_R_33 0 &gpioa 10 0>,
<ST_MORPHO_R_34 0 &gpioc 4 0>,
<ST_MORPHO_R_35 0 &gpiob 14 0>,
<ST_MORPHO_R_36 0 &gpiob 8 0>,
<ST_MORPHO_R_37 0 &gpiob 15 0>;
};
};
``` | /content/code_sandbox/boards/st/nucleo_h503rb/st_morpho_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,231 |
```cmake
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(openocd "--tcl-port=6666")
board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable")
board_runner_args(openocd "--no-halt")
board_runner_args(pyocd "--target=stm32h503rbtx")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
# FIXME: official openocd runner not yet available.
``` | /content/code_sandbox/boards/st/nucleo_h503rb/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 152 |
```unknown
config BOARD_NUCLEO_H503RB
select SOC_STM32H503XX
``` | /content/code_sandbox/boards/st/nucleo_h503rb/Kconfig.nucleo_h503rb | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable clock
CONFIG_CLOCK_CONTROL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable GPIO
CONFIG_GPIO=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_h503rb/nucleo_h503rb_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```yaml
board:
name: nucleo_h503rb
vendor: st
socs:
- name: stm32h503xx
``` | /content/code_sandbox/boards/st/nucleo_h503rb/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: nucleo_h503rb
name: ST Nucleo H503RB
type: mcu
arch: arm
toolchain:
- zephyr
ram: 32
flash: 128
supported:
- arduino_gpio
- arduino_serial
- gpio
- uart
- i2c
- watchdog
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_h503rb/nucleo_h503rb.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 83 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h5/stm32h503Xb.dtsi>
#include <st/h5/stm32h503rbtx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include "st_morpho_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32H503RB-NUCLEO board";
compatible = "st,stm32h503rb-nucleo";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds: leds {
compatible = "gpio-leds";
green_led_2: led_2 {
gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_2;
sw0 = &user_button;
watchdog0 = &iwdg;
};
};
&clk_csi {
status = "okay";
};
&clk_hsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
};
&pll {
div-m = <2>;
mul-n = <40>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart3 {
pinctrl-0 = <&usart3_tx_pa4 &usart3_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rng {
status = "okay";
};
&iwdg {
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
clock-frequency = <I2C_BITRATE_FAST>;
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_h503rb/nucleo_h503rb.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 668 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 0 0>, /* A0 */
<1 0 &gpioa 1 0>, /* A1 */
<2 0 &gpioa 2 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpiob 15 0>, /* D0 */
<7 0 &gpiob 14 0>, /* D1 */
<8 0 &gpioa 10 0>, /* D2 */
<9 0 &gpiob 3 0>, /* D3 */
<10 0 &gpiob 5 0>, /* D4 */
<11 0 &gpiob 4 0>, /* D5 */
<12 0 &gpiob 10 0>, /* D6 */
<13 0 &gpioa 8 0>, /* D7 */
<14 0 &gpioc 7 0>, /* D8 */
<15 0 &gpioc 6 0>, /* D9 */
<16 0 &gpioc 9 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 7 0>, /* D14 */
<21 0 &gpiob 6 0>; /* D15 */
};
};
arduino_serial: &usart1 {};
arduino_i2c: &i2c1 {};
/* arduino_spi (SPI1) uses PA5, to which the user LED is connected */
``` | /content/code_sandbox/boards/st/nucleo_h503rb/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 516 |
```ini
source [find interface/stlink-dap.cfg]
source [find target/stm32h5x.cfg]
transport select "dapdirect_swd"
set CHIPNAME STM32H503RBTX
set BOARDNAME NUCLEO-STM32H503RB
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/nucleo_h503rb/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 157 |
```restructuredtext
.. _stm32h7s78_dk_board:
ST STM32H7S78-DK Discovery
##########################
Overview
********
The STM32H7S78-DK Discovery kit is designed as a complete demonstration and
development platform for STMicroelectronics Arm |reg| Cortex |reg|-M7 core-based
STM32H7S7L8H6H microcontroller with TrustZone |reg|. Here are some highlights of
the STM32H7S78-DK Discovery board:
- STM32H7S7L8H6H microcontroller featuring 64Kbytes of Flash memory and 620 Kbytes of SRAM in 225-pin TFBGA package
- USB Type-C |trade| Host and device with USB power-delivery controller
- SAI Audio DAC stereo with one audio jacks for input/output,
- ST MEMS digital microphone with PDM interface
- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX66UW1G45GXD100 from MACRONIX)
- 10/100-Mbit Ethernet,
- Board connectors
- STMod+ expansion connector with fan-out expansion board for WiFi |reg|, Grove and mikroBUS |trade| compatible connectors
- Pmod |trade| expansion connector
- Audio MEMS daughterboard expansion connector
- ARDUINO |reg| Uno V3 expansion connector
- Flexible power-supply options
- ST-LINK
- USB VBUS
- external sources
- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
- mass storage
- Virtual COM port
- debug port
- 4 user LEDs
- User and reset push-buttons
.. image:: img/stm32h7s78_dk.jpg
:align: center
:alt: STM32H7S78-DK Discovery
More information about the board can be found at the `STM32H7S78-DK Discovery website`_.
Hardware
********
The STM32H7S7xx devices are a high-performance microcontrollers family (STM32H7
Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core.
They operate at a frequency of up to 500 MHz.
- Core: ARM |reg| 32-bit Cortex |reg| -M7 CPU with TrustZone |reg| and FPU.
- Performance benchmark:
- 1284 DMPIS/MHz (Dhrystone 2.1)
- Security
- Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension
- Up to 8 configurable SAU regions
- TrustZone |reg| aware and securable peripherals
- Flexible lifecycle scheme with secure debug authentication
- Preconfigured immutable root of trust (ST-iROT)
- SFI (secure firmware installation)
- Secure data storage with hardware unique key (HUK)
- Secure firmware upgrade support with TF-M
- 2x AES coprocessors including one with DPA resistance
- Public key accelerator, DPA resistant
- On-the-fly decryption of Octo-SPI external memories
- HASH hardware accelerator
- True random number generator, NIST SP800-90B compliant
- 96-bit unique ID
- Active tampers
- True Random Number Generator (RNG) NIST SP800-90B compliant
- Clock management:
- 24 MHz crystal oscillator (HSE)
- 32768 Hz crystal oscillator for RTC (LSE)
- Internal 64 MHz (HSI) trimmable by software
- Internal low-power 32 kHz RC (LSI)( |plusminus| 5%)
- Internal 4 MHz oscillator (CSI), trimmable by software
- Internal 48 MHz (HSI48) with recovery system
- 3 PLLs for system clock, USB, audio, ADC
- Power management
- Embedded regulator (LDO) with three configurable range output to supply the digital circuitry
- Embedded SMPS step-down converter
- RTC with HW calendar, alarms and calibration
- Up to 152 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V
- Up to 16 timers and 2 watchdogs
- 16x 16-bit
- 4x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
- 5x 16-bit low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- 1x SysTick timer
- Memories
- Up to 64KB Flash, 2 banks read-while-write
- 1 Kbyte OTP (one-time programmable)
- 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC
- 4 Kbytes of backup SRAM available in the lowest power modes
- Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
- 2x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats
- 1x HEXASPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats
- 2x SD/SDIO/MMC interfaces
- Rich analog peripherals (independent supply)
- 2x 12-bit ADC with up to 5 MSPS in 12-bit
- 1x Digital temperature sensor
- 35x communication interfaces
- 1x USB Type-C / USB power-delivery controller
- 1x USB OTG full-speed with PHY
- 1x USB OTG high-speed with PHY
- 3x I2C FM+ interfaces (SMBus/PMBus)
- 1x I3C interface
- 7x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control)
- 2x LP UART
- 6x SPIs including 3 muxed with full-duplex I2S
- 2x SAI
- 2x FDCAN
- 2x SD/SDIO/MMC interface
- 2x 16 channel DMA controllers
- 1x 8- to 16- bit camera interface
- 1x HDMI-CEC
- 1x Ethernel MAC interface with DMA controller
- 1x 16-bit parallel slave synchronous-interface
- 1x SPDIF-IN interface
- 1x MDIO slave interface
- CORDIC for trigonometric functions acceleration
- FMAC (filter mathematical accelerator)
- CRC calculation unit
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
More information about STM32H7S7 can be found here:
- `STM32H7Sx on www.st.com`_
- `STM32H7Sx reference manual`_
Supported Features
==================
The Zephyr STM32H7S78_DK board configuration supports the following
hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi bus |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig and dts files:
- Secure target:
- :zephyr_file:`boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig`
- :zephyr_file:`boards/st/stm32h7s78_dk/stm32h7s78_dk.dts`
Zephyr board options
====================
The STM32HS7 is a SoC with Cortex-M7 architecture. Zephyr provides support
for building for Secure firmware.
The BOARD options are summarized below:
+----------------------+-----------------------------------------------+
| BOARD | Description |
+======================+===============================================+
| stm32h7s78_dk | For building Secure firmware |
+----------------------+-----------------------------------------------+
Connections and IOs
===================
STM32H7S78-DK Discovery Board has 12 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32H7S78-DK Discovery board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- USART_4 TX/RX : PD1/PD0 (VCP)
- USART_7 TX/RX : PE8/PE7 (Arduino USART7)
- USER_PB : PC13
- LD1 (green) : PO1
- LD2 (orange) : PO5
- LD3 (red) : PM2
- LD4 (blue) : PM3
- ADC1 channel 6 input : PF12
System Clock
------------
STM32H7S78-DK System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at
500MHz, driven by 24MHz external oscillator (HSE).
Serial Port
-----------
STM32H7S78-DK Discovery board has 2 U(S)ARTs. The Zephyr console output is
assigned to USART4. Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``stm32h7s78_dk`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
STM32H7S78-DK Discovery board includes an ST-LINK/V3E embedded debug tool
interface. Support is available on STM32CubeProgrammer V2.13.0.
Alternatively, this interface will be supported by a next openocd version.
Flashing an application to STM32H7S78-DK Discovery
--------------------------------------------------
Connect the STM32H7S78-DK Discovery to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h7s78_dk
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! stm32h7s78_dk
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h7s78_dk
:maybe-skip-config:
:goals: debug
.. _STM32H7S78-DK Discovery website:
path_to_url
.. _STM32H7S78-DK Discovery board User Manual:
path_to_url
.. _STM32H7Sx on www.st.com:
path_to_url
.. _STM32H7Sx reference manual:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
``` | /content/code_sandbox/boards/st/stm32h7s78_dk/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,743 |
```cmake
board_runner_args(jlink "--device=STM32F401CC" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/steval_fcu001v1/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f4/stm32f401Xc.dtsi>
#include <st/f4/stm32f401c(b-c)ux-pinctrl.dtsi>
/ {
model = "STMicroelectronics Flight Controller Board";
compatible = "st,flight-controller-board";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
red_led_1: led_1 {
gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
red_led_2: led_2 {
gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
aliases {
led0 = &red_led_1;
led1 = &red_led_2;
watchdog0 = &iwdg;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <16>;
mul-n = <336>;
div-p = <4>;
div-q = <7>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(84)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <1>;
};
&i2c2 {
pinctrl-0 = <&i2c2_sda_pb3 &i2c2_scl_pb10>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&timers2 {
status = "okay";
pwm2: pwm {
status = "okay";
pinctrl-0 = <&tim2_ch1_pa0>;
pinctrl-names = "default";
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&iwdg {
status = "okay";
};
``` | /content/code_sandbox/boards/st/steval_fcu001v1/steval_fcu001v1.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 587 |
```yaml
identifier: steval_fcu001v1
name: ST STM32 Flight Controller Unit
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- gpio
- pwm
- i2c
- rtc
- watchdog
ram: 64
flash: 256
vendor: st
``` | /content/code_sandbox/boards/st/steval_fcu001v1/steval_fcu001v1.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 88 |
```yaml
board:
name: steval_fcu001v1
vendor: st
socs:
- name: stm32f401xc
``` | /content/code_sandbox/boards/st/steval_fcu001v1/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config BOARD_STEVAL_FCU001V1
select SOC_STM32F401XC
``` | /content/code_sandbox/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
CONFIG_SERIAL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
set WORKAREASIZE 0x10000
source [find target/stm32f4x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/steval_fcu001v1/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```restructuredtext
.. _nucleo_h503rb_board:
ST Nucleo H503RB
################
Overview
********
The Nucleo-H503RB board features an ARM |reg| Cortex |reg|-M33 core-based
STM32H503RBT6 microcontroller with a wide range of connectivity support and
configurations.
Here are some highlights of the Nucleo-H503RB board:
- STM32H503RB microcontroller featuring 128 Kbytes of Flash memory and 32 Kbytes of
SRAM in LQFP64 package
- Board connectors:
- User USB Type-C |reg|
- MIPI10 for debugging (SWD/JTAG)
- Arduino |reg| Uno V3 connectivity (CN5, CN6, CN8, CN9)
- ST morpho extension connector (CN7, CN10)
- Flexible board power supply:
- ST-LINK USB VBUS
- user USB connector
- external sources
- On-board ST-LINK/V3EC debugger/programmer:
- mass storage
- Virtual COM port
- debug port
- One user LED shared with ARDUINO |reg| Uno V3
- Two push-buttons: USER and RESET
- 32.768 kHz crystal oscillator
- 24 MHz HSE crystal oscillator
More information about the board can be found at the `NUCLEO_H503RB website`_.
.. image:: img/nucleo_h503rb.png
:align: center
:alt: NUCLEO-H503RB
Hardware
********
The STM32H503xx devices are a high-performance microcontrollers family
(STM32H5 series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit
RISC core. They operate at a frequency of up to 250 MHz.
- Core: Arm |reg| Cortex |reg|-M33 CPU with FPU, MPU, 375 DMIPS (Dhrystone 2.1),
and DSP instructions
- ART Accelerator
- Memories
- 128 Kbytes of embedded flash memory with ECC, two banks of read-while-write
- 2-Kbyte OTP (one-time programmable)
- 32-Kbyte SRAM with ECC
- 2 Kbytes of backup SRAM (available in the lowest power modes)
- Clock management
- Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
- Two PLLs for system clock, USB, audio, and ADC
- External oscillators: 4 to 50 MHz HSE, 32.768 kHz LSE
- Embedded regulator (LDO)
- Up to 49 fast I/Os (most 5 V tolerant), up to 9 I/Os with independent supply down to 1.08 V
- Analog peripherals
- 1x 12-bit ADC with up to 2.5 MSPS
- 1x 12-bit dual-channel DAC
- 1x ultra-low-power comparator
- 1x operational amplifier (7 MHz bandwidth)
- 1x Digital temperature sensor
- Up to 11 timers
- 4x 16-bit
- 1x 32-bit
- 2x 16-bit low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- 1x SysTick timer
- RTC with HW calendar, alarms and calibration
- Up to 16x communication interfaces
- Up to 2x I2Cs FM + interfaces (SMBus/PMBus |reg|)
- Up to 2x I3Cs shared with I2C
- Up to 3x USARTs (ISO7816 interface, LIN, IrDA, modem control)
- 1x LPUART
- Up to 3x SPIs including three muxed with full-duplex I2S
- Up to 3x additional SPI from 3x USART when configured in synchronous mode
- 1x FDCAN
- 1x USB 2.0 full-speed host and device
- Two DMA controllers to offload the CPU
- Security
- HASH (SHA-1, SHA-2), HMAC
- True random generator
- 96-bit unique ID
- Active tamper
- Development support: serial wire debug (SWD) and JTAG interfaces
More information about STM32H533RE can be found here:
- `STM32H503rb on www.st.com`_
- `STM32H503 reference manual`_
Supported Features
==================
The Zephyr nucleo_h503rb board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c bus |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig and dts files:
- :zephyr_file:`boards/st/nucleo_h503rb/nucleo_h503rb_defconfig`
- :zephyr_file:`boards/st/nucleo_h503rb/nucleo_h503rb.dts`
Connections and IOs
===================
Nucleo-H503RB board has 8 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32H5 Nucleo-64 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- USART1 TX/RX : PB14/PB15 (Arduino USART1)
- SPI1 SCK/MISO/MOSI/NSS: PA5/PA6/PA7/PC9
- USART3 TX/RX : PA3/PA4 (VCP)
- USER_PB : PC13
- User LED (green): PA5
System Clock
------------
Nucleo H533RE System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at
240 MHz, driven by an 24 MHz high-speed external clock.
Serial Port
-----------
Nucleo H533RE board has up to 3 U(S)ARTs. The Zephyr console output is assigned
to USART3. Default settings are 115200 8N1.
Programming and Debugging
*************************
Applications for the ``nucleo_h503rb`` board can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
OpenOCD Support
===============
For now, openocd support for stm32h5 is not available on upstream OpenOCD.
You can check `OpenOCD official Github mirror`_.
In order to use it though, you should clone from the cutomized
`STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines.
Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in
:zephyr_file:`boards/st/nucleo_h563zi/board.cmake` to point the build
to the paths of the OpenOCD binary and its scripts, before
including the common openocd.board.cmake file:
.. code-block:: none
set(OPENOCD "<path_to_openocd_repo>/src/openocd" CACHE FILEPATH "" FORCE)
set(OPENOCD_DEFAULT_PATH <path_to_opneocd_repo>/tcl)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
Flashing
========
Nucleo-H503RB board includes an ST-LINK/V3EC embedded debug tool interface.
This probe allows to flash the board using various tools.
Board is configured to be flashed using west STM32CubeProgrammer runner.
Installation of `STM32CubeProgrammer`_ is then required to flash the board.
Alternatively, pyocd can also be used to flash and debug the board
if west is told to use it as runner, which can be done by
passing ``-r pyocd``.
For pyocd additional target information needs to be installed.
This can be done by executing the following commands.
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32h5
Alternatively, the openocd interface will be supported by a next openocd version.
When available, OpenOCD could be used in the same way as other tools.
Flashing an application to Nucleo-H503RB
------------------------------------------
Connect the Nucleo-H503RB to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_h503rb
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! nucleo_h503rb/stm32h503xx
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_h503rb
:goals: debug
.. _NUCLEO_H503RB website:
path_to_url
.. _STM32H5 Nucleo-64 board User Manual:
path_to_url
.. _STM32H503RB on www.st.com:
path_to_url
.. _STM32H503 reference manual:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _OpenOCD official Github mirror:
path_to_url
.. _STMicroelectronics OpenOCD Github:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_h503rb/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,367 |
```unknown
config BOARD_STM32H735G_DISCO
select SOC_STM32H735XX
``` | /content/code_sandbox/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```cmake
board_runner_args(jlink "--device=STM32H735IG" "--speed=4000")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32h735g_disco/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```restructuredtext
.. _steval_fcu001v1:
ST STM32 Flight Controller Unit
###############################
Overview
********
The STEVAL-FCU001V1 is a Cortex M4 MCU-based flight controller unit for toy quad-copter drones.
.. figure:: img/steval_fcu001v1.jpg
:align: center
:alt: STM32 Flight Controller Unit
Hardware
********
STM32 Flight Controller Unit provides the following hardware components:
- STM32F401CC in UFQFPN48 package
- ARM |reg| 32-bit Cortex |reg|-M4 MCU with FPU
- 84MHz max MCU frequency
- VDD from 1.7 V to 3.6 V
- 256 KB FLASH
- 64 KB SRAM
- General Purpose Timers
- Watchdog Timers (2)
- On board sensors:
- 3D Accelerometer and 3D Gyroscope: LSM6DSL
- 3D Magnetometer: LIS2MDL
- MEMS Pressure sensor: LPS22HD
- 2 User LEDS
- USART/UART (1)
- I2C (1)
- Bluetooth LE over SPI
More information about the STM32 Flight Controller Unit
can be found in these documents:
- `STEVAL_FCU001V1 website`_
- `STM32F401 reference manual`_
- `STM32F401CC on www.st.com`_
Supported Features
==================
The Zephyr steval_fcu001v1 board configuration supports the following hardware features:
+-----------+------------+------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+------------------------------------+
The default configuration can be found in
:zephyr_file:`boards/st/steval_fcu001v1/steval_fcu001v1_defconfig`
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PA9/PA10
- I2C2 SCL/SDA : PB10/PB3
- PWM_2_CH1 : PA0
- LD1 : PB5
- LD2 : PB4
System Clock
============
The steval_fcu001v1 system clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the system clock is driven by the PLL clock at 84MHz,
driven by a 16MHz high-speed external clock.
Serial Port
===========
The steval_fcu001v1 board has one UART. The Zephyr console output is assigned to UART1.
Default settings are 115200 8N1.
I2C
===
The steval_fcu001v1 board has one I2C. The default I2C mapping for Zephyr is:
- I2C2_SCL : PB10
- I2C2_SDA : PB3
Programming and Debugging
*************************
Applications for the ``steval_fcu001v1`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Flashing Zephyr onto the steval_fcu001v1 board requires an external ST-LINK/V2-1 programmer.
The programmer is attached to the P8 programming header with ARM-JTAG-20-10-Plug-in Adapter.
Flashing an application to STEVAL_FCU001V1
------------------------------------------
Connect the FT232-to-USB port to host system, and RX, TX, Gnd pins to
the P7 header of the steval_fcu001v1 board. Then run a serial host
program to connect with your steval_fcu001v1 via the FT232 board:
.. code-block:: console
$ minicom -D /dev/ttyUSB0
Now build and flash an application. Here is an example for :ref:`hello_world`
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: steval_fcu001v1
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! steval_fcu001v1
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: steval_fcu001v1
:maybe-skip-config:
:goals: debug
.. _STEVAL_FCU001V1 website:
path_to_url
.. _STM32F401CC on www.st.com:
path_to_url
.. _STM32F401 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/steval_fcu001v1/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,172 |
```yaml
identifier: stm32h735g_disco
name: ST STM32H735G Discovery
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 368
flash: 1024
supported:
- arduino_gpio
- gpio
- netif:eth
- memc
- adc
- counter
- can
- usb_device
vendor: st
``` | /content/code_sandbox/boards/st/stm32h735g_disco/stm32h735g_disco.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 107 |
```unknown
/*
*
*/
/ {
pmod0: pmod-connector {
compatible = "digilent,pmod";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpiof 9 0>, /* IO1 */
<1 0 &gpiof 7 0>, /* IO2 */
<2 0 &gpiof 6 0>, /* IO3 */
<3 0 &gpiof 8 0>, /* IO4 */
<4 0 &gpioh 12 0>, /* IO5 */
<5 0 &gpioh 1 0>; /* IO6 */
/* IO7 - not connected */
/* IO8 - not connected */
};
};
``` | /content/code_sandbox/boards/st/stm32h735g_disco/pmod_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 196 |
```yaml
board:
name: stm32h735g_disco
vendor: st
socs:
- name: stm32h735xx
``` | /content/code_sandbox/boards/st/stm32h735g_disco/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
# Enable the internal SMPS regulator
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
CONFIG_SERIAL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 85 |
```unknown
# STM32H735G DISCOVERY board configuration
if BOARD_STM32H735G_DISCO
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_STM32H735G_DISCO
``` | /content/code_sandbox/boards/st/stm32h735g_disco/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```ini
source [find interface/stlink-dap.cfg]
transport select dapdirect_swd
set WORKAREASIZE 0x2000
set CHIPNAME STM32H735IG
set BOARDNAME STM23H735G_DK
source [find target/stm32h7x.cfg]
# Use connect_assert_srst here to be able to program
# even when core is in sleep mode
reset_config srst_only srst_nogate connect_assert_srst
$_CHIPNAME.cpu0 configure -event gdb-attach {
echo "Debugger attaching: halting execution"
gdb_breakpoint_override hard
}
$_CHIPNAME.cpu0 configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/stm32h735g_disco/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 199 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h735Xg.dtsi>
#include <st/h7/stm32h735igkx-pinctrl.dtsi>
#include "pmod_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32H735G DISCOVERY board";
compatible = "st,stm32h735g-disco";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &fdcan1;
};
leds {
compatible = "gpio-leds";
red_led: led_1 {
gpios = <&gpioc 2 GPIO_ACTIVE_LOW>;
label = "User LD2";
};
green_led: led_2 {
gpios = <&gpioc 3 GPIO_ACTIVE_LOW>;
label = "User LD1";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &red_led;
led1 = &green_led;
sw0 = &user_button;
volt-sensor1 = &vbat;
};
};
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&pll {
div-m = <5>;
mul-n = <110>;
div-p = <1>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&pll2 {
div-m = <5>;
mul-n = <80>;
div-p = <5>;
div-q = <5>;
div-r = <5>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(550)>;
d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&uart7 {
pinctrl-0 = <&uart7_tx_pf7 &uart7_rx_pf6>;
pinctrl-names = "default";
current-speed = <115200>;
};
&i2c4 {
pinctrl-0 = <&i2c4_scl_pf14 &i2c4_sda_pf15>;
pinctrl-names = "default";
};
&rng {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_inp0_pa0_c>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&mac {
pinctrl-0 = <ð_rxd0_pc4
ð_rxd1_pc5
ð_ref_clk_pa1
ð_crs_dv_pa7
ð_tx_en_pb11
ð_txd0_pb12
ð_txd1_pb13>;
pinctrl-names = "default";
status = "okay";
};
&mdio {
status = "okay";
pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};
&sdmmc1 {
pinctrl-0 = <&sdmmc1_d0_pc8
&sdmmc1_d1_pc9
&sdmmc1_d2_pc10
&sdmmc1_d3_pc11
&sdmmc1_ck_pc12
&sdmmc1_cmd_pd2>;
pinctrl-names = "default";
cd-gpios = <&gpiof 5 GPIO_ACTIVE_LOW>;
};
&octospi1 {
pinctrl-0 = <&octospim_p1_clk_pf10 &octospim_p1_ncs_pg6
&octospim_p1_io0_pd11 &octospim_p1_io1_pd12
&octospim_p1_io2_pe2 &octospim_p1_io3_pd13
&octospim_p1_io4_pd4 &octospim_p1_io5_pd5
&octospim_p1_io6_pg9 &octospim_p1_io7_pd7
&octospim_p1_dqs_pb2>;
pinctrl-names = "default";
status = "okay";
mx25lm51245: ospi-nor-flash@90000000 {
compatible = "st,stm32-ospi-nor";
reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <OSPI_OPI_MODE>;
data-rate = <OSPI_DTR_TRANSFER>;
status = "okay";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "nor";
reg = <0x00000000 DT_SIZE_M(4)>;
};
};
};
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
backup_regs {
status = "okay";
};
};
&fdcan1 {
pinctrl-0 = <&fdcan1_rx_ph14 &fdcan1_tx_ph13>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
status = "okay";
can-transceiver {
max-bitrate = <8000000>;
};
};
&fdcan2 {
pinctrl-0 = <&fdcan2_rx_pb5 &fdcan2_tx_pb6>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
status = "okay";
can-transceiver {
max-bitrate = <8000000>;
};
};
&fdcan3 {
pinctrl-0 = <&fdcan3_rx_pf6 &fdcan3_tx_pf7>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
<&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
/* Solder bridges SB29 and SB30 need to be closed for this to work */
status = "disabled";
can-transceiver {
max-bitrate = <8000000>;
};
};
zephyr_udc0: &usbotg_hs {
status = "okay";
pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/st/stm32h735g_disco/stm32h735g_disco.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,746 |
```cmake
board_runner_args(jlink "--device=STM32F207ZG" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f207zg/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```yaml
identifier: nucleo_f207zg
name: ST Nucleo F207ZG
type: mcu
arch: arm
ram: 128
flash: 1024
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- arduino_gpio
- arduino_i2c
- arduino_spi
- i2c
- spi
- gpio
- usb_device
- watchdog
- counter
- adc
- dac
- backup_sram
- pwm
- rng
- dma
- rtc
- usbd
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f207zg/nucleo_f207zg.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```unknown
config BOARD_NUCLEO_F207ZG
select SOC_STM32F207XX
``` | /content/code_sandbox/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```yaml
board:
name: nucleo_f207zg
vendor: st
socs:
- name: stm32f207xx
``` | /content/code_sandbox/boards/st/nucleo_f207zg/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
CONFIG_SERIAL=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```restructuredtext
.. _stm32h735g_disco_board:
ST STM32H735G Discovery
#######################
Overview
********
The STM32H735G-DK Discovery kit is a complete demonstration and development
platform for Arm Cortex-M7 core-based STM32H735IGK6U microcontroller, with
1 Mbyte of Flash memory and 564 Kbytes of SRAM.
The STM32H735G-DK Discovery kit is used as a reference design for user
application development before porting to the final product, thus simplifying
the application development.
The full range of hardware features available on the board helps users to enhance
their application development by an evaluation of all the peripherals (such as
USB OTG FS, Ethernet, microSD card, USART, CAN FD, SAI audio DAC stereo with
audio jack input and output, MEMS digital microphone, HyperRAM,
Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others).
ARDUINO Uno V3, Pmod and STMod+ connectors provide easy connection to extension
shields or daughterboards for specific applications.
STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and
programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK board
comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive
software HAL library as well as various software examples.
.. image:: img/stm32h735g_disco.jpg
:align: center
:alt: STM32H735G-DISCO
More information about the board can be found at the `STM32H735G-DISCO website`_.
More information about STM32H735 can be found here:
- `STM32H725/735 on www.st.com`_
- `STM32H735xx reference manual`_
- `STM32H735xx datasheet`_
Supported Features
==================
The current Zephyr stm32h735g_disco board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| FMC | on-chip | memc (SDRAM) |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC Controller |
+-----------+------------+-------------------------------------+
| FDCAN1 | on-chip | CAN-FD Controller |
+-----------+------------+-------------------------------------+
| FDCAN2 | on-chip | CAN-FD Controller |
+-----------+------------+-------------------------------------+
| FDCAN3 | on-chip | CAN-FD Controller (disabled by |
| | | default. Solder bridges SB29 and |
| | | SB30 need to be closed for FDCAN3 |
| | | to work) |
+-----------+------------+-------------------------------------+
| USB | on-chip | usb_device |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/stm32h735g_disco/stm32h735g_disco_defconfig`
Pin Mapping
===========
For more details please refer to `STM32H735G-DISCO website`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
- UART_7 TX/RX : PF7/PF6 (Arduino Serial)
- LD1 : PC2
- LD2 : PC3
- FDCAN1 : CAN
System Clock
============
The STM32H735G System Clock can be driven by an internal or external oscillator,
as well as by the main PLL clock. By default, the System clock
is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock.
Serial Port
===========
The STM32H735G Discovery kit has up to 6 UARTs.
The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual
COM port interface. Default communication settings are 115200 8N1.
Programming and Debugging
*************************
See :ref:`build_an_application` for more information about application builds.
Flashing
========
Flashing operation will depend on the target to be flashed and the SoC
option bytes configuration.
It is advised to use `STM32CubeProgrammer`_ to check and update option bytes
configuration and flash the ``stm32h735g_disco`` target.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32h735g_disco
:goals: debug
.. _STM32H735G-DISCO website:
path_to_url
.. _STM32H725/735 on www.st.com:
path_to_url
.. _STM32H735xx reference manual:
path_to_url
.. _STM32H735xx datasheet:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
``` | /content/code_sandbox/boards/st/stm32h735g_disco/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,315 |
```unknown
# NUCLEO-144 F207ZG board configuration
if BOARD_NUCLEO_F207ZG
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_NUCLEO_F207ZG
``` | /content/code_sandbox/boards/st/nucleo_f207zg/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioc 0 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiof 3 0>, /* A3 */
<4 0 &gpiof 5 0>, /* A4 */
<5 0 &gpiof 10 0>, /* A5 */
<6 0 &gpiog 9 0>, /* D0 */
<7 0 &gpiog 14 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &usart6 {};
``` | /content/code_sandbox/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 497 |
```ini
source [find interface/stlink.cfg]
source [find target/stm32f2x.cfg]
reset_config srst_only srst_nogate
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f207zg/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f2/stm32f207Xg.dtsi>
#include <st/f2/stm32f207z(c-e-f-g)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F207ZG-NUCLEO board";
compatible = "st,stm32f207zg-nucleo";
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds: leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led_1: led_2 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led_1: led_3 {
gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
pwmleds {
compatible = "pwm-leds";
green_pwm_led: led_pwm_1 {
pwms = <&pwm3 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "Green PWM LED";
};
blue_pwm_led: led_pwm_2 {
pwms = <&pwm4 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "Blue PWM LED";
};
red_pwm_led: led_pwm_0 {
pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "Red PWM LED";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_1;
led1 = &blue_led_1;
led2 = &red_led_1;
pwm-led0 = &green_pwm_led;
pwm-led1 = &blue_pwm_led;
pwm-led2 = &red_pwm_led;
green-pwm-led = &green_pwm_led;
blue-pwm-led = &blue_pwm_led;
red-pwm-led = &red_pwm_led;
sw0 = &user_button;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <240>;
div-p = <2>;
div-q = <5>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(120)>;
ahb-prescaler = <1>;
apb1-prescaler = <4>;
apb2-prescaler = <2>;
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart6 {
pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&iwdg {
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&rng {
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in0_pa0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <2>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dma2 {
status = "okay";
};
&mac {
status = "okay";
pinctrl-0 = <ð_mdc_pc1
ð_rxd0_pc4
ð_rxd1_pc5
ð_ref_clk_pa1
ð_mdio_pa2
ð_crs_dv_pa7
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pb13>;
pinctrl-names = "default";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Last sector of size 128KB at the end of 1MB flash is set
* for storage.
*/
storage_partition: partition@e0000 {
label = "storage";
reg = <0x000e0000 DT_SIZE_K(128)>;
};
};
};
&dac1 {
status = "okay";
pinctrl-0 = <&dac_out1_pa4>;
pinctrl-names = "default";
};
&backup_sram {
status = "okay";
};
&timers1 {
status = "okay";
pwm1: pwm {
status = "okay";
pinctrl-0 = <&tim1_ch1_pe9>;
pinctrl-names = "default";
};
};
&timers3 {
status = "okay";
st,prescaler = <10000>;
pwm3: pwm {
status = "okay";
pinctrl-0 = <&tim3_ch3_pb0>;
pinctrl-names = "default";
};
};
&timers4 {
status = "okay";
st,prescaler = <10000>;
pwm4: pwm {
status = "okay";
pinctrl-0 = <&tim4_ch2_pb7>;
pinctrl-names = "default";
};
};
&timers12 {
status = "okay";
st,prescaler = <10000>;
pwm12: pwm {
status = "okay";
pinctrl-0 = <&tim12_ch1_pb14>;
pinctrl-names = "default";
};
};
``` | /content/code_sandbox/boards/st/nucleo_f207zg/nucleo_f207zg.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,715 |
```cmake
board_runner_args(openocd --cmd-post-verify "reset halt")
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
board_runner_args(jlink "--device=STM32H743ZI" "--speed=4000")
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
board_runner_args(pyocd "--target=stm32h743zitx")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_h743zi/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 165 |
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