text stringlengths 9 39.2M | dir stringlengths 25 226 | lang stringclasses 163 values | created_date timestamp[s] | updated_date timestamp[s] | repo_name stringclasses 751 values | repo_full_name stringclasses 752 values | star int64 1.01k 183k | len_tokens int64 1 18.5M |
|---|---|---|---|---|---|---|---|---|
```unknown
/*
*
*/
#include <st/u5/stm32u575Xi.dtsi>
#include <st/u5/stm32u575zitxq-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
leds: leds {
compatible = "gpio-leds";
green_led_1: led_1 {
gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
blue_led_1: led_2 {
gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
red_led_1: led_3 {
gpios = <&gpiog 2 GPIO_ACTIVE_HIGH>;
label = "User LD3";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds: pwmleds {
compatible = "pwm-leds";
status = "disabled";
pwm_led_1: green_led_1 {
pwms = <&pwm3 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "green led";
};
pwm_led_2: blue_led_1 {
pwms = <&pwm4 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "blue led";
};
};
};
&clk_hsi48 {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_msis {
status = "okay";
msi-range = <4>;
msi-pll-mode;
};
&pll1 {
div-m = <1>;
mul-n = <80>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_msis>;
status = "okay";
};
&rcc {
clocks = <&pll1>;
clock-frequency = <DT_FREQ_M(160)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pg7 &lpuart1_rx_pg8>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
pinctrl-0 = <&i2c2_scl_pf1 &i2c2_sda_pf0>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&spi1 {
pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
&spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&dac1 {
/* CAUTION: DAC on PA4 may conflict with SPI1 NSS on same pin */
pinctrl-0 = <&dac1_out1_pa4>;
pinctrl-names = "default";
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in1_pc0>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&adc4 {
pinctrl-0 = <&adc4_in18_pb0>;
pinctrl-names = "default";
st,adc-clock-source = <ASYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&timers3 {
st,prescaler = <10000>;
status = "okay";
pwm3: pwm {
pinctrl-0 = <&tim3_ch2_pc7>;
pinctrl-names = "default";
status = "okay";
};
};
&timers4 {
st,prescaler = <10000>;
status = "okay";
pwm4: pwm {
pinctrl-0 = <&tim4_ch2_pb7>;
pinctrl-names = "default";
status = "okay";
};
};
&iwdg {
status = "okay";
};
&rng {
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&fdcan1 {
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
<&rcc STM32_SRC_PLL1_Q FDCAN1_SEL(1)>;
pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
<&rcc STM32_SRC_LSE RTC_SEL(1)>;
status = "okay";
};
&vref1 {
status = "okay";
};
&vbat4 {
status = "okay";
};
&clk_lsi {
status = "okay";
};
stm32_lp_tick_source: &lptim1 {
clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000800>,
<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,351 |
```yaml
board:
name: nucleo_u575zi_q
vendor: st
socs:
- name: stm32u575xx
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: nucleo_u575zi_q
name: ST Nucleo U575ZI Q
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
supported:
- arduino_gpio
- arduino_i2c
- arduino_serial
- arduino_spi
- can
- adc
- dac
- gpio
- i2c
- spi
- usart
- watchdog
- backup_sram
- dma
- rtc
ram: 786
flash: 2048
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 139 |
```unknown
config BOARD_NUCLEO_U575ZI_Q
select SOC_STM32U575XX
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioa 2 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpiog 8 0>, /* D0 */
<7 0 &gpiog 7 0>, /* D1 */
<8 0 &gpiof 15 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpiof 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioe 9 0>, /* D6 */
<13 0 &gpiof 13 0>, /* D7 */
<14 0 &gpiof 12 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
arduino_serial: &lpuart1 {};
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 500 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# Enable clock
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 73 |
```unknown
/*
*
*/
/dts-v1/;
#include "nucleo_u575zi_q-common.dtsi"
/ {
model = "STMicroelectronics STM32U575ZI-NUCLEO-Q board";
compatible = "st,stm32u575zi-nucleo-q";
#address-cells = <1>;
#size-cells = <1>;
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &fdcan1;
};
aliases {
led0 = &blue_led_1;
sw0 = &user_button;
pwm-led0 = &pwm_led_1;
pwm-led1 = &pwm_led_2;
watchdog0 = &iwdg;
volt-sensor0 = &vref1;
volt-sensor1 = &vbat4;
};
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&gpdma1 {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 291 |
```ini
source [find interface/stlink-dap.cfg]
set WORKAREASIZE 0x8000
transport select "dapdirect_swd"
set CHIPNAME STM32U575ZITxQ
set BOARDNAME NUCLEO-U575ZI-Q
# Enable debug when in low power modes
set ENABLE_LOW_POWER 1
# Stop Watchdog counters when halt
set STOP_WATCHDOG 1
# STlink Debug clock frequency
set CLOCK_FREQ 8000
# Reset configuration
# use hardware reset, connect under reset
# connect_assert_srst needed if low power mode application running (WFI...)
reset_config srst_only srst_nogate connect_assert_srst
set CONNECT_UNDER_RESET 1
set CORE_RESET 0
# ACCESS PORT NUMBER
set AP_NUM 0
# GDB PORT
set GDB_PORT 3333
# BCTM CPU variables
source [find target/stm32u5x.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 254 |
```unknown
# STM32H745ZI Nucleo board configuration
config BOARD_NUCLEO_H745ZI_Q
select SOC_STM32H745XX_M7 if BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7
select SOC_STM32H745XX_M4 if BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```cmake
board_runner_args(jlink "--device=STM32H745ZI" "--speed=4000")
if(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7)
board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
elseif(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4)
board_runner_args(openocd --target-handle=_CHIPNAME.cpu1)
endif()
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 130 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h745Xi_m7.dtsi>
#include "nucleo_h745zi_q.dtsi"
/*
* WARNING:
* Possible pin conflicts: The pins PA2 and PB13 may conflict on selection of
* ETH_STM32_HAL, since they are used in ST Zio or ST morpho connectors. To
* avoid conflicting states the jumpers JP6 and JP7 must be in ON state.
*/
/ {
model = "STMicroelectronics STM32H745ZI-Q-NUCLEO board";
compatible = "st,stm32h745zi-q-nucleo";
/* HW resources belonging to CM7 */
chosen {
zephyr,console = &usart3;
zephyr,shell-uart = &usart3;
zephyr,dtcm = &dtcm;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
pwmleds {
compatible = "pwm-leds";
red_pwm_led: red_pwm_led {
pwms = <&pwm12 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
label = "User LD3 - PWM12";
};
};
aliases {
led0 = &green_led;
pwm-led0 = &red_pwm_led;
sw0 = &user_button;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <120>;
div-p = <2>;
div-q = <8>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(480)>;
};
&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00010000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&timers12 {
st,prescaler = <10000>;
status = "okay";
pwm12: pwm {
status = "okay";
pinctrl-0 = <&tim12_ch1_pb14>;
pinctrl-names = "default";
};
};
&mac {
status = "okay";
pinctrl-0 = <ð_ref_clk_pa1
ð_crs_dv_pa7
ð_rxd0_pc4
ð_rxd1_pc5
ð_tx_en_pg11
ð_txd0_pg13
ð_txd1_pb13>;
pinctrl-names = "default";
};
&mdio {
status = "okay";
pinctrl-0 = <ð_mdio_pa2 ð_mdc_pc1>;
pinctrl-names = "default";
ethernet-phy@0 {
compatible = "ethernet-phy";
reg = <0x00>;
status = "okay";
};
};
&rng {
status = "okay";
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 868 |
```yaml
identifier: nucleo_h745zi_q/stm32h745xx/m4
name: ST Nucleo H745ZI-Q (M4)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 288
flash: 1024
supported:
- arduino_gpio
- gpio
- netif:eth
testing:
ignore_tags:
- mpu
- nfc
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 113 |
```unknown
# Enable GPIO
CONFIG_GPIO=y
# Enable clock
CONFIG_CLOCK_CONTROL=y
# By default SERIAL peripherals are assigned to m7
# Enable uart driver
#CONFIG_SERIAL=y
# Console
#CONFIG_CONSOLE=y
#CONFIG_UART_CONSOLE=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 64 |
```unknown
/*
*
*/
#include <st/h7/stm32h745zitx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
leds: leds {
compatible = "gpio-leds";
green_led: led_1 {
gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
yellow_led: led_2 {
gpios = <&gpioe 1 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button_0 {
gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
label = "User SB1";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&rcc {
d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
&mailbox {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 260 |
```yaml
board:
name: nucleo_h745zi_q
vendor: st
socs:
- name: stm32h745xx
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```unknown
# Enable the internal SMPS regulator
CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Enable UART ( disable to assign to M4 core)
CONFIG_SERIAL=y
# Console ( disable to assign to M4 core)
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clock
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 104 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/h7/stm32h745Xi_m4.dtsi>
#include "nucleo_h745zi_q.dtsi"
/ {
model = "STMicroelectronics STM32H745ZI-Q-NUCLEO board";
compatible = "st,stm32h745zi-q-nucleo";
/* HW resources belonging to CM4 */
chosen {
zephyr,console = &uart8;
zephyr,shell-uart = &uart8;
zephyr,sram = &sram1;
zephyr,flash = &flash1;
};
aliases {
led0 = &yellow_led;
};
};
&uart8 {
pinctrl-0 = <&uart8_tx_pe1 &uart8_rx_pe0>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rcc {
clock-frequency = <DT_FREQ_M(240)>;
};
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 212 |
```unknown
# STM32H745ZI Nucleo board configuration
if BOARD_NUCLEO_H745ZI_Q
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # BOARD_NUCLEO_H745ZI_Q
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 59 |
```yaml
identifier: nucleo_h745zi_q/stm32h745xx/m7
name: ST Nucleo H745ZI-Q (M7)
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 512
flash: 1024
supported:
- arduino_gpio
- arduino_i2c
- uart
- gpio
- counter
- i2c
- pwm
- netif:eth
- usb_device
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 128 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 3 0>, /* A0 */
<1 0 &gpioc 0 0>, /* A1 */
<2 0 &gpioc 3 0>, /* A2 */
<3 0 &gpiob 1 0>, /* A3 */
<4 0 &gpioc 2 0>, /* A4 */
<5 0 &gpiof 11 0>, /* A5 */
<6 0 &gpiob 7 0>, /* D0 */
<7 0 &gpiob 6 0>, /* D1 */
<8 0 &gpiog 14 0>, /* D2 */
<9 0 &gpioe 13 0>, /* D3 */
<10 0 &gpioe 14 0>, /* D4 */
<11 0 &gpioe 11 0>, /* D5 */
<12 0 &gpioa 8 0>, /* D6 */
<13 0 &gpiog 12 0>, /* D7 */
<14 0 &gpiog 9 0>, /* D8 */
<15 0 &gpiod 15 0>, /* D9 */
<16 0 &gpiod 14 0>, /* D10 */
<17 0 &gpiob 5 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_serial: &uart8 {};
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 495 |
```ini
# STM32H745ZI Nucleo board OpenOCD ST-LINK V3 configuration
#
#
source [find board/st_nucleo_h745zi.cfg]
# Use connect_assert_srst here to be able to program
# even when core is in sleep mode
reset_config srst_only srst_nogate connect_assert_srst
$_CHIPNAME.cpu0 configure -event gdb-attach {
echo "Debugger attaching: halting execution"
gdb_breakpoint_override hard
}
$_CHIPNAME.cpu0 configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
# Due to the use of connect_assert_srst, running gdb requires
# to reset halt just after openocd init.
rename init old_init
proc init {} {
old_init
reset halt
}
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 175 |
```restructuredtext
.. _nucleo_u575zi_q_board:
ST Nucleo U575ZI Q
##################
Overview
********
The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU,
provides an affordable and flexible way for users to try out new concepts and
build prototypes by choosing from the various combinations of performance and
power consumption features. Here are some highlights of the Nucleo U575ZI Q
board:
- STM32U575ZI microcontroller in LQFP144 package
- Internal SMPS to generate V core logic supply
- Two types of extension resources:
- Arduino Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- On-board ST-LINK/V3E debugger/programmer
- Flexible board power supply:
- USB VBUS or external source(3.3V, 5V, 7 - 12V)
- ST-Link V3E
- Three users LEDs
- Two push-buttons: USER and RESET
- USB Type-C |trade| Sink device FS
Hardware
********
The STM32U575xx devices are an ultra-low-power microcontrollers family (STM32U5
Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core.
They operate at a frequency of up to 160 MHz.
- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode)
- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU.
- Performance benchmark:
- 1.5 DMPIS/MHz (Drystone 2.1)
- 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ)
- Security
- Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals
- Flexible life cycle scheme with RDP (readout protection) and password protected debug
- Root of trust thanks to unique boot entry and secure hide protection area (HDP)
- Secure Firmware Installation thanks to embedded Root Secure Services
- Secure Firmware Update support with TF-M
- HASH hardware accelerator
- Active tampers
- True Random Number Generator NIST SP800-90B compliant
- 96-bit unique ID
- 512-byte One-Time Programmable for user data
- Clock management:
- 4 to 50 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
- Internal low-power 32 kHz RC ( |plusminus| 5%)
- 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by
LSE (better than |plusminus| 0.25 % accuracy)
- 3 PLLs for system clock, USB, audio, ADC
- Internal 48 MHz with clock recovery
- Power management
- Embedded regulator (LDO)
- Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling
- RTC with HW calendar and calibration
- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V
- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors
- Up to 17 timers and 2 watchdogs
- 2x 16-bit advanced motor-control
- 2x 32-bit and 5 x 16-bit general purpose
- 4x low-power 16-bit timers (available in Stop mode)
- 2x watchdogs
- 2x SysTick timer
- ART accelerator
- 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and
external memories: up to 160 MHz, MPU, 240 DMIPS and DSP
- 4-Kbyte data cache for external memories
- Memories
- 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles
- 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON
- External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories
- 2 Octo-SPI memory interfaces
- Rich analog peripherals (independent supply)
- 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling
- 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode
- 2 12-bit DAC, low-power sample and hold
- 2 operational amplifiers with built-in PGA
- 2 ultra-low-power comparators
- Up to 22 communication interfaces
- USB Type-C / USB power delivery controller
- USB OTG 2.0 full-speed controller
- 2x SAIs (serial audio interface)
- 4x I2C FM+(1 Mbit/s), SMBus/PMBus
- 6x USARTs (ISO 7816, LIN, IrDA, modem)
- 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode)
- 1x FDCAN
- 2x SDMMC interface
- 16- and 4-channel DMA controllers, functional in Stop mode
- 1 multi-function digital filter (6 filters)+ 1 audio digital filter with
sound-activity detection
- CRC calculation unit
- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade|
- True Random Number Generator (RNG)
- Graphic features
- Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation
- 1 digital camera interface
- Mathematical co-processor
- CORDIC for trigonometric functions acceleration
- FMAC (filter mathematical accelerator)
More information about STM32U575ZI can be found here:
- `STM32U575ZI on www.st.com`_
- `STM32U575 reference manual`_
Supported Features
==================
The Zephyr nucleo_u575zi_q board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| CAN/CANFD | on-chip | canbus |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC Controller |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| USB FS | on-chip | USB Full Speed device |
+-----------+------------+-------------------------------------+
| BKP SRAM | on-chip | Backup SRAM |
+-----------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig`
Connections and IOs
===================
Nucleo U575ZI Q Board has 9 GPIO controllers. These controllers are responsible for pin muxing,
input/output, pull-up, etc.
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
- CAN/CANFD_TX: PD1
- CAN/CANFD_RX: PD0
- DAC1_OUT1 : PA4
- I2C_1_SCL : PB8
- I2C_1_SDA : PB9
- I2C_2_SCL : PF1
- I2C_2_SDA : PF0
- LD1 : PC7
- LD2 : PB7
- LD3 : PG2
- LPUART_1_TX : PG7
- LPUART_1_RX : PG8
- SPI_1_NSS : PA4
- SPI_1_SCK : PA5
- SPI_1_MISO : PA6
- SPI_1_MOSI : PA7
- UART_1_TX : PA9
- UART_1_RX : PA10
- UART_2_TX : PD5
- UART_2_RX : PD6
- USER_PB : PC13
System Clock
------------
Nucleo U575ZI Q System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by PLL clock at
160MHz, driven by 4MHz medium speed internal oscillator.
Serial Port
-----------
Nucleo U575ZI Q board has 6 U(S)ARTs. The Zephyr console output is assigned to
USART1. Default settings are 115200 8N1.
Backup SRAM
-----------
In order to test backup SRAM you may want to disconnect VBAT from VDD. You can
do it by removing ``SB50`` jumper on the back side of the board.
Programming and Debugging
*************************
Nucleo U575ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
This probe allows to flash the board using various tools.
Flashing
========
Board is configured to be flashed using west STM32CubeProgrammer runner.
Installation of `STM32CubeProgrammer`_ is then required to flash the board.
Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be
used to flash and debug the board if west is told to use it as runner,
which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``.
For pyocd additional target information needs to be installed.
This can be done by executing the following commands.
.. code-block:: console
$ pyocd pack --update
$ pyocd pack --install stm32u5
Flashing an application to Nucleo U575ZI Q
------------------------------------------
Connect the Nucleo U575ZI Q to your host computer using the USB port.
Then build and flash an application. Here is an example for the
:ref:`hello_world` application.
Run a serial host program to connect with your Nucleo board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then build and flash the application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_u575zi_q
:goals: build flash
You should see the following message on the console:
.. code-block:: console
Hello World! arm
Debugging
=========
Default flasher for this board is openocd. It could be used in the usual way.
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_u575zi_q
:goals: debug
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32U575ZI on www.st.com:
path_to_url
.. _STM32U575 reference manual:
path_to_url
.. _STM32CubeProgrammer:
path_to_url
.. _STMicroelectronics customized version of OpenOCD:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_u575zi_q/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,742 |
```unknown
/*
*/
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
/ {
st_morpho_header: st-morpho-header {
compatible = "st-morpho-header";
#gpio-cells = <2>;
gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
<ST_MORPHO_L_2 0 &gpioc 11 0>,
<ST_MORPHO_L_3 0 &gpioc 12 0>,
<ST_MORPHO_L_4 0 &gpiod 2 0>,
<ST_MORPHO_L_7 0 &gpiof 11 0>,
<ST_MORPHO_L_13 0 &gpioa 13 0>,
<ST_MORPHO_L_15 0 &gpioa 14 0>,
<ST_MORPHO_L_17 0 &gpioa 15 0>,
<ST_MORPHO_L_21 0 &gpiob 7 0>,
<ST_MORPHO_L_23 0 &gpioc 13 0>,
<ST_MORPHO_L_25 0 &gpioc 14 0>,
<ST_MORPHO_L_27 0 &gpioc 15 0>,
<ST_MORPHO_L_28 0 &gpioa 0 0>,
<ST_MORPHO_L_29 0 &gpiof 0 0>,
<ST_MORPHO_L_30 0 &gpioa 1 0>,
<ST_MORPHO_L_31 0 &gpiof 1 0>,
<ST_MORPHO_L_32 0 &gpioa 4 0>,
<ST_MORPHO_L_34 0 &gpiob 0 0>,
<ST_MORPHO_L_35 0 &gpioc 2 0>,
<ST_MORPHO_L_36 0 &gpioc 1 0>, /* SB56=ON, SB46=OFF */
<ST_MORPHO_L_37 0 &gpioc 3 0>,
<ST_MORPHO_L_38 0 &gpioc 0 0>, /* SB51=ON, SB52=OFF */
<ST_MORPHO_R_1 0 &gpioc 9 0>,
<ST_MORPHO_R_2 0 &gpioc 8 0>,
<ST_MORPHO_R_3 0 &gpiob 8 0>,
<ST_MORPHO_R_4 0 &gpioc 6 0>,
<ST_MORPHO_R_5 0 &gpiob 9 0>,
<ST_MORPHO_R_6 0 &gpioc 5 0>,
<ST_MORPHO_R_11 0 &gpioa 5 0>,
<ST_MORPHO_R_12 0 &gpioa 12 0>,
<ST_MORPHO_R_13 0 &gpioa 6 0>,
<ST_MORPHO_R_14 0 &gpioa 11 0>,
<ST_MORPHO_R_15 0 &gpioa 7 0>,
<ST_MORPHO_R_16 0 &gpiob 12 0>,
<ST_MORPHO_R_17 0 &gpiob 6 0>,
<ST_MORPHO_R_18 0 &gpiob 11 0>,
<ST_MORPHO_R_19 0 &gpioc 7 0>,
<ST_MORPHO_R_21 0 &gpioa 9 0>,
<ST_MORPHO_R_22 0 &gpiob 2 0>,
<ST_MORPHO_R_23 0 &gpioa 8 0>,
<ST_MORPHO_R_24 0 &gpiob 1 0>,
<ST_MORPHO_R_25 0 &gpiob 10 0>,
<ST_MORPHO_R_26 0 &gpiob 15 0>,
<ST_MORPHO_R_27 0 &gpiob 4 0>,
<ST_MORPHO_R_28 0 &gpiob 14 0>,
<ST_MORPHO_R_29 0 &gpiob 5 0>,
<ST_MORPHO_R_30 0 &gpiob 13 0>,
<ST_MORPHO_R_31 0 &gpiob 3 0>,
<ST_MORPHO_R_33 0 &gpioa 10 0>,
<ST_MORPHO_R_34 0 &gpioc 4 0>,
<ST_MORPHO_R_35 0 &gpioa 2 0>,
<ST_MORPHO_R_37 0 &gpioa 3 0>;
};
};
``` | /content/code_sandbox/boards/st/nucleo_f091rc/st_morpho_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,203 |
```cmake
board_runner_args(jlink "--device=STM32F091RC" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/nucleo_f091rc/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```yaml
identifier: nucleo_f091rc
name: ST Nucleo F091RC
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
flash: 256
supported:
- arduino_gpio
- arduino_i2c
- arduino_spi
- gpio
- i2c
- nvs
- spi
- counter
- watchdog
- adc
- dac
- dma
- pwm
- can
- rtc
testing:
ignore_tags:
- net
- bluetooth
vendor: st
``` | /content/code_sandbox/boards/st/nucleo_f091rc/nucleo_f091rc.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 150 |
```yaml
board:
name: nucleo_f091rc
vendor: st
socs:
- name: stm32f091xc
``` | /content/code_sandbox/boards/st/nucleo_f091rc/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f0/stm32f091Xc.dtsi>
#include <st/f0/stm32f091r(b-c)tx-pinctrl.dtsi>
#include "arduino_r3_connector.dtsi"
#include "st_morpho_connector.dtsi"
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32F091RC-NUCLEO board";
compatible = "st,stm32f091rc-nucleo";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,canbus = &can1;
};
leds: leds {
compatible = "gpio-leds";
green_led_2: led_2 {
gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User";
gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
pwmleds: pwmleds {
compatible = "pwm-leds";
/* NOTE: disabled by default, PWM2 conflicts with SPI1 */
status = "disabled";
green_pwm_led: green_pwm_led {
pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
};
};
aliases {
led0 = &green_led_2;
sw0 = &user_button;
pwm-led0 = &green_pwm_led;
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
};
};
&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};
&clk_lsi {
status = "okay";
};
&pll {
prediv = <1>;
mul = <6>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(48)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};
&i2c2 {
/* Pin conflict with can1. Enable only with can1 disabled. */
pinctrl-0 = <&i2c2_scl_pa11 &i2c2_sda_pa12>;
pinctrl-names = "default";
status = "disabled";
clock-frequency = <I2C_BITRATE_FAST>;
};
&can1 {
pinctrl-0 = <&can_rx_pa11 &can_tx_pa12>;
pinctrl-names = "default";
status = "okay";
};
&spi1 {
pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
pinctrl-names = "default";
status = "okay";
};
&spi2 {
pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
pinctrl-names = "default";
status = "okay";
};
&iwdg {
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/* Set 6Kb of storage at the end of the 256Kb of flash */
storage_partition: partition@3e800 {
label = "storage";
reg = <0x0003e800 DT_SIZE_K(6)>;
};
};
};
&adc1 {
pinctrl-0 = <&adc_in0_pa0>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&die_temp {
status = "okay";
};
&dac1 {
status = "okay";
pinctrl-0 = <&dac_out1_pa4>;
pinctrl-names = "default";
};
&dma1 {
status = "okay";
};
&timers2 {
st,prescaler = <10000>;
status = "okay";
pwm2: pwm {
/* NOTE: disabled by default, PWM2 conflicts with SPI1 */
pinctrl-0 = <&tim2_ch1_pa5>;
pinctrl-names = "default";
};
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/nucleo_f091rc/nucleo_f091rc.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,262 |
```restructuredtext
.. _nucleo_h745zi_q_board:
ST Nucleo H745ZI-Q
###################
Overview
********
The STM32 Nucleo-144 board provides an affordable and flexible way for users
to try out new concepts and build prototypes by choosing from the various combinations
of performance and power consumption features, provided by the STM32 microcontroller.
For the compatible boards, the internal or external SMPS significantly reduces power
consumption in Run mode.
The ST Zio connector, which extends the ARDUINO Uno V3 connectivity, and
the ST morpho headers provide an easy means of expanding the functionality of the Nucleo
open development platform with a wide choice of specialized shields.
The STM32 Nucleo-144 board does not require any separate probe as it integrates
the ST-LINK V3 debugger/programmer.
The STM32 Nucleo-144 board comes with the STM32 comprehensive free software
libraries and examples available with the STM32Cube MCU Package.
Key Features
- STM32 microcontroller in LQFP144 package
- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support)
- USB OTG or full-speed device (depending on STM32 support)
- 3 user LEDs
- 2 user and reset push-buttons
- 32.768 kHz crystal oscillator
- Board connectors:
- USB with Micro-AB
- Ethernet RJ45 (depending on STM32 support)
- SWDST Zio connector including Arduino* Uno V3ST
- ST morpho expansion
- Flexible power-supply options: ST-LINK USB VBUS or external sources
- External or internal SMPS to generate Vcore logic supply
- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration
- capability: mass storage, virtual COM port and debug port
- USB OTG full speed or device only
- Comprehensive free software libraries and examples available with the
STM32Cube MCU package.
- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers)
.. image:: img/nucleo_h745zi_q.jpg
:align: center
:alt: Nucleo H745ZI-Q
More information about the board can be found at the `Nucleo H745ZI-Q website`_.
Hardware
********
Nucleo H745ZI-Q provides the following hardware components:
- STM32H745ZI in LQFP144 package
- ARM 32-bit Cortex-M7 CPU with FPU
- ARM 32-bit Cortex-M4 CPU with FPU
- Chrom-ART Accelerator
- Hardware JPEG Codec
- 480 MHz max CPU frequency
- VDD from 1.62 V to 3.6 V
- 2 MB Flash
- 1 MB SRAM
- High-resolution timer (2.1 ns)
- 32-bit timers(2)
- 16-bit timers(12)
- SPI(6)
- I2C(4)
- I2S (3)
- USART(4)
- UART(4)
- USB OTG Full Speed and High Speed(1)
- USB OTG Full Speed(1)
- CAN FD(2)
- SAI(2)
- SPDIF_Rx(4)
- HDMI_CEC(1)
- Dual Mode Quad SPI(1)
- Camera Interface
- GPIO (up to 114) with external interrupt capability
- 16-bit ADC(3) with 36 channels / 3.6 MSPS
- 12-bit DAC with 2 channels(2)
- True Random Number Generator (RNG)
- 16-channel DMA
- LCD-TFT Controller with XGA resolution
Supported Features
==================
The Zephyr nucleo_h745zi_q board configuration supports the following hardware
features:
+-------------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+=============+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-------------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-------------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-------------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-------------+------------+-------------------------------------+
| RTC | on-chip | counter |
+-------------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-------------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-------------+------------+-------------------------------------+
| ETHERNET | on-chip | ethernet |
+-------------+------------+-------------------------------------+
| RNG | on-chip | True Random number generator |
+-------------+------------+-------------------------------------+
| USB OTG FS | on-chip | USB device |
+-------------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration per core can be found in the defconfig files:
:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig` and
:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig`
For more details please refer to `STM32 Nucleo-144 board User Manual`_.
Default Zephyr Peripheral Mapping:
----------------------------------
The Nucleo H745ZI board features a ST Zio connector (extended Arduino Uno V3)
and a ST morpho connector. Board is configured as follows:
- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com)
- USER_PB : PC13
- LD1 : PB0
- LD2 : PB7
- LD3 : PB14
- I2C : PB8, PB9
System Clock
------------
Nucleo H745ZI-Q System Clock could be driven by an internal or external
oscillator, as well as the main PLL clock. By default, the System clock is
driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock.
Serial Port
-----------
Nucleo H745ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is
assigned to UART3. Default settings are 115200 8N1.
Resources sharing
-----------------
The dual core nature of STM32H745 SoC requires sharing HW resources between the
two cores. This is done in 3 ways:
- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
has access to bus clock activation and deactivation.
- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
devicetree before compilation. The user must ensure peripherals are not assigned
to both cores at the same time.
- **Run time protection**: Interrupt-controller and GPIO configurations could be
accessed by both cores at run time. Accesses are protected by a hardware semaphore
to avoid potential concurrent access issues.
Programming and Debugging
*************************
Applications for the ``nucleo_h745zi_q`` board should be built per core target,
using either ``nucleo_h745zi_q_m7`` or ```nucleo_h745zi_q_m4`` as the target
(see :ref:`build_an_application` and :ref:`application_run` for more details).
.. note::
If using OpenOCD you will need a recent development version as the last
official release does not support H7 series and ST-LINK V3 yet.
Following links may be helpful: `OpenOCD installing Debug Version`_
and `OpenOCD installing with ST-LINK V3 support`_
.. note::
Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_
Flashing
========
Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
Flashing operation will depend on the target to be flashed and the SoC
option bytes configuration.
By default:
- CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
- CPU1 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0)
Also, default out of the box board configuration enables CM7 and CM4 boot when
board is powered (Option bytes BCM7 and BCM4 are checked).
In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected.
Zephyr flash configuration has been set to meet these default settings.
Flashing an application to STM32H745ZI M7 Core
----------------------------------------------
First, connect the NUCLEO-H745ZI-Q to your host computer using
the USB port to prepare it for flashing. Then build and flash your application.
Here is an example for the :ref:`hello_world` application.
Run a serial host program to connect with your NUCLEO-H745ZI-Q board.
.. code-block:: console
$ minicom -b 115200 -D /dev/ttyACM0
or use screen:
.. code-block:: console
$ screen /dev/ttyACM0 115200
Build and flash the application:
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_h745zi_q_m7
:goals: build flash
You should see the following message on the console:
.. code-block:: console
$ Hello World! nucleo_h745zi_q_m7
.. note::
Sometimes, flashing is not working. It is necessary to erase the flash
(with STM32CubeProgrammer for example) to make it work again.
Similarly, you can build and flash samples on the M4 target. For this, please
take care of the resource sharing (UART port used for console for instance).
Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_h745zi_q_m4
:goals: build flash
.. note::
Flashing both M4 and M7 and pushing RESTART button on the board leads
to LD1 and LD2 flashing simultaneously.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_h745zi_q_m7
:maybe-skip-config:
:goals: debug
Debugging with west is currently not available on Cortex M4 side.
In order to debug a Zephyr application on Cortex M4 side, you can use
`STM32CubeIDE`_.
.. _Nucleo H745ZI-Q website:
path_to_url
.. _STM32 Nucleo-144 board User Manual:
path_to_url
.. _STM32H745ZI on www.st.com:
path_to_url
.. _STM32H745 reference manual:
path_to_url
.. _OpenOCD installing Debug Version:
path_to_url
.. _OpenOCD installing with ST-LINK V3 support:
path_to_url
.. _STM32CubeIDE:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_h745zi_q/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,484 |
```unknown
config BOARD_NUCLEO_F091RC
select SOC_STM32F091XC
``` | /content/code_sandbox/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 21 |
```unknown
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 58 |
```unknown
# STM32 Nucleo-64 development board with STM32F091RC MCU
if BOARD_NUCLEO_F091RC
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_NUCLEO_F091RC
``` | /content/code_sandbox/boards/st/nucleo_f091rc/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```ini
source [find board/st_nucleo_f0.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/nucleo_f091rc/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 70 |
```unknown
/*
*
*/
/ {
arduino_header: connector {
compatible = "arduino-header-r3";
#gpio-cells = <2>;
gpio-map-mask = <0xffffffff 0xffffffc0>;
gpio-map-pass-thru = <0 0x3f>;
gpio-map = <0 0 &gpioa 0 0>, /* A0 */
<1 0 &gpioa 1 0>, /* A1 */
<2 0 &gpioa 4 0>, /* A2 */
<3 0 &gpiob 0 0>, /* A3 */
<4 0 &gpioc 1 0>, /* A4 */
<5 0 &gpioc 0 0>, /* A5 */
<6 0 &gpioa 3 0>, /* D0 */
<7 0 &gpioa 2 0>, /* D1 */
<8 0 &gpioa 10 0>, /* D2 */
<9 0 &gpiob 3 0>, /* D3 */
<10 0 &gpiob 5 0>, /* D4 */
<11 0 &gpiob 4 0>, /* D5 */
<12 0 &gpiob 10 0>, /* D6 */
<13 0 &gpioa 8 0>, /* D7 */
<14 0 &gpioa 9 0>, /* D8 */
<15 0 &gpioc 7 0>, /* D9 */
<16 0 &gpiob 6 0>, /* D10 */
<17 0 &gpioa 7 0>, /* D11 */
<18 0 &gpioa 6 0>, /* D12 */
<19 0 &gpioa 5 0>, /* D13 */
<20 0 &gpiob 9 0>, /* D14 */
<21 0 &gpiob 8 0>; /* D15 */
};
};
arduino_i2c: &i2c1 {};
arduino_spi: &spi1 {};
``` | /content/code_sandbox/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 492 |
```cmake
board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
``` | /content/code_sandbox/boards/st/sensortile_box/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 44 |
```unknown
config BOARD_SENSORTILE_BOX
select SOC_STM32L4R9XX
``` | /content/code_sandbox/boards/st/sensortile_box/Kconfig.sensortile_box | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# Enable GPIO
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# Console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/sensortile_box/sensortile_box_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
board:
name: sensortile_box
vendor: st
socs:
- name: stm32l4r9xx
``` | /content/code_sandbox/boards/st/sensortile_box/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```restructuredtext
.. _nucleo_f091rc_board:
ST Nucleo F091RC
################
Overview
********
The STM32 Nucleo-64 development board with STM32F091RC MCU, supports Arduino and ST morpho connectivity.
The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts,
and build prototypes with the STM32 microcontroller, choosing from the various
combinations of performance, power consumption, and features.
The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality
expansion of the STM32 Nucleo open development platform with a wide choice of
specialized shields.
The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer.
The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together
with various packaged software examples.
.. image:: img/nucleo_f091rc.jpg
:align: center
:alt: Nucleo F091RC
More information about the board can be found at the `Nucleo F091RC website`_.
Hardware
********
Nucleo F091RC provides the following hardware components:
- STM32 microcontroller in QFP64 package
- Two types of extension resources:
- Arduino* Uno V3 connectivity
- ST morpho extension pin headers for full access to all STM32 I/Os
- ARM* mbed*
- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
- Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
- Flexible board power supply:
- USB VBUS or external source (3.3V, 5V, 7 - 12V)
- Power management access point
- Three LEDs:
- USB communication (LD1), user LED (LD2), power LED (LD3)
- Two push-buttons: USER and RESET
- USB re-enumeration capability. Three different interfaces supported on USB:
- Virtual COM port
- Mass storage
- Debug port
- Support of wide choice of Integrated Development Environments (IDEs) including:
- IAR
- ARM Keil
- GCC-based IDEs
More information about STM32F091RC can be found in the
`STM32F091 reference manual`_
Supported Features
==================
The Zephyr nucleo_f091rc board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
| PWM | on-chip | pwm |
+-----------+------------+-------------------------------------+
| COUNTER | on-chip | rtc |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c controller |
+-----------+------------+-------------------------------------+
| SPI | on-chip | SPI controller |
+-----------+------------+-------------------------------------+
| CAN | on-chip | CAN controller |
+-----------+------------+-------------------------------------+
| ADC | on-chip | ADC controller |
+-----------+------------+-------------------------------------+
| DAC | on-chip | DAC controller |
+-----------+------------+-------------------------------------+
| DMA | on-chip | Direct Memory Access |
+-----------+------------+-------------------------------------+
| die-temp | on-chip | die temperature sensor |
+-----------+------------+-------------------------------------+
| RTC | on-chip | rtc |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/nucleo_f091rc/nucleo_f091rc_defconfig`
Connections and IOs
===================
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
Board connectors:
-----------------
.. image:: img/nucleo_f091rc_connectors.jpg
:align: center
:alt: Nucleo F091RC connectors
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_1 TX/RX : PB6/PB7
- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port)
- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
- I2C2 SCL/SDA : PA11/PA12 (disabled by default, uses same pins as CAN)
- CAN RX/TX : PA11/PA12
- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI)
- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15
- USER_PB : PC13
- LD2 : PA5
- DAC_OUT1 : PA4
- PWM_2_CH1 : PA5 (might conflict with SPI1)
For more details please refer to `STM32 Nucleo-64 board User Manual`_.
Programming and Debugging
*************************
Applications for the ``nucleo_f091rc`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface.
This interface is supported by the openocd version included in the Zephyr SDK.
Flashing an application to Nucleo F091RC
----------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: nucleo_f091rc
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:ref:`hello_world` application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: nucleo_f091rc
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _Nucleo F091RC website:
path_to_url
.. _STM32F091 reference manual:
path_to_url
.. _STM32 Nucleo-64 board User Manual:
path_to_url
``` | /content/code_sandbox/boards/st/nucleo_f091rc/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,600 |
```unknown
# SensorTile.box board configuration
if BOARD_SENSORTILE_BOX
if BT
config SPI
default y
config BT_SPI
default y
config BT_BLUENRG_ACI
default y
# Disable Flow control
config BT_HCI_ACL_FLOW_CONTROL
default n
config BT_HCI_VS
default n
endif # BT
config SPI_STM32_INTERRUPT
default y
depends on SPI
endif # BOARD_SENSORTILE_BOX
``` | /content/code_sandbox/boards/st/sensortile_box/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 96 |
```yaml
identifier: sensortile_box
name: ST SensorTile.box
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- pwm
- spi
- ble
- i2c
- gpio
- usb device
- nvs
- counter
ram: 640
flash: 2048
vendor: st
``` | /content/code_sandbox/boards/st/sensortile_box/sensortile_box.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 98 |
```ini
source [find board/st_nucleo_l4.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/sensortile_box/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/l4/stm32l4r9Xi.dtsi>
#include <st/l4/stm32l4r9z(g-i)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics SensorTile.box board";
compatible = "st,sensortile-box";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,bt-c2h-uart = &usart1;
zephyr,bt-hci = &spbtle_1s_sensortile_box;
};
leds {
compatible = "gpio-leds";
blue_led: led {
gpios = <&gpiob 15 GPIO_ACTIVE_HIGH>;
label = "User LD1";
};
green_led: led_2 {
gpios = <&gpiof 2 GPIO_ACTIVE_HIGH>;
label = "User LD4";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "User PB1";
gpios = <&gpiog 1 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &blue_led;
led1 = &green_led;
sw0 = &user_button;
magn0 = &lis2mdl;
accel0 = &lis2dw12;
accel1 = &lsm6dso;
accel2 = &iis3dhhc;
};
};
&clk_lsi {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(16)>;
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <40>;
div-p = <7>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(80)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&usart2 {
pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&i2c1 {
pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
hts221@5f {
compatible = "st,hts221";
reg = <0x5f>;
drdy-gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>;
};
lps22hh@5d {
compatible = "st,lps22hh";
reg = <0x5d>;
drdy-gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>;
};
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pg7 &i2c3_sda_pg8>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
stts751@38 {
compatible = "st,stts751";
reg = <0x38>;
drdy-gpios = <&gpiog 5 GPIO_ACTIVE_LOW>;
};
};
&spi1 {
pinctrl-0 = <&spi1_nss_pe12 &spi1_sck_pe13
&spi1_miso_pe14 &spi1_mosi_pe15>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>, <&gpioe 12 GPIO_ACTIVE_LOW>, <&gpioe 10 GPIO_ACTIVE_LOW>;
lis2dw12: lis2dw12@0 {
compatible = "st,lis2dw12";
spi-max-frequency = <1000000>;
reg = <0>;
irq-gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>;
};
lsm6dso: lsm6dso@1 {
compatible = "st,lsm6dso";
spi-max-frequency = <1000000>;
reg = <1>;
irq-gpios = <&gpioa 2 GPIO_ACTIVE_HIGH>;
int-pin = <1>;
};
iis3dhhc: iis3dhhc@2 {
compatible = "st,iis3dhhc";
spi-max-frequency = <1000000>;
reg = <2>;
irq-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>, <&gpioe 6 GPIO_ACTIVE_HIGH>;
};
};
&spi2 {
pinctrl-0 = <&spi2_sck_pd1 &spi2_miso_pd3 &spi2_mosi_pc3>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpiod 0 GPIO_ACTIVE_LOW>;
spbtle_1s_sensortile_box: spbtle-1s@0 {
compatible = "st,hci-spi-v2";
reg = <0>;
reset-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
irq-gpios = <&gpiod 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
spi-max-frequency = <DT_FREQ_M(1)>;
spi-cpha;
spi-hold-cs;
reset-assert-duration-ms = <6>;
};
};
&spi3 {
pinctrl-0 = <&spi3_nss_pa15 &spi3_sck_pb3
&spi3_miso_pb4 &spi3_mosi_pb5>;
pinctrl-names = "default";
status = "okay";
cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
lis2mdl: lis2mdl@0 {
compatible = "st,lis2mdl";
spi-max-frequency = <1000000>;
reg = <0>;
};
};
zephyr_udc0: &usbotg_fs {
pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
pinctrl-names = "default";
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
read-only;
};
/*
* The flash starting at offset 0x10000 and ending at
* offset 0x1ffff is reserved for use by the application.
*/
slot0_partition: partition@20000 {
label = "image-0";
reg = <0x00020000 DT_SIZE_K(432)>;
};
slot1_partition: partition@8c000 {
label = "image-1";
reg = <0x0008C000 DT_SIZE_K(432)>;
};
scratch_partition: partition@f8000 {
label = "image-scratch";
reg = <0x000F8000 DT_SIZE_K(24)>;
};
storage_partition: partition@fc000 {
label = "storage";
reg = <0x000fc000 DT_SIZE_K(24)>;
};
};
};
``` | /content/code_sandbox/boards/st/sensortile_box/sensortile_box.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,840 |
```cmake
board_runner_args(jlink "--device=STM32F373VC" "--speed=4000")
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
``` | /content/code_sandbox/boards/st/stm32373c_eval/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 55 |
```yaml
identifier: stm32373c_eval
name: ST STM32373C Evaluation
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 32
supported:
- watchdog
- counter
vendor: st
``` | /content/code_sandbox/boards/st/stm32373c_eval/stm32373c_eval.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```yaml
board:
name: stm32373c_eval
vendor: st
socs:
- name: stm32f373xc
``` | /content/code_sandbox/boards/st/stm32373c_eval/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/f3/stm32f373Xc.dtsi>
#include <st/f3/stm32f373v(8-b-c)tx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
/ {
model = "STMicroelectronics STM32373C-EVAL board";
compatible = "st,stm32373c-eval";
chosen {
zephyr,console = &usart2;
zephyr,shell-uart = &usart2;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
green_led_2: led_2 {
gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
label = "User LD2";
};
};
gpio_keys {
compatible = "gpio-keys";
user_button: button {
label = "Key";
gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
zephyr,code = <INPUT_KEY_0>;
};
};
aliases {
led0 = &green_led_2;
sw0 = &user_button;
watchdog0 = &iwdg;
};
};
&clk_lsi {
status = "okay";
};
&clk_hse {
clock-frequency = <DT_FREQ_M(8)>;
status = "okay";
};
&pll {
prediv = <1>;
mul = <9>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(72)>;
ahb-prescaler = <1>;
apb1-prescaler = <2>;
apb2-prescaler = <2>;
};
&usart2 {
pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&rtc {
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
<&rcc STM32_SRC_LSI RTC_SEL(2)>;
status = "okay";
};
&iwdg {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32373c_eval/stm32373c_eval.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 507 |
```unknown
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# Serial Drivers
CONFIG_SERIAL=y
CONFIG_UART_INTERRUPT_DRIVEN=y
# enable console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# GPIO Controller
CONFIG_GPIO=y
# Enable Clocks
CONFIG_CLOCK_CONTROL=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32373c_eval/stm32373c_eval_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 81 |
```unknown
config BOARD_STM32373C_EVAL
select SOC_STM32F373XC
``` | /content/code_sandbox/boards/st/stm32373c_eval/Kconfig.stm32373c_eval | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 20 |
```ini
source [find board/stm32f3discovery.cfg]
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/st/stm32373c_eval/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 71 |
```restructuredtext
.. _stm32373c_eval_board:
ST STM32373C Evaluation
#######################
Overview
********
The STM32373C-EVAL evaluation board is designed as a complete demonstration and development platform for STMicroelectronics ARM Cortex-M4 core-based STM32F373VCT6 microcontroller.
The full range of hardware features on the board can help the user evaluate all peripherals (USB FS, USART, audio DAC, microphone ADC, dot-matrix LCD, IrDA, LDR, MicroSD card, HDMI CEC, ECG, pressure sensor, CAN, IR transmitter and receiver, EEPROM, touch slider, temperature sensor, etc.) and develop their own applications.
Extension headers make it possible to easily connect a daughter board or wrapping board for a specific application.
.. image:: img/stm32373c_eval.jpg
:align: center
:alt: STM32373C-EVAL
More information about the board can be found at the `STM32373C-EVAL website`_.
Hardware
********
STM32373C-EVAL provides the following hardware components:
- STM32F373VCT6 microcontroller
- Four 5 V power supply options:
- Power jack
- ST-LINK/V2 USB connector
- User USB connector
- Daughter board
- Audio jack connected to I2 S DAC
- Microphone connected to ADC through an amplifier
- 2-GByte (or more) MicroSD card on SPI
- Three components on I2 C bus: temperature sensor, EEPROM and dual interface RF EEPROM
- RS-232 communication configurable for communication of Flash loader
- IrDA transceiver
- 240x320 TFT color LCD connected to SPI interface
- Joystick with 4-direction control and selector
- Reset, Wakeup or Tamper, and Key buttons
- 4 color user LEDs
- 2 LEDs for MCU power range indicator
- ECG, pressure sensor and PT100 temperature sensor connected to the 16-bit Sigma Delta ADC of STM32F373VCT6
- Extension connectors for daughter board or wrapping board
- MCU voltage: 3.3 V or adjustable 2.0 V - 3.6 V
- USB FS connector
- Touch slider
- RTC with backup battery
- CAN 2.0 A/B compliant connection
- Light dependent resistor (LDR)
- Two HDMI connectors with DDC and CEC
- IR transmitter and receiver
- Two ADC & DAC input and output signal connectors and one Sigma Delta ADC input signal connector
- Potentiometer
- JTAG/SWD and ETM trace debug support
- Embedded ST-LINK/V2
More information about STM32F373VCT6 can be found here:
- `STM32F373VCT6 reference manual`_
Supported Features
==================
The Zephyr stm32373c_eval board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| CLOCK | on-chip | reset and clock control |
+-----------+------------+-------------------------------------+
| FLASH | on-chip | flash memory |
+-----------+------------+-------------------------------------+
| WATCHDOG | on-chip | independent watchdog |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported in this Zephyr port.
The default configuration can be found in
:zephyr_file:`boards/st/stm32373c_eval/stm32373c_eval_defconfig`
Connections and IOs
===================
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
Board connectors:
-----------------
.. image:: img/stm32373c_eval_connectors.jpg
:align: center
:alt: STM32373C_EVAL connectors
Default Zephyr Peripheral Mapping:
----------------------------------
- UART_2_TX : PD5
- UART_2_RX : PD6
- USER_PB : PA2
- LED2 : PC1
Programming and Debugging
*************************
Applications for the ``stm32373c_eval`` board configuration can be built and
flashed in the usual way (see :ref:`build_an_application` and
:ref:`application_run` for more details).
Flashing
========
STM32373C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface.
At power-on, the board is in firmware-upgrade mode (also called DFU for
"Device Firmware Upgrade"), allowing the firmware to be updated through the USB.
This interface is supported by the openocd version included in Zephyr SDK.
Flashing an application to STM32373C-EVAL
-----------------------------------------
Here is an example for the :zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32373c_eval
:goals: build flash
You will see the LED blinking every second.
Debugging
=========
You can debug an application in the usual way. Here is an example for the
:zephyr:code-sample:`blinky` application.
.. zephyr-app-commands::
:zephyr-app: samples/basic/blinky
:board: stm32373c_eval
:maybe-skip-config:
:goals: debug
References
**********
.. target-notes::
.. _STM32373C-EVAL website:
path_to_url
.. _STM32F373VCT6 reference manual:
path_to_url
``` | /content/code_sandbox/boards/st/stm32373c_eval/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,325 |
```restructuredtext
.. _sensortile_box:
ST SensorTile.box
#################
Overview
********
The STEVAL-MKSBOX1V1 (SensorTile.box) is a ready-to-use box kit for wireless
IoT and wearable sensor platforms to help you use and develop apps based on
remote motion and environmental sensor data.
The SensorTile.box board fits into a small plastic box with a long-life rechargeable
battery, and communicates with a standard smartphone through its Bluetooth interface,
providing data coming from the sensors.
.. image:: img/sensortile_box.jpg
:align: center
:alt: SensorTile.box
More information about the board can be found at the `SensorTile.box website`_.
Hardware
********
SensorTile.box provides the following hardware components:
- Ultra low-power STM32L4R9ZI System on Chip
- LQFP144 package
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive
real-time accelerator (ART Accelerator) allowing 0-wait-state
execution from Flash memory, frequency up to 120 MHz, MPU, 150
DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
- Clock Sources:
- 16 MHz crystal oscillator
- 32 kHz crystal oscillator for RTC (LSE)
- Communication
- Bluetooth Smart connectivity v4.2 (SPBTLE-1S)
- 1 x USB OTG FS (SoC) with micro-B connector
(USB device role only)
- Internal Buses
- 3 x SPI bus
- 3 x I2C bus
- micro-SD connector
- On board sensors:
- Digital temperature sensor (STTS751)
- 6-axis inertial measurement unit (LSM6DSOX)
- 3-axis accelerometers (LIS2DW12 and LIS3DHH)
- 3-axis magnetometer (LIS2MDL)
- Altimeter / pressure sensor (LPS22HH)
- Microphone / audio sensor (MP23ABS1)
- Humidity sensor (HTS221)
- HCP602535ZC LI-ion rechargeable battery (3.7V 500mAh)
- FTSH107 connector for SWD debugging and UART Tx/Rx
Supported Features
==================
The SensorTile.box provides motion, environmental, and audio
sensor data through either the BLE or USB protocols to a host application running
on a smartphone/PC to implement applications such as:
- Pedometer optimized for belt positioning
- Baby crying detection with Cloud AI learning
- Barometer / environmental monitoring
- Vehicle / goods tracking
- Vibration monitoring
- Compass and inclinometer
- Sensor data logger
Connections and IOs
===================
LED
---
- Blue LED = PB15
- Green LED = PF2
Push buttons
------------
- BUTTON = BOOT
(used to let the SensorTile.box enter DFU mode. See `Programming and Debugging`_
section)
- BUTTON = PWR
(used to Power on/off the board when battery is connected)
System Clock
============
SensorTile.box System Clock could be driven by internal or external
oscillator, as well as main PLL clock. By default, the System clock is
driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator.
The system clock can be boosted to 120MHz.
The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz.
Serial Port
===========
There are two possible options for Zephyr console output:
- using USART1 which is available on FTSH107 connector. In this case a JTAG adapter
can be used to connect SensorTile.box to STLINK-V2 and have both SWD and console lines
available on PC.
- using the USB connector, which may be used to make the console available on PC as
USB CDC class.
Console default settings are 115200 8N1.
USB interface
=============
SensorTile.box can be connected as a USB device to a PC host through its micro-B connector.
The final application may use it to declare SensorTile.box device as belonging to a
certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both
functions.
Programming and Debugging
*************************
There are 2 main entry points for flashing STM32FL4Rx SoCs, one using the ROM
bootloader, and another by using the SWD debug port (which requires additional
hardware) on FTSH107 connector.
Flash using the ROM bootloader by powering on the board
while keeping the BOOT0 button pressed.
The ROM bootloader supports flashing via USB (DFU), UART, I2C and SPI.
You can read more about how to enable and use the ROM bootloader by checking
the application note `AN2606`_ (STM32L4Rx section).
Flashing
========
Installing dfu-util
-------------------
It is recommended to use at least v0.8 of dfu-util. The package available in
Debian and Ubuntu can be quite old, so you might have to build dfu-util from source.
Information about how to get the source code and how to build it can be found
at the `DFU-UTIL website`_
Flashing an Application to SensorTile.box
-----------------------------------------
While pressing the BOOT0 button, connect the
micro-USB cable to the USB OTG SensorTile.box
port and to your computer. The board should be
forced to enter DFU mode.
Confirm that the board is in DFU mode:
.. code-block:: console
$ sudo dfu-util -l
dfu-util 0.9
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to path_to_url
Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204A325D574D"
Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", serial="204A325D574D"
Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=0, name="@Internal Flash /0x08000000/512*0004Kg", serial="204A325D574D"
You should see following confirmation on your Linux host:
.. code-block:: console
$ dmesg
usb 2-2: new full-speed USB device number 74 using xhci_hcd
usb 2-2: New USB device found, idVendor=0483, idProduct=df11
usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
usb 2-2: Product: STM32 BOOTLOADER
usb 2-2: Manufacturer: STMicroelectronics
usb 2-2: SerialNumber: 204A325D574D
You can build and flash the provided sample application
(:ref:`sensortile_box sensors`) that reads sensors data and outputs
values on the console.
References
**********
.. target-notes::
.. _SensorTile.box website:
path_to_url
.. _AN2606:
path_to_url
.. _DFU-UTIL website:
path_to_url
``` | /content/code_sandbox/boards/st/sensortile_box/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,682 |
```cmake
board_runner_args(pyocd "--target=stm32wb55vgyx")
board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 97 |
```unknown
# enable uart driver
CONFIG_SERIAL=y
# enable GPIO
CONFIG_GPIO=y
# enable clocks
CONFIG_CLOCK_CONTROL=y
# console
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
# Enable MPU
CONFIG_ARM_MPU=y
# Enable HW stack protection
CONFIG_HW_STACK_PROTECTION=y
# enable pin controller
CONFIG_PINCTRL=y
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 72 |
```yaml
board:
name: stm32wb5mm_dk
vendor: st
socs:
- name: stm32wb55xx
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
config BOARD_STM32WB5MM_DK
select SOC_STM32WB55XX
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 22 |
```unknown
# STM32WB5MM-DK Discovery Development board configuration
if BOARD_STM32WB5MM_DK
config BT_STM32_IPM
default y
depends on BT
endif
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 43 |
```yaml
identifier: stm32wb5mm_dk
name: ST STM32WB5MM-DK Discovery Development Board
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
- xtools
ram: 256
flash: 876
supported:
- gpio
- uart
- i2c
- vl53l0x
- ism330dhcx
vendor: st
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 101 |
```ini
source [find interface/stlink.cfg]
transport select hla_swd
source [find target/stm32wbx.cfg]
reset_config srst_only
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 33 |
```unknown
/*
*
*/
/dts-v1/;
#include <st/wb/stm32wb55Xg.dtsi>
#include <st/wb/stm32wb55vgyx-pinctrl.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <zephyr/dt-bindings/led/led.h>
#include <zephyr/dt-bindings/sensor/ism330dhcx.h>
/ {
model = "STMicroelectronics STM32WB5MM Discovery Development Kit";
compatible = "st,stm32wb5mm-dk";
chosen {
zephyr,console = &usart1;
zephyr,shell-uart = &usart1;
zephyr,bt-mon-uart = &lpuart1;
zephyr,bt-c2h-uart = &lpuart1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,code-partition = &slot0_partition;
};
rgb_led_strip: rgb_strip {
compatible = "ti,tlc59731";
gpios = <&gpioa 7 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
chain-length = <1>;
color-mapping = <LED_COLOR_ID_BLUE
LED_COLOR_ID_GREEN
LED_COLOR_ID_RED>;
status = "disabled";
};
buttons {
compatible = "gpio-keys";
button0: button_0 {
gpios = <&gpioc 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 1";
zephyr,code = <INPUT_KEY_0>;
};
button1: button_1 {
gpios = <&gpioc 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
label = "Push button 2";
zephyr,code = <INPUT_KEY_1>;
};
};
aliases {
watchdog0 = &iwdg;
die-temp0 = &die_temp;
volt-sensor0 = &vref;
volt-sensor1 = &vbat;
led-strip = &rgb_led_strip;
sw0 = &button0;
sw1 = &button1;
accel0 = &ism330dhcx;
};
};
&die_temp {
status = "okay";
};
&clk_hse {
status = "okay";
};
&clk_lse {
status = "okay";
};
&clk_hsi48 {
status = "okay";
};
&clk48 {
/* Node is disabled by default as default source is HSI48 */
/* To select another clock, enable the node */
clocks = <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(32)>;
cpu1-prescaler = <1>;
cpu2-prescaler = <1>;
ahb4-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
};
&usart1 {
pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
pinctrl-names = "default";
current-speed = <115200>;
status = "okay";
};
&lpuart1 {
pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
pinctrl-names = "default";
current-speed = <100000>;
status = "okay";
};
&adc1 {
pinctrl-0 = <&adc1_in3_pc2>;
pinctrl-names = "default";
st,adc-clock-source = <SYNC>;
st,adc-prescaler = <4>;
status = "okay";
};
&iwdg {
status = "okay";
};
zephyr_udc0: &usb {
status = "okay";
pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
pinctrl-names = "default";
};
&aes1 {
status = "okay";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* Configure partitions while leaving space for M0 BLE f/w
* Since STM32WBCube release V1.13.2, only _HCIOnly_ f/w are supported.
* These FW are expected to be located not before 0x080DB000
* Current partition is using the first 876K of the flash for M4
*/
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(48)>;
};
slot0_partition: partition@c000 {
label = "image-0";
reg = <0x0000c000 DT_SIZE_K(400)>;
};
slot1_partition: partition@70000 {
label = "image-1";
reg = <0x00070000 DT_SIZE_K(400)>;
};
scratch_partition: partition@d4000 {
label = "image-scratch";
reg = <0x000d4000 DT_SIZE_K(16)>;
};
storage_partition: partition@d8000 {
label = "storage";
reg = <0x000d8000 DT_SIZE_K(8)>;
};
};
};
&gpioh {
rgb_cs: rgb_cs {
gpios = <1 GPIO_ACTIVE_HIGH>;
gpio-hog;
output-high;
status = "disabled";
};
};
&i2c3 {
pinctrl-0 = <&i2c3_scl_pb13 &i2c3_sda_pb11>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
vl53l0x@29 {
compatible = "st,vl53l0x";
reg = <0x29>;
xshut-gpios = <&gpioc 6 GPIO_ACTIVE_LOW>;
};
ism330dhcx: ism330dhcx@6b {
compatible = "st,ism330dhcx";
reg = <0x6b>;
drdy-gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>;
accel-odr= <ISM330DHCX_DT_ODR_52Hz>;
gyro-odr= <ISM330DHCX_DT_ODR_26H>;
};
};
&vref {
status = "okay";
};
&vbat {
status = "okay";
};
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,455 |
```restructuredtext
.. _boards-microchip-technology-inc:
Microchip Technology Inc.
#########################
.. toctree::
:maxdepth: 1
:glob:
**/*
``` | /content/code_sandbox/boards/microchip/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 38 |
```cmake
set(SPI_IMAGE_NAME spi_image.bin)
board_set_flasher_ifnset(dediprog)
# --vcc=0 - use 3.5V to flash
board_finalize_runner_args(dediprog
"--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}"
"--vcc=0"
)
# This allows a custom script to be used for flashing the SPI chip.
include(${ZEPHYR_BASE}/boards/common/misc.board.cmake)
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 99 |
```unknown
config BOARD_MEC172XEVB_ASSY6906
select SOC_MEC172X_NSZ
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 23 |
```yaml
#
#
#
identifier: mec172xevb_assy6906
name: MEC172X EVB ASSY 6906
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 64
flash: 352
supported:
- gpio
- i2c
- adc
- pwm
- counter
- spi
testing:
binaries:
- spi_image.bin
ignore_tags:
- bluetooth
- net
vendor: microchip
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```yaml
board:
name: mec172xevb_assy6906
vendor: microchip
socs:
- name: mec172x_nsz
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```restructuredtext
.. _stm32wb5mm_dk_discovery_kit:
ST STM32WB5MM-DK
################
Overview
********
The STM32WB5MM-DK Discovery kit is designed as a complete demonstration
and development platform for the STMicroelectronics STM32W5MMG module based
on the Arm |reg| Cortex |reg|-M4 and Arm |reg| Cortex |reg|-M0+ cores.
The STM32 device is a multi-protocol wireless and ultra-low-power device
embedding a powerful and ultra-low-power radio compliant with the
Bluetooth |reg| Low Energy (BLE) SIG specification v5.2 and with
IEEE 802.15.4-2011.
STM32WB5MM-DK supports the following features:
* STM32WB5MMG (1-Mbyte Flash memory, 256-Kbyte SRAM)
- Dual-core 32bit (Arm |reg| Cortex |reg|-M4 and M0+)
- 2.4 GHz RF transceiver
- 0.96-inch 128x64 OLED display
- 128-Mbit Quad-SPI NOR Flash Memory
- Temperature sensor
- Accelerometer/gyroscope sensor
- Time-of-Flight and gesture-detection sensor
- Digital microphone
- RGB LED
- Infrared LED
- 3 push-buttons (2 users and 1 reset) and 1 touch key button
* Board connectors:
- STMod+
- ARDUINO |reg| Uno V3 expansion connector
- USB user with Micro-B connector
- TAG10 10-pin footprint
* Flexible power-supply options:
- ST-LINK/V2-1 USB connector,
- 5 V delivered by:
- ARDUINO |reg|,
- external connector,
- USB charger, or USB power
* On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration
- Virtual COM port and debug port
.. image:: img/STM32WB5MM_DK.jpg
:align: center
:alt: STM32WB5MM-DK
More information about the board can be found in `STM32WB5MM-DK on www.st.com`_.
Hardware
********
STM32WB5MMG is an ultra-low-power and small form factor certified 2.4 GHz
wireless module. It supports Bluetooth |reg| Low Energy 5.4, Zigbee |reg| 3.0,
OpenThread, dynamic, and static concurrent modes, and 802.15.4 proprietary
protocols.
Based on the STMicroelectronics STM32WB55VGY wireless microcontroller,
STM32WB5MMG provides best-in-class RF performance thanks to its high
receiver sensitivity and output power signal. Its low-power features
enable extended battery life, small coin-cell batteries, and energy harvesting.
- Ultra-low-power with FlexPowerControl
- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU
- Radio:
- 2.4GHz
- RF transceiver supporting:
- Bluetooth |reg| 5.4 specification,
- IEEE 802.15.4-2011 PHY and MAC,
- Zigbee |reg| 3.0
- RX sensitivity:
- -96 dBm (Bluetooth |reg| Low Energy at 1 Mbps),
- -100 dBm (802.15.4)
- Programmable output power up to +6 dBm with 1 dB steps
- Integrated balun to reduce BOM
- Support for 2 Mbps
- Support GATT caching
- Support EATT (enhanced ATT)
- Support advertising extension
- Accurate RSSI to enable power control
- Clock Sources:
- 32 MHz crystal oscillator with integrated
trimming capacitors (Radio and CPU clock)
- 32 kHz crystal oscillator for RTC (LSE)
- Internal low-power 32 kHz (5%) RC (LSI1)
- Internal low-power 32 kHz (stability
500 ppm) RC (LSI2)
- Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
0.25% accuracy)
- High speed internal 16 MHz factory
trimmed RC (1%)
- 2x PLL for system clock, USB, SAI, ADC
More information about STM32WB55RG can be found here:
- `STM32WB5MM-DK on www.st.com`_
- `STM32WB5MMG datasheet`_
Supported Features
==================
The Zephyr STM32WB5MM-DK board configuration supports the following hardware features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on this Zephyr port.
The default configuration can be found in the defconfig file:
:zephyr_file:`boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig`
Bluetooth and compatibility with STM32WB Copro Wireless Binaries
================================================================
To operate bluetooth on STM32WB5MMG, Cortex-M0 core should be flashed with
a valid STM32WB Coprocessor binaries (either 'Full stack' or 'HCI Layer').
These binaries are delivered in STM32WB Cube packages, under
``Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/``.
For compatibility information with the various versions of these binaries,
please check `modules/hal/stm32/lib/stm32wb/hci/README`_
in the ``hal_stm32`` repo.
Note that since STM32WB Cube package V1.13.2, `"full stack"` binaries are not
compatible anymore for a use in Zephyr and only `"HCI Only"` versions should be
used on the M0 side.
Connections and IOs
===================
Default Zephyr Peripheral Mapping:
----------------------------------
.. rst-class:: rst-columns
- UART_1 TX/RX : PB7/PB6 ( Connected to ST-Link VCP)
- LPUART_1 TX/RX : PA3/PA2
- USB : PA11/PA12
- SWD : PA13/PA14
- I2C3: SDA/SCL PB11/PB13 (Sensor I2C bus)
System Clock
------------
STM32WB5MMG System Clock could be driven by internal or external oscillator,
as well as main PLL clock. By default System clock is driven by HSE clock at 32MHz.
Serial Port
-----------
STM32WB5MM-DK board has 2 (LP)U(S)ARTs. The Zephyr console output is assigned to USART1.
Default settings are ``115200 8N1``.
LEDs
----
STM32WB5MM-DK has two types of LEDs, The resources coming from STM32WB5MMG are
shared between the RGB and IR LEDs. It is not possible to use them
simultaneously. The selection is done by JP4 and JP5 jumpers.
To use the RGB LED, JP5 must be ON and JP4 OFF. In this configuration,
GPIO_SELECT2 (PH1) is the chip select for this RGB device on SPI1.
Buttons
-------
STM32WB5MM-DK has two user buttons. The first button is mapped to PC12,
and the second to PC13. They have the aliases sw0 and sw1 respectively.
Programming and Debugging
*************************
Applications for the ``stm32wb5mm_dk`` board configuration can be built the
usual way (see :ref:`build_an_application`).
Flashing
========
STM32WB5MM-DK has an on-board ST-Link to flash and debug the firmware on the
module.
Flashing ``hello_world`` application to STM32WB5MM-DK
------------------------------------------------------
Connect the STM32WB5MM-DK to your host computer using the USB port (CN11).
Then build and flash an application. Here is an example for the ``hello_world``
application.
Run a serial host program to connect with your STM32WB5MM-DK board:
.. code-block:: console
$ minicom -D /dev/ttyACM0
Then first build and flash the application for the STM32WB5MM-DK board.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32wb5mm_dk
:goals: build flash
Reset the board and you should see the following messages on the console:
.. code-block:: console
Hello World! stm32w5mm_dk
Debugging
=========
You can debug an application in the usual way. Here is an example for the
`Hello_World`_ application.
.. zephyr-app-commands::
:zephyr-app: samples/hello_world
:board: stm32wb5mm_dk
:maybe-skip-config:
:goals: debug
.. _STM32WB5MM-DK on www.st.com:
path_to_url
.. _STM32WB5MMG datasheet:
path_to_url
.. _modules/hal/stm32/lib/stm32wb/hci/README:
path_to_url
.. _Hello_World:
path_to_url
``` | /content/code_sandbox/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 2,076 |
```unknown
if BOARD_MEC172XEVB_ASSY6906
config INPUT
default y if KSCAN
if RTOS_TIMER
# XEC RTOS timer HW frequency is fixed at 32768 Hz.
# The driver requires tickless mode and ticks per second to be 32768 for
# accurate operation.
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config SYS_CLOCK_TICKS_PER_SEC
default 32768
endif # RTOS_TIMER
if !RTOS_TIMER
# If RTOS timer is not enabled we use ARM Cortex-M
# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
# processor clock divider register. We assume PCR processor clock divider
# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV
#
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 96000000
config SYS_CLOCK_TICKS_PER_SEC
default 1000
endif # RTOS_TIMER
endif # BOARD_MEC172XEVB_ASSY6906
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 220 |
```unknown
#
#
#
CONFIG_RTOS_TIMER=y
CONFIG_CLOCK_CONTROL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 37 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mec172xnsz.dtsi>
#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
/ {
model = "Microchip MEC172XEVB_ASSY6906 evaluation board";
compatible = "microchip,mec172xevb_assy6906", "microchip,mec172xnsz";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart1;
};
aliases {
led0 = &led4;
led1 = &led3;
i2c0 = &i2c_smb_0;
i2c-0 = &i2c_smb_0;
i2c1 = &i2c_smb_1;
i2c7 = &i2c_smb_2;
pwm-0 = &pwm0;
watchdog0 = &wdog;
};
leds {
compatible = "gpio-leds";
led4: led_0 {
/* GPIO241/CMP_VOUT0/PWM0_ALT on schematic,
* LED4 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_241 GPIO_ACTIVE_HIGH>;
label = "LED 4";
};
led3: led_1 {
/* GPIO175/CMP_VOUT1/PWM8_ALT on schematic,
* LED5 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_175 GPIO_ACTIVE_HIGH>;
label = "LED 5";
};
};
};
&cpu0 {
clock-frequency = <96000000>;
status = "okay";
};
/* Initialize ECIA. Does not initialize child devices */
&ecia {
status = "okay";
};
/* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */
&girq24 {
status = "okay";
};
&girq25 {
status = "okay";
};
&rtimer {
status = "okay";
};
&pcr {
status = "okay";
};
&uart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc00_gpio200 &adc03_gpio203
&adc04_gpio204 &adc05_gpio205>;
pinctrl-1 = <&adc00_gpio200_sleep &adc03_gpio203_sleep
&adc04_gpio204_sleep &adc05_gpio205_sleep>;
pinctrl-names = "default", "sleep";
};
&espi0 {
status = "okay";
pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
&espi_alert_n_gpio063 &espi_clk_gpio065
&espi_io0_gpio070 &espi_io1_gpio071
&espi_io2_gpio072 &espi_io3_gpio073 >;
pinctrl-names = "default";
};
/* enable various eSPI child devices (host facing) */
&kbc0 {
status = "okay";
};
&acpi_ec0 {
status = "okay";
};
&acpi_ec1 {
status = "okay";
};
&emi0 {
status = "okay";
};
&p80bd0 {
status = "okay";
};
/* I2C */
&i2c_smb_0 {
status = "okay";
port_sel = <0>;
pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
pinctrl-names = "default";
};
&i2c00_scl_gpio004 {
drive-open-drain;
output-enable;
output-high;
};
&i2c00_sda_gpio003 {
drive-open-drain;
output-enable;
output-high;
};
&i2c_smb_1 {
status = "okay";
port_sel = <1>;
pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;
pinctrl-names = "default";
pca9555@26 {
compatible = "nxp,pca95xx";
/* Depends on JP53 for device address.
* Pin 1-2 = A0, pin 3-4 = A1, pin 5-6 = A2.
* Address is: 0100<A2><A1><A0>b.
*
* Default has pin 1-2 on JP53 connected,
* resulting in device address 0x26.
*/
reg = <0x26>;
gpio-controller;
#gpio-cells = <2>;
};
};
&i2c01_scl_gpio131 {
drive-open-drain;
output-enable;
output-high;
};
&i2c01_sda_gpio130 {
drive-open-drain;
output-enable;
output-high;
};
&i2c_smb_2 {
status = "okay";
port_sel = <7>;
pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
pinctrl-names = "default";
};
&i2c07_scl_gpio013 {
drive-open-drain;
output-enable;
output-high;
};
&i2c07_sda_gpio012 {
drive-open-drain;
output-enable;
output-high;
};
&spi0 {
status = "okay";
compatible = "microchip,xec-qmspi-ldma";
clock-frequency = <4000000>;
lines = <4>;
chip-select = <0>;
pinctrl-0 = < &shd_cs0_n_gpio055
&shd_clk_gpio056
&shd_io0_gpio223
&shd_io1_gpio224
&shd_io2_gpio227
&shd_io3_gpio016 >;
pinctrl-names = "default";
};
&kbd0 {
status = "okay";
pinctrl-0 = < &ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026
&ksi4_gpio027 &ksi5_gpio030 &ksi6_gpio031 &ksi7_gpio032
&kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso03_gpio047
&kso04_gpio107 &kso05_gpio112 &kso06_gpio113 &kso07_gpio120
&kso08_gpio121 &kso09_gpio122 &kso10_gpio123 &kso11_gpio124
&kso12_gpio125 &kso13_gpio126 >;
pinctrl-1 = < &ksi0_gpio017_sleep &ksi1_gpio020_sleep &ksi2_gpio021_sleep
&ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep
&ksi6_gpio031_sleep &ksi7_gpio032_sleep &kso00_gpio040_sleep
&kso01_gpio045_sleep &kso02_gpio046_sleep &kso03_gpio047_sleep
&kso04_gpio107_sleep &kso05_gpio112_sleep &kso06_gpio113_sleep
&kso07_gpio120_sleep &kso08_gpio121_sleep &kso09_gpio122_sleep
&kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep
&kso13_gpio126_sleep >;
pinctrl-names = "default", "sleep";
row-size = <8>;
col-size = <16>;
kscan_input: kscan-input {
compatible = "zephyr,kscan-input";
};
};
&ksi0_gpio017 {
bias-pull-up;
};
&ksi1_gpio020 {
bias-pull-up;
};
&ksi2_gpio021 {
bias-pull-up;
};
&ksi3_gpio026 {
bias-pull-up;
};
&ksi4_gpio027 {
bias-pull-up;
};
&ksi5_gpio030 {
bias-pull-up;
};
&ksi6_gpio031 {
bias-pull-up;
};
&ksi7_gpio032 {
bias-pull-up;
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_gpio053>;
pinctrl-names = "default";
};
&tach0 {
status = "okay";
pinctrl-0 = <&tach0_gpio050>;
pinctrl-names = "default";
};
&ps2_0 {
status = "okay";
pinctrl-0 = <&ps2_clk0a_gpio114 &ps2_dat0a_gpio115>;
pinctrl-1 = <&ps2_clk0a_gpio114_sleep &ps2_dat0a_gpio115_sleep>;
pinctrl-names = "default", "sleep";
};
&timer5 {
status = "okay";
};
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,936 |
```python
#!/usr/bin/env python3
#
#
'''
This script allows flashing a mec172xevb_assy6906 board
attached to a remote system.
Usage:
west flash -r misc-flasher -- mec172x_remote_flasher.py <remote host>
Note:
1. SSH access to remote host with write access to remote /tmp.
Since the script does multiple SSH connections, it is a good idea
to setup public key authentication and ssh-agent.
2. Dediprog "dpcmd" available in path on remote host.
(Can be compiled from path_to_url
3. SSH user must have permission to access USB devices,
since dpcmd needs USB access to communicate with
the Dediprog programmer attached to remote host.
To use with twister, a hardware map file is needed.
Here is a sample map file:
- connected: true
available: true
id: mec172xevb_assy6906
platform: mec172xevb_assy6906
product: mec172xevb_assy6906
runner: misc-flasher
runner_params:
- <ZEPHYR_BASE>/boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py
- <remote host>
serial_pty: "nc,<remote host>,<ser2net port>"
The sample map file assumes the serial console is exposed via ser2net,
and that it can be accessed using nc (netcat).
To use twister:
./scripts/twister --hardware-map <hw map file> --device-testing
Required:
* Fabric (path_to_url
'''
import argparse
import hashlib
import pathlib
import sys
from datetime import datetime
import fabric
from invoke.exceptions import UnexpectedExit
def calc_sha256(spi_file):
'''
Calculate a SHA256 of the SPI binary content plus current
date string.
This is used for remote file name to avoid file name
collision.
'''
sha256 = hashlib.sha256()
# Use SPI file content to calculate SHA.
with open(spi_file, "rb") as fbin:
spi_data = fbin.read()
sha256.update(spi_data)
# Add a date/time to SHA to hopefully
# further avoid file name collision.
now = datetime.now().isoformat()
sha256.update(now.encode("utf-8"))
return sha256.hexdigest()
def parse_args():
'''
Parse command line arguments.
'''
parser = argparse.ArgumentParser(allow_abbrev=False)
# Fixed arguments
parser.add_argument("build_dir",
help="Build directory")
parser.add_argument("remote_host",
help="Remote host name or IP address")
# Arguments about remote machine
remote = parser.add_argument_group("Remote Machine")
remote.add_argument("--remote-tmp", required=False,
help="Remote temporary directory to store SPI binary "
"[default=/tmp for Linux remote]")
remote.add_argument("--dpcmd", required=False, default="dpcmd",
help="Full path to dpcmd on remote machine")
# Remote machine type.
# This affects how remote path is constructed.
remote_type = remote.add_mutually_exclusive_group()
remote_type.add_argument("--remote-is-linux", required=False,
default=True, action="store_true",
help="Set if remote machine is a Linux-like machine [default]")
remote_type.add_argument("--remote-is-win", required=False,
action="store_true",
help="Set if remote machine is a Windows machine")
return parser.parse_args()
def main():
'''
Main
'''
args = parse_args()
# Check for valid arguments and setup variables.
if not args.remote_tmp:
if args.remote_is_win:
# Do not assume a default temporary on Windows,
# as it is usually under user's directory and
# we do not know enough to construct a valid path
# at this time.
print("[ERROR] --remote-tmp is required for --remote-is-win")
sys.exit(1)
if args.remote_is_linux:
remote_tmp = pathlib.PurePosixPath("/tmp")
else:
if args.remote_is_win:
remote_tmp = pathlib.PureWindowsPath(args.remote_tmp)
elif args.remote_is_linux:
remote_tmp = pathlib.PurePosixPath(args.remote_tmp)
# Construct full path to SPI binary.
spi_file_path = pathlib.Path(args.build_dir)
spi_file_path = spi_file_path.joinpath("zephyr", "spi_image.bin")
# Calculate a sha256 digest for SPI file.
# This is used for remote file to avoid file name collision
# if there are multiple MEC17x attached to remote machine
# and all are trying to flash at same time.
sha256 = calc_sha256(spi_file_path)
# Construct full path on remote to store
# the transferred SPI binary.
remote_file_name = remote_tmp.joinpath(f"mec172x_{sha256}.bin")
print(f"[INFO] Build directory: {args.build_dir}")
print(f"[INFO] Remote host: {args.remote_host}")
# Connect to remote host via SSH.
ssh = fabric.Connection(args.remote_host, forward_agent=True)
print("[INFO] Sending file...")
print(f"[INFO] Local SPI file: {spi_file_path}")
print(f"[INFO] Remote SPI file: {remote_file_name}")
# Open SFTP channel, and send the SPI binary over.
sftp = ssh.sftp()
sftp.put(str(spi_file_path), str(remote_file_name))
# Run dpcmd to flash the device.
try:
dpcmd_cmd = f"{args.dpcmd} --auto {str(remote_file_name)} --verify"
print(f"[INFO] Invoking: {dpcmd_cmd}...")
ssh.run(dpcmd_cmd)
except UnexpectedExit:
print("[ERR ] Cannot flashing SPI binary!")
# Remove temporary file.
print(f"[INFO] Removing remote file {remote_file_name}")
sftp.remove(str(remote_file_name))
sftp.close()
ssh.close()
if __name__ == "__main__":
main()
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py | python | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,332 |
```cmake
include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
``` | /content/code_sandbox/boards/microchip/ev11l78a/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 19 |
```unknown
/*
*/
#include <dt-bindings/pinctrl/samd20eXab-pinctrl.h>
&pinctrl {
sercom0_spi_default: sercom0_spi_default {
group1 {
pinmux = <PA8C_SERCOM0_PAD0>,
<PA9C_SERCOM0_PAD1>,
<PA11C_SERCOM0_PAD3>;
};
};
sercom1_uart_default: sercom1_uart_default {
group1 {
pinmux = <PA18C_SERCOM1_PAD2>,
<PA19C_SERCOM1_PAD3>;
};
};
sercom3_i2c_default: sercom3_i2c_default {
group1 {
pinmux = <PA17D_SERCOM3_PAD1>,
<PA18D_SERCOM3_PAD2>;
};
};
adc_default: adc_default {
group1 {
pinmux = <PA4B_ADC_AIN4>,
<PA5B_ADC_AIN5>;
};
};
};
``` | /content/code_sandbox/boards/microchip/ev11l78a/ev11l78a-pinctrl.dtsi | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 226 |
```unknown
CONFIG_SOC_ATMEL_SAMD_OSC8M=y
CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y
CONFIG_BUILD_OUTPUT_HEX=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_INTERRUPT_DRIVEN=y
``` | /content/code_sandbox/boards/microchip/ev11l78a/ev11l78a_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 56 |
```cmake
# Suppress "unique_unit_address_if_enabled" to handle the following overlaps:
# - /soc/pinmux@41004400 & /soc/gpio@41004400
# - /soc/pinmux@41004480 & /soc/gpio@41004480
list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled")
``` | /content/code_sandbox/boards/microchip/ev11l78a/pre_dt_board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```unknown
/*
*
*/
/dts-v1/;
#include <freq.h>
#include <mem.h>
#include <atmel/samd20.dtsi>
#include <atmel/samx2xx16.dtsi>
#include "ev11l78a-pinctrl.dtsi"
/ {
model = "Microchip EV11L78A";
compatible = "atmel,samd20e16", "atmel,samd20";
aliases {
led0 = &cap_mis_led;
spi0 = &sercom0;
i2c0 = &sercom3;
};
chosen {
zephyr,console = &sercom1;
zephyr,shell-uart = &sercom1;
zephyr,sram = &sram0;
zephyr,flash = &flash0;
};
leds {
compatible = "gpio-leds";
cap_mis_led: led_0 {
gpios = <&porta 23 GPIO_ACTIVE_HIGH>;
label = "CAP_MIS";
};
};
csa_i_sense: i_sense {
compatible = "current-sense-amplifier";
io-channels = <&adc 5>;
sense-resistor-micro-ohms = <4000>;
sense-gain-mult = <100>;
};
};
&cpu0 {
clock-frequency = <DT_FREQ_M(48)>;
};
&sercom0 {
status = "okay";
compatible = "atmel,sam0-spi";
dipo = <0>;
dopo = <2>;
#address-cells = <1>;
#size-cells = <0>;
cs-gpios = <&porta 10 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&sercom0_spi_default>;
pinctrl-names = "default";
};
&sercom1 {
status = "okay";
compatible = "atmel,sam0-uart";
current-speed = <115200>;
rxpo = <3>;
txpo = <1>;
pinctrl-0 = <&sercom1_uart_default>;
pinctrl-names = "default";
};
&sercom3 {
status = "okay";
compatible = "atmel,sam0-i2c";
clock-frequency = <I2C_BITRATE_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&sercom3_i2c_default>;
pinctrl-names = "default";
};
&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
/*
* The final 16 KiB is reserved for the application.
* Storage partition will be used by FCB/LittleFS/NVS
* if enabled.
*/
storage_partition: partition@c000 {
label = "storage";
reg = <DT_SIZE_K(64-16) DT_SIZE_K(16)>;
};
};
};
&adc {
status = "okay";
prescaler = <32>;
#address-cells = <1>;
#size-cells = <0>;
channel@4 {
reg = <4>;
zephyr,gain = "ADC_GAIN_1_2";
zephyr,reference = "ADC_REF_VDD_1_2";
zephyr,vref-mv = <1650>;
zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
zephyr,resolution = <12>;
zephyr,input-positive = <4>;
};
pinctrl-0 = <&adc_default>;
pinctrl-names = "default";
};
``` | /content/code_sandbox/boards/microchip/ev11l78a/ev11l78a.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 802 |
```yaml
board:
name: ev11l78a
vendor: microchip
socs:
- name: samd20e16
``` | /content/code_sandbox/boards/microchip/ev11l78a/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 32 |
```yaml
identifier: ev11l78a
name: UPD301C Basic Sink Application Example
type: mcu
arch: arm
ram: 32
flash: 64
toolchain:
- zephyr
- gnuarmemb
- xtools
supported:
- adc
- gpio
- i2c
- spi
- uart
vendor: atmel
``` | /content/code_sandbox/boards/microchip/ev11l78a/ev11l78a.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 89 |
```unknown
if USBC_STACK
# Kernel Options due to Low Memory (4k)
CONFIG_LOG_BUFFER_SIZE=256
CONFIG_MAIN_STACK_SIZE=640
CONFIG_IDLE_STACK_SIZE=200
CONFIG_ISR_STACK_SIZE=512
CONFIG_USBC_STACK_SIZE=512
# Prevent Interrupt Vector Table in RAM
CONFIG_SRAM_VECTOR_TABLE=n
# This board only supports the sink role, so
# no need to ever implement source for it.
CONFIG_USBC_CSM_SINK_ONLY=y
endif # USBC_STACK
``` | /content/code_sandbox/boards/microchip/ev11l78a/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 106 |
```unknown
config BOARD_EV11L78A
select SOC_SAMD20E16
``` | /content/code_sandbox/boards/microchip/ev11l78a/Kconfig.ev11l78a | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 18 |
```ini
source [find interface/jlink.cfg]
transport select swd
# chip name
set CHIPNAME at91samd20e16
set ENDIAN little
set CPUTAPID 0x0bc11477
source [find target/at91samdXX.cfg]
reset_config trst_and_srst separate
$_TARGETNAME configure -event gdb-attach {
echo "Debugger attaching: halting execution"
reset halt
gdb_breakpoint_override hard
}
$_TARGETNAME configure -event gdb-detach {
echo "Debugger detaching: resuming execution"
resume
}
``` | /content/code_sandbox/boards/microchip/ev11l78a/support/openocd.cfg | ini | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 121 |
```restructuredtext
.. _ev11l78a:
UPD301C Basic Sink Application Example
######################################
Overview
********
The UPD301C Basic Sink Application Example Evaluation Kit (EV11L78A)
is a low-cost evaluation platform for Microchip's UPD301C Standalone
Programmable USB Power Delivery (PD) Controller. This RoHS-compliant
evaluation platform comes in a small form factor and adheres to the
USB Type-C Connector Specification and USB PD 3.0 specification.
.. figure:: img/ev11l78a.jpg
:width: 500px
:align: center
:alt: EV11L78A
UPD301C Basic Sink Application Example (Credit: `Microchip Technology`_)
Hardware
********
- ATSAMD20E16 ARM Cortex-M0+ processor at 48 MHz
- UPD301C combines a SAMD20 core and a UPD350 USB-PD controller
- Sink PDO Selector Switch
- Onboard LED Voltmeter
Supported Features
==================
The ev11l78a board configuration supports the following hardware
features:
.. list-table::
:header-rows: 1
* - Interface
- Controller
- Driver / Component
* - NVIC
- on-chip
- nested vector interrupt controller
* - Flash
- on-chip
- Can be used with LittleFS to store files
* - SYSTICK
- on-chip
- systick
* - WDT
- on-chip
- Watchdog
* - ADC
- on-chip
- Analog to Digital Converter
* - GPIO
- on-chip
- I/O ports
* - USART
- on-chip
- Serial ports
* - I2C
- on-chip
- I2C ports
* - SPI
- on-chip
- Serial Peripheral Interface ports
Other hardware features are not currently supported by Zephyr.
Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram.
The default configuration can be found in the Kconfig
:zephyr_file:`boards/microchip/ev11l78a/ev11l78a_defconfig`.
Serial Port
===========
The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs
(SERCOM1) is available on the Debug/Status header.
SPI Port
========
The SAMD20 MCU has 6 SERCOM based SPIs. One of the SPIs (SERCOM0)
is internally connected between the SAMD20 core and the UPD350.
IC Port
========
The SAMD20 MCU has 6 SERCOM based I2Cs. One of the I2Cs (SERCOM3)
is available on the Debug/Status header.
References
**********
.. target-notes::
.. _Microchip Technology:
path_to_url
.. _EV11L78A Schematics:
path_to_url
``` | /content/code_sandbox/boards/microchip/ev11l78a/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 655 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mec172xnsz.dtsi>
#include <microchip/mec172x/mec172xnsz-pinctrl.dtsi>
/ {
model = "Microchip MEC172XMODULAR_ASSY6930 evaluation board";
compatible = "microchip,mec172xmodular_assy6930", "microchip,mec172xnsz";
chosen {
zephyr,sram = &sram0;
zephyr,flash = &flash0;
zephyr,console = &uart1;
};
aliases {
led1 = &led3;
led2 = &led2;
i2c0 = &i2c_smb_0;
i2c1 = &i2c_smb_1;
i2c7 = &i2c_smb_2;
pwm-0 = &pwm0;
};
leds {
compatible = "gpio-leds";
led3: led_1 {
/* GPIO157/LED1 on schematic,
* LED3 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_157 GPIO_ACTIVE_HIGH>;
};
led2: led_2{
/* GPIO153/LED2 on schematic,
* LED2 on silkscreen.
*/
gpios = <MCHP_GPIO_DECODE_153 GPIO_ACTIVE_HIGH>;
};
};
};
&cpu0 {
clock-frequency = <96000000>;
status = "okay";
};
/* Initialize ECIA. Does not initialize child devices */
&ecia {
status = "okay";
};
/* Enable aggregated GIRQ24 and GIRQ25 for eSPI virtual wires interrupts */
&girq24 {
status = "okay";
};
&girq25 {
status = "okay";
};
&rtimer {
status = "okay";
};
&pcr {
status = "okay";
};
&uart1 {
status = "okay";
current-speed = <115200>;
pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
pinctrl-names = "default";
};
&adc0 {
status = "okay";
pinctrl-0 = <&adc00_gpio200 &adc03_gpio203
&adc04_gpio204 &adc05_gpio205>;
pinctrl-names = "default";
};
&espi0 {
status = "okay";
pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
&espi_alert_n_gpio063 &espi_clk_gpio065
&espi_io0_gpio070 &espi_io1_gpio071
&espi_io2_gpio072 &espi_io3_gpio073 >;
pinctrl-names = "default";
};
/* enable various eSPI child devices (host facing) */
&kbc0 {
status = "okay";
};
&acpi_ec0 {
status = "okay";
};
&acpi_ec1 {
status = "okay";
};
&emi0 {
status = "okay";
};
&p80bd0 {
status = "okay";
};
/* I2C */
&i2c_smb_0 {
status = "okay";
port_sel = <0>;
pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
pinctrl-names = "default";
};
&i2c00_scl_gpio004 {
drive-open-drain;
output-enable;
output-high;
};
&i2c00_sda_gpio003 {
drive-open-drain;
output-enable;
output-high;
};
&i2c_smb_1 {
status = "okay";
port_sel = <1>;
pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;
pinctrl-names = "default";
};
&i2c01_scl_gpio131 {
drive-open-drain;
output-enable;
output-high;
};
&i2c01_sda_gpio130 {
drive-open-drain;
output-enable;
output-high;
};
&i2c_smb_2 {
status = "okay";
port_sel = <7>;
pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
pinctrl-names = "default";
};
&i2c07_scl_gpio013 {
drive-open-drain;
output-enable;
output-high;
};
&i2c07_sda_gpio012 {
drive-open-drain;
output-enable;
output-high;
};
&spi0 {
status = "okay";
compatible = "microchip,xec-qmspi-ldma";
clock-frequency = <4000000>;
lines = <4>;
chip-select = <0>;
pinctrl-0 = < &shd_cs0_n_gpio055
&shd_clk_gpio056
&shd_io0_gpio223
&shd_io1_gpio224
&shd_io2_gpio227
&shd_io3_gpio016 >;
pinctrl-names = "default";
};
&kbd0 {
status = "okay";
pinctrl-0 = < &ksi0_gpio017 &ksi1_gpio020 &ksi2_gpio021 &ksi3_gpio026
&ksi4_gpio027 &ksi5_gpio030 &ksi6_gpio031 &ksi7_gpio032
&kso00_gpio040 &kso01_gpio045 &kso02_gpio046 &kso03_gpio047
&kso04_gpio107 &kso05_gpio112 &kso06_gpio113 &kso07_gpio120
&kso08_gpio121 &kso09_gpio122 &kso10_gpio123 &kso11_gpio124
&kso12_gpio125 &kso13_gpio126 >;
pinctrl-1 = < &ksi0_gpio017_sleep &ksi1_gpio020_sleep &ksi2_gpio021_sleep
&ksi3_gpio026_sleep &ksi4_gpio027_sleep &ksi5_gpio030_sleep
&ksi6_gpio031_sleep &ksi7_gpio032_sleep &kso00_gpio040_sleep
&kso01_gpio045_sleep &kso02_gpio046_sleep &kso03_gpio047_sleep
&kso04_gpio107_sleep &kso05_gpio112_sleep &kso06_gpio113_sleep
&kso07_gpio120_sleep &kso08_gpio121_sleep &kso09_gpio122_sleep
&kso10_gpio123_sleep &kso11_gpio124_sleep &kso12_gpio125_sleep
&kso13_gpio126_sleep >;
pinctrl-names = "default", "sleep";
row-size = <8>;
col-size = <16>;
kscan_input: kscan-input {
compatible = "zephyr,kscan-input";
};
};
&ksi0_gpio017 {
bias-pull-up;
};
&ksi1_gpio020 {
bias-pull-up;
};
&ksi2_gpio021 {
bias-pull-up;
};
&ksi3_gpio026 {
bias-pull-up;
};
&ksi4_gpio027 {
bias-pull-up;
};
&ksi5_gpio030 {
bias-pull-up;
};
&ksi6_gpio031 {
bias-pull-up;
};
&ksi7_gpio032 {
bias-pull-up;
};
&pwm0 {
status = "okay";
pinctrl-0 = <&pwm0_gpio053>;
pinctrl-names = "default";
};
&tach0 {
status = "okay";
pinctrl-0 = <&tach0_gpio050>;
pinctrl-names = "default";
};
&ps2_0 {
status = "okay";
pinctrl-0 = <&ps2_clk0a_gpio114 &ps2_dat0a_gpio115>;
pinctrl-names = "default";
};
&timer5 {
status = "okay";
};
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 1,687 |
```cmake
set(SPI_IMAGE_NAME spi_image.bin)
board_set_flasher_ifnset(dediprog)
# --vcc=0 - use 3.5V to flash
board_finalize_runner_args(dediprog
"--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}"
"--vcc=0"
)
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 69 |
```unknown
#
#
#
CONFIG_RTOS_TIMER=y
CONFIG_CLOCK_CONTROL=y
CONFIG_GPIO=y
CONFIG_PINCTRL=y
CONFIG_SERIAL=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_ADC=y
CONFIG_I2C=y
CONFIG_ESPI=y
CONFIG_SPI=y
CONFIG_SPI_ASYNC=y
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 61 |
```unknown
config BOARD_MEC172XMODULAR_ASSY6930
select SOC_MEC172X_NSZ
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 24 |
```yaml
board:
name: mec172xmodular_assy6930
vendor: microchip
socs:
- name: mec172x_nsz
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 36 |
```yaml
#
#
#
identifier: mec172xmodular_assy6930
name: MEC172X MODULAR ASSY 6930
type: mcu
arch: arm
toolchain:
- zephyr
- gnuarmemb
ram: 64
flash: 352
supported:
- gpio
- pinmux
- i2c
vendor: microchip
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 87 |
```restructuredtext
.. _mec172xevb_assy6906:
Microchip MEC172xEVB ASSY6906
#############################
Overview
********
The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the
Microchip MEC172X series microcontrollers. This board needs to be mated with
part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate.
MEC172x and MEC152x SPI image formats are not compatible with each other.
.. image:: mec172xevb_assy6906.jpg
:align: center
:alt: MEC172X EVB ASSY 6906
Hardware
********
- MEC172x ARM Cortex-M4 Processor
- 416 KB RAM and 128 KB boot ROM
- Keyboard interface
- ADC & GPIO headers
- UART0 and UART1
- FAN0, FAN1, FAN2 headers
- FAN PWM interface
- JTAG/SWD, ETM and MCHP Trace ports
- PECI interface 3.0
- I2C voltage translator
- 10 SMBUS headers
- VCI interface
- 1 Hardware Driven PS/2 Port
- eSPI header
- 2 Sockets for SPI NOR chips
- One reset and VCC_PWRDGD pushbuttons
- One external PCA9555 I/O port with jumper selectable I2C address.
- One external LTC2489 delta-sigma ADC with jumper selectable I2C address.
- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector.
For more information about the SOC's please see `MEC172x Reference Manual`_
Supported Features
==================
The mec172xevb_assy6906 board configuration supports the following hardware
features:
+-----------+------------+-------------------------------------+
| Interface | Controller | Driver/Component |
+===========+============+=====================================+
| NVIC | on-chip | nested vector interrupt controller |
+-----------+------------+-------------------------------------+
| SYSTICK | on-chip | systick |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port |
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| PINMUX | on-chip | pinmux |
+-----------+------------+-------------------------------------+
| PS/2 | on-chip | ps2 |
+-----------+------------+-------------------------------------+
| KSCAN | on-chip | kscan |
+-----------+------------+-------------------------------------+
| TACH | on-chip | tachometer |
+-----------+------------+-------------------------------------+
| RPMFAN | on-chip | Fan speed controller |
+-----------+------------+-------------------------------------+
Other hardware features are not currently supported by Zephyr.
The default configuration can be found in the
:zephyr_file:`boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file.
Connections and IOs
===================
This evaluation board kit is comprised of the following HW blocks:
- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_
- MEC172x 144WFBGA SOLDER DC ASSY 6914 with MEC172x silicon `MEC172x Daughter Card Schematic`_
- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_
System Clock
============
The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the
on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock
control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in
the references at the end of this document.
Serial Port
===========
UART1 is configured for serial logs.
Jumper settings
***************
Please follow the jumper settings below to properly demo this
board. Advanced users may deviate from this recommendation.
Jumper setting for MEC172x EVB Assy 6906 Rev A1p0
=================================================
Power-related jumpers
---------------------
If you wish to power from +5V power brick, then connect to barrel connector ``P1``
(5.5mm OD, 2.1mm ID) and move the jumper to ``JP30 5-6``.
If you wish to power from micro-USB type A/B connector ``P2``, move the
jumper to ``JP30 7-8``.
.. note:: A single jumper is required in ``JP30``.
+------+-------+-------+------+------+
| JP31 | JP158 | JP159 | JP40 | JP42 |
+======+=======+=======+======+======+
| 2-3 | 2-3 | 2-3 | 1-2 | 1-2 |
+------+-------+-------+------+------+
+------+------+------+------+------+------+------+
| JP36 | JP37 | JP38 | JP39 | JP41 | JP43 | JP44 |
+======+======+======+======+======+======+======+
| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 |
+------+------+------+------+------+------+------+
+------+------+------+------+------+------+------+------+------+
| JP45 | JP46 | JP47 | JP50 | JP51 | JP52 | JP55 | JP56 | JP57 |
+======+======+======+======+======+======+======+======+======+
| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 |
+------+------+------+------+------+------+------+------+------+
+------+------+------+------+------+------+------+
| JP59 | JP60 | JP61 | JP62 | JP63 | JP65 | JP66 |
+======+======+======+======+======+======+======+
| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 |
+------+------+------+------+------+------+------+
These jumpers configure VCC Power good and nRESET_IN.
+------------------+-------------+
| JP32 | JP33 |
| (VCC Power good) | (nRESET_IN) |
+==================+=============+
| 1-2 | 1-2 |
+------------------+-------------+
Boot-ROM Straps
---------------
These jumpers configure MEC172x Boot-ROM straps.
+------------+--------------+-------------+-------------+---------------+
| JP1 | JP2 | JP3 | JP7 | JP160 |
| (CR_STRAP) | (JTAG_STRAP) | (CMP_STRAP) | (BSS_STRAP) | (UART_BSTRAP) |
+============+==============+=============+=============+===============+
| 1-2 | 2-3 | 2-3 | 1-2 | 1-2 |
+------------+--------------+-------------+-------------+---------------+
``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples
SHD SPI CS0# and if high, it loads code from SHD SPI.
Peripheral Routing Jumpers
--------------------------
Each column of the following table illustrates how to enable UART0, UART1, SHD SPI
and SWD, respectively.
+-------+-------+------+------+------+------+------+
| UART0 (P11) |
+-------+-------+------+------+------+------+------+
| JP13 | JP17 | JP19 | JP22 | JP88 | JP89 | JP93 |
+=======+=======+======+======+======+======+======+
| 2-3 | 2-3 | 1-2 | 1-2 | 2-3 | 2-3 | 1-3 |
+-------+-------+------+------+------+------+------+
| 5-6 | 5-6 | 4-5 | 4-5 | | | 2-4 |
+-------+-------+------+------+------+------+------+
| 8-9 | 8-9 | | | | | |
+-------+-------+------+------+------+------+------+
| 11-12 | 11-12 | | | | | |
+-------+-------+------+------+------+------+------+
| 14-15 | 14-15 | | | | | |
+-------+-------+------+------+------+------+------+
| 17-18 | 17-18 | | | | | |
+-------+-------+------+------+------+------+------+
| | 20-21 | | | | | |
+-------+-------+------+------+------+------+------+
| | 23-24 | | | | | |
+-------+-------+------+------+------+------+------+
+------+------+-------+-------+------+------+-------+-----+--------+------+------+------+-------+
| UART1 |
+---------------------------------------------------+-------------------------------------------+
| (P12) | (P2) |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
| JP11 | JP14 | JP19 | JP24 | JP90 | JP94 | JP157 | JP11 | JP19 | JP24 | JP90 | JP94 | JP157 |
+======+======+=======+=======+======+======+=======+======+=======+======+======+======+=======+
| 1-2 | 1-2 | 20-21 | 2-3 | 2-3 | 1-3 | 1-2 | 1-2 | 11-12 | 5-6 | 2-3 | 1-3 | 1-3 |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
| 4-5 | | | 5-6 | | 2-4 | 4-5 | 4-5 | | 8-9 | | 2-4 | 4-6 |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
| 8-9 | | | 8-9 | | | 7-8 | | |17-18 | | | 7-9 |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
| | | | 11-12 | | | 10-11 | | |23-24 | | | 10-12 |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
| | | | 14-15 | | | | | | | | | |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
| | | | 17-18 | | | | | | | | | |
+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+
NOTE: The "Hello World" example outputs at ``UART1 P12`` .
+----------------------+-------+--------+
| SHD_SPI | SWD | LED4-5 |
+-------+------+-------+-------+--------+
| JP23 | JP25 | JP156 | J18 | JP21 |
+=======+======+=======+=======+========+
| 2-3 | 1-2 | 1-2 | 8-9 | 4-5 |
+-------+------+-------+-------+--------+
| 8-9 | | | 11-12 | 16-17 |
+-------+------+-------+-------+--------+
| 14-15 | | | | |
+-------+------+-------+-------+--------+
| 17-18 | | | | |
+-------+------+-------+-------+--------+
Jumper settings for MEC172x 144WFBGA Socket DC Assy 6914 Rev A0p1
=================================================================
The jumper configuration explained above covers the base board. The ASSY
6914 MEC172x CPU board provides capability for an optional, external 32KHz
clock source. The card includes a 32KHz crystal oscillator. The card can
also be configured to use an external 50% duty cycle 32KHz source on the
XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable
register to select the external source matching the jumper settings. If
using the MEC172x internal silicon oscillator then the 32K jumper settings
are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please
refer to the schematic in reference section below.
Parallel 32KHz crystal configuration
------------------------------------
+-------+-------+
| JP1 | JP2 |
+=======+=======+
| 1-2 | 2-3 |
+-------+-------+
External 32KHz 50% duty cycle configuration
-------------------------------------------
+-------+-------+
| JP2 | JP3 |
+=======+=======+
| NC | 1-2 |
+-------+-------+
NOTE: ``JP121 3-4`` on base board also needs to be loaded.
Programming and Debugging
*************************
Setup
=====
#. If you use Dediprog SF100 programmer, then setup it.
Windows version can be found at the `SF100 Product page`_.
Linux version source code can be found at `SF100 Linux GitHub`_.
Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer.
For Linux please make sure that you copied ``60-dediprog.rules``
from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d)
then restart service using:
.. code-block:: console
$ udevadm control --reload
Add directory with program ``dpcmd`` (on Linux)
or ``dpcmd.exe`` (on Windows) to your ``PATH``.
#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within
that directory.
#. Make the image generation available for Zephyr, by making the tool
searchable by path, or by setting an environment variable
``MEC172X_SPI_GEN``, for example:
.. code-block:: console
export MEC172X_SPI_GEN=<path to tool>/mec172x_spi_gen_lin_x86_64
Note that the tools for Linux and Windows have different file names.
#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support.
If needed, a custom SPI image configuration file can be specified to override the
default one.
.. code-block:: console
export MEC172X_SPI_CFG=custom_spi_cfg.txt
Wiring
========
#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB.
.. image:: spidongle_assy6791.jpg
:align: center
:alt: SPI DONGLE ASSY 6791 Connected
#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip
``U3``. Make sure that your programmer's offset is 0x0.
For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips.
.. image:: dediprog_connector.jpg
:align: center
:alt: SF100 Connected
.. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers!
Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board.
Wiring connection is described in the table below.
+------------+---------------+
| Dediprog | Assy6791 |
| Connector | J6 Connector |
+============+===============+
| VCC | 1 |
+------------+---------------+
| GND | 2 |
+------------+---------------+
| CS | 3 |
+------------+---------------+
| CLK | 4 |
+------------+---------------+
| MISO | 6 |
+------------+---------------+
| MOSI | 5 |
+------------+---------------+
#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board
to your host computer using the RS232 cable.
#. Apply power to the board via a micro-USB cable.
Configure this option by using a jumper between ``JP30 7-8``.
.. image:: jp30_power_options.jpg
:align: center
:alt: Power Connection
Building
========
#. Build :ref:`hello_world` application as you would normally do.
#. The file :file:`spi_image.bin` will be created if the build system
can find the image generation tool. This binary image can be used
to flash the SPI chip.
Flashing
========
#. Run your favorite terminal program to listen for output.
Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it.
For example:
.. code-block:: console
$ minicom -D /dev/ttyUSB0 -o
The -o option tells minicom not to send the modem initialization
string. Connection should be configured as follows:
- Speed: 115200
- Data: 8 bits
- Parity: None
- Stop bits: 1
#. Flash your board using ``west`` from the second terminal window.
Split first and second terminal windows to view both of them.
.. code-block:: console
$ west flash
.. note:: When west process started press Reset button ``S2`` and do not release it
till the whole west process will not be finished successfully.
.. image:: Reset_Button.jpg
:align: center
:alt: Reset Button
.. note:: If you don't want to press Reset button every time, you can disconnect
SPI Dongle ASSY 6791 from the EVB during the west flash programming.
Then connect it back to the ``J34`` header and apply power to the EVB.
Result will be the same.
#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window.
If you don't see this message, press the Reset button and the message should appear.
Debugging
=========
This board comes with a Cortex ETM port which facilitates tracing and debugging
using a single physical connection. In addition, it comes with sockets for
JTAG only sessions.
Troubleshooting
===============
#. In case you don't see your application running, please make sure ``LED1`` and ``LED2``
are lit. If one of these is off, then check the power-related jumpers again.
#. If you can't program the board using Dediprog, disconnect the Assy6791
from the main board Assy6906 and try again.
#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again.
PCA9555 Enabling
================
#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed:
As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port,
however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log,
so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use
I2C01 port by making some jumpers setting as below:
+---------+---------+------------------------------------------+
| Pin 1 | Pin 2 | Comment |
+=========+=========+==========================================+
| JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY |
+---------+---------+------------------------------------------+
| JP53.1 | JP53.2 | Select address 0100b, which means 0x26 |
+---------+---------+------------------------------------------+
| JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 |
+---------+---------+------------------------------------------+
| JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 |
+---------+---------+------------------------------------------+
| JP77.7 | JP77.8 | External pull-up for I2C01_SDA |
+---------+---------+------------------------------------------+
| JP77.9 | JP77.10 | External pull-up for I2C01_SCL |
+---------+---------+------------------------------------------+
| JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 |
+---------+---------+------------------------------------------+
| JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 |
+---------+---------+------------------------------------------+
References
**********
.. target-notes::
.. _MEC172x Reference Manual:
path_to_url
.. _MEC172x EVB Schematic:
path_to_url
.. _MEC172x Daughter Card Schematic:
path_to_url
.. _SPI Dongle Schematic:
path_to_url
.. _MEC172x SPI Image Gen:
path_to_url
.. _SF100 Linux GitHub:
path_to_url
.. _SF100 Product page:
path_to_url
.. _SF100 Linux manual:
path_to_url
``` | /content/code_sandbox/boards/microchip/mec172xevb_assy6906/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 4,951 |
```unknown
if BOARD_MEC172XMODULAR_ASSY6930
config INPUT
default y if KSCAN
if RTOS_TIMER
# XEC RTOS timer HW frequency is fixed at 32768 Hz.
# The driver requires tickless mode and ticks per second to be 32768 for
# accurate operation.
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 32768
config SYS_CLOCK_TICKS_PER_SEC
default 32768
endif # RTOS_TIMER
if !RTOS_TIMER
# If RTOS timer is not enabled we use ARM Cortex-M
# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
# processor clock divider register. We assume PCR processor clock divider
# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV
#
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 96000000
config SYS_CLOCK_TICKS_PER_SEC
default 1000
endif # RTOS_TIMER
endif # BOARD_MEC172XMODULAR_ASSY6930
``` | /content/code_sandbox/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 222 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mpfs.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
cpus {
cpu@0 {
status = "disabled";
};
};
aliases {
led0 = &led0;
sw0 = &sw0;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
zephyr,console = &uart1;
zephyr,shell-uart = &uart1;
zephyr,sram = &sram1;
};
leds {
compatible = "gpio-leds";
led0: led0 {
gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
label = "LED_0";
};
};
keys {
compatible = "gpio-keys";
sw0: sw0 {
gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
label = "SW_0";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart1 {
status = "okay";
current-speed = <115200>;
clock-frequency = <150000000>;
};
&qspi0 {
status = "okay";
qspi_flash: spi-nor-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <5000000>;
size = <DT_SIZE_M(256)>;
jedec-id = [20 ba 19];
};
};
&spi1 {
status = "okay";
};
&syscontroller_qspi {
status = "okay";
sys_ctrl_flash: spi-nor-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <5000000>;
};
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/mpfs_icicle_smp.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 488 |
```cmake
set(SUPPORTED_EMU_PLATFORMS renode)
set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/mpfs250t.resc)
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/board.cmake | cmake | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 31 |
```unknown
/*
*
*/
/dts-v1/;
#include <microchip/mpfs.dtsi>
#include <zephyr/dt-bindings/input/input-event-codes.h>
#include <mem.h>
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
led0 = &led0;
sw0 = &sw0;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
zephyr,console = &uart0;
zephyr,shell-uart = &uart0;
zephyr,sram = &sram1;
};
leds {
compatible = "gpio-leds";
led0: led0 {
gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
label = "LED_0";
};
};
keys {
compatible = "gpio-keys";
sw0: sw0 {
gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
label = "SW_0";
zephyr,code = <INPUT_KEY_0>;
};
};
};
&uart0 {
status = "okay";
current-speed = <115200>;
clock-frequency = <150000000>;
};
&qspi0 {
status = "okay";
qspi_flash: spi-nor-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <5000000>;
size = <DT_SIZE_M(256)>;
jedec-id = [20 ba 19];
};
};
&spi1 {
status = "okay";
};
&syscontroller_qspi {
status = "okay";
sys_ctrl_flash: spi-nor-flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <5000000>;
};
};
&gpio2 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/mpfs_icicle.dts | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 469 |
```unknown
CONFIG_MPFS_HAL=n
CONFIG_BASE64=y
CONFIG_INCLUDE_RESET_VECTOR=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
CONFIG_INIT_STACKS=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_FPU=n
# GPIO driver options
CONFIG_GPIO=y
CONFIG_I2C=y
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/mpfs_icicle_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 74 |
```yaml
board:
name: mpfs_icicle
vendor: microchip
socs:
- name: polarfire
variants:
- name: 'smp'
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/board.yml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 39 |
```unknown
config BOARD_MPFS_ICICLE
select SOC_POLARFIRE
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 16 |
```yaml
identifier: mpfs_icicle
name: Microchip PolarFire ICICLE kit
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 3840
testing:
ignore_tags:
- net
- bluetooth
- flash
vendor: microchip
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/mpfs_icicle.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 67 |
```unknown
CONFIG_MPFS_HAL=n
CONFIG_BASE64=y
CONFIG_INCLUDE_RESET_VECTOR=y
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_XIP=n
CONFIG_INIT_STACKS=y
CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
CONFIG_GPIO=y
CONFIG_I2C=y
CONFIG_SMP=y
CONFIG_RV_BOOT_HART=1
CONFIG_MP_MAX_NUM_CPUS=4
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/mpfs_icicle_smp_defconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 86 |
```unknown
config BOARD_MPFS_ICICLE
select 64BIT
select SCHED_IPI_SUPPORTED
select CPU_HAS_FPU_DOUBLE_PRECISION
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/Kconfig | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 30 |
```yaml
identifier: mpfs_icicle/polarfire/smp
name: Microchip PolarFire ICICLE kit (SMP)
type: mcu
arch: riscv
toolchain:
- zephyr
ram: 3840
testing:
ignore_tags:
- net
- bluetooth
- flash
vendor: microchip
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/mpfs_icicle_smp.yaml | yaml | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 75 |
```unknown
:name: MPFS-ICICLE-KIT
:description: This script is prepared to run Zephyr on a PolarFire SoC Icicle Kit RISC-V board.
$name?="MPFS-ICICLE-KIT"
using sysbus
mach create $name
machine LoadPlatformDescription @platforms/boards/mpfs-icicle-kit.repl
showAnalyzer mmuart0
e51 PerformanceInMips 80
macro reset
"""
sysbus LoadELF $elf
"""
runMacro $reset
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/support/mpfs250t.resc | unknown | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 109 |
```restructuredtext
.. _mpfs_icicle:
Microchip mpfs_icicle
#####################
Overview
********
The Microchip mpfs_icicle board is a PolarFire SoC FPGA based development board with a Microchip MPFS250T fpga device.
The E51 RISC-V CPU can be deployed on the mpfs_icicle board.
More information can be found on the `Microchip website <path_to_url`_.
Programming and debugging
*************************
Building
========
Applications for the ``mpfs_icicle`` board configuration can be built as usual
(see :ref:`build_an_application`):
.. zephyr-app-commands::
:board: mpfs_icicle
:goals: build
To build the default SMP capable variant
.. zephyr-app-commands::
:board: mpfs_icicle/polarfire/smp
:goals: build
Flashing
========
In order to upload the application to the device, you'll need OpenOCD and GDB
with RISC-V support.
You can get them as a part of SoftConsole SDK.
Download and installation instructions can be found on
`Microchip's SoftConsole website
<path_to_url`_.
With the necessary tools installed, you can connect to the board using OpenOCD.
To establish an OpenOCD connection run:
.. code-block:: bash
sudo LD_LIBRARY_PATH=<softconsole_path>/openocd/bin \
<softconsole_path>/openocd/bin/openocd --command "set DEVICE MPFS" --file \
<softconsole_path>/openocd/share/openocd/scripts/board/microsemi-riscv.cfg
Leave it running, and in a different terminal, use GDB to upload the binary to
the board. You can use the RISC-V GDB from a toolchain delivered with
SoftConsole SDK.
Here is the GDB terminal command to connect to the device
and load the binary:
.. code-block:: console
<softconsole_path>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \
-ex "target extended-remote localhost:3333" \
-ex "set mem inaccessible-by-default off" \
-ex "set arch riscv:rv64" \
-ex "set riscv use_compressed_breakpoints no" \
-ex "load" <path_to_executable>
Debugging
=========
Refer to the detailed overview of :ref:`application_debugging`.
``` | /content/code_sandbox/boards/microchip/mpfs_icicle/doc/index.rst | restructuredtext | 2016-05-26T17:54:19 | 2024-08-16T18:09:06 | zephyr | zephyrproject-rtos/zephyr | 10,307 | 523 |
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