code string |
|---|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
/*
Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated... |
// (c) 2001-2015 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated ... |
module UBCSe_11_0_10_1 (S, X, Y);
output [12:0] S;
input [11:0] X;
input [10:1] Y;
wire [11:1] Z;
UBExtender_10_1_1000 U0 (Z[11:1], Y[10:1]);
UBPureCSe_11_1 U1 (S[12:1], X[11:1], Z[11:1]);
UB1DCON_0 U2 (S[0], X[0]);
endmodule |
module hi_us_3( // @[tage.scala:89:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [6:0] W0_addr,
input W0_clk,
input [3:0] W0_data,
input [3:0] W0_mask
);
hi_us_ext hi_us_ext ( // @[tage.scala:89:27]
.R0_addr (R0_addr),
.R0_en (R0_en... |
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated do... |
// (c) 2001-2023 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated ... |
// (c) 2001-2017 intel corporation. all rights reserved.
// your use of intel corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated docum... |
// (c) 2001-2016 altera corporation. all rights reserved.
// your use of altera corporation's design tools, logic functions and other
// software and tools, and its ampp partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated doc... |
module Router_20( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output auto_debug_ou... |
//----------------------------------------------------------------------------
// VSYNC Generator - Sub-Level Module
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGR... |
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