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crypto: chtls - add support for aes256-gcm based ciphers | added support to set 256 bit key to the hardware from setsockopt for aes256-gcm based ciphers. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for aes256-gcm based ciphers | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['chtls'] | ['h', 'c'] | 3 | 71 | 21 | --- diff --git a/drivers/crypto/chelsio/chtls/chtls.h b/drivers/crypto/chelsio/chtls/chtls.h --- a/drivers/crypto/chelsio/chtls/chtls.h +++ b/drivers/crypto/chelsio/chtls/chtls.h - struct tls12_crypto_info_aes_gcm_128 crypto_info; + union { + struct tls12_crypto_info_aes_gcm_128 aes_gcm_128; + struct tls12_crypto_info_aes_gcm_256 aes_gcm_256; + } crypto_info; -int chtls_setkey(struct chtls_sock *csk, u32 keylen, u32 mode); +int chtls_setkey(struct chtls_sock *csk, u32 keylen, u32 mode, int cipher_type); diff --git a/drivers/crypto/chelsio/chtls/chtls_hw.c b/drivers/crypto/chelsio/chtls/chtls_hw.c --- a/drivers/crypto/chelsio/chtls/chtls_hw.c +++ b/drivers/crypto/chelsio/chtls/chtls_hw.c - u32 keylen, u32 optname) + u32 keylen, u32 optname, + int cipher_type) - unsigned char key[aes_keysize_128]; - struct tls12_crypto_info_aes_gcm_128 *gcm_ctx; + unsigned char key[aes_max_key_size]; + unsigned char *key_p, *salt; - int ck_size, key_ctx_size; + int ck_size, key_ctx_size, kctx_mackey_size, salt_size; - gcm_ctx = (struct tls12_crypto_info_aes_gcm_128 *) - &csk->tlshws.crypto_info; - - if (keylen == aes_keysize_128) { - ck_size = chcr_keyctx_cipher_key_size_128; - } else { + /* gcm mode of aes supports 128 and 256 bit encryption, so + * prepare key context base on gcm cipher type + */ + switch (cipher_type) { + case tls_cipher_aes_gcm_128: { + struct tls12_crypto_info_aes_gcm_128 *gcm_ctx_128 = + (struct tls12_crypto_info_aes_gcm_128 *) + &csk->tlshws.crypto_info; + memcpy(key, gcm_ctx_128->key, keylen); + + key_p = gcm_ctx_128->key; + salt = gcm_ctx_128->salt; + ck_size = chcr_keyctx_cipher_key_size_128; + salt_size = tls_cipher_aes_gcm_128_salt_size; + kctx_mackey_size = chcr_keyctx_mac_key_size_128; + break; + } + case tls_cipher_aes_gcm_256: { + struct tls12_crypto_info_aes_gcm_256 *gcm_ctx_256 = + (struct tls12_crypto_info_aes_gcm_256 *) + &csk->tlshws.crypto_info; + memcpy(key, gcm_ctx_256->key, keylen); + + key_p = gcm_ctx_256->key; + salt = gcm_ctx_256->salt; + ck_size = chcr_keyctx_cipher_key_size_256; + salt_size = tls_cipher_aes_gcm_256_salt_size; + kctx_mackey_size = chcr_keyctx_mac_key_size_256; + break; + } + default: - memcpy(key, gcm_ctx->key, keylen); - chcr_keyctx_mac_key_size_128, + kctx_mackey_size, - chcr_keyctx_mac_key_size_128, + kctx_mackey_size, - memcpy(kctx->salt, gcm_ctx->salt, tls_cipher_aes_gcm_128_salt_size); - memcpy(kctx->key, gcm_ctx->key, keylen); + memcpy(kctx->salt, salt, salt_size); + memcpy(kctx->key, key_p, keylen); - memset(gcm_ctx->key, 0, keylen); + memset(key_p, 0, keylen); -int chtls_setkey(struct chtls_sock *csk, u32 keylen, u32 optname) +int chtls_setkey(struct chtls_sock *csk, u32 keylen, + u32 optname, int cipher_type) - ret = chtls_key_info(csk, kctx, keylen, optname); + ret = chtls_key_info(csk, kctx, keylen, optname, cipher_type); diff --git a/drivers/crypto/chelsio/chtls/chtls_main.c b/drivers/crypto/chelsio/chtls/chtls_main.c --- a/drivers/crypto/chelsio/chtls/chtls_main.c +++ b/drivers/crypto/chelsio/chtls/chtls_main.c + int cipher_type; + /* gcm mode of aes supports 128 and 256 bit encryption, so + * copy keys from user based on gcm cipher type. + */ - rc = chtls_setkey(csk, keylen, optname); + cipher_type = tls_cipher_aes_gcm_128; + break; + } + case tls_cipher_aes_gcm_256: { + crypto_info[0] = tmp_crypto_info; + rc = copy_from_user((char *)crypto_info + sizeof(*crypto_info), + optval + sizeof(*crypto_info), + sizeof(struct tls12_crypto_info_aes_gcm_256) + - sizeof(*crypto_info)); + + if (rc) { + rc = -efault; + goto out; + } + + keylen = tls_cipher_aes_gcm_256_key_size; + cipher_type = tls_cipher_aes_gcm_256; + rc = chtls_setkey(csk, keylen, optname, cipher_type); | Cryptography hardware acceleration | 596d0a289554a6946173ec898928e6390bb0943a | vinay kumar yadav | drivers | crypto | chelsio, chtls |
crypto: hisilicon - add aead support on sec2 | authenc(hmac(sha1),cbc(aes)), authenc(hmac(sha256),cbc(aes)), and authenc(hmac(sha512),cbc(aes)) support are added for sec v2. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add aead support on sec2 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['hisilicon'] | ['h', 'kconfig', 'c'] | 4 | 620 | 24 | --- diff --git a/drivers/crypto/hisilicon/kconfig b/drivers/crypto/hisilicon/kconfig --- a/drivers/crypto/hisilicon/kconfig +++ b/drivers/crypto/hisilicon/kconfig + select crypto_aead + select crypto_authenc + select crypto_hmac + select crypto_sha1 + select crypto_sha256 + select crypto_sha512 - cbc, and xts cipher mode. + cbc, and xts cipher mode, and aead algorithms. diff --git a/drivers/crypto/hisilicon/sec2/sec.h b/drivers/crypto/hisilicon/sec2/sec.h --- a/drivers/crypto/hisilicon/sec2/sec.h +++ b/drivers/crypto/hisilicon/sec2/sec.h + u8 *out_mac; + dma_addr_t out_mac_dma; +struct sec_aead_req { + u8 *out_mac; + dma_addr_t out_mac_dma; + struct aead_request *aead_req; +}; + - /* cipher supported only at present */ + struct sec_aead_req aead_req; + +/* sec auth context */ +struct sec_auth_ctx { + dma_addr_t a_key_dma; + u8 *a_key; + u8 a_key_len; + u8 mac_len; + u8 a_alg; + struct crypto_shash *hash_tfm; +}; + +enum sec_alg_type { + sec_skcipher, + sec_aead +}; + + + enum sec_alg_type alg_type; + struct sec_auth_ctx a_ctx; diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.c b/drivers/crypto/hisilicon/sec2/sec_crypto.c --- a/drivers/crypto/hisilicon/sec2/sec_crypto.c +++ b/drivers/crypto/hisilicon/sec2/sec_crypto.c +#include <crypto/authenc.h> +#include <crypto/hash.h> +#include <crypto/internal/aead.h> +#include <crypto/sha.h> +#define sec_akey_offset 5 +#define sec_aead_alg_offset 11 +#define sec_auth_offset 6 + +#define sec_cipher_auth 0xfe +#define sec_auth_cipher 0x1 +#define sec_max_mac_len 64 +#define sec_total_mac_sz (sec_max_mac_len * qm_q_depth) +#define sec_sqe_len_rate 4 +#define sec_sqe_aead_flag 3 -static define_mutex(sec_algs_lock); -static unsigned int sec_active_devs; +static atomic_t sec_active_devs; +static int sec_aead_verify(struct sec_req *req, struct sec_qp_ctx *qp_ctx) +{ + struct aead_request *aead_req = req->aead_req.aead_req; + struct crypto_aead *tfm = crypto_aead_reqtfm(aead_req); + u8 *mac_out = qp_ctx->res[req->req_id].out_mac; + size_t authsize = crypto_aead_authsize(tfm); + u8 *mac = mac_out + sec_max_mac_len; + struct scatterlist *sgl = aead_req->src; + size_t sz; + + sz = sg_pcopy_to_buffer(sgl, sg_nents(sgl), mac, authsize, + aead_req->cryptlen + aead_req->assoclen - + authsize); + if (unlikely(sz != authsize || memcmp(mac_out, mac, sz))) { + dev_err(sec_ctx_dev(req->ctx), "aead verify failure! "); + return -ebadmsg; + } + + return 0; +} + - if (req->err_type || done != sec_sqe_done || - flag != sec_sqe_cflag) { + if (unlikely(req->err_type || done != sec_sqe_done || + (ctx->alg_type == sec_skcipher && flag != sec_sqe_cflag) || + (ctx->alg_type == sec_aead && flag != sec_sqe_aead_flag))) { + if (ctx->alg_type == sec_aead && !req->c_req.encrypt) + err = sec_aead_verify(req, qp_ctx); + +static int sec_alloc_mac_resource(struct device *dev, struct sec_alg_res *res) +{ + int i; + + res->out_mac = dma_alloc_coherent(dev, sec_total_mac_sz << 1, + &res->out_mac_dma, gfp_kernel); + if (!res->out_mac) + return -enomem; + + for (i = 1; i < qm_q_depth; i++) { + res[i].out_mac_dma = res->out_mac_dma + + i * (sec_max_mac_len << 1); + res[i].out_mac = res->out_mac + i * (sec_max_mac_len << 1); + } + + return 0; +} + +static void sec_free_mac_resource(struct device *dev, struct sec_alg_res *res) +{ + if (res->out_mac) + dma_free_coherent(dev, sec_total_mac_sz << 1, + res->out_mac, res->out_mac_dma); +} + + struct sec_alg_res *res = qp_ctx->res; + int ret; + + ret = sec_alloc_civ_resource(dev, res); + if (ret) + return ret; - return sec_alloc_civ_resource(dev, qp_ctx->res); + if (ctx->alg_type == sec_aead) { + ret = sec_alloc_mac_resource(dev, res); + if (ret) + goto get_fail; + } + + return 0; +get_fail: + sec_free_civ_resource(dev, res); + + return ret; + + if (ctx->alg_type == sec_aead) + sec_free_mac_resource(dev, qp_ctx->res); +static int sec_auth_init(struct sec_ctx *ctx) +{ + struct sec_auth_ctx *a_ctx = &ctx->a_ctx; + + a_ctx->a_key = dma_alloc_coherent(sec_ctx_dev(ctx), sec_max_key_size, + &a_ctx->a_key_dma, gfp_kernel); + if (!a_ctx->a_key) + return -enomem; + + return 0; +} + +static void sec_auth_uninit(struct sec_ctx *ctx) +{ + struct sec_auth_ctx *a_ctx = &ctx->a_ctx; + + memzero_explicit(a_ctx->a_key, sec_max_key_size); + dma_free_coherent(sec_ctx_dev(ctx), sec_max_key_size, + a_ctx->a_key, a_ctx->a_key_dma); +} + + ctx->alg_type = sec_skcipher; +static int sec_aead_aes_set_key(struct sec_cipher_ctx *c_ctx, + struct crypto_authenc_keys *keys) +{ + switch (keys->enckeylen) { + case aes_keysize_128: + c_ctx->c_key_len = sec_ckey_128bit; + break; + case aes_keysize_192: + c_ctx->c_key_len = sec_ckey_192bit; + break; + case aes_keysize_256: + c_ctx->c_key_len = sec_ckey_256bit; + break; + default: + pr_err("hisi_sec2: aead aes key error! "); + return -einval; + } + memcpy(c_ctx->c_key, keys->enckey, keys->enckeylen); + + return 0; +} + +static int sec_aead_auth_set_key(struct sec_auth_ctx *ctx, + struct crypto_authenc_keys *keys) +{ + struct crypto_shash *hash_tfm = ctx->hash_tfm; + shash_desc_on_stack(shash, hash_tfm); + int blocksize, ret; + + if (!keys->authkeylen) { + pr_err("hisi_sec2: aead auth key error! "); + return -einval; + } + + blocksize = crypto_shash_blocksize(hash_tfm); + if (keys->authkeylen > blocksize) { + ret = crypto_shash_digest(shash, keys->authkey, + keys->authkeylen, ctx->a_key); + if (ret) { + pr_err("hisi_sec2: aead auth disgest error! "); + return -einval; + } + ctx->a_key_len = blocksize; + } else { + memcpy(ctx->a_key, keys->authkey, keys->authkeylen); + ctx->a_key_len = keys->authkeylen; + } + + return 0; +} + +static int sec_aead_setkey(struct crypto_aead *tfm, const u8 *key, + const u32 keylen, const enum sec_hash_alg a_alg, + const enum sec_calg c_alg, + const enum sec_mac_len mac_len, + const enum sec_cmode c_mode) +{ + struct sec_ctx *ctx = crypto_aead_ctx(tfm); + struct sec_cipher_ctx *c_ctx = &ctx->c_ctx; + struct crypto_authenc_keys keys; + int ret; + + ctx->a_ctx.a_alg = a_alg; + ctx->c_ctx.c_alg = c_alg; + ctx->a_ctx.mac_len = mac_len; + c_ctx->c_mode = c_mode; + + if (crypto_authenc_extractkeys(&keys, key, keylen)) + goto bad_key; + + ret = sec_aead_aes_set_key(c_ctx, &keys); + if (ret) { + dev_err(sec_ctx_dev(ctx), "set sec cipher key err! "); + goto bad_key; + } + + ret = sec_aead_auth_set_key(&ctx->a_ctx, &keys); + if (ret) { + dev_err(sec_ctx_dev(ctx), "set sec auth key err! "); + goto bad_key; + } + + return 0; +bad_key: + memzero_explicit(&keys, sizeof(struct crypto_authenc_keys)); + + return -einval; +} + + +#define gen_sec_aead_setkey_func(name, aalg, calg, maclen, cmode) \ +static int sec_setkey_##name(struct crypto_aead *tfm, const u8 *key, \ + u32 keylen) \ +{ \ + return sec_aead_setkey(tfm, key, keylen, aalg, calg, maclen, cmode);\ +} + +gen_sec_aead_setkey_func(aes_cbc_sha1, sec_a_hmac_sha1, + sec_calg_aes, sec_hmac_sha1_mac, sec_cmode_cbc) +gen_sec_aead_setkey_func(aes_cbc_sha256, sec_a_hmac_sha256, + sec_calg_aes, sec_hmac_sha256_mac, sec_cmode_cbc) +gen_sec_aead_setkey_func(aes_cbc_sha512, sec_a_hmac_sha512, + sec_calg_aes, sec_hmac_sha512_mac, sec_cmode_cbc) + +static int sec_aead_sgl_map(struct sec_ctx *ctx, struct sec_req *req) +{ + struct aead_request *aq = req->aead_req.aead_req; + + return sec_cipher_map(sec_ctx_dev(ctx), req, aq->src, aq->dst); +} + +static void sec_aead_sgl_unmap(struct sec_ctx *ctx, struct sec_req *req) +{ + struct device *dev = sec_ctx_dev(ctx); + struct sec_cipher_req *cq = &req->c_req; + struct aead_request *aq = req->aead_req.aead_req; + + sec_cipher_unmap(dev, cq, aq->src, aq->dst); +} + -static void sec_update_iv(struct sec_req *req) +static void sec_update_iv(struct sec_req *req, enum sec_alg_type alg_type) + struct aead_request *aead_req = req->aead_req.aead_req; + unsigned int cryptlen; + u8 *iv; - sgl = sk_req->dst; + sgl = alg_type == sec_skcipher ? sk_req->dst : aead_req->dst; - sgl = sk_req->src; + sgl = alg_type == sec_skcipher ? sk_req->src : aead_req->src; + + if (alg_type == sec_skcipher) { + iv = sk_req->iv; + cryptlen = sk_req->cryptlen; + } else { + iv = aead_req->iv; + cryptlen = aead_req->cryptlen; + } - sz = sg_pcopy_to_buffer(sgl, sg_nents(sgl), sk_req->iv, - iv_size, sk_req->cryptlen - iv_size); + sz = sg_pcopy_to_buffer(sgl, sg_nents(sgl), iv, iv_size, + cryptlen - iv_size); - sec_update_iv(req); + sec_update_iv(req, sec_skcipher); +static void sec_aead_copy_iv(struct sec_ctx *ctx, struct sec_req *req) +{ + struct aead_request *aead_req = req->aead_req.aead_req; + u8 *c_ivin = req->qp_ctx->res[req->req_id].c_ivin; + + memcpy(c_ivin, aead_req->iv, ctx->c_ctx.ivsize); +} + +static void sec_auth_bd_fill_ex(struct sec_auth_ctx *ctx, int dir, + struct sec_req *req, struct sec_sqe *sec_sqe) +{ + struct sec_aead_req *a_req = &req->aead_req; + struct sec_cipher_req *c_req = &req->c_req; + struct aead_request *aq = a_req->aead_req; + + sec_sqe->type2.a_key_addr = cpu_to_le64(ctx->a_key_dma); + + sec_sqe->type2.mac_key_alg = + cpu_to_le32(ctx->mac_len / sec_sqe_len_rate); + + sec_sqe->type2.mac_key_alg |= + cpu_to_le32((u32)((ctx->a_key_len) / + sec_sqe_len_rate) << sec_akey_offset); + + sec_sqe->type2.mac_key_alg |= + cpu_to_le32((u32)(ctx->a_alg) << sec_aead_alg_offset); + + sec_sqe->type_cipher_auth |= sec_auth_type1 << sec_auth_offset; + + if (dir) + sec_sqe->sds_sa_type &= sec_cipher_auth; + else + sec_sqe->sds_sa_type |= sec_auth_cipher; + + sec_sqe->type2.alen_ivllen = cpu_to_le32(c_req->c_len + aq->assoclen); + + sec_sqe->type2.cipher_src_offset = cpu_to_le16((u16)aq->assoclen); + + sec_sqe->type2.mac_addr = + cpu_to_le64(req->qp_ctx->res[req->req_id].out_mac_dma); +} + +static int sec_aead_bd_fill(struct sec_ctx *ctx, struct sec_req *req) +{ + struct sec_auth_ctx *auth_ctx = &ctx->a_ctx; + struct sec_sqe *sec_sqe = &req->sec_sqe; + int ret; + + ret = sec_skcipher_bd_fill(ctx, req); + if (unlikely(ret)) { + dev_err(sec_ctx_dev(ctx), "skcipher bd fill is error! "); + return ret; + } + + sec_auth_bd_fill_ex(auth_ctx, req->c_req.encrypt, req, sec_sqe); + + return 0; +} + +static void sec_aead_callback(struct sec_ctx *c, struct sec_req *req, int err) +{ + struct aead_request *a_req = req->aead_req.aead_req; + struct crypto_aead *tfm = crypto_aead_reqtfm(a_req); + struct sec_cipher_req *c_req = &req->c_req; + size_t authsize = crypto_aead_authsize(tfm); + struct sec_qp_ctx *qp_ctx = req->qp_ctx; + size_t sz; + + atomic_dec(&qp_ctx->pending_reqs); + + if (!err && c->c_ctx.c_mode == sec_cmode_cbc && c_req->encrypt) + sec_update_iv(req, sec_aead); + + /* copy output mac */ + if (!err && c_req->encrypt) { + struct scatterlist *sgl = a_req->dst; + + sz = sg_pcopy_from_buffer(sgl, sg_nents(sgl), + qp_ctx->res[req->req_id].out_mac, + authsize, a_req->cryptlen + + a_req->assoclen); + + if (unlikely(sz != authsize)) { + dev_err(sec_ctx_dev(req->ctx), "copy out mac err! "); + err = -einval; + } + } + + sec_free_req_id(req); + + if (req->fake_busy) + a_req->base.complete(&a_req->base, -einprogress); + + a_req->base.complete(&a_req->base, err); +} + - sec_update_iv(req); + sec_update_iv(req, ctx->alg_type); - if (ctx->c_ctx.c_mode == sec_cmode_cbc && !req->c_req.encrypt) - memcpy(req->c_req.sk_req->iv, - req->qp_ctx->res[req->req_id].c_ivin, - ctx->c_ctx.ivsize); + if (ctx->c_ctx.c_mode == sec_cmode_cbc && !req->c_req.encrypt) { + if (ctx->alg_type == sec_skcipher) + memcpy(req->c_req.sk_req->iv, + req->qp_ctx->res[req->req_id].c_ivin, + ctx->c_ctx.ivsize); + else + memcpy(req->aead_req.aead_req->iv, + req->qp_ctx->res[req->req_id].c_ivin, + ctx->c_ctx.ivsize); + } +static const struct sec_req_op sec_aead_req_ops = { + .buf_map = sec_aead_sgl_map, + .buf_unmap = sec_aead_sgl_unmap, + .do_transfer = sec_aead_copy_iv, + .bd_fill = sec_aead_bd_fill, + .bd_send = sec_bd_send, + .callback = sec_aead_callback, + .process = sec_process, +}; + +static int sec_aead_init(struct crypto_aead *tfm) +{ + struct sec_ctx *ctx = crypto_aead_ctx(tfm); + int ret; + + crypto_aead_set_reqsize(tfm, sizeof(struct sec_req)); + ctx->alg_type = sec_aead; + ctx->c_ctx.ivsize = crypto_aead_ivsize(tfm); + if (ctx->c_ctx.ivsize > sec_iv_size) { + dev_err(sec_ctx_dev(ctx), "get error aead iv size! "); + return -einval; + } + + ctx->req_op = &sec_aead_req_ops; + ret = sec_ctx_base_init(ctx); + if (ret) + return ret; + + ret = sec_auth_init(ctx); + if (ret) + goto err_auth_init; + + ret = sec_cipher_init(ctx); + if (ret) + goto err_cipher_init; + + return ret; + +err_cipher_init: + sec_auth_uninit(ctx); +err_auth_init: + sec_ctx_base_uninit(ctx); + + return ret; +} + +static void sec_aead_exit(struct crypto_aead *tfm) +{ + struct sec_ctx *ctx = crypto_aead_ctx(tfm); + + sec_cipher_uninit(ctx); + sec_auth_uninit(ctx); + sec_ctx_base_uninit(ctx); +} + +static int sec_aead_ctx_init(struct crypto_aead *tfm, const char *hash_name) +{ + struct sec_ctx *ctx = crypto_aead_ctx(tfm); + struct sec_auth_ctx *auth_ctx = &ctx->a_ctx; + int ret; + + ret = sec_aead_init(tfm); + if (ret) { + pr_err("hisi_sec2: aead init error! "); + return ret; + } + + auth_ctx->hash_tfm = crypto_alloc_shash(hash_name, 0, 0); + if (is_err(auth_ctx->hash_tfm)) { + dev_err(sec_ctx_dev(ctx), "aead alloc shash error! "); + sec_aead_exit(tfm); + return ptr_err(auth_ctx->hash_tfm); + } + + return 0; +} + +static void sec_aead_ctx_exit(struct crypto_aead *tfm) +{ + struct sec_ctx *ctx = crypto_aead_ctx(tfm); + + crypto_free_shash(ctx->a_ctx.hash_tfm); + sec_aead_exit(tfm); +} + +static int sec_aead_sha1_ctx_init(struct crypto_aead *tfm) +{ + return sec_aead_ctx_init(tfm, "sha1"); +} + +static int sec_aead_sha256_ctx_init(struct crypto_aead *tfm) +{ + return sec_aead_ctx_init(tfm, "sha256"); +} + +static int sec_aead_sha512_ctx_init(struct crypto_aead *tfm) +{ + return sec_aead_ctx_init(tfm, "sha512"); +} + +static int sec_aead_param_check(struct sec_ctx *ctx, struct sec_req *sreq) +{ + u8 c_alg = ctx->c_ctx.c_alg; + struct aead_request *req = sreq->aead_req.aead_req; + struct crypto_aead *tfm = crypto_aead_reqtfm(req); + size_t authsize = crypto_aead_authsize(tfm); + + if (unlikely(!req->src || !req->dst || !req->cryptlen)) { + dev_err(sec_ctx_dev(ctx), "aead input param error! "); + return -einval; + } + + /* support aes only */ + if (unlikely(c_alg != sec_calg_aes)) { + dev_err(sec_ctx_dev(ctx), "aead crypto alg error! "); + return -einval; + + } + if (sreq->c_req.encrypt) + sreq->c_req.c_len = req->cryptlen; + else + sreq->c_req.c_len = req->cryptlen - authsize; + + if (unlikely(sreq->c_req.c_len & (aes_block_size - 1))) { + dev_err(sec_ctx_dev(ctx), "aead crypto length error! "); + return -einval; + } + + return 0; +} + +static int sec_aead_crypto(struct aead_request *a_req, bool encrypt) +{ + struct crypto_aead *tfm = crypto_aead_reqtfm(a_req); + struct sec_req *req = aead_request_ctx(a_req); + struct sec_ctx *ctx = crypto_aead_ctx(tfm); + int ret; + + req->aead_req.aead_req = a_req; + req->c_req.encrypt = encrypt; + req->ctx = ctx; + + ret = sec_aead_param_check(ctx, req); + if (unlikely(ret)) + return -einval; + + return ctx->req_op->process(ctx, req); +} + +static int sec_aead_encrypt(struct aead_request *a_req) +{ + return sec_aead_crypto(a_req, true); +} + +static int sec_aead_decrypt(struct aead_request *a_req) +{ + return sec_aead_crypto(a_req, false); +} + +#define sec_aead_gen_alg(sec_cra_name, sec_set_key, ctx_init,\ + ctx_exit, blk_size, iv_size, max_authsize)\ +{\ + .base = {\ + .cra_name = sec_cra_name,\ + .cra_driver_name = "hisi_sec_"sec_cra_name,\ + .cra_priority = sec_priority,\ + .cra_flags = crypto_alg_async,\ + .cra_blocksize = blk_size,\ + .cra_ctxsize = sizeof(struct sec_ctx),\ + .cra_module = this_module,\ + },\ + .init = ctx_init,\ + .exit = ctx_exit,\ + .setkey = sec_set_key,\ + .decrypt = sec_aead_decrypt,\ + .encrypt = sec_aead_encrypt,\ + .ivsize = iv_size,\ + .maxauthsize = max_authsize,\ +} + +#define sec_aead_alg(algname, keyfunc, aead_init, blksize, ivsize, authsize)\ + sec_aead_gen_alg(algname, keyfunc, aead_init,\ + sec_aead_ctx_exit, blksize, ivsize, authsize) + +static struct aead_alg sec_aeads[] = { + sec_aead_alg("authenc(hmac(sha1),cbc(aes))", + sec_setkey_aes_cbc_sha1, sec_aead_sha1_ctx_init, + aes_block_size, aes_block_size, sha1_digest_size), + + sec_aead_alg("authenc(hmac(sha256),cbc(aes))", + sec_setkey_aes_cbc_sha256, sec_aead_sha256_ctx_init, + aes_block_size, aes_block_size, sha256_digest_size), + + sec_aead_alg("authenc(hmac(sha512),cbc(aes))", + sec_setkey_aes_cbc_sha512, sec_aead_sha512_ctx_init, + aes_block_size, aes_block_size, sha512_digest_size), +}; + - mutex_lock(&sec_algs_lock); - if (++sec_active_devs == 1) + if (atomic_add_return(1, &sec_active_devs) == 1) { - mutex_unlock(&sec_algs_lock); + if (ret) + return ret; + + ret = crypto_register_aeads(sec_aeads, array_size(sec_aeads)); + if (ret) + goto reg_aead_fail; + } + + return ret; + +reg_aead_fail: + crypto_unregister_skciphers(sec_skciphers, array_size(sec_skciphers)); - mutex_lock(&sec_algs_lock); - if (--sec_active_devs == 0) + if (atomic_sub_return(1, &sec_active_devs) == 0) { - mutex_unlock(&sec_algs_lock); + crypto_unregister_aeads(sec_aeads, array_size(sec_aeads)); + } diff --git a/drivers/crypto/hisilicon/sec2/sec_crypto.h b/drivers/crypto/hisilicon/sec2/sec_crypto.h --- a/drivers/crypto/hisilicon/sec2/sec_crypto.h +++ b/drivers/crypto/hisilicon/sec2/sec_crypto.h +enum sec_hash_alg { + sec_a_hmac_sha1 = 0x10, + sec_a_hmac_sha256 = 0x11, + sec_a_hmac_sha512 = 0x15, +}; + +enum sec_mac_len { + sec_hmac_sha1_mac = 20, + sec_hmac_sha256_mac = 32, + sec_hmac_sha512_mac = 64, +}; + +enum sec_auth { + sec_no_auth = 0x0, + sec_auth_type1 = 0x1, + sec_auth_type2 = 0x2, +}; + | Cryptography hardware acceleration | 2f072d75d1ab32e9c7c43a54398f4360a0a42d5e | zaibo xu | drivers | crypto | hisilicon, sec2 |
crypto: sun4i-ss - add the a33 variant of ss | the a33 ss has a difference with all other ss, it give sha1 digest directly in be. so this patch adds variant support in sun4i-ss. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add the a33 variant of ss | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['sun4i-ss'] | ['c', 'h'] | 3 | 34 | 2 | --- diff --git a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c --- a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c +++ b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-core.c +#include <linux/of_device.h> +static const struct ss_variant ss_a10_variant = { + .sha1_in_be = false, +}; + +static const struct ss_variant ss_a33_variant = { + .sha1_in_be = true, +}; + + ss->variant = of_device_get_match_data(&pdev->dev); + if (!ss->variant) { + dev_err(&pdev->dev, "missing security system variant "); + return -einval; + } + - { .compatible = "allwinner,sun4i-a10-crypto" }, + { .compatible = "allwinner,sun4i-a10-crypto", + .data = &ss_a10_variant + }, + { .compatible = "allwinner,sun8i-a33-crypto", + .data = &ss_a33_variant + }, diff --git a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c --- a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c +++ b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss-hash.c - v = cpu_to_be32(readl(ss->base + ss_md0 + i * 4)); + if (ss->variant->sha1_in_be) + v = cpu_to_le32(readl(ss->base + ss_md0 + i * 4)); + else + v = cpu_to_be32(readl(ss->base + ss_md0 + i * 4)); diff --git a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h --- a/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h +++ b/drivers/crypto/allwinner/sun4i-ss/sun4i-ss.h +/* + * struct ss_variant - describe ss hardware variant + * @sha1_in_be: the sha1 digest is given by ss in be, and so need to be inverted. + */ +struct ss_variant { + bool sha1_in_be; +}; + + const struct ss_variant *variant; | Cryptography hardware acceleration | 1e02e6fbdadb3a0cb56294ff37eeeb8109e1f493 | corentin labbe maxime ripard mripard kernel org | drivers | crypto | allwinner, sun4i-ss |
pci/p2pdma: add intel skylake-e to the whitelist | intel skylake-e was successfully tested for p2pdma transactions spanning over a host bridge and pci bridge with iommu on. add it to the whitelist. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add intel skylake-e to the whitelist | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['p2pdma'] | ['c'] | 1 | 3 | 0 | --- diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c + /* intel skylake-e */ + {pci_vendor_id_intel, 0x2030, 0}, + {pci_vendor_id_intel, 0x2020, 0}, | PCI | bc123a515cb76c432293a6c4b4765b5ec0c813cf | armen baloyan logan gunthorpe logang deltatee com | drivers | pci | |
pci: brcmstb: add broadcom stb pcie host controller driver | this adds a basic driver for broadcom's stb pcie controller, for now aimed at raspberry pi 4's soc, bcm2711. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add broadcom stb pcie host controller driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['brcmstb'] | ['c', 'kconfig', 'makefile'] | 3 | 764 | 0 | --- diff --git a/drivers/pci/controller/kconfig b/drivers/pci/controller/kconfig --- a/drivers/pci/controller/kconfig +++ b/drivers/pci/controller/kconfig +config pcie_brcmstb + tristate "broadcom brcmstb pcie host controller" + depends on arch_bcm2835 || compile_test + depends on of + help + say y here to enable pcie host controller support for + broadcom stb based socs, like the raspberry pi 4. + diff --git a/drivers/pci/controller/makefile b/drivers/pci/controller/makefile --- a/drivers/pci/controller/makefile +++ b/drivers/pci/controller/makefile +obj-$(config_pcie_brcmstb) += pcie-brcmstb.o diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c --- /dev/null +++ b/drivers/pci/controller/pcie-brcmstb.c +// spdx-license-identifier: gpl-2.0+ +/* copyright (c) 2009 - 2019 broadcom */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/compiler.h> +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/irqdomain.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/log2.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/pci.h> +#include <linux/printk.h> +#include <linux/sizes.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/types.h> + +#include "../pci.h" + +/* brcm_pcie_cap_regs - offset for the mandatory capability config regs */ +#define brcm_pcie_cap_regs 0x00ac + +/* broadcom stb pcie register offsets */ +#define pcie_rc_cfg_vendor_vendor_specific_reg1 0x0188 +#define pcie_rc_cfg_vendor_vendor_specific_reg1_endian_mode_bar2_mask 0xc +#define pcie_rc_cfg_vendor_spcific_reg1_little_endian 0x0 + +#define pcie_rc_cfg_priv1_id_val3 0x043c +#define pcie_rc_cfg_priv1_id_val3_class_code_mask 0xffffff + +#define pcie_rc_dl_mdio_addr 0x1100 +#define pcie_rc_dl_mdio_wr_data 0x1104 +#define pcie_rc_dl_mdio_rd_data 0x1108 + +#define pcie_misc_misc_ctrl 0x4008 +#define pcie_misc_misc_ctrl_scb_access_en_mask 0x1000 +#define pcie_misc_misc_ctrl_cfg_read_ur_mode_mask 0x2000 +#define pcie_misc_misc_ctrl_max_burst_size_mask 0x300000 +#define pcie_misc_misc_ctrl_max_burst_size_128 0x0 +#define pcie_misc_misc_ctrl_scb0_size_mask 0xf8000000 + +#define pcie_misc_cpu_2_pcie_mem_win0_lo 0x400c +#define pcie_mem_win0_lo(win) \ + pcie_misc_cpu_2_pcie_mem_win0_lo + ((win) * 4) + +#define pcie_misc_cpu_2_pcie_mem_win0_hi 0x4010 +#define pcie_mem_win0_hi(win) \ + pcie_misc_cpu_2_pcie_mem_win0_hi + ((win) * 4) + +#define pcie_misc_rc_bar1_config_lo 0x402c +#define pcie_misc_rc_bar1_config_lo_size_mask 0x1f + +#define pcie_misc_rc_bar2_config_lo 0x4034 +#define pcie_misc_rc_bar2_config_lo_size_mask 0x1f +#define pcie_misc_rc_bar2_config_hi 0x4038 + +#define pcie_misc_rc_bar3_config_lo 0x403c +#define pcie_misc_rc_bar3_config_lo_size_mask 0x1f + +#define pcie_misc_pcie_ctrl 0x4064 +#define pcie_misc_pcie_ctrl_pcie_l23_request_mask 0x1 + +#define pcie_misc_pcie_status 0x4068 +#define pcie_misc_pcie_status_pcie_port_mask 0x80 +#define pcie_misc_pcie_status_pcie_dl_active_mask 0x20 +#define pcie_misc_pcie_status_pcie_phylinkup_mask 0x10 +#define pcie_misc_pcie_status_pcie_link_in_l23_mask 0x40 + +#define pcie_misc_cpu_2_pcie_mem_win0_base_limit 0x4070 +#define pcie_misc_cpu_2_pcie_mem_win0_base_limit_limit_mask 0xfff00000 +#define pcie_misc_cpu_2_pcie_mem_win0_base_limit_base_mask 0xfff0 +#define pcie_mem_win0_base_limit(win) \ + pcie_misc_cpu_2_pcie_mem_win0_base_limit + ((win) * 4) + +#define pcie_misc_cpu_2_pcie_mem_win0_base_hi 0x4080 +#define pcie_misc_cpu_2_pcie_mem_win0_base_hi_base_mask 0xff +#define pcie_mem_win0_base_hi(win) \ + pcie_misc_cpu_2_pcie_mem_win0_base_hi + ((win) * 8) + +#define pcie_misc_cpu_2_pcie_mem_win0_limit_hi 0x4084 +#define pcie_misc_cpu_2_pcie_mem_win0_limit_hi_limit_mask 0xff +#define pcie_mem_win0_limit_hi(win) \ + pcie_misc_cpu_2_pcie_mem_win0_limit_hi + ((win) * 8) + +#define pcie_misc_hard_pcie_hard_debug 0x4204 +#define pcie_misc_hard_pcie_hard_debug_clkreq_debug_enable_mask 0x2 +#define pcie_misc_hard_pcie_hard_debug_serdes_iddq_mask 0x08000000 + +#define pcie_msi_intr2_status 0x4500 +#define pcie_msi_intr2_clr 0x4508 +#define pcie_msi_intr2_mask_set 0x4510 +#define pcie_msi_intr2_mask_clr 0x4514 + +#define pcie_ext_cfg_data 0x8000 + +#define pcie_ext_cfg_index 0x9000 +#define pcie_ext_busnum_shift 20 +#define pcie_ext_slot_shift 15 +#define pcie_ext_func_shift 12 + +#define pcie_rgr1_sw_init_1 0x9210 +#define pcie_rgr1_sw_init_1_perst_mask 0x1 +#define pcie_rgr1_sw_init_1_init_mask 0x2 + +/* pcie parameters */ +#define brcm_num_pcie_out_wins 0x4 + +/* mdio registers */ +#define mdio_port0 0x0 +#define mdio_data_mask 0x7fffffff +#define mdio_port_mask 0xf0000 +#define mdio_regad_mask 0xffff +#define mdio_cmd_mask 0xfff00000 +#define mdio_cmd_read 0x1 +#define mdio_cmd_write 0x0 +#define mdio_data_done_mask 0x80000000 +#define mdio_rd_done(x) (((x) & mdio_data_done_mask) ? 1 : 0) +#define mdio_wt_done(x) (((x) & mdio_data_done_mask) ? 0 : 1) +#define ssc_regs_addr 0x1100 +#define set_addr_offset 0x1f +#define ssc_cntl_offset 0x2 +#define ssc_cntl_ovrd_en_mask 0x8000 +#define ssc_cntl_ovrd_val_mask 0x4000 +#define ssc_status_offset 0x1 +#define ssc_status_ssc_mask 0x400 +#define ssc_status_pll_lock_mask 0x800 + +/* internal pcie host controller information.*/ +struct brcm_pcie { + struct device *dev; + void __iomem *base; + struct clk *clk; + struct pci_bus *root_bus; + struct device_node *np; + bool ssc; + int gen; +}; + +/* + * this is to convert the size of the inbound "bar" region to the + * non-linear values of pcie_x_misc_rc_bar[123]_config_lo.size + */ +static int brcm_pcie_encode_ibar_size(u64 size) +{ + int log2_in = ilog2(size); + + if (log2_in >= 12 && log2_in <= 15) + /* covers 4kb to 32kb (inclusive) */ + return (log2_in - 12) + 0x1c; + else if (log2_in >= 16 && log2_in <= 35) + /* covers 64kb to 32gb, (inclusive) */ + return log2_in - 15; + /* something is awry so disable */ + return 0; +} + +static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd) +{ + u32 pkt = 0; + + pkt |= field_prep(mdio_port_mask, port); + pkt |= field_prep(mdio_regad_mask, regad); + pkt |= field_prep(mdio_cmd_mask, cmd); + + return pkt; +} + +/* negative return value indicates error */ +static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val) +{ + int tries; + u32 data; + + writel(brcm_pcie_mdio_form_pkt(port, regad, mdio_cmd_read), + base + pcie_rc_dl_mdio_addr); + readl(base + pcie_rc_dl_mdio_addr); + + data = readl(base + pcie_rc_dl_mdio_rd_data); + for (tries = 0; !mdio_rd_done(data) && tries < 10; tries++) { + udelay(10); + data = readl(base + pcie_rc_dl_mdio_rd_data); + } + + *val = field_get(mdio_data_mask, data); + return mdio_rd_done(data) ? 0 : -eio; +} + +/* negative return value indicates error */ +static int brcm_pcie_mdio_write(void __iomem *base, u8 port, + u8 regad, u16 wrdata) +{ + int tries; + u32 data; + + writel(brcm_pcie_mdio_form_pkt(port, regad, mdio_cmd_write), + base + pcie_rc_dl_mdio_addr); + readl(base + pcie_rc_dl_mdio_addr); + writel(mdio_data_done_mask | wrdata, base + pcie_rc_dl_mdio_wr_data); + + data = readl(base + pcie_rc_dl_mdio_wr_data); + for (tries = 0; !mdio_wt_done(data) && tries < 10; tries++) { + udelay(10); + data = readl(base + pcie_rc_dl_mdio_wr_data); + } + + return mdio_wt_done(data) ? 0 : -eio; +} + +/* + * configures device for spread spectrum clocking (ssc) mode; a negative + * return value indicates error. + */ +static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) +{ + int pll, ssc; + int ret; + u32 tmp; + + ret = brcm_pcie_mdio_write(pcie->base, mdio_port0, set_addr_offset, + ssc_regs_addr); + if (ret < 0) + return ret; + + ret = brcm_pcie_mdio_read(pcie->base, mdio_port0, + ssc_cntl_offset, &tmp); + if (ret < 0) + return ret; + + u32p_replace_bits(&tmp, 1, ssc_cntl_ovrd_en_mask); + u32p_replace_bits(&tmp, 1, ssc_cntl_ovrd_val_mask); + ret = brcm_pcie_mdio_write(pcie->base, mdio_port0, + ssc_cntl_offset, tmp); + if (ret < 0) + return ret; + + usleep_range(1000, 2000); + ret = brcm_pcie_mdio_read(pcie->base, mdio_port0, + ssc_status_offset, &tmp); + if (ret < 0) + return ret; + + ssc = field_get(ssc_status_ssc_mask, tmp); + pll = field_get(ssc_status_pll_lock_mask, tmp); + + return ssc && pll ? 0 : -eio; +} + +/* limits operation to a specific generation (1, 2, or 3) */ +static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) +{ + u16 lnkctl2 = readw(pcie->base + brcm_pcie_cap_regs + pci_exp_lnkctl2); + u32 lnkcap = readl(pcie->base + brcm_pcie_cap_regs + pci_exp_lnkcap); + + lnkcap = (lnkcap & ~pci_exp_lnkcap_sls) | gen; + writel(lnkcap, pcie->base + brcm_pcie_cap_regs + pci_exp_lnkcap); + + lnkctl2 = (lnkctl2 & ~0xf) | gen; + writew(lnkctl2, pcie->base + brcm_pcie_cap_regs + pci_exp_lnkctl2); +} + +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, + unsigned int win, u64 cpu_addr, + u64 pcie_addr, u64 size) +{ + u32 cpu_addr_mb_high, limit_addr_mb_high; + phys_addr_t cpu_addr_mb, limit_addr_mb; + int high_addr_shift; + u32 tmp; + + /* set the base of the pcie_addr window */ + writel(lower_32_bits(pcie_addr), pcie->base + pcie_mem_win0_lo(win)); + writel(upper_32_bits(pcie_addr), pcie->base + pcie_mem_win0_hi(win)); + + /* write the addr base & limit lower bits (in mbs) */ + cpu_addr_mb = cpu_addr / sz_1m; + limit_addr_mb = (cpu_addr + size - 1) / sz_1m; + + tmp = readl(pcie->base + pcie_mem_win0_base_limit(win)); + u32p_replace_bits(&tmp, cpu_addr_mb, + pcie_misc_cpu_2_pcie_mem_win0_base_limit_base_mask); + u32p_replace_bits(&tmp, limit_addr_mb, + pcie_misc_cpu_2_pcie_mem_win0_base_limit_limit_mask); + writel(tmp, pcie->base + pcie_mem_win0_base_limit(win)); + + /* write the cpu & limit addr upper bits */ + high_addr_shift = + hweight32(pcie_misc_cpu_2_pcie_mem_win0_base_limit_base_mask); + + cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift; + tmp = readl(pcie->base + pcie_mem_win0_base_hi(win)); + u32p_replace_bits(&tmp, cpu_addr_mb_high, + pcie_misc_cpu_2_pcie_mem_win0_base_hi_base_mask); + writel(tmp, pcie->base + pcie_mem_win0_base_hi(win)); + + limit_addr_mb_high = limit_addr_mb >> high_addr_shift; + tmp = readl(pcie->base + pcie_mem_win0_limit_hi(win)); + u32p_replace_bits(&tmp, limit_addr_mb_high, + pcie_misc_cpu_2_pcie_mem_win0_limit_hi_limit_mask); + writel(tmp, pcie->base + pcie_mem_win0_limit_hi(win)); +} + +/* the controller is capable of serving in both rc and ep roles */ +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + u32 val = readl(base + pcie_misc_pcie_status); + + return !!field_get(pcie_misc_pcie_status_pcie_port_mask, val); +} + +static bool brcm_pcie_link_up(struct brcm_pcie *pcie) +{ + u32 val = readl(pcie->base + pcie_misc_pcie_status); + u32 dla = field_get(pcie_misc_pcie_status_pcie_dl_active_mask, val); + u32 plu = field_get(pcie_misc_pcie_status_pcie_phylinkup_mask, val); + + return dla && plu; +} + +/* configuration space read/write support */ +static inline int brcm_pcie_cfg_index(int busnr, int devfn, int reg) +{ + return ((pci_slot(devfn) & 0x1f) << pcie_ext_slot_shift) + | ((pci_func(devfn) & 0x07) << pcie_ext_func_shift) + | (busnr << pcie_ext_busnum_shift) + | (reg & ~3); +} + +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct brcm_pcie *pcie = bus->sysdata; + void __iomem *base = pcie->base; + int idx; + + /* accesses to the rc go right to the rc registers if slot==0 */ + if (pci_is_root_bus(bus)) + return pci_slot(devfn) ? null : base + where; + + /* for devices, write to the config space index register */ + idx = brcm_pcie_cfg_index(bus->number, devfn, 0); + writel(idx, pcie->base + pcie_ext_cfg_index); + return base + pcie_ext_cfg_data + where; +} + +static struct pci_ops brcm_pcie_ops = { + .map_bus = brcm_pcie_map_conf, + .read = pci_generic_config_read, + .write = pci_generic_config_write, +}; + +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + tmp = readl(pcie->base + pcie_rgr1_sw_init_1); + u32p_replace_bits(&tmp, val, pcie_rgr1_sw_init_1_init_mask); + writel(tmp, pcie->base + pcie_rgr1_sw_init_1); +} + +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie, u32 val) +{ + u32 tmp; + + tmp = readl(pcie->base + pcie_rgr1_sw_init_1); + u32p_replace_bits(&tmp, val, pcie_rgr1_sw_init_1_perst_mask); + writel(tmp, pcie->base + pcie_rgr1_sw_init_1); +} + +static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, + u64 *rc_bar2_size, + u64 *rc_bar2_offset) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + struct device *dev = pcie->dev; + struct resource_entry *entry; + + entry = resource_list_first_type(&bridge->dma_ranges, ioresource_mem); + if (!entry) + return -enodev; + + + /* + * the controller expects the inbound window offset to be calculated as + * the difference between pcie's address space and cpu's. the offset + * provided by the firmware is calculated the opposite way, so we + * negate it. + */ + *rc_bar2_offset = -entry->offset; + *rc_bar2_size = 1ull << fls64(entry->res->end - entry->res->start); + + /* + * we validate the inbound memory view even though we should trust + * whatever the device-tree provides. this is because of an hw issue on + * early raspberry pi 4's revisions (bcm2711). it turns out its + * firmware has to dynamically edit dma-ranges due to a bug on the + * pcie controller integration, which prohibits any access above the + * lower 3gb of memory. given this, we decided to keep the dma-ranges + * in check, avoiding hard to debug device-tree related issues in the + * future: + * + * the pcie host controller by design must set the inbound viewport to + * be a contiguous arrangement of all of the system's memory. in + * addition, its size mut be a power of two. to further complicate + * matters, the viewport must start on a pcie-address that is aligned + * on a multiple of its size. if a portion of the viewport does not + * represent system memory -- e.g. 3gb of memory requires a 4gb + * viewport -- we can map the outbound memory in or after 3gb and even + * though the viewport will overlap the outbound memory the controller + * will know to send outbound memory downstream and everything else + * upstream. + * + * for example: + * + * - the best-case scenario, memory up to 3gb, is to place the inbound + * region in the first 4gb of pcie-space, as some legacy devices can + * only address 32bits. we would also like to put the msi under 4gb + * as well, since some devices require a 32bit msi target address. + * + * - if the system memory is 4gb or larger we cannot start the inbound + * region at location 0 (since we have to allow some space for + * outbound memory @ 3gb). so instead it will start at the 1x + * multiple of its size + */ + if (!*rc_bar2_size || *rc_bar2_offset % *rc_bar2_size || + (*rc_bar2_offset < sz_4g && *rc_bar2_offset > sz_2g)) { + dev_err(dev, "invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx ", + *rc_bar2_size, *rc_bar2_offset); + return -einval; + } + + return 0; +} + +static int brcm_pcie_setup(struct brcm_pcie *pcie) +{ + struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); + u64 rc_bar2_offset, rc_bar2_size; + void __iomem *base = pcie->base; + struct device *dev = pcie->dev; + struct resource_entry *entry; + unsigned int scb_size_val; + bool ssc_good = false; + struct resource *res; + int num_out_wins = 0; + u16 nlw, cls, lnksta; + int i, ret; + u32 tmp; + + /* reset the bridge */ + brcm_pcie_bridge_sw_init_set(pcie, 1); + + usleep_range(100, 200); + + /* take the bridge out of reset */ + brcm_pcie_bridge_sw_init_set(pcie, 0); + + tmp = readl(base + pcie_misc_hard_pcie_hard_debug); + tmp &= ~pcie_misc_hard_pcie_hard_debug_serdes_iddq_mask; + writel(tmp, base + pcie_misc_hard_pcie_hard_debug); + /* wait for serdes to be stable */ + usleep_range(100, 200); + + /* set scb_max_burst_size, cfg_read_ur_mode, scb_access_en */ + u32p_replace_bits(&tmp, 1, pcie_misc_misc_ctrl_scb_access_en_mask); + u32p_replace_bits(&tmp, 1, pcie_misc_misc_ctrl_cfg_read_ur_mode_mask); + u32p_replace_bits(&tmp, pcie_misc_misc_ctrl_max_burst_size_128, + pcie_misc_misc_ctrl_max_burst_size_mask); + writel(tmp, base + pcie_misc_misc_ctrl); + + ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, + &rc_bar2_offset); + if (ret) + return ret; + + tmp = lower_32_bits(rc_bar2_offset); + u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size), + pcie_misc_rc_bar2_config_lo_size_mask); + writel(tmp, base + pcie_misc_rc_bar2_config_lo); + writel(upper_32_bits(rc_bar2_offset), + base + pcie_misc_rc_bar2_config_hi); + + scb_size_val = rc_bar2_size ? + ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1gb */ + tmp = readl(base + pcie_misc_misc_ctrl); + u32p_replace_bits(&tmp, scb_size_val, + pcie_misc_misc_ctrl_scb0_size_mask); + writel(tmp, base + pcie_misc_misc_ctrl); + + /* disable the pcie->gisb memory window (rc_bar1) */ + tmp = readl(base + pcie_misc_rc_bar1_config_lo); + tmp &= ~pcie_misc_rc_bar1_config_lo_size_mask; + writel(tmp, base + pcie_misc_rc_bar1_config_lo); + + /* disable the pcie->scb memory window (rc_bar3) */ + tmp = readl(base + pcie_misc_rc_bar3_config_lo); + tmp &= ~pcie_misc_rc_bar3_config_lo_size_mask; + writel(tmp, base + pcie_misc_rc_bar3_config_lo); + + /* mask all interrupts since we are not handling any yet */ + writel(0xffffffff, pcie->base + pcie_msi_intr2_mask_set); + + /* clear any interrupts we find on boot */ + writel(0xffffffff, pcie->base + pcie_msi_intr2_clr); + + if (pcie->gen) + brcm_pcie_set_gen(pcie, pcie->gen); + + /* unassert the fundamental reset */ + brcm_pcie_perst_set(pcie, 0); + + /* + * give the rc/ep time to wake up, before trying to configure rc. + * intermittently check status for link-up, up to a total of 100ms. + */ + for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) + msleep(5); + + if (!brcm_pcie_link_up(pcie)) { + dev_err(dev, "link down "); + return -enodev; + } + + if (!brcm_pcie_rc_mode(pcie)) { + dev_err(dev, "pcie misconfigured; is in ep mode "); + return -einval; + } + + resource_list_for_each_entry(entry, &bridge->windows) { + res = entry->res; + + if (resource_type(res) != ioresource_mem) + continue; + + if (num_out_wins >= brcm_num_pcie_out_wins) { + dev_err(pcie->dev, "too many outbound wins "); + return -einval; + } + + brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, + res->start - entry->offset, + resource_size(res)); + num_out_wins++; + } + + /* + * for config space accesses on the rc, show the right class for + * a pcie-pcie bridge (the default setting is to be ep mode). + */ + tmp = readl(base + pcie_rc_cfg_priv1_id_val3); + u32p_replace_bits(&tmp, 0x060400, + pcie_rc_cfg_priv1_id_val3_class_code_mask); + writel(tmp, base + pcie_rc_cfg_priv1_id_val3); + + if (pcie->ssc) { + ret = brcm_pcie_set_ssc(pcie); + if (ret == 0) + ssc_good = true; + else + dev_err(dev, "failed attempt to enter ssc mode "); + } + + lnksta = readw(base + brcm_pcie_cap_regs + pci_exp_lnksta); + cls = field_get(pci_exp_lnksta_cls, lnksta); + nlw = field_get(pci_exp_lnksta_nlw, lnksta); + dev_info(dev, "link up, %s x%u %s ", + pcie_speed2str(cls + pci_speed_133mhz_pcix_533), + nlw, ssc_good ? "(ssc)" : "(!ssc)"); + + /* pcie->scb endian mode for bar */ + tmp = readl(base + pcie_rc_cfg_vendor_vendor_specific_reg1); + u32p_replace_bits(&tmp, pcie_rc_cfg_vendor_spcific_reg1_little_endian, + pcie_rc_cfg_vendor_vendor_specific_reg1_endian_mode_bar2_mask); + writel(tmp, base + pcie_rc_cfg_vendor_vendor_specific_reg1); + + /* + * refclk from rc should be gated with clkreq# input when aspm l0s,l1 + * is enabled => setting the clkreq_debug_enable field to 1. + */ + tmp = readl(base + pcie_misc_hard_pcie_hard_debug); + tmp |= pcie_misc_hard_pcie_hard_debug_clkreq_debug_enable_mask; + writel(tmp, base + pcie_misc_hard_pcie_hard_debug); + + return 0; +} + +/* l23 is a low-power pcie link state */ +static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + int l23, i; + u32 tmp; + + /* assert request for l23 */ + tmp = readl(base + pcie_misc_pcie_ctrl); + u32p_replace_bits(&tmp, 1, pcie_misc_pcie_ctrl_pcie_l23_request_mask); + writel(tmp, base + pcie_misc_pcie_ctrl); + + /* wait up to 36 msec for l23 */ + tmp = readl(base + pcie_misc_pcie_status); + l23 = field_get(pcie_misc_pcie_status_pcie_link_in_l23_mask, tmp); + for (i = 0; i < 15 && !l23; i++) { + usleep_range(2000, 2400); + tmp = readl(base + pcie_misc_pcie_status); + l23 = field_get(pcie_misc_pcie_status_pcie_link_in_l23_mask, + tmp); + } + + if (!l23) + dev_err(pcie->dev, "failed to enter low-power link state "); +} + +static void brcm_pcie_turn_off(struct brcm_pcie *pcie) +{ + void __iomem *base = pcie->base; + int tmp; + + if (brcm_pcie_link_up(pcie)) + brcm_pcie_enter_l23(pcie); + /* assert fundamental reset */ + brcm_pcie_perst_set(pcie, 1); + + /* deassert request for l23 in case it was asserted */ + tmp = readl(base + pcie_misc_pcie_ctrl); + u32p_replace_bits(&tmp, 0, pcie_misc_pcie_ctrl_pcie_l23_request_mask); + writel(tmp, base + pcie_misc_pcie_ctrl); + + /* turn off serdes */ + tmp = readl(base + pcie_misc_hard_pcie_hard_debug); + u32p_replace_bits(&tmp, 1, pcie_misc_hard_pcie_hard_debug_serdes_iddq_mask); + writel(tmp, base + pcie_misc_hard_pcie_hard_debug); + + /* shutdown pcie bridge */ + brcm_pcie_bridge_sw_init_set(pcie, 1); +} + +static void __brcm_pcie_remove(struct brcm_pcie *pcie) +{ + brcm_pcie_turn_off(pcie); + clk_disable_unprepare(pcie->clk); + clk_put(pcie->clk); +} + +static int brcm_pcie_remove(struct platform_device *pdev) +{ + struct brcm_pcie *pcie = platform_get_drvdata(pdev); + + pci_stop_root_bus(pcie->root_bus); + pci_remove_root_bus(pcie->root_bus); + __brcm_pcie_remove(pcie); + + return 0; +} + +static int brcm_pcie_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct pci_host_bridge *bridge; + struct brcm_pcie *pcie; + struct pci_bus *child; + struct resource *res; + int ret; + + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); + if (!bridge) + return -enomem; + + pcie = pci_host_bridge_priv(bridge); + pcie->dev = &pdev->dev; + pcie->np = np; + + res = platform_get_resource(pdev, ioresource_mem, 0); + pcie->base = devm_ioremap_resource(&pdev->dev, res); + if (is_err(pcie->base)) + return ptr_err(pcie->base); + + pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); + if (is_err(pcie->clk)) + return ptr_err(pcie->clk); + + ret = of_pci_get_max_link_speed(np); + pcie->gen = (ret < 0) ? 0 : ret; + + pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); + + ret = pci_parse_request_of_pci_ranges(pcie->dev, &bridge->windows, + &bridge->dma_ranges, null); + if (ret) + return ret; + + ret = clk_prepare_enable(pcie->clk); + if (ret) { + dev_err(&pdev->dev, "could not enable clock "); + return ret; + } + + ret = brcm_pcie_setup(pcie); + if (ret) + goto fail; + + bridge->dev.parent = &pdev->dev; + bridge->busnr = 0; + bridge->ops = &brcm_pcie_ops; + bridge->sysdata = pcie; + bridge->map_irq = of_irq_parse_and_map_pci; + bridge->swizzle_irq = pci_common_swizzle; + + ret = pci_scan_root_bus_bridge(bridge); + if (ret < 0) { + dev_err(pcie->dev, "scanning root bridge failed "); + goto fail; + } + + pci_assign_unassigned_bus_resources(bridge->bus); + list_for_each_entry(child, &bridge->bus->children, node) + pcie_bus_configure_settings(child); + pci_bus_add_devices(bridge->bus); + platform_set_drvdata(pdev, pcie); + pcie->root_bus = bridge->bus; + + return 0; +fail: + __brcm_pcie_remove(pcie); + return ret; +} + +static const struct of_device_id brcm_pcie_match[] = { + { .compatible = "brcm,bcm2711-pcie" }, + {}, +}; +module_device_table(of, brcm_pcie_match); + +static struct platform_driver brcm_pcie_driver = { + .probe = brcm_pcie_probe, + .remove = brcm_pcie_remove, + .driver = { + .name = "brcm-pcie", + .of_match_table = brcm_pcie_match, + }, +}; +module_platform_driver(brcm_pcie_driver); + +module_license("gpl"); +module_description("broadcom stb pcie rc driver"); +module_author("broadcom"); | PCI | c0452137034bda8f686dd9a2e167949bfffd6776 | jim quinlan andrew murray andrew murray arm com jeremy linton jeremy linton arm com | drivers | pci | controller |
pci: brcmstb: add msi support | this adds msi support to the broadcom stb pcie host controller. the msi controller is physically located within the pcie block, however, there is no reason why the msi controller could not be moved elsewhere in the future. msix is not supported by the hw. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add msi support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['brcmstb'] | ['c', 'kconfig'] | 2 | 262 | 1 | --- diff --git a/drivers/pci/controller/kconfig b/drivers/pci/controller/kconfig --- a/drivers/pci/controller/kconfig +++ b/drivers/pci/controller/kconfig + depends on pci_msi_irq_domain diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c +#include <linux/bitops.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/msi.h> +#define pcie_misc_msi_bar_config_lo 0x4044 +#define pcie_misc_msi_bar_config_hi 0x4048 + +#define pcie_misc_msi_data_config 0x404c +#define pcie_misc_msi_data_config_val 0xffe06540 + +#define brcm_int_pci_msi_nr 32 + +/* msi target adresses */ +#define brcm_msi_target_addr_lt_4gb 0x0fffffffcull +#define brcm_msi_target_addr_gt_4gb 0xffffffffcull +struct brcm_msi { + struct device *dev; + void __iomem *base; + struct device_node *np; + struct irq_domain *msi_domain; + struct irq_domain *inner_domain; + struct mutex lock; /* guards the alloc/free operations */ + u64 target_addr; + int irq; + /* used indicates which msi interrupts have been alloc'd */ + unsigned long used; +}; + + u64 msi_target_addr; + struct brcm_msi *msi; +static struct irq_chip brcm_msi_irq_chip = { + .name = "brcm stb pcie msi", + .irq_ack = irq_chip_ack_parent, + .irq_mask = pci_msi_mask_irq, + .irq_unmask = pci_msi_unmask_irq, +}; + +static struct msi_domain_info brcm_msi_domain_info = { + /* multi msi is supported by the controller, but not by this driver */ + .flags = (msi_flag_use_def_dom_ops | msi_flag_use_def_chip_ops), + .chip = &brcm_msi_irq_chip, +}; + +static void brcm_pcie_msi_isr(struct irq_desc *desc) +{ + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned long status, virq; + struct brcm_msi *msi; + struct device *dev; + u32 bit; + + chained_irq_enter(chip, desc); + msi = irq_desc_get_handler_data(desc); + dev = msi->dev; + + status = readl(msi->base + pcie_msi_intr2_status); + for_each_set_bit(bit, &status, brcm_int_pci_msi_nr) { + virq = irq_find_mapping(msi->inner_domain, bit); + if (virq) + generic_handle_irq(virq); + else + dev_dbg(dev, "unexpected msi "); + } + + chained_irq_exit(chip, desc); +} + +static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) +{ + struct brcm_msi *msi = irq_data_get_irq_chip_data(data); + + msg->address_lo = lower_32_bits(msi->target_addr); + msg->address_hi = upper_32_bits(msi->target_addr); + msg->data = (0xffff & pcie_misc_msi_data_config_val) | data->hwirq; +} + +static int brcm_msi_set_affinity(struct irq_data *irq_data, + const struct cpumask *mask, bool force) +{ + return -einval; +} + +static void brcm_msi_ack_irq(struct irq_data *data) +{ + struct brcm_msi *msi = irq_data_get_irq_chip_data(data); + + writel(1 << data->hwirq, msi->base + pcie_msi_intr2_clr); +} + + +static struct irq_chip brcm_msi_bottom_irq_chip = { + .name = "brcm stb msi", + .irq_compose_msi_msg = brcm_msi_compose_msi_msg, + .irq_set_affinity = brcm_msi_set_affinity, + .irq_ack = brcm_msi_ack_irq, +}; + +static int brcm_msi_alloc(struct brcm_msi *msi) +{ + int hwirq; + + mutex_lock(&msi->lock); + hwirq = bitmap_find_free_region(&msi->used, brcm_int_pci_msi_nr, 0); + mutex_unlock(&msi->lock); + + return hwirq; +} + +static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq) +{ + mutex_lock(&msi->lock); + bitmap_release_region(&msi->used, hwirq, 0); + mutex_unlock(&msi->lock); +} + +static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, + unsigned int nr_irqs, void *args) +{ + struct brcm_msi *msi = domain->host_data; + int hwirq; + + hwirq = brcm_msi_alloc(msi); + + if (hwirq < 0) + return hwirq; + + irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq, + &brcm_msi_bottom_irq_chip, domain->host_data, + handle_edge_irq, null, null); + return 0; +} + +static void brcm_irq_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d = irq_domain_get_irq_data(domain, virq); + struct brcm_msi *msi = irq_data_get_irq_chip_data(d); + + brcm_msi_free(msi, d->hwirq); +} + +static const struct irq_domain_ops msi_domain_ops = { + .alloc = brcm_irq_domain_alloc, + .free = brcm_irq_domain_free, +}; + +static int brcm_allocate_domains(struct brcm_msi *msi) +{ + struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); + struct device *dev = msi->dev; + + msi->inner_domain = irq_domain_add_linear(null, brcm_int_pci_msi_nr, + &msi_domain_ops, msi); + if (!msi->inner_domain) { + dev_err(dev, "failed to create irq domain "); + return -enomem; + } + + msi->msi_domain = pci_msi_create_irq_domain(fwnode, + &brcm_msi_domain_info, + msi->inner_domain); + if (!msi->msi_domain) { + dev_err(dev, "failed to create msi domain "); + irq_domain_remove(msi->inner_domain); + return -enomem; + } + + return 0; +} + +static void brcm_free_domains(struct brcm_msi *msi) +{ + irq_domain_remove(msi->msi_domain); + irq_domain_remove(msi->inner_domain); +} + +static void brcm_msi_remove(struct brcm_pcie *pcie) +{ + struct brcm_msi *msi = pcie->msi; + + if (!msi) + return; + irq_set_chained_handler(msi->irq, null); + irq_set_handler_data(msi->irq, null); + brcm_free_domains(msi); +} + +static void brcm_msi_set_regs(struct brcm_msi *msi) +{ + writel(0xffffffff, msi->base + pcie_msi_intr2_mask_clr); + + /* + * the 0 bit of pcie_misc_msi_bar_config_lo is repurposed to msi + * enable, which we set to 1. + */ + writel(lower_32_bits(msi->target_addr) | 0x1, + msi->base + pcie_misc_msi_bar_config_lo); + writel(upper_32_bits(msi->target_addr), + msi->base + pcie_misc_msi_bar_config_hi); + + writel(pcie_misc_msi_data_config_val, + msi->base + pcie_misc_msi_data_config); +} + +static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) +{ + struct brcm_msi *msi; + int irq, ret; + struct device *dev = pcie->dev; + + irq = irq_of_parse_and_map(dev->of_node, 1); + if (irq <= 0) { + dev_err(dev, "cannot map msi interrupt "); + return -enodev; + } + + msi = devm_kzalloc(dev, sizeof(struct brcm_msi), gfp_kernel); + if (!msi) + return -enomem; + + mutex_init(&msi->lock); + msi->dev = dev; + msi->base = pcie->base; + msi->np = pcie->np; + msi->target_addr = pcie->msi_target_addr; + msi->irq = irq; + + ret = brcm_allocate_domains(msi); + if (ret) + return ret; + + irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); + + brcm_msi_set_regs(msi); + pcie->msi = msi; + + return 0; +} + + /* + * we ideally want the msi target address to be located in the 32bit + * addressable memory area. some devices might depend on it. this is + * possible either when the inbound window is located above the lower + * 4gb or when the inbound area is smaller than 4gb (taking into + * account the rounding-up we're forced to perform). + */ + if (rc_bar2_offset >= sz_4g || (rc_bar2_size + rc_bar2_offset) < sz_4g) + pcie->msi_target_addr = brcm_msi_target_addr_lt_4gb; + else + pcie->msi_target_addr = brcm_msi_target_addr_gt_4gb; + + brcm_msi_remove(pcie); - struct device_node *np = pdev->dev.of_node; + struct device_node *np = pdev->dev.of_node, *msi_np; + msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); + if (pci_msi_enabled() && msi_np == pcie->np) { + ret = brcm_pcie_enable_msi(pcie); + if (ret) { + dev_err(pcie->dev, "probe of internal msi failed"); + goto fail; + } + } + | PCI | 40ca1bf580ef24df30702032ba5e40dfdcaa200b | jim quinlan | drivers | pci | controller |
pci: dwc: intel: pcie rc controller driver | add support to pcie rc controller on intel gateway socs. pcie controller is based of synopsys designware pcie core. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | pcie rc controller driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['dwc', 'intel'] | ['c', 'kconfig', 'makefile', 'h'] | 6 | 626 | 0 | --- diff --git a/drivers/pci/controller/dwc/kconfig b/drivers/pci/controller/dwc/kconfig --- a/drivers/pci/controller/dwc/kconfig +++ b/drivers/pci/controller/dwc/kconfig +config pcie_intel_gw + bool "intel gateway pcie host controller support" + depends on of && (x86 || compile_test) + depends on pci_msi_irq_domain + select pcie_dw_host + help + say 'y' here to enable pcie host controller support on intel + gateway socs. + the pcie controller uses the designware core plus intel-specific + hardware wrappers. + diff --git a/drivers/pci/controller/dwc/makefile b/drivers/pci/controller/dwc/makefile --- a/drivers/pci/controller/dwc/makefile +++ b/drivers/pci/controller/dwc/makefile +obj-$(config_pcie_intel_gw) += pcie-intel-gw.o diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c +#include "../../pci.h" +void dw_pcie_upconfig_setup(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, pcie_port_multi_lane_ctrl); + val |= port_mlti_upcfg_support; + dw_pcie_writel_dbi(pci, pcie_port_multi_lane_ctrl, val); +} +export_symbol_gpl(dw_pcie_upconfig_setup); + +void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen) +{ + u32 reg, val; + u8 offset = dw_pcie_find_capability(pci, pci_cap_id_exp); + + reg = dw_pcie_readl_dbi(pci, offset + pci_exp_lnkctl2); + reg &= ~pci_exp_lnkctl2_tls; + + switch (pcie_link_speed[link_gen]) { + case pcie_speed_2_5gt: + reg |= pci_exp_lnkctl2_tls_2_5gt; + break; + case pcie_speed_5_0gt: + reg |= pci_exp_lnkctl2_tls_5_0gt; + break; + case pcie_speed_8_0gt: + reg |= pci_exp_lnkctl2_tls_8_0gt; + break; + case pcie_speed_16_0gt: + reg |= pci_exp_lnkctl2_tls_16_0gt; + break; + default: + /* use hardware capability */ + val = dw_pcie_readl_dbi(pci, offset + pci_exp_lnkcap); + val = field_get(pci_exp_lnkcap_sls, val); + reg &= ~pci_exp_lnkctl2_hasd; + reg |= field_prep(pci_exp_lnkctl2_tls, val); + break; + } + + dw_pcie_writel_dbi(pci, offset + pci_exp_lnkctl2, reg); +} +export_symbol_gpl(dw_pcie_link_set_max_speed); + +void dw_pcie_link_set_n_fts(struct dw_pcie *pci, u32 n_fts) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, pcie_link_width_speed_control); + val &= ~port_logic_n_fts_mask; + val |= n_fts & port_logic_n_fts_mask; + dw_pcie_writel_dbi(pci, pcie_link_width_speed_control, val); +} +export_symbol_gpl(dw_pcie_link_set_n_fts); + diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h +#define pcie_port_afr 0x70c +#define port_afr_n_fts_mask genmask(15, 8) +#define port_afr_cc_n_fts_mask genmask(23, 16) + +#define port_link_dll_link_en bit(5) +#define port_logic_n_fts_mask genmask(7, 0) +#define pcie_port_multi_lane_ctrl 0x8c0 +#define port_mlti_upcfg_support bit(7) + +void dw_pcie_upconfig_setup(struct dw_pcie *pci); +void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen); +void dw_pcie_link_set_n_fts(struct dw_pcie *pci, u32 n_fts); diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c +// spdx-license-identifier: gpl-2.0 +/* + * pcie host controller driver for intel gateway socs + * + * copyright (c) 2019 intel corporation. + */ + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/gpio/consumer.h> +#include <linux/iopoll.h> +#include <linux/pci_regs.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/reset.h> + +#include "../../pci.h" +#include "pcie-designware.h" + +#define port_afr_n_fts_gen12_dft (sz_128 - 1) +#define port_afr_n_fts_gen3 180 +#define port_afr_n_fts_gen4 196 + +/* pcie application logic registers */ +#define pcie_app_ccr 0x10 +#define pcie_app_ccr_ltssm_enable bit(0) + +#define pcie_app_msg_cr 0x30 +#define pcie_app_msg_xmt_pm_turnoff bit(0) + +#define pcie_app_pmc 0x44 +#define pcie_app_pmc_in_l2 bit(20) + +#define pcie_app_irnen 0xf4 +#define pcie_app_irncr 0xf8 +#define pcie_app_irn_aer_report bit(0) +#define pcie_app_irn_pme bit(2) +#define pcie_app_irn_rx_vdm_msg bit(4) +#define pcie_app_irn_pm_to_ack bit(9) +#define pcie_app_irn_link_auto_bw_stat bit(11) +#define pcie_app_irn_bw_mgt bit(12) +#define pcie_app_irn_msg_ltr bit(18) +#define pcie_app_irn_sys_err_rc bit(29) +#define pcie_app_intx_ofst 12 + +#define pcie_app_irn_int \ + (pcie_app_irn_aer_report | pcie_app_irn_pme | \ + pcie_app_irn_rx_vdm_msg | pcie_app_irn_sys_err_rc | \ + pcie_app_irn_pm_to_ack | pcie_app_irn_msg_ltr | \ + pcie_app_irn_bw_mgt | pcie_app_irn_link_auto_bw_stat | \ + (pcie_app_intx_ofst + pci_interrupt_inta) | \ + (pcie_app_intx_ofst + pci_interrupt_intb) | \ + (pcie_app_intx_ofst + pci_interrupt_intc) | \ + (pcie_app_intx_ofst + pci_interrupt_intd)) + +#define bus_iatu_offset sz_256m +#define reset_interval_ms 100 + +struct intel_pcie_soc { + unsigned int pcie_ver; + unsigned int pcie_atu_offset; + u32 num_viewport; +}; + +struct intel_pcie_port { + struct dw_pcie pci; + void __iomem *app_base; + struct gpio_desc *reset_gpio; + u32 rst_intrvl; + u32 max_speed; + u32 link_gen; + u32 max_width; + u32 n_fts; + struct clk *core_clk; + struct reset_control *core_rst; + struct phy *phy; + u8 pcie_cap_ofst; +}; + +static void pcie_update_bits(void __iomem *base, u32 ofs, u32 mask, u32 val) +{ + u32 old; + + old = readl(base + ofs); + val = (old & ~mask) | (val & mask); + + if (val != old) + writel(val, base + ofs); +} + +static inline u32 pcie_app_rd(struct intel_pcie_port *lpp, u32 ofs) +{ + return readl(lpp->app_base + ofs); +} + +static inline void pcie_app_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val) +{ + writel(val, lpp->app_base + ofs); +} + +static void pcie_app_wr_mask(struct intel_pcie_port *lpp, u32 ofs, + u32 mask, u32 val) +{ + pcie_update_bits(lpp->app_base, ofs, mask, val); +} + +static inline u32 pcie_rc_cfg_rd(struct intel_pcie_port *lpp, u32 ofs) +{ + return dw_pcie_readl_dbi(&lpp->pci, ofs); +} + +static inline void pcie_rc_cfg_wr(struct intel_pcie_port *lpp, u32 ofs, u32 val) +{ + dw_pcie_writel_dbi(&lpp->pci, ofs, val); +} + +static void pcie_rc_cfg_wr_mask(struct intel_pcie_port *lpp, u32 ofs, + u32 mask, u32 val) +{ + pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); +} + +static void intel_pcie_ltssm_enable(struct intel_pcie_port *lpp) +{ + pcie_app_wr_mask(lpp, pcie_app_ccr, pcie_app_ccr_ltssm_enable, + pcie_app_ccr_ltssm_enable); +} + +static void intel_pcie_ltssm_disable(struct intel_pcie_port *lpp) +{ + pcie_app_wr_mask(lpp, pcie_app_ccr, pcie_app_ccr_ltssm_enable, 0); +} + +static void intel_pcie_link_setup(struct intel_pcie_port *lpp) +{ + u32 val; + u8 offset = lpp->pcie_cap_ofst; + + val = pcie_rc_cfg_rd(lpp, offset + pci_exp_lnkcap); + lpp->max_speed = field_get(pci_exp_lnkcap_sls, val); + lpp->max_width = field_get(pci_exp_lnkcap_mlw, val); + + val = pcie_rc_cfg_rd(lpp, offset + pci_exp_lnkctl); + + val &= ~(pci_exp_lnkctl_ld | pci_exp_lnkctl_aspmc); + pcie_rc_cfg_wr(lpp, offset + pci_exp_lnkctl, val); +} + +static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp) +{ + u32 val, mask; + + switch (pcie_link_speed[lpp->max_speed]) { + case pcie_speed_8_0gt: + lpp->n_fts = port_afr_n_fts_gen3; + break; + case pcie_speed_16_0gt: + lpp->n_fts = port_afr_n_fts_gen4; + break; + default: + lpp->n_fts = port_afr_n_fts_gen12_dft; + break; + } + + mask = port_afr_n_fts_mask | port_afr_cc_n_fts_mask; + val = field_prep(port_afr_n_fts_mask, lpp->n_fts) | + field_prep(port_afr_cc_n_fts_mask, lpp->n_fts); + pcie_rc_cfg_wr_mask(lpp, pcie_port_afr, mask, val); + + /* port link control register */ + pcie_rc_cfg_wr_mask(lpp, pcie_port_link_control, port_link_dll_link_en, + port_link_dll_link_en); +} + +static void intel_pcie_rc_setup(struct intel_pcie_port *lpp) +{ + intel_pcie_ltssm_disable(lpp); + intel_pcie_link_setup(lpp); + dw_pcie_setup_rc(&lpp->pci.pp); + dw_pcie_upconfig_setup(&lpp->pci); + intel_pcie_port_logic_setup(lpp); + dw_pcie_link_set_max_speed(&lpp->pci, lpp->link_gen); + dw_pcie_link_set_n_fts(&lpp->pci, lpp->n_fts); +} + +static int intel_pcie_ep_rst_init(struct intel_pcie_port *lpp) +{ + struct device *dev = lpp->pci.dev; + int ret; + + lpp->reset_gpio = devm_gpiod_get(dev, "reset", gpiod_out_low); + if (is_err(lpp->reset_gpio)) { + ret = ptr_err(lpp->reset_gpio); + if (ret != -eprobe_defer) + dev_err(dev, "failed to request pcie gpio: %d ", ret); + return ret; + } + + /* make initial reset last for 100us */ + usleep_range(100, 200); + + return 0; +} + +static void intel_pcie_core_rst_assert(struct intel_pcie_port *lpp) +{ + reset_control_assert(lpp->core_rst); +} + +static void intel_pcie_core_rst_deassert(struct intel_pcie_port *lpp) +{ + /* + * one micro-second delay to make sure the reset pulse + * wide enough so that core reset is clean. + */ + udelay(1); + reset_control_deassert(lpp->core_rst); + + /* + * some soc core reset also reset phy, more delay needed + * to make sure the reset process is done. + */ + usleep_range(1000, 2000); +} + +static void intel_pcie_device_rst_assert(struct intel_pcie_port *lpp) +{ + gpiod_set_value_cansleep(lpp->reset_gpio, 1); +} + +static void intel_pcie_device_rst_deassert(struct intel_pcie_port *lpp) +{ + msleep(lpp->rst_intrvl); + gpiod_set_value_cansleep(lpp->reset_gpio, 0); +} + +static int intel_pcie_app_logic_setup(struct intel_pcie_port *lpp) +{ + intel_pcie_device_rst_deassert(lpp); + intel_pcie_ltssm_enable(lpp); + + return dw_pcie_wait_for_link(&lpp->pci); +} + +static void intel_pcie_core_irq_disable(struct intel_pcie_port *lpp) +{ + pcie_app_wr(lpp, pcie_app_irnen, 0); + pcie_app_wr(lpp, pcie_app_irncr, pcie_app_irn_int); +} + +static int intel_pcie_get_resources(struct platform_device *pdev) +{ + struct intel_pcie_port *lpp = platform_get_drvdata(pdev); + struct dw_pcie *pci = &lpp->pci; + struct device *dev = pci->dev; + struct resource *res; + int ret; + + res = platform_get_resource_byname(pdev, ioresource_mem, "dbi"); + pci->dbi_base = devm_ioremap_resource(dev, res); + if (is_err(pci->dbi_base)) + return ptr_err(pci->dbi_base); + + lpp->core_clk = devm_clk_get(dev, null); + if (is_err(lpp->core_clk)) { + ret = ptr_err(lpp->core_clk); + if (ret != -eprobe_defer) + dev_err(dev, "failed to get clks: %d ", ret); + return ret; + } + + lpp->core_rst = devm_reset_control_get(dev, null); + if (is_err(lpp->core_rst)) { + ret = ptr_err(lpp->core_rst); + if (ret != -eprobe_defer) + dev_err(dev, "failed to get resets: %d ", ret); + return ret; + } + + ret = device_property_match_string(dev, "device_type", "pci"); + if (ret) { + dev_err(dev, "failed to find pci device type: %d ", ret); + return ret; + } + + ret = device_property_read_u32(dev, "reset-assert-ms", + &lpp->rst_intrvl); + if (ret) + lpp->rst_intrvl = reset_interval_ms; + + ret = of_pci_get_max_link_speed(dev->of_node); + lpp->link_gen = ret < 0 ? 0 : ret; + + res = platform_get_resource_byname(pdev, ioresource_mem, "app"); + lpp->app_base = devm_ioremap_resource(dev, res); + if (is_err(lpp->app_base)) + return ptr_err(lpp->app_base); + + lpp->phy = devm_phy_get(dev, "pcie"); + if (is_err(lpp->phy)) { + ret = ptr_err(lpp->phy); + if (ret != -eprobe_defer) + dev_err(dev, "couldn't get pcie-phy: %d ", ret); + return ret; + } + + return 0; +} + +static void intel_pcie_deinit_phy(struct intel_pcie_port *lpp) +{ + phy_exit(lpp->phy); +} + +static int intel_pcie_wait_l2(struct intel_pcie_port *lpp) +{ + u32 value; + int ret; + + if (pcie_link_speed[lpp->max_speed] < pcie_speed_8_0gt) + return 0; + + /* send pme_turn_off message */ + pcie_app_wr_mask(lpp, pcie_app_msg_cr, pcie_app_msg_xmt_pm_turnoff, + pcie_app_msg_xmt_pm_turnoff); + + /* read pmc status and wait for falling into l2 link state */ + ret = readl_poll_timeout(lpp->app_base + pcie_app_pmc, value, + value & pcie_app_pmc_in_l2, 20, + jiffies_to_usecs(5 * hz)); + if (ret) + dev_err(lpp->pci.dev, "pcie link enter l2 timeout! "); + + return ret; +} + +static void intel_pcie_turn_off(struct intel_pcie_port *lpp) +{ + if (dw_pcie_link_up(&lpp->pci)) + intel_pcie_wait_l2(lpp); + + /* put endpoint device in reset state */ + intel_pcie_device_rst_assert(lpp); + pcie_rc_cfg_wr_mask(lpp, pci_command, pci_command_memory, 0); +} + +static int intel_pcie_host_setup(struct intel_pcie_port *lpp) +{ + struct device *dev = lpp->pci.dev; + int ret; + + intel_pcie_core_rst_assert(lpp); + intel_pcie_device_rst_assert(lpp); + + ret = phy_init(lpp->phy); + if (ret) + return ret; + + intel_pcie_core_rst_deassert(lpp); + + ret = clk_prepare_enable(lpp->core_clk); + if (ret) { + dev_err(lpp->pci.dev, "core clock enable failed: %d ", ret); + goto clk_err; + } + + if (!lpp->pcie_cap_ofst) { + ret = dw_pcie_find_capability(&lpp->pci, pci_cap_id_exp); + if (!ret) { + ret = -enxio; + dev_err(dev, "invalid pcie capability offset "); + goto app_init_err; + } + + lpp->pcie_cap_ofst = ret; + } + + intel_pcie_rc_setup(lpp); + ret = intel_pcie_app_logic_setup(lpp); + if (ret) + goto app_init_err; + + /* enable integrated interrupts */ + pcie_app_wr_mask(lpp, pcie_app_irnen, pcie_app_irn_int, + pcie_app_irn_int); + + return 0; + +app_init_err: + clk_disable_unprepare(lpp->core_clk); +clk_err: + intel_pcie_core_rst_assert(lpp); + intel_pcie_deinit_phy(lpp); + + return ret; +} + +static void __intel_pcie_remove(struct intel_pcie_port *lpp) +{ + intel_pcie_core_irq_disable(lpp); + intel_pcie_turn_off(lpp); + clk_disable_unprepare(lpp->core_clk); + intel_pcie_core_rst_assert(lpp); + intel_pcie_deinit_phy(lpp); +} + +static int intel_pcie_remove(struct platform_device *pdev) +{ + struct intel_pcie_port *lpp = platform_get_drvdata(pdev); + struct pcie_port *pp = &lpp->pci.pp; + + dw_pcie_host_deinit(pp); + __intel_pcie_remove(lpp); + + return 0; +} + +static int __maybe_unused intel_pcie_suspend_noirq(struct device *dev) +{ + struct intel_pcie_port *lpp = dev_get_drvdata(dev); + int ret; + + intel_pcie_core_irq_disable(lpp); + ret = intel_pcie_wait_l2(lpp); + if (ret) + return ret; + + intel_pcie_deinit_phy(lpp); + clk_disable_unprepare(lpp->core_clk); + return ret; +} + +static int __maybe_unused intel_pcie_resume_noirq(struct device *dev) +{ + struct intel_pcie_port *lpp = dev_get_drvdata(dev); + + return intel_pcie_host_setup(lpp); +} + +static int intel_pcie_rc_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct intel_pcie_port *lpp = dev_get_drvdata(pci->dev); + + return intel_pcie_host_setup(lpp); +} + +/* + * dummy function so that dw core doesn't configure msi + */ +static int intel_pcie_msi_init(struct pcie_port *pp) +{ + return 0; +} + +u64 intel_pcie_cpu_addr(struct dw_pcie *pcie, u64 cpu_addr) +{ + return cpu_addr + bus_iatu_offset; +} + +static const struct dw_pcie_ops intel_pcie_ops = { + .cpu_addr_fixup = intel_pcie_cpu_addr, +}; + +static const struct dw_pcie_host_ops intel_pcie_dw_ops = { + .host_init = intel_pcie_rc_init, + .msi_host_init = intel_pcie_msi_init, +}; + +static const struct intel_pcie_soc pcie_data = { + .pcie_ver = 0x520a, + .pcie_atu_offset = 0xc0000, + .num_viewport = 3, +}; + +static int intel_pcie_probe(struct platform_device *pdev) +{ + const struct intel_pcie_soc *data; + struct device *dev = &pdev->dev; + struct intel_pcie_port *lpp; + struct pcie_port *pp; + struct dw_pcie *pci; + int ret; + + lpp = devm_kzalloc(dev, sizeof(*lpp), gfp_kernel); + if (!lpp) + return -enomem; + + platform_set_drvdata(pdev, lpp); + pci = &lpp->pci; + pci->dev = dev; + pp = &pci->pp; + + ret = intel_pcie_get_resources(pdev); + if (ret) + return ret; + + ret = intel_pcie_ep_rst_init(lpp); + if (ret) + return ret; + + data = device_get_match_data(dev); + if (!data) + return -enodev; + + pci->ops = &intel_pcie_ops; + pci->version = data->pcie_ver; + pci->atu_base = pci->dbi_base + data->pcie_atu_offset; + pp->ops = &intel_pcie_dw_ops; + + ret = dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "cannot initialize host "); + return ret; + } + + /* + * intel pcie doesn't configure io region, so set viewport + * to not perform io region access. + */ + pci->num_viewport = data->num_viewport; + + return 0; +} + +static const struct dev_pm_ops intel_pcie_pm_ops = { + set_noirq_system_sleep_pm_ops(intel_pcie_suspend_noirq, + intel_pcie_resume_noirq) +}; + +static const struct of_device_id of_intel_pcie_match[] = { + { .compatible = "intel,lgm-pcie", .data = &pcie_data }, + {} +}; + +static struct platform_driver intel_pcie_driver = { + .probe = intel_pcie_probe, + .remove = intel_pcie_remove, + .driver = { + .name = "intel-gw-pcie", + .of_match_table = of_intel_pcie_match, + .pm = &intel_pcie_pm_ops, + }, +}; +builtin_platform_driver(intel_pcie_driver); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h +#define pci_exp_lnkctl2_hasd 0x0020 /* hw autonomous speed disable */ | PCI | ed22aaaede44f647477a5048e62855c0ed49c9bd | dilip kota | include | uapi | controller, dwc, linux |
pci: qcom: add support for sdm845 pcie controller | the sdm845 has one gen2 and one gen3 controller, add support for these. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for sdm845 pcie controller | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['qcom'] | ['c'] | 1 | 150 | 0 | --- diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c +#define pcie20_parf_device_type 0x1000 +#define device_type_rc 0x4 + +struct qcom_pcie_resources_2_7_0 { + struct clk_bulk_data clks[6]; + struct regulator_bulk_data supplies[2]; + struct reset_control *pci_reset; + struct clk *pipe_clk; +}; + + struct qcom_pcie_resources_2_7_0 v2_7_0; +static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + int ret; + + res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); + if (is_err(res->pci_reset)) + return ptr_err(res->pci_reset); + + res->supplies[0].supply = "vdda"; + res->supplies[1].supply = "vddpe-3v3"; + ret = devm_regulator_bulk_get(dev, array_size(res->supplies), + res->supplies); + if (ret) + return ret; + + res->clks[0].id = "aux"; + res->clks[1].id = "cfg"; + res->clks[2].id = "bus_master"; + res->clks[3].id = "bus_slave"; + res->clks[4].id = "slave_q2a"; + res->clks[5].id = "tbu"; + + ret = devm_clk_bulk_get(dev, array_size(res->clks), res->clks); + if (ret < 0) + return ret; + + res->pipe_clk = devm_clk_get(dev, "pipe"); + return ptr_err_or_zero(res->pipe_clk); +} + +static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + struct dw_pcie *pci = pcie->pci; + struct device *dev = pci->dev; + u32 val; + int ret; + + ret = regulator_bulk_enable(array_size(res->supplies), res->supplies); + if (ret < 0) { + dev_err(dev, "cannot enable regulators "); + return ret; + } + + ret = clk_bulk_prepare_enable(array_size(res->clks), res->clks); + if (ret < 0) + goto err_disable_regulators; + + ret = reset_control_assert(res->pci_reset); + if (ret < 0) { + dev_err(dev, "cannot deassert pci reset "); + goto err_disable_clocks; + } + + usleep_range(1000, 1500); + + ret = reset_control_deassert(res->pci_reset); + if (ret < 0) { + dev_err(dev, "cannot deassert pci reset "); + goto err_disable_clocks; + } + + ret = clk_prepare_enable(res->pipe_clk); + if (ret) { + dev_err(dev, "cannot prepare/enable pipe clock "); + goto err_disable_clocks; + } + + /* configure pcie to rc mode */ + writel(device_type_rc, pcie->parf + pcie20_parf_device_type); + + /* enable pcie clocks and resets */ + val = readl(pcie->parf + pcie20_parf_phy_ctrl); + val &= ~bit(0); + writel(val, pcie->parf + pcie20_parf_phy_ctrl); + + /* change dbi base address */ + writel(0, pcie->parf + pcie20_parf_dbi_base_addr); + + /* mac phy_powerdown mux disable */ + val = readl(pcie->parf + pcie20_parf_sys_ctrl); + val &= ~bit(29); + writel(val, pcie->parf + pcie20_parf_sys_ctrl); + + val = readl(pcie->parf + pcie20_parf_mhi_clock_reset_ctrl); + val |= bit(4); + writel(val, pcie->parf + pcie20_parf_mhi_clock_reset_ctrl); + + if (is_enabled(config_pci_msi)) { + val = readl(pcie->parf + pcie20_parf_axi_mstr_wr_addr_halt); + val |= bit(31); + writel(val, pcie->parf + pcie20_parf_axi_mstr_wr_addr_halt); + } + + return 0; +err_disable_clocks: + clk_bulk_disable_unprepare(array_size(res->clks), res->clks); +err_disable_regulators: + regulator_bulk_disable(array_size(res->supplies), res->supplies); + + return ret; +} + +static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + clk_bulk_disable_unprepare(array_size(res->clks), res->clks); + regulator_bulk_disable(array_size(res->supplies), res->supplies); +} + +static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + return clk_prepare_enable(res->pipe_clk); +} + +static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie) +{ + struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; + + clk_disable_unprepare(res->pipe_clk); +} + +/* qcom ip rev.: 2.7.0 synopsys ip rev.: 4.30a */ +static const struct qcom_pcie_ops ops_2_7_0 = { + .get_resources = qcom_pcie_get_resources_2_7_0, + .init = qcom_pcie_init_2_7_0, + .deinit = qcom_pcie_deinit_2_7_0, + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, + .post_init = qcom_pcie_post_init_2_7_0, + .post_deinit = qcom_pcie_post_deinit_2_7_0, +}; + + { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 }, | PCI | ed8cc3b1fc84f110336edaafaa203f65aa26b5e0 | bjorn andersson stanimir varbanov svarbanov mm sol com vinod koul vkoul kernel org philipp zabel p zabel pengutronix de andrew murray andrew murray arm com | drivers | pci | controller, dwc |
pci/switchtec: add gen4 device ids | now that gen4 is properly supported, advertise support in the module's device id table and add the same ids to the list of switchtec quirks. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add gen4 device ids | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['switchtec'] | ['c'] | 2 | 36 | 0 | --- diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c +switchtec_quirk(0x4000); /* pfx 100xg4 */ +switchtec_quirk(0x4084); /* pfx 84xg4 */ +switchtec_quirk(0x4068); /* pfx 68xg4 */ +switchtec_quirk(0x4052); /* pfx 52xg4 */ +switchtec_quirk(0x4036); /* pfx 36xg4 */ +switchtec_quirk(0x4028); /* pfx 28xg4 */ +switchtec_quirk(0x4100); /* psx 100xg4 */ +switchtec_quirk(0x4184); /* psx 84xg4 */ +switchtec_quirk(0x4168); /* psx 68xg4 */ +switchtec_quirk(0x4152); /* psx 52xg4 */ +switchtec_quirk(0x4136); /* psx 36xg4 */ +switchtec_quirk(0x4128); /* psx 28xg4 */ +switchtec_quirk(0x4200); /* pax 100xg4 */ +switchtec_quirk(0x4284); /* pax 84xg4 */ +switchtec_quirk(0x4268); /* pax 68xg4 */ +switchtec_quirk(0x4252); /* pax 52xg4 */ +switchtec_quirk(0x4236); /* pax 36xg4 */ +switchtec_quirk(0x4228); /* pax 28xg4 */ diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c + switchtec_pci_device(0x4000, switchtec_gen4), //pfx 100xg4 + switchtec_pci_device(0x4084, switchtec_gen4), //pfx 84xg4 + switchtec_pci_device(0x4068, switchtec_gen4), //pfx 68xg4 + switchtec_pci_device(0x4052, switchtec_gen4), //pfx 52xg4 + switchtec_pci_device(0x4036, switchtec_gen4), //pfx 36xg4 + switchtec_pci_device(0x4028, switchtec_gen4), //pfx 28xg4 + switchtec_pci_device(0x4100, switchtec_gen4), //psx 100xg4 + switchtec_pci_device(0x4184, switchtec_gen4), //psx 84xg4 + switchtec_pci_device(0x4168, switchtec_gen4), //psx 68xg4 + switchtec_pci_device(0x4152, switchtec_gen4), //psx 52xg4 + switchtec_pci_device(0x4136, switchtec_gen4), //psx 36xg4 + switchtec_pci_device(0x4128, switchtec_gen4), //psx 28xg4 + switchtec_pci_device(0x4200, switchtec_gen4), //pax 100xg4 + switchtec_pci_device(0x4284, switchtec_gen4), //pax 84xg4 + switchtec_pci_device(0x4268, switchtec_gen4), //pax 68xg4 + switchtec_pci_device(0x4252, switchtec_gen4), //pax 52xg4 + switchtec_pci_device(0x4236, switchtec_gen4), //pax 36xg4 + switchtec_pci_device(0x4228, switchtec_gen4), //pax 28xg4 | PCI | 7a30ebb9f2a253eae908cc3e1ba7daaa3bfe2bba | kelvin cao | drivers | pci | switch |
pci/switchtec: add gen4 flash information interface support | add the new flash_info registers struct and the implementation of ioctl_flash_part_info() for the new gen4 hardware. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add gen4 flash information interface support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['switchtec'] | ['c', 'h'] | 3 | 171 | 0 | --- diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c + } else if (stdev->gen == switchtec_gen4) { + info.flash_length = ioread32(&fi->gen4.flash_length); + info.num_partitions = switchtec_num_partitions_gen4; +static int flash_part_info_gen4(struct switchtec_dev *stdev, + struct switchtec_ioctl_flash_part_info *info) +{ + struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4; + struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4; + struct active_partition_info_gen4 __iomem *af = &fi->active_flag; + + switch (info->flash_partition) { + case switchtec_ioctl_part_map_0: + set_fw_info_part(info, &fi->map0); + break; + case switchtec_ioctl_part_map_1: + set_fw_info_part(info, &fi->map1); + break; + case switchtec_ioctl_part_key_0: + set_fw_info_part(info, &fi->key0); + if (ioread8(&af->key) == switchtec_gen4_key0_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->key_running) == switchtec_gen4_key0_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_key_1: + set_fw_info_part(info, &fi->key1); + if (ioread8(&af->key) == switchtec_gen4_key1_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->key_running) == switchtec_gen4_key1_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_bl2_0: + set_fw_info_part(info, &fi->bl2_0); + if (ioread8(&af->bl2) == switchtec_gen4_bl2_0_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->bl2_running) == switchtec_gen4_bl2_0_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_bl2_1: + set_fw_info_part(info, &fi->bl2_1); + if (ioread8(&af->bl2) == switchtec_gen4_bl2_1_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->bl2_running) == switchtec_gen4_bl2_1_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_cfg0: + set_fw_info_part(info, &fi->cfg0); + if (ioread8(&af->cfg) == switchtec_gen4_cfg0_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->cfg_running) == switchtec_gen4_cfg0_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_cfg1: + set_fw_info_part(info, &fi->cfg1); + if (ioread8(&af->cfg) == switchtec_gen4_cfg1_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->cfg_running) == switchtec_gen4_cfg1_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_img0: + set_fw_info_part(info, &fi->img0); + if (ioread8(&af->img) == switchtec_gen4_img0_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->img_running) == switchtec_gen4_img0_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_img1: + set_fw_info_part(info, &fi->img1); + if (ioread8(&af->img) == switchtec_gen4_img1_active) + info->active |= switchtec_ioctl_part_active; + if (ioread16(&si->img_running) == switchtec_gen4_img1_running) + info->active |= switchtec_ioctl_part_running; + break; + case switchtec_ioctl_part_nvlog: + set_fw_info_part(info, &fi->nvlog); + break; + case switchtec_ioctl_part_vendor0: + set_fw_info_part(info, &fi->vendor[0]); + break; + case switchtec_ioctl_part_vendor1: + set_fw_info_part(info, &fi->vendor[1]); + break; + case switchtec_ioctl_part_vendor2: + set_fw_info_part(info, &fi->vendor[2]); + break; + case switchtec_ioctl_part_vendor3: + set_fw_info_part(info, &fi->vendor[3]); + break; + case switchtec_ioctl_part_vendor4: + set_fw_info_part(info, &fi->vendor[4]); + break; + case switchtec_ioctl_part_vendor5: + set_fw_info_part(info, &fi->vendor[5]); + break; + case switchtec_ioctl_part_vendor6: + set_fw_info_part(info, &fi->vendor[6]); + break; + case switchtec_ioctl_part_vendor7: + set_fw_info_part(info, &fi->vendor[7]); + break; + default: + return -einval; + } + + return 0; +} + + } else if (stdev->gen == switchtec_gen4) { + ret = flash_part_info_gen4(stdev, &info); + if (ret) + return ret; diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h --- a/include/linux/switchtec.h +++ b/include/linux/switchtec.h +enum { + switchtec_gen4_map0_running = 0x00, + switchtec_gen4_map1_running = 0x01, + switchtec_gen4_key0_running = 0x02, + switchtec_gen4_key1_running = 0x03, + switchtec_gen4_bl2_0_running = 0x04, + switchtec_gen4_bl2_1_running = 0x05, + switchtec_gen4_cfg0_running = 0x06, + switchtec_gen4_cfg1_running = 0x07, + switchtec_gen4_img0_running = 0x08, + switchtec_gen4_img1_running = 0x09, +}; + +enum { + switchtec_gen4_key0_active = 0, + switchtec_gen4_key1_active = 1, + switchtec_gen4_bl2_0_active = 0, + switchtec_gen4_bl2_1_active = 1, + switchtec_gen4_cfg0_active = 0, + switchtec_gen4_cfg1_active = 1, + switchtec_gen4_img0_active = 0, + switchtec_gen4_img1_active = 1, +}; + +struct flash_info_regs_gen4 { + u32 flash_address; + u32 flash_length; + + struct active_partition_info_gen4 { + unsigned char bl2; + unsigned char cfg; + unsigned char img; + unsigned char key; + } active_flag; + + u32 reserved[3]; + + struct partition_info map0; + struct partition_info map1; + struct partition_info key0; + struct partition_info key1; + struct partition_info bl2_0; + struct partition_info bl2_1; + struct partition_info cfg0; + struct partition_info cfg1; + struct partition_info img0; + struct partition_info img1; + struct partition_info nvlog; + struct partition_info vendor[8]; +}; + + struct flash_info_regs_gen4 gen4; diff --git a/include/uapi/linux/switchtec_ioctl.h b/include/uapi/linux/switchtec_ioctl.h --- a/include/uapi/linux/switchtec_ioctl.h +++ b/include/uapi/linux/switchtec_ioctl.h +#define switchtec_ioctl_part_bl2_0 13 +#define switchtec_ioctl_part_bl2_1 14 +#define switchtec_ioctl_part_map_0 15 +#define switchtec_ioctl_part_map_1 16 +#define switchtec_ioctl_part_key_0 17 +#define switchtec_ioctl_part_key_1 18 + +#define switchtec_num_partitions_gen4 19 | PCI | 4efa1d2e36976d7b26f2e67f4c838330fbc91299 | kelvin cao | include | uapi | linux, switch |
pci: vmd: add two vmd device ids | add new vmd device ids that require the bus restriction mode. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add two vmd device ids | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['vmd'] | ['c'] | 1 | 4 | 0 | --- diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c + {pci_device(pci_vendor_id_intel, 0x467f), + .driver_data = vmd_feat_has_bus_restrictions,}, + {pci_device(pci_vendor_id_intel, 0x4c3d), + .driver_data = vmd_feat_has_bus_restrictions,}, | PCI | db51b4c85fb756f33617c1d29643e57be9bd2f1d | sushma kalakota | drivers | pci | controller |
thunderbolt: make tb_find_port() available to other files | we will be needing this when adding initial usb4 support so make it available to other files in the driver as well. we also rename it to tb_switch_find_port() to follow conventions used in switch.c. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c', 'h'] | 3 | 22 | 20 | --- diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c +/** + * tb_switch_find_port() - return the first port of @type on @sw or null + * @sw: switch to find the port from + * @type: port type to look for + */ +struct tb_port *tb_switch_find_port(struct tb_switch *sw, + enum tb_port_type type) +{ + struct tb_port *port; + + tb_switch_for_each_port(sw, port) { + if (port->config.type == type) + return port; + } + + return null; +} + diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c -/** - * tb_find_port() - return the first port of @type on @sw or null - * @sw: switch to find the port from - * @type: port type to look for - */ -static struct tb_port *tb_find_port(struct tb_switch *sw, - enum tb_port_type type) -{ - struct tb_port *port; - - tb_switch_for_each_port(sw, port) { - if (port->config.type == type) - return port; - } - - return null; -} - - up = tb_find_port(sw, tb_type_pcie_up); + up = tb_switch_find_port(sw, tb_type_pcie_up); - nhi_port = tb_find_port(tb->root_switch, tb_type_nhi); + nhi_port = tb_switch_find_port(tb->root_switch, tb_type_nhi); diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h +struct tb_port *tb_switch_find_port(struct tb_switch *sw, + enum tb_port_type type); | Thunderbolt | 386e5e29d81cd088a1111277a18f13d571a6cea5 | mika westerberg | drivers | thunderbolt | |
thunderbolt: call tb_eeprom_get_drom_offset() from tb_eeprom_read_n() | we are going to re-use tb_drom_read() for usb4 drom reading as well. usb4 has separate router operations for this which does not need the drom_offset. therefore we move call to tb_eeprom_get_drom_offset() into tb_eeprom_read_n() where it is needed. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c'] | 1 | 43 | 45 | --- diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c --- a/drivers/thunderbolt/eeprom.c +++ b/drivers/thunderbolt/eeprom.c +/** + * tb_eeprom_get_drom_offset - get drom offset within eeprom + */ +static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset) +{ + struct tb_cap_plug_events cap; + int res; + + if (!sw->cap_plug_events) { + tb_sw_warn(sw, "no tb_cap_plug_events, cannot read eeprom "); + return -enodev; + } + res = tb_sw_read(sw, &cap, tb_cfg_switch, sw->cap_plug_events, + sizeof(cap) / 4); + if (res) + return res; + + if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) { + tb_sw_warn(sw, "no nvm "); + return -enodev; + } + + if (cap.drom_offset > 0xffff) { + tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x ", + cap.drom_offset); + return -enxio; + } + *offset = cap.drom_offset; + return 0; +} + + u16 drom_offset; + + res = tb_eeprom_get_drom_offset(sw, &drom_offset); + if (res) + return res; + + offset += drom_offset; + -/** - * tb_eeprom_get_drom_offset - get drom offset within eeprom - */ -static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset) -{ - struct tb_cap_plug_events cap; - int res; - if (!sw->cap_plug_events) { - tb_sw_warn(sw, "no tb_cap_plug_events, cannot read eeprom "); - return -enosys; - } - res = tb_sw_read(sw, &cap, tb_cfg_switch, sw->cap_plug_events, - sizeof(cap) / 4); - if (res) - return res; - - if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) { - tb_sw_warn(sw, "no nvm "); - return -enosys; - } - - if (cap.drom_offset > 0xffff) { - tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x ", - cap.drom_offset); - return -enxio; - } - *offset = cap.drom_offset; - return 0; -} - - u16 drom_offset; - int res = tb_eeprom_get_drom_offset(sw, &drom_offset); - if (res) - return res; - - if (drom_offset == 0) - return -enodev; + int res; - res = tb_eeprom_read_n(sw, drom_offset, data, 9); + res = tb_eeprom_read_n(sw, 0, data, 9); - u16 drom_offset; - res = tb_eeprom_get_drom_offset(sw, &drom_offset); - if (res) - return res; - - res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2); + res = tb_eeprom_read_n(sw, 14, (u8 *) &size, 2); - res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size); + res = tb_eeprom_read_n(sw, 0, sw->drom, size); | Thunderbolt | 4deb200d34a779aa336ddcd213e39eb6104eb78a | mika westerberg | drivers | thunderbolt | |
thunderbolt: populate pg field in hot plug acknowledgment packet | usb4 1.0 section 6.4.2.7 specifies a new field (pg) in notification packet that is sent as response of hot plug/unplug events. this field tells whether the acknowledgment is for plug or unplug event. this needs to be set accordingly in order the router to send further hot plug notifications. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c', 'h'] | 4 | 20 | 11 | --- diff --git a/drivers/thunderbolt/ctl.c b/drivers/thunderbolt/ctl.c --- a/drivers/thunderbolt/ctl.c +++ b/drivers/thunderbolt/ctl.c - * tb_cfg_error() - send error packet + * tb_cfg_ack_plug() - ack hot plug/unplug event + * @ctl: control channel to use + * @route: router that originated the event + * @port: port where the hot plug/unplug happened + * @unplug: ack hot plug or unplug - * return: returns 0 on success or an error code on failure. + * call this as response for hot plug/unplug event to ack it. + * returns %0 on success or an error code on failure. -int tb_cfg_error(struct tb_ctl *ctl, u64 route, u32 port, - enum tb_cfg_error error) +int tb_cfg_ack_plug(struct tb_ctl *ctl, u64 route, u32 port, bool unplug) - .error = error, + .error = tb_cfg_error_ack_plug_event, + .pg = unplug ? tb_cfg_error_pg_hot_unplug + : tb_cfg_error_pg_hot_plug, - tb_ctl_dbg(ctl, "resetting error on %llx:%x. ", route, port); + tb_ctl_dbg(ctl, "acking hot %splug event on %llx:%x ", + unplug ? "un" : "", route, port); diff --git a/drivers/thunderbolt/ctl.h b/drivers/thunderbolt/ctl.h --- a/drivers/thunderbolt/ctl.h +++ b/drivers/thunderbolt/ctl.h -int tb_cfg_error(struct tb_ctl *ctl, u64 route, u32 port, - enum tb_cfg_error error); +int tb_cfg_ack_plug(struct tb_ctl *ctl, u64 route, u32 port, bool unplug); diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c - if (tb_cfg_error(tb->ctl, route, pkg->port, - tb_cfg_error_ack_plug_event)) { + if (tb_cfg_ack_plug(tb->ctl, route, pkg->port, pkg->unplug)) { diff --git a/drivers/thunderbolt/tb_msgs.h b/drivers/thunderbolt/tb_msgs.h --- a/drivers/thunderbolt/tb_msgs.h +++ b/drivers/thunderbolt/tb_msgs.h - u32 zero3:16; + u32 zero3:14; + u32 pg:2; +#define tb_cfg_error_pg_hot_plug 0x2 +#define tb_cfg_error_pg_hot_unplug 0x3 + | Thunderbolt | 210e9f56e9e12472741b949950f9efcebf350750 | mika westerberg | drivers | thunderbolt | |
thunderbolt: add initial support for usb4 | usb4 is the public specification based on thunderbolt 3 protocol. there are some differences in register layouts and flows. in addition to pcie and dp tunneling, usb4 supports tunneling of usb 3.x. usb4 is also backward compatible with thunderbolt 3 (and older generations but the spec only talks about 3rd generation). usb4 compliant devices can be identified by checking usb4 version field in router configuration space. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c', 'makefile', 'h'] | 11 | 1,158 | 117 | - pcie tunneling - display port tunneling - host and device nvm firmware upgrade - p2p networking --- diff --git a/drivers/thunderbolt/makefile b/drivers/thunderbolt/makefile --- a/drivers/thunderbolt/makefile +++ b/drivers/thunderbolt/makefile -thunderbolt-objs += domain.o dma_port.o icm.o property.o xdomain.o lc.o +thunderbolt-objs += domain.o dma_port.o icm.o property.o xdomain.o lc.o usb4.o diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c --- a/drivers/thunderbolt/eeprom.c +++ b/drivers/thunderbolt/eeprom.c +static int usb4_copy_host_drom(struct tb_switch *sw, u16 *size) +{ + int ret; + + ret = usb4_switch_drom_read(sw, 14, size, sizeof(*size)); + if (ret) + return ret; + + /* size includes crc8 + uid + crc32 */ + *size += 1 + 8 + 4; + sw->drom = kzalloc(*size, gfp_kernel); + if (!sw->drom) + return -enomem; + + ret = usb4_switch_drom_read(sw, 0, sw->drom, *size); + if (ret) { + kfree(sw->drom); + sw->drom = null; + } + + return ret; +} + +static int tb_drom_read_n(struct tb_switch *sw, u16 offset, u8 *val, + size_t count) +{ + if (tb_switch_is_usb4(sw)) + return usb4_switch_drom_read(sw, offset, val, count); + return tb_eeprom_read_n(sw, offset, val, count); +} + - * the root switch contains only a dummy drom (header only, - * no entries). hardcode the configuration here. + * usb4 hosts may support reading drom through router + * operations. - tb_drom_read_uid_only(sw, &sw->uid); + if (tb_switch_is_usb4(sw)) { + usb4_switch_read_uid(sw, &sw->uid); + if (!usb4_copy_host_drom(sw, &size)) + goto parse; + } else { + /* + * the root switch contains only a dummy drom + * (header only, no entries). hardcode the + * configuration here. + */ + tb_drom_read_uid_only(sw, &sw->uid); + } + - res = tb_eeprom_read_n(sw, 14, (u8 *) &size, 2); + res = tb_drom_read_n(sw, 14, (u8 *) &size, 2); - res = tb_eeprom_read_n(sw, 0, sw->drom, size); + res = tb_drom_read_n(sw, 0, sw->drom, size); diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c + /* any usb4 compliant host */ + { pci_device_class(pci_class_serial_usb_usb4, ~0) }, + diff --git a/drivers/thunderbolt/nhi.h b/drivers/thunderbolt/nhi.h --- a/drivers/thunderbolt/nhi.h +++ b/drivers/thunderbolt/nhi.h +#define pci_class_serial_usb_usb4 0x0c0340 + diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c + if (tb_switch_is_usb4(sw)) + return usb4_switch_nvm_write(sw, 0, buf, image_size); -static int nvm_authenticate_host(struct tb_switch *sw) +static int nvm_authenticate_host_dma_port(struct tb_switch *sw) -static int nvm_authenticate_device(struct tb_switch *sw) +static int nvm_authenticate_device_dma_port(struct tb_switch *sw) +static void nvm_authenticate_start_dma_port(struct tb_switch *sw) +{ + struct pci_dev *root_port; + + /* + * during host router nvm upgrade we should not allow root port to + * go into d3cold because some root ports cannot trigger pme + * itself. to be on the safe side keep the root port in d0 during + * the whole upgrade process. + */ + root_port = pci_find_pcie_root_port(sw->tb->nhi->pdev); + if (root_port) + pm_runtime_get_noresume(&root_port->dev); +} + +static void nvm_authenticate_complete_dma_port(struct tb_switch *sw) +{ + struct pci_dev *root_port; + + root_port = pci_find_pcie_root_port(sw->tb->nhi->pdev); + if (root_port) + pm_runtime_put(&root_port->dev); +} + +static inline bool nvm_readable(struct tb_switch *sw) +{ + if (tb_switch_is_usb4(sw)) { + /* + * usb4 devices must support nvm operations but it is + * optional for hosts. therefore we query the nvm sector + * size here and if it is supported assume nvm + * operations are implemented. + */ + return usb4_switch_nvm_sector_size(sw) > 0; + } + + /* thunderbolt 2 and 3 devices support nvm through dma port */ + return !!sw->dma_port; +} + +static inline bool nvm_upgradeable(struct tb_switch *sw) +{ + if (sw->no_nvm_upgrade) + return false; + return nvm_readable(sw); +} + +static inline int nvm_read(struct tb_switch *sw, unsigned int address, + void *buf, size_t size) +{ + if (tb_switch_is_usb4(sw)) + return usb4_switch_nvm_read(sw, address, buf, size); + return dma_port_flash_read(sw->dma_port, address, buf, size); +} + +static int nvm_authenticate(struct tb_switch *sw) +{ + int ret; + + if (tb_switch_is_usb4(sw)) + return usb4_switch_nvm_authenticate(sw); + + if (!tb_route(sw)) { + nvm_authenticate_start_dma_port(sw); + ret = nvm_authenticate_host_dma_port(sw); + } else { + ret = nvm_authenticate_device_dma_port(sw); + } + + return ret; +} + - ret = dma_port_flash_read(sw->dma_port, offset, val, bytes); + ret = nvm_read(sw, offset, val, bytes); - if (!sw->dma_port) + if (!nvm_readable(sw)) + /* + * the nvm format of non-intel hardware is not known so + * currently restrict nvm upgrade for intel hardware. we may + * relax this in the future when we learn other nvm formats. + */ + if (sw->config.vendor_id != pci_vendor_id_intel) { + dev_info(&sw->dev, + "nvm format of vendor %#x is not known, disabling nvm upgrade ", + sw->config.vendor_id); + return 0; + } + - ret = dma_port_flash_read(sw->dma_port, nvm_flash_size, &val, - sizeof(val)); + ret = nvm_read(sw, nvm_flash_size, &val, sizeof(val)); - ret = dma_port_flash_read(sw->dma_port, nvm_version, &val, - sizeof(val)); + ret = nvm_read(sw, nvm_version, &val, sizeof(val)); +/** + * tb_port_unlock() - unlock downstream port + * @port: port to unlock + * + * needed for usb4 but can be called for any cio/usb4 ports. makes the + * downstream router accessible for cm. + */ +int tb_port_unlock(struct tb_port *port) +{ + if (tb_switch_is_icm(port->sw)) + return 0; + if (!tb_port_is_null(port)) + return -einval; + if (tb_switch_is_usb4(port->sw)) + return usb4_port_unlock(port); + return 0; +} + + + cap = tb_port_find_cap(port, tb_port_cap_usb4); + if (cap > 0) + port->cap_usb4 = cap; -static void tb_dump_switch(struct tb *tb, struct tb_regs_switch_header *sw) +static const char *tb_switch_generation_name(const struct tb_switch *sw) +{ + switch (sw->generation) { + case 1: + return "thunderbolt 1"; + case 2: + return "thunderbolt 2"; + case 3: + return "thunderbolt 3"; + case 4: + return "usb4"; + default: + return "unknown"; + } +} + +static void tb_dump_switch(const struct tb *tb, const struct tb_switch *sw) - tb_dbg(tb, " switch: %x:%x (revision: %d, tb version: %d) ", - sw->vendor_id, sw->device_id, sw->revision, - sw->thunderbolt_version); - tb_dbg(tb, " max port number: %d ", sw->max_port_number); + const struct tb_regs_switch_header *regs = &sw->config; + + tb_dbg(tb, " %s switch: %x:%x (revision: %d, tb version: %d) ", + tb_switch_generation_name(sw), regs->vendor_id, regs->device_id, + regs->revision, regs->thunderbolt_version); + tb_dbg(tb, " max port number: %d ", regs->max_port_number); - sw->upstream_port_number, sw->depth, - (((u64) sw->route_hi) << 32) | sw->route_lo, - sw->enabled, sw->plug_events_delay); + regs->upstream_port_number, regs->depth, + (((u64) regs->route_hi) << 32) | regs->route_lo, + regs->enabled, regs->plug_events_delay); - sw->__unknown1, sw->__unknown4); + regs->__unknown1, regs->__unknown4); + /* plug events are always enabled in usb4 */ + if (tb_switch_is_usb4(sw)) + return 0; + -static void nvm_authenticate_start(struct tb_switch *sw) -{ - struct pci_dev *root_port; - - /* - * during host router nvm upgrade we should not allow root port to - * go into d3cold because some root ports cannot trigger pme - * itself. to be on the safe side keep the root port in d0 during - * the whole upgrade process. - */ - root_port = pci_find_pcie_root_port(sw->tb->nhi->pdev); - if (root_port) - pm_runtime_get_noresume(&root_port->dev); -} - -static void nvm_authenticate_complete(struct tb_switch *sw) -{ - struct pci_dev *root_port; - - root_port = pci_find_pcie_root_port(sw->tb->nhi->pdev); - if (root_port) - pm_runtime_put(&root_port->dev); -} - - - if (!tb_route(sw)) { - /* - * keep root port from suspending as long as the - * nvm upgrade process is running. - */ - nvm_authenticate_start(sw); - ret = nvm_authenticate_host(sw); - } else { - ret = nvm_authenticate_device(sw); - } + ret = nvm_authenticate(sw); - if (sw->dma_port && !sw->no_nvm_upgrade) + if (nvm_upgradeable(sw)) - if (sw->dma_port) + if (nvm_readable(sw)) + if (tb_switch_is_usb4(sw)) + return 4; + +static bool tb_switch_exceeds_max_depth(const struct tb_switch *sw, int depth) +{ + int max_depth; + + if (tb_switch_is_usb4(sw) || + (sw->tb->root_switch && tb_switch_is_usb4(sw->tb->root_switch))) + max_depth = usb4_switch_max_depth; + else + max_depth = tb_switch_max_depth; + + return depth > max_depth; +} + - /* make sure we do not exceed maximum topology limit */ + /* unlock the downstream port so we can access the switch below */ + if (route) { + struct tb_switch *parent_sw = tb_to_switch(parent); + struct tb_port *down; + + down = tb_port_at(route, parent_sw); + tb_port_unlock(down); + } + - if (depth > tb_switch_max_depth) - return err_ptr(-eaddrnotavail); + sw->generation = tb_switch_get_generation(sw); + - tb_dump_switch(tb, &sw->config); + tb_dump_switch(tb, sw); + /* make sure we do not exceed maximum topology limit */ + if (tb_switch_exceeds_max_depth(sw, depth)) + return err_ptr(-eaddrnotavail); + - sw->generation = tb_switch_get_generation(sw); - - if (ret < 0) { - tb_sw_warn(sw, "cannot find tb_vse_cap_plug_events aborting "); - goto err_free_sw_ports; - } - sw->cap_plug_events = ret; + if (ret > 0) + sw->cap_plug_events = ret; - * connection manager to use. + * connection manager to use. can be called to the switch again after + * resume from low power states to re-initialize it. - tb_dbg(tb, "initializing switch at %#llx (depth: %d, up port: %d) ", - route, tb_route_length(route), sw->config.upstream_port_number); - if (sw->config.vendor_id != pci_vendor_id_intel) - tb_sw_warn(sw, "unknown switch vendor id %#x ", - sw->config.vendor_id); + tb_dbg(tb, "%s switch at %#llx (depth: %d, up port: %d) ", + sw->config.enabled ? "restoring " : "initializing", route, + tb_route_length(route), sw->config.upstream_port_number); - /* upload configuration */ - ret = tb_sw_write(sw, 1 + (u32 *)&sw->config, tb_cfg_switch, 1, 3); - if (ret) - return ret; + if (tb_switch_is_usb4(sw)) { + /* + * for usb4 devices, we need to program the cm version + * accordingly so that it knows to expose all the + * additional capabilities. + */ + sw->config.cmuv = usb4_version_1_0; + + /* enumerate the switch */ + ret = tb_sw_write(sw, (u32 *)&sw->config + 1, tb_cfg_switch, + router_cs_1, 4); + if (ret) + return ret; - ret = tb_lc_configure_link(sw); + ret = usb4_switch_setup(sw); + if (ret) + return ret; + + ret = usb4_switch_configure_link(sw); + } else { + if (sw->config.vendor_id != pci_vendor_id_intel) + tb_sw_warn(sw, "unknown switch vendor id %#x ", + sw->config.vendor_id); + + if (!sw->cap_plug_events) { + tb_sw_warn(sw, "cannot find tb_vse_cap_plug_events aborting "); + return -enodev; + } + + /* enumerate the switch */ + ret = tb_sw_write(sw, (u32 *)&sw->config + 1, tb_cfg_switch, + router_cs_1, 3); + if (ret) + return ret; + + ret = tb_lc_configure_link(sw); + } + bool uid = false; - /* - * the newer controllers include fused uuid as part of link - * controller specific registers - */ - ret = tb_lc_read_uuid(sw, uuid); - if (ret) { + if (tb_switch_is_usb4(sw)) { + ret = usb4_switch_read_uid(sw, &sw->uid); + if (ret) + return ret; + uid = true; + } else { + /* + * the newer controllers include fused uuid as part of + * link controller specific registers + */ + ret = tb_lc_read_uuid(sw, uuid); + if (ret) { + if (ret != -einval) + return ret; + uid = true; + } + } + + if (uid) { - nvm_authenticate_complete(sw); + nvm_authenticate_complete_dma_port(sw); - nvm_authenticate_complete(sw); + nvm_authenticate_complete_dma_port(sw); + if (tb_switch_is_usb4(sw)) + return usb4_switch_lane_bonding_possible(sw); - tb_lc_unconfigure_link(sw); + + if (tb_switch_is_usb4(sw)) + usb4_switch_unconfigure_link(sw); + else + tb_lc_unconfigure_link(sw); - err = tb_drom_read_uid_only(sw, &uid); + if (tb_switch_is_usb4(sw)) + err = usb4_switch_read_uid(sw, &uid); + else + err = tb_drom_read_uid_only(sw, &uid); - /* upload configuration */ - err = tb_sw_write(sw, 1 + (u32 *) &sw->config, tb_cfg_switch, 1, 3); - if (err) - return err; - - err = tb_lc_configure_link(sw); - if (err) - return err; - - err = tb_plug_events_active(sw, true); + err = tb_switch_configure(sw); - } else if (tb_port_has_remote(port)) { - if (tb_switch_resume(port->remote->sw)) { + } else if (tb_port_has_remote(port) || port->xdomain) { + /* + * always unlock the port so the downstream + * switch/domain is accessible. + */ + if (tb_port_unlock(port)) + tb_port_warn(port, "failed to unlock port "); + if (port->remote && tb_switch_resume(port->remote->sw)) { - tb_lc_set_sleep(sw); + if (tb_switch_is_usb4(sw)) + usb4_switch_set_sleep(sw); + else + tb_lc_set_sleep(sw); + if (tb_switch_is_usb4(sw)) + return usb4_switch_query_dp_resource(sw, in); + if (tb_switch_is_usb4(sw)) + return usb4_switch_alloc_dp_resource(sw, in); - if (tb_lc_dp_sink_dealloc(sw, in)) { + int ret; + + if (tb_switch_is_usb4(sw)) + ret = usb4_switch_dealloc_dp_resource(sw, in); + else + ret = tb_lc_dp_sink_dealloc(sw, in); + + if (ret) - } diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c + struct tb_port *down = null; + - * hierarchy, do mapping here for root switch downstream pcie - * ports. + * hierarchy, do mapping here for switch downstream pcie ports. - if (!tb_route(sw)) { + if (tb_switch_is_usb4(sw)) { + down = usb4_switch_map_pcie_down(sw, port); + } else if (!tb_route(sw)) { - if (warn_on(!tb_port_is_pcie_down(&sw->ports[index]))) + + down = &sw->ports[index]; + } + + if (down) { + if (warn_on(!tb_port_is_pcie_down(down))) - if (warn_on(tb_pci_port_is_enabled(&sw->ports[index]))) + if (warn_on(tb_pci_port_is_enabled(down))) - return &sw->ports[index]; + return down; diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h +#define usb4_switch_max_depth 5 + * @cap_usb4: offset to the usb4 port capability (%0 if not present) + int cap_usb4; +/** + * tb_switch_is_usb4() - is the switch usb4 compliant + * @sw: switch to check + * + * returns true if the @sw is usb4 compliant router, false otherwise. + */ +static inline bool tb_switch_is_usb4(const struct tb_switch *sw) +{ + return sw->config.thunderbolt_version == usb4_version_1_0; +} + +int tb_port_unlock(struct tb_port *port); +int usb4_switch_setup(struct tb_switch *sw); +int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid); +int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, + size_t size); +int usb4_switch_configure_link(struct tb_switch *sw); +void usb4_switch_unconfigure_link(struct tb_switch *sw); +bool usb4_switch_lane_bonding_possible(struct tb_switch *sw); +int usb4_switch_set_sleep(struct tb_switch *sw); +int usb4_switch_nvm_sector_size(struct tb_switch *sw); +int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, + size_t size); +int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, + const void *buf, size_t size); +int usb4_switch_nvm_authenticate(struct tb_switch *sw); +bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in); +int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in); +int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in); +struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, + const struct tb_port *port); + +int usb4_port_unlock(struct tb_port *port); diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h + tb_port_cap_usb4 = 0x06, - u32 __unknown4:16; + u32 cmuv:8; + u32 __unknown4:8; +/* usb4 version 1.0 */ +#define usb4_version_1_0 0x20 + +#define router_cs_1 0x01 +#define router_cs_4 0x04 +#define router_cs_5 0x05 +#define router_cs_5_slp bit(0) +#define router_cs_5_c3s bit(23) +#define router_cs_5_pto bit(24) +#define router_cs_5_hco bit(26) +#define router_cs_5_cv bit(31) +#define router_cs_6 0x06 +#define router_cs_6_slpr bit(0) +#define router_cs_6_tns bit(1) +#define router_cs_6_hci bit(18) +#define router_cs_6_cr bit(25) +#define router_cs_7 0x07 +#define router_cs_9 0x09 +#define router_cs_25 0x19 +#define router_cs_26 0x1a +#define router_cs_26_status_mask genmask(29, 24) +#define router_cs_26_status_shift 24 +#define router_cs_26_ons bit(30) +#define router_cs_26_ov bit(31) + +#define adp_cs_4_lck bit(31) +/* usb4 port registers */ +#define port_cs_18 0x12 +#define port_cs_18_be bit(8) +#define port_cs_19 0x13 +#define port_cs_19_pc bit(3) + diff --git a/drivers/thunderbolt/tunnel.c b/drivers/thunderbolt/tunnel.c --- a/drivers/thunderbolt/tunnel.c +++ b/drivers/thunderbolt/tunnel.c +static bool tb_dp_is_usb4(const struct tb_switch *sw) +{ + /* titan ridge dp adapters need the same treatment as usb4 */ + return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw); +} + - if (!tb_switch_is_titan_ridge(in->sw) || - !tb_switch_is_titan_ridge(out->sw)) + if (!tb_dp_is_usb4(in->sw) || !tb_dp_is_usb4(out->sw)) - if (tb_switch_is_titan_ridge(sw)) { + if (tb_dp_is_usb4(sw)) { diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c --- /dev/null +++ b/drivers/thunderbolt/usb4.c +// spdx-license-identifier: gpl-2.0 +/* + * usb4 specific functionality + * + * copyright (c) 2019, intel corporation + * authors: mika westerberg <mika.westerberg@linux.intel.com> + * rajmohan mani <rajmohan.mani@intel.com> + */ + +#include <linux/delay.h> +#include <linux/ktime.h> + +#include "tb.h" + +#define usb4_data_dwords 16 +#define usb4_data_retries 3 + +enum usb4_switch_op { + usb4_switch_op_query_dp_resource = 0x10, + usb4_switch_op_alloc_dp_resource = 0x11, + usb4_switch_op_dealloc_dp_resource = 0x12, + usb4_switch_op_nvm_write = 0x20, + usb4_switch_op_nvm_auth = 0x21, + usb4_switch_op_nvm_read = 0x22, + usb4_switch_op_nvm_set_offset = 0x23, + usb4_switch_op_drom_read = 0x24, + usb4_switch_op_nvm_sector_size = 0x25, +}; + +#define usb4_nvm_read_offset_mask genmask(23, 2) +#define usb4_nvm_read_offset_shift 2 +#define usb4_nvm_read_length_mask genmask(27, 24) +#define usb4_nvm_read_length_shift 24 + +#define usb4_nvm_set_offset_mask usb4_nvm_read_offset_mask +#define usb4_nvm_set_offset_shift usb4_nvm_read_offset_shift + +#define usb4_drom_address_mask genmask(14, 2) +#define usb4_drom_address_shift 2 +#define usb4_drom_size_mask genmask(19, 15) +#define usb4_drom_size_shift 15 + +#define usb4_nvm_sector_size_mask genmask(23, 0) + +typedef int (*read_block_fn)(struct tb_switch *, unsigned int, void *, size_t); +typedef int (*write_block_fn)(struct tb_switch *, const void *, size_t); + +static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit, + u32 value, int timeout_msec) +{ + ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); + + do { + u32 val; + int ret; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, offset, 1); + if (ret) + return ret; + + if ((val & bit) == value) + return 0; + + usleep_range(50, 100); + } while (ktime_before(ktime_get(), timeout)); + + return -etimedout; +} + +static int usb4_switch_op_read_data(struct tb_switch *sw, void *data, + size_t dwords) +{ + if (dwords > usb4_data_dwords) + return -einval; + + return tb_sw_read(sw, data, tb_cfg_switch, router_cs_9, dwords); +} + +static int usb4_switch_op_write_data(struct tb_switch *sw, const void *data, + size_t dwords) +{ + if (dwords > usb4_data_dwords) + return -einval; + + return tb_sw_write(sw, data, tb_cfg_switch, router_cs_9, dwords); +} + +static int usb4_switch_op_read_metadata(struct tb_switch *sw, u32 *metadata) +{ + return tb_sw_read(sw, metadata, tb_cfg_switch, router_cs_25, 1); +} + +static int usb4_switch_op_write_metadata(struct tb_switch *sw, u32 metadata) +{ + return tb_sw_write(sw, &metadata, tb_cfg_switch, router_cs_25, 1); +} + +static int usb4_switch_do_read_data(struct tb_switch *sw, u16 address, + void *buf, size_t size, read_block_fn read_block) +{ + unsigned int retries = usb4_data_retries; + unsigned int offset; + + offset = address & 3; + address = address & ~3; + + do { + size_t nbytes = min_t(size_t, size, usb4_data_dwords * 4); + unsigned int dwaddress, dwords; + u8 data[usb4_data_dwords * 4]; + int ret; + + dwaddress = address / 4; + dwords = align(nbytes, 4) / 4; + + ret = read_block(sw, dwaddress, data, dwords); + if (ret) { + if (ret == -etimedout) { + if (retries--) + continue; + ret = -eio; + } + return ret; + } + + memcpy(buf, data + offset, nbytes); + + size -= nbytes; + address += nbytes; + buf += nbytes; + } while (size > 0); + + return 0; +} + +static int usb4_switch_do_write_data(struct tb_switch *sw, u16 address, + const void *buf, size_t size, write_block_fn write_next_block) +{ + unsigned int retries = usb4_data_retries; + unsigned int offset; + + offset = address & 3; + address = address & ~3; + + do { + u32 nbytes = min_t(u32, size, usb4_data_dwords * 4); + u8 data[usb4_data_dwords * 4]; + int ret; + + memcpy(data + offset, buf, nbytes); + + ret = write_next_block(sw, data, nbytes / 4); + if (ret) { + if (ret == -etimedout) { + if (retries--) + continue; + ret = -eio; + } + return ret; + } + + size -= nbytes; + address += nbytes; + buf += nbytes; + } while (size > 0); + + return 0; +} + +static int usb4_switch_op(struct tb_switch *sw, u16 opcode, u8 *status) +{ + u32 val; + int ret; + + val = opcode | router_cs_26_ov; + ret = tb_sw_write(sw, &val, tb_cfg_switch, router_cs_26, 1); + if (ret) + return ret; + + ret = usb4_switch_wait_for_bit(sw, router_cs_26, router_cs_26_ov, 0, 500); + if (ret) + return ret; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, router_cs_26, 1); + if (val & router_cs_26_ons) + return -eopnotsupp; + + *status = (val & router_cs_26_status_mask) >> router_cs_26_status_shift; + return 0; +} + +/** + * usb4_switch_setup() - additional setup for usb4 device + * @sw: usb4 router to setup + * + * usb4 routers need additional settings in order to enable all the + * tunneling. this function enables usb and pcie tunneling if it can be + * enabled (e.g the parent switch also supports them). if usb tunneling + * is not available for some reason (like that there is thunderbolt 3 + * switch upstream) then the internal xhci controller is enabled + * instead. + */ +int usb4_switch_setup(struct tb_switch *sw) +{ + struct tb_switch *parent; + bool tbt3, xhci; + u32 val = 0; + int ret; + + if (!tb_route(sw)) + return 0; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, router_cs_6, 1); + if (ret) + return ret; + + xhci = val & router_cs_6_hci; + tbt3 = !(val & router_cs_6_tns); + + tb_sw_dbg(sw, "tbt3 support: %s, xhci: %s ", + tbt3 ? "yes" : "no", xhci ? "yes" : "no"); + + ret = tb_sw_read(sw, &val, tb_cfg_switch, router_cs_5, 1); + if (ret) + return ret; + + parent = tb_switch_parent(sw); + + /* only enable pcie tunneling if the parent router supports it */ + if (tb_switch_find_port(parent, tb_type_pcie_down)) { + val |= router_cs_5_pto; + /* xhci can be enabled if pcie tunneling is supported */ + if (xhci & router_cs_6_hci) + val |= router_cs_5_hco; + } + + /* tbt3 supported by the cm */ + val |= router_cs_5_c3s; + /* tunneling configuration is ready now */ + val |= router_cs_5_cv; + + ret = tb_sw_write(sw, &val, tb_cfg_switch, router_cs_5, 1); + if (ret) + return ret; + + return usb4_switch_wait_for_bit(sw, router_cs_6, router_cs_6_cr, + router_cs_6_cr, 50); +} + +/** + * usb4_switch_read_uid() - read uid from usb4 router + * @sw: usb4 router + * + * reads 64-bit uid from usb4 router config space. + */ +int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid) +{ + return tb_sw_read(sw, uid, tb_cfg_switch, router_cs_7, 2); +} + +static int usb4_switch_drom_read_block(struct tb_switch *sw, + unsigned int dwaddress, void *buf, + size_t dwords) +{ + u8 status = 0; + u32 metadata; + int ret; + + metadata = (dwords << usb4_drom_size_shift) & usb4_drom_size_mask; + metadata |= (dwaddress << usb4_drom_address_shift) & + usb4_drom_address_mask; + + ret = usb4_switch_op_write_metadata(sw, metadata); + if (ret) + return ret; + + ret = usb4_switch_op(sw, usb4_switch_op_drom_read, &status); + if (ret) + return ret; + + if (status) + return -eio; + + return usb4_switch_op_read_data(sw, buf, dwords); +} + +/** + * usb4_switch_drom_read() - read arbitrary bytes from usb4 router drom + * @sw: usb4 router + * + * uses usb4 router operations to read router drom. for devices this + * should always work but for hosts it may return %-eopnotsupp in which + * case the host router does not have drom. + */ +int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, + size_t size) +{ + return usb4_switch_do_read_data(sw, address, buf, size, + usb4_switch_drom_read_block); +} + +static int usb4_set_port_configured(struct tb_port *port, bool configured) +{ + int ret; + u32 val; + + ret = tb_port_read(port, &val, tb_cfg_port, + port->cap_usb4 + port_cs_19, 1); + if (ret) + return ret; + + if (configured) + val |= port_cs_19_pc; + else + val &= ~port_cs_19_pc; + + return tb_port_write(port, &val, tb_cfg_port, + port->cap_usb4 + port_cs_19, 1); +} + +/** + * usb4_switch_configure_link() - set upstream usb4 link configured + * @sw: usb4 router + * + * sets the upstream usb4 link to be configured for power management + * purposes. + */ +int usb4_switch_configure_link(struct tb_switch *sw) +{ + struct tb_port *up; + + if (!tb_route(sw)) + return 0; + + up = tb_upstream_port(sw); + return usb4_set_port_configured(up, true); +} + +/** + * usb4_switch_unconfigure_link() - un-set upstream usb4 link configuration + * @sw: usb4 router + * + * reverse of usb4_switch_configure_link(). + */ +void usb4_switch_unconfigure_link(struct tb_switch *sw) +{ + struct tb_port *up; + + if (sw->is_unplugged || !tb_route(sw)) + return; + + up = tb_upstream_port(sw); + usb4_set_port_configured(up, false); +} + +/** + * usb4_switch_lane_bonding_possible() - are conditions met for lane bonding + * @sw: usb4 router + * + * checks whether conditions are met so that lane bonding can be + * established with the upstream router. call only for device routers. + */ +bool usb4_switch_lane_bonding_possible(struct tb_switch *sw) +{ + struct tb_port *up; + int ret; + u32 val; + + up = tb_upstream_port(sw); + ret = tb_port_read(up, &val, tb_cfg_port, up->cap_usb4 + port_cs_18, 1); + if (ret) + return false; + + return !!(val & port_cs_18_be); +} + +/** + * usb4_switch_set_sleep() - prepare the router to enter sleep + * @sw: usb4 router + * + * enables wakes and sets sleep bit for the router. returns when the + * router sleep ready bit has been asserted. + */ +int usb4_switch_set_sleep(struct tb_switch *sw) +{ + int ret; + u32 val; + + /* set sleep bit and wait for sleep ready to be asserted */ + ret = tb_sw_read(sw, &val, tb_cfg_switch, router_cs_5, 1); + if (ret) + return ret; + + val |= router_cs_5_slp; + + ret = tb_sw_write(sw, &val, tb_cfg_switch, router_cs_5, 1); + if (ret) + return ret; + + return usb4_switch_wait_for_bit(sw, router_cs_6, router_cs_6_slpr, + router_cs_6_slpr, 500); +} + +/** + * usb4_switch_nvm_sector_size() - return router nvm sector size + * @sw: usb4 router + * + * if the router supports nvm operations this function returns the nvm + * sector size in bytes. if nvm operations are not supported returns + * %-eopnotsupp. + */ +int usb4_switch_nvm_sector_size(struct tb_switch *sw) +{ + u32 metadata; + u8 status; + int ret; + + ret = usb4_switch_op(sw, usb4_switch_op_nvm_sector_size, &status); + if (ret) + return ret; + + if (status) + return status == 0x2 ? -eopnotsupp : -eio; + + ret = usb4_switch_op_read_metadata(sw, &metadata); + if (ret) + return ret; + + return metadata & usb4_nvm_sector_size_mask; +} + +static int usb4_switch_nvm_read_block(struct tb_switch *sw, + unsigned int dwaddress, void *buf, size_t dwords) +{ + u8 status = 0; + u32 metadata; + int ret; + + metadata = (dwords << usb4_nvm_read_length_shift) & + usb4_nvm_read_length_mask; + metadata |= (dwaddress << usb4_nvm_read_offset_shift) & + usb4_nvm_read_offset_mask; + + ret = usb4_switch_op_write_metadata(sw, metadata); + if (ret) + return ret; + + ret = usb4_switch_op(sw, usb4_switch_op_nvm_read, &status); + if (ret) + return ret; + + if (status) + return -eio; + + return usb4_switch_op_read_data(sw, buf, dwords); +} + +/** + * usb4_switch_nvm_read() - read arbitrary bytes from router nvm + * @sw: usb4 router + * @address: starting address in bytes + * @buf: read data is placed here + * @size: how many bytes to read + * + * reads nvm contents of the router. if nvm is not supported returns + * %-eopnotsupp. + */ +int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, + size_t size) +{ + return usb4_switch_do_read_data(sw, address, buf, size, + usb4_switch_nvm_read_block); +} + +static int usb4_switch_nvm_set_offset(struct tb_switch *sw, + unsigned int address) +{ + u32 metadata, dwaddress; + u8 status = 0; + int ret; + + dwaddress = address / 4; + metadata = (dwaddress << usb4_nvm_set_offset_shift) & + usb4_nvm_set_offset_mask; + + ret = usb4_switch_op_write_metadata(sw, metadata); + if (ret) + return ret; + + ret = usb4_switch_op(sw, usb4_switch_op_nvm_set_offset, &status); + if (ret) + return ret; + + return status ? -eio : 0; +} + +static int usb4_switch_nvm_write_next_block(struct tb_switch *sw, + const void *buf, size_t dwords) +{ + u8 status; + int ret; + + ret = usb4_switch_op_write_data(sw, buf, dwords); + if (ret) + return ret; + + ret = usb4_switch_op(sw, usb4_switch_op_nvm_write, &status); + if (ret) + return ret; + + return status ? -eio : 0; +} + +/** + * usb4_switch_nvm_write() - write to the router nvm + * @sw: usb4 router + * @address: start address where to write in bytes + * @buf: pointer to the data to write + * @size: size of @buf in bytes + * + * writes @buf to the router nvm using usb4 router operations. if nvm + * write is not supported returns %-eopnotsupp. + */ +int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, + const void *buf, size_t size) +{ + int ret; + + ret = usb4_switch_nvm_set_offset(sw, address); + if (ret) + return ret; + + return usb4_switch_do_write_data(sw, address, buf, size, + usb4_switch_nvm_write_next_block); +} + +/** + * usb4_switch_nvm_authenticate() - authenticate new nvm + * @sw: usb4 router + * + * after the new nvm has been written via usb4_switch_nvm_write(), this + * function triggers nvm authentication process. if the authentication + * is successful the router is power cycled and the new nvm starts + * running. in case of failure returns negative errno. + */ +int usb4_switch_nvm_authenticate(struct tb_switch *sw) +{ + u8 status = 0; + int ret; + + ret = usb4_switch_op(sw, usb4_switch_op_nvm_auth, &status); + if (ret) + return ret; + + switch (status) { + case 0x0: + tb_sw_dbg(sw, "nvm authentication successful "); + return 0; + case 0x1: + return -einval; + case 0x2: + return -eagain; + case 0x3: + return -eopnotsupp; + default: + return -eio; + } +} + +/** + * usb4_switch_query_dp_resource() - query availability of dp in resource + * @sw: usb4 router + * @in: dp in adapter + * + * for dp tunneling this function can be used to query availability of + * dp in resource. returns true if the resource is available for dp + * tunneling, false otherwise. + */ +bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in) +{ + u8 status; + int ret; + + ret = usb4_switch_op_write_metadata(sw, in->port); + if (ret) + return false; + + ret = usb4_switch_op(sw, usb4_switch_op_query_dp_resource, &status); + /* + * if dp resource allocation is not supported assume it is + * always available. + */ + if (ret == -eopnotsupp) + return true; + else if (ret) + return false; + + return !status; +} + +/** + * usb4_switch_alloc_dp_resource() - allocate dp in resource + * @sw: usb4 router + * @in: dp in adapter + * + * allocates dp in resource for dp tunneling using usb4 router + * operations. if the resource was allocated returns %0. otherwise + * returns negative errno, in particular %-ebusy if the resource is + * already allocated. + */ +int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in) +{ + u8 status; + int ret; + + ret = usb4_switch_op_write_metadata(sw, in->port); + if (ret) + return ret; + + ret = usb4_switch_op(sw, usb4_switch_op_alloc_dp_resource, &status); + if (ret == -eopnotsupp) + return 0; + else if (ret) + return ret; + + return status ? -ebusy : 0; +} + +/** + * usb4_switch_dealloc_dp_resource() - releases allocated dp in resource + * @sw: usb4 router + * @in: dp in adapter + * + * releases the previously allocated dp in resource. + */ +int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in) +{ + u8 status; + int ret; + + ret = usb4_switch_op_write_metadata(sw, in->port); + if (ret) + return ret; + + ret = usb4_switch_op(sw, usb4_switch_op_dealloc_dp_resource, &status); + if (ret == -eopnotsupp) + return 0; + else if (ret) + return ret; + + return status ? -eio : 0; +} + +static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port) +{ + struct tb_port *p; + int usb4_idx = 0; + + /* assume port is primary */ + tb_switch_for_each_port(sw, p) { + if (!tb_port_is_null(p)) + continue; + if (tb_is_upstream_port(p)) + continue; + if (!p->link_nr) { + if (p == port) + break; + usb4_idx++; + } + } + + return usb4_idx; +} + +/** + * usb4_switch_map_pcie_down() - map usb4 port to a pcie downstream adapter + * @sw: usb4 router + * @port: usb4 port + * + * usb4 routers have direct mapping between usb4 ports and pcie + * downstream adapters where the pcie topology is extended. this + * function returns the corresponding downstream pcie adapter or %null + * if no such mapping was possible. + */ +struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, + const struct tb_port *port) +{ + int usb4_idx = usb4_port_idx(sw, port); + struct tb_port *p; + int pcie_idx = 0; + + /* find pcie down port matching usb4_port */ + tb_switch_for_each_port(sw, p) { + if (!tb_port_is_pcie_down(p)) + continue; + + if (pcie_idx == usb4_idx && !tb_pci_port_is_enabled(p)) + return p; + + pcie_idx++; + } + + return null; +} + +/** + * usb4_port_unlock() - unlock usb4 downstream port + * @port: usb4 port to unlock + * + * unlocks usb4 downstream port so that the connection manager can + * access the router below this port. + */ +int usb4_port_unlock(struct tb_port *port) +{ + int ret; + u32 val; + + ret = tb_port_read(port, &val, tb_cfg_port, adp_cs_4, 1); + if (ret) + return ret; + + val &= ~adp_cs_4_lck; + return tb_port_write(port, &val, tb_cfg_port, adp_cs_4, 1); +} diff --git a/drivers/thunderbolt/xdomain.c b/drivers/thunderbolt/xdomain.c --- a/drivers/thunderbolt/xdomain.c +++ b/drivers/thunderbolt/xdomain.c + struct tb_switch *parent_sw = tb_to_switch(parent); + struct tb_port *down; + + /* make sure the downstream domain is accessible */ + down = tb_port_at(route, parent_sw); + tb_port_unlock(down); | Thunderbolt | b04079837b2094f09e145676eec4b9a56ae8a6aa | mika westerberg | drivers | thunderbolt | |
thunderbolt: update kconfig entries to usb4 | since the driver now supports usb4 which is the standard going forward, update the kconfig entry to mention this and rename the entry from config_thunderbolt to config_usb4 instead to help people to find the correct option if they want to enable usb4. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['kconfig', 'makefile'] | 5 | 14 | 13 | --- diff --git a/drivers/makefile b/drivers/makefile --- a/drivers/makefile +++ b/drivers/makefile -obj-$(config_thunderbolt) += thunderbolt/ +obj-$(config_usb4) += thunderbolt/ diff --git a/drivers/net/kconfig b/drivers/net/kconfig --- a/drivers/net/kconfig +++ b/drivers/net/kconfig -config thunderbolt_net - tristate "networking over thunderbolt cable" - depends on thunderbolt && inet +config usb4_net + tristate "networking over usb4 and thunderbolt cables" + depends on usb4 && inet - select this if you want to create network between two - computers over a thunderbolt cable. the driver supports apple + select this if you want to create network between two computers + over a usb4 and thunderbolt cables. the driver supports apple diff --git a/drivers/net/makefile b/drivers/net/makefile --- a/drivers/net/makefile +++ b/drivers/net/makefile -obj-$(config_thunderbolt_net) += thunderbolt-net.o +obj-$(config_usb4_net) += thunderbolt-net.o diff --git a/drivers/thunderbolt/kconfig b/drivers/thunderbolt/kconfig --- a/drivers/thunderbolt/kconfig +++ b/drivers/thunderbolt/kconfig -menuconfig thunderbolt - tristate "thunderbolt support" +menuconfig usb4 + tristate "unified support for usb4 and thunderbolt" - thunderbolt controller driver. this driver is required if you - want to hotplug thunderbolt devices on apple hardware or on pcs - with intel falcon ridge or newer. + usb4 and thunderbolt driver. usb4 is the public speficiation + based on thunderbolt 3 protocol. this driver is required if + you want to hotplug thunderbolt and usb4 compliant devices on + apple hardware or on pcs with intel falcon ridge or newer. diff --git a/drivers/thunderbolt/makefile b/drivers/thunderbolt/makefile --- a/drivers/thunderbolt/makefile +++ b/drivers/thunderbolt/makefile -obj-${config_thunderbolt} := thunderbolt.o +obj-${config_usb4} := thunderbolt.o | Thunderbolt | 690ac0d20d4022bb3c7d84e0e3760eb40aa8028d | mika westerberg | drivers | net | |
thunderbolt: make tb_switch_find_cap() available to other files | we need to find switch capabilities in order to implement tmu support so make it available to other files as well. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c', 'h'] | 2 | 11 | 1 | --- diff --git a/drivers/thunderbolt/cap.c b/drivers/thunderbolt/cap.c --- a/drivers/thunderbolt/cap.c +++ b/drivers/thunderbolt/cap.c -static int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap) +/** + * tb_switch_find_cap() - find switch capability + * @sw switch to find the capability for + * @cap: capability to look + * + * returns offset to start of capability or %-enoent if no such + * capability was found. negative errno is returned if there was an + * error. + */ +int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap) diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h +int tb_switch_find_cap(struct tb_switch *sw, enum tb_switch_cap cap); | Thunderbolt | aa43a9dcf7fcb71f34689bc63cdfb3464d2bebbb | rajmohan mani | drivers | thunderbolt | |
thunderbolt: add support for time management unit | time management unit (tmu) is included in each usb4 router. it is used to synchronize time across the usb4 fabric. by default when usb4 router is plugged to the domain, its tmu is turned off. this differs from thunderbolt (1, 2 and 3) devices whose tmu is by default configured to bi-directional hifi mode. since time synchronization is needed for proper display port tunneling this means we need to configure the tmu on usb4 compliant devices. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c', 'makefile', 'h'] | 6 | 483 | 1 | --- diff --git a/drivers/thunderbolt/makefile b/drivers/thunderbolt/makefile --- a/drivers/thunderbolt/makefile +++ b/drivers/thunderbolt/makefile -thunderbolt-objs += domain.o dma_port.o icm.o property.o xdomain.o lc.o usb4.o +thunderbolt-objs += domain.o dma_port.o icm.o property.o xdomain.o lc.o tmu.o usb4.o diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c + + ret = tb_switch_tmu_init(sw); + if (ret) + return ret; diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c +static int tb_enable_tmu(struct tb_switch *sw) +{ + int ret; + + /* if it is already enabled in correct mode, don't touch it */ + if (tb_switch_tmu_is_enabled(sw)) + return 0; + + ret = tb_switch_tmu_disable(sw); + if (ret) + return ret; + + ret = tb_switch_tmu_post_time(sw); + if (ret) + return ret; + + return tb_switch_tmu_enable(sw); +} + + if (tb_enable_tmu(sw)) + tb_sw_warn(sw, "failed to enable tmu "); + + tb_switch_tmu_disable(port->remote->sw); + /* enable tmu if it is off */ + tb_switch_tmu_enable(tb->root_switch); + if (tb_enable_tmu(sw)) + tb_sw_warn(sw, "failed to restore tmu configuration "); + diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h +/** + * enum tb_switch_tmu_rate - tmu refresh rate + * @tb_switch_tmu_rate_off: %0 (disable time sync handshake) + * @tb_switch_tmu_rate_hifi: %16 us time interval between successive + * transmission of the delay request tsnos + * (time sync notification ordered set) on a link + * @tb_switch_tmu_rate_normal: %1 ms time interval between successive + * transmission of the delay request tsnos on + * a link + */ +enum tb_switch_tmu_rate { + tb_switch_tmu_rate_off = 0, + tb_switch_tmu_rate_hifi = 16, + tb_switch_tmu_rate_normal = 1000, +}; + +/** + * struct tb_switch_tmu - structure holding switch tmu configuration + * @cap: offset to the tmu capability (%0 if not found) + * @has_ucap: does the switch support uni-directional mode + * @rate: tmu refresh rate related to upstream switch. in case of root + * switch this holds the domain rate. + * @unidirectional: is the tmu in uni-directional or bi-directional mode + * related to upstream switch. don't case for root switch. + */ +struct tb_switch_tmu { + int cap; + bool has_ucap; + enum tb_switch_tmu_rate rate; + bool unidirectional; +}; + + * @tmu: the switch tmu configuration + struct tb_switch_tmu tmu; + * @cap_tmu: offset of the adapter specific tmu capability (%0 if not present) + int cap_tmu; +int tb_switch_tmu_init(struct tb_switch *sw); +int tb_switch_tmu_post_time(struct tb_switch *sw); +int tb_switch_tmu_disable(struct tb_switch *sw); +int tb_switch_tmu_enable(struct tb_switch *sw); + +static inline bool tb_switch_tmu_is_enabled(const struct tb_switch *sw) +{ + return sw->tmu.rate == tb_switch_tmu_rate_hifi && + !sw->tmu.unidirectional; +} + diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h + tb_switch_cap_tmu = 0x03, +/* router tmu configuration */ +#define tmu_rtr_cs_0 0x00 +#define tmu_rtr_cs_0_td bit(27) +#define tmu_rtr_cs_0_ucap bit(30) +#define tmu_rtr_cs_1 0x01 +#define tmu_rtr_cs_1_local_time_ns_mask genmask(31, 16) +#define tmu_rtr_cs_1_local_time_ns_shift 16 +#define tmu_rtr_cs_2 0x02 +#define tmu_rtr_cs_3 0x03 +#define tmu_rtr_cs_3_local_time_ns_mask genmask(15, 0) +#define tmu_rtr_cs_3_ts_packet_interval_mask genmask(31, 16) +#define tmu_rtr_cs_3_ts_packet_interval_shift 16 +#define tmu_rtr_cs_22 0x16 +#define tmu_rtr_cs_24 0x18 + +/* tmu adapter registers */ +#define tmu_adp_cs_3 0x03 +#define tmu_adp_cs_3_udm bit(29) + diff --git a/drivers/thunderbolt/tmu.c b/drivers/thunderbolt/tmu.c --- /dev/null +++ b/drivers/thunderbolt/tmu.c +// spdx-license-identifier: gpl-2.0 +/* + * thunderbolt time management unit (tmu) support + * + * copyright (c) 2019, intel corporation + * authors: mika westerberg <mika.westerberg@linux.intel.com> + * rajmohan mani <rajmohan.mani@intel.com> + */ + +#include <linux/delay.h> + +#include "tb.h" + +static const char *tb_switch_tmu_mode_name(const struct tb_switch *sw) +{ + bool root_switch = !tb_route(sw); + + switch (sw->tmu.rate) { + case tb_switch_tmu_rate_off: + return "off"; + + case tb_switch_tmu_rate_hifi: + /* root switch does not have upstream directionality */ + if (root_switch) + return "hifi"; + if (sw->tmu.unidirectional) + return "uni-directional, hifi"; + return "bi-directional, hifi"; + + case tb_switch_tmu_rate_normal: + if (root_switch) + return "normal"; + return "uni-directional, normal"; + + default: + return "unknown"; + } +} + +static bool tb_switch_tmu_ucap_supported(struct tb_switch *sw) +{ + int ret; + u32 val; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, + sw->tmu.cap + tmu_rtr_cs_0, 1); + if (ret) + return false; + + return !!(val & tmu_rtr_cs_0_ucap); +} + +static int tb_switch_tmu_rate_read(struct tb_switch *sw) +{ + int ret; + u32 val; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, + sw->tmu.cap + tmu_rtr_cs_3, 1); + if (ret) + return ret; + + val >>= tmu_rtr_cs_3_ts_packet_interval_shift; + return val; +} + +static int tb_switch_tmu_rate_write(struct tb_switch *sw, int rate) +{ + int ret; + u32 val; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, + sw->tmu.cap + tmu_rtr_cs_3, 1); + if (ret) + return ret; + + val &= ~tmu_rtr_cs_3_ts_packet_interval_mask; + val |= rate << tmu_rtr_cs_3_ts_packet_interval_shift; + + return tb_sw_write(sw, &val, tb_cfg_switch, + sw->tmu.cap + tmu_rtr_cs_3, 1); +} + +static int tb_port_tmu_write(struct tb_port *port, u8 offset, u32 mask, + u32 value) +{ + u32 data; + int ret; + + ret = tb_port_read(port, &data, tb_cfg_port, port->cap_tmu + offset, 1); + if (ret) + return ret; + + data &= ~mask; + data |= value; + + return tb_port_write(port, &data, tb_cfg_port, + port->cap_tmu + offset, 1); +} + +static int tb_port_tmu_set_unidirectional(struct tb_port *port, + bool unidirectional) +{ + u32 val; + + if (!port->sw->tmu.has_ucap) + return 0; + + val = unidirectional ? tmu_adp_cs_3_udm : 0; + return tb_port_tmu_write(port, tmu_adp_cs_3, tmu_adp_cs_3_udm, val); +} + +static inline int tb_port_tmu_unidirectional_disable(struct tb_port *port) +{ + return tb_port_tmu_set_unidirectional(port, false); +} + +static bool tb_port_tmu_is_unidirectional(struct tb_port *port) +{ + int ret; + u32 val; + + ret = tb_port_read(port, &val, tb_cfg_port, + port->cap_tmu + tmu_adp_cs_3, 1); + if (ret) + return false; + + return val & tmu_adp_cs_3_udm; +} + +static int tb_switch_tmu_set_time_disruption(struct tb_switch *sw, bool set) +{ + int ret; + u32 val; + + ret = tb_sw_read(sw, &val, tb_cfg_switch, + sw->tmu.cap + tmu_rtr_cs_0, 1); + if (ret) + return ret; + + if (set) + val |= tmu_rtr_cs_0_td; + else + val &= ~tmu_rtr_cs_0_td; + + return tb_sw_write(sw, &val, tb_cfg_switch, + sw->tmu.cap + tmu_rtr_cs_0, 1); +} + +/** + * tb_switch_tmu_init() - initialize switch tmu structures + * @sw: switch to initialized + * + * this function must be called before other tmu related functions to + * makes the internal structures are filled in correctly. does not + * change any hardware configuration. + */ +int tb_switch_tmu_init(struct tb_switch *sw) +{ + struct tb_port *port; + int ret; + + if (tb_switch_is_icm(sw)) + return 0; + + ret = tb_switch_find_cap(sw, tb_switch_cap_tmu); + if (ret > 0) + sw->tmu.cap = ret; + + tb_switch_for_each_port(sw, port) { + int cap; + + cap = tb_port_find_cap(port, tb_port_cap_time1); + if (cap > 0) + port->cap_tmu = cap; + } + + ret = tb_switch_tmu_rate_read(sw); + if (ret < 0) + return ret; + + sw->tmu.rate = ret; + + sw->tmu.has_ucap = tb_switch_tmu_ucap_supported(sw); + if (sw->tmu.has_ucap) { + tb_sw_dbg(sw, "tmu: supports uni-directional mode "); + + if (tb_route(sw)) { + struct tb_port *up = tb_upstream_port(sw); + + sw->tmu.unidirectional = + tb_port_tmu_is_unidirectional(up); + } + } else { + sw->tmu.unidirectional = false; + } + + tb_sw_dbg(sw, "tmu: current mode: %s ", tb_switch_tmu_mode_name(sw)); + return 0; +} + +/** + * tb_switch_tmu_post_time() - update switch local time + * @sw: switch whose time to update + * + * updates switch local time using time posting procedure. + */ +int tb_switch_tmu_post_time(struct tb_switch *sw) +{ + unsigned int post_local_time_offset, post_time_offset; + struct tb_switch *root_switch = sw->tb->root_switch; + u64 hi, mid, lo, local_time, post_time; + int i, ret, retries = 100; + u32 gm_local_time[3]; + + if (!tb_route(sw)) + return 0; + + if (!tb_switch_is_usb4(sw)) + return 0; + + /* need to be able to read the grand master time */ + if (!root_switch->tmu.cap) + return 0; + + ret = tb_sw_read(root_switch, gm_local_time, tb_cfg_switch, + root_switch->tmu.cap + tmu_rtr_cs_1, + array_size(gm_local_time)); + if (ret) + return ret; + + for (i = 0; i < array_size(gm_local_time); i++) + tb_sw_dbg(root_switch, "local_time[%d]=0x%08x ", i, + gm_local_time[i]); + + /* convert to nanoseconds (drop fractional part) */ + hi = gm_local_time[2] & tmu_rtr_cs_3_local_time_ns_mask; + mid = gm_local_time[1]; + lo = (gm_local_time[0] & tmu_rtr_cs_1_local_time_ns_mask) >> + tmu_rtr_cs_1_local_time_ns_shift; + local_time = hi << 48 | mid << 16 | lo; + + /* tell the switch that time sync is disrupted for a while */ + ret = tb_switch_tmu_set_time_disruption(sw, true); + if (ret) + return ret; + + post_local_time_offset = sw->tmu.cap + tmu_rtr_cs_22; + post_time_offset = sw->tmu.cap + tmu_rtr_cs_24; + + /* + * write the grandmaster time to the post local time registers + * of the new switch. + */ + ret = tb_sw_write(sw, &local_time, tb_cfg_switch, + post_local_time_offset, 2); + if (ret) + goto out; + + /* + * have the new switch update its local time (by writing 1 to + * the post_time registers) and wait for the completion of the + * same (post_time register becomes 0). this means the time has + * been converged properly. + */ + post_time = 1; + + ret = tb_sw_write(sw, &post_time, tb_cfg_switch, post_time_offset, 2); + if (ret) + goto out; + + do { + usleep_range(5, 10); + ret = tb_sw_read(sw, &post_time, tb_cfg_switch, + post_time_offset, 2); + if (ret) + goto out; + } while (--retries && post_time); + + if (!retries) { + ret = -etimedout; + goto out; + } + + tb_sw_dbg(sw, "tmu: updated local time to %#llx ", local_time); + +out: + tb_switch_tmu_set_time_disruption(sw, false); + return ret; +} + +/** + * tb_switch_tmu_disable() - disable tmu of a switch + * @sw: switch whose tmu to disable + * + * turns off tmu of @sw if it is enabled. if not enabled does nothing. + */ +int tb_switch_tmu_disable(struct tb_switch *sw) +{ + int ret; + + if (!tb_switch_is_usb4(sw)) + return 0; + + /* already disabled? */ + if (sw->tmu.rate == tb_switch_tmu_rate_off) + return 0; + + if (sw->tmu.unidirectional) { + struct tb_switch *parent = tb_switch_parent(sw); + struct tb_port *up, *down; + + up = tb_upstream_port(sw); + down = tb_port_at(tb_route(sw), parent); + + /* the switch may be unplugged so ignore any errors */ + tb_port_tmu_unidirectional_disable(up); + ret = tb_port_tmu_unidirectional_disable(down); + if (ret) + return ret; + } + + tb_switch_tmu_rate_write(sw, tb_switch_tmu_rate_off); + + sw->tmu.unidirectional = false; + sw->tmu.rate = tb_switch_tmu_rate_off; + + tb_sw_dbg(sw, "tmu: disabled "); + return 0; +} + +/** + * tb_switch_tmu_enable() - enable tmu on a switch + * @sw: switch whose tmu to enable + * + * enables tmu of a switch to be in bi-directional, hifi mode. in this mode + * all tunneling should work. + */ +int tb_switch_tmu_enable(struct tb_switch *sw) +{ + int ret; + + if (!tb_switch_is_usb4(sw)) + return 0; + + if (tb_switch_tmu_is_enabled(sw)) + return 0; + + ret = tb_switch_tmu_set_time_disruption(sw, true); + if (ret) + return ret; + + /* change mode to bi-directional */ + if (tb_route(sw) && sw->tmu.unidirectional) { + struct tb_switch *parent = tb_switch_parent(sw); + struct tb_port *up, *down; + + up = tb_upstream_port(sw); + down = tb_port_at(tb_route(sw), parent); + + ret = tb_port_tmu_unidirectional_disable(down); + if (ret) + return ret; + + ret = tb_switch_tmu_rate_write(sw, tb_switch_tmu_rate_hifi); + if (ret) + return ret; + + ret = tb_port_tmu_unidirectional_disable(up); + if (ret) + return ret; + } else { + ret = tb_switch_tmu_rate_write(sw, tb_switch_tmu_rate_hifi); + if (ret) + return ret; + } + + sw->tmu.unidirectional = false; + sw->tmu.rate = tb_switch_tmu_rate_hifi; + tb_sw_dbg(sw, "tmu: mode set to: %s ", tb_switch_tmu_mode_name(sw)); + + return tb_switch_tmu_set_time_disruption(sw, false); +} | Thunderbolt | cf29b9afb121494a7aa12dae6eebf81347e0313b | rajmohan mani | drivers | thunderbolt | |
thunderbolt: add support for usb 3.x tunnels | usb4 added a capability to tunnel usb 3.x protocol over the usb4 fabric. usb4 device routers may include integrated superspeed hub or a function or both. usb tunneling follows pcie so that the tunnel is created between the parent and the child router from usb3 downstream adapter port to usb3 upstream adapter port over a single usb4 link. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['c', 'h'] | 7 | 395 | 27 | --- diff --git a/drivers/thunderbolt/switch.c b/drivers/thunderbolt/switch.c --- a/drivers/thunderbolt/switch.c +++ b/drivers/thunderbolt/switch.c + case tb_type_usb3_up: + case tb_type_usb3_down: + return tb_usb3_port_is_enabled(port); + +/** + * tb_usb3_port_is_enabled() - is the usb3 adapter port enabled + * @port: usb3 adapter port to check + */ +bool tb_usb3_port_is_enabled(struct tb_port *port) +{ + u32 data; + + if (tb_port_read(port, &data, tb_cfg_port, + port->cap_adap + adp_usb3_cs_0, 1)) + return false; + + return !!(data & adp_usb3_cs_0_pe); +} + +/** + * tb_usb3_port_enable() - enable usb3 adapter port + * @port: usb3 adapter port to enable + * @enable: enable/disable the usb3 adapter + */ +int tb_usb3_port_enable(struct tb_port *port, bool enable) +{ + u32 word = enable ? (adp_usb3_cs_0_pe | adp_usb3_cs_0_v) + : adp_usb3_cs_0_v; + + if (!port->cap_adap) + return -enxio; + return tb_port_write(port, &word, tb_cfg_port, + port->cap_adap + adp_usb3_cs_0, 1); +} + diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c + case tb_type_usb3_down: + tunnel = tb_tunnel_discover_usb3(tb, port); + break; + +/** + * tb_find_unused_port() - return the first inactive port on @sw + * @sw: switch to find the port on + * @type: port type to look for + */ +static struct tb_port *tb_find_unused_port(struct tb_switch *sw, + enum tb_port_type type) +{ + struct tb_port *port; + + tb_switch_for_each_port(sw, port) { + if (tb_is_upstream_port(port)) + continue; + if (port->config.type != type) + continue; + if (!port->cap_adap) + continue; + if (tb_port_is_enabled(port)) + continue; + return port; + } + return null; +} + +static struct tb_port *tb_find_usb3_down(struct tb_switch *sw, + const struct tb_port *port) +{ + struct tb_port *down; + + down = usb4_switch_map_usb3_down(sw, port); + if (down) { + if (warn_on(!tb_port_is_usb3_down(down))) + goto out; + if (warn_on(tb_usb3_port_is_enabled(down))) + goto out; + + return down; + } + +out: + return tb_find_unused_port(sw, tb_type_usb3_down); +} + +static int tb_tunnel_usb3(struct tb *tb, struct tb_switch *sw) +{ + struct tb_switch *parent = tb_switch_parent(sw); + struct tb_port *up, *down, *port; + struct tb_cm *tcm = tb_priv(tb); + struct tb_tunnel *tunnel; + + up = tb_switch_find_port(sw, tb_type_usb3_up); + if (!up) + return 0; + + /* + * look up available down port. since we are chaining it should + * be found right above this switch. + */ + port = tb_port_at(tb_route(sw), parent); + down = tb_find_usb3_down(parent, port); + if (!down) + return 0; + + if (tb_route(parent)) { + struct tb_port *parent_up; + /* + * check first that the parent switch has its upstream usb3 + * port enabled. otherwise the chain is not complete and + * there is no point setting up a new tunnel. + */ + parent_up = tb_switch_find_port(parent, tb_type_usb3_up); + if (!parent_up || !tb_port_is_enabled(parent_up)) + return 0; + } + + tunnel = tb_tunnel_alloc_usb3(tb, up, down); + if (!tunnel) + return -enomem; + + if (tb_tunnel_activate(tunnel)) { + tb_port_info(up, + "usb3 tunnel activation failed, aborting "); + tb_tunnel_free(tunnel); + return -eio; + } + + list_add_tail(&tunnel->list, &tcm->tunnel_list); + return 0; +} + +static int tb_create_usb3_tunnels(struct tb_switch *sw) +{ + struct tb_port *port; + int ret; + + if (tb_route(sw)) { + ret = tb_tunnel_usb3(sw->tb, sw); + if (ret) + return ret; + } + + tb_switch_for_each_port(sw, port) { + if (!tb_port_has_remote(port)) + continue; + ret = tb_create_usb3_tunnels(port->remote->sw); + if (ret) + return ret; + } + + return 0; +} + + /* + * create usb 3.x tunnels only when the switch is plugged to the + * domain. this is because we scan the domain also during discovery + * and want to discover existing usb 3.x tunnels before we create + * any new. + */ + if (tcm->hotplug_active && tb_tunnel_usb3(sw->tb, sw)) + tb_sw_warn(sw, "usb3 tunnel creation failed "); + -/** - * tb_find_unused_port() - return the first inactive port on @sw - * @sw: switch to find the port on - * @type: port type to look for - */ -static struct tb_port *tb_find_unused_port(struct tb_switch *sw, - enum tb_port_type type) -{ - struct tb_port *port; - - tb_switch_for_each_port(sw, port) { - if (tb_is_upstream_port(port)) - continue; - if (port->config.type != type) - continue; - if (port->cap_adap) - continue; - if (tb_port_is_enabled(port)) - continue; - return port; - } - return null; -} - + /* + * if the boot firmware did not create usb 3.x tunnels create them + * now for the whole topology. + */ + tb_create_usb3_tunnels(tb->root_switch); diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h +static inline bool tb_port_is_usb3_down(const struct tb_port *port) +{ + return port && port->config.type == tb_type_usb3_down; +} + +static inline bool tb_port_is_usb3_up(const struct tb_port *port) +{ + return port && port->config.type == tb_type_usb3_up; +} + +bool tb_usb3_port_is_enabled(struct tb_port *port); +int tb_usb3_port_enable(struct tb_port *port, bool enable); + +struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, + const struct tb_port *port); diff --git a/drivers/thunderbolt/tb_regs.h b/drivers/thunderbolt/tb_regs.h --- a/drivers/thunderbolt/tb_regs.h +++ b/drivers/thunderbolt/tb_regs.h +#define router_cs_5_uto bit(25) - /* tb_type_usb = 0x200000, lower order bits are not known */ + tb_type_usb3_down = 0x200101, + tb_type_usb3_up = 0x200102, +/* usb adapter registers */ +#define adp_usb3_cs_0 0x00 +#define adp_usb3_cs_0_v bit(30) +#define adp_usb3_cs_0_pe bit(31) + diff --git a/drivers/thunderbolt/tunnel.c b/drivers/thunderbolt/tunnel.c --- a/drivers/thunderbolt/tunnel.c +++ b/drivers/thunderbolt/tunnel.c +/* usb3 adapters use always hopid of 8 for both directions */ +#define tb_usb3_hopid 8 + +#define tb_usb3_path_down 0 +#define tb_usb3_path_up 1 + -static const char * const tb_tunnel_names[] = { "pci", "dp", "dma" }; +static const char * const tb_tunnel_names[] = { "pci", "dp", "dma", "usb3" }; +static int tb_usb3_activate(struct tb_tunnel *tunnel, bool activate) +{ + int res; + + res = tb_usb3_port_enable(tunnel->src_port, activate); + if (res) + return res; + + if (tb_port_is_usb3_up(tunnel->dst_port)) + return tb_usb3_port_enable(tunnel->dst_port, activate); + + return 0; +} + +static void tb_usb3_init_path(struct tb_path *path) +{ + path->egress_fc_enable = tb_path_source | tb_path_internal; + path->egress_shared_buffer = tb_path_none; + path->ingress_fc_enable = tb_path_all; + path->ingress_shared_buffer = tb_path_none; + path->priority = 3; + path->weight = 3; + path->drop_packages = 0; + path->nfc_credits = 0; + path->hops[0].initial_credits = 7; + path->hops[1].initial_credits = + tb_initial_credits(path->hops[1].in_port->sw); +} + +/** + * tb_tunnel_discover_usb3() - discover existing usb3 tunnels + * @tb: pointer to the domain structure + * @down: usb3 downstream adapter + * + * if @down adapter is active, follows the tunnel to the usb3 upstream + * adapter and back. returns the discovered tunnel or %null if there was + * no tunnel. + */ +struct tb_tunnel *tb_tunnel_discover_usb3(struct tb *tb, struct tb_port *down) +{ + struct tb_tunnel *tunnel; + struct tb_path *path; + + if (!tb_usb3_port_is_enabled(down)) + return null; + + tunnel = tb_tunnel_alloc(tb, 2, tb_tunnel_usb3); + if (!tunnel) + return null; + + tunnel->activate = tb_usb3_activate; + tunnel->src_port = down; + + /* + * discover both paths even if they are not complete. we will + * clean them up by calling tb_tunnel_deactivate() below in that + * case. + */ + path = tb_path_discover(down, tb_usb3_hopid, null, -1, + &tunnel->dst_port, "usb3 up"); + if (!path) { + /* just disable the downstream port */ + tb_usb3_port_enable(down, false); + goto err_free; + } + tunnel->paths[tb_usb3_path_up] = path; + tb_usb3_init_path(tunnel->paths[tb_usb3_path_up]); + + path = tb_path_discover(tunnel->dst_port, -1, down, tb_usb3_hopid, null, + "usb3 down"); + if (!path) + goto err_deactivate; + tunnel->paths[tb_usb3_path_down] = path; + tb_usb3_init_path(tunnel->paths[tb_usb3_path_down]); + + /* validate that the tunnel is complete */ + if (!tb_port_is_usb3_up(tunnel->dst_port)) { + tb_port_warn(tunnel->dst_port, + "path does not end on an usb3 adapter, cleaning up "); + goto err_deactivate; + } + + if (down != tunnel->src_port) { + tb_tunnel_warn(tunnel, "path is not complete, cleaning up "); + goto err_deactivate; + } + + if (!tb_usb3_port_is_enabled(tunnel->dst_port)) { + tb_tunnel_warn(tunnel, + "tunnel is not fully activated, cleaning up "); + goto err_deactivate; + } + + tb_tunnel_dbg(tunnel, "discovered "); + return tunnel; + +err_deactivate: + tb_tunnel_deactivate(tunnel); +err_free: + tb_tunnel_free(tunnel); + + return null; +} + +/** + * tb_tunnel_alloc_usb3() - allocate a usb3 tunnel + * @tb: pointer to the domain structure + * @up: usb3 upstream adapter port + * @down: usb3 downstream adapter port + * + * allocate an usb3 tunnel. the ports must be of type @tb_type_usb3_up and + * @tb_type_usb3_down. + * + * return: returns a tb_tunnel on success or %null on failure. + */ +struct tb_tunnel *tb_tunnel_alloc_usb3(struct tb *tb, struct tb_port *up, + struct tb_port *down) +{ + struct tb_tunnel *tunnel; + struct tb_path *path; + + tunnel = tb_tunnel_alloc(tb, 2, tb_tunnel_usb3); + if (!tunnel) + return null; + + tunnel->activate = tb_usb3_activate; + tunnel->src_port = down; + tunnel->dst_port = up; + + path = tb_path_alloc(tb, down, tb_usb3_hopid, up, tb_usb3_hopid, 0, + "usb3 down"); + if (!path) { + tb_tunnel_free(tunnel); + return null; + } + tb_usb3_init_path(path); + tunnel->paths[tb_usb3_path_down] = path; + + path = tb_path_alloc(tb, up, tb_usb3_hopid, down, tb_usb3_hopid, 0, + "usb3 up"); + if (!path) { + tb_tunnel_free(tunnel); + return null; + } + tb_usb3_init_path(path); + tunnel->paths[tb_usb3_path_up] = path; + + return tunnel; +} + diff --git a/drivers/thunderbolt/tunnel.h b/drivers/thunderbolt/tunnel.h --- a/drivers/thunderbolt/tunnel.h +++ b/drivers/thunderbolt/tunnel.h + tb_tunnel_usb3, +struct tb_tunnel *tb_tunnel_discover_usb3(struct tb *tb, struct tb_port *down); +struct tb_tunnel *tb_tunnel_alloc_usb3(struct tb *tb, struct tb_port *up, + struct tb_port *down); +static inline bool tb_tunnel_is_usb3(const struct tb_tunnel *tunnel) +{ + return tunnel->type == tb_tunnel_usb3; +} + diff --git a/drivers/thunderbolt/usb4.c b/drivers/thunderbolt/usb4.c --- a/drivers/thunderbolt/usb4.c +++ b/drivers/thunderbolt/usb4.c + if (tb_switch_find_port(parent, tb_type_usb3_down)) { + val |= router_cs_5_uto; + xhci = false; + } + - /* xhci can be enabled if pcie tunneling is supported */ + /* + * xhci can be enabled if pcie tunneling is supported + * and the parent does not have any usb3 dowstream + * adapters (so we cannot do usb 3.x tunneling). + */ +/** + * usb4_switch_map_usb3_down() - map usb4 port to a usb3 downstream adapter + * @sw: usb4 router + * @port: usb4 port + * + * usb4 routers have direct mapping between usb4 ports and usb 3.x + * downstream adapters where the usb 3.x topology is extended. this + * function returns the corresponding downstream usb 3.x adapter or + * %null if no such mapping was possible. + */ +struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, + const struct tb_port *port) +{ + int usb4_idx = usb4_port_idx(sw, port); + struct tb_port *p; + int usb_idx = 0; + + /* find usb3 down port matching usb4_port */ + tb_switch_for_each_port(sw, p) { + if (!tb_port_is_usb3_down(p)) + continue; + + if (usb_idx == usb4_idx && !tb_usb3_port_is_enabled(p)) + return p; + + usb_idx++; + } + + return null; +} + | Thunderbolt | e6f818585713efb29d54f732f41291f75046a2c7 | rajmohan mani | drivers | thunderbolt | |
thunderbolt: update documentation with the usb4 information | update user's and administrator's guide to mention usb4, how it relates to thunderbolt and and how it is supported in linux. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for usb 4. usb4 is the public specification of thunderbolt 3 protocol | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['(featured) thunderbolt'] | ['rst'] | 1 | 25 | 5 | --- diff --git a/documentation/admin-guide/thunderbolt.rst b/documentation/admin-guide/thunderbolt.rst --- a/documentation/admin-guide/thunderbolt.rst +++ b/documentation/admin-guide/thunderbolt.rst -============= - thunderbolt -============= +.. spdx-license-identifier: gpl-2.0 + +====================== + usb4 and thunderbolt +====================== +usb4 is the public specification based on thunderbolt 3 protocol with +some differences at the register level among other things. connection +manager is an entity running on the host router (host controller) +responsible for enumerating routers and establishing tunnels. a +connection manager can be implemented either in firmware or software. +typically pcs come with a firmware connection manager for thunderbolt 3 +and early usb4 capable systems. apple systems on the other hand use +software connection manager and the later usb4 compliant devices follow +the suit. + +the linux thunderbolt driver supports both and can detect at runtime which +connection manager implementation is to be used. to be on the safe side the +software connection manager in linux also advertises security level +''user'' which means pcie tunneling is disabled by default. the +documentation below applies to both implementations with the exception that +the software connection manager only supports ''user'' security level and +is expected to be accompanied with an iommu based dma protection. + +security levels and how to use them +----------------------------------- -security levels and how to use them ------------------------------------ | Thunderbolt | ea81896dc98f324ff3fb9b1e74b4915a1beb3296 | mika westerberg | documentation | admin-guide | |
clk: add support for setting clk_rate via debugfs | for testing, it is useful to be able to specify a clock rate manually. as this is a dangerous feature, it is not enabled by default. users need to modify the source directly and #define clock_allow_write_debugfs. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for setting clk_rate via debugfs | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | [] | ['c'] | 1 | 37 | 1 | --- diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c +#undef clock_allow_write_debugfs +#ifdef clock_allow_write_debugfs +/* + * this can be dangerous, therefore don't provide any real compile time + * configuration option for this feature. + * people who want to use this will need to modify the source code directly. + */ +static int clk_rate_set(void *data, u64 val) +{ + struct clk_core *core = data; + int ret; + + clk_prepare_lock(); + ret = clk_core_set_rate_nolock(core, val); + clk_prepare_unlock(); + + return ret; +} + +#define clk_rate_mode 0644 +#else +#define clk_rate_set null +#define clk_rate_mode 0444 +#endif + +static int clk_rate_get(void *data, u64 *val) +{ + struct clk_core *core = data; + + *val = core->rate; + return 0; +} + +define_debugfs_attribute(clk_rate_fops, clk_rate_get, clk_rate_set, "%llu "); + - debugfs_create_ulong("clk_rate", 0444, root, &core->rate); + debugfs_create_file("clk_rate", clk_rate_mode, root, core, + &clk_rate_fops); | Clock | 37215da5553eb00616291a82decb958bb2d98fc1 | geert uytterhoeven | drivers | clk | |
clk: fsl-sai: new driver | with this driver it is possible to use the bclk pin of the sai module as a generic clock output. this is esp. useful if you want to drive a clock to an audio codec. because the output only allows integer divider values the audio codec needs an integrated pll. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | new driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['fsl-sai'] | ['c', 'kconfig', 'makefile'] | 3 | 105 | 0 | --- diff --git a/drivers/clk/kconfig b/drivers/clk/kconfig --- a/drivers/clk/kconfig +++ b/drivers/clk/kconfig +config common_clk_fsl_sai + bool "clock driver for bclk of freescale sai cores" + depends on arch_layerscape || compile_test + help + this driver supports the freescale sai (synchronous audio interface) + to be used as a generic clock output. some socs have restrictions + regarding the possible pin multiplexer settings. eg. on some socs + two sai interfaces can only be enabled together. if just one is + needed, the bclk pin of the second one can be used as general + purpose clock output. ideally, it can be used to drive an audio + codec (sometimes known as mclk). + diff --git a/drivers/clk/makefile b/drivers/clk/makefile --- a/drivers/clk/makefile +++ b/drivers/clk/makefile +obj-$(config_common_clk_fsl_sai) += clk-fsl-sai.o diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c --- /dev/null +++ b/drivers/clk/clk-fsl-sai.c +// spdx-license-identifier: gpl-2.0 +/* + * freescale sai bclk as a generic clock driver + * + * copyright 2020 michael walle <michael@walle.cc> + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/slab.h> + +#define i2s_csr 0x00 +#define i2s_cr2 0x08 +#define csr_bce_bit 28 +#define cr2_bcd bit(24) +#define cr2_div_shift 0 +#define cr2_div_width 8 + +struct fsl_sai_clk { + struct clk_divider div; + struct clk_gate gate; + spinlock_t lock; +}; + +static int fsl_sai_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct fsl_sai_clk *sai_clk; + struct clk_parent_data pdata = { .index = 0 }; + void __iomem *base; + struct clk_hw *hw; + struct resource *res; + + sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), gfp_kernel); + if (!sai_clk) + return -enomem; + + res = platform_get_resource(pdev, ioresource_mem, 0); + base = devm_ioremap_resource(dev, res); + if (is_err(base)) + return ptr_err(base); + + spin_lock_init(&sai_clk->lock); + + sai_clk->gate.reg = base + i2s_csr; + sai_clk->gate.bit_idx = csr_bce_bit; + sai_clk->gate.lock = &sai_clk->lock; + + sai_clk->div.reg = base + i2s_cr2; + sai_clk->div.shift = cr2_div_shift; + sai_clk->div.width = cr2_div_width; + sai_clk->div.lock = &sai_clk->lock; + + /* set clock direction, we are the bclk master */ + writel(cr2_bcd, base + i2s_cr2); + + hw = clk_hw_register_composite_pdata(dev, dev->of_node->name, + &pdata, 1, null, null, + &sai_clk->div.hw, + &clk_divider_ops, + &sai_clk->gate.hw, + &clk_gate_ops, + clk_set_rate_gate); + if (is_err(hw)) + return ptr_err(hw); + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); +} + +static const struct of_device_id of_fsl_sai_clk_ids[] = { + { .compatible = "fsl,vf610-sai-clock" }, + { } +}; +module_device_table(of, of_fsl_sai_clk_ids); + +static struct platform_driver fsl_sai_clk_driver = { + .probe = fsl_sai_clk_probe, + .driver = { + .name = "fsl-sai-clk", + .of_match_table = of_fsl_sai_clk_ids, + }, +}; +module_platform_driver(fsl_sai_clk_driver); + +module_description("freescale sai bitclock-as-a-clock driver"); +module_author("michael walle <michael@walle.cc>"); +module_license("gpl"); +module_alias("platform:fsl-sai-clk"); | Clock | 9cd10205227cbe9bbd48fd6bf78dad88b45526b0 | michael walle | drivers | clk | |
clk: imx: add support for i.mx8mp clock driver | add clock driver support for i.mx8mp which is a new soc of i.mx8m family. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for i.mx8mp clock driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['imx'] | ['c', 'kconfig', 'makefile'] | 3 | 771 | 0 | --- diff --git a/drivers/clk/imx/kconfig b/drivers/clk/imx/kconfig --- a/drivers/clk/imx/kconfig +++ b/drivers/clk/imx/kconfig +config clk_imx8mp + bool "imx8mp ccm clock driver" + depends on arch_mxc && arm64 + help + build the driver for i.mx8mp ccm clock driver + diff --git a/drivers/clk/imx/makefile b/drivers/clk/imx/makefile --- a/drivers/clk/imx/makefile +++ b/drivers/clk/imx/makefile +obj-$(config_clk_imx8mp) += clk-imx8mp.o diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c --- /dev/null +++ b/drivers/clk/imx/clk-imx8mp.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright 2019 nxp. + */ + +#include <dt-bindings/clock/imx8mp-clock.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/types.h> + +#include "clk.h" + +static u32 share_count_nand; +static u32 share_count_media; + +static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", }; +static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", }; +static const char * const audio_pll2_bypass_sels[] = {"audio_pll2", "audio_pll2_ref_sel", }; +static const char * const video_pll1_bypass_sels[] = {"video_pll1", "video_pll1_ref_sel", }; +static const char * const dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", }; +static const char * const gpu_pll_bypass_sels[] = {"gpu_pll", "gpu_pll_ref_sel", }; +static const char * const vpu_pll_bypass_sels[] = {"vpu_pll", "vpu_pll_ref_sel", }; +static const char * const arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", }; +static const char * const sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", }; +static const char * const sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", }; +static const char * const sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", }; + +static const char * const imx8mp_a53_sels[] = {"osc_24m", "arm_pll_out", "sys_pll2_500m", + "sys_pll2_1000m", "sys_pll1_800m", "sys_pll1_400m", + "audio_pll1_out", "sys_pll3_out", }; + +static const char * const imx8mp_m7_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_250m", + "vpu_pll_out", "sys_pll1_800m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; + +static const char * const imx8mp_ml_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_gpu3d_core_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_gpu3d_shader_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_gpu2d_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_audio_axi_sels[] = {"osc_24m", "gpu_pll_out", "sys_pll1_800m", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_hsio_axi_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mp_media_isp_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_400m", "audio_pll2_out", + "clk_ext1", "sys_pll2_500m", }; + +static const char * const imx8mp_main_axi_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "sys_pll1_100m",}; + +static const char * const imx8mp_enet_axi_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_250m", "sys_pll2_200m", "audio_pll1_out", + "video_pll1_out", "sys_pll3_out", }; + +static const char * const imx8mp_nand_usdhc_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll1_800m", + "sys_pll2_200m", "sys_pll1_133m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll1_out", }; + +static const char * const imx8mp_vpu_bus_sels[] = {"osc_24m", "sys_pll1_800m", "vpu_pll_out", + "audio_pll2_out", "sys_pll3_out", "sys_pll2_1000m", + "sys_pll2_200m", "sys_pll1_100m", }; + +static const char * const imx8mp_media_axi_sels[] = {"osc_24m", "sys_pll2_1000m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", + "clk_ext1", "sys_pll2_500m", }; + +static const char * const imx8mp_media_apb_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll1_800m", + "sys_pll3_out", "sys_pll1_40m", "audio_pll2_out", + "clk_ext1", "sys_pll1_133m", }; + +static const char * const imx8mp_gpu_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_gpu_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_noc_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_noc_io_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_1000m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_ml_axi_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_ml_ahb_sels[] = {"osc_24m", "sys_pll1_800m", "gpu_pll_out", + "sys_pll3_out", "sys_pll2_1000m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", + "sys_pll1_400m", "sys_pll2_125m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; + +static const char * const imx8mp_audio_ahb_sels[] = {"osc_24m", "sys_pll2_500m", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll2_166m", "sys_pll3_out", + "audio_pll1_out", "video_pll1_out", }; + +static const char * const imx8mp_mipi_dsi_esc_rx_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_dram_alt_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_100m", + "sys_pll2_500m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll1_out", "sys_pll1_266m", }; + +static const char * const imx8mp_dram_apb_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char * const imx8mp_vpu_g1_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char * const imx8mp_vpu_g2_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll1_100m", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char * const imx8mp_can1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char * const imx8mp_can2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char * const imx8mp_memrepair_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; + +static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_160m", "sys_pll1_200m", }; + +static const char * const imx8mp_i2c5_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_i2c6_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_sai1_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext1", "clk_ext2", }; + +static const char * const imx8mp_sai2_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext2", "clk_ext3", }; + +static const char * const imx8mp_sai3_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char * const imx8mp_sai4_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext1", "clk_ext2", }; + +static const char * const imx8mp_sai5_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext2", "clk_ext3", }; + +static const char * const imx8mp_sai6_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char * const imx8mp_enet_qos_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char * const imx8mp_enet_qos_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + +static const char * const imx8mp_enet_ref_sels[] = {"osc_24m", "sys_pll2_125m", "sys_pll2_50m", + "sys_pll2_100m", "sys_pll1_160m", "audio_pll1_out", + "video_pll1_out", "clk_ext4", }; + +static const char * const imx8mp_enet_timer_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "video_pll1_out", }; + +static const char * const imx8mp_enet_phy_ref_sels[] = {"osc_24m", "sys_pll2_50m", "sys_pll2_125m", + "sys_pll2_200m", "sys_pll2_500m", "audio_pll1_out", + "video_pll1_out", "audio_pll2_out", }; + +static const char * const imx8mp_nand_sels[] = {"osc_24m", "sys_pll2_500m", "audio_pll1_out", + "sys_pll1_400m", "audio_pll2_out", "sys_pll3_out", + "sys_pll2_250m", "video_pll1_out", }; + +static const char * const imx8mp_qspi_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll2_333m", + "sys_pll2_500m", "audio_pll2_out", "sys_pll1_266m", + "sys_pll3_out", "sys_pll1_100m", }; + +static const char * const imx8mp_usdhc1_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char * const imx8mp_usdhc2_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char * const imx8mp_i2c1_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_i2c2_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_i2c3_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_i2c4_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_uart1_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mp_uart2_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_uart3_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext4", "audio_pll2_out", }; + +static const char * const imx8mp_uart4_sels[] = {"osc_24m", "sys_pll1_80m", "sys_pll2_200m", + "sys_pll2_100m", "sys_pll3_out", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_usb_core_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_usb_phy_ref_sels[] = {"osc_24m", "sys_pll1_100m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll2_200m", "clk_ext2", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_gic_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll2_100m", "sys_pll1_800m", + "sys_pll2_500m", "clk_ext4", "audio_pll2_out" }; + +static const char * const imx8mp_ecspi1_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char * const imx8mp_ecspi2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char * const imx8mp_pwm1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char * const imx8mp_pwm2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext1", + "sys_pll1_80m", "video_pll1_out", }; + +static const char * const imx8mp_pwm3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char * const imx8mp_pwm4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_160m", + "sys_pll1_40m", "sys_pll3_out", "clk_ext2", + "sys_pll1_80m", "video_pll1_out", }; + +static const char * const imx8mp_gpt1_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1" }; + +static const char * const imx8mp_gpt2_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext2" }; + +static const char * const imx8mp_gpt3_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext3" }; + +static const char * const imx8mp_gpt4_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext1" }; + +static const char * const imx8mp_gpt5_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext2" }; + +static const char * const imx8mp_gpt6_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_400m", + "sys_pll1_40m", "video_pll1_out", "sys_pll1_80m", + "audio_pll1_out", "clk_ext3" }; + +static const char * const imx8mp_wdog_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_160m", + "vpu_pll_out", "sys_pll2_125m", "sys_pll3_out", + "sys_pll1_80m", "sys_pll2_166m" }; + +static const char * const imx8mp_wrclk_sels[] = {"osc_24m", "sys_pll1_40m", "vpu_pll_out", + "sys_pll3_out", "sys_pll2_200m", "sys_pll1_266m", + "sys_pll2_500m", "sys_pll1_100m" }; + +static const char * const imx8mp_ipp_do_clko1_sels[] = {"osc_24m", "sys_pll1_800m", "sys_pll1_133m", + "sys_pll1_200m", "audio_pll2_out", "sys_pll2_500m", + "vpu_pll_out", "sys_pll1_80m" }; + +static const char * const imx8mp_ipp_do_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", + "sys_pll1_166m", "sys_pll3_out", "audio_pll1_out", + "video_pll1_out", "osc_32k" }; + +static const char * const imx8mp_hdmi_fdcc_tst_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "audio_pll2_out", "video_pll1_out", }; + +static const char * const imx8mp_hdmi_27m_sels[] = {"osc_24m", "sys_pll1_160m", "sys_pll2_50m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", + "audio_pll2_out", "sys_pll1_133m", }; + +static const char * const imx8mp_hdmi_ref_266m_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll3_out", + "sys_pll2_333m", "sys_pll1_266m", "sys_pll2_200m", + "audio_pll1_out", "video_pll1_out", }; + +static const char * const imx8mp_usdhc3_sels[] = {"osc_24m", "sys_pll1_400m", "sys_pll1_800m", + "sys_pll2_500m", "sys_pll3_out", "sys_pll1_266m", + "audio_pll2_out", "sys_pll1_100m", }; + +static const char * const imx8mp_media_cam1_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "audio_pll2_out", + "video_pll1_out", }; + +static const char * const imx8mp_media_mipi_phy1_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", + "clk_ext2", "audio_pll2_out", + "video_pll1_out", }; + +static const char * const imx8mp_media_disp1_pix_sels[] = {"osc_24m", "video_pll1_out", "audio_pll2_out", + "audio_pll1_out", "sys_pll1_800m", + "sys_pll2_1000m", "sys_pll3_out", "clk_ext4", }; + +static const char * const imx8mp_media_cam2_pix_sels[] = {"osc_24m", "sys_pll1_266m", "sys_pll2_250m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "audio_pll2_out", + "video_pll1_out", }; + +static const char * const imx8mp_media_mipi_phy2_ref_sels[] = {"osc_24m", "sys_pll2_333m", "sys_pll2_100m", + "sys_pll1_800m", "sys_pll2_1000m", + "clk_ext2", "audio_pll2_out", + "video_pll1_out", }; + +static const char * const imx8mp_media_mipi_csi2_esc_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll1_80m", + "sys_pll1_800m", "sys_pll2_1000m", + "sys_pll3_out", "clk_ext3", + "audio_pll2_out", }; + +static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", "sys_pll2_250m", "sys_pll2_200m", + "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_500m", + "sys_pll2_333m", "sys_pll3_out", }; + +static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", "sys_pll2_100m", "sys_pll2_500m", + "clk_ext1", "clk_ext2", "clk_ext3", + "clk_ext4", "sys_pll1_400m", }; + +static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll2_50m", + "sys_pll3_out", "sys_pll2_100m", + "sys_pll1_80m", "sys_pll1_160m", + "sys_pll1_200m", }; + +static const char * const imx8mp_ecspi3_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_40m", + "sys_pll1_160m", "sys_pll1_800m", "sys_pll3_out", + "sys_pll2_250m", "audio_pll2_out", }; + +static const char * const imx8mp_pdm_sels[] = {"osc_24m", "sys_pll2_100m", "audio_pll1_out", + "sys_pll1_800m", "sys_pll2_1000m", "sys_pll3_out", + "clk_ext3", "audio_pll2_out", }; + +static const char * const imx8mp_vpu_vc8000e_sels[] = {"osc_24m", "vpu_pll_out", "sys_pll1_800m", + "sys_pll2_1000m", "audio_pll2_out", "sys_pll2_125m", + "sys_pll3_out", "audio_pll1_out", }; + +static const char * const imx8mp_sai7_sels[] = {"osc_24m", "audio_pll1_out", "audio_pll2_out", + "video_pll1_out", "sys_pll1_133m", "osc_hdmi", + "clk_ext3", "clk_ext4", }; + +static const char * const imx8mp_dram_core_sels[] = {"dram_pll_out", "dram_alt_root", }; + +static struct clk_hw **hws; +static struct clk_hw_onecell_data *clk_hw_data; + +static const int uart_clk_ids[] = { + imx8mp_clk_uart1_root, + imx8mp_clk_uart2_root, + imx8mp_clk_uart3_root, + imx8mp_clk_uart4_root, +}; +static struct clk **uart_clks[array_size(uart_clk_ids) + 1]; + +static int imx8mp_clocks_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *anatop_base, *ccm_base; + int i; + + np = of_find_compatible_node(null, null, "fsl,imx8mp-anatop"); + anatop_base = of_iomap(np, 0); + if (warn_on(!anatop_base)) + return -enomem; + + np = dev->of_node; + ccm_base = devm_platform_ioremap_resource(pdev, 0); + if (warn_on(is_err(ccm_base))) { + iounmap(anatop_base); + return ptr_err(ccm_base); + } + + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, imx8mp_clk_end), gfp_kernel); + if (warn_on(!clk_hw_data)) { + iounmap(anatop_base); + return -enomem; + } + + clk_hw_data->num = imx8mp_clk_end; + hws = clk_hw_data->hws; + + hws[imx8mp_clk_dummy] = imx_clk_hw_fixed("dummy", 0); + hws[imx8mp_clk_24m] = imx_obtain_fixed_clk_hw(np, "osc_24m"); + hws[imx8mp_clk_32k] = imx_obtain_fixed_clk_hw(np, "osc_32k"); + hws[imx8mp_clk_ext1] = imx_obtain_fixed_clk_hw(np, "clk_ext1"); + hws[imx8mp_clk_ext2] = imx_obtain_fixed_clk_hw(np, "clk_ext2"); + hws[imx8mp_clk_ext3] = imx_obtain_fixed_clk_hw(np, "clk_ext3"); + hws[imx8mp_clk_ext4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); + + hws[imx8mp_audio_pll1_ref_sel] = imx_clk_hw_mux("audio_pll1_ref_sel", anatop_base + 0x0, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_audio_pll2_ref_sel] = imx_clk_hw_mux("audio_pll2_ref_sel", anatop_base + 0x14, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_video_pll1_ref_sel] = imx_clk_hw_mux("video_pll1_ref_sel", anatop_base + 0x28, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_dram_pll_ref_sel] = imx_clk_hw_mux("dram_pll_ref_sel", anatop_base + 0x50, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_gpu_pll_ref_sel] = imx_clk_hw_mux("gpu_pll_ref_sel", anatop_base + 0x64, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_vpu_pll_ref_sel] = imx_clk_hw_mux("vpu_pll_ref_sel", anatop_base + 0x74, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_arm_pll_ref_sel] = imx_clk_hw_mux("arm_pll_ref_sel", anatop_base + 0x84, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_sys_pll1_ref_sel] = imx_clk_hw_mux("sys_pll1_ref_sel", anatop_base + 0x94, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_sys_pll2_ref_sel] = imx_clk_hw_mux("sys_pll2_ref_sel", anatop_base + 0x104, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + hws[imx8mp_sys_pll3_ref_sel] = imx_clk_hw_mux("sys_pll3_ref_sel", anatop_base + 0x114, 0, 2, pll_ref_sels, array_size(pll_ref_sels)); + + hws[imx8mp_audio_pll1] = imx_clk_hw_pll14xx("audio_pll1", "audio_pll1_ref_sel", anatop_base, &imx_1443x_pll); + hws[imx8mp_audio_pll2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", anatop_base + 0x14, &imx_1443x_pll); + hws[imx8mp_video_pll1] = imx_clk_hw_pll14xx("video_pll1", "video_pll1_ref_sel", anatop_base + 0x28, &imx_1443x_pll); + hws[imx8mp_dram_pll] = imx_clk_hw_pll14xx("dram_pll", "dram_pll_ref_sel", anatop_base + 0x50, &imx_1443x_dram_pll); + hws[imx8mp_gpu_pll] = imx_clk_hw_pll14xx("gpu_pll", "gpu_pll_ref_sel", anatop_base + 0x64, &imx_1416x_pll); + hws[imx8mp_vpu_pll] = imx_clk_hw_pll14xx("vpu_pll", "vpu_pll_ref_sel", anatop_base + 0x74, &imx_1416x_pll); + hws[imx8mp_arm_pll] = imx_clk_hw_pll14xx("arm_pll", "arm_pll_ref_sel", anatop_base + 0x84, &imx_1416x_pll); + hws[imx8mp_sys_pll1] = imx_clk_hw_pll14xx("sys_pll1", "sys_pll1_ref_sel", anatop_base + 0x94, &imx_1416x_pll); + hws[imx8mp_sys_pll2] = imx_clk_hw_pll14xx("sys_pll2", "sys_pll2_ref_sel", anatop_base + 0x104, &imx_1416x_pll); + hws[imx8mp_sys_pll3] = imx_clk_hw_pll14xx("sys_pll3", "sys_pll3_ref_sel", anatop_base + 0x114, &imx_1416x_pll); + + hws[imx8mp_audio_pll1_bypass] = imx_clk_hw_mux_flags("audio_pll1_bypass", anatop_base, 4, 1, audio_pll1_bypass_sels, array_size(audio_pll1_bypass_sels), clk_set_rate_parent); + hws[imx8mp_audio_pll2_bypass] = imx_clk_hw_mux_flags("audio_pll2_bypass", anatop_base + 0x14, 4, 1, audio_pll2_bypass_sels, array_size(audio_pll2_bypass_sels), clk_set_rate_parent); + hws[imx8mp_video_pll1_bypass] = imx_clk_hw_mux_flags("video_pll1_bypass", anatop_base + 0x28, 4, 1, video_pll1_bypass_sels, array_size(video_pll1_bypass_sels), clk_set_rate_parent); + hws[imx8mp_dram_pll_bypass] = imx_clk_hw_mux_flags("dram_pll_bypass", anatop_base + 0x50, 4, 1, dram_pll_bypass_sels, array_size(dram_pll_bypass_sels), clk_set_rate_parent); + hws[imx8mp_gpu_pll_bypass] = imx_clk_hw_mux_flags("gpu_pll_bypass", anatop_base + 0x64, 4, 1, gpu_pll_bypass_sels, array_size(gpu_pll_bypass_sels), clk_set_rate_parent); + hws[imx8mp_vpu_pll_bypass] = imx_clk_hw_mux_flags("vpu_pll_bypass", anatop_base + 0x74, 4, 1, vpu_pll_bypass_sels, array_size(vpu_pll_bypass_sels), clk_set_rate_parent); + hws[imx8mp_arm_pll_bypass] = imx_clk_hw_mux_flags("arm_pll_bypass", anatop_base + 0x84, 4, 1, arm_pll_bypass_sels, array_size(arm_pll_bypass_sels), clk_set_rate_parent); + hws[imx8mp_sys_pll1_bypass] = imx_clk_hw_mux_flags("sys_pll1_bypass", anatop_base + 0x94, 4, 1, sys_pll1_bypass_sels, array_size(sys_pll1_bypass_sels), clk_set_rate_parent); + hws[imx8mp_sys_pll2_bypass] = imx_clk_hw_mux_flags("sys_pll2_bypass", anatop_base + 0x104, 4, 1, sys_pll2_bypass_sels, array_size(sys_pll2_bypass_sels), clk_set_rate_parent); + hws[imx8mp_sys_pll3_bypass] = imx_clk_hw_mux_flags("sys_pll3_bypass", anatop_base + 0x114, 4, 1, sys_pll3_bypass_sels, array_size(sys_pll3_bypass_sels), clk_set_rate_parent); + + hws[imx8mp_audio_pll1_out] = imx_clk_hw_gate("audio_pll1_out", "audio_pll1_bypass", anatop_base, 13); + hws[imx8mp_audio_pll2_out] = imx_clk_hw_gate("audio_pll2_out", "audio_pll2_bypass", anatop_base + 0x14, 13); + hws[imx8mp_video_pll1_out] = imx_clk_hw_gate("video_pll1_out", "video_pll1_bypass", anatop_base + 0x28, 13); + hws[imx8mp_dram_pll_out] = imx_clk_hw_gate("dram_pll_out", "dram_pll_bypass", anatop_base + 0x50, 13); + hws[imx8mp_gpu_pll_out] = imx_clk_hw_gate("gpu_pll_out", "gpu_pll_bypass", anatop_base + 0x64, 11); + hws[imx8mp_vpu_pll_out] = imx_clk_hw_gate("vpu_pll_out", "vpu_pll_bypass", anatop_base + 0x74, 11); + hws[imx8mp_arm_pll_out] = imx_clk_hw_gate("arm_pll_out", "arm_pll_bypass", anatop_base + 0x84, 11); + hws[imx8mp_sys_pll1_out] = imx_clk_hw_gate("sys_pll1_out", "sys_pll1_bypass", anatop_base + 0x94, 11); + hws[imx8mp_sys_pll2_out] = imx_clk_hw_gate("sys_pll2_out", "sys_pll2_bypass", anatop_base + 0x104, 11); + hws[imx8mp_sys_pll3_out] = imx_clk_hw_gate("sys_pll3_out", "sys_pll3_bypass", anatop_base + 0x114, 11); + + hws[imx8mp_sys_pll1_40m] = imx_clk_hw_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20); + hws[imx8mp_sys_pll1_80m] = imx_clk_hw_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10); + hws[imx8mp_sys_pll1_100m] = imx_clk_hw_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8); + hws[imx8mp_sys_pll1_133m] = imx_clk_hw_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6); + hws[imx8mp_sys_pll1_160m] = imx_clk_hw_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5); + hws[imx8mp_sys_pll1_200m] = imx_clk_hw_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4); + hws[imx8mp_sys_pll1_266m] = imx_clk_hw_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3); + hws[imx8mp_sys_pll1_400m] = imx_clk_hw_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2); + hws[imx8mp_sys_pll1_800m] = imx_clk_hw_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1); + + hws[imx8mp_sys_pll2_50m] = imx_clk_hw_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20); + hws[imx8mp_sys_pll2_100m] = imx_clk_hw_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10); + hws[imx8mp_sys_pll2_125m] = imx_clk_hw_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8); + hws[imx8mp_sys_pll2_166m] = imx_clk_hw_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6); + hws[imx8mp_sys_pll2_200m] = imx_clk_hw_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5); + hws[imx8mp_sys_pll2_250m] = imx_clk_hw_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4); + hws[imx8mp_sys_pll2_333m] = imx_clk_hw_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3); + hws[imx8mp_sys_pll2_500m] = imx_clk_hw_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2); + hws[imx8mp_sys_pll2_1000m] = imx_clk_hw_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1); + + hws[imx8mp_clk_a53_src] = imx_clk_hw_mux2("arm_a53_src", ccm_base + 0x8000, 24, 3, imx8mp_a53_sels, array_size(imx8mp_a53_sels)); + hws[imx8mp_clk_m7_src] = imx_clk_hw_mux2("arm_m7_src", ccm_base + 0x8080, 24, 3, imx8mp_m7_sels, array_size(imx8mp_m7_sels)); + hws[imx8mp_clk_ml_src] = imx_clk_hw_mux2("ml_src", ccm_base + 0x8100, 24, 3, imx8mp_ml_sels, array_size(imx8mp_ml_sels)); + hws[imx8mp_clk_gpu3d_core_src] = imx_clk_hw_mux2("gpu3d_core_src", ccm_base + 0x8180, 24, 3, imx8mp_gpu3d_core_sels, array_size(imx8mp_gpu3d_core_sels)); + hws[imx8mp_clk_gpu3d_shader_src] = imx_clk_hw_mux2("gpu3d_shader_src", ccm_base + 0x8200, 24, 3, imx8mp_gpu3d_shader_sels, array_size(imx8mp_gpu3d_shader_sels)); + hws[imx8mp_clk_gpu2d_src] = imx_clk_hw_mux2("gpu2d_src", ccm_base + 0x8280, 24, 3, imx8mp_gpu2d_sels, array_size(imx8mp_gpu2d_sels)); + hws[imx8mp_clk_audio_axi_src] = imx_clk_hw_mux2("audio_axi_src", ccm_base + 0x8300, 24, 3, imx8mp_audio_axi_sels, array_size(imx8mp_audio_axi_sels)); + hws[imx8mp_clk_hsio_axi_src] = imx_clk_hw_mux2("hsio_axi_src", ccm_base + 0x8380, 24, 3, imx8mp_hsio_axi_sels, array_size(imx8mp_hsio_axi_sels)); + hws[imx8mp_clk_media_isp_src] = imx_clk_hw_mux2("media_isp_src", ccm_base + 0x8400, 24, 3, imx8mp_media_isp_sels, array_size(imx8mp_media_isp_sels)); + hws[imx8mp_clk_a53_cg] = imx_clk_hw_gate3("arm_a53_cg", "arm_a53_src", ccm_base + 0x8000, 28); + hws[imx8mp_clk_m4_cg] = imx_clk_hw_gate3("arm_m7_cg", "arm_m7_src", ccm_base + 0x8080, 28); + hws[imx8mp_clk_ml_cg] = imx_clk_hw_gate3("ml_cg", "ml_src", ccm_base + 0x8100, 28); + hws[imx8mp_clk_gpu3d_core_cg] = imx_clk_hw_gate3("gpu3d_core_cg", "gpu3d_core_src", ccm_base + 0x8180, 28); + hws[imx8mp_clk_gpu3d_shader_cg] = imx_clk_hw_gate3("gpu3d_shader_cg", "gpu3d_shader_src", ccm_base + 0x8200, 28); + hws[imx8mp_clk_gpu2d_cg] = imx_clk_hw_gate3("gpu2d_cg", "gpu2d_src", ccm_base + 0x8280, 28); + hws[imx8mp_clk_audio_axi_cg] = imx_clk_hw_gate3("audio_axi_cg", "audio_axi_src", ccm_base + 0x8300, 28); + hws[imx8mp_clk_hsio_axi_cg] = imx_clk_hw_gate3("hsio_axi_cg", "hsio_axi_src", ccm_base + 0x8380, 28); + hws[imx8mp_clk_media_isp_cg] = imx_clk_hw_gate3("media_isp_cg", "media_isp_src", ccm_base + 0x8400, 28); + hws[imx8mp_clk_a53_div] = imx_clk_hw_divider2("arm_a53_div", "arm_a53_cg", ccm_base + 0x8000, 0, 3); + hws[imx8mp_clk_m7_div] = imx_clk_hw_divider2("arm_m7_div", "arm_m7_cg", ccm_base + 0x8080, 0, 3); + hws[imx8mp_clk_ml_div] = imx_clk_hw_divider2("ml_div", "ml_cg", ccm_base + 0x8100, 0, 3); + hws[imx8mp_clk_gpu3d_core_div] = imx_clk_hw_divider2("gpu3d_core_div", "gpu3d_core_cg", ccm_base + 0x8180, 0, 3); + hws[imx8mp_clk_gpu3d_shader_div] = imx_clk_hw_divider2("gpu3d_shader_div", "gpu3d_shader_cg", ccm_base + 0x8200, 0, 3); + hws[imx8mp_clk_gpu2d_div] = imx_clk_hw_divider2("gpu2d_div", "gpu2d_cg", ccm_base + 0x8280, 0, 3); + hws[imx8mp_clk_audio_axi_div] = imx_clk_hw_divider2("audio_axi_div", "audio_axi_cg", ccm_base + 0x8300, 0, 3); + hws[imx8mp_clk_hsio_axi_div] = imx_clk_hw_divider2("hsio_axi_div", "hsio_axi_cg", ccm_base + 0x8380, 0, 3); + hws[imx8mp_clk_media_isp_div] = imx_clk_hw_divider2("media_isp_div", "media_isp_cg", ccm_base + 0x8400, 0, 3); + + hws[imx8mp_clk_main_axi] = imx8m_clk_hw_composite_critical("main_axi", imx8mp_main_axi_sels, ccm_base + 0x8800); + hws[imx8mp_clk_enet_axi] = imx8m_clk_hw_composite("enet_axi", imx8mp_enet_axi_sels, ccm_base + 0x8880); + hws[imx8mp_clk_nand_usdhc_bus] = imx8m_clk_hw_composite_critical("nand_usdhc_bus", imx8mp_nand_usdhc_sels, ccm_base + 0x8900); + hws[imx8mp_clk_vpu_bus] = imx8m_clk_hw_composite("vpu_bus", imx8mp_vpu_bus_sels, ccm_base + 0x8980); + hws[imx8mp_clk_media_axi] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00); + hws[imx8mp_clk_media_apb] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80); + hws[imx8mp_clk_hdmi_apb] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00); + hws[imx8mp_clk_hdmi_axi] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_apb_sels, ccm_base + 0x8b80); + hws[imx8mp_clk_gpu_axi] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00); + hws[imx8mp_clk_gpu_ahb] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80); + hws[imx8mp_clk_noc] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00); + hws[imx8mp_clk_noc_io] = imx8m_clk_hw_composite_critical("noc_io", imx8mp_noc_io_sels, ccm_base + 0x8d80); + hws[imx8mp_clk_ml_axi] = imx8m_clk_hw_composite("ml_axi", imx8mp_ml_axi_sels, ccm_base + 0x8e00); + hws[imx8mp_clk_ml_ahb] = imx8m_clk_hw_composite("ml_ahb", imx8mp_ml_ahb_sels, ccm_base + 0x8e80); + + hws[imx8mp_clk_ahb] = imx8m_clk_hw_composite_critical("ahb_root", imx8mp_ahb_sels, ccm_base + 0x9000); + hws[imx8mp_clk_audio_ahb] = imx8m_clk_hw_composite("audio_ahb", imx8mp_audio_ahb_sels, ccm_base + 0x9100); + hws[imx8mp_clk_mipi_dsi_esc_rx] = imx8m_clk_hw_composite("mipi_dsi_esc_rx", imx8mp_mipi_dsi_esc_rx_sels, ccm_base + 0x9200); + + hws[imx8mp_clk_ipg_root] = imx_clk_hw_divider2("ipg_root", "ahb_root", ccm_base + 0x9080, 0, 1); + hws[imx8mp_clk_ipg_audio_root] = imx_clk_hw_divider2("ipg_audio_root", "audio_ahb", ccm_base + 0x9180, 0, 1); + + hws[imx8mp_clk_dram_alt] = imx8m_clk_hw_composite("dram_alt", imx8mp_dram_alt_sels, ccm_base + 0xa000); + hws[imx8mp_clk_dram_apb] = imx8m_clk_hw_composite_critical("dram_apb", imx8mp_dram_apb_sels, ccm_base + 0xa080); + hws[imx8mp_clk_vpu_g1] = imx8m_clk_hw_composite("vpu_g1", imx8mp_vpu_g1_sels, ccm_base + 0xa100); + hws[imx8mp_clk_vpu_g2] = imx8m_clk_hw_composite("vpu_g2", imx8mp_vpu_g2_sels, ccm_base + 0xa180); + hws[imx8mp_clk_can1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, ccm_base + 0xa200); + hws[imx8mp_clk_can2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, ccm_base + 0xa280); + hws[imx8mp_clk_memrepair] = imx8m_clk_hw_composite("memrepair", imx8mp_memrepair_sels, ccm_base + 0xa300); + hws[imx8mp_clk_pcie_phy] = imx8m_clk_hw_composite("pcie_phy", imx8mp_pcie_phy_sels, ccm_base + 0xa380); + hws[imx8mp_clk_pcie_aux] = imx8m_clk_hw_composite("pcie_aux", imx8mp_pcie_aux_sels, ccm_base + 0xa400); + hws[imx8mp_clk_i2c5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, ccm_base + 0xa480); + hws[imx8mp_clk_i2c6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, ccm_base + 0xa500); + hws[imx8mp_clk_sai1] = imx8m_clk_hw_composite("sai1", imx8mp_sai1_sels, ccm_base + 0xa580); + hws[imx8mp_clk_sai2] = imx8m_clk_hw_composite("sai2", imx8mp_sai2_sels, ccm_base + 0xa600); + hws[imx8mp_clk_sai3] = imx8m_clk_hw_composite("sai3", imx8mp_sai3_sels, ccm_base + 0xa680); + hws[imx8mp_clk_sai4] = imx8m_clk_hw_composite("sai4", imx8mp_sai4_sels, ccm_base + 0xa700); + hws[imx8mp_clk_sai5] = imx8m_clk_hw_composite("sai5", imx8mp_sai5_sels, ccm_base + 0xa780); + hws[imx8mp_clk_sai6] = imx8m_clk_hw_composite("sai6", imx8mp_sai6_sels, ccm_base + 0xa800); + hws[imx8mp_clk_enet_qos] = imx8m_clk_hw_composite("enet_qos", imx8mp_enet_qos_sels, ccm_base + 0xa880); + hws[imx8mp_clk_enet_qos_timer] = imx8m_clk_hw_composite("enet_qos_timer", imx8mp_enet_qos_timer_sels, ccm_base + 0xa900); + hws[imx8mp_clk_enet_ref] = imx8m_clk_hw_composite("enet_ref", imx8mp_enet_ref_sels, ccm_base + 0xa980); + hws[imx8mp_clk_enet_timer] = imx8m_clk_hw_composite("enet_timer", imx8mp_enet_timer_sels, ccm_base + 0xaa00); + hws[imx8mp_clk_enet_phy_ref] = imx8m_clk_hw_composite("enet_phy_ref", imx8mp_enet_phy_ref_sels, ccm_base + 0xaa80); + hws[imx8mp_clk_nand] = imx8m_clk_hw_composite("nand", imx8mp_nand_sels, ccm_base + 0xab00); + hws[imx8mp_clk_qspi] = imx8m_clk_hw_composite("qspi", imx8mp_qspi_sels, ccm_base + 0xab80); + hws[imx8mp_clk_usdhc1] = imx8m_clk_hw_composite("usdhc1", imx8mp_usdhc1_sels, ccm_base + 0xac00); + hws[imx8mp_clk_usdhc2] = imx8m_clk_hw_composite("usdhc2", imx8mp_usdhc2_sels, ccm_base + 0xac80); + hws[imx8mp_clk_i2c1] = imx8m_clk_hw_composite("i2c1", imx8mp_i2c1_sels, ccm_base + 0xad00); + hws[imx8mp_clk_i2c2] = imx8m_clk_hw_composite("i2c2", imx8mp_i2c2_sels, ccm_base + 0xad80); + hws[imx8mp_clk_i2c3] = imx8m_clk_hw_composite("i2c3", imx8mp_i2c3_sels, ccm_base + 0xae00); + hws[imx8mp_clk_i2c4] = imx8m_clk_hw_composite("i2c4", imx8mp_i2c4_sels, ccm_base + 0xae80); + + hws[imx8mp_clk_uart1] = imx8m_clk_hw_composite("uart1", imx8mp_uart1_sels, ccm_base + 0xaf00); + hws[imx8mp_clk_uart2] = imx8m_clk_hw_composite("uart2", imx8mp_uart2_sels, ccm_base + 0xaf80); + hws[imx8mp_clk_uart3] = imx8m_clk_hw_composite("uart3", imx8mp_uart3_sels, ccm_base + 0xb000); + hws[imx8mp_clk_uart4] = imx8m_clk_hw_composite("uart4", imx8mp_uart4_sels, ccm_base + 0xb080); + hws[imx8mp_clk_usb_core_ref] = imx8m_clk_hw_composite("usb_core_ref", imx8mp_usb_core_ref_sels, ccm_base + 0xb100); + hws[imx8mp_clk_usb_phy_ref] = imx8m_clk_hw_composite("usb_phy_ref", imx8mp_usb_phy_ref_sels, ccm_base + 0xb180); + hws[imx8mp_clk_gic] = imx8m_clk_hw_composite_critical("gic", imx8mp_gic_sels, ccm_base + 0xb200); + hws[imx8mp_clk_ecspi1] = imx8m_clk_hw_composite("ecspi1", imx8mp_ecspi1_sels, ccm_base + 0xb280); + hws[imx8mp_clk_ecspi2] = imx8m_clk_hw_composite("ecspi2", imx8mp_ecspi2_sels, ccm_base + 0xb300); + hws[imx8mp_clk_pwm1] = imx8m_clk_hw_composite("pwm1", imx8mp_pwm1_sels, ccm_base + 0xb380); + hws[imx8mp_clk_pwm2] = imx8m_clk_hw_composite("pwm2", imx8mp_pwm2_sels, ccm_base + 0xb400); + hws[imx8mp_clk_pwm3] = imx8m_clk_hw_composite("pwm3", imx8mp_pwm3_sels, ccm_base + 0xb480); + hws[imx8mp_clk_pwm4] = imx8m_clk_hw_composite("pwm4", imx8mp_pwm4_sels, ccm_base + 0xb500); + + hws[imx8mp_clk_gpt1] = imx8m_clk_hw_composite("gpt1", imx8mp_gpt1_sels, ccm_base + 0xb580); + hws[imx8mp_clk_gpt2] = imx8m_clk_hw_composite("gpt2", imx8mp_gpt2_sels, ccm_base + 0xb600); + hws[imx8mp_clk_gpt3] = imx8m_clk_hw_composite("gpt3", imx8mp_gpt3_sels, ccm_base + 0xb680); + hws[imx8mp_clk_gpt4] = imx8m_clk_hw_composite("gpt4", imx8mp_gpt4_sels, ccm_base + 0xb700); + hws[imx8mp_clk_gpt5] = imx8m_clk_hw_composite("gpt5", imx8mp_gpt5_sels, ccm_base + 0xb780); + hws[imx8mp_clk_gpt6] = imx8m_clk_hw_composite("gpt6", imx8mp_gpt6_sels, ccm_base + 0xb800); + hws[imx8mp_clk_wdog] = imx8m_clk_hw_composite("wdog", imx8mp_wdog_sels, ccm_base + 0xb900); + hws[imx8mp_clk_wrclk] = imx8m_clk_hw_composite("wrclk", imx8mp_wrclk_sels, ccm_base + 0xb980); + hws[imx8mp_clk_ipp_do_clko1] = imx8m_clk_hw_composite("ipp_do_clko1", imx8mp_ipp_do_clko1_sels, ccm_base + 0xba00); + hws[imx8mp_clk_ipp_do_clko2] = imx8m_clk_hw_composite("ipp_do_clko2", imx8mp_ipp_do_clko2_sels, ccm_base + 0xba80); + hws[imx8mp_clk_hdmi_fdcc_tst] = imx8m_clk_hw_composite("hdmi_fdcc_tst", imx8mp_hdmi_fdcc_tst_sels, ccm_base + 0xbb00); + hws[imx8mp_clk_hdmi_27m] = imx8m_clk_hw_composite("hdmi_27m", imx8mp_hdmi_27m_sels, ccm_base + 0xbb80); + hws[imx8mp_clk_hdmi_ref_266m] = imx8m_clk_hw_composite("hdmi_ref_266m", imx8mp_hdmi_ref_266m_sels, ccm_base + 0xbc00); + hws[imx8mp_clk_usdhc3] = imx8m_clk_hw_composite("usdhc3", imx8mp_usdhc3_sels, ccm_base + 0xbc80); + hws[imx8mp_clk_media_cam1_pix] = imx8m_clk_hw_composite("media_cam1_pix", imx8mp_media_cam1_pix_sels, ccm_base + 0xbd00); + hws[imx8mp_clk_media_mipi_phy1_ref] = imx8m_clk_hw_composite("media_mipi_phy1_ref", imx8mp_media_mipi_phy1_ref_sels, ccm_base + 0xbd80); + hws[imx8mp_clk_media_disp1_pix] = imx8m_clk_hw_composite("media_disp1_pix", imx8mp_media_disp1_pix_sels, ccm_base + 0xbe00); + hws[imx8mp_clk_media_cam2_pix] = imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 0xbe80); + hws[imx8mp_clk_media_mipi_phy2_ref] = imx8m_clk_hw_composite("media_mipi_phy2_ref", imx8mp_media_mipi_phy2_ref_sels, ccm_base + 0xbf00); + hws[imx8mp_clk_media_mipi_csi2_esc] = imx8m_clk_hw_composite("media_mipi_csi2_esc", imx8mp_media_mipi_csi2_esc_sels, ccm_base + 0xbf80); + hws[imx8mp_clk_pcie2_ctrl] = imx8m_clk_hw_composite("pcie2_ctrl", imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000); + hws[imx8mp_clk_pcie2_phy] = imx8m_clk_hw_composite("pcie2_phy", imx8mp_pcie2_phy_sels, ccm_base + 0xc080); + hws[imx8mp_clk_media_mipi_test_byte] = imx8m_clk_hw_composite("media_mipi_test_byte", imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100); + hws[imx8mp_clk_ecspi3] = imx8m_clk_hw_composite("ecspi3", imx8mp_ecspi3_sels, ccm_base + 0xc180); + hws[imx8mp_clk_pdm] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, ccm_base + 0xc200); + hws[imx8mp_clk_vpu_vc8000e] = imx8m_clk_hw_composite("vpu_vc8000e", imx8mp_vpu_vc8000e_sels, ccm_base + 0xc280); + hws[imx8mp_clk_sai7] = imx8m_clk_hw_composite("sai7", imx8mp_sai7_sels, ccm_base + 0xc300); + + hws[imx8mp_clk_dram_alt_root] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4); + hws[imx8mp_clk_dram_core] = imx_clk_hw_mux2_flags("dram_core_clk", ccm_base + 0x9800, 24, 1, imx8mp_dram_core_sels, array_size(imx8mp_dram_core_sels), clk_is_critical); + + hws[imx8mp_clk_dram1_root] = imx_clk_hw_gate4_flags("dram1_root_clk", "dram_core_clk", ccm_base + 0x4050, 0, clk_is_critical); + hws[imx8mp_clk_ecspi1_root] = imx_clk_hw_gate4("ecspi1_root_clk", "ecspi1", ccm_base + 0x4070, 0); + hws[imx8mp_clk_ecspi2_root] = imx_clk_hw_gate4("ecspi2_root_clk", "ecspi2", ccm_base + 0x4080, 0); + hws[imx8mp_clk_ecspi3_root] = imx_clk_hw_gate4("ecspi3_root_clk", "ecspi3", ccm_base + 0x4090, 0); + hws[imx8mp_clk_enet1_root] = imx_clk_hw_gate4("enet1_root_clk", "enet_axi", ccm_base + 0x40a0, 0); + hws[imx8mp_clk_gpio1_root] = imx_clk_hw_gate4("gpio1_root_clk", "ipg_root", ccm_base + 0x40b0, 0); + hws[imx8mp_clk_gpio2_root] = imx_clk_hw_gate4("gpio2_root_clk", "ipg_root", ccm_base + 0x40c0, 0); + hws[imx8mp_clk_gpio3_root] = imx_clk_hw_gate4("gpio3_root_clk", "ipg_root", ccm_base + 0x40d0, 0); + hws[imx8mp_clk_gpio4_root] = imx_clk_hw_gate4("gpio4_root_clk", "ipg_root", ccm_base + 0x40e0, 0); + hws[imx8mp_clk_gpio5_root] = imx_clk_hw_gate4("gpio5_root_clk", "ipg_root", ccm_base + 0x40f0, 0); + hws[imx8mp_clk_gpt1_root] = imx_clk_hw_gate4("gpt1_root_clk", "gpt1", ccm_base + 0x4100, 0); + hws[imx8mp_clk_gpt2_root] = imx_clk_hw_gate4("gpt2_root_clk", "gpt2", ccm_base + 0x4110, 0); + hws[imx8mp_clk_gpt3_root] = imx_clk_hw_gate4("gpt3_root_clk", "gpt3", ccm_base + 0x4120, 0); + hws[imx8mp_clk_gpt4_root] = imx_clk_hw_gate4("gpt4_root_clk", "gpt4", ccm_base + 0x4130, 0); + hws[imx8mp_clk_gpt5_root] = imx_clk_hw_gate4("gpt5_root_clk", "gpt5", ccm_base + 0x4140, 0); + hws[imx8mp_clk_gpt6_root] = imx_clk_hw_gate4("gpt6_root_clk", "gpt6", ccm_base + 0x4150, 0); + hws[imx8mp_clk_i2c1_root] = imx_clk_hw_gate4("i2c1_root_clk", "i2c1", ccm_base + 0x4170, 0); + hws[imx8mp_clk_i2c2_root] = imx_clk_hw_gate4("i2c2_root_clk", "i2c2", ccm_base + 0x4180, 0); + hws[imx8mp_clk_i2c3_root] = imx_clk_hw_gate4("i2c3_root_clk", "i2c3", ccm_base + 0x4190, 0); + hws[imx8mp_clk_i2c4_root] = imx_clk_hw_gate4("i2c4_root_clk", "i2c4", ccm_base + 0x41a0, 0); + hws[imx8mp_clk_pcie_root] = imx_clk_hw_gate4("pcie_root_clk", "pcie_aux", ccm_base + 0x4250, 0); + hws[imx8mp_clk_pwm1_root] = imx_clk_hw_gate4("pwm1_root_clk", "pwm1", ccm_base + 0x4280, 0); + hws[imx8mp_clk_pwm2_root] = imx_clk_hw_gate4("pwm2_root_clk", "pwm2", ccm_base + 0x4290, 0); + hws[imx8mp_clk_pwm3_root] = imx_clk_hw_gate4("pwm3_root_clk", "pwm3", ccm_base + 0x42a0, 0); + hws[imx8mp_clk_pwm4_root] = imx_clk_hw_gate4("pwm4_root_clk", "pwm4", ccm_base + 0x42b0, 0); + hws[imx8mp_clk_qos_root] = imx_clk_hw_gate4("qos_root_clk", "ipg_root", ccm_base + 0x42c0, 0); + hws[imx8mp_clk_qos_enet_root] = imx_clk_hw_gate4("qos_enet_root_clk", "ipg_root", ccm_base + 0x42e0, 0); + hws[imx8mp_clk_qspi_root] = imx_clk_hw_gate4("qspi_root_clk", "qspi", ccm_base + 0x42f0, 0); + hws[imx8mp_clk_nand_root] = imx_clk_hw_gate2_shared2("nand_root_clk", "nand", ccm_base + 0x4300, 0, &share_count_nand); + hws[imx8mp_clk_nand_usdhc_bus_rawnand_clk] = imx_clk_hw_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_bus", ccm_base + 0x4300, 0, &share_count_nand); + hws[imx8mp_clk_i2c5_root] = imx_clk_hw_gate2("i2c5_root_clk", "i2c5", ccm_base + 0x4330, 0); + hws[imx8mp_clk_i2c6_root] = imx_clk_hw_gate2("i2c6_root_clk", "i2c6", ccm_base + 0x4340, 0); + hws[imx8mp_clk_can1_root] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0); + hws[imx8mp_clk_can2_root] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0); + hws[imx8mp_clk_sdma1_root] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0); + hws[imx8mp_clk_enet_qos_root] = imx_clk_hw_gate4("enet_qos_root_clk", "enet_axi", ccm_base + 0x43b0, 0); + hws[imx8mp_clk_sim_enet_root] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0); + hws[imx8mp_clk_gpu2d_root] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0); + hws[imx8mp_clk_gpu3d_root] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0); + hws[imx8mp_clk_snvs_root] = imx_clk_hw_gate4("snvs_root_clk", "ipg_root", ccm_base + 0x4470, 0); + hws[imx8mp_clk_uart1_root] = imx_clk_hw_gate4("uart1_root_clk", "uart1", ccm_base + 0x4490, 0); + hws[imx8mp_clk_uart2_root] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0); + hws[imx8mp_clk_uart3_root] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0); + hws[imx8mp_clk_uart4_root] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0); + hws[imx8mp_clk_usb_root] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0); + hws[imx8mp_clk_usb_phy_root] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0); + hws[imx8mp_clk_usdhc1_root] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0); + hws[imx8mp_clk_usdhc2_root] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0); + hws[imx8mp_clk_wdog1_root] = imx_clk_hw_gate4("wdog1_root_clk", "wdog", ccm_base + 0x4530, 0); + hws[imx8mp_clk_wdog2_root] = imx_clk_hw_gate4("wdog2_root_clk", "wdog", ccm_base + 0x4540, 0); + hws[imx8mp_clk_wdog3_root] = imx_clk_hw_gate4("wdog3_root_clk", "wdog", ccm_base + 0x4550, 0); + hws[imx8mp_clk_vpu_g1_root] = imx_clk_hw_gate4("vpu_g1_root_clk", "vpu_g1", ccm_base + 0x4560, 0); + hws[imx8mp_clk_gpu_root] = imx_clk_hw_gate4("gpu_root_clk", "gpu_axi", ccm_base + 0x4570, 0); + hws[imx8mp_clk_vpu_vc8ke_root] = imx_clk_hw_gate4("vpu_vc8ke_root_clk", "vpu_vc8000e", ccm_base + 0x4590, 0); + hws[imx8mp_clk_vpu_g2_root] = imx_clk_hw_gate4("vpu_g2_root_clk", "vpu_g2", ccm_base + 0x45a0, 0); + hws[imx8mp_clk_npu_root] = imx_clk_hw_gate4("npu_root_clk", "ml_div", ccm_base + 0x45b0, 0); + hws[imx8mp_clk_hsio_root] = imx_clk_hw_gate4("hsio_root_clk", "ipg_root", ccm_base + 0x45c0, 0); + hws[imx8mp_clk_media_apb_root] = imx_clk_hw_gate2_shared2("media_apb_root_clk", "media_apb", ccm_base + 0x45d0, 0, &share_count_media); + hws[imx8mp_clk_media_axi_root] = imx_clk_hw_gate2_shared2("media_axi_root_clk", "media_axi", ccm_base + 0x45d0, 0, &share_count_media); + hws[imx8mp_clk_media_cam1_pix_root] = imx_clk_hw_gate2_shared2("media_cam1_pix_root_clk", "media_cam1_pix", ccm_base + 0x45d0, 0, &share_count_media); + hws[imx8mp_clk_media_cam2_pix_root] = imx_clk_hw_gate2_shared2("media_cam2_pix_root_clk", "media_cam2_pix", ccm_base + 0x45d0, 0, &share_count_media); + hws[imx8mp_clk_media_disp1_pix_root] = imx_clk_hw_gate2_shared2("media_disp1_pix_root_clk", "media_disp1_pix", ccm_base + 0x45d0, 0, &share_count_media); + hws[imx8mp_clk_media_disp2_pix_root] = imx_clk_hw_gate2_shared2("media_disp2_pix_root_clk", "media_disp2_pix", ccm_base + 0x45d0, 0, &share_count_media); + hws[imx8mp_clk_media_isp_root] = imx_clk_hw_gate2_shared2("media_isp_root_clk", "media_isp_div", ccm_base + 0x45d0, 0, &share_count_media); + + hws[imx8mp_clk_usdhc3_root] = imx_clk_hw_gate4("usdhc3_root_clk", "usdhc3", ccm_base + 0x45e0, 0); + hws[imx8mp_clk_hdmi_root] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0); + hws[imx8mp_clk_tsensor_root] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0); + hws[imx8mp_clk_vpu_root] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0); + hws[imx8mp_clk_audio_root] = imx_clk_hw_gate4("audio_root_clk", "ipg_root", ccm_base + 0x4650, 0); + + hws[imx8mp_clk_arm] = imx_clk_hw_cpu("arm", "arm_a53_div", + hws[imx8mp_clk_a53_div]->clk, + hws[imx8mp_clk_a53_src]->clk, + hws[imx8mp_arm_pll_out]->clk, + hws[imx8mp_sys_pll1_800m]->clk); + + imx_check_clk_hws(hws, imx8mp_clk_end); + + of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); + + for (i = 0; i < array_size(uart_clk_ids); i++) { + int index = uart_clk_ids[i]; + + uart_clks[i] = &hws[index]->clk; + } + + imx_register_uart_clocks(uart_clks); + + return 0; +} + +static const struct of_device_id imx8mp_clk_of_match[] = { + { .compatible = "fsl,imx8mp-ccm" }, + { /* sentinel */ } +}; +module_device_table(of, imx8mp_clk_of_match); + +static struct platform_driver imx8mp_clk_driver = { + .probe = imx8mp_clocks_probe, + .driver = { + .name = "imx8mp-ccm", + /* + * disable bind attributes: clocks are not removed and + * reloading the driver will crash or break devices. + */ + .suppress_bind_attrs = true, + .of_match_table = of_match_ptr(imx8mp_clk_of_match), + }, +}; +module_platform_driver(imx8mp_clk_driver); | Clock | 9c140d9926761b0f5d329ff6c09a1540f3d5e1d3 | anson huang abel vesa abel vesa nxp com | drivers | clk | imx |
clk: ls1028a: add clock driver for display output interface | add clock driver for qoriq ls1028a display output interfaces(lcd, dphy), as implemented in tsmc cln28hpm pll, this pll supports the programmable integer division and range of the display output pixel clock's 27-594mhz. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add clock driver for display output interface | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['ls1028a'] | ['c', 'kconfig', 'makefile'] | 3 | 297 | 0 | --- diff --git a/drivers/clk/kconfig b/drivers/clk/kconfig --- a/drivers/clk/kconfig +++ b/drivers/clk/kconfig +config clk_ls1028a_plldig + tristate "clock driver for ls1028a display output" + depends on arch_layerscape || compile_test + default arch_layerscape + help + this driver support the display output interfaces(lcd, dphy) pixel clocks + of the qoriq layerscape ls1028a, as implemented tsmc cln28hpm pll. not all + features of the pll are currently supported by the driver. by default, + configured bypass mode with this pll. + diff --git a/drivers/clk/makefile b/drivers/clk/makefile --- a/drivers/clk/makefile +++ b/drivers/clk/makefile +obj-$(config_clk_ls1028a_plldig) += clk-plldig.o diff --git a/drivers/clk/clk-plldig.c b/drivers/clk/clk-plldig.c --- /dev/null +++ b/drivers/clk/clk-plldig.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright 2019 nxp + * + * clock driver for ls1028a display output interfaces(lcd, dphy). + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/module.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/bitfield.h> + +/* plldig register offsets and bit masks */ +#define plldig_reg_pllsr 0x24 +#define plldig_lock_mask bit(2) +#define plldig_reg_plldv 0x28 +#define plldig_mfd_mask genmask(7, 0) +#define plldig_rfdphi1_mask genmask(30, 25) +#define plldig_reg_pllfm 0x2c +#define plldig_sscgbyp_enable bit(30) +#define plldig_reg_pllfd 0x30 +#define plldig_fden bit(30) +#define plldig_frac_mask genmask(15, 0) +#define plldig_reg_pllcal1 0x38 +#define plldig_reg_pllcal2 0x3c + +/* range of the vco frequencies, in hz */ +#define plldig_min_vco_freq 650000000 +#define plldig_max_vco_freq 1300000000 + +/* range of the output frequencies, in hz */ +#define phi1_min_freq 27000000 +#define phi1_max_freq 600000000 + +/* maximum value of the reduced frequency divider */ +#define max_rfdphi1 63ul + +/* best value of multiplication factor divider */ +#define plldig_default_mfd 44 + +/* + * denominator part of the fractional part of the + * loop multiplication factor. + */ +#define mfden 20480 + +static const struct clk_parent_data parent_data[] = { + { .index = 0 }, +}; + +struct clk_plldig { + struct clk_hw hw; + void __iomem *regs; + unsigned int vco_freq; +}; + +#define to_clk_plldig(_hw) container_of(_hw, struct clk_plldig, hw) + +static int plldig_enable(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val; + + val = readl(data->regs + plldig_reg_pllfm); + /* + * use bypass mode with pll off by default, the frequency overshoot + * detector output was disable. sscg bypass mode should be enable. + */ + val |= plldig_sscgbyp_enable; + writel(val, data->regs + plldig_reg_pllfm); + + return 0; +} + +static void plldig_disable(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val; + + val = readl(data->regs + plldig_reg_pllfm); + + val &= ~plldig_sscgbyp_enable; + val |= field_prep(plldig_sscgbyp_enable, 0x0); + + writel(val, data->regs + plldig_reg_pllfm); +} + +static int plldig_is_enabled(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + + return readl(data->regs + plldig_reg_pllfm) & + plldig_sscgbyp_enable; +} + +static unsigned long plldig_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_plldig *data = to_clk_plldig(hw); + u32 val, rfdphi1; + + val = readl(data->regs + plldig_reg_plldv); + + /* check if pll is bypassed */ + if (val & plldig_sscgbyp_enable) + return parent_rate; + + rfdphi1 = field_get(plldig_rfdphi1_mask, val); + + /* + * if rfdphi1 has a value of 1 the vco frequency is also divided by + * one. + */ + if (!rfdphi1) + rfdphi1 = 1; + + return div_round_up(data->vco_freq, rfdphi1); +} + +static unsigned long plldig_calc_target_div(unsigned long vco_freq, + unsigned long target_rate) +{ + unsigned long div; + + div = div_round_closest(vco_freq, target_rate); + div = clamp(div, 1ul, max_rfdphi1); + + return div; +} + +static int plldig_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct clk_plldig *data = to_clk_plldig(hw); + unsigned int div; + + req->rate = clamp(req->rate, phi1_min_freq, phi1_max_freq); + div = plldig_calc_target_div(data->vco_freq, req->rate); + req->rate = div_round_up(data->vco_freq, div); + + return 0; +} + +static int plldig_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_plldig *data = to_clk_plldig(hw); + unsigned int val, cond; + unsigned int rfdphi1; + + rate = clamp(rate, phi1_min_freq, phi1_max_freq); + rfdphi1 = plldig_calc_target_div(data->vco_freq, rate); + + /* update the divider value */ + val = readl(data->regs + plldig_reg_plldv); + val &= ~plldig_rfdphi1_mask; + val |= field_prep(plldig_rfdphi1_mask, rfdphi1); + writel(val, data->regs + plldig_reg_plldv); + + /* waiting for old lock state to clear */ + udelay(200); + + /* wait until pll is locked or timeout */ + return readl_poll_timeout_atomic(data->regs + plldig_reg_pllsr, cond, + cond & plldig_lock_mask, 0, + usec_per_msec); +} + +static const struct clk_ops plldig_clk_ops = { + .enable = plldig_enable, + .disable = plldig_disable, + .is_enabled = plldig_is_enabled, + .recalc_rate = plldig_recalc_rate, + .determine_rate = plldig_determine_rate, + .set_rate = plldig_set_rate, +}; + +static int plldig_init(struct clk_hw *hw) +{ + struct clk_plldig *data = to_clk_plldig(hw); + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + unsigned long val; + unsigned long long lltmp; + unsigned int mfd, fracdiv = 0; + + if (!parent) + return -einval; + + if (data->vco_freq) { + mfd = data->vco_freq / parent_rate; + lltmp = data->vco_freq % parent_rate; + lltmp *= mfden; + do_div(lltmp, parent_rate); + fracdiv = lltmp; + } else { + mfd = plldig_default_mfd; + data->vco_freq = parent_rate * mfd; + } + + val = field_prep(plldig_mfd_mask, mfd); + writel(val, data->regs + plldig_reg_plldv); + + /* enable fractional divider */ + if (fracdiv) { + val = field_prep(plldig_frac_mask, fracdiv); + val |= plldig_fden; + writel(val, data->regs + plldig_reg_pllfd); + } + + return 0; +} + +static int plldig_clk_probe(struct platform_device *pdev) +{ + struct clk_plldig *data; + struct device *dev = &pdev->dev; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + data->regs = devm_platform_ioremap_resource(pdev, 0); + if (is_err(data->regs)) + return ptr_err(data->regs); + + data->hw.init = clk_hw_init_parents_data("dpclk", + parent_data, + &plldig_clk_ops, + 0); + + ret = devm_clk_hw_register(dev, &data->hw); + if (ret) { + dev_err(dev, "failed to register %s clock ", + dev->of_node->name); + return ret; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, + &data->hw); + if (ret) { + dev_err(dev, "unable to add clk provider "); + return ret; + } + + /* + * the frequency of the vco cannot be changed during runtime. + * therefore, let the user specify a desired frequency. + */ + if (!of_property_read_u32(dev->of_node, "fsl,vco-hz", + &data->vco_freq)) { + if (data->vco_freq < plldig_min_vco_freq || + data->vco_freq > plldig_max_vco_freq) + return -einval; + } + + return plldig_init(&data->hw); +} + +static const struct of_device_id plldig_clk_id[] = { + { .compatible = "fsl,ls1028a-plldig" }, + { } +}; +module_device_table(of, plldig_clk_id); + +static struct platform_driver plldig_clk_driver = { + .driver = { + .name = "plldig-clock", + .of_match_table = plldig_clk_id, + }, + .probe = plldig_clk_probe, +}; +module_platform_driver(plldig_clk_driver); + +module_license("gpl v2"); +module_author("wen he <wen.he_1@nxp.com>"); +module_description("ls1028a display output interface pixel clock driver"); | Clock | d37010a3c162f23e47a11a8f5946dbd974999c42 | wen he | drivers | clk | |
clk: meson: add a driver for the meson8/8b/8m2 ddr clock controller | the meson8/meson8b/meson8m2 socs embed a ddr clock controller in the mmcbus registers. there is no public documentation, but the u-boot gpl sources from the amlogic bsp show that the ddr clock controller is identical on all three socs: #define cfg_ddr_clk 792 #define cfg_pll_m (((cfg_ddr_clk/12)*12)/24) #define cfg_pll_n 1 #define cfg_pll_od 1 | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add a driver for the meson8/8b/8m2 ddr clock controller | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['meson'] | ['c', 'makefile'] | 2 | 150 | 1 | - am_ddr_pll_cntl[29] is the reset bit - am_ddr_pll_cntl[30] is the enable bit - am_ddr_pll_cntl[31] is the lock bit - am_ddr_pll_cntl[8:0] is the m value (assuming the width is 9 bits - am_ddr_pll_cntl[13:9] is the n value (assuming the width is 5 bits - am_ddr_pll_cntl[17:16] is the od (assuming the width is 2 bits based --- diff --git a/drivers/clk/meson/makefile b/drivers/clk/meson/makefile --- a/drivers/clk/meson/makefile +++ b/drivers/clk/meson/makefile -obj-$(config_common_clk_meson8b) += meson8b.o +obj-$(config_common_clk_meson8b) += meson8b.o meson8-ddr.o diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c --- /dev/null +++ b/drivers/clk/meson/meson8-ddr.c +// spdx-license-identifier: gpl-2.0+ +/* + * amlogic meson8 ddr clock controller + * + * copyright (c) 2019 martin blumenstingl <martin.blumenstingl@googlemail.com> + */ + +#include <dt-bindings/clock/meson8-ddr-clkc.h> + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +#include "clk-regmap.h" +#include "clk-pll.h" + +#define am_ddr_pll_cntl 0x00 +#define am_ddr_pll_cntl1 0x04 +#define am_ddr_pll_cntl2 0x08 +#define am_ddr_pll_cntl3 0x0c +#define am_ddr_pll_cntl4 0x10 +#define am_ddr_pll_sts 0x14 +#define ddr_clk_cntl 0x18 +#define ddr_clk_sts 0x1c + +static struct clk_regmap meson8_ddr_pll_dco = { + .data = &(struct meson_clk_pll_data){ + .en = { + .reg_off = am_ddr_pll_cntl, + .shift = 30, + .width = 1, + }, + .m = { + .reg_off = am_ddr_pll_cntl, + .shift = 0, + .width = 9, + }, + .n = { + .reg_off = am_ddr_pll_cntl, + .shift = 9, + .width = 5, + }, + .l = { + .reg_off = am_ddr_pll_cntl, + .shift = 31, + .width = 1, + }, + .rst = { + .reg_off = am_ddr_pll_cntl, + .shift = 29, + .width = 1, + }, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll_dco", + .ops = &meson_clk_pll_ro_ops, + .parent_data = &(const struct clk_parent_data) { + .fw_name = "xtal", + }, + .num_parents = 1, + }, +}; + +static struct clk_regmap meson8_ddr_pll = { + .data = &(struct clk_regmap_div_data){ + .offset = am_ddr_pll_cntl, + .shift = 16, + .width = 2, + .flags = clk_divider_power_of_two, + }, + .hw.init = &(struct clk_init_data){ + .name = "ddr_pll", + .ops = &clk_regmap_divider_ro_ops, + .parent_hws = (const struct clk_hw *[]) { + &meson8_ddr_pll_dco.hw + }, + .num_parents = 1, + }, +}; + +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = { + .hws = { + [ddr_clkid_ddr_pll_dco] = &meson8_ddr_pll_dco.hw, + [ddr_clkid_ddr_pll] = &meson8_ddr_pll.hw, + }, + .num = 2, +}; + +static struct clk_regmap *const meson8_ddr_clk_regmaps[] = { + &meson8_ddr_pll_dco, + &meson8_ddr_pll, +}; + +static const struct regmap_config meson8_ddr_clkc_regmap_config = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = ddr_clk_sts, +}; + +static int meson8_ddr_clkc_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + void __iomem *base; + struct clk_hw *hw; + int ret, i; + + base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(base)) + return ptr_err(base); + + regmap = devm_regmap_init_mmio(&pdev->dev, base, + &meson8_ddr_clkc_regmap_config); + if (is_err(regmap)) + return ptr_err(regmap); + + /* populate regmap */ + for (i = 0; i < array_size(meson8_ddr_clk_regmaps); i++) + meson8_ddr_clk_regmaps[i]->map = regmap; + + /* register all clks */ + for (i = 0; i < meson8_ddr_clk_hw_onecell_data.num; i++) { + hw = meson8_ddr_clk_hw_onecell_data.hws[i]; + + ret = devm_clk_hw_register(&pdev->dev, hw); + if (ret) { + dev_err(&pdev->dev, "clock registration failed "); + return ret; + } + } + + return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_onecell_get, + &meson8_ddr_clk_hw_onecell_data); +} + +static const struct of_device_id meson8_ddr_clkc_match_table[] = { + { .compatible = "amlogic,meson8-ddr-clkc" }, + { .compatible = "amlogic,meson8b-ddr-clkc" }, + { /* sentinel */ } +}; + +static struct platform_driver meson8_ddr_clkc_driver = { + .probe = meson8_ddr_clkc_probe, + .driver = { + .name = "meson8-ddr-clkc", + .of_match_table = meson8_ddr_clkc_match_table, + }, +}; + +builtin_platform_driver(meson8_ddr_clkc_driver); | Clock | 64aa7008e957a0a60f1ca3227d85ad1e507252cd | martin blumenstingl | drivers | clk | meson |
clk: qcom: add msm8998 multimedia clock controller (mmcc) driver | add a driver for the multimedia clock controller found on msm8998 based devices. this should allow most multimedia device drivers to probe and control their clocks. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add msm8998 multimedia clock controller (mmcc) driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['qcom'] | ['c', 'kconfig', 'makefile'] | 3 | 2,923 | 0 | --- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config msm_mmcc_8998 + tristate "msm8998 multimedia clock controller" + select msm_gcc_8998 + select qcom_gdsc + help + support for the multimedia clock controller on msm8998 devices. + say y if you want to support multimedia devices such as display, + graphics, video encode/decode, camera, etc. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_msm_mmcc_8998) += mmcc-msm8998.o diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c --- /dev/null +++ b/drivers/clk/qcom/mmcc-msm8998.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019, the linux foundation. all rights reserved. + */ + +#include <linux/kernel.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/clk-provider.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#include <dt-bindings/clock/qcom,mmcc-msm8998.h> + +#include "common.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-alpha-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "reset.h" +#include "gdsc.h" + +enum { + p_xo, + p_gpll0, + p_gpll0_div, + p_mmpll0_out_even, + p_mmpll1_out_even, + p_mmpll3_out_even, + p_mmpll4_out_even, + p_mmpll5_out_even, + p_mmpll6_out_even, + p_mmpll7_out_even, + p_mmpll10_out_even, + p_dsi0pll, + p_dsi1pll, + p_dsi0pll_byte, + p_dsi1pll_byte, + p_hdmipll, + p_dpvco, + p_dplink, + p_core_bi_pll_test_se, +}; + +static struct clk_fixed_factor gpll0_div = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "mmss_gpll0_div", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "gpll0", + .name = "gpll0" + }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct clk_div_table post_div_table_fabia_even[] = { + { 0x0, 1 }, + { 0x1, 2 }, + { 0x3, 4 }, + { 0x7, 8 }, + { } +}; + +static struct clk_alpha_pll mmpll0 = { + .offset = 0xc000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr = { + .enable_reg = 0x1e0, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mmpll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll0_out_even = { + .offset = 0xc000, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll0_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll1 = { + .offset = 0xc050, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr = { + .enable_reg = 0x1e0, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "mmpll1", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll1_out_even = { + .offset = 0xc050, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll1_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll3 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll3", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll3_out_even = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll3_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll4 = { + .offset = 0x50, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll4", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll4_out_even = { + .offset = 0x50, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll4_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll5 = { + .offset = 0xa0, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll5", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll5_out_even = { + .offset = 0xa0, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll5_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll6 = { + .offset = 0xf0, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll6", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll6_out_even = { + .offset = 0xf0, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll6_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll7 = { + .offset = 0x140, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll7", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll7_out_even = { + .offset = 0x140, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll7_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static struct clk_alpha_pll mmpll10 = { + .offset = 0x190, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll10", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + .name = "xo" + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_fabia_ops, + }, +}; + +static struct clk_alpha_pll_postdiv mmpll10_out_even = { + .offset = 0x190, + .post_div_shift = 8, + .post_div_table = post_div_table_fabia_even, + .num_post_div = array_size(post_div_table_fabia_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "mmpll10_out_even", + .parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static const struct parent_map mmss_xo_hdmi_map[] = { + { p_xo, 0 }, + { p_hdmipll, 1 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_hdmi[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "hdmipll", .name = "hdmipll" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = { + { p_xo, 0 }, + { p_dsi0pll, 1 }, + { p_dsi1pll, 2 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "dsi0dsi", .name = "dsi0dsi" }, + { .fw_name = "dsi1dsi", .name = "dsi1dsi" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_dsibyte_map[] = { + { p_xo, 0 }, + { p_dsi0pll_byte, 1 }, + { p_dsi1pll_byte, 2 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_dsibyte[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "dsi0byte", .name = "dsi0byte" }, + { .fw_name = "dsi1byte", .name = "dsi1byte" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_dp_map[] = { + { p_xo, 0 }, + { p_dplink, 1 }, + { p_dpvco, 2 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_dp[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "dplink", .name = "dplink" }, + { .fw_name = "dpvco", .name = "dpvco" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll0_out_even, 1 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll0_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll0_out_even, 1 }, + { p_mmpll1_out_even, 2 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll0_out_even.clkr.hw }, + { .hw = &mmpll1_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll0_out_even, 1 }, + { p_mmpll5_out_even, 2 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll0_out_even.clkr.hw }, + { .hw = &mmpll5_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll0_out_even, 1 }, + { p_mmpll3_out_even, 3 }, + { p_mmpll6_out_even, 4 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll0_out_even.clkr.hw }, + { .hw = &mmpll3_out_even.clkr.hw }, + { .hw = &mmpll6_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll4_out_even, 1 }, + { p_mmpll7_out_even, 2 }, + { p_mmpll10_out_even, 3 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll4_out_even.clkr.hw }, + { .hw = &mmpll7_out_even.clkr.hw }, + { .hw = &mmpll10_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll0_out_even, 1 }, + { p_mmpll7_out_even, 2 }, + { p_mmpll10_out_even, 3 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll0_out_even.clkr.hw }, + { .hw = &mmpll7_out_even.clkr.hw }, + { .hw = &mmpll10_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = { + { p_xo, 0 }, + { p_mmpll0_out_even, 1 }, + { p_mmpll4_out_even, 2 }, + { p_mmpll7_out_even, 3 }, + { p_mmpll10_out_even, 4 }, + { p_gpll0, 5 }, + { p_gpll0_div, 6 }, + { p_core_bi_pll_test_se, 7 } +}; + +static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = { + { .fw_name = "xo", .name = "xo" }, + { .hw = &mmpll0_out_even.clkr.hw }, + { .hw = &mmpll4_out_even.clkr.hw }, + { .hw = &mmpll7_out_even.clkr.hw }, + { .hw = &mmpll10_out_even.clkr.hw }, + { .fw_name = "gpll0", .name = "gpll0" }, + { .hw = &gpll0_div.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static struct clk_rcg2 byte0_clk_src = { + .cmd_rcgr = 0x2120, + .hid_width = 5, + .parent_map = mmss_xo_dsibyte_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte0_clk_src", + .parent_data = mmss_xo_dsibyte, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_rcg2 byte1_clk_src = { + .cmd_rcgr = 0x2140, + .hid_width = 5, + .parent_map = mmss_xo_dsibyte_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "byte1_clk_src", + .parent_data = mmss_xo_dsibyte, + .num_parents = 4, + .ops = &clk_byte2_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_cci_clk_src[] = { + f(37500000, p_gpll0, 16, 0, 0), + f(50000000, p_gpll0, 12, 0, 0), + f(100000000, p_gpll0, 6, 0, 0), + { } +}; + +static struct clk_rcg2 cci_clk_src = { + .cmd_rcgr = 0x3300, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_cci_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cci_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_cpp_clk_src[] = { + f(100000000, p_gpll0, 6, 0, 0), + f(200000000, p_gpll0, 3, 0, 0), + f(384000000, p_mmpll4_out_even, 2, 0, 0), + f(404000000, p_mmpll0_out_even, 2, 0, 0), + f(480000000, p_mmpll7_out_even, 2, 0, 0), + f(576000000, p_mmpll10_out_even, 1, 0, 0), + f(600000000, p_gpll0, 1, 0, 0), + { } +}; + +static struct clk_rcg2 cpp_clk_src = { + .cmd_rcgr = 0x3640, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_cpp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "cpp_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_csi_clk_src[] = { + f(164571429, p_mmpll10_out_even, 3.5, 0, 0), + f(256000000, p_mmpll4_out_even, 3, 0, 0), + f(274290000, p_mmpll7_out_even, 3.5, 0, 0), + f(300000000, p_gpll0, 2, 0, 0), + f(384000000, p_mmpll4_out_even, 2, 0, 0), + f(576000000, p_mmpll10_out_even, 1, 0, 0), + { } +}; + +static struct clk_rcg2 csi0_clk_src = { + .cmd_rcgr = 0x3090, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi1_clk_src = { + .cmd_rcgr = 0x3100, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi2_clk_src = { + .cmd_rcgr = 0x3160, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi3_clk_src = { + .cmd_rcgr = 0x31c0, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi3_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_csiphy_clk_src[] = { + f(164571429, p_mmpll10_out_even, 3.5, 0, 0), + f(256000000, p_mmpll4_out_even, 3, 0, 0), + f(274290000, p_mmpll7_out_even, 3.5, 0, 0), + f(300000000, p_gpll0, 2, 0, 0), + f(384000000, p_mmpll4_out_even, 2, 0, 0), + { } +}; + +static struct clk_rcg2 csiphy_clk_src = { + .cmd_rcgr = 0x3800, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csiphy_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csiphy_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_csiphytimer_clk_src[] = { + f(200000000, p_gpll0, 3, 0, 0), + f(269333333, p_mmpll0_out_even, 3, 0, 0), + { } +}; + +static struct clk_rcg2 csi0phytimer_clk_src = { + .cmd_rcgr = 0x3000, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csiphytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi0phytimer_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi1phytimer_clk_src = { + .cmd_rcgr = 0x3030, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csiphytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi1phytimer_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 csi2phytimer_clk_src = { + .cmd_rcgr = 0x3060, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_csiphytimer_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "csi2phytimer_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dp_aux_clk_src[] = { + f(19200000, p_xo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 dp_aux_clk_src = { + .cmd_rcgr = 0x2260, + .hid_width = 5, + .parent_map = mmss_xo_gpll0_gpll0_div_map, + .freq_tbl = ftbl_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_aux_clk_src", + .parent_data = mmss_xo_gpll0_gpll0_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dp_crypto_clk_src[] = { + f(101250, p_dplink, 1, 5, 16), + f(168750, p_dplink, 1, 5, 16), + f(337500, p_dplink, 1, 5, 16), + { } +}; + +static struct clk_rcg2 dp_crypto_clk_src = { + .cmd_rcgr = 0x2220, + .hid_width = 5, + .parent_map = mmss_xo_dp_map, + .freq_tbl = ftbl_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_crypto_clk_src", + .parent_data = mmss_xo_dp, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dp_link_clk_src[] = { + f(162000, p_dplink, 2, 0, 0), + f(270000, p_dplink, 2, 0, 0), + f(540000, p_dplink, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dp_link_clk_src = { + .cmd_rcgr = 0x2200, + .hid_width = 5, + .parent_map = mmss_xo_dp_map, + .freq_tbl = ftbl_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_link_clk_src", + .parent_data = mmss_xo_dp, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_dp_pixel_clk_src[] = { + f(154000000, p_dpvco, 1, 0, 0), + f(337500000, p_dpvco, 2, 0, 0), + f(675000000, p_dpvco, 2, 0, 0), + { } +}; + +static struct clk_rcg2 dp_pixel_clk_src = { + .cmd_rcgr = 0x2240, + .hid_width = 5, + .parent_map = mmss_xo_dp_map, + .freq_tbl = ftbl_dp_pixel_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "dp_pixel_clk_src", + .parent_data = mmss_xo_dp, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_esc_clk_src[] = { + f(19200000, p_xo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 esc0_clk_src = { + .cmd_rcgr = 0x2160, + .hid_width = 5, + .parent_map = mmss_xo_dsibyte_map, + .freq_tbl = ftbl_esc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc0_clk_src", + .parent_data = mmss_xo_dsibyte, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 esc1_clk_src = { + .cmd_rcgr = 0x2180, + .hid_width = 5, + .parent_map = mmss_xo_dsibyte_map, + .freq_tbl = ftbl_esc_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "esc1_clk_src", + .parent_data = mmss_xo_dsibyte, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_extpclk_clk_src[] = { + { .src = p_hdmipll }, + { } +}; + +static struct clk_rcg2 extpclk_clk_src = { + .cmd_rcgr = 0x2060, + .hid_width = 5, + .parent_map = mmss_xo_hdmi_map, + .freq_tbl = ftbl_extpclk_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "extpclk_clk_src", + .parent_data = mmss_xo_hdmi, + .num_parents = 3, + .ops = &clk_byte_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_fd_core_clk_src[] = { + f(100000000, p_gpll0, 6, 0, 0), + f(200000000, p_gpll0, 3, 0, 0), + f(404000000, p_mmpll0_out_even, 2, 0, 0), + f(480000000, p_mmpll7_out_even, 2, 0, 0), + f(576000000, p_mmpll10_out_even, 1, 0, 0), + { } +}; + +static struct clk_rcg2 fd_core_clk_src = { + .cmd_rcgr = 0x3b00, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_fd_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "fd_core_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_hdmi_clk_src[] = { + f(19200000, p_xo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 hdmi_clk_src = { + .cmd_rcgr = 0x2100, + .hid_width = 5, + .parent_map = mmss_xo_gpll0_gpll0_div_map, + .freq_tbl = ftbl_hdmi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "hdmi_clk_src", + .parent_data = mmss_xo_gpll0_gpll0_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_jpeg0_clk_src[] = { + f(75000000, p_gpll0, 8, 0, 0), + f(150000000, p_gpll0, 4, 0, 0), + f(320000000, p_mmpll7_out_even, 3, 0, 0), + f(480000000, p_mmpll7_out_even, 2, 0, 0), + { } +}; + +static struct clk_rcg2 jpeg0_clk_src = { + .cmd_rcgr = 0x3500, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_jpeg0_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "jpeg0_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_maxi_clk_src[] = { + f(19200000, p_xo, 1, 0, 0), + f(75000000, p_gpll0_div, 4, 0, 0), + f(171428571, p_gpll0, 3.5, 0, 0), + f(323200000, p_mmpll0_out_even, 2.5, 0, 0), + f(406000000, p_mmpll1_out_even, 2, 0, 0), + { } +}; + +static struct clk_rcg2 maxi_clk_src = { + .cmd_rcgr = 0xf020, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, + .freq_tbl = ftbl_maxi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "maxi_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_mclk_clk_src[] = { + f(4800000, p_xo, 4, 0, 0), + f(6000000, p_gpll0_div, 10, 1, 5), + f(8000000, p_gpll0_div, 1, 2, 75), + f(9600000, p_xo, 2, 0, 0), + f(16666667, p_gpll0_div, 2, 1, 9), + f(19200000, p_xo, 1, 0, 0), + f(24000000, p_gpll0_div, 1, 2, 25), + f(33333333, p_gpll0_div, 1, 2, 9), + f(48000000, p_gpll0, 1, 2, 25), + f(66666667, p_gpll0, 1, 2, 9), + { } +}; + +static struct clk_rcg2 mclk0_clk_src = { + .cmd_rcgr = 0x3360, + .hid_width = 5, + .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_mclk_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk0_clk_src", + .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk1_clk_src = { + .cmd_rcgr = 0x3390, + .hid_width = 5, + .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_mclk_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk1_clk_src", + .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk2_clk_src = { + .cmd_rcgr = 0x33c0, + .hid_width = 5, + .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_mclk_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk2_clk_src", + .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 mclk3_clk_src = { + .cmd_rcgr = 0x33f0, + .hid_width = 5, + .parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_mclk_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mclk3_clk_src", + .parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_mdp_clk_src[] = { + f(85714286, p_gpll0, 7, 0, 0), + f(100000000, p_gpll0, 6, 0, 0), + f(150000000, p_gpll0, 4, 0, 0), + f(171428571, p_gpll0, 3.5, 0, 0), + f(200000000, p_gpll0, 3, 0, 0), + f(275000000, p_mmpll5_out_even, 3, 0, 0), + f(300000000, p_gpll0, 2, 0, 0), + f(330000000, p_mmpll5_out_even, 2.5, 0, 0), + f(412500000, p_mmpll5_out_even, 2, 0, 0), + { } +}; + +static struct clk_rcg2 mdp_clk_src = { + .cmd_rcgr = 0x2040, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, + .freq_tbl = ftbl_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "mdp_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_vsync_clk_src[] = { + f(19200000, p_xo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vsync_clk_src = { + .cmd_rcgr = 0x2080, + .hid_width = 5, + .parent_map = mmss_xo_gpll0_gpll0_div_map, + .freq_tbl = ftbl_vsync_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vsync_clk_src", + .parent_data = mmss_xo_gpll0_gpll0_div, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_ahb_clk_src[] = { + f(19200000, p_xo, 1, 0, 0), + f(40000000, p_gpll0, 15, 0, 0), + f(80800000, p_mmpll0_out_even, 10, 0, 0), + { } +}; + +static struct clk_rcg2 ahb_clk_src = { + .cmd_rcgr = 0x5000, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map, + .freq_tbl = ftbl_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ahb_clk_src", + .parent_data = mmss_xo_mmpll0_gpll0_gpll0_div, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_axi_clk_src[] = { + f(75000000, p_gpll0, 8, 0, 0), + f(171428571, p_gpll0, 3.5, 0, 0), + f(240000000, p_gpll0, 2.5, 0, 0), + f(323200000, p_mmpll0_out_even, 2.5, 0, 0), + f(406000000, p_mmpll0_out_even, 2, 0, 0), + { } +}; + +/* ro to linux */ +static struct clk_rcg2 axi_clk_src = { + .cmd_rcgr = 0xd000, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map, + .freq_tbl = ftbl_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "axi_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 pclk0_clk_src = { + .cmd_rcgr = 0x2000, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmss_xo_dsi0pll_dsi1pll_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk0_clk_src", + .parent_data = mmss_xo_dsi0pll_dsi1pll, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_rcg2 pclk1_clk_src = { + .cmd_rcgr = 0x2020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = mmss_xo_dsi0pll_dsi1pll_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pclk1_clk_src", + .parent_data = mmss_xo_dsi0pll_dsi1pll, + .num_parents = 4, + .ops = &clk_pixel_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_rot_clk_src[] = { + f(171428571, p_gpll0, 3.5, 0, 0), + f(275000000, p_mmpll5_out_even, 3, 0, 0), + f(330000000, p_mmpll5_out_even, 2.5, 0, 0), + f(412500000, p_mmpll5_out_even, 2, 0, 0), + { } +}; + +static struct clk_rcg2 rot_clk_src = { + .cmd_rcgr = 0x21a0, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map, + .freq_tbl = ftbl_rot_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rot_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_video_core_clk_src[] = { + f(200000000, p_gpll0, 3, 0, 0), + f(269330000, p_mmpll0_out_even, 3, 0, 0), + f(355200000, p_mmpll6_out_even, 2.5, 0, 0), + f(444000000, p_mmpll6_out_even, 2, 0, 0), + f(533000000, p_mmpll3_out_even, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_core_clk_src = { + .cmd_rcgr = 0x1000, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map, + .freq_tbl = ftbl_video_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_core_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_subcore0_clk_src = { + .cmd_rcgr = 0x1060, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map, + .freq_tbl = ftbl_video_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_subcore0_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 video_subcore1_clk_src = { + .cmd_rcgr = 0x1080, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map, + .freq_tbl = ftbl_video_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_subcore1_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_vfe_clk_src[] = { + f(200000000, p_gpll0, 3, 0, 0), + f(300000000, p_gpll0, 2, 0, 0), + f(320000000, p_mmpll7_out_even, 3, 0, 0), + f(384000000, p_mmpll4_out_even, 2, 0, 0), + f(404000000, p_mmpll0_out_even, 2, 0, 0), + f(480000000, p_mmpll7_out_even, 2, 0, 0), + f(576000000, p_mmpll10_out_even, 1, 0, 0), + f(600000000, p_gpll0, 1, 0, 0), + { } +}; + +static struct clk_rcg2 vfe0_clk_src = { + .cmd_rcgr = 0x3600, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_vfe_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe0_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 vfe1_clk_src = { + .cmd_rcgr = 0x3620, + .hid_width = 5, + .parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map, + .freq_tbl = ftbl_vfe_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "vfe1_clk_src", + .parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div, + .num_parents = 8, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch misc_ahb_clk = { + .halt_reg = 0x328, + .clkr = { + .enable_reg = 0x328, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "misc_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch video_core_clk = { + .halt_reg = 0x1028, + .clkr = { + .enable_reg = 0x1028, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_core_clk", + .parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch video_ahb_clk = { + .halt_reg = 0x1030, + .clkr = { + .enable_reg = 0x1030, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch video_axi_clk = { + .halt_reg = 0x1034, + .clkr = { + .enable_reg = 0x1034, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_maxi_clk = { + .halt_reg = 0x1038, + .clkr = { + .enable_reg = 0x1038, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_maxi_clk", + .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch video_subcore0_clk = { + .halt_reg = 0x1048, + .clkr = { + .enable_reg = 0x1048, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_subcore0_clk", + .parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch video_subcore1_clk = { + .halt_reg = 0x104c, + .clkr = { + .enable_reg = 0x104c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_subcore1_clk", + .parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_ahb_clk = { + .halt_reg = 0x2308, + .clkr = { + .enable_reg = 0x2308, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_hdmi_dp_ahb_clk = { + .halt_reg = 0x230c, + .clkr = { + .enable_reg = 0x230c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_hdmi_dp_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_axi_clk = { + .halt_reg = 0x2310, + .clkr = { + .enable_reg = 0x2310, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mdss_pclk0_clk = { + .halt_reg = 0x2314, + .clkr = { + .enable_reg = 0x2314, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_pclk0_clk", + .parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_pclk1_clk = { + .halt_reg = 0x2318, + .clkr = { + .enable_reg = 0x2318, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_pclk1_clk", + .parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_mdp_clk = { + .halt_reg = 0x231c, + .clkr = { + .enable_reg = 0x231c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_mdp_clk", + .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_mdp_lut_clk = { + .halt_reg = 0x2320, + .clkr = { + .enable_reg = 0x2320, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_mdp_lut_clk", + .parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_extpclk_clk = { + .halt_reg = 0x2324, + .clkr = { + .enable_reg = 0x2324, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_extpclk_clk", + .parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_vsync_clk = { + .halt_reg = 0x2328, + .clkr = { + .enable_reg = 0x2328, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_vsync_clk", + .parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_hdmi_clk = { + .halt_reg = 0x2338, + .clkr = { + .enable_reg = 0x2338, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_hdmi_clk", + .parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_byte0_clk = { + .halt_reg = 0x233c, + .clkr = { + .enable_reg = 0x233c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_byte0_clk", + .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_byte1_clk = { + .halt_reg = 0x2340, + .clkr = { + .enable_reg = 0x2340, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_byte1_clk", + .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_esc0_clk = { + .halt_reg = 0x2344, + .clkr = { + .enable_reg = 0x2344, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_esc0_clk", + .parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_esc1_clk = { + .halt_reg = 0x2348, + .clkr = { + .enable_reg = 0x2348, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_esc1_clk", + .parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_rot_clk = { + .halt_reg = 0x2350, + .clkr = { + .enable_reg = 0x2350, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_rot_clk", + .parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_dp_link_clk = { + .halt_reg = 0x2354, + .clkr = { + .enable_reg = 0x2354, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_dp_link_clk", + .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_dp_link_intf_clk = { + .halt_reg = 0x2358, + .clkr = { + .enable_reg = 0x2358, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_dp_link_intf_clk", + .parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_dp_crypto_clk = { + .halt_reg = 0x235c, + .clkr = { + .enable_reg = 0x235c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_dp_crypto_clk", + .parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_dp_pixel_clk = { + .halt_reg = 0x2360, + .clkr = { + .enable_reg = 0x2360, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_dp_pixel_clk", + .parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_dp_aux_clk = { + .halt_reg = 0x2364, + .clkr = { + .enable_reg = 0x2364, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_dp_aux_clk", + .parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_byte0_intf_clk = { + .halt_reg = 0x2374, + .clkr = { + .enable_reg = 0x2374, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_byte0_intf_clk", + .parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mdss_byte1_intf_clk = { + .halt_reg = 0x2378, + .clkr = { + .enable_reg = 0x2378, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mdss_byte1_intf_clk", + .parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi0phytimer_clk = { + .halt_reg = 0x3024, + .clkr = { + .enable_reg = 0x3024, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi0phytimer_clk", + .parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi1phytimer_clk = { + .halt_reg = 0x3054, + .clkr = { + .enable_reg = 0x3054, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi1phytimer_clk", + .parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi2phytimer_clk = { + .halt_reg = 0x3084, + .clkr = { + .enable_reg = 0x3084, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi2phytimer_clk", + .parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi0_clk = { + .halt_reg = 0x30b4, + .clkr = { + .enable_reg = 0x30b4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi0_clk", + .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi0_ahb_clk = { + .halt_reg = 0x30bc, + .clkr = { + .enable_reg = 0x30bc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi0_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi0rdi_clk = { + .halt_reg = 0x30d4, + .clkr = { + .enable_reg = 0x30d4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi0rdi_clk", + .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi0pix_clk = { + .halt_reg = 0x30e4, + .clkr = { + .enable_reg = 0x30e4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi0pix_clk", + .parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi1_clk = { + .halt_reg = 0x3124, + .clkr = { + .enable_reg = 0x3124, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi1_clk", + .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi1_ahb_clk = { + .halt_reg = 0x3128, + .clkr = { + .enable_reg = 0x3128, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi1rdi_clk = { + .halt_reg = 0x3144, + .clkr = { + .enable_reg = 0x3144, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi1rdi_clk", + .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi1pix_clk = { + .halt_reg = 0x3154, + .clkr = { + .enable_reg = 0x3154, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi1pix_clk", + .parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi2_clk = { + .halt_reg = 0x3184, + .clkr = { + .enable_reg = 0x3184, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi2_clk", + .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi2_ahb_clk = { + .halt_reg = 0x3188, + .clkr = { + .enable_reg = 0x3188, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi2_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi2rdi_clk = { + .halt_reg = 0x31a4, + .clkr = { + .enable_reg = 0x31a4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi2rdi_clk", + .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi2pix_clk = { + .halt_reg = 0x31b4, + .clkr = { + .enable_reg = 0x31b4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi2pix_clk", + .parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi3_clk = { + .halt_reg = 0x31e4, + .clkr = { + .enable_reg = 0x31e4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi3_clk", + .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi3_ahb_clk = { + .halt_reg = 0x31e8, + .clkr = { + .enable_reg = 0x31e8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi3_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi3rdi_clk = { + .halt_reg = 0x3204, + .clkr = { + .enable_reg = 0x3204, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi3rdi_clk", + .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi3pix_clk = { + .halt_reg = 0x3214, + .clkr = { + .enable_reg = 0x3214, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi3pix_clk", + .parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_ispif_ahb_clk = { + .halt_reg = 0x3224, + .clkr = { + .enable_reg = 0x3224, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_ispif_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cci_clk = { + .halt_reg = 0x3344, + .clkr = { + .enable_reg = 0x3344, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cci_clk", + .parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cci_ahb_clk = { + .halt_reg = 0x3348, + .clkr = { + .enable_reg = 0x3348, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cci_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_mclk0_clk = { + .halt_reg = 0x3384, + .clkr = { + .enable_reg = 0x3384, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_mclk0_clk", + .parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_mclk1_clk = { + .halt_reg = 0x33b4, + .clkr = { + .enable_reg = 0x33b4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_mclk1_clk", + .parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_mclk2_clk = { + .halt_reg = 0x33e4, + .clkr = { + .enable_reg = 0x33e4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_mclk2_clk", + .parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_mclk3_clk = { + .halt_reg = 0x3414, + .clkr = { + .enable_reg = 0x3414, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_mclk3_clk", + .parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_top_ahb_clk = { + .halt_reg = 0x3484, + .clkr = { + .enable_reg = 0x3484, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_top_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_ahb_clk = { + .halt_reg = 0x348c, + .clkr = { + .enable_reg = 0x348c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_micro_ahb_clk = { + .halt_reg = 0x3494, + .clkr = { + .enable_reg = 0x3494, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_micro_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_jpeg0_clk = { + .halt_reg = 0x35a8, + .clkr = { + .enable_reg = 0x35a8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_jpeg0_clk", + .parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_jpeg_ahb_clk = { + .halt_reg = 0x35b4, + .clkr = { + .enable_reg = 0x35b4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_jpeg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_jpeg_axi_clk = { + .halt_reg = 0x35b8, + .clkr = { + .enable_reg = 0x35b8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_jpeg_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camss_vfe0_ahb_clk = { + .halt_reg = 0x3668, + .clkr = { + .enable_reg = 0x3668, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe0_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe1_ahb_clk = { + .halt_reg = 0x3678, + .clkr = { + .enable_reg = 0x3678, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe0_clk = { + .halt_reg = 0x36a8, + .clkr = { + .enable_reg = 0x36a8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe0_clk", + .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe1_clk = { + .halt_reg = 0x36ac, + .clkr = { + .enable_reg = 0x36ac, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe1_clk", + .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cpp_clk = { + .halt_reg = 0x36b0, + .clkr = { + .enable_reg = 0x36b0, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cpp_clk", + .parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cpp_ahb_clk = { + .halt_reg = 0x36b4, + .clkr = { + .enable_reg = 0x36b4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cpp_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe_vbif_ahb_clk = { + .halt_reg = 0x36b8, + .clkr = { + .enable_reg = 0x36b8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe_vbif_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe_vbif_axi_clk = { + .halt_reg = 0x36bc, + .clkr = { + .enable_reg = 0x36bc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe_vbif_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camss_cpp_axi_clk = { + .halt_reg = 0x36c4, + .clkr = { + .enable_reg = 0x36c4, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cpp_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch camss_cpp_vbif_ahb_clk = { + .halt_reg = 0x36c8, + .clkr = { + .enable_reg = 0x36c8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cpp_vbif_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi_vfe0_clk = { + .halt_reg = 0x3704, + .clkr = { + .enable_reg = 0x3704, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi_vfe0_clk", + .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csi_vfe1_clk = { + .halt_reg = 0x3714, + .clkr = { + .enable_reg = 0x3714, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csi_vfe1_clk", + .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe0_stream_clk = { + .halt_reg = 0x3720, + .clkr = { + .enable_reg = 0x3720, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe0_stream_clk", + .parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_vfe1_stream_clk = { + .halt_reg = 0x3724, + .clkr = { + .enable_reg = 0x3724, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_vfe1_stream_clk", + .parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cphy_csid0_clk = { + .halt_reg = 0x3730, + .clkr = { + .enable_reg = 0x3730, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cphy_csid0_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cphy_csid1_clk = { + .halt_reg = 0x3734, + .clkr = { + .enable_reg = 0x3734, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cphy_csid1_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cphy_csid2_clk = { + .halt_reg = 0x3738, + .clkr = { + .enable_reg = 0x3738, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cphy_csid2_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_cphy_csid3_clk = { + .halt_reg = 0x373c, + .clkr = { + .enable_reg = 0x373c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_cphy_csid3_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csiphy0_clk = { + .halt_reg = 0x3740, + .clkr = { + .enable_reg = 0x3740, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csiphy0_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csiphy1_clk = { + .halt_reg = 0x3744, + .clkr = { + .enable_reg = 0x3744, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csiphy1_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch camss_csiphy2_clk = { + .halt_reg = 0x3748, + .clkr = { + .enable_reg = 0x3748, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "camss_csiphy2_clk", + .parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch fd_core_clk = { + .halt_reg = 0x3b68, + .clkr = { + .enable_reg = 0x3b68, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "fd_core_clk", + .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch fd_core_uar_clk = { + .halt_reg = 0x3b6c, + .clkr = { + .enable_reg = 0x3b6c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "fd_core_uar_clk", + .parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch fd_ahb_clk = { + .halt_reg = 0x3b74, + .clkr = { + .enable_reg = 0x3b74, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "fd_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch mnoc_ahb_clk = { + .halt_reg = 0x5024, + .clkr = { + .enable_reg = 0x5024, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mnoc_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch bimc_smmu_ahb_clk = { + .halt_reg = 0xe004, + .clkr = { + .enable_reg = 0xe004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "bimc_smmu_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch bimc_smmu_axi_clk = { + .halt_reg = 0xe008, + .clkr = { + .enable_reg = 0xe008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "bimc_smmu_axi_clk", + .parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mnoc_maxi_clk = { + .halt_reg = 0xf004, + .clkr = { + .enable_reg = 0xf004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mnoc_maxi_clk", + .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch vmem_maxi_clk = { + .halt_reg = 0xf064, + .clkr = { + .enable_reg = 0xf064, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "vmem_maxi_clk", + .parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_branch vmem_ahb_clk = { + .halt_reg = 0xf068, + .clkr = { + .enable_reg = 0xf068, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "vmem_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_branch2_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_hw *mmcc_msm8998_hws[] = { + &gpll0_div.hw, +}; + +static struct gdsc video_top_gdsc = { + .gdscr = 0x1024, + .pd = { + .name = "video_top", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc video_subcore0_gdsc = { + .gdscr = 0x1040, + .pd = { + .name = "video_subcore0", + }, + .parent = &video_top_gdsc.pd, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc video_subcore1_gdsc = { + .gdscr = 0x1044, + .pd = { + .name = "video_subcore1", + }, + .parent = &video_top_gdsc.pd, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x2304, + .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 }, + .cxc_count = 4, + .pd = { + .name = "mdss", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc camss_top_gdsc = { + .gdscr = 0x34a0, + .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494, + 0x35a8, 0x3868 }, + .cxc_count = 7, + .pd = { + .name = "camss_top", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc camss_vfe0_gdsc = { + .gdscr = 0x3664, + .pd = { + .name = "camss_vfe0", + }, + .parent = &camss_top_gdsc.pd, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc camss_vfe1_gdsc = { + .gdscr = 0x3674, + .pd = { + .name = "camss_vfe1_gdsc", + }, + .parent = &camss_top_gdsc.pd, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc camss_cpp_gdsc = { + .gdscr = 0x36d4, + .pd = { + .name = "camss_cpp", + }, + .parent = &camss_top_gdsc.pd, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc bimc_smmu_gdsc = { + .gdscr = 0xe020, + .gds_hw_ctrl = 0xe024, + .pd = { + .name = "bimc_smmu", + }, + .pwrsts = pwrsts_off_on, + .flags = hw_ctrl, +}; + +static struct clk_regmap *mmcc_msm8998_clocks[] = { + [mmpll0] = &mmpll0.clkr, + [mmpll0_out_even] = &mmpll0_out_even.clkr, + [mmpll1] = &mmpll1.clkr, + [mmpll1_out_even] = &mmpll1_out_even.clkr, + [mmpll3] = &mmpll3.clkr, + [mmpll3_out_even] = &mmpll3_out_even.clkr, + [mmpll4] = &mmpll4.clkr, + [mmpll4_out_even] = &mmpll4_out_even.clkr, + [mmpll5] = &mmpll5.clkr, + [mmpll5_out_even] = &mmpll5_out_even.clkr, + [mmpll6] = &mmpll6.clkr, + [mmpll6_out_even] = &mmpll6_out_even.clkr, + [mmpll7] = &mmpll7.clkr, + [mmpll7_out_even] = &mmpll7_out_even.clkr, + [mmpll10] = &mmpll10.clkr, + [mmpll10_out_even] = &mmpll10_out_even.clkr, + [byte0_clk_src] = &byte0_clk_src.clkr, + [byte1_clk_src] = &byte1_clk_src.clkr, + [cci_clk_src] = &cci_clk_src.clkr, + [cpp_clk_src] = &cpp_clk_src.clkr, + [csi0_clk_src] = &csi0_clk_src.clkr, + [csi1_clk_src] = &csi1_clk_src.clkr, + [csi2_clk_src] = &csi2_clk_src.clkr, + [csi3_clk_src] = &csi3_clk_src.clkr, + [csiphy_clk_src] = &csiphy_clk_src.clkr, + [csi0phytimer_clk_src] = &csi0phytimer_clk_src.clkr, + [csi1phytimer_clk_src] = &csi1phytimer_clk_src.clkr, + [csi2phytimer_clk_src] = &csi2phytimer_clk_src.clkr, + [dp_aux_clk_src] = &dp_aux_clk_src.clkr, + [dp_crypto_clk_src] = &dp_crypto_clk_src.clkr, + [dp_link_clk_src] = &dp_link_clk_src.clkr, + [dp_pixel_clk_src] = &dp_pixel_clk_src.clkr, + [esc0_clk_src] = &esc0_clk_src.clkr, + [esc1_clk_src] = &esc1_clk_src.clkr, + [extpclk_clk_src] = &extpclk_clk_src.clkr, + [fd_core_clk_src] = &fd_core_clk_src.clkr, + [hdmi_clk_src] = &hdmi_clk_src.clkr, + [jpeg0_clk_src] = &jpeg0_clk_src.clkr, + [maxi_clk_src] = &maxi_clk_src.clkr, + [mclk0_clk_src] = &mclk0_clk_src.clkr, + [mclk1_clk_src] = &mclk1_clk_src.clkr, + [mclk2_clk_src] = &mclk2_clk_src.clkr, + [mclk3_clk_src] = &mclk3_clk_src.clkr, + [mdp_clk_src] = &mdp_clk_src.clkr, + [vsync_clk_src] = &vsync_clk_src.clkr, + [ahb_clk_src] = &ahb_clk_src.clkr, + [axi_clk_src] = &axi_clk_src.clkr, + [pclk0_clk_src] = &pclk0_clk_src.clkr, + [pclk1_clk_src] = &pclk1_clk_src.clkr, + [rot_clk_src] = &rot_clk_src.clkr, + [video_core_clk_src] = &video_core_clk_src.clkr, + [video_subcore0_clk_src] = &video_subcore0_clk_src.clkr, + [video_subcore1_clk_src] = &video_subcore1_clk_src.clkr, + [vfe0_clk_src] = &vfe0_clk_src.clkr, + [vfe1_clk_src] = &vfe1_clk_src.clkr, + [misc_ahb_clk] = &misc_ahb_clk.clkr, + [video_core_clk] = &video_core_clk.clkr, + [video_ahb_clk] = &video_ahb_clk.clkr, + [video_axi_clk] = &video_axi_clk.clkr, + [video_maxi_clk] = &video_maxi_clk.clkr, + [video_subcore0_clk] = &video_subcore0_clk.clkr, + [video_subcore1_clk] = &video_subcore1_clk.clkr, + [mdss_ahb_clk] = &mdss_ahb_clk.clkr, + [mdss_hdmi_dp_ahb_clk] = &mdss_hdmi_dp_ahb_clk.clkr, + [mdss_axi_clk] = &mdss_axi_clk.clkr, + [mdss_pclk0_clk] = &mdss_pclk0_clk.clkr, + [mdss_pclk1_clk] = &mdss_pclk1_clk.clkr, + [mdss_mdp_clk] = &mdss_mdp_clk.clkr, + [mdss_mdp_lut_clk] = &mdss_mdp_lut_clk.clkr, + [mdss_extpclk_clk] = &mdss_extpclk_clk.clkr, + [mdss_vsync_clk] = &mdss_vsync_clk.clkr, + [mdss_hdmi_clk] = &mdss_hdmi_clk.clkr, + [mdss_byte0_clk] = &mdss_byte0_clk.clkr, + [mdss_byte1_clk] = &mdss_byte1_clk.clkr, + [mdss_esc0_clk] = &mdss_esc0_clk.clkr, + [mdss_esc1_clk] = &mdss_esc1_clk.clkr, + [mdss_rot_clk] = &mdss_rot_clk.clkr, + [mdss_dp_link_clk] = &mdss_dp_link_clk.clkr, + [mdss_dp_link_intf_clk] = &mdss_dp_link_intf_clk.clkr, + [mdss_dp_crypto_clk] = &mdss_dp_crypto_clk.clkr, + [mdss_dp_pixel_clk] = &mdss_dp_pixel_clk.clkr, + [mdss_dp_aux_clk] = &mdss_dp_aux_clk.clkr, + [mdss_byte0_intf_clk] = &mdss_byte0_intf_clk.clkr, + [mdss_byte1_intf_clk] = &mdss_byte1_intf_clk.clkr, + [camss_csi0phytimer_clk] = &camss_csi0phytimer_clk.clkr, + [camss_csi1phytimer_clk] = &camss_csi1phytimer_clk.clkr, + [camss_csi2phytimer_clk] = &camss_csi2phytimer_clk.clkr, + [camss_csi0_clk] = &camss_csi0_clk.clkr, + [camss_csi0_ahb_clk] = &camss_csi0_ahb_clk.clkr, + [camss_csi0rdi_clk] = &camss_csi0rdi_clk.clkr, + [camss_csi0pix_clk] = &camss_csi0pix_clk.clkr, + [camss_csi1_clk] = &camss_csi1_clk.clkr, + [camss_csi1_ahb_clk] = &camss_csi1_ahb_clk.clkr, + [camss_csi1rdi_clk] = &camss_csi1rdi_clk.clkr, + [camss_csi1pix_clk] = &camss_csi1pix_clk.clkr, + [camss_csi2_clk] = &camss_csi2_clk.clkr, + [camss_csi2_ahb_clk] = &camss_csi2_ahb_clk.clkr, + [camss_csi2rdi_clk] = &camss_csi2rdi_clk.clkr, + [camss_csi2pix_clk] = &camss_csi2pix_clk.clkr, + [camss_csi3_clk] = &camss_csi3_clk.clkr, + [camss_csi3_ahb_clk] = &camss_csi3_ahb_clk.clkr, + [camss_csi3rdi_clk] = &camss_csi3rdi_clk.clkr, + [camss_csi3pix_clk] = &camss_csi3pix_clk.clkr, + [camss_ispif_ahb_clk] = &camss_ispif_ahb_clk.clkr, + [camss_cci_clk] = &camss_cci_clk.clkr, + [camss_cci_ahb_clk] = &camss_cci_ahb_clk.clkr, + [camss_mclk0_clk] = &camss_mclk0_clk.clkr, + [camss_mclk1_clk] = &camss_mclk1_clk.clkr, + [camss_mclk2_clk] = &camss_mclk2_clk.clkr, + [camss_mclk3_clk] = &camss_mclk3_clk.clkr, + [camss_top_ahb_clk] = &camss_top_ahb_clk.clkr, + [camss_ahb_clk] = &camss_ahb_clk.clkr, + [camss_micro_ahb_clk] = &camss_micro_ahb_clk.clkr, + [camss_jpeg0_clk] = &camss_jpeg0_clk.clkr, + [camss_jpeg_ahb_clk] = &camss_jpeg_ahb_clk.clkr, + [camss_jpeg_axi_clk] = &camss_jpeg_axi_clk.clkr, + [camss_vfe0_ahb_clk] = &camss_vfe0_ahb_clk.clkr, + [camss_vfe1_ahb_clk] = &camss_vfe1_ahb_clk.clkr, + [camss_vfe0_clk] = &camss_vfe0_clk.clkr, + [camss_vfe1_clk] = &camss_vfe1_clk.clkr, + [camss_cpp_clk] = &camss_cpp_clk.clkr, + [camss_cpp_ahb_clk] = &camss_cpp_ahb_clk.clkr, + [camss_vfe_vbif_ahb_clk] = &camss_vfe_vbif_ahb_clk.clkr, + [camss_vfe_vbif_axi_clk] = &camss_vfe_vbif_axi_clk.clkr, + [camss_cpp_axi_clk] = &camss_cpp_axi_clk.clkr, + [camss_cpp_vbif_ahb_clk] = &camss_cpp_vbif_ahb_clk.clkr, + [camss_csi_vfe0_clk] = &camss_csi_vfe0_clk.clkr, + [camss_csi_vfe1_clk] = &camss_csi_vfe1_clk.clkr, + [camss_vfe0_stream_clk] = &camss_vfe0_stream_clk.clkr, + [camss_vfe1_stream_clk] = &camss_vfe1_stream_clk.clkr, + [camss_cphy_csid0_clk] = &camss_cphy_csid0_clk.clkr, + [camss_cphy_csid1_clk] = &camss_cphy_csid1_clk.clkr, + [camss_cphy_csid2_clk] = &camss_cphy_csid2_clk.clkr, + [camss_cphy_csid3_clk] = &camss_cphy_csid3_clk.clkr, + [camss_csiphy0_clk] = &camss_csiphy0_clk.clkr, + [camss_csiphy1_clk] = &camss_csiphy1_clk.clkr, + [camss_csiphy2_clk] = &camss_csiphy2_clk.clkr, + [fd_core_clk] = &fd_core_clk.clkr, + [fd_core_uar_clk] = &fd_core_uar_clk.clkr, + [fd_ahb_clk] = &fd_ahb_clk.clkr, + [mnoc_ahb_clk] = &mnoc_ahb_clk.clkr, + [bimc_smmu_ahb_clk] = &bimc_smmu_ahb_clk.clkr, + [bimc_smmu_axi_clk] = &bimc_smmu_axi_clk.clkr, + [mnoc_maxi_clk] = &mnoc_maxi_clk.clkr, + [vmem_maxi_clk] = &vmem_maxi_clk.clkr, + [vmem_ahb_clk] = &vmem_ahb_clk.clkr, +}; + +static struct gdsc *mmcc_msm8998_gdscs[] = { + [video_top_gdsc] = &video_top_gdsc, + [video_subcore0_gdsc] = &video_subcore0_gdsc, + [video_subcore1_gdsc] = &video_subcore1_gdsc, + [mdss_gdsc] = &mdss_gdsc, + [camss_top_gdsc] = &camss_top_gdsc, + [camss_vfe0_gdsc] = &camss_vfe0_gdsc, + [camss_vfe1_gdsc] = &camss_vfe1_gdsc, + [camss_cpp_gdsc] = &camss_cpp_gdsc, + [bimc_smmu_gdsc] = &bimc_smmu_gdsc, +}; + +static const struct qcom_reset_map mmcc_msm8998_resets[] = { + [spdm_bcr] = { 0x200 }, + [spdm_rm_bcr] = { 0x300 }, + [misc_bcr] = { 0x320 }, + [video_top_bcr] = { 0x1020 }, + [throttle_video_bcr] = { 0x1180 }, + [mdss_bcr] = { 0x2300 }, + [throttle_mdss_bcr] = { 0x2460 }, + [camss_phy0_bcr] = { 0x3020 }, + [camss_phy1_bcr] = { 0x3050 }, + [camss_phy2_bcr] = { 0x3080 }, + [camss_csi0_bcr] = { 0x30b0 }, + [camss_csi0rdi_bcr] = { 0x30d0 }, + [camss_csi0pix_bcr] = { 0x30e0 }, + [camss_csi1_bcr] = { 0x3120 }, + [camss_csi1rdi_bcr] = { 0x3140 }, + [camss_csi1pix_bcr] = { 0x3150 }, + [camss_csi2_bcr] = { 0x3180 }, + [camss_csi2rdi_bcr] = { 0x31a0 }, + [camss_csi2pix_bcr] = { 0x31b0 }, + [camss_csi3_bcr] = { 0x31e0 }, + [camss_csi3rdi_bcr] = { 0x3200 }, + [camss_csi3pix_bcr] = { 0x3210 }, + [camss_ispif_bcr] = { 0x3220 }, + [camss_cci_bcr] = { 0x3340 }, + [camss_top_bcr] = { 0x3480 }, + [camss_ahb_bcr] = { 0x3488 }, + [camss_micro_bcr] = { 0x3490 }, + [camss_jpeg_bcr] = { 0x35a0 }, + [camss_vfe0_bcr] = { 0x3660 }, + [camss_vfe1_bcr] = { 0x3670 }, + [camss_vfe_vbif_bcr] = { 0x36a0 }, + [camss_cpp_top_bcr] = { 0x36c0 }, + [camss_cpp_bcr] = { 0x36d0 }, + [camss_csi_vfe0_bcr] = { 0x3700 }, + [camss_csi_vfe1_bcr] = { 0x3710 }, + [camss_fd_bcr] = { 0x3b60 }, + [throttle_camss_bcr] = { 0x3c30 }, + [mnocahb_bcr] = { 0x5020 }, + [mnocaxi_bcr] = { 0xd020 }, + [bmic_smmu_bcr] = { 0xe000 }, + [mnoc_maxi_bcr] = { 0xf000 }, + [vmem_bcr] = { 0xf060 }, + [bto_bcr] = { 0x10004 }, +}; + +static const struct regmap_config mmcc_msm8998_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10004, + .fast_io = true, +}; + +static const struct qcom_cc_desc mmcc_msm8998_desc = { + .config = &mmcc_msm8998_regmap_config, + .clks = mmcc_msm8998_clocks, + .num_clks = array_size(mmcc_msm8998_clocks), + .resets = mmcc_msm8998_resets, + .num_resets = array_size(mmcc_msm8998_resets), + .gdscs = mmcc_msm8998_gdscs, + .num_gdscs = array_size(mmcc_msm8998_gdscs), + .clk_hws = mmcc_msm8998_hws, + .num_clk_hws = array_size(mmcc_msm8998_hws), +}; + +static const struct of_device_id mmcc_msm8998_match_table[] = { + { .compatible = "qcom,mmcc-msm8998" }, + { } +}; +module_device_table(of, mmcc_msm8998_match_table); + +static int mmcc_msm8998_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc); + if (is_err(regmap)) + return ptr_err(regmap); + + return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap); +} + +static struct platform_driver mmcc_msm8998_driver = { + .probe = mmcc_msm8998_probe, + .driver = { + .name = "mmcc-msm8998", + .of_match_table = mmcc_msm8998_match_table, + }, +}; +module_platform_driver(mmcc_msm8998_driver); + +module_description("qcom mmcc msm8998 driver"); +module_license("gpl v2"); | Clock | d14b15b5931c2b3eb15613d28f904c44ea4f183c | jeffrey hugo bjorn andersson bjorn andersson linaro org | drivers | clk | qcom |
clk: qcom: add display clock controller driver for sc7180 | add support for the display clock controller found on sc7180 based devices. this would allow display drivers to probe and control their clocks. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add display clock controller driver for sc7180 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['qcom'] | ['c', 'kconfig', 'makefile'] | 3 | 786 | 0 | --- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config sc_dispcc_7180 + tristate "sc7180 display clock controller" + select sc_gcc_7180 + help + support for the display clock controller on qualcomm technologies, inc + sc7180 devices. + say y if you want to support display devices and functionality such as + splash screen. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_sc_dispcc_7180) += dispcc-sc7180.o diff --git a/drivers/clk/qcom/dispcc-sc7180.c b/drivers/clk/qcom/dispcc-sc7180.c --- /dev/null +++ b/drivers/clk/qcom/dispcc-sc7180.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2019, the linux foundation. all rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,dispcc-sc7180.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" + +enum { + p_bi_tcxo, + p_chip_sleep_clk, + p_core_bi_pll_test_se, + p_disp_cc_pll0_out_even, + p_disp_cc_pll0_out_main, + p_dp_phy_pll_link_clk, + p_dp_phy_pll_vco_div_clk, + p_dsi0_phy_pll_out_byteclk, + p_dsi0_phy_pll_out_dsiclk, + p_gpll0_out_main, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct clk_alpha_pll disp_cc_pll0 = { + .offset = 0x0, + .vco_table = fabia_vco, + .num_vco = array_size(fabia_vco), + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_disp_cc_pll0_out_even[] = { + { 0x0, 1 }, + { } +}; + +static struct clk_alpha_pll_postdiv disp_cc_pll0_out_even = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_disp_cc_pll0_out_even, + .num_post_div = array_size(post_div_table_disp_cc_pll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_pll0_out_even", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_pll0.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_alpha_pll_postdiv_fabia_ops, + }, +}; + +static const struct parent_map disp_cc_parent_map_0[] = { + { p_bi_tcxo, 0 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_1[] = { + { p_bi_tcxo, 0 }, + { p_dp_phy_pll_link_clk, 1 }, + { p_dp_phy_pll_vco_div_clk, 2 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dp_phy_pll_link_clk", .name = "dp_phy_pll_link_clk" }, + { .fw_name = "dp_phy_pll_vco_div_clk", + .name = "dp_phy_pll_vco_div_clk"}, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_2[] = { + { p_bi_tcxo, 0 }, + { p_dsi0_phy_pll_out_byteclk, 1 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_byteclk", + .name = "dsi0_phy_pll_out_byteclk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_3[] = { + { p_bi_tcxo, 0 }, + { p_disp_cc_pll0_out_main, 1 }, + { p_gpll0_out_main, 4 }, + { p_disp_cc_pll0_out_even, 5 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &disp_cc_pll0.clkr.hw }, + { .fw_name = "gcc_disp_gpll0_clk_src" }, + { .hw = &disp_cc_pll0_out_even.clkr.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_4[] = { + { p_bi_tcxo, 0 }, + { p_gpll0_out_main, 4 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "gcc_disp_gpll0_clk_src" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct parent_map disp_cc_parent_map_5[] = { + { p_bi_tcxo, 0 }, + { p_dsi0_phy_pll_out_dsiclk, 1 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data disp_cc_parent_data_5[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "dsi0_phy_pll_out_dsiclk", + .name = "dsi0_phy_pll_out_dsiclk" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + f(37500000, p_gpll0_out_main, 16, 0, 0), + f(75000000, p_gpll0_out_main, 8, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = { + .cmd_rcgr = 0x22bc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_4, + .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk_src", + .parent_data = disp_cc_parent_data_4, + .num_parents = 3, + .flags = clk_set_rate_parent, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = { + .cmd_rcgr = 0x2110, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = 3, + .flags = clk_set_rate_parent, + .ops = &clk_byte2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x21dc, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x2194, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = 4, + .flags = clk_set_rate_parent, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x2178, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = 4, + .flags = clk_set_rate_parent, + .ops = &clk_byte2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x21ac, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_data = disp_cc_parent_data_1, + .num_parents = 4, + .flags = clk_set_rate_parent, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { + .cmd_rcgr = 0x2148, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk_src", + .parent_data = disp_cc_parent_data_2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + f(200000000, p_gpll0_out_main, 3, 0, 0), + f(300000000, p_gpll0_out_main, 2, 0, 0), + f(345000000, p_disp_cc_pll0_out_main, 4, 0, 0), + f(460000000, p_disp_cc_pll0_out_main, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = { + .cmd_rcgr = 0x20c8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = 5, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = { + .cmd_rcgr = 0x2098, + .mnd_width = 8, + .hid_width = 5, + .parent_map = disp_cc_parent_map_5, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk_src", + .parent_data = disp_cc_parent_data_5, + .num_parents = 3, + .flags = clk_set_rate_parent, + .ops = &clk_pixel_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_rot_clk_src = { + .cmd_rcgr = 0x20e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_3, + .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk_src", + .parent_data = disp_cc_parent_data_3, + .num_parents = 5, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { + .cmd_rcgr = 0x20f8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_0, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk_src", + .parent_data = disp_cc_parent_data_0, + .num_parents = 2, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_ahb_clk = { + .halt_reg = 0x2080, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2080, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_clk = { + .halt_reg = 0x2028, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2028, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { + .reg = 0x2128, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_byte0_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_clk_src.clkr.hw + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = { + .reg = 0x2190, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "disp_cc_mdss_dp_link_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw + }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_branch disp_cc_mdss_byte0_intf_clk = { + .halt_reg = 0x202c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x202c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_byte0_intf_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_byte0_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x2054, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2054, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x2048, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2048, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_crypto_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x2040, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_link_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2044, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_link_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x204c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x204c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_dp_pixel_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_esc0_clk = { + .halt_reg = 0x2038, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2038, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_esc0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_esc0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_clk = { + .halt_reg = 0x200c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x200c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_mdp_lut_clk = { + .halt_reg = 0x201c, + .halt_check = branch_voted, + .clkr = { + .enable_reg = 0x201c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_mdp_lut_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_mdp_clk_src.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = { + .halt_reg = 0x4004, + .halt_check = branch_voted, + .clkr = { + .enable_reg = 0x4004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_non_gdsc_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_pclk0_clk = { + .halt_reg = 0x2004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_pclk0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_pclk0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rot_clk = { + .halt_reg = 0x2014, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rot_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_rot_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_ahb_clk = { + .halt_reg = 0x400c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x400c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_is_critical | clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_rscc_vsync_clk = { + .halt_reg = 0x4008, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x4008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_rscc_vsync_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_vsync_clk = { + .halt_reg = 0x2024, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x2024, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_vsync_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &disp_cc_mdss_vsync_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc mdss_gdsc = { + .gdscr = 0x3000, + .pd = { + .name = "mdss_gdsc", + }, + .pwrsts = pwrsts_off_on, + .flags = hw_ctrl, +}; + +static struct gdsc *disp_cc_sc7180_gdscs[] = { + [mdss_gdsc] = &mdss_gdsc, +}; + +static struct clk_regmap *disp_cc_sc7180_clocks[] = { + [disp_cc_mdss_ahb_clk] = &disp_cc_mdss_ahb_clk.clkr, + [disp_cc_mdss_ahb_clk_src] = &disp_cc_mdss_ahb_clk_src.clkr, + [disp_cc_mdss_byte0_clk] = &disp_cc_mdss_byte0_clk.clkr, + [disp_cc_mdss_byte0_clk_src] = &disp_cc_mdss_byte0_clk_src.clkr, + [disp_cc_mdss_byte0_div_clk_src] = &disp_cc_mdss_byte0_div_clk_src.clkr, + [disp_cc_mdss_byte0_intf_clk] = &disp_cc_mdss_byte0_intf_clk.clkr, + [disp_cc_mdss_dp_aux_clk] = &disp_cc_mdss_dp_aux_clk.clkr, + [disp_cc_mdss_dp_aux_clk_src] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [disp_cc_mdss_dp_crypto_clk] = &disp_cc_mdss_dp_crypto_clk.clkr, + [disp_cc_mdss_dp_crypto_clk_src] = &disp_cc_mdss_dp_crypto_clk_src.clkr, + [disp_cc_mdss_dp_link_clk] = &disp_cc_mdss_dp_link_clk.clkr, + [disp_cc_mdss_dp_link_clk_src] = &disp_cc_mdss_dp_link_clk_src.clkr, + [disp_cc_mdss_dp_link_div_clk_src] = + &disp_cc_mdss_dp_link_div_clk_src.clkr, + [disp_cc_mdss_dp_link_intf_clk] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [disp_cc_mdss_dp_pixel_clk] = &disp_cc_mdss_dp_pixel_clk.clkr, + [disp_cc_mdss_dp_pixel_clk_src] = &disp_cc_mdss_dp_pixel_clk_src.clkr, + [disp_cc_mdss_esc0_clk] = &disp_cc_mdss_esc0_clk.clkr, + [disp_cc_mdss_esc0_clk_src] = &disp_cc_mdss_esc0_clk_src.clkr, + [disp_cc_mdss_mdp_clk] = &disp_cc_mdss_mdp_clk.clkr, + [disp_cc_mdss_mdp_clk_src] = &disp_cc_mdss_mdp_clk_src.clkr, + [disp_cc_mdss_mdp_lut_clk] = &disp_cc_mdss_mdp_lut_clk.clkr, + [disp_cc_mdss_non_gdsc_ahb_clk] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr, + [disp_cc_mdss_pclk0_clk] = &disp_cc_mdss_pclk0_clk.clkr, + [disp_cc_mdss_pclk0_clk_src] = &disp_cc_mdss_pclk0_clk_src.clkr, + [disp_cc_mdss_rot_clk] = &disp_cc_mdss_rot_clk.clkr, + [disp_cc_mdss_rot_clk_src] = &disp_cc_mdss_rot_clk_src.clkr, + [disp_cc_mdss_rscc_ahb_clk] = &disp_cc_mdss_rscc_ahb_clk.clkr, + [disp_cc_mdss_rscc_vsync_clk] = &disp_cc_mdss_rscc_vsync_clk.clkr, + [disp_cc_mdss_vsync_clk] = &disp_cc_mdss_vsync_clk.clkr, + [disp_cc_mdss_vsync_clk_src] = &disp_cc_mdss_vsync_clk_src.clkr, + [disp_cc_pll0] = &disp_cc_pll0.clkr, + [disp_cc_pll0_out_even] = &disp_cc_pll0_out_even.clkr, +}; + +static const struct regmap_config disp_cc_sc7180_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x10000, + .fast_io = true, +}; + +static const struct qcom_cc_desc disp_cc_sc7180_desc = { + .config = &disp_cc_sc7180_regmap_config, + .clks = disp_cc_sc7180_clocks, + .num_clks = array_size(disp_cc_sc7180_clocks), + .gdscs = disp_cc_sc7180_gdscs, + .num_gdscs = array_size(disp_cc_sc7180_gdscs), +}; + +static const struct of_device_id disp_cc_sc7180_match_table[] = { + { .compatible = "qcom,sc7180-dispcc" }, + { } +}; +module_device_table(of, disp_cc_sc7180_match_table); + +static int disp_cc_sc7180_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct alpha_pll_config disp_cc_pll_config = {}; + + regmap = qcom_cc_map(pdev, &disp_cc_sc7180_desc); + if (is_err(regmap)) + return ptr_err(regmap); + + /* 1380mhz configuration */ + disp_cc_pll_config.l = 0x47; + disp_cc_pll_config.alpha = 0xe000; + disp_cc_pll_config.user_ctl_val = 0x00000001; + disp_cc_pll_config.user_ctl_hi_val = 0x00004805; + + clk_fabia_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll_config); + + return qcom_cc_really_probe(pdev, &disp_cc_sc7180_desc, regmap); +} + +static struct platform_driver disp_cc_sc7180_driver = { + .probe = disp_cc_sc7180_probe, + .driver = { + .name = "sc7180-dispcc", + .of_match_table = disp_cc_sc7180_match_table, + }, +}; + +static int __init disp_cc_sc7180_init(void) +{ + return platform_driver_register(&disp_cc_sc7180_driver); +} +subsys_initcall(disp_cc_sc7180_init); + +static void __exit disp_cc_sc7180_exit(void) +{ + platform_driver_unregister(&disp_cc_sc7180_driver); +} +module_exit(disp_cc_sc7180_exit); + +module_description("qti disp_cc sc7180 driver"); +module_license("gpl v2"); | Clock | dd3d06622138e913fa2a0b9a21c0aae231eb45b7 | taniya das | drivers | clk | qcom |
clk: qcom: add graphics clock controller driver for sc7180 | add support for the graphics clock controller found on sc7180 based devices. this would allow graphics drivers to probe and control their clocks. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add graphics clock controller driver for sc7180 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['qcom'] | ['c', 'kconfig', 'makefile'] | 3 | 275 | 0 | --- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config sc_gpucc_7180 + tristate "sc7180 graphics clock controller" + select sc_gcc_7180 + help + support for the graphics clock controller on sc7180 devices. + say y if you want to support graphics controller devices and + functionality such as 3d graphics. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_sc_gpucc_7180) += gpucc-sc7180.o diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c --- /dev/null +++ b/drivers/clk/qcom/gpucc-sc7180.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2019, the linux foundation. all rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,gpucc-sc7180.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" + +#define cx_gmu_cbcr_sleep_mask 0xf +#define cx_gmu_cbcr_sleep_shift 4 +#define cx_gmu_cbcr_wake_mask 0xf +#define cx_gmu_cbcr_wake_shift 8 +#define clk_dis_wait_shift 12 +#define clk_dis_wait_mask (0xf << clk_dis_wait_shift) + +enum { + p_bi_tcxo, + p_core_bi_pll_test_se, + p_gpll0_out_main, + p_gpll0_out_main_div, + p_gpu_cc_pll1_out_even, + p_gpu_cc_pll1_out_main, + p_gpu_cc_pll1_out_odd, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct clk_alpha_pll gpu_cc_pll1 = { + .offset = 0x100, + .vco_table = fabia_vco, + .num_vco = array_size(fabia_vco), + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_pll1", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct parent_map gpu_cc_parent_map_0[] = { + { p_bi_tcxo, 0 }, + { p_gpu_cc_pll1_out_main, 3 }, + { p_gpll0_out_main, 5 }, + { p_gpll0_out_main_div, 6 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data gpu_cc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpu_cc_pll1.clkr.hw }, + { .fw_name = "gcc_gpu_gpll0_clk_src" }, + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + f(200000000, p_gpll0_out_main_div, 1.5, 0, 0), + { } +}; + +static struct clk_rcg2 gpu_cc_gmu_clk_src = { + .cmd_rcgr = 0x1120, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gpu_cc_parent_map_0, + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpu_cc_gmu_clk_src", + .parent_data = gpu_cc_parent_data_0, + .num_parents = 5, + .flags = clk_set_rate_parent, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch gpu_cc_crc_ahb_clk = { + .halt_reg = 0x107c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x107c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_crc_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_gmu_clk = { + .halt_reg = 0x1098, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x1098, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_gmu_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpu_cc_gmu_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { + .halt_reg = 0x108c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x108c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cx_snoc_dvm_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_aon_clk = { + .halt_reg = 0x1004, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x1004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_aon_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gpu_cc_cxo_clk = { + .halt_reg = 0x109c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x109c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpu_cc_cxo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc cx_gdsc = { + .gdscr = 0x106c, + .gds_hw_ctrl = 0x1540, + .pd = { + .name = "cx_gdsc", + }, + .pwrsts = pwrsts_off_on, + .flags = votable, +}; + +static struct gdsc *gpu_cc_sc7180_gdscs[] = { + [cx_gdsc] = &cx_gdsc, +}; + +static struct clk_regmap *gpu_cc_sc7180_clocks[] = { + [gpu_cc_cxo_clk] = &gpu_cc_cxo_clk.clkr, + [gpu_cc_crc_ahb_clk] = &gpu_cc_crc_ahb_clk.clkr, + [gpu_cc_cx_gmu_clk] = &gpu_cc_cx_gmu_clk.clkr, + [gpu_cc_cx_snoc_dvm_clk] = &gpu_cc_cx_snoc_dvm_clk.clkr, + [gpu_cc_cxo_aon_clk] = &gpu_cc_cxo_aon_clk.clkr, + [gpu_cc_gmu_clk_src] = &gpu_cc_gmu_clk_src.clkr, + [gpu_cc_pll1] = &gpu_cc_pll1.clkr, +}; + +static const struct regmap_config gpu_cc_sc7180_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x8008, + .fast_io = true, +}; + +static const struct qcom_cc_desc gpu_cc_sc7180_desc = { + .config = &gpu_cc_sc7180_regmap_config, + .clks = gpu_cc_sc7180_clocks, + .num_clks = array_size(gpu_cc_sc7180_clocks), + .gdscs = gpu_cc_sc7180_gdscs, + .num_gdscs = array_size(gpu_cc_sc7180_gdscs), +}; + +static const struct of_device_id gpu_cc_sc7180_match_table[] = { + { .compatible = "qcom,sc7180-gpucc" }, + { } +}; +module_device_table(of, gpu_cc_sc7180_match_table); + +static int gpu_cc_sc7180_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct alpha_pll_config gpu_cc_pll_config = {}; + unsigned int value, mask; + + regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc); + if (is_err(regmap)) + return ptr_err(regmap); + + /* 360mhz configuration */ + gpu_cc_pll_config.l = 0x12; + gpu_cc_pll_config.alpha = 0xc000; + gpu_cc_pll_config.config_ctl_val = 0x20485699; + gpu_cc_pll_config.config_ctl_hi_val = 0x00002067; + gpu_cc_pll_config.user_ctl_val = 0x00000001; + gpu_cc_pll_config.user_ctl_hi_val = 0x00004805; + gpu_cc_pll_config.test_ctl_hi_val = 0x40000000; + + clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config); + + /* recommended wakeup/sleep settings for the gpu_cc_cx_gmu_clk */ + mask = cx_gmu_cbcr_wake_mask << cx_gmu_cbcr_wake_shift; + mask |= cx_gmu_cbcr_sleep_mask << cx_gmu_cbcr_sleep_shift; + value = 0xf << cx_gmu_cbcr_wake_shift | 0xf << cx_gmu_cbcr_sleep_shift; + regmap_update_bits(regmap, 0x1098, mask, value); + + /* configure clk_dis_wait for gpu_cx_gdsc */ + regmap_update_bits(regmap, 0x106c, clk_dis_wait_mask, + 8 << clk_dis_wait_shift); + + return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap); +} + +static struct platform_driver gpu_cc_sc7180_driver = { + .probe = gpu_cc_sc7180_probe, + .driver = { + .name = "sc7180-gpucc", + .of_match_table = gpu_cc_sc7180_match_table, + }, +}; + +static int __init gpu_cc_sc7180_init(void) +{ + return platform_driver_register(&gpu_cc_sc7180_driver); +} +subsys_initcall(gpu_cc_sc7180_init); + +static void __exit gpu_cc_sc7180_exit(void) +{ + platform_driver_unregister(&gpu_cc_sc7180_driver); +} +module_exit(gpu_cc_sc7180_exit); + +module_description("qti gpu_cc sc7180 driver"); +module_license("gpl v2"); | Clock | 745ff069a49c52d323c98672fc92c312aee62dd9 | taniya das | drivers | clk | qcom |
clk: qcom: add ipq6018 global clock controller support | this patch adds support for the global clock controller found on the ipq6018 based devices. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add ipq6018 global clock controller support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['qcom'] | ['c', 'kconfig', 'makefile'] | 3 | 4,644 | 0 | --- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config ipq_gcc_6018 + tristate "ipq6018 global clock controller" + help + support for global clock controller on ipq6018 devices. + say y if you want to use peripheral devices such as uart, spi, + i2c, usb, sd/emmc, etc. select this for the root clock + of ipq6018. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_ipq_gcc_6018) += gcc-ipq6018.o diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c --- /dev/null +++ b/drivers/clk/qcom/gcc-ipq6018.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018, the linux foundation. all rights reserved. + */ + +#include <linux/kernel.h> +#include <linux/err.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/clk-provider.h> +#include <linux/regmap.h> + +#include <linux/reset-controller.h> +#include <dt-bindings/clock/qcom,gcc-ipq6018.h> +#include <dt-bindings/reset/qcom,gcc-ipq6018.h> + +#include "common.h" +#include "clk-regmap.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-branch.h" +#include "clk-alpha-pll.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "reset.h" + +#define f(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } + +enum { + p_xo, + p_bias_pll, + p_uniphy0_rx, + p_uniphy0_tx, + p_uniphy1_rx, + p_bias_pll_nss_noc, + p_uniphy1_tx, + p_pcie20_phy0_pipe, + p_usb3phy_0_pipe, + p_gpll0, + p_gpll0_div2, + p_gpll2, + p_gpll4, + p_gpll6, + p_sleep_clk, + p_ubi32_pll, + p_nss_crypto_pll, + p_pi_sleep, +}; + +static struct clk_alpha_pll gpll0_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll0_out_main_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main_div2", + .parent_hws = (const struct clk_hw *[]){ + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_alpha_pll_postdiv gpll0 = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .width = 4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_hws = (const struct clk_hw *[]){ + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw}, + { .hw = &gpll0_out_main_div2.hw}, +}; + +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll0_div2, 4 }, +}; + +static struct clk_alpha_pll ubi32_pll_main = { + .offset = 0x25000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_huayra], + .flags = supports_dynamic_update, + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = bit(6), + .hw.init = &(struct clk_init_data){ + .name = "ubi32_pll_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_huayra_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv ubi32_pll = { + .offset = 0x25000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_huayra], + .width = 2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ubi32_pll", + .parent_hws = (const struct clk_hw *[]){ + &ubi32_pll_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_alpha_pll gpll6_main = { + .offset = 0x37000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_brammo], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = bit(7), + .hw.init = &(struct clk_init_data){ + .name = "gpll6_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll6 = { + .offset = 0x37000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_brammo], + .width = 2, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll6", + .parent_hws = (const struct clk_hw *[]){ + &gpll6_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_alpha_pll gpll4_main = { + .offset = 0x24000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = bit(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll4 = { + .offset = 0x24000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .width = 4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_hws = (const struct clk_hw *[]){ + &gpll4_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(50000000, p_gpll0, 16, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 pcnoc_bfdcd_clk_src = { + .cmd_rcgr = 0x27000, + .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcnoc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_alpha_pll gpll2_main = { + .offset = 0x4a000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = bit(2), + .hw.init = &(struct clk_init_data){ + .name = "gpll2_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv gpll2 = { + .offset = 0x4a000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .width = 4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll2", + .parent_hws = (const struct clk_hw *[]){ + &gpll2_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_alpha_pll nss_crypto_pll_main = { + .offset = 0x22000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .clkr = { + .enable_reg = 0x0b000, + .enable_mask = bit(4), + .hw.init = &(struct clk_init_data){ + .name = "nss_crypto_pll_main", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll_postdiv nss_crypto_pll = { + .offset = 0x22000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_default], + .width = 4, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_crypto_pll", + .parent_hws = (const struct clk_hw *[]){ + &nss_crypto_pll_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { + f(160000000, p_gpll0_div2, 2.5, 0, 0), + f(320000000, p_gpll0, 2.5, 0, 0), + f(600000000, p_gpll4, 2, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = { + { p_xo, 0 }, + { p_gpll4, 1 }, + { p_gpll0, 2 }, + { p_gpll6, 3 }, + { p_gpll0_div2, 4 }, +}; + +static struct clk_rcg2 qdss_tsctr_clk_src = { + .cmd_rcgr = 0x29064, + .freq_tbl = ftbl_qdss_tsctr_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qdss_tsctr_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor qdss_dap_sync_clk_src = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "qdss_dap_sync_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &qdss_tsctr_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_qdss_at_clk_src[] = { + f(66670000, p_gpll0_div2, 6, 0, 0), + f(240000000, p_gpll4, 5, 0, 0), + { } +}; + +static struct clk_rcg2 qdss_at_clk_src = { + .cmd_rcgr = 0x2900c, + .freq_tbl = ftbl_qdss_at_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qdss_at_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "qdss_tsctr_div2_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &qdss_tsctr_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_fixed_factor_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_ppe_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(300000000, p_bias_pll, 1, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = { + { .fw_name = "xo" }, + { .fw_name = "bias_pll_cc_clk" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &nss_crypto_pll.clkr.hw }, + { .hw = &ubi32_pll.clkr.hw }, +}; + +static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = { + { p_xo, 0 }, + { p_bias_pll, 1 }, + { p_gpll0, 2 }, + { p_gpll4, 3 }, + { p_nss_crypto_pll, 4 }, + { p_ubi32_pll, 5 }, +}; + +static struct clk_rcg2 nss_ppe_clk_src = { + .cmd_rcgr = 0x68080, + .freq_tbl = ftbl_nss_ppe_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_ppe_clk_src", + .parent_data = gcc_xo_bias_gpll0_gpll4_nss_ubi32, + .num_parents = 6, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_xo_clk_src = { + .halt_reg = 0x30018, + .clkr = { + .enable_reg = 0x30018, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_xo_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "xo", + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_nss_ce_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, +}; + +static struct clk_rcg2 nss_ce_clk_src = { + .cmd_rcgr = 0x68098, + .freq_tbl = ftbl_nss_ce_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_ce_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_sleep_clk_src = { + .halt_reg = 0x30000, + .clkr = { + .enable_reg = 0x30000, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sleep_clk_src", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "sleep_clk", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_snoc_nssnoc_bfdcd_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(50000000, p_gpll0_div2, 8, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + f(133333333, p_gpll0, 6, 0, 0), + f(160000000, p_gpll0, 5, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + f(266666667, p_gpll0, 3, 0, 0), + { } +}; + +static const struct clk_parent_data + gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll6, 2 }, + { p_gpll0_div2, 3 }, +}; + +static struct clk_rcg2 snoc_nssnoc_bfdcd_clk_src = { + .cmd_rcgr = 0x76054, + .freq_tbl = ftbl_snoc_nssnoc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "snoc_nssnoc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_gpll0_div2, 16, 0, 0), + f(50000000, p_gpll0, 16, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 apss_ahb_clk_src = { + .cmd_rcgr = 0x46000, + .freq_tbl = ftbl_apss_ahb_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_ahb_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_uniphy1_rx, 12.5, 0, 0), + f(25000000, p_uniphy0_rx, 5, 0, 0), + f(78125000, p_uniphy1_rx, 4, 0, 0), + f(125000000, p_uniphy1_rx, 2.5, 0, 0), + f(125000000, p_uniphy0_rx, 1, 0, 0), + f(156250000, p_uniphy1_rx, 2, 0, 0), + f(312500000, p_uniphy1_rx, 1, 0, 0), + { } +}; + +static const struct clk_parent_data +gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = { + { .fw_name = "xo" }, + { .fw_name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy1_gcc_rx_clk" }, + { .fw_name = "uniphy1_gcc_tx_clk" }, + { .hw = &ubi32_pll.clkr.hw }, + { .fw_name = "bias_pll_cc_clk" }, +}; + +static const struct parent_map +gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map[] = { + { p_xo, 0 }, + { p_uniphy0_rx, 1 }, + { p_uniphy0_tx, 2 }, + { p_uniphy1_rx, 3 }, + { p_uniphy1_tx, 4 }, + { p_ubi32_pll, 5 }, + { p_bias_pll, 6 }, +}; + +static struct clk_rcg2 nss_port5_rx_clk_src = { + .cmd_rcgr = 0x68060, + .freq_tbl = ftbl_nss_port5_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port5_rx_clk_src", + .parent_data = gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_uniphy1_tx, 12.5, 0, 0), + f(25000000, p_uniphy0_tx, 5, 0, 0), + f(78125000, p_uniphy1_tx, 4, 0, 0), + f(125000000, p_uniphy1_tx, 2.5, 0, 0), + f(125000000, p_uniphy0_tx, 1, 0, 0), + f(156250000, p_uniphy1_tx, 2, 0, 0), + f(312500000, p_uniphy1_tx, 1, 0, 0), + { } +}; + +static const struct clk_parent_data +gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = { + { .fw_name = "xo" }, + { .fw_name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy1_gcc_tx_clk" }, + { .fw_name = "uniphy1_gcc_rx_clk" }, + { .hw = &ubi32_pll.clkr.hw }, + { .fw_name = "bias_pll_cc_clk" }, +}; + +static const struct parent_map +gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map[] = { + { p_xo, 0 }, + { p_uniphy0_tx, 1 }, + { p_uniphy0_rx, 2 }, + { p_uniphy1_tx, 3 }, + { p_uniphy1_rx, 4 }, + { p_ubi32_pll, 5 }, + { p_bias_pll, 6 }, +}; + +static struct clk_rcg2 nss_port5_tx_clk_src = { + .cmd_rcgr = 0x68068, + .freq_tbl = ftbl_nss_port5_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port5_tx_clk_src", + .parent_data = gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias, + .num_parents = 7, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_pcie_axi_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + f(240000000, p_gpll4, 5, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll4.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll4, 2 }, +}; + +static struct clk_rcg2 pcie0_axi_clk_src = { + .cmd_rcgr = 0x75054, + .freq_tbl = ftbl_pcie_axi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll4_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcie0_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll4, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb0_master_clk_src[] = { + f(80000000, p_gpll0_div2, 5, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + f(133330000, p_gpll0, 6, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &gpll0_out_main_div2.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { + { p_xo, 0 }, + { p_gpll0_div2, 2 }, + { p_gpll0, 1 }, +}; + +static struct clk_rcg2 usb0_master_clk_src = { + .cmd_rcgr = 0x3e00c, + .freq_tbl = ftbl_usb0_master_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb0_master_clk_src", + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div apss_ahb_postdiv_clk_src = { + .reg = 0x46018, + .shift = 4, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "apss_ahb_postdiv_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &apss_ahb_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + }, + }, +}; + +static struct clk_fixed_factor gcc_xo_div4_clk_src = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "gcc_xo_div4_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_nss_port1_rx_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_uniphy0_rx, 5, 0, 0), + f(125000000, p_uniphy0_rx, 1, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = { + { .fw_name = "xo" }, + { .fw_name = "uniphy0_gcc_rx_clk" }, + { .fw_name = "uniphy0_gcc_tx_clk" }, + { .hw = &ubi32_pll.clkr.hw }, + { .fw_name = "bias_pll_cc_clk" }, +}; + +static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = { + { p_xo, 0 }, + { p_uniphy0_rx, 1 }, + { p_uniphy0_tx, 2 }, + { p_ubi32_pll, 5 }, + { p_bias_pll, 6 }, +}; + +static struct clk_rcg2 nss_port1_rx_clk_src = { + .cmd_rcgr = 0x68020, + .freq_tbl = ftbl_nss_port1_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port1_rx_clk_src", + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_port1_tx_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_uniphy0_tx, 5, 0, 0), + f(125000000, p_uniphy0_tx, 1, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = { + { .fw_name = "xo" }, + { .fw_name = "uniphy0_gcc_tx_clk" }, + { .fw_name = "uniphy0_gcc_rx_clk" }, + { .hw = &ubi32_pll.clkr.hw }, + { .fw_name = "bias_pll_cc_clk" }, +}; + +static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = { + { p_xo, 0 }, + { p_uniphy0_tx, 1 }, + { p_uniphy0_rx, 2 }, + { p_ubi32_pll, 5 }, + { p_bias_pll, 6 }, +}; + +static struct clk_rcg2 nss_port1_tx_clk_src = { + .cmd_rcgr = 0x68028, + .freq_tbl = ftbl_nss_port1_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port1_tx_clk_src", + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_port2_rx_clk_src = { + .cmd_rcgr = 0x68030, + .freq_tbl = ftbl_nss_port1_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port2_rx_clk_src", + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_port2_tx_clk_src = { + .cmd_rcgr = 0x68038, + .freq_tbl = ftbl_nss_port1_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port2_tx_clk_src", + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_port3_rx_clk_src = { + .cmd_rcgr = 0x68040, + .freq_tbl = ftbl_nss_port1_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port3_rx_clk_src", + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_port3_tx_clk_src = { + .cmd_rcgr = 0x68048, + .freq_tbl = ftbl_nss_port1_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port3_tx_clk_src", + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_port4_rx_clk_src = { + .cmd_rcgr = 0x68050, + .freq_tbl = ftbl_nss_port1_rx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_rx_tx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port4_rx_clk_src", + .parent_data = gcc_xo_uniphy0_rx_tx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_port4_tx_clk_src = { + .cmd_rcgr = 0x68058, + .freq_tbl = ftbl_nss_port1_tx_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_uniphy0_tx_rx_ubi32_bias_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_port4_tx_clk_src", + .parent_data = gcc_xo_uniphy0_tx_rx_ubi32_bias, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_port5_rx_div_clk_src = { + .reg = 0x68440, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port5_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_rx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port5_tx_div_clk_src = { + .reg = 0x68444, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port5_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_tx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static const struct freq_tbl ftbl_apss_axi_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(100000000, p_gpll0_div2, 4, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + f(308570000, p_gpll6, 3.5, 0, 0), + f(400000000, p_gpll0, 2, 0, 0), + f(533000000, p_gpll0, 1.5, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll6_ubi32_gpll0_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map +gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll6, 2 }, + { p_ubi32_pll, 3 }, + { p_gpll0_div2, 6 }, +}; + +static struct clk_rcg2 apss_axi_clk_src = { + .cmd_rcgr = 0x38048, + .freq_tbl = ftbl_apss_axi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "apss_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_ubi32_gpll0_div2, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_crypto_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(300000000, p_nss_crypto_pll, 2, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_nss_crypto_pll_gpll0[] = { + { .fw_name = "xo" }, + { .hw = &nss_crypto_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, +}; + +static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = { + { p_xo, 0 }, + { p_nss_crypto_pll, 1 }, + { p_gpll0, 2 }, +}; + +static struct clk_rcg2 nss_crypto_clk_src = { + .cmd_rcgr = 0x68144, + .freq_tbl = ftbl_nss_crypto_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_nss_crypto_pll_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_crypto_clk_src", + .parent_data = gcc_xo_nss_crypto_pll_gpll0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_port1_rx_div_clk_src = { + .reg = 0x68400, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port1_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port1_rx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port1_tx_div_clk_src = { + .reg = 0x68404, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port1_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port1_tx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port2_rx_div_clk_src = { + .reg = 0x68410, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port2_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port2_rx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port2_tx_div_clk_src = { + .reg = 0x68414, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port2_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port2_tx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port3_rx_div_clk_src = { + .reg = 0x68420, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port3_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port3_rx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port3_tx_div_clk_src = { + .reg = 0x68424, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port3_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port3_tx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port4_rx_div_clk_src = { + .reg = 0x68430, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port4_rx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port4_rx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static struct clk_regmap_div nss_port4_tx_div_clk_src = { + .reg = 0x68434, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_port4_tx_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_port4_tx_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static const struct freq_tbl ftbl_nss_ubi_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(149760000, p_ubi32_pll, 10, 0, 0), + f(187200000, p_ubi32_pll, 8, 0, 0), + f(249600000, p_ubi32_pll, 6, 0, 0), + f(374400000, p_ubi32_pll, 4, 0, 0), + f(748800000, p_ubi32_pll, 2, 0, 0), + f(1497600000, p_ubi32_pll, 1, 0, 0), + { } +}; + +static const struct clk_parent_data + gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = { + { .fw_name = "xo" }, + { .hw = &ubi32_pll.clkr.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll6.clkr.hw }, +}; + +static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = { + { p_xo, 0 }, + { p_ubi32_pll, 1 }, + { p_gpll0, 2 }, + { p_gpll2, 3 }, + { p_gpll4, 4 }, + { p_gpll6, 5 }, +}; + +static struct clk_rcg2 nss_ubi0_clk_src = { + .cmd_rcgr = 0x68104, + .freq_tbl = ftbl_nss_ubi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "nss_ubi0_clk_src", + .parent_data = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6, + .num_parents = 6, + .ops = &clk_rcg2_ops, + .flags = clk_set_rate_parent, + }, +}; + +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 adss_pwm_clk_src = { + .cmd_rcgr = 0x1c008, + .freq_tbl = ftbl_adss_pwm_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "adss_pwm_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_gpll0_div2, 16, 0, 0), + f(50000000, p_gpll0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { + .cmd_rcgr = 0x0200c, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { + f(960000, p_xo, 10, 2, 5), + f(4800000, p_xo, 5, 0, 0), + f(9600000, p_xo, 2, 4, 5), + f(12500000, p_gpll0_div2, 16, 1, 2), + f(16000000, p_gpll0, 10, 1, 5), + f(24000000, p_xo, 1, 0, 0), + f(25000000, p_gpll0, 16, 1, 2), + f(50000000, p_gpll0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { + .cmd_rcgr = 0x02024, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup1_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { + .cmd_rcgr = 0x03000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { + .cmd_rcgr = 0x03014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup2_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { + .cmd_rcgr = 0x04000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { + .cmd_rcgr = 0x04014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup3_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { + .cmd_rcgr = 0x05000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { + .cmd_rcgr = 0x05014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup4_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { + .cmd_rcgr = 0x06000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { + .cmd_rcgr = 0x06014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup5_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { + .cmd_rcgr = 0x07000, + .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_i2c_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { + .cmd_rcgr = 0x07014, + .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_qup6_spi_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { + f(3686400, p_gpll0_div2, 1, 144, 15625), + f(7372800, p_gpll0_div2, 1, 288, 15625), + f(14745600, p_gpll0_div2, 1, 576, 15625), + f(16000000, p_gpll0_div2, 5, 1, 5), + f(24000000, p_xo, 1, 0, 0), + f(24000000, p_gpll0, 1, 3, 100), + f(25000000, p_gpll0, 16, 1, 2), + f(32000000, p_gpll0, 1, 1, 25), + f(40000000, p_gpll0, 1, 1, 20), + f(46400000, p_gpll0, 1, 29, 500), + f(48000000, p_gpll0, 1, 3, 50), + f(51200000, p_gpll0, 1, 8, 125), + f(56000000, p_gpll0, 1, 7, 100), + f(58982400, p_gpll0, 1, 1152, 15625), + f(60000000, p_gpll0, 1, 3, 40), + f(64000000, p_gpll0, 12.5, 1, 1), + { } +}; + +static struct clk_rcg2 blsp1_uart1_apps_clk_src = { + .cmd_rcgr = 0x02044, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart1_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart2_apps_clk_src = { + .cmd_rcgr = 0x03034, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart2_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart3_apps_clk_src = { + .cmd_rcgr = 0x04034, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart3_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart4_apps_clk_src = { + .cmd_rcgr = 0x05034, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart4_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart5_apps_clk_src = { + .cmd_rcgr = 0x06034, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart5_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 blsp1_uart6_apps_clk_src = { + .cmd_rcgr = 0x07034, + .freq_tbl = ftbl_blsp1_uart_apps_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "blsp1_uart6_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_crypto_clk_src[] = { + f(40000000, p_gpll0_div2, 10, 0, 0), + f(80000000, p_gpll0, 10, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + f(160000000, p_gpll0, 5, 0, 0), + { } +}; + +static struct clk_rcg2 crypto_clk_src = { + .cmd_rcgr = 0x16004, + .freq_tbl = ftbl_crypto_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "crypto_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gp_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(50000000, p_gpll0_div2, 8, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + f(266666666, p_gpll0, 3, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_sleep_clk[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll6, 2 }, + { p_gpll0_div2, 4 }, + { p_sleep_clk, 6 }, +}; + +static struct clk_rcg2 gp1_clk_src = { + .cmd_rcgr = 0x08004, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp1_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp2_clk_src = { + .cmd_rcgr = 0x09004, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp2_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gp3_clk_src = { + .cmd_rcgr = 0x0a004, + .freq_tbl = ftbl_gp_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gp3_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_gpll0_sleep_clk, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_fixed_factor nss_ppe_cdiv_clk_src = { + .mult = 1, + .div = 4, + .hw.init = &(struct clk_init_data){ + .name = "nss_ppe_cdiv_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_regmap_div nss_ubi0_div_clk_src = { + .reg = 0x68118, + .shift = 0, + .width = 4, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "nss_ubi0_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &nss_ubi0_clk_src.clkr.hw }, + .num_parents = 1, + .ops = &clk_regmap_div_ro_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static const struct freq_tbl ftbl_pcie_aux_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), +}; + +static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { + { p_xo, 0 }, + { p_gpll0, 2 }, + { p_pi_sleep, 6 }, +}; + +static struct clk_rcg2 pcie0_aux_clk_src = { + .cmd_rcgr = 0x75024, + .freq_tbl = ftbl_pcie_aux_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcie0_aux_clk_src", + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = { + { .fw_name = "pcie20_phy0_pipe_clk" }, + { .fw_name = "xo" }, +}; + +static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { + { p_pcie20_phy0_pipe, 0 }, + { p_xo, 2 }, +}; + +static struct clk_regmap_mux pcie0_pipe_clk_src = { + .reg = 0x7501c, + .shift = 8, + .width = 2, + .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "pcie0_pipe_clk_src", + .parent_data = gcc_pcie20_phy0_pipe_clk_xo, + .num_parents = 2, + .ops = &clk_regmap_mux_closest_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = { + f(144000, p_xo, 16, 12, 125), + f(400000, p_xo, 12, 1, 5), + f(24000000, p_gpll2, 12, 1, 4), + f(48000000, p_gpll2, 12, 1, 2), + f(96000000, p_gpll2, 12, 0, 0), + f(177777778, p_gpll0, 4.5, 0, 0), + f(192000000, p_gpll2, 6, 0, 0), + f(384000000, p_gpll2, 3, 0, 0), + { } +}; + +static const struct clk_parent_data + gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll2, 2 }, + { p_gpll0_div2, 4 }, +}; + +static struct clk_rcg2 sdcc1_apps_clk_src = { + .cmd_rcgr = 0x42004, + .freq_tbl = ftbl_sdcc_apps_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_apps_clk_src", + .parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb_aux_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 usb0_aux_clk_src = { + .cmd_rcgr = 0x3e05c, + .freq_tbl = ftbl_usb_aux_clk_src, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb0_aux_clk_src", + .parent_data = gcc_xo_gpll0_core_pi_sleep_clk, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(60000000, p_gpll6, 6, 1, 3), + { } +}; + +static const struct clk_parent_data + gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = { + { p_xo, 0 }, + { p_gpll6, 1 }, + { p_gpll0, 3 }, + { p_gpll0_div2, 4 }, +}; + +static struct clk_rcg2 usb0_mock_utmi_clk_src = { + .cmd_rcgr = 0x3e020, + .freq_tbl = ftbl_usb_mock_utmi_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb0_mock_utmi_clk_src", + .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = { + { .fw_name = "usb3phy_0_cc_pipe_clk" }, + { .fw_name = "xo" }, +}; + +static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { + { p_usb3phy_0_pipe, 0 }, + { p_xo, 2 }, +}; + +static struct clk_regmap_mux usb0_pipe_clk_src = { + .reg = 0x3e048, + .shift = 8, + .width = 2, + .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "usb0_pipe_clk_src", + .parent_data = gcc_usb3phy_0_cc_pipe_clk_xo, + .num_parents = 2, + .ops = &clk_regmap_mux_closest_ops, + .flags = clk_set_rate_parent, + }, + }, +}; + +static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = { + f(80000000, p_gpll0_div2, 5, 0, 0), + f(160000000, p_gpll0, 5, 0, 0), + f(216000000, p_gpll6, 5, 0, 0), + f(308570000, p_gpll6, 3.5, 0, 0), +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll6_gpll0_div2[] = { + { .fw_name = "xo"}, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll6.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll6, 2 }, + { p_gpll0_div2, 4 }, +}; + +static struct clk_rcg2 sdcc1_ice_core_clk_src = { + .cmd_rcgr = 0x5d000, + .freq_tbl = ftbl_sdcc_ice_core_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "sdcc1_ice_core_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_gpll0_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(50000000, p_gpll0_div2, 8, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + { } +}; + +static struct clk_rcg2 qdss_stm_clk_src = { + .cmd_rcgr = 0x2902c, + .freq_tbl = ftbl_qdss_stm_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qdss_stm_clk_src", + .parent_data = gcc_xo_gpll0_gpll0_out_main_div2, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { + f(80000000, p_gpll0_div2, 5, 0, 0), + f(160000000, p_gpll0, 5, 0, 0), + f(300000000, p_gpll4, 4, 0, 0), + { } +}; + +static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = { + { .fw_name = "xo" }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_main_div2.hw }, +}; + +static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = { + { p_xo, 0 }, + { p_gpll4, 1 }, + { p_gpll0, 2 }, + { p_gpll0_div2, 4 }, +}; + +static struct clk_rcg2 qdss_traceclkin_clk_src = { + .cmd_rcgr = 0x29048, + .freq_tbl = ftbl_qdss_traceclkin_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "qdss_traceclkin_clk_src", + .parent_data = gcc_xo_gpll4_gpll0_gpll0_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 usb1_mock_utmi_clk_src = { + .cmd_rcgr = 0x3f020, + .freq_tbl = ftbl_usb_mock_utmi_clk_src, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "usb1_mock_utmi_clk_src", + .parent_data = gcc_xo_gpll6_gpll0_gpll0_out_main_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_adss_pwm_clk = { + .halt_reg = 0x1c020, + .clkr = { + .enable_reg = 0x1c020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_adss_pwm_clk", + .parent_hws = (const struct clk_hw *[]){ + &adss_pwm_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_apss_ahb_clk = { + .halt_reg = 0x4601c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apss_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &apss_ahb_postdiv_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(50000000, p_gpll0_div2, 8, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + f(133333333, p_gpll0, 6, 0, 0), + f(160000000, p_gpll0, 5, 0, 0), + f(200000000, p_gpll0, 4, 0, 0), + f(266666667, p_gpll0, 3, 0, 0), + { } +}; + +static struct clk_rcg2 system_noc_bfdcd_clk_src = { + .cmd_rcgr = 0x26004, + .freq_tbl = ftbl_system_noc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "system_noc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll6_gpll0_out_main_div2, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_ubi32_mem_noc_bfdcd_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(307670000, p_bias_pll_nss_noc, 1.5, 0, 0), + f(533333333, p_gpll0, 1.5, 0, 0), + { } +}; + +static const struct clk_parent_data + gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .fw_name = "bias_pll_nss_noc_clk" }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll2, 3 }, + { p_bias_pll_nss_noc, 4 }, +}; + +static struct clk_rcg2 ubi32_mem_noc_bfdcd_clk_src = { + .cmd_rcgr = 0x68088, + .freq_tbl = ftbl_ubi32_mem_noc_bfdcd_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "ubi32_mem_noc_bfdcd_clk_src", + .parent_data = gcc_xo_gpll0_gpll2_bias_pll_nss_noc_clk, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_apss_axi_clk = { + .halt_reg = 0x46020, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_apss_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &apss_axi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_ahb_clk = { + .halt_reg = 0x01008, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { + .halt_reg = 0x02008, + .clkr = { + .enable_reg = 0x02008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup1_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { + .halt_reg = 0x02004, + .clkr = { + .enable_reg = 0x02004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup1_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup1_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { + .halt_reg = 0x03010, + .clkr = { + .enable_reg = 0x03010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup2_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { + .halt_reg = 0x0300c, + .clkr = { + .enable_reg = 0x0300c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup2_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup2_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { + .halt_reg = 0x04010, + .clkr = { + .enable_reg = 0x04010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup3_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { + .halt_reg = 0x0400c, + .clkr = { + .enable_reg = 0x0400c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup3_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup3_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { + .halt_reg = 0x05010, + .clkr = { + .enable_reg = 0x05010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup4_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { + .halt_reg = 0x0500c, + .clkr = { + .enable_reg = 0x0500c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup4_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup4_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { + .halt_reg = 0x06010, + .clkr = { + .enable_reg = 0x06010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup5_i2c_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup5_i2c_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { + .halt_reg = 0x0600c, + .clkr = { + .enable_reg = 0x0600c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup5_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup5_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { + .halt_reg = 0x0700c, + .clkr = { + .enable_reg = 0x0700c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_qup6_spi_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_qup6_spi_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart1_apps_clk = { + .halt_reg = 0x0203c, + .clkr = { + .enable_reg = 0x0203c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart1_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_uart1_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart2_apps_clk = { + .halt_reg = 0x0302c, + .clkr = { + .enable_reg = 0x0302c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart2_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_uart2_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart3_apps_clk = { + .halt_reg = 0x0402c, + .clkr = { + .enable_reg = 0x0402c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart3_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_uart3_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart4_apps_clk = { + .halt_reg = 0x0502c, + .clkr = { + .enable_reg = 0x0502c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart4_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_uart4_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart5_apps_clk = { + .halt_reg = 0x0602c, + .clkr = { + .enable_reg = 0x0602c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart5_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_uart5_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_blsp1_uart6_apps_clk = { + .halt_reg = 0x0702c, + .clkr = { + .enable_reg = 0x0702c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_blsp1_uart6_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &blsp1_uart6_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ahb_clk = { + .halt_reg = 0x16024, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_axi_clk = { + .halt_reg = 0x16020, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_clk = { + .halt_reg = 0x1601c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_clk", + .parent_hws = (const struct clk_hw *[]){ + &crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_fixed_factor gpll6_out_main_div2 = { + .mult = 1, + .div = 2, + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_main_div2", + .parent_hws = (const struct clk_hw *[]){ + &gpll6_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_branch gcc_xo_clk = { + .halt_reg = 0x30030, + .clkr = { + .enable_reg = 0x30030, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_xo_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x08000, + .clkr = { + .enable_reg = 0x08000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_hws = (const struct clk_hw *[]){ + &gp1_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x09000, + .clkr = { + .enable_reg = 0x09000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_hws = (const struct clk_hw *[]){ + &gp2_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x0a000, + .clkr = { + .enable_reg = 0x0a000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_hws = (const struct clk_hw *[]){ + &gp3_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mdio_ahb_clk = { + .halt_reg = 0x58004, + .clkr = { + .enable_reg = 0x58004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mdio_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_crypto_ppe_clk = { + .halt_reg = 0x68310, + .clkr = { + .enable_reg = 0x68310, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_crypto_ppe_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ce_apb_clk = { + .halt_reg = 0x68174, + .clkr = { + .enable_reg = 0x68174, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_ce_apb_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ce_axi_clk = { + .halt_reg = 0x68170, + .clkr = { + .enable_reg = 0x68170, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_ce_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_cfg_clk = { + .halt_reg = 0x68160, + .clkr = { + .enable_reg = 0x68160, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_crypto_clk = { + .halt_reg = 0x68164, + .clkr = { + .enable_reg = 0x68164, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_crypto_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_csr_clk = { + .halt_reg = 0x68318, + .clkr = { + .enable_reg = 0x68318, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_csr_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_edma_cfg_clk = { + .halt_reg = 0x6819c, + .clkr = { + .enable_reg = 0x6819c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_edma_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_edma_clk = { + .halt_reg = 0x68198, + .clkr = { + .enable_reg = 0x68198, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_edma_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_noc_clk = { + .halt_reg = 0x68168, + .clkr = { + .enable_reg = 0x68168, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_noc_clk", + .parent_hws = (const struct clk_hw *[]){ + &snoc_nssnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_utcm_clk = { + .halt_reg = 0x2606c, + .clkr = { + .enable_reg = 0x2606c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ubi0_utcm_clk", + .parent_hws = (const struct clk_hw *[]){ + &snoc_nssnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_nssnoc_clk = { + .halt_reg = 0x26070, + .clkr = { + .enable_reg = 0x26070, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_snoc_nssnoc_clk", + .parent_hws = (const struct clk_hw *[]){ + &snoc_nssnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(133333333, p_gpll0, 6, 0, 0), + { } +}; + +static const struct freq_tbl ftbl_q6_axi_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(400000000, p_gpll0, 2, 0, 0), + { } +}; + +static struct clk_rcg2 wcss_ahb_clk_src = { + .cmd_rcgr = 0x59020, + .freq_tbl = ftbl_wcss_ahb_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "wcss_ahb_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_gpll6[] = { + { .fw_name = "xo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll2.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll6.clkr.hw }, +}; + +static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_gpll6_map[] = { + { p_xo, 0 }, + { p_gpll0, 1 }, + { p_gpll2, 2 }, + { p_gpll4, 3 }, + { p_gpll6, 4 }, +}; + +static struct clk_rcg2 q6_axi_clk_src = { + .cmd_rcgr = 0x59120, + .freq_tbl = ftbl_q6_axi_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_gpll2_gpll4_gpll6_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "q6_axi_clk_src", + .parent_data = gcc_xo_gpll0_gpll2_gpll4_gpll6, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_lpass_core_axim_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(100000000, p_gpll0, 8, 0, 0), + { } +}; + +static struct clk_rcg2 lpass_core_axim_clk_src = { + .cmd_rcgr = 0x1f020, + .freq_tbl = ftbl_lpass_core_axim_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "lpass_core_axim_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_lpass_snoc_cfg_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(266666667, p_gpll0, 3, 0, 0), + { } +}; + +static struct clk_rcg2 lpass_snoc_cfg_clk_src = { + .cmd_rcgr = 0x1f040, + .freq_tbl = ftbl_lpass_snoc_cfg_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "lpass_snoc_cfg_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_lpass_q6_axim_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(400000000, p_gpll0, 2, 0, 0), + { } +}; + +static struct clk_rcg2 lpass_q6_axim_clk_src = { + .cmd_rcgr = 0x1f008, + .freq_tbl = ftbl_lpass_q6_axim_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "lpass_q6_axim_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct freq_tbl ftbl_rbcpr_wcss_clk_src[] = { + f(24000000, p_xo, 1, 0, 0), + f(50000000, p_gpll0, 16, 0, 0), + { } +}; + +static struct clk_rcg2 rbcpr_wcss_clk_src = { + .cmd_rcgr = 0x3a00c, + .freq_tbl = ftbl_rbcpr_wcss_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "rbcpr_wcss_clk_src", + .parent_data = gcc_xo_gpll0_out_main_div2_gpll0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_lpass_core_axim_clk = { + .halt_reg = 0x1f028, + .clkr = { + .enable_reg = 0x1f028, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_core_axim_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_core_axim_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_snoc_cfg_clk = { + .halt_reg = 0x1f048, + .clkr = { + .enable_reg = 0x1f048, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_snoc_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_snoc_cfg_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_q6_axim_clk = { + .halt_reg = 0x1f010, + .clkr = { + .enable_reg = 0x1f010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6_axim_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_q6_axim_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_q6_atbm_at_clk = { + .halt_reg = 0x1f018, + .clkr = { + .enable_reg = 0x1f018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6_atbm_at_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_at_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_q6_pclkdbg_clk = { + .halt_reg = 0x1f01c, + .clkr = { + .enable_reg = 0x1f01c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6_pclkdbg_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_q6ss_tsctr_1to2_clk = { + .halt_reg = 0x1f014, + .clkr = { + .enable_reg = 0x1f014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6ss_tsctr_1to2_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_tsctr_div2_clk_src.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_q6ss_trig_clk = { + .halt_reg = 0x1f038, + .clkr = { + .enable_reg = 0x1f038, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_q6ss_trig_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_lpass_tbu_clk = { + .halt_reg = 0x12094, + .clkr = { + .enable_reg = 0xb00c, + .enable_mask = bit(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_lpass_tbu_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_q6_axim_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcnoc_lpass_clk = { + .halt_reg = 0x27020, + .clkr = { + .enable_reg = 0x27020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcnoc_lpass_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_core_axim_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mem_noc_lpass_clk = { + .halt_reg = 0x1d044, + .clkr = { + .enable_reg = 0x1d044, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mem_noc_lpass_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_q6_axim_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_lpass_cfg_clk = { + .halt_reg = 0x26074, + .clkr = { + .enable_reg = 0x26074, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_snoc_lpass_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ + &lpass_snoc_cfg_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_mem_noc_ubi32_clk = { + .halt_reg = 0x1d03c, + .clkr = { + .enable_reg = 0x1d03c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_mem_noc_ubi32_clk", + .parent_hws = (const struct clk_hw *[]){ + &ubi32_mem_noc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port1_rx_clk = { + .halt_reg = 0x68240, + .clkr = { + .enable_reg = 0x68240, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port1_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port1_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port1_tx_clk = { + .halt_reg = 0x68244, + .clkr = { + .enable_reg = 0x68244, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port1_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port1_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port2_rx_clk = { + .halt_reg = 0x68248, + .clkr = { + .enable_reg = 0x68248, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port2_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port2_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port2_tx_clk = { + .halt_reg = 0x6824c, + .clkr = { + .enable_reg = 0x6824c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port2_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port2_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port3_rx_clk = { + .halt_reg = 0x68250, + .clkr = { + .enable_reg = 0x68250, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port3_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port3_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port3_tx_clk = { + .halt_reg = 0x68254, + .clkr = { + .enable_reg = 0x68254, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port3_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port3_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port4_rx_clk = { + .halt_reg = 0x68258, + .clkr = { + .enable_reg = 0x68258, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port4_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port4_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port4_tx_clk = { + .halt_reg = 0x6825c, + .clkr = { + .enable_reg = 0x6825c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port4_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port4_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port5_rx_clk = { + .halt_reg = 0x68260, + .clkr = { + .enable_reg = 0x68260, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port5_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_port5_tx_clk = { + .halt_reg = 0x68264, + .clkr = { + .enable_reg = 0x68264, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_port5_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ppe_cfg_clk = { + .halt_reg = 0x68194, + .clkr = { + .enable_reg = 0x68194, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_ppe_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ppe_clk = { + .halt_reg = 0x68190, + .clkr = { + .enable_reg = 0x68190, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_ppe_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ppe_ipe_clk = { + .halt_reg = 0x68338, + .clkr = { + .enable_reg = 0x68338, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_ppe_ipe_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nss_ptp_ref_clk = { + .halt_reg = 0x6816c, + .clkr = { + .enable_reg = 0x6816c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nss_ptp_ref_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_cdiv_clk_src.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_ce_apb_clk = { + .halt_reg = 0x6830c, + .clkr = { + .enable_reg = 0x6830c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_ce_apb_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_ce_axi_clk = { + .halt_reg = 0x68308, + .clkr = { + .enable_reg = 0x68308, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_ce_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_crypto_clk = { + .halt_reg = 0x68314, + .clkr = { + .enable_reg = 0x68314, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_crypto_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_crypto_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_ppe_cfg_clk = { + .halt_reg = 0x68304, + .clkr = { + .enable_reg = 0x68304, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_ppe_cfg_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_ppe_clk = { + .halt_reg = 0x68300, + .clkr = { + .enable_reg = 0x68300, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_ppe_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { + .halt_reg = 0x68180, + .clkr = { + .enable_reg = 0x68180, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_qosgen_ref_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_snoc_clk = { + .halt_reg = 0x68188, + .clkr = { + .enable_reg = 0x68188, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_snoc_clk", + .parent_hws = (const struct clk_hw *[]){ + &system_noc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_timeout_ref_clk = { + .halt_reg = 0x68184, + .clkr = { + .enable_reg = 0x68184, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_timeout_ref_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_div4_clk_src.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = { + .halt_reg = 0x68270, + .clkr = { + .enable_reg = 0x68270, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_nssnoc_ubi0_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_port1_mac_clk = { + .halt_reg = 0x68320, + .clkr = { + .enable_reg = 0x68320, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_port1_mac_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_port2_mac_clk = { + .halt_reg = 0x68324, + .clkr = { + .enable_reg = 0x68324, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_port2_mac_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_port3_mac_clk = { + .halt_reg = 0x68328, + .clkr = { + .enable_reg = 0x68328, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_port3_mac_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_port4_mac_clk = { + .halt_reg = 0x6832c, + .clkr = { + .enable_reg = 0x6832c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_port4_mac_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_port5_mac_clk = { + .halt_reg = 0x68330, + .clkr = { + .enable_reg = 0x68330, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_port5_mac_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ppe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_ahb_clk = { + .halt_reg = 0x6820c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x6820c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ubi0_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ce_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_axi_clk = { + .halt_reg = 0x68200, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x68200, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ubi0_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &ubi32_mem_noc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_nc_axi_clk = { + .halt_reg = 0x68204, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x68204, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ubi0_nc_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &snoc_nssnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ubi0_core_clk = { + .halt_reg = 0x68210, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x68210, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ubi0_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_ubi0_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_ahb_clk = { + .halt_reg = 0x75010, + .clkr = { + .enable_reg = 0x75010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_aux_clk = { + .halt_reg = 0x75014, + .clkr = { + .enable_reg = 0x75014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_aux_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_aux_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_m_clk = { + .halt_reg = 0x75008, + .clkr = { + .enable_reg = 0x75008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_axi_m_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_axi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_clk = { + .halt_reg = 0x7500c, + .clkr = { + .enable_reg = 0x7500c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_axi_s_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_axi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_pcie0_axi_clk = { + .halt_reg = 0x26048, + .clkr = { + .enable_reg = 0x26048, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_pcie0_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_axi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_pipe_clk = { + .halt_reg = 0x75018, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x75018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_pipe_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_pipe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x13004, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x0b004, + .enable_mask = bit(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qdss_dap_clk = { + .halt_reg = 0x29084, + .clkr = { + .enable_reg = 0x29084, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qdss_dap_clk", + .parent_hws = (const struct clk_hw *[]){ + &qdss_dap_sync_clk_src.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_ahb_clk = { + .halt_reg = 0x57024, + .clkr = { + .enable_reg = 0x57024, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qpic_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qpic_clk = { + .halt_reg = 0x57020, + .clkr = { + .enable_reg = 0x57020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qpic_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ahb_clk = { + .halt_reg = 0x4201c, + .clkr = { + .enable_reg = 0x4201c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_apps_clk = { + .halt_reg = 0x42018, + .clkr = { + .enable_reg = 0x42018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_apps_clk", + .parent_hws = (const struct clk_hw *[]){ + &sdcc1_apps_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_ahb_clk = { + .halt_reg = 0x56008, + .clkr = { + .enable_reg = 0x56008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port1_rx_clk = { + .halt_reg = 0x56010, + .clkr = { + .enable_reg = 0x56010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port1_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port1_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port1_tx_clk = { + .halt_reg = 0x56014, + .clkr = { + .enable_reg = 0x56014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port1_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port1_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port2_rx_clk = { + .halt_reg = 0x56018, + .clkr = { + .enable_reg = 0x56018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port2_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port2_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port2_tx_clk = { + .halt_reg = 0x5601c, + .clkr = { + .enable_reg = 0x5601c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port2_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port2_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port3_rx_clk = { + .halt_reg = 0x56020, + .clkr = { + .enable_reg = 0x56020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port3_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port3_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port3_tx_clk = { + .halt_reg = 0x56024, + .clkr = { + .enable_reg = 0x56024, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port3_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port3_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port4_rx_clk = { + .halt_reg = 0x56028, + .clkr = { + .enable_reg = 0x56028, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port4_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port4_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port4_tx_clk = { + .halt_reg = 0x5602c, + .clkr = { + .enable_reg = 0x5602c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port4_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port4_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port5_rx_clk = { + .halt_reg = 0x56030, + .clkr = { + .enable_reg = 0x56030, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port5_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_port5_tx_clk = { + .halt_reg = 0x56034, + .clkr = { + .enable_reg = 0x56034, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_port5_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy0_sys_clk = { + .halt_reg = 0x5600c, + .clkr = { + .enable_reg = 0x5600c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy0_sys_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_ahb_clk = { + .halt_reg = 0x56108, + .clkr = { + .enable_reg = 0x56108, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy1_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_port5_rx_clk = { + .halt_reg = 0x56110, + .clkr = { + .enable_reg = 0x56110, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy1_port5_rx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_rx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_port5_tx_clk = { + .halt_reg = 0x56114, + .clkr = { + .enable_reg = 0x56114, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy1_port5_tx_clk", + .parent_hws = (const struct clk_hw *[]){ + &nss_port5_tx_div_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_uniphy1_sys_clk = { + .halt_reg = 0x5610c, + .clkr = { + .enable_reg = 0x5610c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_uniphy1_sys_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_aux_clk = { + .halt_reg = 0x3e044, + .clkr = { + .enable_reg = 0x3e044, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb0_aux_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb0_aux_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_master_clk = { + .halt_reg = 0x3e000, + .clkr = { + .enable_reg = 0x3e000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb0_master_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb0_master_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = { + .halt_reg = 0x47014, + .clkr = { + .enable_reg = 0x47014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_snoc_bus_timeout2_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb0_master_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_rcg2 pcie0_rchng_clk_src = { + .cmd_rcgr = 0x75070, + .freq_tbl = ftbl_pcie_rchng_clk_src, + .hid_width = 5, + .parent_map = gcc_xo_gpll0_map, + .clkr.hw.init = &(struct clk_init_data){ + .name = "pcie0_rchng_clk_src", + .parent_data = gcc_xo_gpll0, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_branch gcc_pcie0_rchng_clk = { + .halt_reg = 0x75070, + .clkr = { + .enable_reg = 0x75070, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_rchng_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_rchng_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { + .halt_reg = 0x75048, + .clkr = { + .enable_reg = 0x75048, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_axi_s_bridge_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcie0_axi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sys_noc_usb0_axi_clk = { + .halt_reg = 0x26040, + .clkr = { + .enable_reg = 0x26040, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sys_noc_usb0_axi_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb0_master_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_mock_utmi_clk = { + .halt_reg = 0x3e008, + .clkr = { + .enable_reg = 0x3e008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb0_mock_utmi_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb0_mock_utmi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { + .halt_reg = 0x3e080, + .clkr = { + .enable_reg = 0x3e080, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb0_phy_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_pipe_clk = { + .halt_reg = 0x3e040, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x3e040, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb0_pipe_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb0_pipe_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb0_sleep_clk = { + .halt_reg = 0x3e004, + .clkr = { + .enable_reg = 0x3e004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb0_sleep_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_sleep_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_master_clk = { + .halt_reg = 0x3f000, + .clkr = { + .enable_reg = 0x3f000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb1_master_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_mock_utmi_clk = { + .halt_reg = 0x3f008, + .clkr = { + .enable_reg = 0x3f008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb1_mock_utmi_clk", + .parent_hws = (const struct clk_hw *[]){ + &usb1_mock_utmi_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = { + .halt_reg = 0x3f080, + .clkr = { + .enable_reg = 0x3f080, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb1_phy_cfg_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb1_sleep_clk = { + .halt_reg = 0x3f004, + .clkr = { + .enable_reg = 0x3f004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb1_sleep_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_sleep_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_ahb_clk = { + .halt_reg = 0x56308, + .clkr = { + .enable_reg = 0x56308, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cmn_12gpll_ahb_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cmn_12gpll_sys_clk = { + .halt_reg = 0x5630c, + .clkr = { + .enable_reg = 0x5630c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cmn_12gpll_sys_clk", + .parent_hws = (const struct clk_hw *[]){ + &gcc_xo_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc1_ice_core_clk = { + .halt_reg = 0x5d014, + .clkr = { + .enable_reg = 0x5d014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc1_ice_core_clk", + .parent_hws = (const struct clk_hw *[]){ + &sdcc1_ice_core_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_dcc_clk = { + .halt_reg = 0x77004, + .clkr = { + .enable_reg = 0x77004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_dcc_clk", + .parent_hws = (const struct clk_hw *[]){ + &pcnoc_bfdcd_clk_src.clkr.hw }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x3e, + .alpha = 0x57, + .config_ctl_val = 0x240d6aa8, + .config_ctl_hi_val = 0x3c2, + .main_output_mask = bit(0), + .aux_output_mask = bit(1), + .pre_div_val = 0x0, + .pre_div_mask = bit(12), + .post_div_val = 0x0, + .post_div_mask = genmask(9, 8), +}; + +static const struct alpha_pll_config nss_crypto_pll_config = { + .l = 0x32, + .alpha = 0x0, + .alpha_hi = 0x0, + .config_ctl_val = 0x4001055b, + .main_output_mask = bit(0), + .pre_div_val = 0x0, + .pre_div_mask = genmask(14, 12), + .post_div_val = 0x1 << 8, + .post_div_mask = genmask(11, 8), + .vco_mask = genmask(21, 20), + .vco_val = 0x0, + .alpha_en_mask = bit(24), +}; + +static struct clk_hw *gcc_ipq6018_hws[] = { + &gpll0_out_main_div2.hw, + &gcc_xo_div4_clk_src.hw, + &nss_ppe_cdiv_clk_src.hw, + &gpll6_out_main_div2.hw, + &qdss_dap_sync_clk_src.hw, + &qdss_tsctr_div2_clk_src.hw, +}; + +static struct clk_regmap *gcc_ipq6018_clks[] = { + [gpll0_main] = &gpll0_main.clkr, + [gpll0] = &gpll0.clkr, + [ubi32_pll_main] = &ubi32_pll_main.clkr, + [ubi32_pll] = &ubi32_pll.clkr, + [gpll6_main] = &gpll6_main.clkr, + [gpll6] = &gpll6.clkr, + [gpll4_main] = &gpll4_main.clkr, + [gpll4] = &gpll4.clkr, + [pcnoc_bfdcd_clk_src] = &pcnoc_bfdcd_clk_src.clkr, + [gpll2_main] = &gpll2_main.clkr, + [gpll2] = &gpll2.clkr, + [nss_crypto_pll_main] = &nss_crypto_pll_main.clkr, + [nss_crypto_pll] = &nss_crypto_pll.clkr, + [qdss_tsctr_clk_src] = &qdss_tsctr_clk_src.clkr, + [qdss_at_clk_src] = &qdss_at_clk_src.clkr, + [nss_ppe_clk_src] = &nss_ppe_clk_src.clkr, + [gcc_xo_clk_src] = &gcc_xo_clk_src.clkr, + [system_noc_bfdcd_clk_src] = &system_noc_bfdcd_clk_src.clkr, + [snoc_nssnoc_bfdcd_clk_src] = &snoc_nssnoc_bfdcd_clk_src.clkr, + [nss_ce_clk_src] = &nss_ce_clk_src.clkr, + [gcc_sleep_clk_src] = &gcc_sleep_clk_src.clkr, + [apss_ahb_clk_src] = &apss_ahb_clk_src.clkr, + [nss_port5_rx_clk_src] = &nss_port5_rx_clk_src.clkr, + [nss_port5_tx_clk_src] = &nss_port5_tx_clk_src.clkr, + [ubi32_mem_noc_bfdcd_clk_src] = &ubi32_mem_noc_bfdcd_clk_src.clkr, + [pcie0_axi_clk_src] = &pcie0_axi_clk_src.clkr, + [usb0_master_clk_src] = &usb0_master_clk_src.clkr, + [apss_ahb_postdiv_clk_src] = &apss_ahb_postdiv_clk_src.clkr, + [nss_port1_rx_clk_src] = &nss_port1_rx_clk_src.clkr, + [nss_port1_tx_clk_src] = &nss_port1_tx_clk_src.clkr, + [nss_port2_rx_clk_src] = &nss_port2_rx_clk_src.clkr, + [nss_port2_tx_clk_src] = &nss_port2_tx_clk_src.clkr, + [nss_port3_rx_clk_src] = &nss_port3_rx_clk_src.clkr, + [nss_port3_tx_clk_src] = &nss_port3_tx_clk_src.clkr, + [nss_port4_rx_clk_src] = &nss_port4_rx_clk_src.clkr, + [nss_port4_tx_clk_src] = &nss_port4_tx_clk_src.clkr, + [nss_port5_rx_div_clk_src] = &nss_port5_rx_div_clk_src.clkr, + [nss_port5_tx_div_clk_src] = &nss_port5_tx_div_clk_src.clkr, + [apss_axi_clk_src] = &apss_axi_clk_src.clkr, + [nss_crypto_clk_src] = &nss_crypto_clk_src.clkr, + [nss_port1_rx_div_clk_src] = &nss_port1_rx_div_clk_src.clkr, + [nss_port1_tx_div_clk_src] = &nss_port1_tx_div_clk_src.clkr, + [nss_port2_rx_div_clk_src] = &nss_port2_rx_div_clk_src.clkr, + [nss_port2_tx_div_clk_src] = &nss_port2_tx_div_clk_src.clkr, + [nss_port3_rx_div_clk_src] = &nss_port3_rx_div_clk_src.clkr, + [nss_port3_tx_div_clk_src] = &nss_port3_tx_div_clk_src.clkr, + [nss_port4_rx_div_clk_src] = &nss_port4_rx_div_clk_src.clkr, + [nss_port4_tx_div_clk_src] = &nss_port4_tx_div_clk_src.clkr, + [nss_ubi0_clk_src] = &nss_ubi0_clk_src.clkr, + [adss_pwm_clk_src] = &adss_pwm_clk_src.clkr, + [blsp1_qup1_i2c_apps_clk_src] = &blsp1_qup1_i2c_apps_clk_src.clkr, + [blsp1_qup1_spi_apps_clk_src] = &blsp1_qup1_spi_apps_clk_src.clkr, + [blsp1_qup2_i2c_apps_clk_src] = &blsp1_qup2_i2c_apps_clk_src.clkr, + [blsp1_qup2_spi_apps_clk_src] = &blsp1_qup2_spi_apps_clk_src.clkr, + [blsp1_qup3_i2c_apps_clk_src] = &blsp1_qup3_i2c_apps_clk_src.clkr, + [blsp1_qup3_spi_apps_clk_src] = &blsp1_qup3_spi_apps_clk_src.clkr, + [blsp1_qup4_i2c_apps_clk_src] = &blsp1_qup4_i2c_apps_clk_src.clkr, + [blsp1_qup4_spi_apps_clk_src] = &blsp1_qup4_spi_apps_clk_src.clkr, + [blsp1_qup5_i2c_apps_clk_src] = &blsp1_qup5_i2c_apps_clk_src.clkr, + [blsp1_qup5_spi_apps_clk_src] = &blsp1_qup5_spi_apps_clk_src.clkr, + [blsp1_qup6_i2c_apps_clk_src] = &blsp1_qup6_i2c_apps_clk_src.clkr, + [blsp1_qup6_spi_apps_clk_src] = &blsp1_qup6_spi_apps_clk_src.clkr, + [blsp1_uart1_apps_clk_src] = &blsp1_uart1_apps_clk_src.clkr, + [blsp1_uart2_apps_clk_src] = &blsp1_uart2_apps_clk_src.clkr, + [blsp1_uart3_apps_clk_src] = &blsp1_uart3_apps_clk_src.clkr, + [blsp1_uart4_apps_clk_src] = &blsp1_uart4_apps_clk_src.clkr, + [blsp1_uart5_apps_clk_src] = &blsp1_uart5_apps_clk_src.clkr, + [blsp1_uart6_apps_clk_src] = &blsp1_uart6_apps_clk_src.clkr, + [crypto_clk_src] = &crypto_clk_src.clkr, + [gp1_clk_src] = &gp1_clk_src.clkr, + [gp2_clk_src] = &gp2_clk_src.clkr, + [gp3_clk_src] = &gp3_clk_src.clkr, + [nss_ubi0_div_clk_src] = &nss_ubi0_div_clk_src.clkr, + [pcie0_aux_clk_src] = &pcie0_aux_clk_src.clkr, + [pcie0_pipe_clk_src] = &pcie0_pipe_clk_src.clkr, + [sdcc1_apps_clk_src] = &sdcc1_apps_clk_src.clkr, + [usb0_aux_clk_src] = &usb0_aux_clk_src.clkr, + [usb0_mock_utmi_clk_src] = &usb0_mock_utmi_clk_src.clkr, + [usb0_pipe_clk_src] = &usb0_pipe_clk_src.clkr, + [usb1_mock_utmi_clk_src] = &usb1_mock_utmi_clk_src.clkr, + [gcc_adss_pwm_clk] = &gcc_adss_pwm_clk.clkr, + [gcc_apss_ahb_clk] = &gcc_apss_ahb_clk.clkr, + [gcc_apss_axi_clk] = &gcc_apss_axi_clk.clkr, + [gcc_blsp1_ahb_clk] = &gcc_blsp1_ahb_clk.clkr, + [gcc_blsp1_qup1_i2c_apps_clk] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, + [gcc_blsp1_qup1_spi_apps_clk] = &gcc_blsp1_qup1_spi_apps_clk.clkr, + [gcc_blsp1_qup2_i2c_apps_clk] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, + [gcc_blsp1_qup2_spi_apps_clk] = &gcc_blsp1_qup2_spi_apps_clk.clkr, + [gcc_blsp1_qup3_i2c_apps_clk] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, + [gcc_blsp1_qup3_spi_apps_clk] = &gcc_blsp1_qup3_spi_apps_clk.clkr, + [gcc_blsp1_qup4_i2c_apps_clk] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, + [gcc_blsp1_qup4_spi_apps_clk] = &gcc_blsp1_qup4_spi_apps_clk.clkr, + [gcc_blsp1_qup5_i2c_apps_clk] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, + [gcc_blsp1_qup5_spi_apps_clk] = &gcc_blsp1_qup5_spi_apps_clk.clkr, + [gcc_blsp1_qup6_spi_apps_clk] = &gcc_blsp1_qup6_spi_apps_clk.clkr, + [gcc_blsp1_uart1_apps_clk] = &gcc_blsp1_uart1_apps_clk.clkr, + [gcc_blsp1_uart2_apps_clk] = &gcc_blsp1_uart2_apps_clk.clkr, + [gcc_blsp1_uart3_apps_clk] = &gcc_blsp1_uart3_apps_clk.clkr, + [gcc_blsp1_uart4_apps_clk] = &gcc_blsp1_uart4_apps_clk.clkr, + [gcc_blsp1_uart5_apps_clk] = &gcc_blsp1_uart5_apps_clk.clkr, + [gcc_blsp1_uart6_apps_clk] = &gcc_blsp1_uart6_apps_clk.clkr, + [gcc_crypto_ahb_clk] = &gcc_crypto_ahb_clk.clkr, + [gcc_crypto_axi_clk] = &gcc_crypto_axi_clk.clkr, + [gcc_crypto_clk] = &gcc_crypto_clk.clkr, + [gcc_xo_clk] = &gcc_xo_clk.clkr, + [gcc_gp1_clk] = &gcc_gp1_clk.clkr, + [gcc_gp2_clk] = &gcc_gp2_clk.clkr, + [gcc_gp3_clk] = &gcc_gp3_clk.clkr, + [gcc_mdio_ahb_clk] = &gcc_mdio_ahb_clk.clkr, + [gcc_crypto_ppe_clk] = &gcc_crypto_ppe_clk.clkr, + [gcc_nss_ce_apb_clk] = &gcc_nss_ce_apb_clk.clkr, + [gcc_nss_ce_axi_clk] = &gcc_nss_ce_axi_clk.clkr, + [gcc_nss_cfg_clk] = &gcc_nss_cfg_clk.clkr, + [gcc_nss_crypto_clk] = &gcc_nss_crypto_clk.clkr, + [gcc_nss_csr_clk] = &gcc_nss_csr_clk.clkr, + [gcc_nss_edma_cfg_clk] = &gcc_nss_edma_cfg_clk.clkr, + [gcc_nss_edma_clk] = &gcc_nss_edma_clk.clkr, + [gcc_nss_noc_clk] = &gcc_nss_noc_clk.clkr, + [gcc_ubi0_utcm_clk] = &gcc_ubi0_utcm_clk.clkr, + [gcc_snoc_nssnoc_clk] = &gcc_snoc_nssnoc_clk.clkr, + [gcc_nss_port1_rx_clk] = &gcc_nss_port1_rx_clk.clkr, + [gcc_nss_port1_tx_clk] = &gcc_nss_port1_tx_clk.clkr, + [gcc_nss_port2_rx_clk] = &gcc_nss_port2_rx_clk.clkr, + [gcc_nss_port2_tx_clk] = &gcc_nss_port2_tx_clk.clkr, + [gcc_nss_port3_rx_clk] = &gcc_nss_port3_rx_clk.clkr, + [gcc_nss_port3_tx_clk] = &gcc_nss_port3_tx_clk.clkr, + [gcc_nss_port4_rx_clk] = &gcc_nss_port4_rx_clk.clkr, + [gcc_nss_port4_tx_clk] = &gcc_nss_port4_tx_clk.clkr, + [gcc_nss_port5_rx_clk] = &gcc_nss_port5_rx_clk.clkr, + [gcc_nss_port5_tx_clk] = &gcc_nss_port5_tx_clk.clkr, + [gcc_nss_ppe_cfg_clk] = &gcc_nss_ppe_cfg_clk.clkr, + [gcc_nss_ppe_clk] = &gcc_nss_ppe_clk.clkr, + [gcc_nss_ppe_ipe_clk] = &gcc_nss_ppe_ipe_clk.clkr, + [gcc_nss_ptp_ref_clk] = &gcc_nss_ptp_ref_clk.clkr, + [gcc_nssnoc_ce_apb_clk] = &gcc_nssnoc_ce_apb_clk.clkr, + [gcc_nssnoc_ce_axi_clk] = &gcc_nssnoc_ce_axi_clk.clkr, + [gcc_nssnoc_crypto_clk] = &gcc_nssnoc_crypto_clk.clkr, + [gcc_nssnoc_ppe_cfg_clk] = &gcc_nssnoc_ppe_cfg_clk.clkr, + [gcc_nssnoc_ppe_clk] = &gcc_nssnoc_ppe_clk.clkr, + [gcc_nssnoc_qosgen_ref_clk] = &gcc_nssnoc_qosgen_ref_clk.clkr, + [gcc_nssnoc_snoc_clk] = &gcc_nssnoc_snoc_clk.clkr, + [gcc_nssnoc_timeout_ref_clk] = &gcc_nssnoc_timeout_ref_clk.clkr, + [gcc_nssnoc_ubi0_ahb_clk] = &gcc_nssnoc_ubi0_ahb_clk.clkr, + [gcc_port1_mac_clk] = &gcc_port1_mac_clk.clkr, + [gcc_port2_mac_clk] = &gcc_port2_mac_clk.clkr, + [gcc_port3_mac_clk] = &gcc_port3_mac_clk.clkr, + [gcc_port4_mac_clk] = &gcc_port4_mac_clk.clkr, + [gcc_port5_mac_clk] = &gcc_port5_mac_clk.clkr, + [gcc_ubi0_ahb_clk] = &gcc_ubi0_ahb_clk.clkr, + [gcc_ubi0_axi_clk] = &gcc_ubi0_axi_clk.clkr, + [gcc_ubi0_nc_axi_clk] = &gcc_ubi0_nc_axi_clk.clkr, + [gcc_ubi0_core_clk] = &gcc_ubi0_core_clk.clkr, + [gcc_pcie0_ahb_clk] = &gcc_pcie0_ahb_clk.clkr, + [gcc_pcie0_aux_clk] = &gcc_pcie0_aux_clk.clkr, + [gcc_pcie0_axi_m_clk] = &gcc_pcie0_axi_m_clk.clkr, + [gcc_pcie0_axi_s_clk] = &gcc_pcie0_axi_s_clk.clkr, + [gcc_sys_noc_pcie0_axi_clk] = &gcc_sys_noc_pcie0_axi_clk.clkr, + [gcc_pcie0_pipe_clk] = &gcc_pcie0_pipe_clk.clkr, + [gcc_prng_ahb_clk] = &gcc_prng_ahb_clk.clkr, + [gcc_qdss_dap_clk] = &gcc_qdss_dap_clk.clkr, + [gcc_qpic_ahb_clk] = &gcc_qpic_ahb_clk.clkr, + [gcc_qpic_clk] = &gcc_qpic_clk.clkr, + [gcc_sdcc1_ahb_clk] = &gcc_sdcc1_ahb_clk.clkr, + [gcc_sdcc1_apps_clk] = &gcc_sdcc1_apps_clk.clkr, + [gcc_uniphy0_ahb_clk] = &gcc_uniphy0_ahb_clk.clkr, + [gcc_uniphy0_port1_rx_clk] = &gcc_uniphy0_port1_rx_clk.clkr, + [gcc_uniphy0_port1_tx_clk] = &gcc_uniphy0_port1_tx_clk.clkr, + [gcc_uniphy0_port2_rx_clk] = &gcc_uniphy0_port2_rx_clk.clkr, + [gcc_uniphy0_port2_tx_clk] = &gcc_uniphy0_port2_tx_clk.clkr, + [gcc_uniphy0_port3_rx_clk] = &gcc_uniphy0_port3_rx_clk.clkr, + [gcc_uniphy0_port3_tx_clk] = &gcc_uniphy0_port3_tx_clk.clkr, + [gcc_uniphy0_port4_rx_clk] = &gcc_uniphy0_port4_rx_clk.clkr, + [gcc_uniphy0_port4_tx_clk] = &gcc_uniphy0_port4_tx_clk.clkr, + [gcc_uniphy0_port5_rx_clk] = &gcc_uniphy0_port5_rx_clk.clkr, + [gcc_uniphy0_port5_tx_clk] = &gcc_uniphy0_port5_tx_clk.clkr, + [gcc_uniphy0_sys_clk] = &gcc_uniphy0_sys_clk.clkr, + [gcc_uniphy1_ahb_clk] = &gcc_uniphy1_ahb_clk.clkr, + [gcc_uniphy1_port5_rx_clk] = &gcc_uniphy1_port5_rx_clk.clkr, + [gcc_uniphy1_port5_tx_clk] = &gcc_uniphy1_port5_tx_clk.clkr, + [gcc_uniphy1_sys_clk] = &gcc_uniphy1_sys_clk.clkr, + [gcc_usb0_aux_clk] = &gcc_usb0_aux_clk.clkr, + [gcc_sys_noc_usb0_axi_clk] = &gcc_sys_noc_usb0_axi_clk.clkr, + [gcc_snoc_bus_timeout2_ahb_clk] = &gcc_snoc_bus_timeout2_ahb_clk.clkr, + [gcc_usb0_master_clk] = &gcc_usb0_master_clk.clkr, + [gcc_usb0_mock_utmi_clk] = &gcc_usb0_mock_utmi_clk.clkr, + [gcc_usb0_phy_cfg_ahb_clk] = &gcc_usb0_phy_cfg_ahb_clk.clkr, + [gcc_usb0_pipe_clk] = &gcc_usb0_pipe_clk.clkr, + [gcc_usb0_sleep_clk] = &gcc_usb0_sleep_clk.clkr, + [gcc_usb1_master_clk] = &gcc_usb1_master_clk.clkr, + [gcc_usb1_mock_utmi_clk] = &gcc_usb1_mock_utmi_clk.clkr, + [gcc_usb1_phy_cfg_ahb_clk] = &gcc_usb1_phy_cfg_ahb_clk.clkr, + [gcc_usb1_sleep_clk] = &gcc_usb1_sleep_clk.clkr, + [gcc_cmn_12gpll_ahb_clk] = &gcc_cmn_12gpll_ahb_clk.clkr, + [gcc_cmn_12gpll_sys_clk] = &gcc_cmn_12gpll_sys_clk.clkr, + [gcc_sdcc1_ice_core_clk] = &gcc_sdcc1_ice_core_clk.clkr, + [sdcc1_ice_core_clk_src] = &sdcc1_ice_core_clk_src.clkr, + [gcc_dcc_clk] = &gcc_dcc_clk.clkr, + [pcie0_rchng_clk_src] = &pcie0_rchng_clk_src.clkr, + [gcc_pcie0_axi_s_bridge_clk] = &gcc_pcie0_axi_s_bridge_clk.clkr, + [pcie0_rchng_clk] = &gcc_pcie0_rchng_clk.clkr, + [wcss_ahb_clk_src] = &wcss_ahb_clk_src.clkr, + [q6_axi_clk_src] = &q6_axi_clk_src.clkr, + [rbcpr_wcss_clk_src] = &rbcpr_wcss_clk_src.clkr, + [gcc_lpass_core_axim_clk] = &gcc_lpass_core_axim_clk.clkr, + [lpass_core_axim_clk_src] = &lpass_core_axim_clk_src.clkr, + [gcc_lpass_snoc_cfg_clk] = &gcc_lpass_snoc_cfg_clk.clkr, + [lpass_snoc_cfg_clk_src] = &lpass_snoc_cfg_clk_src.clkr, + [gcc_lpass_q6_axim_clk] = &gcc_lpass_q6_axim_clk.clkr, + [lpass_q6_axim_clk_src] = &lpass_q6_axim_clk_src.clkr, + [gcc_lpass_q6_atbm_at_clk] = &gcc_lpass_q6_atbm_at_clk.clkr, + [gcc_lpass_q6_pclkdbg_clk] = &gcc_lpass_q6_pclkdbg_clk.clkr, + [gcc_lpass_q6ss_tsctr_1to2_clk] = &gcc_lpass_q6ss_tsctr_1to2_clk.clkr, + [gcc_lpass_q6ss_trig_clk] = &gcc_lpass_q6ss_trig_clk.clkr, + [gcc_lpass_tbu_clk] = &gcc_lpass_tbu_clk.clkr, + [gcc_pcnoc_lpass_clk] = &gcc_pcnoc_lpass_clk.clkr, + [gcc_mem_noc_ubi32_clk] = &gcc_mem_noc_ubi32_clk.clkr, + [gcc_mem_noc_lpass_clk] = &gcc_mem_noc_lpass_clk.clkr, + [gcc_snoc_lpass_cfg_clk] = &gcc_snoc_lpass_cfg_clk.clkr, + [qdss_stm_clk_src] = &qdss_stm_clk_src.clkr, + [qdss_traceclkin_clk_src] = &qdss_traceclkin_clk_src.clkr, +}; + +static const struct qcom_reset_map gcc_ipq6018_resets[] = { + [gcc_blsp1_bcr] = { 0x01000, 0 }, + [gcc_blsp1_qup1_bcr] = { 0x02000, 0 }, + [gcc_blsp1_uart1_bcr] = { 0x02038, 0 }, + [gcc_blsp1_qup2_bcr] = { 0x03008, 0 }, + [gcc_blsp1_uart2_bcr] = { 0x03028, 0 }, + [gcc_blsp1_qup3_bcr] = { 0x04008, 0 }, + [gcc_blsp1_uart3_bcr] = { 0x04028, 0 }, + [gcc_blsp1_qup4_bcr] = { 0x05008, 0 }, + [gcc_blsp1_uart4_bcr] = { 0x05028, 0 }, + [gcc_blsp1_qup5_bcr] = { 0x06008, 0 }, + [gcc_blsp1_uart5_bcr] = { 0x06028, 0 }, + [gcc_blsp1_qup6_bcr] = { 0x07008, 0 }, + [gcc_blsp1_uart6_bcr] = { 0x07028, 0 }, + [gcc_imem_bcr] = { 0x0e000, 0 }, + [gcc_smmu_bcr] = { 0x12000, 0 }, + [gcc_apss_tcu_bcr] = { 0x12050, 0 }, + [gcc_smmu_xpu_bcr] = { 0x12054, 0 }, + [gcc_pcnoc_tbu_bcr] = { 0x12058, 0 }, + [gcc_smmu_cfg_bcr] = { 0x1208c, 0 }, + [gcc_prng_bcr] = { 0x13000, 0 }, + [gcc_boot_rom_bcr] = { 0x13008, 0 }, + [gcc_crypto_bcr] = { 0x16000, 0 }, + [gcc_wcss_bcr] = { 0x18000, 0 }, + [gcc_wcss_q6_bcr] = { 0x18100, 0 }, + [gcc_nss_bcr] = { 0x19000, 0 }, + [gcc_sec_ctrl_bcr] = { 0x1a000, 0 }, + [gcc_adss_bcr] = { 0x1c000, 0 }, + [gcc_ddrss_bcr] = { 0x1e000, 0 }, + [gcc_system_noc_bcr] = { 0x26000, 0 }, + [gcc_pcnoc_bcr] = { 0x27018, 0 }, + [gcc_tcsr_bcr] = { 0x28000, 0 }, + [gcc_qdss_bcr] = { 0x29000, 0 }, + [gcc_dcd_bcr] = { 0x2a000, 0 }, + [gcc_msg_ram_bcr] = { 0x2b000, 0 }, + [gcc_mpm_bcr] = { 0x2c000, 0 }, + [gcc_spdm_bcr] = { 0x2f000, 0 }, + [gcc_rbcpr_bcr] = { 0x33000, 0 }, + [gcc_rbcpr_mx_bcr] = { 0x33014, 0 }, + [gcc_tlmm_bcr] = { 0x34000, 0 }, + [gcc_rbcpr_wcss_bcr] = { 0x3a000, 0 }, + [gcc_usb0_phy_bcr] = { 0x3e034, 0 }, + [gcc_usb3phy_0_phy_bcr] = { 0x3e03c, 0 }, + [gcc_usb0_bcr] = { 0x3e070, 0 }, + [gcc_usb1_bcr] = { 0x3f070, 0 }, + [gcc_qusb2_0_phy_bcr] = { 0x4103c, 0 }, + [gcc_qusb2_1_phy_bcr] = { 0x41040, 0 }, + [gcc_sdcc1_bcr] = { 0x42000, 0 }, + [gcc_snoc_bus_timeout0_bcr] = { 0x47000, 0 }, + [gcc_snoc_bus_timeout1_bcr] = { 0x47008, 0 }, + [gcc_snoc_bus_timeout2_bcr] = { 0x47010, 0 }, + [gcc_pcnoc_bus_timeout0_bcr] = { 0x48000, 0 }, + [gcc_pcnoc_bus_timeout1_bcr] = { 0x48008, 0 }, + [gcc_pcnoc_bus_timeout2_bcr] = { 0x48010, 0 }, + [gcc_pcnoc_bus_timeout3_bcr] = { 0x48018, 0 }, + [gcc_pcnoc_bus_timeout4_bcr] = { 0x48020, 0 }, + [gcc_pcnoc_bus_timeout5_bcr] = { 0x48028, 0 }, + [gcc_pcnoc_bus_timeout6_bcr] = { 0x48030, 0 }, + [gcc_pcnoc_bus_timeout7_bcr] = { 0x48038, 0 }, + [gcc_pcnoc_bus_timeout8_bcr] = { 0x48040, 0 }, + [gcc_pcnoc_bus_timeout9_bcr] = { 0x48048, 0 }, + [gcc_uniphy0_bcr] = { 0x56000, 0 }, + [gcc_uniphy1_bcr] = { 0x56100, 0 }, + [gcc_cmn_12gpll_bcr] = { 0x56300, 0 }, + [gcc_qpic_bcr] = { 0x57018, 0 }, + [gcc_mdio_bcr] = { 0x58000, 0 }, + [gcc_wcss_core_tbu_bcr] = { 0x66000, 0 }, + [gcc_wcss_q6_tbu_bcr] = { 0x67000, 0 }, + [gcc_usb0_tbu_bcr] = { 0x6a000, 0 }, + [gcc_pcie0_tbu_bcr] = { 0x6b000, 0 }, + [gcc_nss_noc_tbu_bcr] = { 0x6e000, 0 }, + [gcc_pcie0_bcr] = { 0x75004, 0 }, + [gcc_pcie0_phy_bcr] = { 0x75038, 0 }, + [gcc_pcie0phy_phy_bcr] = { 0x7503c, 0 }, + [gcc_pcie0_link_down_bcr] = { 0x75044, 0 }, + [gcc_dcc_bcr] = { 0x77000, 0 }, + [gcc_apc0_voltage_droop_detector_bcr] = { 0x78000, 0 }, + [gcc_smmu_cats_bcr] = { 0x7c000, 0 }, + [gcc_ubi0_axi_ares] = { 0x68010, 0 }, + [gcc_ubi0_ahb_ares] = { 0x68010, 1 }, + [gcc_ubi0_nc_axi_ares] = { 0x68010, 2 }, + [gcc_ubi0_dbg_ares] = { 0x68010, 3 }, + [gcc_ubi0_core_clamp_enable] = { 0x68010, 4 }, + [gcc_ubi0_clkrst_clamp_enable] = { 0x68010, 5 }, + [gcc_ubi0_utcm_ares] = { 0x68010, 6 }, + [gcc_ubi0_core_ares] = { 0x68010, 7 }, + [gcc_nss_cfg_ares] = { 0x68010, 16 }, + [gcc_nss_noc_ares] = { 0x68010, 18 }, + [gcc_nss_crypto_ares] = { 0x68010, 19 }, + [gcc_nss_csr_ares] = { 0x68010, 20 }, + [gcc_nss_ce_apb_ares] = { 0x68010, 21 }, + [gcc_nss_ce_axi_ares] = { 0x68010, 22 }, + [gcc_nssnoc_ce_apb_ares] = { 0x68010, 23 }, + [gcc_nssnoc_ce_axi_ares] = { 0x68010, 24 }, + [gcc_nssnoc_ubi0_ahb_ares] = { 0x68010, 25 }, + [gcc_nssnoc_snoc_ares] = { 0x68010, 27 }, + [gcc_nssnoc_crypto_ares] = { 0x68010, 28 }, + [gcc_nssnoc_atb_ares] = { 0x68010, 29 }, + [gcc_nssnoc_qosgen_ref_ares] = { 0x68010, 30 }, + [gcc_nssnoc_timeout_ref_ares] = { 0x68010, 31 }, + [gcc_pcie0_pipe_ares] = { 0x75040, 0 }, + [gcc_pcie0_sleep_ares] = { 0x75040, 1 }, + [gcc_pcie0_core_sticky_ares] = { 0x75040, 2 }, + [gcc_pcie0_axi_master_ares] = { 0x75040, 3 }, + [gcc_pcie0_axi_slave_ares] = { 0x75040, 4 }, + [gcc_pcie0_ahb_ares] = { 0x75040, 5 }, + [gcc_pcie0_axi_master_sticky_ares] = { 0x75040, 6 }, + [gcc_pcie0_axi_slave_sticky_ares] = { 0x75040, 7 }, + [gcc_ppe_full_reset] = { 0x68014, 0 }, + [gcc_uniphy0_soft_reset] = { 0x56004, 0 }, + [gcc_uniphy0_xpcs_reset] = { 0x56004, 2 }, + [gcc_uniphy1_soft_reset] = { 0x56104, 0 }, + [gcc_uniphy1_xpcs_reset] = { 0x56104, 2 }, + [gcc_edma_hw_reset] = { 0x68014, 0 }, + [gcc_nssport1_reset] = { 0x68014, 0 }, + [gcc_nssport2_reset] = { 0x68014, 0 }, + [gcc_nssport3_reset] = { 0x68014, 0 }, + [gcc_nssport4_reset] = { 0x68014, 0 }, + [gcc_nssport5_reset] = { 0x68014, 0 }, + [gcc_uniphy0_port1_ares] = { 0x56004, 0 }, + [gcc_uniphy0_port2_ares] = { 0x56004, 0 }, + [gcc_uniphy0_port3_ares] = { 0x56004, 0 }, + [gcc_uniphy0_port4_ares] = { 0x56004, 0 }, + [gcc_uniphy0_port5_ares] = { 0x56004, 0 }, + [gcc_uniphy0_port_4_5_reset] = { 0x56004, 0 }, + [gcc_uniphy0_port_4_reset] = { 0x56004, 0 }, + [gcc_lpass_bcr] = {0x1f000, 0}, + [gcc_ubi32_tbu_bcr] = {0x65000, 0}, + [gcc_lpass_tbu_bcr] = {0x6c000, 0}, + [gcc_wcssaon_reset] = {0x59010, 0}, + [gcc_lpass_q6_axim_ares] = {0x1f004, 0}, + [gcc_lpass_q6ss_tsctr_1to2_ares] = {0x1f004, 1}, + [gcc_lpass_q6ss_trig_ares] = {0x1f004, 2}, + [gcc_lpass_q6_atbm_at_ares] = {0x1f004, 3}, + [gcc_lpass_q6_pclkdbg_ares] = {0x1f004, 4}, + [gcc_lpass_core_axim_ares] = {0x1f004, 5}, + [gcc_lpass_snoc_cfg_ares] = {0x1f004, 6}, + [gcc_wcss_dbg_ares] = {0x59008, 0}, + [gcc_wcss_ecahb_ares] = {0x59008, 1}, + [gcc_wcss_acmt_ares] = {0x59008, 2}, + [gcc_wcss_dbg_bdg_ares] = {0x59008, 3}, + [gcc_wcss_ahb_s_ares] = {0x59008, 4}, + [gcc_wcss_axi_m_ares] = {0x59008, 5}, + [gcc_q6ss_dbg_ares] = {0x59110, 0}, + [gcc_q6_ahb_s_ares] = {0x59110, 1}, + [gcc_q6_ahb_ares] = {0x59110, 2}, + [gcc_q6_axim2_ares] = {0x59110, 3}, + [gcc_q6_axim_ares] = {0x59110, 4}, +}; + +static const struct of_device_id gcc_ipq6018_match_table[] = { + { .compatible = "qcom,gcc-ipq6018" }, + { } +}; +module_device_table(of, gcc_ipq6018_match_table); + +static const struct regmap_config gcc_ipq6018_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x7fffc, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_ipq6018_desc = { + .config = &gcc_ipq6018_regmap_config, + .clks = gcc_ipq6018_clks, + .num_clks = array_size(gcc_ipq6018_clks), + .resets = gcc_ipq6018_resets, + .num_resets = array_size(gcc_ipq6018_resets), + .clk_hws = gcc_ipq6018_hws, + .num_clk_hws = array_size(gcc_ipq6018_hws), +}; + +static int gcc_ipq6018_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + + regmap = qcom_cc_map(pdev, &gcc_ipq6018_desc); + if (is_err(regmap)) + return ptr_err(regmap); + + /* disable sw_collapse for usb0 gdscr */ + regmap_update_bits(regmap, 0x3e078, bit(0), 0x0); + /* enable sw_override for usb0 gdscr */ + regmap_update_bits(regmap, 0x3e078, bit(2), bit(2)); + /* disable sw_collapse for usb1 gdscr */ + regmap_update_bits(regmap, 0x3f078, bit(0), 0x0); + /* enable sw_override for usb1 gdscr */ + regmap_update_bits(regmap, 0x3f078, bit(2), bit(2)); + + /* sw workaround for ubi huyara pll */ + regmap_update_bits(regmap, 0x2501c, bit(26), bit(26)); + + clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); + + clk_alpha_pll_configure(&nss_crypto_pll_main, regmap, + &nss_crypto_pll_config); + + return qcom_cc_really_probe(pdev, &gcc_ipq6018_desc, regmap); +} + +static struct platform_driver gcc_ipq6018_driver = { + .probe = gcc_ipq6018_probe, + .driver = { + .name = "qcom,gcc-ipq6018", + .of_match_table = gcc_ipq6018_match_table, + }, +}; + +static int __init gcc_ipq6018_init(void) +{ + return platform_driver_register(&gcc_ipq6018_driver); +} +core_initcall(gcc_ipq6018_init); + +static void __exit gcc_ipq6018_exit(void) +{ + platform_driver_unregister(&gcc_ipq6018_driver); +} +module_exit(gcc_ipq6018_exit); + +module_description("qualcomm technologies, inc. gcc ipq6018 driver"); +module_license("gpl v2"); | Clock | d9db07f088af01a1080d01de363141b673c7d646 | sricharan r | drivers | clk | qcom |
clk: qcom: add video clock controller driver for sc7180 | add support for the video clock controller found on sc7180 based devices. this would allow video drivers to probe and control their clocks. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add video clock controller driver for sc7180 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['qcom'] | ['c', 'kconfig', 'makefile'] | 3 | 268 | 0 | --- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config sc_videocc_7180 + tristate "sc7180 video clock controller" + select sc_gcc_7180 + help + support for the video clock controller on sc7180 devices. + say y if you want to support video devices and functionality such as + video encode and decode. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_sc_videocc_7180) += videocc-sc7180.o diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-sc7180.c --- /dev/null +++ b/drivers/clk/qcom/videocc-sc7180.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2019, the linux foundation. all rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,videocc-sc7180.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "common.h" +#include "gdsc.h" + +enum { + p_bi_tcxo, + p_chip_sleep_clk, + p_core_bi_pll_test_se, + p_video_pll0_out_even, + p_video_pll0_out_main, + p_video_pll0_out_odd, +}; + +static const struct pll_vco fabia_vco[] = { + { 249600000, 2000000000, 0 }, +}; + +static struct clk_alpha_pll video_pll0 = { + .offset = 0x42c, + .vco_table = fabia_vco, + .num_vco = array_size(fabia_vco), + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_fabia], + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "video_pll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fabia_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_1[] = { + { p_bi_tcxo, 0 }, + { p_video_pll0_out_main, 1 }, + { p_core_bi_pll_test_se, 7 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &video_pll0.clkr.hw }, + { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, +}; + +static const struct freq_tbl ftbl_video_cc_venus_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + f(150000000, p_video_pll0_out_main, 4, 0, 0), + f(270000000, p_video_pll0_out_main, 2.5, 0, 0), + f(340000000, p_video_pll0_out_main, 2, 0, 0), + f(434000000, p_video_pll0_out_main, 2, 0, 0), + f(500000000, p_video_pll0_out_main, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_venus_clk_src = { + .cmd_rcgr = 0x7f0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = video_cc_parent_map_1, + .freq_tbl = ftbl_video_cc_venus_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_clk_src", + .parent_data = video_cc_parent_data_1, + .num_parents = 3, + .flags = clk_set_rate_parent, + .ops = &clk_rcg2_shared_ops, + }, +}; + +static struct clk_branch video_cc_vcodec0_axi_clk = { + .halt_reg = 0x9ec, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x9ec, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_vcodec0_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_vcodec0_core_clk = { + .halt_reg = 0x890, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x890, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_vcodec0_core_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &video_cc_venus_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ahb_clk = { + .halt_reg = 0xa4c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xa4c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_axi_clk = { + .halt_reg = 0x9cc, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x9cc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_ctl_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_venus_ctl_core_clk = { + .halt_reg = 0x850, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x850, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "video_cc_venus_ctl_core_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &video_cc_venus_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc venus_gdsc = { + .gdscr = 0x814, + .pd = { + .name = "venus_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc vcodec0_gdsc = { + .gdscr = 0x874, + .pd = { + .name = "vcodec0_gdsc", + }, + .flags = hw_ctrl, + .pwrsts = pwrsts_off_on, +}; + +static struct clk_regmap *video_cc_sc7180_clocks[] = { + [video_cc_vcodec0_axi_clk] = &video_cc_vcodec0_axi_clk.clkr, + [video_cc_vcodec0_core_clk] = &video_cc_vcodec0_core_clk.clkr, + [video_cc_venus_ahb_clk] = &video_cc_venus_ahb_clk.clkr, + [video_cc_venus_clk_src] = &video_cc_venus_clk_src.clkr, + [video_cc_venus_ctl_axi_clk] = &video_cc_venus_ctl_axi_clk.clkr, + [video_cc_venus_ctl_core_clk] = &video_cc_venus_ctl_core_clk.clkr, + [video_pll0] = &video_pll0.clkr, +}; + +static struct gdsc *video_cc_sc7180_gdscs[] = { + [venus_gdsc] = &venus_gdsc, + [vcodec0_gdsc] = &vcodec0_gdsc, +}; + +static const struct regmap_config video_cc_sc7180_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0xb94, + .fast_io = true, +}; + +static const struct qcom_cc_desc video_cc_sc7180_desc = { + .config = &video_cc_sc7180_regmap_config, + .clks = video_cc_sc7180_clocks, + .num_clks = array_size(video_cc_sc7180_clocks), + .gdscs = video_cc_sc7180_gdscs, + .num_gdscs = array_size(video_cc_sc7180_gdscs), +}; + +static const struct of_device_id video_cc_sc7180_match_table[] = { + { .compatible = "qcom,sc7180-videocc" }, + { } +}; +module_device_table(of, video_cc_sc7180_match_table); + +static int video_cc_sc7180_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + struct alpha_pll_config video_pll0_config = {}; + + regmap = qcom_cc_map(pdev, &video_cc_sc7180_desc); + if (is_err(regmap)) + return ptr_err(regmap); + + video_pll0_config.l = 0x1f; + video_pll0_config.alpha = 0x4000; + video_pll0_config.user_ctl_val = 0x00000001; + video_pll0_config.user_ctl_hi_val = 0x00004805; + + clk_fabia_pll_configure(&video_pll0, regmap, &video_pll0_config); + + /* keep video_cc_xo_clk always-on */ + regmap_update_bits(regmap, 0x984, 0x1, 0x1); + + return qcom_cc_really_probe(pdev, &video_cc_sc7180_desc, regmap); +} + +static struct platform_driver video_cc_sc7180_driver = { + .probe = video_cc_sc7180_probe, + .driver = { + .name = "sc7180-videocc", + .of_match_table = video_cc_sc7180_match_table, + }, +}; + +static int __init video_cc_sc7180_init(void) +{ + return platform_driver_register(&video_cc_sc7180_driver); +} +subsys_initcall(video_cc_sc7180_init); + +static void __exit video_cc_sc7180_exit(void) +{ + platform_driver_unregister(&video_cc_sc7180_driver); +} +module_exit(video_cc_sc7180_exit); + +module_license("gpl v2"); +module_description("qti videocc sc7180 driver"); | Clock | 253dc75a0bb8f6207b3ac5f4897871b7b47a554e | taniya das | drivers | clk | qcom |
clocksource/drivers/timer-microchip-pit64b: add microchip pit64b support | add driver for microchip pit64b timer. timer could be used in continuous mode or oneshot mode. the hardware has 2x32 bit registers for period emulating a 64 bit timer. the lsb_pr and msb_pr registers are used to set the period value (compare value). tlsb and tmsb keeps the current value of the counter. after a compare the tlsb and tmsb register resets. the driver uses pit64b timer for clocksource or clockevent. first requested timer would be registered as clockevent, second one would be registered as clocksource. individual pit64b hardware resources were used for clocksource and clockevent to be able to support high resolution timers with this hardware implementation. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add microchip pit64b support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['timer-microchip-pit64b'] | ['c', 'kconfig', 'makefile', 'txt'] | 4 | 466 | 0 | --- diff --git a/documentation/devicetree/bindings/arm/atmel-sysregs.txt b/documentation/devicetree/bindings/arm/atmel-sysregs.txt --- a/documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/documentation/devicetree/bindings/arm/atmel-sysregs.txt - interrupts: should contain interrupt for the pit which is the irq line +pit64b timer required properties: +- compatible: should be "microchip,sam9x60-pit64b" +- reg: should contain registers location and length +- interrupts: should contain interrupt for pit64b timer +- clocks: should contain the available clock sources for pit64b timer. + - compatible: should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: should contain registers location and length diff --git a/drivers/clocksource/kconfig b/drivers/clocksource/kconfig --- a/drivers/clocksource/kconfig +++ b/drivers/clocksource/kconfig +config microchip_pit64b + bool "microchip pit64b support" + depends on of || compile_test + select clksrc_mmio + help + this option enables microchip pit64b timer for atmel + based system. it supports the oneshot, the periodic + modes and high resolution. it is used as a clocksource + and a clockevent. + diff --git a/drivers/clocksource/makefile b/drivers/clocksource/makefile --- a/drivers/clocksource/makefile +++ b/drivers/clocksource/makefile +obj-$(config_microchip_pit64b) += timer-microchip-pit64b.o diff --git a/drivers/clocksource/timer-microchip-pit64b.c b/drivers/clocksource/timer-microchip-pit64b.c --- /dev/null +++ b/drivers/clocksource/timer-microchip-pit64b.c +// spdx-license-identifier: gpl-2.0 +/* + * 64-bit periodic interval timer driver + * + * copyright (c) 2019 microchip technology inc. and its subsidiaries + * + * author: claudiu beznea <claudiu.beznea@microchip.com> + */ + +#include <linux/clk.h> +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> +#include <linux/sched_clock.h> +#include <linux/slab.h> + +#define mchp_pit64b_cr 0x00 /* control register */ +#define mchp_pit64b_cr_start bit(0) +#define mchp_pit64b_cr_swrst bit(8) + +#define mchp_pit64b_mr 0x04 /* mode register */ +#define mchp_pit64b_mr_cont bit(0) +#define mchp_pit64b_mr_one_shot (0) +#define mchp_pit64b_mr_sgclk bit(3) +#define mchp_pit64b_mr_pres genmask(11, 8) + +#define mchp_pit64b_lsb_pr 0x08 /* lsb period register */ + +#define mchp_pit64b_msb_pr 0x0c /* msb period register */ + +#define mchp_pit64b_ier 0x10 /* interrupt enable register */ +#define mchp_pit64b_ier_period bit(0) + +#define mchp_pit64b_isr 0x1c /* interrupt status register */ + +#define mchp_pit64b_tlsbr 0x20 /* timer lsb register */ + +#define mchp_pit64b_tmsbr 0x24 /* timer msb register */ + +#define mchp_pit64b_pres_max 0x10 +#define mchp_pit64b_lsbmask genmask_ull(31, 0) +#define mchp_pit64b_pres_to_mode(p) (mchp_pit64b_mr_pres & ((p) << 8)) +#define mchp_pit64b_mode_to_pres(m) ((mchp_pit64b_mr_pres & (m)) >> 8) +#define mchp_pit64b_def_cs_freq 5000000ul /* 5 mhz */ +#define mchp_pit64b_def_ce_freq 32768 /* 32 khz */ + +#define mchp_pit64b_name "pit64b" + +/** + * struct mchp_pit64b_timer - pit64b timer data structure + * @base: base address of pit64b hardware block + * @pclk: pit64b's peripheral clock + * @gclk: pit64b's generic clock + * @mode: precomputed value for mode register + */ +struct mchp_pit64b_timer { + void __iomem *base; + struct clk *pclk; + struct clk *gclk; + u32 mode; +}; + +/** + * mchp_pit64b_clkevt - pit64b clockevent data structure + * @timer: pit64b timer + * @clkevt: clockevent + */ +struct mchp_pit64b_clkevt { + struct mchp_pit64b_timer timer; + struct clock_event_device clkevt; +}; + +#define to_mchp_pit64b_timer(x) \ + ((struct mchp_pit64b_timer *)container_of(x,\ + struct mchp_pit64b_clkevt, clkevt)) + +/* base address for clocksource timer. */ +static void __iomem *mchp_pit64b_cs_base; +/* default cycles for clockevent timer. */ +static u64 mchp_pit64b_ce_cycles; + +static inline u64 mchp_pit64b_cnt_read(void __iomem *base) +{ + unsigned long flags; + u32 low, high; + + raw_local_irq_save(flags); + + /* + * when using a 64 bit period tlsb must be read first, followed by the + * read of tmsb. this sequence generates an atomic read of the 64 bit + * timer value whatever the lapse of time between the accesses. + */ + low = readl_relaxed(base + mchp_pit64b_tlsbr); + high = readl_relaxed(base + mchp_pit64b_tmsbr); + + raw_local_irq_restore(flags); + + return (((u64)high << 32) | low); +} + +static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer, + u64 cycles, u32 mode, u32 irqs) +{ + u32 low, high; + + low = cycles & mchp_pit64b_lsbmask; + high = cycles >> 32; + + writel_relaxed(mchp_pit64b_cr_swrst, timer->base + mchp_pit64b_cr); + writel_relaxed(mode | timer->mode, timer->base + mchp_pit64b_mr); + writel_relaxed(high, timer->base + mchp_pit64b_msb_pr); + writel_relaxed(low, timer->base + mchp_pit64b_lsb_pr); + writel_relaxed(irqs, timer->base + mchp_pit64b_ier); + writel_relaxed(mchp_pit64b_cr_start, timer->base + mchp_pit64b_cr); +} + +static u64 mchp_pit64b_clksrc_read(struct clocksource *cs) +{ + return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); +} + +static u64 mchp_pit64b_sched_read_clk(void) +{ + return mchp_pit64b_cnt_read(mchp_pit64b_cs_base); +} + +static int mchp_pit64b_clkevt_shutdown(struct clock_event_device *cedev) +{ + struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); + + writel_relaxed(mchp_pit64b_cr_swrst, timer->base + mchp_pit64b_cr); + + return 0; +} + +static int mchp_pit64b_clkevt_set_periodic(struct clock_event_device *cedev) +{ + struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); + + mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, mchp_pit64b_mr_cont, + mchp_pit64b_ier_period); + + return 0; +} + +static int mchp_pit64b_clkevt_set_next_event(unsigned long evt, + struct clock_event_device *cedev) +{ + struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); + + mchp_pit64b_reset(timer, evt, mchp_pit64b_mr_one_shot, + mchp_pit64b_ier_period); + + return 0; +} + +static void mchp_pit64b_clkevt_suspend(struct clock_event_device *cedev) +{ + struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); + + writel_relaxed(mchp_pit64b_cr_swrst, timer->base + mchp_pit64b_cr); + if (timer->mode & mchp_pit64b_mr_sgclk) + clk_disable_unprepare(timer->gclk); + clk_disable_unprepare(timer->pclk); +} + +static void mchp_pit64b_clkevt_resume(struct clock_event_device *cedev) +{ + struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev); + + clk_prepare_enable(timer->pclk); + if (timer->mode & mchp_pit64b_mr_sgclk) + clk_prepare_enable(timer->gclk); +} + +static irqreturn_t mchp_pit64b_interrupt(int irq, void *dev_id) +{ + struct mchp_pit64b_clkevt *irq_data = dev_id; + + /* need to clear the interrupt. */ + readl_relaxed(irq_data->timer.base + mchp_pit64b_isr); + + irq_data->clkevt.event_handler(&irq_data->clkevt); + + return irq_handled; +} + +static void __init mchp_pit64b_pres_compute(u32 *pres, u32 clk_rate, + u32 max_rate) +{ + u32 tmp; + + for (*pres = 0; *pres < mchp_pit64b_pres_max; (*pres)++) { + tmp = clk_rate / (*pres + 1); + if (tmp <= max_rate) + break; + } + + /* use the bigest prescaler if we didn't match one. */ + if (*pres == mchp_pit64b_pres_max) + *pres = mchp_pit64b_pres_max - 1; +} + +/** + * mchp_pit64b_init_mode - prepare pit64b mode register value to be used at + * runtime; this includes prescaler and sgclk bit + * + * pit64b timer may be fed by gclk or pclk. when gclk is used its rate has to + * be at least 3 times lower that pclk's rate. pclk rate is fixed, gclk rate + * could be changed via clock apis. the chosen clock (pclk or gclk) could be + * divided by the internal pit64b's divider. + * + * this function, first tries to use gclk by requesting the desired rate from + * pmc and then using the internal pit64b prescaler, if any, to reach the + * requested rate. if pclk/gclk < 3 (condition requested by pit64b hardware) + * then the function falls back on using pclk as clock source for pit64b timer + * choosing the highest prescaler in case it doesn't locate one to match the + * requested frequency. + * + * below is presented the pit64b block in relation with pmc: + * + * pit64b + * pmc +------------------------------------+ + * +----+ | +-----+ | + * | |-->gclk -->|-->| | +---------+ +-----+ | + * | | | | mux |--->| divider |->|timer| | + * | |-->pclk -->|-->| | +---------+ +-----+ | + * +----+ | +-----+ | + * | ^ | + * | sel | + * +------------------------------------+ + * + * where: + * - gclk rate <= pclk rate/3 + * - gclk rate could be requested from pmc + * - pclk rate is fixed (cannot be requested from pmc) + */ +static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer, + unsigned long max_rate) +{ + unsigned long pclk_rate, diff = 0, best_diff = ulong_max; + long gclk_round = 0; + u32 pres, best_pres = 0; + + pclk_rate = clk_get_rate(timer->pclk); + if (!pclk_rate) + return -einval; + + /* try using gclk. */ + gclk_round = clk_round_rate(timer->gclk, max_rate); + if (gclk_round < 0) + goto pclk; + + if (pclk_rate / gclk_round < 3) + goto pclk; + + mchp_pit64b_pres_compute(&pres, gclk_round, max_rate); + best_diff = abs(gclk_round / (pres + 1) - max_rate); + best_pres = pres; + + if (!best_diff) { + timer->mode |= mchp_pit64b_mr_sgclk; + goto done; + } + +pclk: + /* check if requested rate could be obtained using pclk. */ + mchp_pit64b_pres_compute(&pres, pclk_rate, max_rate); + diff = abs(pclk_rate / (pres + 1) - max_rate); + + if (best_diff > diff) { + /* use pclk. */ + best_pres = pres; + } else { + /* use gclk. */ + timer->mode |= mchp_pit64b_mr_sgclk; + clk_set_rate(timer->gclk, gclk_round); + } + +done: + timer->mode |= mchp_pit64b_pres_to_mode(best_pres); + + pr_info("pit64b: using clk=%s with prescaler %u, freq=%lu [hz] ", + timer->mode & mchp_pit64b_mr_sgclk ? "gclk" : "pclk", best_pres, + timer->mode & mchp_pit64b_mr_sgclk ? + gclk_round / (best_pres + 1) : pclk_rate / (best_pres + 1)); + + return 0; +} + +static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer, + u32 clk_rate) +{ + int ret; + + mchp_pit64b_reset(timer, ullong_max, mchp_pit64b_mr_cont, 0); + + mchp_pit64b_cs_base = timer->base; + + ret = clocksource_mmio_init(timer->base, mchp_pit64b_name, clk_rate, + 210, 64, mchp_pit64b_clksrc_read); + if (ret) { + pr_debug("clksrc: failed to register pit64b clocksource! "); + + /* stop timer. */ + writel_relaxed(mchp_pit64b_cr_swrst, + timer->base + mchp_pit64b_cr); + + return ret; + } + + sched_clock_register(mchp_pit64b_sched_read_clk, 64, clk_rate); + + return 0; +} + +static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer, + u32 clk_rate, u32 irq) +{ + struct mchp_pit64b_clkevt *ce; + int ret; + + ce = kzalloc(sizeof(*ce), gfp_kernel); + if (!ce) + return -enomem; + + mchp_pit64b_ce_cycles = div_round_closest(clk_rate, hz); + + ce->timer.base = timer->base; + ce->timer.pclk = timer->pclk; + ce->timer.gclk = timer->gclk; + ce->timer.mode = timer->mode; + ce->clkevt.name = mchp_pit64b_name; + ce->clkevt.features = clock_evt_feat_oneshot | clock_evt_feat_periodic; + ce->clkevt.rating = 150; + ce->clkevt.set_state_shutdown = mchp_pit64b_clkevt_shutdown; + ce->clkevt.set_state_periodic = mchp_pit64b_clkevt_set_periodic; + ce->clkevt.set_next_event = mchp_pit64b_clkevt_set_next_event; + ce->clkevt.suspend = mchp_pit64b_clkevt_suspend; + ce->clkevt.resume = mchp_pit64b_clkevt_resume; + ce->clkevt.cpumask = cpumask_of(0); + ce->clkevt.irq = irq; + + ret = request_irq(irq, mchp_pit64b_interrupt, irqf_timer, + "pit64b_tick", ce); + if (ret) { + pr_debug("clkevt: failed to setup pit64b irq "); + kfree(ce); + return ret; + } + + clockevents_config_and_register(&ce->clkevt, clk_rate, 1, ulong_max); + + return 0; +} + +static int __init mchp_pit64b_dt_init_timer(struct device_node *node, + bool clkevt) +{ + u32 freq = clkevt ? mchp_pit64b_def_ce_freq : mchp_pit64b_def_cs_freq; + struct mchp_pit64b_timer timer = { 0 }; + unsigned long clk_rate; + u32 irq = 0; + int ret; + + /* parse dt node. */ + timer.pclk = of_clk_get_by_name(node, "pclk"); + if (is_err(timer.pclk)) + return ptr_err(timer.pclk); + + timer.gclk = of_clk_get_by_name(node, "gclk"); + if (is_err(timer.gclk)) + return ptr_err(timer.gclk); + + timer.base = of_iomap(node, 0); + if (!timer.base) + return -enxio; + + if (clkevt) { + irq = irq_of_parse_and_map(node, 0); + if (!irq) { + ret = -enodev; + goto io_unmap; + } + } + + /* initialize mode (prescaler + sgck bit). to be used at runtime. */ + ret = mchp_pit64b_init_mode(&timer, freq); + if (ret) + goto irq_unmap; + + ret = clk_prepare_enable(timer.pclk); + if (ret) + goto irq_unmap; + + if (timer.mode & mchp_pit64b_mr_sgclk) { + ret = clk_prepare_enable(timer.gclk); + if (ret) + goto pclk_unprepare; + + clk_rate = clk_get_rate(timer.gclk); + } else { + clk_rate = clk_get_rate(timer.pclk); + } + clk_rate = clk_rate / (mchp_pit64b_mode_to_pres(timer.mode) + 1); + + if (clkevt) + ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq); + else + ret = mchp_pit64b_init_clksrc(&timer, clk_rate); + + if (ret) + goto gclk_unprepare; + + return 0; + +gclk_unprepare: + if (timer.mode & mchp_pit64b_mr_sgclk) + clk_disable_unprepare(timer.gclk); +pclk_unprepare: + clk_disable_unprepare(timer.pclk); +irq_unmap: + irq_dispose_mapping(irq); +io_unmap: + iounmap(timer.base); + + return ret; +} + +static int __init mchp_pit64b_dt_init(struct device_node *node) +{ + static int inits; + + switch (inits++) { + case 0: + /* 1st request, register clockevent. */ + return mchp_pit64b_dt_init_timer(node, true); + case 1: + /* 2nd request, register clocksource. */ + return mchp_pit64b_dt_init_timer(node, false); + } + + /* the rest, don't care. */ + return -einval; +} + +timer_of_declare(mchp_pit64b, "microchip,sam9x60-pit64b", mchp_pit64b_dt_init); | Clock | 625022a5f160619ae180d54097ddd65bb3795913 | claudiu beznea | documentation | devicetree | arm, bindings |
clk: zynqmp: add support for get max divider | to achieve best possible rate, maximum limit of divider is required while computation. get maximum supported divisor from firmware. to maintain backward compatibility assign maximum possible value(0xffff) if query for max divisor is not successful. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for get max divider | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['zynqmp'] | ['c', 'h'] | 2 | 37 | 0 | --- diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c + u16 max_div; +/** + * zynqmp_clk_get_max_divisor() - get maximum supported divisor from firmware. + * @clk_id: id of clock + * @type: divider type + * + * return: maximum divisor of a clock if query data is successful + * u16_max in case of query data is not success + */ +u32 zynqmp_clk_get_max_divisor(u32 clk_id, u32 type) +{ + const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops(); + struct zynqmp_pm_query_data qdata = {0}; + u32 ret_payload[payload_arg_cnt]; + int ret; + + qdata.qid = pm_qid_clock_get_max_divisor; + qdata.arg1 = clk_id; + qdata.arg2 = type; + ret = eemi_ops->query_data(qdata, ret_payload); + /* + * to maintain backward compatibility return maximum possible value + * (0xffff) if query for max divisor is not successful. + */ + if (ret) + return u16_max; + + return ret_payload[1]; +} + + /* + * to achieve best possible rate, maximum limit of divider is required + * while computation. + */ + div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type); + diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h + pm_qid_clock_get_max_divisor, | Clock | e942171bbb762977afaa1eb24a312c3bd56386a5 | rajan vaja michal simek michal simek xilinx com | include | linux | firmware, zynqmp |
phy: core: add consumer device link support | in order to enforce suspend/resume ordering, this commit creates link between phy consumers and phy devices. this link avoids to suspend phy before phy consumers. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add consumer device link support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['core'] | ['c', 'h'] | 4 | 53 | 9 | --- diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c - phy_put(phy); + phy_put(dev, phy); - * phy_put() - release the phy - * @phy: the phy returned by phy_get() + * of_phy_put() - release the phy + * @phy: the phy returned by of_phy_get() - * releases a refcount the caller received from phy_get(). + * releases a refcount the caller received from of_phy_get(). -void phy_put(struct phy *phy) +void of_phy_put(struct phy *phy) +export_symbol_gpl(of_phy_put); + +/** + * phy_put() - release the phy + * @dev: device that wants to release this phy + * @phy: the phy returned by phy_get() + * + * releases a refcount the caller received from phy_get(). + */ +void phy_put(struct device *dev, struct phy *phy) +{ + device_link_remove(dev, &phy->dev); + of_phy_put(phy); +} + struct device_link *link; + link = device_link_add(dev, &phy->dev, dl_flag_stateless); + if (!link) { + dev_err(dev, "failed to create device link to %s ", + dev_name(phy->dev.parent)); + return err_ptr(-einval); + } + + struct device_link *link; + return phy; + } + + link = device_link_add(dev, &phy->dev, dl_flag_stateless); + if (!link) { + dev_err(dev, "failed to create device link to %s ", + dev_name(phy->dev.parent)); + return err_ptr(-einval); + struct device_link *link; + link = device_link_add(dev, &phy->dev, dl_flag_stateless); + if (!link) { + dev_err(dev, "failed to create device link to %s ", + dev_name(phy->dev.parent)); + return err_ptr(-einval); + } + diff --git a/drivers/usb/renesas_usbhs/rcar2.c b/drivers/usb/renesas_usbhs/rcar2.c --- a/drivers/usb/renesas_usbhs/rcar2.c +++ b/drivers/usb/renesas_usbhs/rcar2.c - phy_put(priv->phy); + phy_put(&pdev->dev, priv->phy); diff --git a/drivers/usb/renesas_usbhs/rza2.c b/drivers/usb/renesas_usbhs/rza2.c --- a/drivers/usb/renesas_usbhs/rza2.c +++ b/drivers/usb/renesas_usbhs/rza2.c - phy_put(priv->phy); + phy_put(&pdev->dev, priv->phy); diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h -void phy_put(struct phy *phy); +void of_phy_put(struct phy *phy); +void phy_put(struct device *dev, struct phy *phy); -static inline void phy_put(struct phy *phy) +static inline void of_phy_put(struct phy *phy) +{ +} + +static inline void phy_put(struct device *dev, struct phy *phy) | PHY ("physical layer" framework) | 987351e1ea7772cf2f0795e917fb33b2e282e1c1 | alexandre torgue | include | linux | phy, renesas_usbhs |
phy: cadence: sierra: add support for serdes_16g used in j721e soc | serdes_16g in ti's j721e soc uses cadence sierra phy. add support to use cadence sierra driver in j721e soc. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for serdes_16g used in j721e soc | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['cadence', 'sierra'] | ['c'] | 1 | 14 | 0 | --- diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c --- a/drivers/phy/cadence/phy-cadence-sierra.c +++ b/drivers/phy/cadence/phy-cadence-sierra.c +static const struct cdns_sierra_data cdns_ti_map_sierra = { + sierra_macro_id, + 0x0, + 0x1, + array_size(cdns_pcie_regs), + array_size(cdns_usb_regs), + cdns_pcie_regs, + cdns_usb_regs +}; + + { + .compatible = "ti,sierra-phy-t0", + .data = &cdns_ti_map_sierra, + }, | PHY ("physical layer" framework) | 367da978713b4efa1c1689935c5c5d839e778c67 | kishon vijay abraham i | drivers | phy | cadence |
phy: intel-lgm-emmc: add support for emmc phy | add support for emmc phy on intel's lightning mountain soc. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for emmc phy | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['intel-lgm-emmc'] | ['c', 'kconfig', 'makefile'] | 5 | 296 | 0 | --- diff --git a/drivers/phy/kconfig b/drivers/phy/kconfig --- a/drivers/phy/kconfig +++ b/drivers/phy/kconfig +source "drivers/phy/intel/kconfig" diff --git a/drivers/phy/makefile b/drivers/phy/makefile --- a/drivers/phy/makefile +++ b/drivers/phy/makefile + intel/ \ diff --git a/drivers/phy/intel/kconfig b/drivers/phy/intel/kconfig --- /dev/null +++ b/drivers/phy/intel/kconfig +# spdx-license-identifier: gpl-2.0 +# +# phy drivers for intel lightning mountain(lgm) platform +# +config phy_intel_emmc + tristate "intel emmc phy driver" + select generic_phy + help + enable this to support the intel emmc phy diff --git a/drivers/phy/intel/makefile b/drivers/phy/intel/makefile --- /dev/null +++ b/drivers/phy/intel/makefile +# spdx-license-identifier: gpl-2.0 +obj-$(config_phy_intel_emmc) += phy-intel-emmc.o diff --git a/drivers/phy/intel/phy-intel-emmc.c b/drivers/phy/intel/phy-intel-emmc.c --- /dev/null +++ b/drivers/phy/intel/phy-intel-emmc.c +// spdx-license-identifier: gpl-2.0 +/* + * intel emmc phy driver + * copyright (c) 2019 intel, corp. + */ + +#include <linux/bits.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +/* emmc phy register definitions */ +#define emmc_phyctrl0_reg 0xa8 +#define dr_ty_mask genmask(30, 28) +#define dr_ty_shift(x) (((x) << 28) & dr_ty_mask) +#define otapdlyena bit(14) +#define otapdlysel_mask genmask(13, 10) +#define otapdlysel_shift(x) (((x) << 10) & otapdlysel_mask) + +#define emmc_phyctrl1_reg 0xac +#define pdb_mask bit(0) +#define pdb_shift(x) (((x) << 0) & pdb_mask) +#define endll_mask bit(7) +#define endll_shift(x) (((x) << 7) & endll_mask) + +#define emmc_phyctrl2_reg 0xb0 +#define frqsel_25m 0 +#define frqsel_50m 1 +#define frqsel_100m 2 +#define frqsel_150m 3 +#define frqsel_mask genmask(24, 22) +#define frqsel_shift(x) (((x) << 22) & frqsel_mask) + +#define emmc_phystat_reg 0xbc +#define caldone_mask bit(9) +#define dllrdy_mask bit(8) +#define is_caldone(x) ((x) & caldone_mask) +#define is_dllrdy(x) ((x) & dllrdy_mask) + +struct intel_emmc_phy { + struct regmap *syscfg; + struct clk *emmcclk; +}; + +static int intel_emmc_phy_power(struct phy *phy, bool on_off) +{ + struct intel_emmc_phy *priv = phy_get_drvdata(phy); + unsigned int caldone; + unsigned int dllrdy; + unsigned int freqsel; + unsigned long rate; + int ret, quot; + + /* + * keep phyctrl_pdb and phyctrl_endll low to allow + * initialization of calio state m/c dffs + */ + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl1_reg, pdb_mask, + pdb_shift(0)); + if (ret) { + dev_err(&phy->dev, "calio power down bar failed: %d ", ret); + return ret; + } + + /* already finish power_off above */ + if (!on_off) + return 0; + + rate = clk_get_rate(priv->emmcclk); + quot = div_round_closest(rate, 50000000); + if (quot > frqsel_150m) + dev_warn(&phy->dev, "unsupported rate: %lu ", rate); + freqsel = clamp_t(int, quot, frqsel_25m, frqsel_150m); + + /* + * according to the user manual, calpad calibration + * cycle takes more than 2us without the minimal recommended + * value, so we may need a little margin here + */ + udelay(5); + + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl1_reg, pdb_mask, + pdb_shift(1)); + if (ret) { + dev_err(&phy->dev, "calio power down bar failed: %d ", ret); + return ret; + } + + /* + * according to the user manual, it asks driver to wait 5us for + * calpad busy trimming. however it is documented that this value is + * pvt(a.k.a process,voltage and temperature) relevant, so some + * failure cases are found which indicates we should be more tolerant + * to calpad busy trimming. + */ + ret = regmap_read_poll_timeout(priv->syscfg, emmc_phystat_reg, + caldone, is_caldone(caldone), + 0, 50); + if (ret) { + dev_err(&phy->dev, "caldone failed, ret=%d ", ret); + return ret; + } + + /* set the frequency of the dll operation */ + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl2_reg, frqsel_mask, + frqsel_shift(freqsel)); + if (ret) { + dev_err(&phy->dev, "set the frequency of dll failed:%d ", ret); + return ret; + } + + /* turn on the dll */ + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl1_reg, endll_mask, + endll_shift(1)); + if (ret) { + dev_err(&phy->dev, "turn on the dll failed: %d ", ret); + return ret; + } + + /* + * after enabling analog dll circuits docs say that we need 10.2 us if + * our source clock is at 50 mhz and that lock time scales linearly + * with clock speed. if we are powering on the phy and the card clock + * is super slow (like 100 khz) this could take as long as 5.1 ms as + * per the math: 10.2 us * (50000000 hz / 100000 hz) => 5.1 ms + * hopefully we won't be running at 100 khz, but we should still make + * sure we wait long enough. + * + * note: there appear to be corner cases where the dll seems to take + * extra long to lock for reasons that aren't understood. in some + * extreme cases we've seen it take up to over 10ms (!). we'll be + * generous and give it 50ms. + */ + ret = regmap_read_poll_timeout(priv->syscfg, + emmc_phystat_reg, + dllrdy, is_dllrdy(dllrdy), + 0, 50 * usec_per_msec); + if (ret) { + dev_err(&phy->dev, "dllrdy failed. ret=%d ", ret); + return ret; + } + + return 0; +} + +static int intel_emmc_phy_init(struct phy *phy) +{ + struct intel_emmc_phy *priv = phy_get_drvdata(phy); + + /* + * we purposely get the clock here and not in probe to avoid the + * circular dependency problem. we expect: + * - phy driver to probe + * - sdhci driver to start probe + * - sdhci driver to register it's clock + * - sdhci driver to get the phy + * - sdhci driver to init the phy + * + * the clock is optional, so upon any error just return it like + * any other error to user. + * + */ + priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk"); + if (is_err(priv->emmcclk)) { + dev_err(&phy->dev, "error: getting emmcclk "); + return ptr_err(priv->emmcclk); + } + + return 0; +} + +static int intel_emmc_phy_exit(struct phy *phy) +{ + struct intel_emmc_phy *priv = phy_get_drvdata(phy); + + clk_put(priv->emmcclk); + + return 0; +} + +static int intel_emmc_phy_power_on(struct phy *phy) +{ + struct intel_emmc_phy *priv = phy_get_drvdata(phy); + int ret; + + /* drive impedance: 50 ohm */ + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl0_reg, dr_ty_mask, + dr_ty_shift(6)); + if (ret) { + dev_err(&phy->dev, "error set drive-impednce-50ohm: %d ", ret); + return ret; + } + + /* output tap delay: disable */ + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl0_reg, otapdlyena, + 0); + if (ret) { + dev_err(&phy->dev, "error set output tap delay : %d ", ret); + return ret; + } + + /* output tap delay */ + ret = regmap_update_bits(priv->syscfg, emmc_phyctrl0_reg, + otapdlysel_mask, otapdlysel_shift(4)); + if (ret) { + dev_err(&phy->dev, "error: output tap dly select: %d ", ret); + return ret; + } + + /* power up emmc phy analog blocks */ + return intel_emmc_phy_power(phy, true); +} + +static int intel_emmc_phy_power_off(struct phy *phy) +{ + /* power down emmc phy analog blocks */ + return intel_emmc_phy_power(phy, false); +} + +static const struct phy_ops ops = { + .init = intel_emmc_phy_init, + .exit = intel_emmc_phy_exit, + .power_on = intel_emmc_phy_power_on, + .power_off = intel_emmc_phy_power_off, + .owner = this_module, +}; + +static int intel_emmc_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct intel_emmc_phy *priv; + struct phy *generic_phy; + struct phy_provider *phy_provider; + + priv = devm_kzalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + /* get emmc phy (accessed via chiptop) regmap */ + priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon"); + if (is_err(priv->syscfg)) { + dev_err(dev, "failed to find syscon "); + return ptr_err(priv->syscfg); + } + + generic_phy = devm_phy_create(dev, np, &ops); + if (is_err(generic_phy)) { + dev_err(dev, "failed to create phy "); + return ptr_err(generic_phy); + } + + phy_set_drvdata(generic_phy, priv); + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return ptr_err_or_zero(phy_provider); +} + +static const struct of_device_id intel_emmc_phy_dt_ids[] = { + { .compatible = "intel,lgm-emmc-phy" }, + {} +}; + +module_device_table(of, intel_emmc_phy_dt_ids); + +static struct platform_driver intel_emmc_driver = { + .probe = intel_emmc_phy_probe, + .driver = { + .name = "intel-emmc-phy", + .of_match_table = intel_emmc_phy_dt_ids, + }, +}; + +module_platform_driver(intel_emmc_driver); + +module_author("peter harliman liem <peter.harliman.liem@intel.com>"); +module_description("intel emmc phy driver"); | PHY ("physical layer" framework) | 9227942383307f97fa6992416f73af4a23ef972c | ramuthevar vadivel murugan andy shevchenko andriy shevchenko intel com | drivers | phy | intel |
phy: ti: j721e-wiz: add support for wiz module present in ti j721e soc | add support for wiz module present in ti's j721e soc. wiz is a serdes wrapper used to configure some of the input signals to the serdes. it is used with both sierra(16g) and torrent(10g) serdes. this driver configures three clock selects (pll0, pll1, dig), two divider clocks and supports resets for each of the lanes. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for wiz module present in ti j721e soc | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['ti', 'j721e-wiz'] | ['c', 'kconfig', 'makefile'] | 3 | 914 | 0 | --- diff --git a/drivers/phy/ti/kconfig b/drivers/phy/ti/kconfig --- a/drivers/phy/ti/kconfig +++ b/drivers/phy/ti/kconfig +config phy_j721e_wiz + tristate "ti j721e wiz (serdes wrapper) support" + depends on of && arch_k3 || compile_test + depends on common_clk + select generic_phy + select multiplexer + select regmap_mmio + select mux_mmio + help + this option enables support for wiz module present in ti's j721e + soc. wiz is a serdes wrapper used to configure some of the input + signals to the serdes (sierra/torrent). this driver configures + three clock selects (pll0, pll1, dig) and resets for each of the + lanes. + diff --git a/drivers/phy/ti/makefile b/drivers/phy/ti/makefile --- a/drivers/phy/ti/makefile +++ b/drivers/phy/ti/makefile +obj-$(config_phy_j721e_wiz) += phy-j721e-wiz.o diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c --- /dev/null +++ b/drivers/phy/ti/phy-j721e-wiz.c +// spdx-license-identifier: gpl-2.0 +/** + * wrapper driver for serdes used in j721e + * + * copyright (c) 2019 texas instruments incorporated - http://www.ti.com/ + * author: kishon vijay abraham i <kishon@ti.com> + */ + +#include <dt-bindings/phy/phy.h> +#include <linux/clk.h> +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/mux/consumer.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#define wiz_serdes_ctrl 0x404 +#define wiz_serdes_top_ctrl 0x408 +#define wiz_serdes_rst 0x40c +#define wiz_lanectl(n) (0x480 + (0x40 * (n))) + +#define wiz_max_lanes 4 +#define wiz_mux_num_clocks 3 +#define wiz_div_num_clocks_16g 2 +#define wiz_div_num_clocks_10g 1 + +enum wiz_lane_standard_mode { + lane_mode_gen1, + lane_mode_gen2, + lane_mode_gen3, + lane_mode_gen4, +}; + +enum wiz_refclk_mux_sel { + pll0_refclk, + pll1_refclk, + refclk_dig, +}; + +enum wiz_refclk_div_sel { + cmn_refclk_dig_div, + cmn_refclk1_dig_div, +}; + +static const struct reg_field por_en = reg_field(wiz_serdes_ctrl, 31, 31); +static const struct reg_field phy_reset_n = reg_field(wiz_serdes_rst, 31, 31); +static const struct reg_field pll1_refclk_mux_sel = + reg_field(wiz_serdes_rst, 29, 29); +static const struct reg_field pll0_refclk_mux_sel = + reg_field(wiz_serdes_rst, 28, 28); +static const struct reg_field refclk_dig_sel_16g = + reg_field(wiz_serdes_rst, 24, 25); +static const struct reg_field refclk_dig_sel_10g = + reg_field(wiz_serdes_rst, 24, 24); +static const struct reg_field pma_cmn_refclk_int_mode = + reg_field(wiz_serdes_top_ctrl, 28, 29); +static const struct reg_field pma_cmn_refclk_mode = + reg_field(wiz_serdes_top_ctrl, 30, 31); +static const struct reg_field pma_cmn_refclk_dig_div = + reg_field(wiz_serdes_top_ctrl, 26, 27); +static const struct reg_field pma_cmn_refclk1_dig_div = + reg_field(wiz_serdes_top_ctrl, 24, 25); + +static const struct reg_field p_enable[wiz_max_lanes] = { + reg_field(wiz_lanectl(0), 30, 31), + reg_field(wiz_lanectl(1), 30, 31), + reg_field(wiz_lanectl(2), 30, 31), + reg_field(wiz_lanectl(3), 30, 31), +}; + +static const struct reg_field p_align[wiz_max_lanes] = { + reg_field(wiz_lanectl(0), 29, 29), + reg_field(wiz_lanectl(1), 29, 29), + reg_field(wiz_lanectl(2), 29, 29), + reg_field(wiz_lanectl(3), 29, 29), +}; + +static const struct reg_field p_raw_auto_start[wiz_max_lanes] = { + reg_field(wiz_lanectl(0), 28, 28), + reg_field(wiz_lanectl(1), 28, 28), + reg_field(wiz_lanectl(2), 28, 28), + reg_field(wiz_lanectl(3), 28, 28), +}; + +static const struct reg_field p_standard_mode[wiz_max_lanes] = { + reg_field(wiz_lanectl(0), 24, 25), + reg_field(wiz_lanectl(1), 24, 25), + reg_field(wiz_lanectl(2), 24, 25), + reg_field(wiz_lanectl(3), 24, 25), +}; + +struct wiz_clk_mux { + struct clk_hw hw; + struct regmap_field *field; + u32 *table; + struct clk_init_data clk_data; +}; + +#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw) + +struct wiz_clk_divider { + struct clk_hw hw; + struct regmap_field *field; + struct clk_div_table *table; + struct clk_init_data clk_data; +}; + +#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw) + +struct wiz_clk_mux_sel { + struct regmap_field *field; + u32 table[4]; + const char *node_name; +}; + +struct wiz_clk_div_sel { + struct regmap_field *field; + struct clk_div_table *table; + const char *node_name; +}; + +static struct wiz_clk_mux_sel clk_mux_sel_16g[] = { + { + /* + * mux value to be configured for each of the input clocks + * in the order populated in device tree + */ + .table = { 1, 0 }, + .node_name = "pll0-refclk", + }, + { + .table = { 1, 0 }, + .node_name = "pll1-refclk", + }, + { + .table = { 1, 3, 0, 2 }, + .node_name = "refclk-dig", + }, +}; + +static struct wiz_clk_mux_sel clk_mux_sel_10g[] = { + { + /* + * mux value to be configured for each of the input clocks + * in the order populated in device tree + */ + .table = { 1, 0 }, + .node_name = "pll0-refclk", + }, + { + .table = { 1, 0 }, + .node_name = "pll1-refclk", + }, + { + .table = { 1, 0 }, + .node_name = "refclk-dig", + }, +}; + +static struct clk_div_table clk_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 4, }, + { .val = 3, .div = 8, }, +}; + +static struct wiz_clk_div_sel clk_div_sel[] = { + { + .table = clk_div_table, + .node_name = "cmn-refclk-dig-div", + }, + { + .table = clk_div_table, + .node_name = "cmn-refclk1-dig-div", + }, +}; + +enum wiz_type { + j721e_wiz_16g, + j721e_wiz_10g, +}; + +struct wiz { + struct regmap *regmap; + enum wiz_type type; + struct wiz_clk_mux_sel *clk_mux_sel; + struct wiz_clk_div_sel *clk_div_sel; + unsigned int clk_div_sel_num; + struct regmap_field *por_en; + struct regmap_field *phy_reset_n; + struct regmap_field *p_enable[wiz_max_lanes]; + struct regmap_field *p_align[wiz_max_lanes]; + struct regmap_field *p_raw_auto_start[wiz_max_lanes]; + struct regmap_field *p_standard_mode[wiz_max_lanes]; + struct regmap_field *pma_cmn_refclk_int_mode; + struct regmap_field *pma_cmn_refclk_mode; + struct regmap_field *pma_cmn_refclk_dig_div; + struct regmap_field *pma_cmn_refclk1_dig_div; + + struct device *dev; + u32 num_lanes; + struct platform_device *serdes_pdev; + struct reset_controller_dev wiz_phy_reset_dev; +}; + +static int wiz_reset(struct wiz *wiz) +{ + int ret; + + ret = regmap_field_write(wiz->por_en, 0x1); + if (ret) + return ret; + + mdelay(1); + + ret = regmap_field_write(wiz->por_en, 0x0); + if (ret) + return ret; + + return 0; +} + +static int wiz_mode_select(struct wiz *wiz) +{ + u32 num_lanes = wiz->num_lanes; + int ret; + int i; + + for (i = 0; i < num_lanes; i++) { + ret = regmap_field_write(wiz->p_standard_mode[i], + lane_mode_gen4); + if (ret) + return ret; + } + + return 0; +} + +static int wiz_init_raw_interface(struct wiz *wiz, bool enable) +{ + u32 num_lanes = wiz->num_lanes; + int i; + int ret; + + for (i = 0; i < num_lanes; i++) { + ret = regmap_field_write(wiz->p_align[i], enable); + if (ret) + return ret; + + ret = regmap_field_write(wiz->p_raw_auto_start[i], enable); + if (ret) + return ret; + } + + return 0; +} + +static int wiz_init(struct wiz *wiz) +{ + struct device *dev = wiz->dev; + int ret; + + ret = wiz_reset(wiz); + if (ret) { + dev_err(dev, "wiz reset failed "); + return ret; + } + + ret = wiz_mode_select(wiz); + if (ret) { + dev_err(dev, "wiz mode select failed "); + return ret; + } + + ret = wiz_init_raw_interface(wiz, true); + if (ret) { + dev_err(dev, "wiz interface initialization failed "); + return ret; + } + + return 0; +} + +static int wiz_regfield_init(struct wiz *wiz) +{ + struct wiz_clk_mux_sel *clk_mux_sel; + struct wiz_clk_div_sel *clk_div_sel; + struct regmap *regmap = wiz->regmap; + int num_lanes = wiz->num_lanes; + struct device *dev = wiz->dev; + int i; + + wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en); + if (is_err(wiz->por_en)) { + dev_err(dev, "por_en reg field init failed "); + return ptr_err(wiz->por_en); + } + + wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap, + phy_reset_n); + if (is_err(wiz->phy_reset_n)) { + dev_err(dev, "phy_reset_n reg field init failed "); + return ptr_err(wiz->phy_reset_n); + } + + wiz->pma_cmn_refclk_int_mode = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode); + if (is_err(wiz->pma_cmn_refclk_int_mode)) { + dev_err(dev, "pma_cmn_refclk_int_mode reg field init failed "); + return ptr_err(wiz->pma_cmn_refclk_int_mode); + } + + wiz->pma_cmn_refclk_mode = + devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode); + if (is_err(wiz->pma_cmn_refclk_mode)) { + dev_err(dev, "pma_cmn_refclk_mode reg field init failed "); + return ptr_err(wiz->pma_cmn_refclk_mode); + } + + clk_div_sel = &wiz->clk_div_sel[cmn_refclk_dig_div]; + clk_div_sel->field = devm_regmap_field_alloc(dev, regmap, + pma_cmn_refclk_dig_div); + if (is_err(clk_div_sel->field)) { + dev_err(dev, "pma_cmn_refclk_dig_div reg field init failed "); + return ptr_err(clk_div_sel->field); + } + + if (wiz->type == j721e_wiz_16g) { + clk_div_sel = &wiz->clk_div_sel[cmn_refclk1_dig_div]; + clk_div_sel->field = + devm_regmap_field_alloc(dev, regmap, + pma_cmn_refclk1_dig_div); + if (is_err(clk_div_sel->field)) { + dev_err(dev, "pma_cmn_refclk1_dig_div reg field init failed "); + return ptr_err(clk_div_sel->field); + } + } + + clk_mux_sel = &wiz->clk_mux_sel[pll0_refclk]; + clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, + pll0_refclk_mux_sel); + if (is_err(clk_mux_sel->field)) { + dev_err(dev, "pll0_refclk_sel reg field init failed "); + return ptr_err(clk_mux_sel->field); + } + + clk_mux_sel = &wiz->clk_mux_sel[pll1_refclk]; + clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap, + pll1_refclk_mux_sel); + if (is_err(clk_mux_sel->field)) { + dev_err(dev, "pll1_refclk_sel reg field init failed "); + return ptr_err(clk_mux_sel->field); + } + + clk_mux_sel = &wiz->clk_mux_sel[refclk_dig]; + if (wiz->type == j721e_wiz_10g) + clk_mux_sel->field = + devm_regmap_field_alloc(dev, regmap, + refclk_dig_sel_10g); + else + clk_mux_sel->field = + devm_regmap_field_alloc(dev, regmap, + refclk_dig_sel_16g); + + if (is_err(clk_mux_sel->field)) { + dev_err(dev, "refclk_dig_sel reg field init failed "); + return ptr_err(clk_mux_sel->field); + } + + for (i = 0; i < num_lanes; i++) { + wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap, + p_enable[i]); + if (is_err(wiz->p_enable[i])) { + dev_err(dev, "p%d_enable reg field init failed ", i); + return ptr_err(wiz->p_enable[i]); + } + + wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap, + p_align[i]); + if (is_err(wiz->p_align[i])) { + dev_err(dev, "p%d_align reg field init failed ", i); + return ptr_err(wiz->p_align[i]); + } + + wiz->p_raw_auto_start[i] = + devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]); + if (is_err(wiz->p_raw_auto_start[i])) { + dev_err(dev, "p%d_raw_auto_start reg field init fail ", + i); + return ptr_err(wiz->p_raw_auto_start[i]); + } + + wiz->p_standard_mode[i] = + devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]); + if (is_err(wiz->p_standard_mode[i])) { + dev_err(dev, "p%d_standard_mode reg field init fail ", + i); + return ptr_err(wiz->p_standard_mode[i]); + } + } + + return 0; +} + +static u8 wiz_clk_mux_get_parent(struct clk_hw *hw) +{ + struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); + struct regmap_field *field = mux->field; + unsigned int val; + + regmap_field_read(field, &val); + return clk_mux_val_to_index(hw, mux->table, 0, val); +} + +static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct wiz_clk_mux *mux = to_wiz_clk_mux(hw); + struct regmap_field *field = mux->field; + int val; + + val = mux->table[index]; + return regmap_field_write(field, val); +} + +static const struct clk_ops wiz_clk_mux_ops = { + .set_parent = wiz_clk_mux_set_parent, + .get_parent = wiz_clk_mux_get_parent, +}; + +static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node, + struct regmap_field *field, u32 *table) +{ + struct device *dev = wiz->dev; + struct clk_init_data *init; + const char **parent_names; + unsigned int num_parents; + struct wiz_clk_mux *mux; + char clk_name[100]; + struct clk *clk; + int ret; + + mux = devm_kzalloc(dev, sizeof(*mux), gfp_kernel); + if (!mux) + return -enomem; + + num_parents = of_clk_get_parent_count(node); + if (num_parents < 2) { + dev_err(dev, "serdes clock must have parents "); + return -einval; + } + + parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), + gfp_kernel); + if (!parent_names) + return -enomem; + + of_clk_parent_fill(node, parent_names, num_parents); + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + init = &mux->clk_data; + + init->ops = &wiz_clk_mux_ops; + init->flags = clk_set_rate_no_reparent; + init->parent_names = parent_names; + init->num_parents = num_parents; + init->name = clk_name; + + mux->field = field; + mux->table = table; + mux->hw.init = init; + + clk = devm_clk_register(dev, &mux->hw); + if (is_err(clk)) + return ptr_err(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "failed to add clock provider: %s ", clk_name); + + return ret; +} + +static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct wiz_clk_divider *div = to_wiz_clk_div(hw); + struct regmap_field *field = div->field; + int val; + + regmap_field_read(field, &val); + + return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2); +} + +static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct wiz_clk_divider *div = to_wiz_clk_div(hw); + + return divider_round_rate(hw, rate, prate, div->table, 2, 0x0); +} + +static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct wiz_clk_divider *div = to_wiz_clk_div(hw); + struct regmap_field *field = div->field; + int val; + + val = divider_get_val(rate, parent_rate, div->table, 2, 0x0); + if (val < 0) + return val; + + return regmap_field_write(field, val); +} + +static const struct clk_ops wiz_clk_div_ops = { + .recalc_rate = wiz_clk_div_recalc_rate, + .round_rate = wiz_clk_div_round_rate, + .set_rate = wiz_clk_div_set_rate, +}; + +static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node, + struct regmap_field *field, + struct clk_div_table *table) +{ + struct device *dev = wiz->dev; + struct wiz_clk_divider *div; + struct clk_init_data *init; + const char **parent_names; + char clk_name[100]; + struct clk *clk; + int ret; + + div = devm_kzalloc(dev, sizeof(*div), gfp_kernel); + if (!div) + return -enomem; + + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), + node->name); + + parent_names = devm_kzalloc(dev, sizeof(char *), gfp_kernel); + if (!parent_names) + return -enomem; + + of_clk_parent_fill(node, parent_names, 1); + + init = &div->clk_data; + + init->ops = &wiz_clk_div_ops; + init->flags = 0; + init->parent_names = parent_names; + init->num_parents = 1; + init->name = clk_name; + + div->field = field; + div->table = table; + div->hw.init = init; + + clk = devm_clk_register(dev, &div->hw); + if (is_err(clk)) + return ptr_err(clk); + + ret = of_clk_add_provider(node, of_clk_src_simple_get, clk); + if (ret) + dev_err(dev, "failed to add clock provider: %s ", clk_name); + + return ret; +} + +static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node) +{ + struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct device_node *clk_node; + int i; + + for (i = 0; i < wiz_mux_num_clocks; i++) { + clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name); + of_clk_del_provider(clk_node); + of_node_put(clk_node); + } +} + +static int wiz_clock_init(struct wiz *wiz, struct device_node *node) +{ + struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel; + struct device *dev = wiz->dev; + struct device_node *clk_node; + const char *node_name; + unsigned long rate; + struct clk *clk; + int ret; + int i; + + clk = devm_clk_get(dev, "core_ref_clk"); + if (is_err(clk)) { + dev_err(dev, "core_ref_clk clock not found "); + ret = ptr_err(clk); + return ret; + } + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1); + else + regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3); + + clk = devm_clk_get(dev, "ext_ref_clk"); + if (is_err(clk)) { + dev_err(dev, "ext_ref_clk clock not found "); + ret = ptr_err(clk); + return ret; + } + + rate = clk_get_rate(clk); + if (rate >= 100000000) + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0); + else + regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2); + + for (i = 0; i < wiz_mux_num_clocks; i++) { + node_name = clk_mux_sel[i].node_name; + clk_node = of_get_child_by_name(node, node_name); + if (!clk_node) { + dev_err(dev, "unable to get %s node ", node_name); + ret = -einval; + goto err; + } + + ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field, + clk_mux_sel[i].table); + if (ret) { + dev_err(dev, "failed to register %s clock ", + node_name); + of_node_put(clk_node); + goto err; + } + + of_node_put(clk_node); + } + + for (i = 0; i < wiz->clk_div_sel_num; i++) { + node_name = clk_div_sel[i].node_name; + clk_node = of_get_child_by_name(node, node_name); + if (!clk_node) { + dev_err(dev, "unable to get %s node ", node_name); + ret = -einval; + goto err; + } + + ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field, + clk_div_sel[i].table); + if (ret) { + dev_err(dev, "failed to register %s clock ", + node_name); + of_node_put(clk_node); + goto err; + } + + of_node_put(clk_node); + } + + return 0; +err: + wiz_clock_cleanup(wiz, node); + + return ret; +} + +static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct device *dev = rcdev->dev; + struct wiz *wiz = dev_get_drvdata(dev); + int ret = 0; + + if (id == 0) { + ret = regmap_field_write(wiz->phy_reset_n, false); + return ret; + } + + ret = regmap_field_write(wiz->p_enable[id - 1], false); + return ret; +} + +static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct device *dev = rcdev->dev; + struct wiz *wiz = dev_get_drvdata(dev); + int ret; + + if (id == 0) { + ret = regmap_field_write(wiz->phy_reset_n, true); + return ret; + } + + ret = regmap_field_write(wiz->p_enable[id - 1], true); + return ret; +} + +static const struct reset_control_ops wiz_phy_reset_ops = { + .assert = wiz_phy_reset_assert, + .deassert = wiz_phy_reset_deassert, +}; + +static struct regmap_config wiz_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, +}; + +static const struct of_device_id wiz_id_table[] = { + { + .compatible = "ti,j721e-wiz-16g", .data = (void *)j721e_wiz_16g + }, + { + .compatible = "ti,j721e-wiz-10g", .data = (void *)j721e_wiz_10g + }, + {} +}; +module_device_table(of, wiz_id_table); + +static int wiz_probe(struct platform_device *pdev) +{ + struct reset_controller_dev *phy_reset_dev; + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct platform_device *serdes_pdev; + struct device_node *child_node; + struct regmap *regmap; + struct resource res; + void __iomem *base; + struct wiz *wiz; + u32 num_lanes; + int ret; + + wiz = devm_kzalloc(dev, sizeof(*wiz), gfp_kernel); + if (!wiz) + return -enomem; + + wiz->type = (enum wiz_type)of_device_get_match_data(dev); + + child_node = of_get_child_by_name(node, "serdes"); + if (!child_node) { + dev_err(dev, "failed to get serdes child dt node "); + return -enodev; + } + + ret = of_address_to_resource(child_node, 0, &res); + if (ret) { + dev_err(dev, "failed to get memory resource "); + goto err_addr_to_resource; + } + + base = devm_ioremap(dev, res.start, resource_size(&res)); + if (is_err(base)) + goto err_addr_to_resource; + + regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config); + if (is_err(regmap)) { + dev_err(dev, "failed to initialize regmap "); + ret = ptr_err(regmap); + goto err_addr_to_resource; + } + + ret = of_property_read_u32(node, "num-lanes", &num_lanes); + if (ret) { + dev_err(dev, "failed to read num-lanes property "); + goto err_addr_to_resource; + } + + if (num_lanes > wiz_max_lanes) { + dev_err(dev, "cannot support %d lanes ", num_lanes); + goto err_addr_to_resource; + } + + wiz->dev = dev; + wiz->regmap = regmap; + wiz->num_lanes = num_lanes; + if (wiz->type == j721e_wiz_10g) + wiz->clk_mux_sel = clk_mux_sel_10g; + else + wiz->clk_mux_sel = clk_mux_sel_16g; + + wiz->clk_div_sel = clk_div_sel; + + if (wiz->type == j721e_wiz_10g) + wiz->clk_div_sel_num = wiz_div_num_clocks_10g; + else + wiz->clk_div_sel_num = wiz_div_num_clocks_16g; + + platform_set_drvdata(pdev, wiz); + + ret = wiz_regfield_init(wiz); + if (ret) { + dev_err(dev, "failed to initialize regfields "); + goto err_addr_to_resource; + } + + phy_reset_dev = &wiz->wiz_phy_reset_dev; + phy_reset_dev->dev = dev; + phy_reset_dev->ops = &wiz_phy_reset_ops, + phy_reset_dev->owner = this_module, + phy_reset_dev->of_node = node; + /* reset for each of the lane and one for the entire serdes */ + phy_reset_dev->nr_resets = num_lanes + 1; + + ret = devm_reset_controller_register(dev, phy_reset_dev); + if (ret < 0) { + dev_warn(dev, "failed to register reset controller "); + goto err_addr_to_resource; + } + + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed "); + goto err_get_sync; + } + + ret = wiz_clock_init(wiz, node); + if (ret < 0) { + dev_warn(dev, "failed to initialize clocks "); + goto err_get_sync; + } + + serdes_pdev = of_platform_device_create(child_node, null, dev); + if (!serdes_pdev) { + dev_warn(dev, "unable to create serdes platform device "); + goto err_pdev_create; + } + wiz->serdes_pdev = serdes_pdev; + + ret = wiz_init(wiz); + if (ret) { + dev_err(dev, "wiz initialization failed "); + goto err_wiz_init; + } + + of_node_put(child_node); + return 0; + +err_wiz_init: + of_platform_device_destroy(&serdes_pdev->dev, null); + +err_pdev_create: + wiz_clock_cleanup(wiz, node); + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + +err_addr_to_resource: + of_node_put(child_node); + + return ret; +} + +static int wiz_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct platform_device *serdes_pdev; + struct wiz *wiz; + + wiz = dev_get_drvdata(dev); + serdes_pdev = wiz->serdes_pdev; + + of_platform_device_destroy(&serdes_pdev->dev, null); + wiz_clock_cleanup(wiz, node); + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return 0; +} + +static struct platform_driver wiz_driver = { + .probe = wiz_probe, + .remove = wiz_remove, + .driver = { + .name = "wiz", + .of_match_table = wiz_id_table, + }, +}; +module_platform_driver(wiz_driver); + +module_author("texas instruments inc."); +module_description("ti j721e wiz driver"); +module_license("gpl v2"); | PHY ("physical layer" framework) | 091876cc355d6739e393efa4b3d07f451a6a035c | kishon vijay abraham i | drivers | phy | ti |
phy: usb: add support for new synopsys usb controller on the 7211b0 | the 7211b0 has added the stb xhci synopsys controller and it will be used instead of the rpi based dwc usb controller. the new synopsys xhci controller core is the same one that is used on the 7216, but because of the way the stb usb phy is used on both the a0 and b0, some of the phy control is different. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for new synopsys usb controller on the 7211b0 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['usb'] | ['c', 'h'] | 4 | 295 | 78 | --- diff --git a/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c b/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c --- a/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c +++ b/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c +#define phy_lock_timeout_ms 200 + +/* register definitions for syscon piarbctl registers */ +#define piarbctl_cam 0x00 +#define piarbctl_splitter 0x04 +#define piarbctl_misc 0x08 +#define piarbctl_misc_secure_mask 0x80000000 +#define piarbctl_misc_usb_select_mask 0x40000000 +#define piarbctl_misc_usb_4g_sdram_mask 0x20000000 +#define piarbctl_misc_usb_priority_mask 0x000f0000 +#define piarbctl_misc_usb_mem_page_mask 0x0000f000 +#define piarbctl_misc_cam1_mem_page_mask 0x00000f00 +#define piarbctl_misc_cam0_mem_page_mask 0x000000f0 +#define piarbctl_misc_sata_priority_mask 0x0000000f +#define piarbctl_usb_m_asb_ctrl 0x10 + +#define piarbctl_misc_usb_only_mask \ + (piarbctl_misc_usb_select_mask | \ + piarbctl_misc_usb_4g_sdram_mask | \ + piarbctl_misc_usb_priority_mask | \ + piarbctl_misc_usb_mem_page_mask) + +#define usb_ctrl_setup_tca_drv_sel_mask 0x01000000 +/* register definitions for the usb_phy block in 7211b0 */ +#define usb_phy_pll_ldo_ctl 0x08 +#define usb_phy_pll_ldo_ctl_afe_corerdy_mask 0x00000004 +#define usb_phy_utmi_ctl_1 0x04 +#define usb_phy_utmi_ctl_1_phy_mode_mask 0x0000000c +#define usb_phy_utmi_ctl_1_phy_mode_shift 2 +#define usb_phy_status 0x20 +#define usb_phy_status_pll_lock_mask 0x00000001 + +/* register definitions for the mdio registers in the dwc2 block of + * the 7211b0. + * note: the phy's mdio registers are only accessible through the + * legacy designware usb controller even though it's not being used. + */ +#define usb_gmdiocsr 0 +#define usb_gmdiogen 4 + + +static void usb_mdio_write_7211b0(struct brcm_usb_init_params *params, + uint8_t addr, uint16_t data) +{ + void __iomem *usb_mdio = params->regs[brcm_regs_usb_mdio]; + + addr &= 0x1f; /* 5-bit address */ + brcm_usb_writel(0xffffffff, usb_mdio + usb_gmdiogen); + while (brcm_usb_readl(usb_mdio + usb_gmdiocsr) & (1<<31)) + ; + brcm_usb_writel(0x59020000 | (addr << 18) | data, + usb_mdio + usb_gmdiogen); + while (brcm_usb_readl(usb_mdio + usb_gmdiocsr) & (1<<31)) + ; + brcm_usb_writel(0x00000000, usb_mdio + usb_gmdiogen); + while (brcm_usb_readl(usb_mdio + usb_gmdiocsr) & (1<<31)) + ; +} + +static uint16_t __maybe_unused usb_mdio_read_7211b0( + struct brcm_usb_init_params *params, uint8_t addr) +{ + void __iomem *usb_mdio = params->regs[brcm_regs_usb_mdio]; + + addr &= 0x1f; /* 5-bit address */ + brcm_usb_writel(0xffffffff, usb_mdio + usb_gmdiogen); + while (brcm_usb_readl(usb_mdio + usb_gmdiocsr) & (1<<31)) + ; + brcm_usb_writel(0x69020000 | (addr << 18), usb_mdio + usb_gmdiogen); + while (brcm_usb_readl(usb_mdio + usb_gmdiocsr) & (1<<31)) + ; + brcm_usb_writel(0x00000000, usb_mdio + usb_gmdiogen); + while (brcm_usb_readl(usb_mdio + usb_gmdiocsr) & (1<<31)) + ; + return brcm_usb_readl(usb_mdio + usb_gmdiocsr) & 0xffff; +} + +static void usb2_eye_fix_7211b0(struct brcm_usb_init_params *params) +{ + /* select bank */ + usb_mdio_write_7211b0(params, 0x1f, 0x80a0); + + /* set the eye */ + usb_mdio_write_7211b0(params, 0x0a, 0xc6a0); +} - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; +static void syscon_piarbctl_init(struct regmap *rmap) +{ + /* switch from legacy usb otg controller to new stb usb controller */ + regmap_update_bits(rmap, piarbctl_misc, piarbctl_misc_usb_only_mask, + piarbctl_misc_usb_select_mask | + piarbctl_misc_usb_4g_sdram_mask); +} + - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; +static void usb_init_common_7211b0(struct brcm_usb_init_params *params) +{ + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; + void __iomem *usb_phy = params->regs[brcm_regs_usb_phy]; + int timeout_ms = phy_lock_timeout_ms; + u32 reg; + + if (params->syscon_piarbctl) + syscon_piarbctl_init(params->syscon_piarbctl); + + /* init the phy */ + reg = brcm_usb_readl(usb_phy + usb_phy_pll_ldo_ctl); + reg |= usb_phy_pll_ldo_ctl_afe_corerdy_mask; + brcm_usb_writel(reg, usb_phy + usb_phy_pll_ldo_ctl); + + /* wait for lock */ + while (timeout_ms-- > 0) { + reg = brcm_usb_readl(usb_phy + usb_phy_status); + if (reg & usb_phy_status_pll_lock_mask) + break; + usleep_range(1000, 2000); + } + + /* set the phy_mode */ + reg = brcm_usb_readl(usb_phy + usb_phy_utmi_ctl_1); + reg &= ~usb_phy_utmi_ctl_1_phy_mode_mask; + reg |= params->mode << usb_phy_utmi_ctl_1_phy_mode_shift; + brcm_usb_writel(reg, usb_phy + usb_phy_utmi_ctl_1); + + /* fix the incorrect default */ + reg = brcm_usb_readl(ctrl + usb_ctrl_setup); + reg &= ~usb_ctrl_setup_tca_drv_sel_mask; + brcm_usb_writel(reg, ctrl + usb_ctrl_setup); + + usb_init_common(params); + + usb2_eye_fix_7211b0(params); +} + - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; +static const struct brcm_usb_init_ops bcm7211b0_ops = { + .init_ipp = usb_init_ipp, + .init_common = usb_init_common_7211b0, + .init_xhci = usb_init_xhci, + .uninit_common = usb_uninit_common, + .uninit_xhci = usb_uninit_xhci, + .get_dual_select = usb_get_dual_select, + .set_dual_select = usb_set_dual_select, +}; + + +void brcm_usb_dvr_init_7211b0(struct brcm_usb_init_params *params) +{ + + pr_debug("%s ", __func__); + + params->family_name = "7211"; + params->ops = &bcm7211b0_ops; +} diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.c b/drivers/phy/broadcom/phy-brcm-usb-init.c --- a/drivers/phy/broadcom/phy-brcm-usb-init.c +++ b/drivers/phy/broadcom/phy-brcm-usb-init.c - brcm_usb_ctrl_unset(params->ctrl_regs + reg_offset, mask); + brcm_usb_ctrl_unset(params->regs[brcm_regs_ctrl] + reg_offset, mask); - brcm_usb_ctrl_set(params->ctrl_regs + reg_offset, mask); + brcm_usb_ctrl_set(params->regs[brcm_regs_ctrl] + reg_offset, mask); - void __iomem *ctrl_base = params->ctrl_regs; + void __iomem *ctrl_base = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl_base = params->ctrl_regs; + void __iomem *ctrl_base = params->regs[brcm_regs_ctrl]; - void __iomem *xhci_ec_base = params->xhci_ec_regs; + void __iomem *xhci_ec_base = params->regs[brcm_regs_xhci_ec]; - usb_ctrl_unset(params->ctrl_regs, usb30_ctl1, phy3_resetb); - usb_ctrl_set(params->ctrl_regs, usb30_ctl1, phy3_resetb); + usb_ctrl_unset(params->regs[brcm_regs_ctrl], usb30_ctl1, phy3_resetb); + usb_ctrl_set(params->regs[brcm_regs_ctrl], usb30_ctl1, phy3_resetb); - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - usb_ctrl_set(params->ctrl_regs, usb30_pctl, phy3_iddq_override); + usb_ctrl_set(params->regs[brcm_regs_ctrl], usb30_pctl, + phy3_iddq_override); - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - void __iomem *ctrl = params->ctrl_regs; + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.h b/drivers/phy/broadcom/phy-brcm-usb-init.h --- a/drivers/phy/broadcom/phy-brcm-usb-init.h +++ b/drivers/phy/broadcom/phy-brcm-usb-init.h +#include <linux/regmap.h> + -struct brcm_usb_init_params; +enum brcmusb_reg_sel { + brcm_regs_ctrl = 0, + brcm_regs_xhci_ec, + brcm_regs_xhci_gbl, + brcm_regs_usb_phy, + brcm_regs_usb_mdio, + brcm_regs_max +}; - void __iomem *ctrl_regs; - void __iomem *xhci_ec_regs; - void __iomem *xhci_gbl_regs; + void __iomem *regs[brcm_regs_max]; + struct regmap *syscon_piarbctl; +void brcm_usb_dvr_init_7211b0(struct brcm_usb_init_params *params); diff --git a/drivers/phy/broadcom/phy-brcm-usb.c b/drivers/phy/broadcom/phy-brcm-usb.c --- a/drivers/phy/broadcom/phy-brcm-usb.c +++ b/drivers/phy/broadcom/phy-brcm-usb.c +#include <linux/mfd/syscon.h> +struct match_chip_info { + void *init_func; + u8 required_regs[brcm_regs_max + 1]; +}; + +static s8 *node_reg_names[brcm_regs_max] = { + "crtl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio" +}; + +static struct match_chip_info chip_info_7216 = { + .init_func = &brcm_usb_dvr_init_7216, + .required_regs = { + brcm_regs_ctrl, + brcm_regs_xhci_ec, + brcm_regs_xhci_gbl, + -1, + }, +}; + +static struct match_chip_info chip_info_7211b0 = { + .init_func = &brcm_usb_dvr_init_7211b0, + .required_regs = { + brcm_regs_ctrl, + brcm_regs_xhci_ec, + brcm_regs_xhci_gbl, + brcm_regs_usb_phy, + brcm_regs_usb_mdio, + -1, + }, +}; + +static struct match_chip_info chip_info_7445 = { + .init_func = &brcm_usb_dvr_init_7445, + .required_regs = { + brcm_regs_ctrl, + brcm_regs_xhci_ec, + -1, + }, +}; + - .data = &brcm_usb_dvr_init_7216, + .data = &chip_info_7216, + }, + { + .compatible = "brcm,bcm7211-usb-phy", + .data = &chip_info_7211b0, + }, + { + .compatible = "brcm,brcmstb-usb-phy", + .data = &chip_info_7445, - { .compatible = "brcm,brcmstb-usb-phy" }, +static int brcm_usb_get_regs(struct platform_device *pdev, + enum brcmusb_reg_sel regs, + struct brcm_usb_init_params *ini) +{ + struct resource *res; + + /* older dt nodes have ctrl and optional xhci_ec by index only */ + res = platform_get_resource_byname(pdev, ioresource_mem, + node_reg_names[regs]); + if (res == null) { + if (regs == brcm_regs_ctrl) { + res = platform_get_resource(pdev, ioresource_mem, 0); + } else if (regs == brcm_regs_xhci_ec) { + res = platform_get_resource(pdev, ioresource_mem, 1); + /* xhci_ec registers are optional */ + if (res == null) + return 0; + } + if (res == null) { + dev_err(&pdev->dev, "can't get %s base address ", + node_reg_names[regs]); + return 1; + } + } + ini->regs[regs] = devm_ioremap_resource(&pdev->dev, res); + if (is_err(ini->regs[regs])) { + dev_err(&pdev->dev, "can't map %s register space ", + node_reg_names[regs]); + return 1; + } + return 0; +} + - struct resource *res_ctrl; - struct resource *res_xhciec = null; - struct resource *res_xhcigbl = null; + void (*dvr_init)(struct brcm_usb_init_params *params); + const struct match_chip_info *info; + struct regmap *rmap; + int x; - if (match && match->data) { - void (*dvr_init)(struct brcm_usb_init_params *params); - - dvr_init = match->data; - (*dvr_init)(&priv->ini); - } else { - brcm_usb_dvr_init_7445(&priv->ini); - } + info = match->data; + dvr_init = info->init_func; + (*dvr_init)(&priv->ini); - /* newer dt node has reg-names. xhci_ec and xhci_gbl are optional. */ - res_ctrl = platform_get_resource_byname(pdev, ioresource_mem, "ctrl"); - if (res_ctrl != null) { - res_xhciec = platform_get_resource_byname(pdev, - ioresource_mem, - "xhci_ec"); - res_xhcigbl = platform_get_resource_byname(pdev, - ioresource_mem, - "xhci_gbl"); - } else { - /* older dt node without reg-names, use index */ - res_ctrl = platform_get_resource(pdev, ioresource_mem, 0); - if (res_ctrl == null) { - dev_err(dev, "can't get ctrl base address "); - return -einval; - } - res_xhciec = platform_get_resource(pdev, ioresource_mem, 1); - } - priv->ini.ctrl_regs = devm_ioremap_resource(dev, res_ctrl); - if (is_err(priv->ini.ctrl_regs)) { - dev_err(dev, "can't map ctrl register space "); - return -einval; - } - if (res_xhciec) { - priv->ini.xhci_ec_regs = - devm_ioremap_resource(dev, res_xhciec); - if (is_err(priv->ini.xhci_ec_regs)) { - dev_err(dev, "can't map xhci ec register space "); - return -einval; - } - } - if (res_xhcigbl) { - priv->ini.xhci_gbl_regs = - devm_ioremap_resource(dev, res_xhcigbl); - if (is_err(priv->ini.xhci_gbl_regs)) { - dev_err(dev, "can't map xhci global register space "); - return -einval; - } - } - + for (x = 0; x < brcm_regs_max; x++) { + if (info->required_regs[x] >= brcm_regs_max) + break; + + err = brcm_usb_get_regs(pdev, info->required_regs[x], + &priv->ini); + if (err) + return -einval; + } + + /* get piarbctl syscon if it exists */ + rmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "syscon-piarbctl"); + if (is_err(rmap)) + rmap = syscon_regmap_lookup_by_phandle(dev->of_node, + "brcm,syscon-piarbctl"); + if (!is_err(rmap)) + priv->ini.syscon_piarbctl = rmap; + | PHY ("physical layer" framework) | 9d5f51dcdb646c2ed21649d379fbb703994f1ec9 | al cooper florian fainelli f fainelli gmail com | drivers | phy | broadcom |
phy: usb: add support for new synopsys usb controller on the 7216 | the 7216 has the new usb xhci controller from synopsys. while this new controller and the phy are similar to the stb versions, the major differences are: | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for new synopsys usb controller on the 7216 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['usb'] | ['c', 'makefile', 'h'] | 4 | 227 | 18 | - many of the registers and fields in the ctrl block have been - a new set of synopsys control registers, bchp_usb_xhci_gbl, were - mdio functionality has been replaced with direct access registers - power up phy defaults that had to be changed by mdio in previous --- diff --git a/drivers/phy/broadcom/makefile b/drivers/phy/broadcom/makefile --- a/drivers/phy/broadcom/makefile +++ b/drivers/phy/broadcom/makefile -phy-brcm-usb-dvr-objs := phy-brcm-usb.o phy-brcm-usb-init.o +phy-brcm-usb-dvr-objs := phy-brcm-usb.o phy-brcm-usb-init.o phy-brcm-usb-init-synopsys.o diff --git a/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c b/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c --- /dev/null +++ b/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c +// spdx-license-identifier: gpl-2.0 +/* copyright (c) 2018, broadcom */ + +/* + * this module contains usb phy initialization for power up and s3 resume + * for newer synopsys based usb hardware first used on the bcm7216. + */ + +#include <linux/delay.h> +#include <linux/io.h> + +#include <linux/soc/brcmstb/brcmstb.h> +#include "phy-brcm-usb-init.h" + +/* register definitions for the usb ctrl block */ +#define usb_ctrl_setup 0x00 +#define usb_ctrl_setup_strap_ipp_sel_mask 0x02000000 +#define usb_ctrl_setup_scb2_en_mask 0x00008000 +#define usb_ctrl_setup_scb1_en_mask 0x00004000 +#define usb_ctrl_setup_soft_shutdown_mask 0x00000200 +#define usb_ctrl_setup_ipp_mask 0x00000020 +#define usb_ctrl_setup_ioc_mask 0x00000010 +#define usb_ctrl_usb_pm 0x04 +#define usb_ctrl_usb_pm_usb_pwrdn_mask 0x80000000 +#define usb_ctrl_usb_pm_soft_reset_mask 0x40000000 +#define usb_ctrl_usb_pm_bdc_soft_resetb_mask 0x00800000 +#define usb_ctrl_usb_pm_xhc_soft_resetb_mask 0x00400000 +#define usb_ctrl_usb_pm_status 0x08 +#define usb_ctrl_usb_device_ctl1 0x10 +#define usb_ctrl_usb_device_ctl1_port_mode_mask 0x00000003 + + +static void xhci_soft_reset(struct brcm_usb_init_params *params, + int on_off) +{ + void __iomem *ctrl = params->ctrl_regs; + + /* assert reset */ + if (on_off) + usb_ctrl_unset(ctrl, usb_pm, xhc_soft_resetb); + /* de-assert reset */ + else + usb_ctrl_set(ctrl, usb_pm, xhc_soft_resetb); +} + +static void usb_init_ipp(struct brcm_usb_init_params *params) +{ + void __iomem *ctrl = params->ctrl_regs; + u32 reg; + u32 orig_reg; + + pr_debug("%s ", __func__); + + orig_reg = reg = brcm_usb_readl(usb_ctrl_reg(ctrl, setup)); + if (params->ipp != 2) + /* override ipp strap pin (if it exits) */ + reg &= ~(usb_ctrl_mask(setup, strap_ipp_sel)); + + /* override the default oc and pp polarity */ + reg &= ~(usb_ctrl_mask(setup, ipp) | usb_ctrl_mask(setup, ioc)); + if (params->ioc) + reg |= usb_ctrl_mask(setup, ioc); + if (params->ipp == 1) + reg |= usb_ctrl_mask(setup, ipp); + brcm_usb_writel(reg, usb_ctrl_reg(ctrl, setup)); + + /* + * if we're changing ipp, make sure power is off long enough + * to turn off any connected devices. + */ + if ((reg ^ orig_reg) & usb_ctrl_mask(setup, ipp)) + msleep(50); +} + +static void usb_init_common(struct brcm_usb_init_params *params) +{ + u32 reg; + void __iomem *ctrl = params->ctrl_regs; + + pr_debug("%s ", __func__); + + usb_ctrl_unset(ctrl, usb_pm, usb_pwrdn); + /* 1 millisecond - for usb clocks to settle down */ + usleep_range(1000, 2000); + + if (usb_ctrl_mask(usb_device_ctl1, port_mode)) { + reg = brcm_usb_readl(usb_ctrl_reg(ctrl, usb_device_ctl1)); + reg &= ~usb_ctrl_mask(usb_device_ctl1, port_mode); + reg |= params->mode; + brcm_usb_writel(reg, usb_ctrl_reg(ctrl, usb_device_ctl1)); + } + switch (params->mode) { + case usb_ctlr_mode_host: + usb_ctrl_unset(ctrl, usb_pm, bdc_soft_resetb); + break; + default: + usb_ctrl_unset(ctrl, usb_pm, bdc_soft_resetb); + usb_ctrl_set(ctrl, usb_pm, bdc_soft_resetb); + break; + } +} + +static void usb_init_xhci(struct brcm_usb_init_params *params) +{ + pr_debug("%s ", __func__); + + xhci_soft_reset(params, 0); +} + +static void usb_uninit_common(struct brcm_usb_init_params *params) +{ + void __iomem *ctrl = params->ctrl_regs; + + pr_debug("%s ", __func__); + + usb_ctrl_set(ctrl, usb_pm, usb_pwrdn); + +} + +static void usb_uninit_xhci(struct brcm_usb_init_params *params) +{ + + pr_debug("%s ", __func__); + + xhci_soft_reset(params, 1); +} + +static int usb_get_dual_select(struct brcm_usb_init_params *params) +{ + void __iomem *ctrl = params->ctrl_regs; + u32 reg = 0; + + pr_debug("%s ", __func__); + + reg = brcm_usb_readl(usb_ctrl_reg(ctrl, usb_device_ctl1)); + reg &= usb_ctrl_mask(usb_device_ctl1, port_mode); + return reg; +} + +static void usb_set_dual_select(struct brcm_usb_init_params *params, int mode) +{ + void __iomem *ctrl = params->ctrl_regs; + u32 reg; + + pr_debug("%s ", __func__); + + reg = brcm_usb_readl(usb_ctrl_reg(ctrl, usb_device_ctl1)); + reg &= ~usb_ctrl_mask(usb_device_ctl1, port_mode); + reg |= mode; + brcm_usb_writel(reg, usb_ctrl_reg(ctrl, usb_device_ctl1)); +} + + +static const struct brcm_usb_init_ops bcm7216_ops = { + .init_ipp = usb_init_ipp, + .init_common = usb_init_common, + .init_xhci = usb_init_xhci, + .uninit_common = usb_uninit_common, + .uninit_xhci = usb_uninit_xhci, + .get_dual_select = usb_get_dual_select, + .set_dual_select = usb_set_dual_select, +}; + +void brcm_usb_dvr_init_7216(struct brcm_usb_init_params *params) +{ + + pr_debug("%s ", __func__); + + params->family_name = "7216"; + params->ops = &bcm7216_ops; +} diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.h b/drivers/phy/broadcom/phy-brcm-usb-init.h --- a/drivers/phy/broadcom/phy-brcm-usb-init.h +++ b/drivers/phy/broadcom/phy-brcm-usb-init.h + void __iomem *xhci_gbl_regs; +void brcm_usb_dvr_init_7216(struct brcm_usb_init_params *params); diff --git a/drivers/phy/broadcom/phy-brcm-usb.c b/drivers/phy/broadcom/phy-brcm-usb.c --- a/drivers/phy/broadcom/phy-brcm-usb.c +++ b/drivers/phy/broadcom/phy-brcm-usb.c +static const struct of_device_id brcm_usb_dt_ids[] = { + { + .compatible = "brcm,bcm7216-usb-phy", + .data = &brcm_usb_dvr_init_7216, + }, + { .compatible = "brcm,brcmstb-usb-phy" }, + { /* sentinel */ } +}; + - struct resource *res; + struct resource *res_ctrl; + struct resource *res_xhciec = null; + struct resource *res_xhcigbl = null; + const struct of_device_id *match; - brcm_usb_dvr_init_7445(&priv->ini); + + match = of_match_node(brcm_usb_dt_ids, dev->of_node); + if (match && match->data) { + void (*dvr_init)(struct brcm_usb_init_params *params); + + dvr_init = match->data; + (*dvr_init)(&priv->ini); + } else { + brcm_usb_dvr_init_7445(&priv->ini); + } + - res = platform_get_resource(pdev, ioresource_mem, 0); - if (!res) { - dev_err(dev, "can't get usb_ctrl base address "); - return -einval; + + /* newer dt node has reg-names. xhci_ec and xhci_gbl are optional. */ + res_ctrl = platform_get_resource_byname(pdev, ioresource_mem, "ctrl"); + if (res_ctrl != null) { + res_xhciec = platform_get_resource_byname(pdev, + ioresource_mem, + "xhci_ec"); + res_xhcigbl = platform_get_resource_byname(pdev, + ioresource_mem, + "xhci_gbl"); + } else { + /* older dt node without reg-names, use index */ + res_ctrl = platform_get_resource(pdev, ioresource_mem, 0); + if (res_ctrl == null) { + dev_err(dev, "can't get ctrl base address "); + return -einval; + } + res_xhciec = platform_get_resource(pdev, ioresource_mem, 1); - priv->ini.ctrl_regs = devm_ioremap_resource(dev, res); + priv->ini.ctrl_regs = devm_ioremap_resource(dev, res_ctrl); - - /* the xhci ec registers are optional */ - res = platform_get_resource(pdev, ioresource_mem, 1); - if (res) { + if (res_xhciec) { - devm_ioremap_resource(dev, res); + devm_ioremap_resource(dev, res_xhciec); + if (res_xhcigbl) { + priv->ini.xhci_gbl_regs = + devm_ioremap_resource(dev, res_xhcigbl); + if (is_err(priv->ini.xhci_gbl_regs)) { + dev_err(dev, "can't map xhci global register space "); + return -einval; + } + } -static const struct of_device_id brcm_usb_dt_ids[] = { - { .compatible = "brcm,brcmstb-usb-phy" }, - { /* sentinel */ } -}; - | PHY ("physical layer" framework) | 4e5b9c9a73b32d28759225a40d30848393a8f1fd | al cooper | drivers | phy | broadcom |
phy: usb: add support for wake and usb low power mode for 7211 s2/s5 | add support for 7211 usb wake. disable all possible 7211 usb logic for s2/s5 if usb wake is not enabled. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for wake and usb low power mode for 7211 s2/s5 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['usb'] | ['c', 'h'] | 4 | 105 | 34 | --- diff --git a/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c b/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c --- a/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c +++ b/drivers/phy/broadcom/phy-brcm-usb-init-synopsys.c -#define piarbctl_usb_m_asb_ctrl 0x10 +#define usb_ctrl_test_port_ctl 0x30 +#define usb_ctrl_test_port_ctl_tpout_sel_mask 0x000000ff +#define usb_ctrl_test_port_ctl_tpout_sel_pme_gen_mask 0x0000002e +#define usb_ctrl_tp_diag1 0x34 +#define usb_ctlr_tp_diag1_wake_mask 0x00000002 +#define usb_ctrl_ctlr_cshcr 0x50 +#define usb_ctrl_ctlr_cshcr_ctl_pme_en_mask 0x00040000 +#define usb_phy_pll_ctl 0x00 +#define usb_phy_pll_ctl_pll_resetb_mask 0x40000000 +#define usb_phy_pll_ldo_ctl_afe_ldo_pwrdwnb_mask 0x00000002 +#define usb_phy_pll_ldo_ctl_afe_bg_pwrdwnb_mask 0x00000001 +#define usb_phy_iddq 0x1c +#define usb_phy_iddq_phy_iddq_mask 0x00000001 +static void usb_wake_enable_7211b0(struct brcm_usb_init_params *params, + bool enable) +{ + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; + + if (enable) + usb_ctrl_set(ctrl, ctlr_cshcr, ctl_pme_en); + else + usb_ctrl_unset(ctrl, ctlr_cshcr, ctl_pme_en); +} + + usb_ctrl_unset(ctrl, usb_pm, usb_pwrdn); + + usb_wake_enable_7211b0(params, false); + if (!params->wake_enabled) { + + /* undo possible suspend settings */ + brcm_usb_writel(0, usb_phy + usb_phy_iddq); + reg = brcm_usb_readl(usb_phy + usb_phy_pll_ctl); + reg |= usb_phy_pll_ctl_pll_resetb_mask; + brcm_usb_writel(reg, usb_phy + usb_phy_pll_ctl); + + /* temporarily enable fsm so phy comes up properly */ + reg = brcm_usb_readl(usb_phy + usb_phy_utmi_ctl_1); + reg |= usb_phy_utmi_ctl_1_power_up_fsm_en_mask; + brcm_usb_writel(reg, usb_phy + usb_phy_utmi_ctl_1); + } + - reg = brcm_usb_readl(usb_phy + usb_phy_pll_ldo_ctl); - reg |= usb_phy_pll_ldo_ctl_afe_corerdy_mask; + reg = usb_phy_pll_ldo_ctl_afe_corerdy_mask | + usb_phy_pll_ldo_ctl_afe_ldo_pwrdwnb_mask | + usb_phy_pll_ldo_ctl_afe_bg_pwrdwnb_mask; +static void usb_uninit_common_7211b0(struct brcm_usb_init_params *params) +{ + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; + void __iomem *usb_phy = params->regs[brcm_regs_usb_phy]; + u32 reg; + + pr_debug("%s ", __func__); + + if (params->wake_enabled) { + usb_ctrl_set(ctrl, test_port_ctl, tpout_sel_pme_gen); + usb_wake_enable_7211b0(params, true); + } else { + usb_ctrl_set(ctrl, usb_pm, usb_pwrdn); + brcm_usb_writel(0, usb_phy + usb_phy_pll_ldo_ctl); + reg = brcm_usb_readl(usb_phy + usb_phy_pll_ctl); + reg &= ~usb_phy_pll_ctl_pll_resetb_mask; + brcm_usb_writel(reg, usb_phy + usb_phy_pll_ctl); + brcm_usb_writel(usb_phy_iddq_phy_iddq_mask, + usb_phy + usb_phy_iddq); + } + +} + - xhci_soft_reset(params, 1); + if (!params->wake_enabled) + xhci_soft_reset(params, 1); - - .uninit_common = usb_uninit_common, + .uninit_common = usb_uninit_common_7211b0, + params->suspend_with_clocks = true; diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.c b/drivers/phy/broadcom/phy-brcm-usb-init.c --- a/drivers/phy/broadcom/phy-brcm-usb-init.c +++ b/drivers/phy/broadcom/phy-brcm-usb-init.c +static void usb_wake_enable(struct brcm_usb_init_params *params, + bool enable) +{ + void __iomem *ctrl = params->regs[brcm_regs_ctrl]; + + if (enable) + usb_ctrl_set(ctrl, usb_pm, rmtwkup_en); + else + usb_ctrl_unset(ctrl, usb_pm, rmtwkup_en); +} + + usb_wake_enable(params, false); + if (params->wake_enabled) + usb_wake_enable(params, true); -static void usb_wake_enable(struct brcm_usb_init_params *params, - int enable) -{ - void __iomem *ctrl = params->regs[brcm_regs_ctrl]; - - if (enable) - usb_ctrl_set(ctrl, usb_pm, rmtwkup_en); - else - usb_ctrl_unset(ctrl, usb_pm, rmtwkup_en); -} - - .wake_enable = usb_wake_enable, diff --git a/drivers/phy/broadcom/phy-brcm-usb-init.h b/drivers/phy/broadcom/phy-brcm-usb-init.h --- a/drivers/phy/broadcom/phy-brcm-usb-init.h +++ b/drivers/phy/broadcom/phy-brcm-usb-init.h - void (*wake_enable)(struct brcm_usb_init_params *params, - int enable); + bool wake_enabled; + bool suspend_with_clocks; -static inline void brcm_usb_wake_enable(struct brcm_usb_init_params *ini, - int enable) -{ - if (ini->ops->wake_enable) - ini->ops->wake_enable(ini, enable); -} - diff --git a/drivers/phy/broadcom/phy-brcm-usb.c b/drivers/phy/broadcom/phy-brcm-usb.c --- a/drivers/phy/broadcom/phy-brcm-usb.c +++ b/drivers/phy/broadcom/phy-brcm-usb.c + priv->ini.wake_enabled = device_may_wakeup(dev); - brcm_usb_wake_enable(&priv->ini, true); - if (priv->phys[brcm_usb_phy_3_0].inited) - clk_disable_unprepare(priv->usb_30_clk); - if (priv->phys[brcm_usb_phy_2_0].inited || !priv->has_eohci) - clk_disable_unprepare(priv->usb_20_clk); + + /* + * handle the clocks unless needed for wake. this has + * to work for both older xhci->3.0-clks, eohci->2.0-clks + * and newer xhci->2.0-clks/3.0-clks. + */ + + if (!priv->ini.suspend_with_clocks) { + if (priv->phys[brcm_usb_phy_3_0].inited) + clk_disable_unprepare(priv->usb_30_clk); + if (priv->phys[brcm_usb_phy_2_0].inited || + !priv->has_eohci) + clk_disable_unprepare(priv->usb_20_clk); + } - brcm_usb_wake_enable(&priv->ini, false); + if (!priv->has_eohci) + clk_disable_unprepare(priv->usb_20_clk); - + priv->ini.wake_enabled = false; | PHY ("physical layer" framework) | b0c0b66c0b432d3f3a1ae5849298ba9c7f1810c5 | al cooper | drivers | phy | broadcom |
pci/switchtec: add gen4 system info register support | add the gen4-specific system info registers and ensure their usage is guarded by a check on the device's generation. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add gen4 system info register support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['pci/switchtec'] | ['c', 'h'] | 2 | 48 | 0 | --- diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c + else if (stdev->gen == switchtec_gen4) \ + return io_string_show(buf, &si->gen4.field, \ + sizeof(si->gen4.field)); \ + else if (stdev->gen == switchtec_gen4) + part_id = &stdev->mmio_sys_info->gen4.partition_id; diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h --- a/include/linux/switchtec.h +++ b/include/linux/switchtec.h + switchtec_gen4, +struct sys_info_regs_gen4 { + u16 gas_layout_ver; + u8 evlist_ver; + u8 reserved1; + u16 mgmt_cmd_set_ver; + u16 fabric_cmd_set_ver; + u32 reserved2[2]; + u8 mrpc_uart_ver; + u8 mrpc_twi_ver; + u8 mrpc_eth_ver; + u8 mrpc_inband_ver; + u32 reserved3[7]; + u32 fw_update_tmo; + u32 xml_version_cfg; + u32 xml_version_img; + u32 partition_id; + u16 bl2_running; + u16 cfg_running; + u16 img_running; + u16 key_running; + u32 reserved4[43]; + u32 vendor_seeprom_twi; + u32 vendor_table_revision; + u32 vendor_specific_info[2]; + u16 p2p_vendor_id; + u16 p2p_device_id; + u8 p2p_revision_id; + u8 reserved5[3]; + u32 p2p_class_id; + u16 subsystem_vendor_id; + u16 subsystem_id; + u32 p2p_serial_number[2]; + u8 mac_addr[6]; + u8 reserved6[2]; + u32 reserved7[3]; + char vendor_id[8]; + char product_id[24]; + char product_revision[2]; + u16 reserved8; +} __packed; + + struct sys_info_regs_gen4 gen4; | Various | a3321ca394082f403b447646d81c18ff6b39f4a6 | logan gunthorpe | include | linux | switch |
pci/switchtec: add support for intercomm notify and upstream error containment | add support for the inter fabric manager communication (intercomm) notify event in pax variants of switchtec hardware and the upstream error containment port in the mr1 release of gen3 firmware. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for intercomm notify and upstream error containment | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['pci/switchtec'] | ['c', 'h'] | 3 | 11 | 3 | --- diff --git a/drivers/pci/switch/switchtec.c b/drivers/pci/switch/switchtec.c --- a/drivers/pci/switch/switchtec.c +++ b/drivers/pci/switch/switchtec.c + ev_par(switchtec_ioctl_event_intercomm_req_notify, + intercomm_notify_hdr), + ev_pff(switchtec_ioctl_event_uec, uec_hdr), diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h --- a/include/linux/switchtec.h +++ b/include/linux/switchtec.h - u32 reserved4[159]; + u32 intercomm_notify_hdr; + u32 intercomm_notify_data[5]; + u32 reserved4[153]; - u32 reserved3[6]; + u32 uec_hdr; + u32 uec_data[5]; diff --git a/include/uapi/linux/switchtec_ioctl.h b/include/uapi/linux/switchtec_ioctl.h --- a/include/uapi/linux/switchtec_ioctl.h +++ b/include/uapi/linux/switchtec_ioctl.h -#define switchtec_ioctl_max_events 30 +#define switchtec_ioctl_event_intercomm_req_notify 30 +#define switchtec_ioctl_event_uec 31 +#define switchtec_ioctl_max_events 32 | Various | a6b0ef9a7d03bb78d37c420753741ef8a082160b | logan gunthorpe | include | uapi | linux, switch |
firmware: qcom_scm: dynamically support smccc and legacy conventions | dynamically support smcccc and legacy conventions by detecting which convention to use at runtime. qcom_scm_call_atomic and qcom_scm_call can then be moved in qcom_scm.c and use underlying convention backend as appropriate. thus, rename qcom_scm-64,-32 to reflect that they are backends for -smc and -legacy, respectively. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | dynamically support smccc and legacy conventions | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['firmware', 'qcom_scm'] | ['c', 'kconfig', 'makefile', 'h'] | 6 | 176 | 135 | --- diff --git a/drivers/firmware/kconfig b/drivers/firmware/kconfig --- a/drivers/firmware/kconfig +++ b/drivers/firmware/kconfig -config qcom_scm_32 - def_bool y - depends on qcom_scm && arm - -config qcom_scm_64 - def_bool y - depends on qcom_scm && arm64 - diff --git a/drivers/firmware/makefile b/drivers/firmware/makefile --- a/drivers/firmware/makefile +++ b/drivers/firmware/makefile -obj-$(config_qcom_scm) += qcom_scm.o -obj-$(config_qcom_scm_64) += qcom_scm-64.o -obj-$(config_qcom_scm_32) += qcom_scm-32.o +obj-$(config_qcom_scm) += qcom_scm.o qcom_scm-smc.o qcom_scm-legacy.o diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-legacy.c --- a/drivers/firmware/qcom_scm-32.c +++ b/drivers/firmware/qcom_scm-legacy.c -#define scm_legacy_fnid(s, c) (((s) << 10) | ((c) & 0x3ff)) -int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, - struct qcom_scm_res *res) +int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, + struct qcom_scm_res *res) -int qcom_scm_call_atomic(struct device *unused, - const struct qcom_scm_desc *desc, - struct qcom_scm_res *res) +int scm_legacy_call_atomic(struct device *unused, + const struct qcom_scm_desc *desc, + struct qcom_scm_res *res) - -int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = qcom_scm_svc_info, - .cmd = qcom_scm_info_is_call_avail, - .args[0] = scm_legacy_fnid(svc_id, cmd_id), - .arginfo = qcom_scm_args(1), - }; - struct qcom_scm_res res; - - ret = qcom_scm_call(dev, &desc, &res); - - return ret ? : res.result[0]; -} - -void __qcom_scm_init(void) -{ -} diff --git a/drivers/firmware/qcom_scm-64.c b/drivers/firmware/qcom_scm-smc.c --- a/drivers/firmware/qcom_scm-64.c +++ b/drivers/firmware/qcom_scm-smc.c -#define scm_smc_fnid(s, c) ((((s) & 0xff) << 8) | ((c) & 0xff)) - -static u64 qcom_smccc_convention = -1; -static int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc, - struct qcom_scm_res *res, bool atomic) +int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc, + struct qcom_scm_res *res, bool atomic) + u32 qcom_smccc_convention = + (qcom_scm_convention == smc_convention_arm_32) ? + arm_smccc_smc_32 : arm_smccc_smc_64; - -/** - * qcom_scm_call() - invoke a syscall in the secure world - * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier - * @desc: descriptor structure containing arguments and return values - * - * sends a command to the scm and waits for the command to finish processing. - * this should *only* be called in pre-emptible context. - */ -int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, - struct qcom_scm_res *res) -{ - might_sleep(); - return __scm_smc_call(dev, desc, res, false); -} - -/** - * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() - * @dev: device - * @svc_id: service identifier - * @cmd_id: command identifier - * @desc: descriptor structure containing arguments and return values - * @res: structure containing results from smc/hvc call - * - * sends a command to the scm and waits for the command to finish processing. - * this can be called in atomic context. - */ -int qcom_scm_call_atomic(struct device *dev, const struct qcom_scm_desc *desc, - struct qcom_scm_res *res) -{ - return __scm_smc_call(dev, desc, res, true); -} - -int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, u32 cmd_id) -{ - int ret; - struct qcom_scm_desc desc = { - .svc = qcom_scm_svc_info, - .cmd = qcom_scm_info_is_call_avail, - .owner = arm_smccc_owner_sip, - }; - struct qcom_scm_res res; - - desc.arginfo = qcom_scm_args(1); - desc.args[0] = scm_smc_fnid(svc_id, cmd_id) | - (arm_smccc_owner_sip << arm_smccc_owner_shift); - - ret = qcom_scm_call(dev, &desc, &res); - - return ret ? : res.result[0]; -} - -void __qcom_scm_init(void) -{ - struct qcom_scm_desc desc = { - .svc = qcom_scm_svc_info, - .cmd = qcom_scm_info_is_call_avail, - .args[0] = scm_smc_fnid(qcom_scm_svc_info, - qcom_scm_info_is_call_avail) | - (arm_smccc_owner_sip << arm_smccc_owner_shift), - .arginfo = qcom_scm_args(1), - .owner = arm_smccc_owner_sip, - }; - struct qcom_scm_res res; - int ret; - - qcom_smccc_convention = arm_smccc_smc_64; - // device isn't required as there is only one argument - no device - // needed to dma_map_single to secure world - ret = qcom_scm_call_atomic(null, &desc, &res); - if (!ret && res.result[0] == 1) - goto out; - - qcom_smccc_convention = arm_smccc_smc_32; - ret = qcom_scm_call_atomic(null, &desc, &res); - if (!ret && res.result[0] == 1) - goto out; - - qcom_smccc_convention = -1; - bug(); -out: - pr_info("qcom scm smc convention: %lld ", qcom_smccc_convention); -} diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c +static const char *qcom_scm_convention_names[] = { + [smc_convention_unknown] = "unknown", + [smc_convention_arm_32] = "smc arm 32", + [smc_convention_arm_64] = "smc arm 64", + [smc_convention_legacy] = "smc legacy", +}; + +static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, + u32 cmd_id); + +enum qcom_scm_convention qcom_scm_convention; +static bool has_queried __read_mostly; +static define_spinlock(query_lock); + +static void __query_convention(void) +{ + unsigned long flags; + struct qcom_scm_desc desc = { + .svc = qcom_scm_svc_info, + .cmd = qcom_scm_info_is_call_avail, + .args[0] = scm_smc_fnid(qcom_scm_svc_info, + qcom_scm_info_is_call_avail) | + (arm_smccc_owner_sip << arm_smccc_owner_shift), + .arginfo = qcom_scm_args(1), + .owner = arm_smccc_owner_sip, + }; + struct qcom_scm_res res; + int ret; + + spin_lock_irqsave(&query_lock, flags); + if (has_queried) + goto out; + + qcom_scm_convention = smc_convention_arm_64; + // device isn't required as there is only one argument - no device + // needed to dma_map_single to secure world + ret = scm_smc_call(null, &desc, &res, true); + if (!ret && res.result[0] == 1) + goto out; + + qcom_scm_convention = smc_convention_arm_32; + ret = scm_smc_call(null, &desc, &res, true); + if (!ret && res.result[0] == 1) + goto out; + + qcom_scm_convention = smc_convention_legacy; +out: + has_queried = true; + spin_unlock_irqrestore(&query_lock, flags); + pr_info("qcom_scm: convention: %s ", + qcom_scm_convention_names[qcom_scm_convention]); +} + +static inline enum qcom_scm_convention __get_convention(void) +{ + if (unlikely(!has_queried)) + __query_convention(); + return qcom_scm_convention; +} + +/** + * qcom_scm_call() - invoke a syscall in the secure world + * @dev: device + * @svc_id: service identifier + * @cmd_id: command identifier + * @desc: descriptor structure containing arguments and return values + * + * sends a command to the scm and waits for the command to finish processing. + * this should *only* be called in pre-emptible context. + */ +static int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, + struct qcom_scm_res *res) +{ + might_sleep(); + switch (__get_convention()) { + case smc_convention_arm_32: + case smc_convention_arm_64: + return scm_smc_call(dev, desc, res, false); + case smc_convention_legacy: + return scm_legacy_call(dev, desc, res); + default: + pr_err("unknown current scm calling convention. "); + return -einval; + } +} + +/** + * qcom_scm_call_atomic() - atomic variation of qcom_scm_call() + * @dev: device + * @svc_id: service identifier + * @cmd_id: command identifier + * @desc: descriptor structure containing arguments and return values + * @res: structure containing results from smc/hvc call + * + * sends a command to the scm and waits for the command to finish processing. + * this can be called in atomic context. + */ +static int qcom_scm_call_atomic(struct device *dev, + const struct qcom_scm_desc *desc, + struct qcom_scm_res *res) +{ + switch (__get_convention()) { + case smc_convention_arm_32: + case smc_convention_arm_64: + return scm_smc_call(dev, desc, res, true); + case smc_convention_legacy: + return scm_legacy_call_atomic(dev, desc, res); + default: + pr_err("unknown current scm calling convention. "); + return -einval; + } +} + +static int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, + u32 cmd_id) +{ + int ret; + struct qcom_scm_desc desc = { + .svc = qcom_scm_svc_info, + .cmd = qcom_scm_info_is_call_avail, + .owner = arm_smccc_owner_sip, + }; + struct qcom_scm_res res; + + desc.arginfo = qcom_scm_args(1); + switch (__get_convention()) { + case smc_convention_arm_32: + case smc_convention_arm_64: + desc.args[0] = scm_smc_fnid(svc_id, cmd_id) | + (arm_smccc_owner_sip << arm_smccc_owner_shift); + break; + case smc_convention_legacy: + desc.args[0] = scm_legacy_fnid(svc_id, cmd_id); + break; + default: + pr_err("unknown smc convention being used "); + return -einval; + } + + ret = qcom_scm_call(dev, &desc, &res); + + return ret ? : res.result[0]; +} + - __qcom_scm_init(); + __query_convention(); diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h + +enum qcom_scm_convention { + smc_convention_unknown, + smc_convention_legacy, + smc_convention_arm_32, + smc_convention_arm_64, +}; + +extern enum qcom_scm_convention qcom_scm_convention; + -extern int qcom_scm_call(struct device *dev, const struct qcom_scm_desc *desc, - struct qcom_scm_res *res); -extern int qcom_scm_call_atomic(struct device *dev, - const struct qcom_scm_desc *desc, - struct qcom_scm_res *res); +#define scm_smc_fnid(s, c) ((((s) & 0xff) << 8) | ((c) & 0xff)) +extern int scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc, + struct qcom_scm_res *res, bool atomic); + +#define scm_legacy_fnid(s, c) (((s) << 10) | ((c) & 0x3ff)) +extern int scm_legacy_call_atomic(struct device *dev, + const struct qcom_scm_desc *desc, + struct qcom_scm_res *res); +extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, + struct qcom_scm_res *res); -extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id, - u32 cmd_id); | Various | 9a434cee773ae15309ac225f27551b5492618e4a | elliot berman | drivers | firmware | |
interconnect: add interconnect_graph file to debugfs | the interconnect graphs can be difficult to understand and the current "interconnect_summary" file doesn't even display links in any way. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add interconnect_graph file to debugfs | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['interconnect'] | ['c', 'rst'] | 2 | 88 | 0 | --- diff --git a/documentation/driver-api/interconnect.rst b/documentation/driver-api/interconnect.rst --- a/documentation/driver-api/interconnect.rst +++ b/documentation/driver-api/interconnect.rst + +interconnect debugfs interfaces +------------------------------- + +like several other subsystems interconnect will create some files for debugging +and introspection. files in debugfs are not considered abi so application +software shouldn't rely on format details change between kernel versions. + +''/sys/kernel/debug/interconnect/interconnect_summary'': + +show all interconnect nodes in the system with their aggregated bandwidth +request. indented under each node show bandwidth requests from each device. + +''/sys/kernel/debug/interconnect/interconnect_graph'': + +show the interconnect graph in the graphviz dot format. it shows all +interconnect nodes and links in the system and groups together nodes from the +same provider as subgraphs. the format is human-readable and can also be piped +through dot to generate diagrams in many graphical formats:: + + $ cat /sys/kernel/debug/interconnect/interconnect_graph | \ + dot -tsvg > interconnect_graph.svg diff --git a/drivers/interconnect/core.c b/drivers/interconnect/core.c --- a/drivers/interconnect/core.c +++ b/drivers/interconnect/core.c +static void icc_graph_show_link(struct seq_file *s, int level, + struct icc_node *n, struct icc_node *m) +{ + seq_printf(s, "%s"%d:%s" -> "%d:%s" ", + level == 2 ? " " : " ", + n->id, n->name, m->id, m->name); +} + +static void icc_graph_show_node(struct seq_file *s, struct icc_node *n) +{ + seq_printf(s, " "%d:%s" [label="%d:%s", + n->id, n->name, n->id, n->name); + seq_printf(s, " |avg_bw=%ukbps", n->avg_bw); + seq_printf(s, " |peak_bw=%ukbps", n->peak_bw); + seq_puts(s, ""] "); +} + +static int icc_graph_show(struct seq_file *s, void *data) +{ + struct icc_provider *provider; + struct icc_node *n; + int cluster_index = 0; + int i; + + seq_puts(s, "digraph { rankdir = lr node [shape = record] "); + mutex_lock(&icc_lock); + + /* draw providers as cluster subgraphs */ + cluster_index = 0; + list_for_each_entry(provider, &icc_providers, provider_list) { + seq_printf(s, " subgraph cluster_%d { ", ++cluster_index); + if (provider->dev) + seq_printf(s, " label = "%s" ", + dev_name(provider->dev)); + + /* draw nodes */ + list_for_each_entry(n, &provider->nodes, node_list) + icc_graph_show_node(s, n); + + /* draw internal links */ + list_for_each_entry(n, &provider->nodes, node_list) + for (i = 0; i < n->num_links; ++i) + if (n->provider == n->links[i]->provider) + icc_graph_show_link(s, 2, n, + n->links[i]); + + seq_puts(s, " } "); + } + + /* draw external links */ + list_for_each_entry(provider, &icc_providers, provider_list) + list_for_each_entry(n, &provider->nodes, node_list) + for (i = 0; i < n->num_links; ++i) + if (n->provider != n->links[i]->provider) + icc_graph_show_link(s, 1, n, + n->links[i]); + + mutex_unlock(&icc_lock); + seq_puts(s, "}"); + + return 0; +} +define_show_attribute(icc_graph); + + debugfs_create_file("interconnect_graph", 0444, + icc_debugfs_dir, null, &icc_graph_fops); | Various | 1a0013c62b33158dcb67a3c11872a03be50711a3 | leonard crestez | documentation | driver-api | |
interconnect: qcom: add msm8916 interconnect provider driver | add driver for the qualcomm interconnect buses found in msm8916 based platforms. the topology consists of three nocs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pairs. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add msm8916 interconnect provider driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['interconnect', 'qcom'] | ['c', 'kconfig', 'makefile'] | 3 | 565 | 0 | --- diff --git a/drivers/interconnect/qcom/kconfig b/drivers/interconnect/qcom/kconfig --- a/drivers/interconnect/qcom/kconfig +++ b/drivers/interconnect/qcom/kconfig +config interconnect_qcom_msm8916 + tristate "qualcomm msm8916 interconnect driver" + depends on interconnect_qcom + depends on qcom_smd_rpm + select interconnect_qcom_smd_rpm + help + this is a driver for the qualcomm network-on-chip on msm8916-based + platforms. + diff --git a/drivers/interconnect/qcom/makefile b/drivers/interconnect/qcom/makefile --- a/drivers/interconnect/qcom/makefile +++ b/drivers/interconnect/qcom/makefile +qnoc-msm8916-objs := msm8916.o +obj-$(config_interconnect_qcom_msm8916) += qnoc-msm8916.o diff --git a/drivers/interconnect/qcom/msm8916.c b/drivers/interconnect/qcom/msm8916.c --- /dev/null +++ b/drivers/interconnect/qcom/msm8916.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018-2020 linaro ltd + * author: georgi djakov <georgi.djakov@linaro.org> + */ + +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/interconnect-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/of_device.h> + +#include <dt-bindings/interconnect/qcom,msm8916.h> + +#include "smd-rpm.h" + +#define rpm_bus_master_req 0x73616d62 +#define rpm_bus_slave_req 0x766c7362 + +enum { + msm8916_bimc_snoc_mas = 1, + msm8916_bimc_snoc_slv, + msm8916_master_ampss_m0, + msm8916_master_lpass, + msm8916_master_blsp_1, + msm8916_master_dehr, + msm8916_master_graphics_3d, + msm8916_master_jpeg, + msm8916_master_mdp_port0, + msm8916_master_crypto_core0, + msm8916_master_sdcc_1, + msm8916_master_sdcc_2, + msm8916_master_qdss_bam, + msm8916_master_qdss_etr, + msm8916_master_snoc_cfg, + msm8916_master_spdm, + msm8916_master_tcu0, + msm8916_master_tcu1, + msm8916_master_usb_hs, + msm8916_master_vfe, + msm8916_master_video_p0, + msm8916_snoc_mm_int_0, + msm8916_snoc_mm_int_1, + msm8916_snoc_mm_int_2, + msm8916_snoc_mm_int_bimc, + msm8916_pnoc_int_0, + msm8916_pnoc_int_1, + msm8916_pnoc_mas_0, + msm8916_pnoc_mas_1, + msm8916_pnoc_slv_0, + msm8916_pnoc_slv_1, + msm8916_pnoc_slv_2, + msm8916_pnoc_slv_3, + msm8916_pnoc_slv_4, + msm8916_pnoc_slv_8, + msm8916_pnoc_slv_9, + msm8916_pnoc_snoc_mas, + msm8916_pnoc_snoc_slv, + msm8916_snoc_qdss_int, + msm8916_slave_ampss_l2, + msm8916_slave_apss, + msm8916_slave_lpass, + msm8916_slave_bimc_cfg, + msm8916_slave_blsp_1, + msm8916_slave_boot_rom, + msm8916_slave_camera_cfg, + msm8916_slave_cats_128, + msm8916_slave_ocmem_64, + msm8916_slave_clk_ctl, + msm8916_slave_crypto_0_cfg, + msm8916_slave_dehr_cfg, + msm8916_slave_display_cfg, + msm8916_slave_ebi_ch0, + msm8916_slave_graphics_3d_cfg, + msm8916_slave_imem_cfg, + msm8916_slave_imem, + msm8916_slave_mpm, + msm8916_slave_msg_ram, + msm8916_slave_mss, + msm8916_slave_pdm, + msm8916_slave_pmic_arb, + msm8916_slave_pnoc_cfg, + msm8916_slave_prng, + msm8916_slave_qdss_cfg, + msm8916_slave_qdss_stm, + msm8916_slave_rbcpr_cfg, + msm8916_slave_sdcc_1, + msm8916_slave_sdcc_2, + msm8916_slave_security, + msm8916_slave_snoc_cfg, + msm8916_slave_spdm, + msm8916_slave_srvc_snoc, + msm8916_slave_tcsr, + msm8916_slave_tlmm, + msm8916_slave_usb_hs, + msm8916_slave_venus_cfg, + msm8916_snoc_bimc_0_mas, + msm8916_snoc_bimc_0_slv, + msm8916_snoc_bimc_1_mas, + msm8916_snoc_bimc_1_slv, + msm8916_snoc_int_0, + msm8916_snoc_int_1, + msm8916_snoc_int_bimc, + msm8916_snoc_pnoc_mas, + msm8916_snoc_pnoc_slv, +}; + +#define to_msm8916_provider(_provider) \ + container_of(_provider, struct msm8916_icc_provider, provider) + +static const struct clk_bulk_data msm8916_bus_clocks[] = { + { .id = "bus" }, + { .id = "bus_a" }, +}; + +/** + * struct msm8916_icc_provider - qualcomm specific interconnect provider + * @provider: generic interconnect provider + * @bus_clks: the clk_bulk_data table of bus clocks + * @num_clks: the total number of clk_bulk_data entries + */ +struct msm8916_icc_provider { + struct icc_provider provider; + struct clk_bulk_data *bus_clks; + int num_clks; +}; + +#define msm8916_max_links 8 + +/** + * struct msm8916_icc_node - qualcomm specific interconnect nodes + * @name: the node name used in debugfs + * @id: a unique node identifier + * @links: an array of nodes where we can go next while traversing + * @num_links: the total number of @links + * @buswidth: width of the interconnect between a node and the bus (bytes) + * @mas_rpm_id: rpm id for devices that are bus masters + * @slv_rpm_id: rpm id for devices that are bus slaves + * @rate: current bus clock rate in hz + */ +struct msm8916_icc_node { + unsigned char *name; + u16 id; + u16 links[msm8916_max_links]; + u16 num_links; + u16 buswidth; + int mas_rpm_id; + int slv_rpm_id; + u64 rate; +}; + +struct msm8916_icc_desc { + struct msm8916_icc_node **nodes; + size_t num_nodes; +}; + +#define define_qnode(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \ + ...) \ + static struct msm8916_icc_node _name = { \ + .name = #_name, \ + .id = _id, \ + .buswidth = _buswidth, \ + .mas_rpm_id = _mas_rpm_id, \ + .slv_rpm_id = _slv_rpm_id, \ + .num_links = array_size(((int[]){ __va_args__ })), \ + .links = { __va_args__ }, \ + } + +define_qnode(bimc_snoc_mas, msm8916_bimc_snoc_mas, 8, -1, -1, msm8916_bimc_snoc_slv); +define_qnode(bimc_snoc_slv, msm8916_bimc_snoc_slv, 8, -1, -1, msm8916_snoc_int_0, msm8916_snoc_int_1); +define_qnode(mas_apss, msm8916_master_ampss_m0, 8, -1, -1, msm8916_slave_ebi_ch0, msm8916_bimc_snoc_mas, msm8916_slave_ampss_l2); +define_qnode(mas_audio, msm8916_master_lpass, 4, -1, -1, msm8916_pnoc_mas_0); +define_qnode(mas_blsp_1, msm8916_master_blsp_1, 4, -1, -1, msm8916_pnoc_mas_1); +define_qnode(mas_dehr, msm8916_master_dehr, 4, -1, -1, msm8916_pnoc_mas_0); +define_qnode(mas_gfx, msm8916_master_graphics_3d, 8, -1, -1, msm8916_slave_ebi_ch0, msm8916_bimc_snoc_mas, msm8916_slave_ampss_l2); +define_qnode(mas_jpeg, msm8916_master_jpeg, 16, -1, -1, msm8916_snoc_mm_int_0, msm8916_snoc_mm_int_2); +define_qnode(mas_mdp, msm8916_master_mdp_port0, 16, -1, -1, msm8916_snoc_mm_int_0, msm8916_snoc_mm_int_2); +define_qnode(mas_pcnoc_crypto_0, msm8916_master_crypto_core0, 8, -1, -1, msm8916_pnoc_int_1); +define_qnode(mas_pcnoc_sdcc_1, msm8916_master_sdcc_1, 8, -1, -1, msm8916_pnoc_int_1); +define_qnode(mas_pcnoc_sdcc_2, msm8916_master_sdcc_2, 8, -1, -1, msm8916_pnoc_int_1); +define_qnode(mas_qdss_bam, msm8916_master_qdss_bam, 8, -1, -1, msm8916_snoc_qdss_int); +define_qnode(mas_qdss_etr, msm8916_master_qdss_etr, 8, -1, -1, msm8916_snoc_qdss_int); +define_qnode(mas_snoc_cfg, msm8916_master_snoc_cfg, 4, 20, -1, msm8916_snoc_qdss_int); +define_qnode(mas_spdm, msm8916_master_spdm, 4, -1, -1, msm8916_pnoc_mas_0); +define_qnode(mas_tcu0, msm8916_master_tcu0, 8, -1, -1, msm8916_slave_ebi_ch0, msm8916_bimc_snoc_mas, msm8916_slave_ampss_l2); +define_qnode(mas_tcu1, msm8916_master_tcu1, 8, -1, -1, msm8916_slave_ebi_ch0, msm8916_bimc_snoc_mas, msm8916_slave_ampss_l2); +define_qnode(mas_usb_hs, msm8916_master_usb_hs, 4, -1, -1, msm8916_pnoc_mas_1); +define_qnode(mas_vfe, msm8916_master_vfe, 16, -1, -1, msm8916_snoc_mm_int_1, msm8916_snoc_mm_int_2); +define_qnode(mas_video, msm8916_master_video_p0, 16, -1, -1, msm8916_snoc_mm_int_0, msm8916_snoc_mm_int_2); +define_qnode(mm_int_0, msm8916_snoc_mm_int_0, 16, -1, -1, msm8916_snoc_mm_int_bimc); +define_qnode(mm_int_1, msm8916_snoc_mm_int_1, 16, -1, -1, msm8916_snoc_mm_int_bimc); +define_qnode(mm_int_2, msm8916_snoc_mm_int_2, 16, -1, -1, msm8916_snoc_int_0); +define_qnode(mm_int_bimc, msm8916_snoc_mm_int_bimc, 16, -1, -1, msm8916_snoc_bimc_1_mas); +define_qnode(pcnoc_int_0, msm8916_pnoc_int_0, 8, -1, -1, msm8916_pnoc_snoc_mas, msm8916_pnoc_slv_0, msm8916_pnoc_slv_1, msm8916_pnoc_slv_2, msm8916_pnoc_slv_3, msm8916_pnoc_slv_4, msm8916_pnoc_slv_8, msm8916_pnoc_slv_9); +define_qnode(pcnoc_int_1, msm8916_pnoc_int_1, 8, -1, -1, msm8916_pnoc_snoc_mas); +define_qnode(pcnoc_m_0, msm8916_pnoc_mas_0, 8, -1, -1, msm8916_pnoc_int_0); +define_qnode(pcnoc_m_1, msm8916_pnoc_mas_1, 8, -1, -1, msm8916_pnoc_snoc_mas); +define_qnode(pcnoc_s_0, msm8916_pnoc_slv_0, 8, -1, -1, msm8916_slave_clk_ctl, msm8916_slave_tlmm, msm8916_slave_tcsr, msm8916_slave_security, msm8916_slave_mss); +define_qnode(pcnoc_s_1, msm8916_pnoc_slv_1, 8, -1, -1, msm8916_slave_imem_cfg, msm8916_slave_crypto_0_cfg, msm8916_slave_msg_ram, msm8916_slave_pdm, msm8916_slave_prng); +define_qnode(pcnoc_s_2, msm8916_pnoc_slv_2, 8, -1, -1, msm8916_slave_spdm, msm8916_slave_boot_rom, msm8916_slave_bimc_cfg, msm8916_slave_pnoc_cfg, msm8916_slave_pmic_arb); +define_qnode(pcnoc_s_3, msm8916_pnoc_slv_3, 8, -1, -1, msm8916_slave_mpm, msm8916_slave_snoc_cfg, msm8916_slave_rbcpr_cfg, msm8916_slave_qdss_cfg, msm8916_slave_dehr_cfg); +define_qnode(pcnoc_s_4, msm8916_pnoc_slv_4, 8, -1, -1, msm8916_slave_venus_cfg, msm8916_slave_camera_cfg, msm8916_slave_display_cfg); +define_qnode(pcnoc_s_8, msm8916_pnoc_slv_8, 8, -1, -1, msm8916_slave_usb_hs, msm8916_slave_sdcc_1, msm8916_slave_blsp_1); +define_qnode(pcnoc_s_9, msm8916_pnoc_slv_9, 8, -1, -1, msm8916_slave_sdcc_2, msm8916_slave_lpass, msm8916_slave_graphics_3d_cfg); +define_qnode(pcnoc_snoc_mas, msm8916_pnoc_snoc_mas, 8, 29, -1, msm8916_pnoc_snoc_slv); +define_qnode(pcnoc_snoc_slv, msm8916_pnoc_snoc_slv, 8, -1, 45, msm8916_snoc_int_0, msm8916_snoc_int_bimc, msm8916_snoc_int_1); +define_qnode(qdss_int, msm8916_snoc_qdss_int, 8, -1, -1, msm8916_snoc_int_0, msm8916_snoc_int_bimc); +define_qnode(slv_apps_l2, msm8916_slave_ampss_l2, 8, -1, -1, 0); +define_qnode(slv_apss, msm8916_slave_apss, 4, -1, 20, 0); +define_qnode(slv_audio, msm8916_slave_lpass, 4, -1, -1, 0); +define_qnode(slv_bimc_cfg, msm8916_slave_bimc_cfg, 4, -1, -1, 0); +define_qnode(slv_blsp_1, msm8916_slave_blsp_1, 4, -1, -1, 0); +define_qnode(slv_boot_rom, msm8916_slave_boot_rom, 4, -1, -1, 0); +define_qnode(slv_camera_cfg, msm8916_slave_camera_cfg, 4, -1, -1, 0); +define_qnode(slv_cats_0, msm8916_slave_cats_128, 16, -1, 106, 0); +define_qnode(slv_cats_1, msm8916_slave_ocmem_64, 8, -1, 107, 0); +define_qnode(slv_clk_ctl, msm8916_slave_clk_ctl, 4, -1, -1, 0); +define_qnode(slv_crypto_0_cfg, msm8916_slave_crypto_0_cfg, 4, -1, -1, 0); +define_qnode(slv_dehr_cfg, msm8916_slave_dehr_cfg, 4, -1, -1, 0); +define_qnode(slv_display_cfg, msm8916_slave_display_cfg, 4, -1, -1, 0); +define_qnode(slv_ebi_ch0, msm8916_slave_ebi_ch0, 8, -1, 0, 0); +define_qnode(slv_gfx_cfg, msm8916_slave_graphics_3d_cfg, 4, -1, -1, 0); +define_qnode(slv_imem_cfg, msm8916_slave_imem_cfg, 4, -1, -1, 0); +define_qnode(slv_imem, msm8916_slave_imem, 8, -1, 26, 0); +define_qnode(slv_mpm, msm8916_slave_mpm, 4, -1, -1, 0); +define_qnode(slv_msg_ram, msm8916_slave_msg_ram, 4, -1, -1, 0); +define_qnode(slv_mss, msm8916_slave_mss, 4, -1, -1, 0); +define_qnode(slv_pdm, msm8916_slave_pdm, 4, -1, -1, 0); +define_qnode(slv_pmic_arb, msm8916_slave_pmic_arb, 4, -1, -1, 0); +define_qnode(slv_pcnoc_cfg, msm8916_slave_pnoc_cfg, 4, -1, -1, 0); +define_qnode(slv_prng, msm8916_slave_prng, 4, -1, -1, 0); +define_qnode(slv_qdss_cfg, msm8916_slave_qdss_cfg, 4, -1, -1, 0); +define_qnode(slv_qdss_stm, msm8916_slave_qdss_stm, 4, -1, 30, 0); +define_qnode(slv_rbcpr_cfg, msm8916_slave_rbcpr_cfg, 4, -1, -1, 0); +define_qnode(slv_sdcc_1, msm8916_slave_sdcc_1, 4, -1, -1, 0); +define_qnode(slv_sdcc_2, msm8916_slave_sdcc_2, 4, -1, -1, 0); +define_qnode(slv_security, msm8916_slave_security, 4, -1, -1, 0); +define_qnode(slv_snoc_cfg, msm8916_slave_snoc_cfg, 4, -1, -1, 0); +define_qnode(slv_spdm, msm8916_slave_spdm, 4, -1, -1, 0); +define_qnode(slv_srvc_snoc, msm8916_slave_srvc_snoc, 8, -1, 29, 0); +define_qnode(slv_tcsr, msm8916_slave_tcsr, 4, -1, -1, 0); +define_qnode(slv_tlmm, msm8916_slave_tlmm, 4, -1, -1, 0); +define_qnode(slv_usb_hs, msm8916_slave_usb_hs, 4, -1, -1, 0); +define_qnode(slv_venus_cfg, msm8916_slave_venus_cfg, 4, -1, -1, 0); +define_qnode(snoc_bimc_0_mas, msm8916_snoc_bimc_0_mas, 8, 3, -1, msm8916_snoc_bimc_0_slv); +define_qnode(snoc_bimc_0_slv, msm8916_snoc_bimc_0_slv, 8, -1, 24, msm8916_slave_ebi_ch0); +define_qnode(snoc_bimc_1_mas, msm8916_snoc_bimc_1_mas, 16, -1, -1, msm8916_snoc_bimc_1_slv); +define_qnode(snoc_bimc_1_slv, msm8916_snoc_bimc_1_slv, 8, -1, -1, msm8916_slave_ebi_ch0); +define_qnode(snoc_int_0, msm8916_snoc_int_0, 8, 99, 130, msm8916_slave_qdss_stm, msm8916_slave_imem, msm8916_snoc_pnoc_mas); +define_qnode(snoc_int_1, msm8916_snoc_int_1, 8, 100, 131, msm8916_slave_apss, msm8916_slave_cats_128, msm8916_slave_ocmem_64); +define_qnode(snoc_int_bimc, msm8916_snoc_int_bimc, 8, 101, 132, msm8916_snoc_bimc_0_mas); +define_qnode(snoc_pcnoc_mas, msm8916_snoc_pnoc_mas, 8, -1, -1, msm8916_snoc_pnoc_slv); +define_qnode(snoc_pcnoc_slv, msm8916_snoc_pnoc_slv, 8, -1, -1, msm8916_pnoc_int_0); + +static struct msm8916_icc_node *msm8916_snoc_nodes[] = { + [bimc_snoc_slv] = &bimc_snoc_slv, + [master_jpeg] = &mas_jpeg, + [master_mdp_port0] = &mas_mdp, + [master_qdss_bam] = &mas_qdss_bam, + [master_qdss_etr] = &mas_qdss_etr, + [master_snoc_cfg] = &mas_snoc_cfg, + [master_vfe] = &mas_vfe, + [master_video_p0] = &mas_video, + [snoc_mm_int_0] = &mm_int_0, + [snoc_mm_int_1] = &mm_int_1, + [snoc_mm_int_2] = &mm_int_2, + [snoc_mm_int_bimc] = &mm_int_bimc, + [pcnoc_snoc_slv] = &pcnoc_snoc_slv, + [slave_apss] = &slv_apss, + [slave_cats_128] = &slv_cats_0, + [slave_ocmem_64] = &slv_cats_1, + [slave_imem] = &slv_imem, + [slave_qdss_stm] = &slv_qdss_stm, + [slave_srvc_snoc] = &slv_srvc_snoc, + [snoc_bimc_0_mas] = &snoc_bimc_0_mas, + [snoc_bimc_1_mas] = &snoc_bimc_1_mas, + [snoc_int_0] = &snoc_int_0, + [snoc_int_1] = &snoc_int_1, + [snoc_int_bimc] = &snoc_int_bimc, + [snoc_pcnoc_mas] = &snoc_pcnoc_mas, + [snoc_qdss_int] = &qdss_int, +}; + +static struct msm8916_icc_desc msm8916_snoc = { + .nodes = msm8916_snoc_nodes, + .num_nodes = array_size(msm8916_snoc_nodes), +}; + +static struct msm8916_icc_node *msm8916_bimc_nodes[] = { + [bimc_snoc_mas] = &bimc_snoc_mas, + [master_ampss_m0] = &mas_apss, + [master_graphics_3d] = &mas_gfx, + [master_tcu0] = &mas_tcu0, + [master_tcu1] = &mas_tcu1, + [slave_ampss_l2] = &slv_apps_l2, + [slave_ebi_ch0] = &slv_ebi_ch0, + [snoc_bimc_0_slv] = &snoc_bimc_0_slv, + [snoc_bimc_1_slv] = &snoc_bimc_1_slv, +}; + +static struct msm8916_icc_desc msm8916_bimc = { + .nodes = msm8916_bimc_nodes, + .num_nodes = array_size(msm8916_bimc_nodes), +}; + +static struct msm8916_icc_node *msm8916_pcnoc_nodes[] = { + [master_blsp_1] = &mas_blsp_1, + [master_dehr] = &mas_dehr, + [master_lpass] = &mas_audio, + [master_crypto_core0] = &mas_pcnoc_crypto_0, + [master_sdcc_1] = &mas_pcnoc_sdcc_1, + [master_sdcc_2] = &mas_pcnoc_sdcc_2, + [master_spdm] = &mas_spdm, + [master_usb_hs] = &mas_usb_hs, + [pcnoc_int_0] = &pcnoc_int_0, + [pcnoc_int_1] = &pcnoc_int_1, + [pcnoc_mas_0] = &pcnoc_m_0, + [pcnoc_mas_1] = &pcnoc_m_1, + [pcnoc_slv_0] = &pcnoc_s_0, + [pcnoc_slv_1] = &pcnoc_s_1, + [pcnoc_slv_2] = &pcnoc_s_2, + [pcnoc_slv_3] = &pcnoc_s_3, + [pcnoc_slv_4] = &pcnoc_s_4, + [pcnoc_slv_8] = &pcnoc_s_8, + [pcnoc_slv_9] = &pcnoc_s_9, + [pcnoc_snoc_mas] = &pcnoc_snoc_mas, + [slave_bimc_cfg] = &slv_bimc_cfg, + [slave_blsp_1] = &slv_blsp_1, + [slave_boot_rom] = &slv_boot_rom, + [slave_camera_cfg] = &slv_camera_cfg, + [slave_clk_ctl] = &slv_clk_ctl, + [slave_crypto_0_cfg] = &slv_crypto_0_cfg, + [slave_dehr_cfg] = &slv_dehr_cfg, + [slave_display_cfg] = &slv_display_cfg, + [slave_graphics_3d_cfg] = &slv_gfx_cfg, + [slave_imem_cfg] = &slv_imem_cfg, + [slave_lpass] = &slv_audio, + [slave_mpm] = &slv_mpm, + [slave_msg_ram] = &slv_msg_ram, + [slave_mss] = &slv_mss, + [slave_pdm] = &slv_pdm, + [slave_pmic_arb] = &slv_pmic_arb, + [slave_pcnoc_cfg] = &slv_pcnoc_cfg, + [slave_prng] = &slv_prng, + [slave_qdss_cfg] = &slv_qdss_cfg, + [slave_rbcpr_cfg] = &slv_rbcpr_cfg, + [slave_sdcc_1] = &slv_sdcc_1, + [slave_sdcc_2] = &slv_sdcc_2, + [slave_security] = &slv_security, + [slave_snoc_cfg] = &slv_snoc_cfg, + [slave_spdm] = &slv_spdm, + [slave_tcsr] = &slv_tcsr, + [slave_tlmm] = &slv_tlmm, + [slave_usb_hs] = &slv_usb_hs, + [slave_venus_cfg] = &slv_venus_cfg, + [snoc_pcnoc_slv] = &snoc_pcnoc_slv, +}; + +static struct msm8916_icc_desc msm8916_pcnoc = { + .nodes = msm8916_pcnoc_nodes, + .num_nodes = array_size(msm8916_pcnoc_nodes), +}; + +static int msm8916_icc_set(struct icc_node *src, struct icc_node *dst) +{ + struct msm8916_icc_provider *qp; + struct msm8916_icc_node *qn; + u64 sum_bw, max_peak_bw, rate; + u32 agg_avg = 0, agg_peak = 0; + struct icc_provider *provider; + struct icc_node *n; + int ret, i; + + qn = src->data; + provider = src->provider; + qp = to_msm8916_provider(provider); + + list_for_each_entry(n, &provider->nodes, node_list) + provider->aggregate(n, 0, n->avg_bw, n->peak_bw, + &agg_avg, &agg_peak); + + sum_bw = icc_units_to_bps(agg_avg); + max_peak_bw = icc_units_to_bps(agg_peak); + + /* send bandwidth request message to the rpm processor */ + if (qn->mas_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(qcom_smd_rpm_active_state, + rpm_bus_master_req, + qn->mas_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send mas %d error %d ", + qn->mas_rpm_id, ret); + return ret; + } + } + + if (qn->slv_rpm_id != -1) { + ret = qcom_icc_rpm_smd_send(qcom_smd_rpm_active_state, + rpm_bus_slave_req, + qn->slv_rpm_id, + sum_bw); + if (ret) { + pr_err("qcom_icc_rpm_smd_send slv error %d ", + ret); + return ret; + } + } + + rate = max(sum_bw, max_peak_bw); + + do_div(rate, qn->buswidth); + + if (qn->rate == rate) + return 0; + + for (i = 0; i < qp->num_clks; i++) { + ret = clk_set_rate(qp->bus_clks[i].clk, rate); + if (ret) { + pr_err("%s clk_set_rate error: %d ", + qp->bus_clks[i].id, ret); + return ret; + } + } + + qn->rate = rate; + + return 0; +} + +static int msm8916_qnoc_probe(struct platform_device *pdev) +{ + const struct msm8916_icc_desc *desc; + struct msm8916_icc_node **qnodes; + struct msm8916_icc_provider *qp; + struct device *dev = &pdev->dev; + struct icc_onecell_data *data; + struct icc_provider *provider; + struct icc_node *node; + size_t num_nodes, i; + int ret; + + /* wait for the rpm proxy */ + if (!qcom_icc_rpm_smd_available()) + return -eprobe_defer; + + desc = of_device_get_match_data(dev); + if (!desc) + return -einval; + + qnodes = desc->nodes; + num_nodes = desc->num_nodes; + + qp = devm_kzalloc(dev, sizeof(*qp), gfp_kernel); + if (!qp) + return -enomem; + + data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes), + gfp_kernel); + if (!data) + return -enomem; + + qp->bus_clks = devm_kmemdup(dev, msm8916_bus_clocks, + sizeof(msm8916_bus_clocks), gfp_kernel); + if (!qp->bus_clks) + return -enomem; + + qp->num_clks = array_size(msm8916_bus_clocks); + ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks); + if (ret) + return ret; + + provider = &qp->provider; + init_list_head(&provider->nodes); + provider->dev = dev; + provider->set = msm8916_icc_set; + provider->aggregate = icc_std_aggregate; + provider->xlate = of_icc_xlate_onecell; + provider->data = data; + + ret = icc_provider_add(provider); + if (ret) { + dev_err(dev, "error adding interconnect provider: %d ", ret); + clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); + return ret; + } + + for (i = 0; i < num_nodes; i++) { + size_t j; + + node = icc_node_create(qnodes[i]->id); + if (is_err(node)) { + ret = ptr_err(node); + goto err; + } + + node->name = qnodes[i]->name; + node->data = qnodes[i]; + icc_node_add(node, provider); + + for (j = 0; j < qnodes[i]->num_links; j++) + icc_link_create(node, qnodes[i]->links[j]); + + data->nodes[i] = node; + } + data->num_nodes = num_nodes; + + platform_set_drvdata(pdev, qp); + + return 0; + +err: + icc_nodes_remove(provider); + icc_provider_del(provider); + clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); + + return ret; +} + +static int msm8916_qnoc_remove(struct platform_device *pdev) +{ + struct msm8916_icc_provider *qp = platform_get_drvdata(pdev); + + icc_nodes_remove(&qp->provider); + clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks); + return icc_provider_del(&qp->provider); +} + +static const struct of_device_id msm8916_noc_of_match[] = { + { .compatible = "qcom,msm8916-bimc", .data = &msm8916_bimc }, + { .compatible = "qcom,msm8916-pcnoc", .data = &msm8916_pcnoc }, + { .compatible = "qcom,msm8916-snoc", .data = &msm8916_snoc }, + { } +}; +module_device_table(of, msm8916_noc_of_match); + +static struct platform_driver msm8916_noc_driver = { + .probe = msm8916_qnoc_probe, + .remove = msm8916_qnoc_remove, + .driver = { + .name = "qnoc-msm8916", + .of_match_table = msm8916_noc_of_match, + }, +}; +module_platform_driver(msm8916_noc_driver); +module_author("georgi djakov <georgi.djakov@linaro.org>"); +module_description("qualcomm msm8916 noc driver"); +module_license("gpl v2"); | Various | 30c8fa3ec61a46da80698e1f8ab95df4d42bf374 | georgi djakov evan green evgreen chromium org | drivers | interconnect | qcom |
iommu/arm-smmu-v3: add support for substream ids | at the moment, the smmuv3 driver implements only one stage-1 or stage-2 page directory per device. however smmuv3 allows more than one address space for some devices, by providing multiple stage-1 page directories. in addition to the stream id (sid), that identifies a device, we can now have substream ids (ssid) identifying an address space. in pcie, sid is called requester id (rid) and ssid is called process address-space id (pasid). a complete stage-1 walk goes through the context descriptor table: | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for substream ids | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['iommu/arm-smmu-v3'] | ['c'] | 1 | 111 | 22 | +--------+ ,------->+-------+ ,------->+-------+ +--------+ | +-------+ | +-------+ +--------+ +-------+ +-------+ +--------+ +-------+ +-------+ --- diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c --- a/drivers/iommu/arm-smmu-v3.c +++ b/drivers/iommu/arm-smmu-v3.c +#define strtab_ste_1_s1dss genmask_ull(1, 0) +#define strtab_ste_1_s1dss_terminate 0x0 +#define strtab_ste_1_s1dss_bypass 0x1 +#define strtab_ste_1_s1dss_ssid0 0x2 + +#define cmdq_cfgi_0_ssid genmask_ull(31, 12) + #define cmdq_op_cfgi_cd 0x5 + #define cmdq_op_cfgi_cd_all 0x6 + u32 ssid; + u8 s1fmt; + case cmdq_op_cfgi_cd: + cmd[0] |= field_prep(cmdq_cfgi_0_ssid, ent->cfgi.ssid); + /* fallthrough */ + case cmdq_op_cfgi_cd_all: + cmd[0] |= field_prep(cmdq_cfgi_0_sid, ent->cfgi.sid); + break; -static void arm_smmu_write_ctx_desc(struct arm_smmu_device *smmu, - struct arm_smmu_s1_cfg *cfg) +static void arm_smmu_sync_cd(struct arm_smmu_domain *smmu_domain, + int ssid, bool leaf) - u64 val; - __le64 *cdptr = cfg->cdcfg.cdtab; + size_t i; + unsigned long flags; + struct arm_smmu_master *master; + struct arm_smmu_device *smmu = smmu_domain->smmu; + struct arm_smmu_cmdq_ent cmd = { + .opcode = cmdq_op_cfgi_cd, + .cfgi = { + .ssid = ssid, + .leaf = leaf, + }, + }; + + spin_lock_irqsave(&smmu_domain->devices_lock, flags); + list_for_each_entry(master, &smmu_domain->devices, domain_head) { + for (i = 0; i < master->num_sids; i++) { + cmd.cfgi.sid = master->sids[i]; + arm_smmu_cmdq_issue_cmd(smmu, &cmd); + } + } + spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); + + arm_smmu_cmdq_issue_sync(smmu); +} +static int arm_smmu_write_ctx_desc(struct arm_smmu_domain *smmu_domain, + int ssid, struct arm_smmu_ctx_desc *cd) +{ - * we don't need to issue any invalidation here, as we'll invalidate - * the ste when installing the new entry anyway. + * this function handles the following cases: + * + * (1) install primary cd, for normal dma traffic (ssid = 0). + * (2) install a secondary cd, for sid+ssid traffic. + * (3) update asid of a cd. atomically write the first 64 bits of the + * cd, then invalidate the old entry and mappings. + * (4) remove a secondary cd. - val = cfg->cd.tcr | -#ifdef __big_endian - ctxdesc_cd_0_endi | -#endif - ctxdesc_cd_0_r | ctxdesc_cd_0_a | ctxdesc_cd_0_aset | - ctxdesc_cd_0_aa64 | field_prep(ctxdesc_cd_0_asid, cfg->cd.asid) | - ctxdesc_cd_0_v; + u64 val; + bool cd_live; + struct arm_smmu_device *smmu = smmu_domain->smmu; + __le64 *cdptr = smmu_domain->s1_cfg.cdcfg.cdtab + ssid * + ctxdesc_cd_dwords; - /* stall_model==0b10 && cd.s==0 is illegal */ - if (smmu->features & arm_smmu_feat_stall_force) - val |= ctxdesc_cd_0_s; + val = le64_to_cpu(cdptr[0]); + cd_live = !!(val & ctxdesc_cd_0_v); - cdptr[0] = cpu_to_le64(val); + if (!cd) { /* (4) */ + val = 0; + } else if (cd_live) { /* (3) */ + val &= ~ctxdesc_cd_0_asid; + val |= field_prep(ctxdesc_cd_0_asid, cd->asid); + /* + * until cd+tlb invalidation, both asids may be used for tagging + * this substream's traffic + */ + } else { /* (1) and (2) */ + cdptr[1] = cpu_to_le64(cd->ttbr & ctxdesc_cd_1_ttb0_mask); + cdptr[2] = 0; + cdptr[3] = cpu_to_le64(cd->mair); - val = cfg->cd.ttbr & ctxdesc_cd_1_ttb0_mask; - cdptr[1] = cpu_to_le64(val); + /* + * ste is live, and the smmu might read dwords of this cd in any + * order. ensure that it observes valid values before reading + * v=1. + */ + arm_smmu_sync_cd(smmu_domain, ssid, true); - cdptr[3] = cpu_to_le64(cfg->cd.mair); + val = cd->tcr | +#ifdef __big_endian + ctxdesc_cd_0_endi | +#endif + ctxdesc_cd_0_r | ctxdesc_cd_0_a | ctxdesc_cd_0_aset | + ctxdesc_cd_0_aa64 | + field_prep(ctxdesc_cd_0_asid, cd->asid) | + ctxdesc_cd_0_v; + + /* stall_model==0b10 && cd.s==0 is illegal */ + if (smmu->features & arm_smmu_feat_stall_force) + val |= ctxdesc_cd_0_s; + } + + /* + * the smmu accesses 64-bit values atomically. see ihi0070ca 3.21.3 + * "configuration structures and configuration invalidation completion" + * + * the size of single-copy atomic reads made by the smmu is + * implementation defined but must be at least 64 bits. any single + * field within an aligned 64-bit span of a structure can be altered + * without first making the structure invalid. + */ + write_once(cdptr[0], cpu_to_le64(val)); + arm_smmu_sync_cd(smmu_domain, ssid, true); + return 0; + cfg->s1fmt = strtab_ste_0_s1fmt_linear; + + field_prep(strtab_ste_1_s1dss, strtab_ste_1_s1dss_ssid0) | - field_prep(strtab_ste_0_cfg, strtab_ste_0_cfg_s1_trans); + field_prep(strtab_ste_0_cfg, strtab_ste_0_cfg_s1_trans) | + field_prep(strtab_ste_0_s1cdmax, s1_cfg->s1cdmax) | + field_prep(strtab_ste_0_s1fmt, s1_cfg->s1fmt); - arm_smmu_write_ctx_desc(smmu, &smmu_domain->s1_cfg); + arm_smmu_write_ctx_desc(smmu_domain, 0, + &smmu_domain->s1_cfg.cd); | Various | 87f42391f6a57c252453aff2005fe2ec74f6873b | jean philippe brucker | drivers | iommu | |
iommu/vt-d: add kconfig option to enable/disable scalable mode | this adds kconfig option intel_iommu_scalable_mode_default_on to make it easier for distributions to enable or disable the intel iommu scalable mode by default during kernel build. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add kconfig option to enable/disable scalable mode | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['iommu/vt-d'] | ['c', 'kconfig'] | 2 | 18 | 1 | --- diff --git a/drivers/iommu/kconfig b/drivers/iommu/kconfig --- a/drivers/iommu/kconfig +++ b/drivers/iommu/kconfig +config intel_iommu_scalable_mode_default_on + bool "enable intel iommu scalable mode by default" + depends on intel_iommu + help + selecting this option will enable by default the scalable mode if + hardware presents the capability. the scalable mode is defined in + vt-d 3.0. the scalable mode capability could be checked by reading + /sys/devices/virtual/iommu/dmar*/intel-iommu/ecap. if this option + is not selected, scalable mode support could also be enabled by + passing intel_iommu=sm_on to the kernel. if not sure, please use + the default value. + diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c -#endif /*config_intel_iommu_default_on*/ +#endif /* config_intel_iommu_default_on */ +#ifdef intel_iommu_scalable_mode_default_on +int intel_iommu_sm = 1; +#else +#endif /* intel_iommu_scalable_mode_default_on */ + | Various | 046182525db611964da0db113dde9d3a2969085c | lu baolu | drivers | iommu | |
iommu/vt-d: debugfs: add support to show page table internals | export page table internals of the domain attached to each device. example of such dump on a skylake machine: | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support to show page table internals | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['iommu/vt-d', 'debugfs'] | ['c', 'h'] | 3 | 79 | 2 | --- diff --git a/drivers/iommu/intel-iommu-debugfs.c b/drivers/iommu/intel-iommu-debugfs.c --- a/drivers/iommu/intel-iommu-debugfs.c +++ b/drivers/iommu/intel-iommu-debugfs.c + * lu baolu <baolu.lu@linux.intel.com> +static inline unsigned long level_to_directory_size(int level) +{ + return bit_ull(vtd_page_shift + vtd_stride_shift * (level - 1)); +} + +static inline void +dump_page_info(struct seq_file *m, unsigned long iova, u64 *path) +{ + seq_printf(m, "0x%013lx | 0x%016llx 0x%016llx 0x%016llx 0x%016llx 0x%016llx ", + iova >> vtd_page_shift, path[5], path[4], + path[3], path[2], path[1]); +} + +static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde, + int level, unsigned long start, + u64 *path) +{ + int i; + + if (level > 5 || level < 1) + return; + + for (i = 0; i < bit_ull(vtd_stride_shift); + i++, pde++, start += level_to_directory_size(level)) { + if (!dma_pte_present(pde)) + continue; + + path[level] = pde->val; + if (dma_pte_superpage(pde) || level == 1) + dump_page_info(m, start, path); + else + pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)), + level - 1, start, path); + path[level] = 0; + } +} + +static int show_device_domain_translation(struct device *dev, void *data) +{ + struct dmar_domain *domain = find_domain(dev); + struct seq_file *m = data; + u64 path[6] = { 0 }; + + if (!domain) + return 0; + + seq_printf(m, "device %s with pasid %d @0x%llx ", + dev_name(dev), domain->default_pasid, + (u64)virt_to_phys(domain->pgd)); + seq_puts(m, "iova_pfn pml5e pml4e pdpe pde pte "); + + pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path); + seq_putc(m, ' '); + + return 0; +} + +static int domain_translation_struct_show(struct seq_file *m, void *unused) +{ + unsigned long flags; + int ret; + + spin_lock_irqsave(&device_domain_lock, flags); + ret = bus_for_each_dev(&pci_bus_type, null, m, + show_device_domain_translation); + spin_unlock_irqrestore(&device_domain_lock, flags); + + return ret; +} +define_show_attribute(domain_translation_struct); + + debugfs_create_file("domain_translation_struct", 0444, + intel_iommu_debug, null, + &domain_translation_struct_fops); diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c --- a/drivers/iommu/intel-iommu.c +++ b/drivers/iommu/intel-iommu.c -static define_spinlock(device_domain_lock); +define_spinlock(device_domain_lock); -static struct dmar_domain *find_domain(struct device *dev) +struct dmar_domain *find_domain(struct device *dev) diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h +extern spinlock_t device_domain_lock; +struct dmar_domain *find_domain(struct device *dev); | Various | e2726daea583d81e447b71e09b79e67f618d6152 | lu baolu | include | linux | |
irqchip/gic-v4.1: implement the v4.1 flavour of vmapp | the its vmapp command gains some new fields with gicv4.1: - a default doorbell, which allows a single doorbell to be used for all the vlpis routed to a given vpe - a pointer to the configuration table (instead of having it in a register that gets context switched) - a flag indicating whether this is the first map or the last unmap for this particular vpe - a flag indicating whether the pending table is known to be zeroed, or not | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | implement the v4.1 flavour of vmapp | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['irqchip/gic-v4.1'] | ['c', 'h'] | 2 | 69 | 9 | - a default doorbell, which allows a single doorbell to be used for - a pointer to the configuration table (instead of having it in a register - a flag indicating whether this is the first map or the last unmap for - a flag indicating whether the pending table is known to be zeroed, or not --- diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c +static void its_encode_vconf_addr(struct its_cmd_block *cmd, u64 vconf_pa) +{ + its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); +} + +static void its_encode_alloc(struct its_cmd_block *cmd, bool alloc) +{ + its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); +} + +static void its_encode_ptz(struct its_cmd_block *cmd, bool ptz) +{ + its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); +} + +static void its_encode_vmapp_default_db(struct its_cmd_block *cmd, + u32 vpe_db_lpi) +{ + its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); +} + - unsigned long vpt_addr; + unsigned long vpt_addr, vconf_addr; - - vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); - target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; + bool alloc; + + if (!desc->its_vmapp_cmd.valid) { + if (is_v4_1(its)) { + alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); + its_encode_alloc(cmd, alloc); + } + + goto out; + } + + vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); + target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; + + if (!is_v4_1(its)) + goto out; + + vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); + + alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); + + its_encode_alloc(cmd, alloc); + + /* we can only signal ptz when alloc==1. why do we have two bits? */ + its_encode_ptz(cmd, alloc); + its_encode_vconf_addr(cmd, vconf_addr); + its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); + +out: - vpe->vpe_proxy_event = -1; + if (gic_rdists->has_rvpeid) + atomic_set(&vpe->vmapp_count, 0); + else + vpe->vpe_proxy_event = -1; diff --git a/include/linux/irqchip/arm-gic-v4.h b/include/linux/irqchip/arm-gic-v4.h --- a/include/linux/irqchip/arm-gic-v4.h +++ b/include/linux/irqchip/arm-gic-v4.h - /* vpe proxy mapping */ - int vpe_proxy_event; + union { + /* gicv4.0 implementations */ + struct { + /* vpe proxy mapping */ + int vpe_proxy_event; + /* implementation defined area invalid */ + bool idai; + }; + /* gicv4.1 implementations */ + struct { + atomic_t vmapp_count; + }; + }; + - /* implementation defined area invalid */ - bool idai; | Various | 64edfaa9a2342a3ce34f8cb982c2c2df84db4de3 | marc zyngier | include | linux | irqchip |
irqchip/meson-gpio: add support for meson a1 socs | the meson a1 socs have some changes compared with previous chips. for a113l, it contains 62 pins and can be spied on: | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for meson a1 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['irqchip/meson-gpio'] | ['c'] | 1 | 42 | 0 | - 62:128 undefined - 61:50 12 pins on bank a - 49:37 13 pins on bank f - 36:20 17 pins on bank x - 19:13 7 pins on bank b - 12:0 13 pins on bank p - padctrl_gpio_irq_ctrl0 - padctrl_gpio_irq_ctrl[x] --- diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c --- a/drivers/irqchip/irq-meson-gpio.c +++ b/drivers/irqchip/irq-meson-gpio.c +/* use for a1 like chips */ +#define reg_pin_a1_sel 0x04 + +static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, + unsigned int channel, + unsigned long hwirq); +static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl); +#define init_meson_a1_common_data(irqs) \ + init_meson_common(irqs, meson_a1_gpio_irq_init, \ + meson_a1_gpio_irq_sel_pin) \ + .support_edge_both = true, \ + .edge_both_offset = 16, \ + .edge_single_offset = 8, \ + .pol_low_offset = 0, \ + .pin_sel_mask = 0x7f, \ + +static const struct meson_gpio_irq_params a1_params = { + init_meson_a1_common_data(62) +}; + + { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params }, +static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl, + unsigned int channel, + unsigned long hwirq) +{ + unsigned int reg_offset; + unsigned int bit_offset; + + bit_offset = ((channel % 2) == 0) ? 0 : 16; + reg_offset = reg_pin_a1_sel + ((channel / 2) << 2); + + meson_gpio_irq_update_bits(ctl, reg_offset, + ctl->params->pin_sel_mask << bit_offset, + hwirq << bit_offset); +} + +/* for a1 or later chips like a1 there is a switch to enable/disable irq */ +static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl) +{ + meson_gpio_irq_update_bits(ctl, reg_edge_pol, bit(31), bit(31)); +} + | Various | 8f78bd62bdd7a7b0a9906c4827245bf17056f781 | qianggui song | drivers | irqchip | |
irqchip: add aspeed scu interrupt controller | the aspeed socs provide some interrupts through the system control unit registers. add an interrupt controller that provides these interrupts to the system. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add aspeed scu interrupt controller | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['irqchip'] | ['c', 'makefile', 'maintainers'] | 3 | 241 | 1 | --- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +f: drivers/irqchip/irq-aspeed-scu-ic.c diff --git a/drivers/irqchip/makefile b/drivers/irqchip/makefile --- a/drivers/irqchip/makefile +++ b/drivers/irqchip/makefile -obj-$(config_arch_aspeed) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o +obj-$(config_arch_aspeed) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c --- /dev/null +++ b/drivers/irqchip/irq-aspeed-scu-ic.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * aspeed ast24xx, ast25xx, and ast26xx scu interrupt controller + * copyright 2019 ibm corporation + * + * eddie james <eajames@linux.ibm.com> + */ + +#include <linux/bitops.h> +#include <linux/irq.h> +#include <linux/irqchip.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/irqdomain.h> +#include <linux/mfd/syscon.h> +#include <linux/of_irq.h> +#include <linux/regmap.h> + +#define aspeed_scu_ic_reg 0x018 +#define aspeed_scu_ic_shift 0 +#define aspeed_scu_ic_enable genmask(6, aspeed_scu_ic_shift) +#define aspeed_scu_ic_num_irqs 7 +#define aspeed_scu_ic_status_shift 16 + +#define aspeed_ast2600_scu_ic0_reg 0x560 +#define aspeed_ast2600_scu_ic0_shift 0 +#define aspeed_ast2600_scu_ic0_enable \ + genmask(5, aspeed_ast2600_scu_ic0_shift) +#define aspeed_ast2600_scu_ic0_num_irqs 6 + +#define aspeed_ast2600_scu_ic1_reg 0x570 +#define aspeed_ast2600_scu_ic1_shift 4 +#define aspeed_ast2600_scu_ic1_enable \ + genmask(5, aspeed_ast2600_scu_ic1_shift) +#define aspeed_ast2600_scu_ic1_num_irqs 2 + +struct aspeed_scu_ic { + unsigned long irq_enable; + unsigned long irq_shift; + unsigned int num_irqs; + unsigned int reg; + struct regmap *scu; + struct irq_domain *irq_domain; +}; + +static void aspeed_scu_ic_irq_handler(struct irq_desc *desc) +{ + unsigned int irq; + unsigned int sts; + unsigned long bit; + unsigned long enabled; + unsigned long max; + unsigned long status; + struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc); + struct irq_chip *chip = irq_desc_get_chip(desc); + unsigned int mask = scu_ic->irq_enable << aspeed_scu_ic_status_shift; + + chained_irq_enter(chip, desc); + + /* + * the scu ic has just one register to control its operation and read + * status. the interrupt enable bits occupy the lower 16 bits of the + * register, while the interrupt status bits occupy the upper 16 bits. + * the status bit for a given interrupt is always 16 bits shifted from + * the enable bit for the same interrupt. + * therefore, perform the irq operations in the enable bit space by + * shifting the status down to get the mapping and then back up to + * clear the bit. + */ + regmap_read(scu_ic->scu, scu_ic->reg, &sts); + enabled = sts & scu_ic->irq_enable; + status = (sts >> aspeed_scu_ic_status_shift) & enabled; + + bit = scu_ic->irq_shift; + max = scu_ic->num_irqs + bit; + + for_each_set_bit_from(bit, &status, max) { + irq = irq_find_mapping(scu_ic->irq_domain, + bit - scu_ic->irq_shift); + generic_handle_irq(irq); + + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, + bit(bit + aspeed_scu_ic_status_shift)); + } + + chained_irq_exit(chip, desc); +} + +static void aspeed_scu_ic_irq_mask(struct irq_data *data) +{ + struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data); + unsigned int mask = bit(data->hwirq + scu_ic->irq_shift) | + (scu_ic->irq_enable << aspeed_scu_ic_status_shift); + + /* + * status bits are cleared by writing 1. in order to prevent the mask + * operation from clearing the status bits, they should be under the + * mask and written with 0. + */ + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, 0); +} + +static void aspeed_scu_ic_irq_unmask(struct irq_data *data) +{ + struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data); + unsigned int bit = bit(data->hwirq + scu_ic->irq_shift); + unsigned int mask = bit | + (scu_ic->irq_enable << aspeed_scu_ic_status_shift); + + /* + * status bits are cleared by writing 1. in order to prevent the unmask + * operation from clearing the status bits, they should be under the + * mask and written with 0. + */ + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit); +} + +static int aspeed_scu_ic_irq_set_affinity(struct irq_data *data, + const struct cpumask *dest, + bool force) +{ + return -einval; +} + +static struct irq_chip aspeed_scu_ic_chip = { + .name = "aspeed-scu-ic", + .irq_mask = aspeed_scu_ic_irq_mask, + .irq_unmask = aspeed_scu_ic_irq_unmask, + .irq_set_affinity = aspeed_scu_ic_irq_set_affinity, +}; + +static int aspeed_scu_ic_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &aspeed_scu_ic_chip, handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops aspeed_scu_ic_domain_ops = { + .map = aspeed_scu_ic_map, +}; + +static int aspeed_scu_ic_of_init_common(struct aspeed_scu_ic *scu_ic, + struct device_node *node) +{ + int irq; + int rc = 0; + + if (!node->parent) { + rc = -enodev; + goto err; + } + + scu_ic->scu = syscon_node_to_regmap(node->parent); + if (is_err(scu_ic->scu)) { + rc = ptr_err(scu_ic->scu); + goto err; + } + + irq = irq_of_parse_and_map(node, 0); + if (irq < 0) { + rc = irq; + goto err; + } + + scu_ic->irq_domain = irq_domain_add_linear(node, scu_ic->num_irqs, + &aspeed_scu_ic_domain_ops, + scu_ic); + if (!scu_ic->irq_domain) { + rc = -enomem; + goto err; + } + + irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler, + scu_ic); + + return 0; + +err: + kfree(scu_ic); + + return rc; +} + +static int __init aspeed_scu_ic_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), gfp_kernel); + + if (!scu_ic) + return -enomem; + + scu_ic->irq_enable = aspeed_scu_ic_enable; + scu_ic->irq_shift = aspeed_scu_ic_shift; + scu_ic->num_irqs = aspeed_scu_ic_num_irqs; + scu_ic->reg = aspeed_scu_ic_reg; + + return aspeed_scu_ic_of_init_common(scu_ic, node); +} + +static int __init aspeed_ast2600_scu_ic0_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), gfp_kernel); + + if (!scu_ic) + return -enomem; + + scu_ic->irq_enable = aspeed_ast2600_scu_ic0_enable; + scu_ic->irq_shift = aspeed_ast2600_scu_ic0_shift; + scu_ic->num_irqs = aspeed_ast2600_scu_ic0_num_irqs; + scu_ic->reg = aspeed_ast2600_scu_ic0_reg; + + return aspeed_scu_ic_of_init_common(scu_ic, node); +} + +static int __init aspeed_ast2600_scu_ic1_of_init(struct device_node *node, + struct device_node *parent) +{ + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), gfp_kernel); + + if (!scu_ic) + return -enomem; + + scu_ic->irq_enable = aspeed_ast2600_scu_ic1_enable; + scu_ic->irq_shift = aspeed_ast2600_scu_ic1_shift; + scu_ic->num_irqs = aspeed_ast2600_scu_ic1_num_irqs; + scu_ic->reg = aspeed_ast2600_scu_ic1_reg; + + return aspeed_scu_ic_of_init_common(scu_ic, node); +} + +irqchip_declare(ast2400_scu_ic, "aspeed,ast2400-scu-ic", aspeed_scu_ic_of_init); +irqchip_declare(ast2500_scu_ic, "aspeed,ast2500-scu-ic", aspeed_scu_ic_of_init); +irqchip_declare(ast2600_scu_ic0, "aspeed,ast2600-scu-ic0", + aspeed_ast2600_scu_ic0_of_init); +irqchip_declare(ast2600_scu_ic1, "aspeed,ast2600-scu-ic1", + aspeed_ast2600_scu_ic1_of_init); | Various | 04f605906ff00c649751519ca73d3058372cdc78 | eddie james andrew jeffery andrew aj id au | drivers | irqchip | |
irqchip: add nxp intmux interrupt multiplexer support | the interrupt multiplexer (intmux) expands the number of peripherals that can interrupt the core: * the intmux has 8 channels that are assigned to 8 nvic interrupt slots. * each intmux channel can receive up to 32 interrupt sources and has 1 interrupt output. * the intmux routes the interrupt sources to the interrupt outputs. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add nxp intmux interrupt multiplexer support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['irqchip'] | ['c', 'kconfig', 'makefile'] | 3 | 316 | 0 | --- diff --git a/drivers/irqchip/kconfig b/drivers/irqchip/kconfig --- a/drivers/irqchip/kconfig +++ b/drivers/irqchip/kconfig +config imx_intmux + def_bool y if arch_mxc + select irq_domain + help + support for the i.mx intmux interrupt multiplexer. + diff --git a/drivers/irqchip/makefile b/drivers/irqchip/makefile --- a/drivers/irqchip/makefile +++ b/drivers/irqchip/makefile +obj-$(config_imx_intmux) += irq-imx-intmux.o diff --git a/drivers/irqchip/irq-imx-intmux.c b/drivers/irqchip/irq-imx-intmux.c --- /dev/null +++ b/drivers/irqchip/irq-imx-intmux.c +// spdx-license-identifier: gpl-2.0 +// copyright 2017 nxp + +/* intmux block diagram + * + * ________________ + * interrupt source # 0 +---->| | + * | | | + * interrupt source # 1 +++-->| | + * ... | | | channel # 0 |--------->interrupt out # 0 + * ... | | | | + * ... | | | | + * interrupt source # x-1 +++-->|________________| + * | | | + * | | | + * | | | ________________ + * +---->| | + * | | | | | + * | +-->| | + * | | | | channel # 1 |--------->interrupt out # 1 + * | | +>| | + * | | | | | + * | | | |________________| + * | | | + * | | | + * | | | ... + * | | | ... + * | | | + * | | | ________________ + * +---->| | + * | | | | + * +-->| | + * | | channel # n |--------->interrupt out # n + * +>| | + * | | + * |________________| + * + * + * n: interrupt channel instance number (n=7) + * x: interrupt source number for each channel (x=32) + * + * the intmux interrupt multiplexer has 8 channels, each channel receives 32 + * interrupt sources and generates 1 interrupt output. + * + */ + +#include <linux/clk.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqchip/chained_irq.h> +#include <linux/irqdomain.h> +#include <linux/kernel.h> +#include <linux/of_irq.h> +#include <linux/of_platform.h> +#include <linux/spinlock.h> + +#define chanier(n) (0x10 + (0x40 * n)) +#define chanipr(n) (0x20 + (0x40 * n)) + +#define chan_max_num 0x8 + +struct intmux_irqchip_data { + int chanidx; + int irq; + struct irq_domain *domain; +}; + +struct intmux_data { + raw_spinlock_t lock; + void __iomem *regs; + struct clk *ipg_clk; + int channum; + struct intmux_irqchip_data irqchip_data[]; +}; + +static void imx_intmux_irq_mask(struct irq_data *d) +{ + struct intmux_irqchip_data *irqchip_data = d->chip_data; + int idx = irqchip_data->chanidx; + struct intmux_data *data = container_of(irqchip_data, struct intmux_data, + irqchip_data[idx]); + unsigned long flags; + void __iomem *reg; + u32 val; + + raw_spin_lock_irqsave(&data->lock, flags); + reg = data->regs + chanier(idx); + val = readl_relaxed(reg); + /* disable the interrupt source of this channel */ + val &= ~bit(d->hwirq); + writel_relaxed(val, reg); + raw_spin_unlock_irqrestore(&data->lock, flags); +} + +static void imx_intmux_irq_unmask(struct irq_data *d) +{ + struct intmux_irqchip_data *irqchip_data = d->chip_data; + int idx = irqchip_data->chanidx; + struct intmux_data *data = container_of(irqchip_data, struct intmux_data, + irqchip_data[idx]); + unsigned long flags; + void __iomem *reg; + u32 val; + + raw_spin_lock_irqsave(&data->lock, flags); + reg = data->regs + chanier(idx); + val = readl_relaxed(reg); + /* enable the interrupt source of this channel */ + val |= bit(d->hwirq); + writel_relaxed(val, reg); + raw_spin_unlock_irqrestore(&data->lock, flags); +} + +static struct irq_chip imx_intmux_irq_chip = { + .name = "intmux", + .irq_mask = imx_intmux_irq_mask, + .irq_unmask = imx_intmux_irq_unmask, +}; + +static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_data(irq, h->host_data); + irq_set_chip_and_handler(irq, &imx_intmux_irq_chip, handle_level_irq); + + return 0; +} + +static int imx_intmux_irq_xlate(struct irq_domain *d, struct device_node *node, + const u32 *intspec, unsigned int intsize, + unsigned long *out_hwirq, unsigned int *out_type) +{ + struct intmux_irqchip_data *irqchip_data = d->host_data; + int idx = irqchip_data->chanidx; + struct intmux_data *data = container_of(irqchip_data, struct intmux_data, + irqchip_data[idx]); + + /* + * two cells needed in interrupt specifier: + * the 1st cell: hw interrupt number + * the 2nd cell: channel index + */ + if (warn_on(intsize != 2)) + return -einval; + + if (warn_on(intspec[1] >= data->channum)) + return -einval; + + *out_hwirq = intspec[0]; + *out_type = irq_type_level_high; + + return 0; +} + +static int imx_intmux_irq_select(struct irq_domain *d, struct irq_fwspec *fwspec, + enum irq_domain_bus_token bus_token) +{ + struct intmux_irqchip_data *irqchip_data = d->host_data; + + /* not for us */ + if (fwspec->fwnode != d->fwnode) + return false; + + return irqchip_data->chanidx == fwspec->param[1]; +} + +static const struct irq_domain_ops imx_intmux_domain_ops = { + .map = imx_intmux_irq_map, + .xlate = imx_intmux_irq_xlate, + .select = imx_intmux_irq_select, +}; + +static void imx_intmux_irq_handler(struct irq_desc *desc) +{ + struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc); + int idx = irqchip_data->chanidx; + struct intmux_data *data = container_of(irqchip_data, struct intmux_data, + irqchip_data[idx]); + unsigned long irqstat; + int pos, virq; + + chained_irq_enter(irq_desc_get_chip(desc), desc); + + /* read the interrupt source pending status of this channel */ + irqstat = readl_relaxed(data->regs + chanipr(idx)); + + for_each_set_bit(pos, &irqstat, 32) { + virq = irq_find_mapping(irqchip_data->domain, pos); + if (virq) + generic_handle_irq(virq); + } + + chained_irq_exit(irq_desc_get_chip(desc), desc); +} + +static int imx_intmux_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct irq_domain *domain; + struct intmux_data *data; + int channum; + int i, ret; + + channum = platform_irq_count(pdev); + if (channum == -eprobe_defer) { + return -eprobe_defer; + } else if (channum > chan_max_num) { + dev_err(&pdev->dev, "supports up to %d multiplex channels ", + chan_max_num); + return -einval; + } + + data = devm_kzalloc(&pdev->dev, sizeof(*data) + + channum * sizeof(data->irqchip_data[0]), gfp_kernel); + if (!data) + return -enomem; + + data->regs = devm_platform_ioremap_resource(pdev, 0); + if (is_err(data->regs)) { + dev_err(&pdev->dev, "failed to initialize reg "); + return ptr_err(data->regs); + } + + data->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); + if (is_err(data->ipg_clk)) { + ret = ptr_err(data->ipg_clk); + if (ret != -eprobe_defer) + dev_err(&pdev->dev, "failed to get ipg clk: %d ", ret); + return ret; + } + + data->channum = channum; + raw_spin_lock_init(&data->lock); + + ret = clk_prepare_enable(data->ipg_clk); + if (ret) { + dev_err(&pdev->dev, "failed to enable ipg clk: %d ", ret); + return ret; + } + + for (i = 0; i < channum; i++) { + data->irqchip_data[i].chanidx = i; + + data->irqchip_data[i].irq = irq_of_parse_and_map(np, i); + if (data->irqchip_data[i].irq <= 0) { + ret = -einval; + dev_err(&pdev->dev, "failed to get irq "); + goto out; + } + + domain = irq_domain_add_linear(np, 32, &imx_intmux_domain_ops, + &data->irqchip_data[i]); + if (!domain) { + ret = -enomem; + dev_err(&pdev->dev, "failed to create irq domain "); + goto out; + } + data->irqchip_data[i].domain = domain; + + /* disable all interrupt sources of this channel firstly */ + writel_relaxed(0, data->regs + chanier(i)); + + irq_set_chained_handler_and_data(data->irqchip_data[i].irq, + imx_intmux_irq_handler, + &data->irqchip_data[i]); + } + + platform_set_drvdata(pdev, data); + + return 0; +out: + clk_disable_unprepare(data->ipg_clk); + return ret; +} + +static int imx_intmux_remove(struct platform_device *pdev) +{ + struct intmux_data *data = platform_get_drvdata(pdev); + int i; + + for (i = 0; i < data->channum; i++) { + /* disable all interrupt sources of this channel */ + writel_relaxed(0, data->regs + chanier(i)); + + irq_set_chained_handler_and_data(data->irqchip_data[i].irq, + null, null); + + irq_domain_remove(data->irqchip_data[i].domain); + } + + clk_disable_unprepare(data->ipg_clk); + + return 0; +} + +static const struct of_device_id imx_intmux_id[] = { + { .compatible = "fsl,imx-intmux", }, + { /* sentinel */ }, +}; + +static struct platform_driver imx_intmux_driver = { + .driver = { + .name = "imx-intmux", + .of_match_table = imx_intmux_id, + }, + .probe = imx_intmux_probe, + .remove = imx_intmux_remove, +}; +builtin_platform_driver(imx_intmux_driver); | Various | 2fbb13961e741494992bae7bfaf7259b65769f9f | joakim zhang | drivers | irqchip | |
isdn: capi: dead code removal | the staging isdn drivers are gone, and config_bt_cmtp is now the only user. this means a lot of the code in the subsystem has no remaining callers and can be removed. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | dead code removal | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['isdn', 'capi'] | ['c', 'kconfig', 'rst', 'makefile', 'h'] | 14 | 179 | 1,606 | --- diff --git a/documentation/isdn/interface_capi.rst b/documentation/isdn/interface_capi.rst --- a/documentation/isdn/interface_capi.rst +++ b/documentation/isdn/interface_capi.rst -capi drivers optionally register themselves with kernel capi by calling the -kernel capi function register_capi_driver() with a pointer to a struct -capi_driver. this structure must be filled with the name and revision of the -driver, and optionally a pointer to a callback function, add_card(). the -registration can be revoked by calling the function unregister_capi_driver() -with a pointer to the same struct capi_driver. - -''int (*add_card)(struct capi_driver *driver, capicardparams *data)'' - a callback function pointer (may be null) - ------------------- -''const struct file_operations *proc_fops'' - pointers to callback functions for the device's proc file - system entry, /proc/capi/controllers/<n>; pointer to the device's - capi_ctr structure is available from struct proc_dir_entry::data - which is available from struct inode. - -functions capi_cmsg2message() and capi_message2cmsg() are provided to convert -messages between their transport encoding described in the capi 2.0 standard -and their _cmsg structure representation. note that capi_cmsg2message() does -not know or check the size of its destination buffer. the caller must make -sure it is big enough to accommodate the resulting capi message. - -(declared in <linux/isdn/capilli.h>) - -:: - - void register_capi_driver(struct capi_driver *drvr) - void unregister_capi_driver(struct capi_driver *drvr) - -register/unregister a driver with kernel capi - -:: - - void capi_ctr_suspend_output(struct capi_ctr *ctrlr) - void capi_ctr_resume_output(struct capi_ctr *ctrlr) - -signal suspend/resume - -library functions (from <linux/isdn/capilli.h>): - -:: - - void capilib_new_ncci(struct list_head *head, u16 applid, - u32 ncci, u32 winsize) - void capilib_free_ncci(struct list_head *head, u16 applid, u32 ncci) - void capilib_release_appl(struct list_head *head, u16 applid) - void capilib_release(struct list_head *head) - void capilib_data_b3_conf(struct list_head *head, u16 applid, - u32 ncci, u16 msgid) - u16 capilib_data_b3_req(struct list_head *head, u16 applid, - u32 ncci, u16 msgid) - - -''unsigned capi_cmsg2message(_cmsg *cmsg, u8 *msg)'' - assembles a capi 2.0 message from the parameters in ''*cmsg'', - storing the result in ''*msg''. - -''unsigned capi_message2cmsg(_cmsg *cmsg, u8 *msg)'' - disassembles the capi 2.0 message in ''*msg'', storing the parameters - in ''*cmsg''. - -''unsigned capi_cmsg_header(_cmsg *cmsg, u16 applid, u8 command, u8 subcommand, u16 messagenumber, u32 controller)'' - fills the header part and address field of the _cmsg structure ''*cmsg'' - with the given values, zeroing the remainder of the structure so only - parameters with non-default values need to be changed before sending - the message. - -''void capi_cmsg_answer(_cmsg *cmsg)'' - sets the low bit of the subcommand field in ''*cmsg'', thereby - converting ''_req'' to ''_conf'' and ''_ind'' to ''_resp''. - diff --git a/drivers/isdn/makefile b/drivers/isdn/makefile --- a/drivers/isdn/makefile +++ b/drivers/isdn/makefile -obj-$(config_isdn_capi) += capi/ +obj-$(config_bt_cmtp) += capi/ diff --git a/drivers/isdn/capi/kconfig b/drivers/isdn/capi/kconfig --- a/drivers/isdn/capi/kconfig +++ b/drivers/isdn/capi/kconfig -menuconfig isdn_capi - tristate "capi 2.0 subsystem" +config isdn_capi + def_bool isdn && bt -if isdn_capi - - bool "capi trace support" - default y + def_bool bt_cmtp - this will increase the size of the kernelcapi module by 20 kb. - if unsure, say y. - -config isdn_capi_capi20 - tristate "capi2.0 /dev/capi20 support" - help - this option will provide the capi 2.0 interface to userspace - applications via /dev/capi20. applications should use the - standardized libcapi20 to access this functionality. you should say - y/m here. - bool "capi2.0 middleware support" - depends on isdn_capi_capi20 && tty + def_bool bt_cmtp && tty - -config isdn_capi_capidrv_verbose - bool "verbose reason code reporting" - depends on isdn_capi_capidrv - help - if you say y here, the capidrv interface will give verbose reasons - for disconnecting. this will increase the size of the kernel by 7 kb. - if unsure, say n. - -endif diff --git a/drivers/isdn/capi/makefile b/drivers/isdn/capi/makefile --- a/drivers/isdn/capi/makefile +++ b/drivers/isdn/capi/makefile -# makefile for the capi subsystem. +# makefile for the capi subsystem used by bt_cmtp -# ordering constraints: kernelcapi.o first - -# each configuration option enables a list of files. - -obj-$(config_isdn_capi) += kernelcapi.o -obj-$(config_isdn_capi_capi20) += capi.o -obj-$(config_isdn_capi_capidrv) += capidrv.o - -# multipart objects. - -kernelcapi-y := kcapi.o capiutil.o capilib.o -kernelcapi-$(config_proc_fs) += kcapi_proc.o - -ccflags-y += -i$(srctree)/$(src)/../include -i$(srctree)/$(src)/../include/uapi +obj-$(config_bt_cmtp) += kernelcapi.o +kernelcapi-y := kcapi.o capiutil.o capi.o kcapi_proc.o diff --git a/drivers/isdn/capi/capi.c b/drivers/isdn/capi/capi.c --- a/drivers/isdn/capi/capi.c +++ b/drivers/isdn/capi/capi.c -module_description("capi4linux: userspace /dev/capi20 interface"); +#include "kcapi.h" + +module_description("capi4linux: kernel capi layer and /dev/capi20 interface"); + int ret; + + ret = kcapi_init(); + if (ret) + return ret; + kcapi_exit(); + kcapi_exit(); + kcapi_exit(); + + kcapi_exit(); diff --git a/drivers/isdn/capi/capilib.c b/drivers/isdn/capi/capilib.c --- a/drivers/isdn/capi/capilib.c +++ /dev/null -// spdx-license-identifier: gpl-2.0 - -#include <linux/slab.h> -#include <linux/kernel.h> -#include <linux/module.h> -#include <linux/isdn/capilli.h> - -#define dbg(format, arg...) do { \ - printk(kern_debug "%s: " format " " , __func__ , ## arg); \ - } while (0) - -struct capilib_msgidqueue { - struct capilib_msgidqueue *next; - u16 msgid; -}; - -struct capilib_ncci { - struct list_head list; - u16 applid; - u32 ncci; - u32 winsize; - int nmsg; - struct capilib_msgidqueue *msgidqueue; - struct capilib_msgidqueue *msgidlast; - struct capilib_msgidqueue *msgidfree; - struct capilib_msgidqueue msgidpool[capi_maxdatawindow]; -}; - -// --------------------------------------------------------------------------- -// ncci handling - -static inline void mq_init(struct capilib_ncci *np) -{ - u_int i; - np->msgidqueue = null; - np->msgidlast = null; - np->nmsg = 0; - memset(np->msgidpool, 0, sizeof(np->msgidpool)); - np->msgidfree = &np->msgidpool[0]; - for (i = 1; i < np->winsize; i++) { - np->msgidpool[i].next = np->msgidfree; - np->msgidfree = &np->msgidpool[i]; - } -} - -static inline int mq_enqueue(struct capilib_ncci *np, u16 msgid) -{ - struct capilib_msgidqueue *mq; - if ((mq = np->msgidfree) == null) - return 0; - np->msgidfree = mq->next; - mq->msgid = msgid; - mq->next = null; - if (np->msgidlast) - np->msgidlast->next = mq; - np->msgidlast = mq; - if (!np->msgidqueue) - np->msgidqueue = mq; - np->nmsg++; - return 1; -} - -static inline int mq_dequeue(struct capilib_ncci *np, u16 msgid) -{ - struct capilib_msgidqueue **pp; - for (pp = &np->msgidqueue; *pp; pp = &(*pp)->next) { - if ((*pp)->msgid == msgid) { - struct capilib_msgidqueue *mq = *pp; - *pp = mq->next; - if (mq == np->msgidlast) - np->msgidlast = null; - mq->next = np->msgidfree; - np->msgidfree = mq; - np->nmsg--; - return 1; - } - } - return 0; -} - -void capilib_new_ncci(struct list_head *head, u16 applid, u32 ncci, u32 winsize) -{ - struct capilib_ncci *np; - - np = kmalloc(sizeof(*np), gfp_atomic); - if (!np) { - printk(kern_warning "capilib_new_ncci: no memory. "); - return; - } - if (winsize > capi_maxdatawindow) { - printk(kern_err "capi_new_ncci: winsize %d too big ", - winsize); - winsize = capi_maxdatawindow; - } - np->applid = applid; - np->ncci = ncci; - np->winsize = winsize; - mq_init(np); - list_add_tail(&np->list, head); - dbg("kcapi: appl %d ncci 0x%x up", applid, ncci); -} - -export_symbol(capilib_new_ncci); - -void capilib_free_ncci(struct list_head *head, u16 applid, u32 ncci) -{ - struct list_head *l; - struct capilib_ncci *np; - - list_for_each(l, head) { - np = list_entry(l, struct capilib_ncci, list); - if (np->applid != applid) - continue; - if (np->ncci != ncci) - continue; - printk(kern_info "kcapi: appl %d ncci 0x%x down ", applid, ncci); - list_del(&np->list); - kfree(np); - return; - } - printk(kern_err "capilib_free_ncci: ncci 0x%x not found ", ncci); -} - -export_symbol(capilib_free_ncci); - -void capilib_release_appl(struct list_head *head, u16 applid) -{ - struct list_head *l, *n; - struct capilib_ncci *np; - - list_for_each_safe(l, n, head) { - np = list_entry(l, struct capilib_ncci, list); - if (np->applid != applid) - continue; - printk(kern_info "kcapi: appl %d ncci 0x%x forced down ", applid, np->ncci); - list_del(&np->list); - kfree(np); - } -} - -export_symbol(capilib_release_appl); - -void capilib_release(struct list_head *head) -{ - struct list_head *l, *n; - struct capilib_ncci *np; - - list_for_each_safe(l, n, head) { - np = list_entry(l, struct capilib_ncci, list); - printk(kern_info "kcapi: appl %d ncci 0x%x forced down ", np->applid, np->ncci); - list_del(&np->list); - kfree(np); - } -} - -export_symbol(capilib_release); - -u16 capilib_data_b3_req(struct list_head *head, u16 applid, u32 ncci, u16 msgid) -{ - struct list_head *l; - struct capilib_ncci *np; - - list_for_each(l, head) { - np = list_entry(l, struct capilib_ncci, list); - if (np->applid != applid) - continue; - if (np->ncci != ncci) - continue; - - if (mq_enqueue(np, msgid) == 0) - return capi_sendqueuefull; - - return capi_noerror; - } - printk(kern_err "capilib_data_b3_req: ncci 0x%x not found ", ncci); - return capi_noerror; -} - -export_symbol(capilib_data_b3_req); - -void capilib_data_b3_conf(struct list_head *head, u16 applid, u32 ncci, u16 msgid) -{ - struct list_head *l; - struct capilib_ncci *np; - - list_for_each(l, head) { - np = list_entry(l, struct capilib_ncci, list); - if (np->applid != applid) - continue; - if (np->ncci != ncci) - continue; - - if (mq_dequeue(np, msgid) == 0) { - printk(kern_err "kcapi: msgid %hu ncci 0x%x not on queue ", - msgid, ncci); - } - return; - } - printk(kern_err "capilib_data_b3_conf: ncci 0x%x not found ", ncci); -} - -export_symbol(capilib_data_b3_conf); diff --git a/drivers/isdn/capi/capiutil.c b/drivers/isdn/capi/capiutil.c --- a/drivers/isdn/capi/capiutil.c +++ b/drivers/isdn/capi/capiutil.c +#include "kcapi.h" + -/*-------------------------------------------------------*/ -static void pars_2_message(_cmsg *cmsg) -{ - - for (; typ != _cend; cmsg->p++) { - switch (typ) { - case _cbyte: - bytetlcpy(cmsg->m + cmsg->l, off); - cmsg->l++; - break; - case _cword: - wordtlcpy(cmsg->m + cmsg->l, off); - cmsg->l += 2; - break; - case _cdword: - dwordtlcpy(cmsg->m + cmsg->l, off); - cmsg->l += 4; - break; - case _cstruct: - if (*(u8 **) off == null) { - *(cmsg->m + cmsg->l) = ''; - cmsg->l++; - } else if (**(_cstruct *) off != 0xff) { - structtlcpy(cmsg->m + cmsg->l, *(_cstruct *) off, 1 + **(_cstruct *) off); - cmsg->l += 1 + **(_cstruct *) off; - } else { - _cstruct s = *(_cstruct *) off; - structtlcpy(cmsg->m + cmsg->l, s, 3 + *(u16 *) (s + 1)); - cmsg->l += 3 + *(u16 *) (s + 1); - } - break; - case _cmstruct: -/*----- metastruktur 0 -----*/ - if (*(_cmstruct *) off == capi_default) { - *(cmsg->m + cmsg->l) = ''; - cmsg->l++; - jumpcstruct(cmsg); - } -/*----- metastruktur wird composed -----*/ - else { - unsigned _l = cmsg->l; - unsigned _ls; - cmsg->l++; - cmsg->p++; - pars_2_message(cmsg); - _ls = cmsg->l - _l - 1; - if (_ls < 255) - (cmsg->m + _l)[0] = (u8) _ls; - else { - structtlcpyovl(cmsg->m + _l + 3, cmsg->m + _l + 1, _ls); - (cmsg->m + _l)[0] = 0xff; - wordtlcpy(cmsg->m + _l + 1, &_ls); - } - } - break; - } - } -} - -/** - * capi_cmsg2message() - assemble capi 2.0 message from _cmsg structure - * @cmsg: _cmsg structure - * @msg: buffer for assembled message - * - * return value: 0 for success - */ - -unsigned capi_cmsg2message(_cmsg *cmsg, u8 *msg) -{ - cmsg->m = msg; - cmsg->l = 8; - cmsg->p = 0; - cmsg->par = capi_cmd2par(cmsg->command, cmsg->subcommand); - if (!cmsg->par) - return 1; /* invalid command/subcommand */ - - pars_2_message(cmsg); - - wordtlcpy(msg + 0, &cmsg->l); - bytetlcpy(cmsg->m + 4, &cmsg->command); - bytetlcpy(cmsg->m + 5, &cmsg->subcommand); - wordtlcpy(cmsg->m + 2, &cmsg->applid); - wordtlcpy(cmsg->m + 6, &cmsg->messagenumber); - - return 0; -} - -/*-------------------------------------------------------*/ -static void message_2_pars(_cmsg *cmsg) -{ - for (; typ != _cend; cmsg->p++) { - - switch (typ) { - case _cbyte: - bytetrcpy(cmsg->m + cmsg->l, off); - cmsg->l++; - break; - case _cword: - wordtrcpy(cmsg->m + cmsg->l, off); - cmsg->l += 2; - break; - case _cdword: - dwordtrcpy(cmsg->m + cmsg->l, off); - cmsg->l += 4; - break; - case _cstruct: - *(u8 **) off = cmsg->m + cmsg->l; - - if (cmsg->m[cmsg->l] != 0xff) - cmsg->l += 1 + cmsg->m[cmsg->l]; - else - cmsg->l += 3 + *(u16 *) (cmsg->m + cmsg->l + 1); - break; - case _cmstruct: -/*----- metastruktur 0 -----*/ - if (cmsg->m[cmsg->l] == '') { - *(_cmstruct *) off = capi_default; - cmsg->l++; - jumpcstruct(cmsg); - } else { - unsigned _l = cmsg->l; - *(_cmstruct *) off = capi_compose; - cmsg->l = (cmsg->m + _l)[0] == 255 ? cmsg->l + 3 : cmsg->l + 1; - cmsg->p++; - message_2_pars(cmsg); - } - break; - } - } -} - -/** - * capi_message2cmsg() - disassemble capi 2.0 message into _cmsg structure - * @cmsg: _cmsg structure - * @msg: buffer for assembled message - * - * return value: 0 for success - */ - -unsigned capi_message2cmsg(_cmsg *cmsg, u8 *msg) -{ - memset(cmsg, 0, sizeof(_cmsg)); - cmsg->m = msg; - cmsg->l = 8; - cmsg->p = 0; - bytetrcpy(cmsg->m + 4, &cmsg->command); - bytetrcpy(cmsg->m + 5, &cmsg->subcommand); - cmsg->par = capi_cmd2par(cmsg->command, cmsg->subcommand); - if (!cmsg->par) - return 1; /* invalid command/subcommand */ - - message_2_pars(cmsg); - - wordtrcpy(msg + 0, &cmsg->l); - wordtrcpy(cmsg->m + 2, &cmsg->applid); - wordtrcpy(cmsg->m + 6, &cmsg->messagenumber); - - return 0; -} - -/** - * capi_cmsg_header() - initialize header part of _cmsg structure - * @cmsg: _cmsg structure - * @_applid: applid field value - * @_command: command field value - * @_subcommand: subcommand field value - * @_messagenumber: message number field value - * @_controller: controller/plci/ncci field value - * - * return value: 0 for success - */ - -unsigned capi_cmsg_header(_cmsg *cmsg, u16 _applid, - u8 _command, u8 _subcommand, - u16 _messagenumber, u32 _controller) -{ - memset(cmsg, 0, sizeof(_cmsg)); - cmsg->applid = _applid; - cmsg->command = _command; - cmsg->subcommand = _subcommand; - cmsg->messagenumber = _messagenumber; - cmsg->adr.adrcontroller = _controller; - return 0; -} - - -/** - * capi_cmsg2str() - format _cmsg structure for printing - * @cmsg: _cmsg structure - * - * allocates a capi debug buffer and fills it with a printable representation - * of the capi 2.0 message stored in @cmsg by a previous call to - * capi_cmsg2message() or capi_message2cmsg(). - * return value: allocated debug buffer, null on error - * the returned buffer should be freed by a call to cdebbuf_free() after use. - */ - -_cdebbuf *capi_cmsg2str(_cmsg *cmsg) -{ - _cdebbuf *cdb; - - if (!cmsg->m) - return null; /* no message */ - cdb = cdebbuf_alloc(); - if (!cdb) - return null; - cmsg->l = 8; - cmsg->p = 0; - cdb = bufprint(cdb, "%s id=%03d #0x%04x len=%04d ", - capi_cmd2str(cmsg->command, cmsg->subcommand), - ((u16 *) cmsg->m)[1], - ((u16 *) cmsg->m)[3], - ((u16 *) cmsg->m)[0]); - cdb = protocol_message_2_pars(cdb, cmsg, 1); - return cdb; -} - -void __exit cdebug_exit(void) +void cdebug_exit(void) -void __exit cdebug_exit(void) +void cdebug_exit(void) - -export_symbol(cdebbuf_free); -export_symbol(capi_cmsg2message); -export_symbol(capi_message2cmsg); -export_symbol(capi_cmsg_header); -export_symbol(capi_cmd2str); -export_symbol(capi_cmsg2str); -export_symbol(capi_message2str); diff --git a/drivers/isdn/capi/kcapi.c b/drivers/isdn/capi/kcapi.c --- a/drivers/isdn/capi/kcapi.c +++ b/drivers/isdn/capi/kcapi.c -#define avmb1_compat - -#ifdef avmb1_compat -#include <linux/b1lli.h> -#endif -module_description("capi4linux: kernel capi layer"); -module_author("carsten paeth"); -module_license("gpl"); -list_head(capi_drivers); -define_mutex(capi_drivers_lock); - -static blocking_notifier_head(ctr_notifier_list); - - - wake_up_interruptible_all(&ctr->state_wait_queue); - - wake_up_interruptible_all(&ctr->state_wait_queue); -static int -notify_handler(struct notifier_block *nb, unsigned long val, void *v) +static void do_notify_work(struct work_struct *work) - u32 contr = (long)v; + struct capictr_event *event = + container_of(work, struct capictr_event, work); - switch (val) { + switch (event->type) { - notify_up(contr); + notify_up(event->controller); - notify_down(contr); + notify_down(event->controller); - return notify_ok; -} -static void do_notify_work(struct work_struct *work) -{ - struct capictr_event *event = - container_of(work, struct capictr_event, work); - - blocking_notifier_call_chain(&ctr_notifier_list, event->type, - (void *)(long)event->controller); -/* - * the notifier will result in adding/deleteing of devices. devices can - * only removed in user process, not in bh. - */ -int register_capictr_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_register(&ctr_notifier_list, nb); -} -export_symbol_gpl(register_capictr_notifier); - -int unregister_capictr_notifier(struct notifier_block *nb) -{ - return blocking_notifier_chain_unregister(&ctr_notifier_list, nb); -} -export_symbol_gpl(unregister_capictr_notifier); - -/** - * capi_ctr_suspend_output() - suspend controller - * @ctr: controller descriptor structure. - * - * called by hardware driver to stop data flow. - * - * note: the caller is responsible for synchronizing concurrent state changes - * as well as invocations of capi_ctr_handle_message. - */ - -void capi_ctr_suspend_output(struct capi_ctr *ctr) -{ - if (!ctr->blocked) { - printk(kern_debug "kcapi: controller [%03d] suspend ", - ctr->cnr); - ctr->blocked = 1; - } -} - -export_symbol(capi_ctr_suspend_output); - -/** - * capi_ctr_resume_output() - resume controller - * @ctr: controller descriptor structure. - * - * called by hardware driver to resume data flow. - * - * note: the caller is responsible for synchronizing concurrent state changes - * as well as invocations of capi_ctr_handle_message. - */ - -void capi_ctr_resume_output(struct capi_ctr *ctr) -{ - if (ctr->blocked) { - printk(kern_debug "kcapi: controller [%03d] resumed ", - ctr->cnr); - ctr->blocked = 0; - } -} - -export_symbol(capi_ctr_resume_output); - - init_waitqueue_head(&ctr->state_wait_queue); -/** - * register_capi_driver() - register capi driver - * @driver: driver descriptor structure. - * - * called by hardware driver to register itself with the capi subsystem. - */ - -void register_capi_driver(struct capi_driver *driver) -{ - mutex_lock(&capi_drivers_lock); - list_add_tail(&driver->list, &capi_drivers); - mutex_unlock(&capi_drivers_lock); -} - -export_symbol(register_capi_driver); - -/** - * unregister_capi_driver() - unregister capi driver - * @driver: driver descriptor structure. - * - * called by hardware driver to unregister itself from the capi subsystem. - */ - -void unregister_capi_driver(struct capi_driver *driver) -{ - mutex_lock(&capi_drivers_lock); - list_del(&driver->list); - mutex_unlock(&capi_drivers_lock); -} - -export_symbol(unregister_capi_driver); - -export_symbol(capi20_isinstalled); - -export_symbol(capi20_register); - -export_symbol(capi20_release); - -export_symbol(capi20_put_message); - -export_symbol(capi20_get_manufacturer); - -export_symbol(capi20_get_version); - -export_symbol(capi20_get_serial); - -export_symbol(capi20_get_profile); - -/* must be called with capi_controller_lock held. */ -static int wait_on_ctr_state(struct capi_ctr *ctr, unsigned int state) -{ - define_wait(wait); - int retval = 0; - - ctr = capi_ctr_get(ctr); - if (!ctr) - return -esrch; - - for (;;) { - prepare_to_wait(&ctr->state_wait_queue, &wait, - task_interruptible); - - if (ctr->state == state) - break; - if (ctr->state == capi_ctr_detached) { - retval = -esrch; - break; - } - if (signal_pending(current)) { - retval = -eintr; - break; - } - - mutex_unlock(&capi_controller_lock); - schedule(); - mutex_lock(&capi_controller_lock); - } - finish_wait(&ctr->state_wait_queue, &wait); - - capi_ctr_put(ctr); - - return retval; -} - -#ifdef avmb1_compat -static int old_capi_manufacturer(unsigned int cmd, void __user *data) -{ - avmb1_loadandconfigdef ldef; - avmb1_extcarddef cdef; - avmb1_resetdef rdef; - capicardparams cparams; - struct capi_ctr *ctr; - struct capi_driver *driver = null; - capiloaddata ldata; - struct list_head *l; - int retval; - - switch (cmd) { - case avmb1_addcard: - case avmb1_addcard_with_type: - if (cmd == avmb1_addcard) { - if ((retval = copy_from_user(&cdef, data, - sizeof(avmb1_carddef)))) - return -efault; - cdef.cardtype = avm_cardtype_b1; - cdef.cardnr = 0; - } else { - if ((retval = copy_from_user(&cdef, data, - sizeof(avmb1_extcarddef)))) - return -efault; - } - cparams.port = cdef.port; - cparams.irq = cdef.irq; - cparams.cardnr = cdef.cardnr; - - mutex_lock(&capi_drivers_lock); - - switch (cdef.cardtype) { - case avm_cardtype_b1: - list_for_each(l, &capi_drivers) { - driver = list_entry(l, struct capi_driver, list); - if (strcmp(driver->name, "b1isa") == 0) - break; - } - break; - case avm_cardtype_t1: - list_for_each(l, &capi_drivers) { - driver = list_entry(l, struct capi_driver, list); - if (strcmp(driver->name, "t1isa") == 0) - break; - } - break; - default: - driver = null; - break; - } - if (!driver) { - printk(kern_err "kcapi: driver not loaded. "); - retval = -eio; - } else if (!driver->add_card) { - printk(kern_err "kcapi: driver has no add card function. "); - retval = -eio; - } else - retval = driver->add_card(driver, &cparams); - - mutex_unlock(&capi_drivers_lock); - return retval; - - case avmb1_load: - case avmb1_load_and_config: - - if (cmd == avmb1_load) { - if (copy_from_user(&ldef, data, - sizeof(avmb1_loaddef))) - return -efault; - ldef.t4config.len = 0; - ldef.t4config.data = null; - } else { - if (copy_from_user(&ldef, data, - sizeof(avmb1_loadandconfigdef))) - return -efault; - } - - mutex_lock(&capi_controller_lock); - - ctr = get_capi_ctr_by_nr(ldef.contr); - if (!ctr) { - retval = -einval; - goto load_unlock_out; - } - - if (ctr->load_firmware == null) { - printk(kern_debug "kcapi: load: no load function "); - retval = -esrch; - goto load_unlock_out; - } - - if (ldef.t4file.len <= 0) { - printk(kern_debug "kcapi: load: invalid parameter: length of t4file is %d ? ", ldef.t4file.len); - retval = -einval; - goto load_unlock_out; - } - if (ldef.t4file.data == null) { - printk(kern_debug "kcapi: load: invalid parameter: dataptr is 0 "); - retval = -einval; - goto load_unlock_out; - } - - ldata.firmware.user = 1; - ldata.firmware.data = ldef.t4file.data; - ldata.firmware.len = ldef.t4file.len; - ldata.configuration.user = 1; - ldata.configuration.data = ldef.t4config.data; - ldata.configuration.len = ldef.t4config.len; - - if (ctr->state != capi_ctr_detected) { - printk(kern_info "kcapi: load: contr=%d not in detect state ", ldef.contr); - retval = -ebusy; - goto load_unlock_out; - } - ctr->state = capi_ctr_loading; - - retval = ctr->load_firmware(ctr, &ldata); - if (retval) { - ctr->state = capi_ctr_detected; - goto load_unlock_out; - } - - retval = wait_on_ctr_state(ctr, capi_ctr_running); - - load_unlock_out: - mutex_unlock(&capi_controller_lock); - return retval; - - case avmb1_resetcard: - if (copy_from_user(&rdef, data, sizeof(avmb1_resetdef))) - return -efault; - - retval = 0; - - mutex_lock(&capi_controller_lock); - - ctr = get_capi_ctr_by_nr(rdef.contr); - if (!ctr) { - retval = -esrch; - goto reset_unlock_out; - } - - if (ctr->state == capi_ctr_detected) - goto reset_unlock_out; - - if (ctr->reset_ctr == null) { - printk(kern_debug "kcapi: reset: no reset function "); - retval = -esrch; - goto reset_unlock_out; - } - - ctr->reset_ctr(ctr); - - retval = wait_on_ctr_state(ctr, capi_ctr_detected); - - reset_unlock_out: - mutex_unlock(&capi_controller_lock); - return retval; - } - return -einval; -} -#endif - -#ifdef avmb1_compat - case avmb1_load: - case avmb1_load_and_config: - case avmb1_resetcard: - case avmb1_get_cardinfo: - case avmb1_removecard: - return old_capi_manufacturer(cmd, data); -#endif - case kcapi_cmd_addcard: - { - struct list_head *l; - struct capi_driver *driver = null; - capicardparams cparams; - kcapi_carddef cdef; - - if ((retval = copy_from_user(&cdef, data, sizeof(cdef)))) - return -efault; - - cparams.port = cdef.port; - cparams.irq = cdef.irq; - cparams.membase = cdef.membase; - cparams.cardnr = cdef.cardnr; - cparams.cardtype = 0; - cdef.driver[sizeof(cdef.driver) - 1] = 0; - - mutex_lock(&capi_drivers_lock); - - list_for_each(l, &capi_drivers) { - driver = list_entry(l, struct capi_driver, list); - if (strcmp(driver->name, cdef.driver) == 0) - break; - } - if (driver == null) { - printk(kern_err "kcapi: driver "%s" not loaded. ", - cdef.driver); - retval = -esrch; - } else if (!driver->add_card) { - printk(kern_err "kcapi: driver "%s" has no add card function. ", cdef.driver); - retval = -eio; - } else - retval = driver->add_card(driver, &cparams); - - mutex_unlock(&capi_drivers_lock); - return retval; - } -export_symbol(capi20_manufacturer); - -static struct notifier_block capictr_nb = { - .notifier_call = notify_handler, - .priority = int_max, -}; - -static int __init kcapi_init(void) +int __init kcapi_init(void) - register_capictr_notifier(&capictr_nb); - - unregister_capictr_notifier(&capictr_nb); -static void __exit kcapi_exit(void) +void kcapi_exit(void) - unregister_capictr_notifier(&capictr_nb); - -module_init(kcapi_init); -module_exit(kcapi_exit); diff --git a/drivers/isdn/capi/kcapi.h b/drivers/isdn/capi/kcapi.h --- a/drivers/isdn/capi/kcapi.h +++ b/drivers/isdn/capi/kcapi.h -extern struct list_head capi_drivers; -extern struct mutex capi_drivers_lock; - -#ifdef config_proc_fs - -#else +struct capi20_appl { + u16 applid; + capi_register_params rparam; + void (*recv_message)(struct capi20_appl *ap, struct sk_buff *skb); + void *private; -static inline void kcapi_proc_init(void) { }; -static inline void kcapi_proc_exit(void) { }; + /* internal to kernelcapi.o */ + unsigned long nrecvctlpkt; + unsigned long nrecvdatapkt; + unsigned long nsentctlpkt; + unsigned long nsentdatapkt; + struct mutex recv_mtx; + struct sk_buff_head recv_queue; + struct work_struct recv_work; + int release_in_progress; +}; -#endif +u16 capi20_isinstalled(void); +u16 capi20_register(struct capi20_appl *ap); +u16 capi20_release(struct capi20_appl *ap); +u16 capi20_put_message(struct capi20_appl *ap, struct sk_buff *skb); +u16 capi20_get_manufacturer(u32 contr, u8 buf[capi_manufacturer_len]); +u16 capi20_get_version(u32 contr, struct capi_version *verp); +u16 capi20_get_serial(u32 contr, u8 serial[capi_serial_len]); +u16 capi20_get_profile(u32 contr, struct capi_profile *profp); +int capi20_manufacturer(unsigned long cmd, void __user *data); + +#define capictr_up 0 +#define capictr_down 1 + +int kcapi_init(void); +void kcapi_exit(void); + +/*----- basic-type definitions -----*/ + +typedef __u8 *_cstruct; + +typedef enum { + capi_compose, + capi_default +} _cmstruct; + +/* + the _cmsg structure contains all possible capi 2.0 parameter. + all parameters are stored here first. the function capi_cmsg_2_message + assembles the parameter and builds capi2.0 conform messages. + capi_message_2_cmsg disassembles capi 2.0 messages and stores the + parameter in the _cmsg structure + */ + +typedef struct { + /* header */ + __u16 applid; + __u8 command; + __u8 subcommand; + __u16 messagenumber; + + /* parameter */ + union { + __u32 adrcontroller; + __u32 adrplci; + __u32 adrncci; + } adr; + + _cmstruct additionalinfo; + _cstruct b1configuration; + __u16 b1protocol; + _cstruct b2configuration; + __u16 b2protocol; + _cstruct b3configuration; + __u16 b3protocol; + _cstruct bc; + _cstruct bchannelinformation; + _cmstruct bprotocol; + _cstruct calledpartynumber; + _cstruct calledpartysubaddress; + _cstruct callingpartynumber; + _cstruct callingpartysubaddress; + __u32 cipmask; + __u32 cipmask2; + __u16 cipvalue; + __u32 class; + _cstruct connectednumber; + _cstruct connectedsubaddress; + __u32 data; + __u16 datahandle; + __u16 datalength; + _cstruct facilityconfirmationparameter; + _cstruct facilitydataarray; + _cstruct facilityindicationparameter; + _cstruct facilityrequestparameter; + __u16 facilityselector; + __u16 flags; + __u32 function; + _cstruct hlc; + __u16 info; + _cstruct infoelement; + __u32 infomask; + __u16 infonumber; + _cstruct keypadfacility; + _cstruct llc; + _cstruct manudata; + __u32 manuid; + _cstruct ncpi; + __u16 reason; + __u16 reason_b3; + __u16 reject; + _cstruct useruserdata; + + /* intern */ + unsigned l, p; + unsigned char *par; + __u8 *m; + + /* buffer to construct message */ + __u8 buf[180]; + +} _cmsg; + +/*-----------------------------------------------------------------------*/ + +/* + * debugging / tracing functions + */ + +char *capi_cmd2str(__u8 cmd, __u8 subcmd); + +typedef struct { + u_char *buf; + u_char *p; + size_t size; + size_t pos; +} _cdebbuf; + +#define cdebug_size 1024 +#define cdebug_gsize 4096 + +void cdebbuf_free(_cdebbuf *cdb); +int cdebug_init(void); +void cdebug_exit(void); + +_cdebbuf *capi_message2str(__u8 *msg); diff --git a/drivers/isdn/capi/kcapi_proc.c b/drivers/isdn/capi/kcapi_proc.c --- a/drivers/isdn/capi/kcapi_proc.c +++ b/drivers/isdn/capi/kcapi_proc.c -static void *capi_driver_start(struct seq_file *seq, loff_t *pos) - __acquires(&capi_drivers_lock) +/* /proc/capi/drivers is always empty */ +static ssize_t empty_read(struct file *file, char __user *buf, + size_t size, loff_t *off) - mutex_lock(&capi_drivers_lock); - return seq_list_start(&capi_drivers, *pos); -} - -static void *capi_driver_next(struct seq_file *seq, void *v, loff_t *pos) -{ - return seq_list_next(v, &capi_drivers, pos); -} - -static void capi_driver_stop(struct seq_file *seq, void *v) - __releases(&capi_drivers_lock) -{ - mutex_unlock(&capi_drivers_lock); -} - -static int capi_driver_show(struct seq_file *seq, void *v) -{ - struct capi_driver *drv = list_entry(v, struct capi_driver, list); - - seq_printf(seq, "%-32s %s ", drv->name, drv->revision); -static const struct seq_operations seq_capi_driver_ops = { - .start = capi_driver_start, - .next = capi_driver_next, - .stop = capi_driver_stop, - .show = capi_driver_show, +static const struct file_operations empty_fops = { + .read = empty_read, - proc_create_seq("capi/driver", 0, null, &seq_capi_driver_ops); + proc_create("capi/driver", 0, null, &empty_fops); diff --git a/include/linux/isdn/capilli.h b/include/linux/isdn/capilli.h --- a/include/linux/isdn/capilli.h +++ b/include/linux/isdn/capilli.h - wait_queue_head_t state_wait_queue; -void capi_ctr_suspend_output(struct capi_ctr * card); -void capi_ctr_resume_output(struct capi_ctr * card); - int (*add_card)(struct capi_driver *driver, capicardparams *data); - -void register_capi_driver(struct capi_driver *driver); -void unregister_capi_driver(struct capi_driver *driver); - -// --------------------------------------------------------------------------- -// library functions for use by hardware controller drivers - -void capilib_new_ncci(struct list_head *head, u16 applid, u32 ncci, u32 winsize); -void capilib_free_ncci(struct list_head *head, u16 applid, u32 ncci); -void capilib_release_appl(struct list_head *head, u16 applid); -void capilib_release(struct list_head *head); -void capilib_data_b3_conf(struct list_head *head, u16 applid, u32 ncci, u16 msgid); -u16 capilib_data_b3_req(struct list_head *head, u16 applid, u32 ncci, u16 msgid); - diff --git a/include/linux/isdn/capiutil.h b/include/linux/isdn/capiutil.h --- a/include/linux/isdn/capiutil.h +++ b/include/linux/isdn/capiutil.h -/*----- basic-type definitions -----*/ - -typedef __u8 *_cstruct; - -typedef enum { - capi_compose, - capi_default -} _cmstruct; - -/* - the _cmsg structure contains all possible capi 2.0 parameter. - all parameters are stored here first. the function capi_cmsg_2_message - assembles the parameter and builds capi2.0 conform messages. - capi_message_2_cmsg disassembles capi 2.0 messages and stores the - parameter in the _cmsg structure - */ - -typedef struct { - /* header */ - __u16 applid; - __u8 command; - __u8 subcommand; - __u16 messagenumber; - - /* parameter */ - union { - __u32 adrcontroller; - __u32 adrplci; - __u32 adrncci; - } adr; - - _cmstruct additionalinfo; - _cstruct b1configuration; - __u16 b1protocol; - _cstruct b2configuration; - __u16 b2protocol; - _cstruct b3configuration; - __u16 b3protocol; - _cstruct bc; - _cstruct bchannelinformation; - _cmstruct bprotocol; - _cstruct calledpartynumber; - _cstruct calledpartysubaddress; - _cstruct callingpartynumber; - _cstruct callingpartysubaddress; - __u32 cipmask; - __u32 cipmask2; - __u16 cipvalue; - __u32 class; - _cstruct connectednumber; - _cstruct connectedsubaddress; - __u32 data; - __u16 datahandle; - __u16 datalength; - _cstruct facilityconfirmationparameter; - _cstruct facilitydataarray; - _cstruct facilityindicationparameter; - _cstruct facilityrequestparameter; - __u16 facilityselector; - __u16 flags; - __u32 function; - _cstruct hlc; - __u16 info; - _cstruct infoelement; - __u32 infomask; - __u16 infonumber; - _cstruct keypadfacility; - _cstruct llc; - _cstruct manudata; - __u32 manuid; - _cstruct ncpi; - __u16 reason; - __u16 reason_b3; - __u16 reject; - _cstruct useruserdata; - - /* intern */ - unsigned l, p; - unsigned char *par; - __u8 *m; - - /* buffer to construct message */ - __u8 buf[180]; - -} _cmsg; - -/* - * capi_cmsg2message() assembles the parameter from _cmsg to a capi 2.0 - * conform message - */ -unsigned capi_cmsg2message(_cmsg * cmsg, __u8 * msg); - -/* - * capi_message2cmsg disassembles a capi message an writes the parameter - * into _cmsg for easy access - */ -unsigned capi_message2cmsg(_cmsg * cmsg, __u8 * msg); - -/* - * capi_cmsg_header() fills the _cmsg structure with default values, so only - * parameter with non default values must be changed before sending the - * message. - */ -unsigned capi_cmsg_header(_cmsg * cmsg, __u16 _applid, - __u8 _command, __u8 _subcommand, - __u16 _messagenumber, __u32 _controller); - -/*-----------------------------------------------------------------------*/ - -/* - * debugging / tracing functions - */ - -char *capi_cmd2str(__u8 cmd, __u8 subcmd); - -typedef struct { - u_char *buf; - u_char *p; - size_t size; - size_t pos; -} _cdebbuf; - -#define cdebug_size 1024 -#define cdebug_gsize 4096 - -void cdebbuf_free(_cdebbuf *cdb); -int cdebug_init(void); -void cdebug_exit(void); - -_cdebbuf *capi_cmsg2str(_cmsg *cmsg); -_cdebbuf *capi_message2str(__u8 *msg); - -/*-----------------------------------------------------------------------*/ - -static inline void capi_cmsg_answer(_cmsg * cmsg) -{ - cmsg->subcommand |= 0x01; -} - -/*-----------------------------------------------------------------------*/ - -static inline void capi_fill_connect_b3_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - _cstruct ncpi) -{ - capi_cmsg_header(cmsg, applid, 0x82, 0x80, messagenumber, adr); - cmsg->ncpi = ncpi; -} - -static inline void capi_fill_facility_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 facilityselector, - _cstruct facilityrequestparameter) -{ - capi_cmsg_header(cmsg, applid, 0x80, 0x80, messagenumber, adr); - cmsg->facilityselector = facilityselector; - cmsg->facilityrequestparameter = facilityrequestparameter; -} - -static inline void capi_fill_info_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - _cstruct calledpartynumber, - _cstruct bchannelinformation, - _cstruct keypadfacility, - _cstruct useruserdata, - _cstruct facilitydataarray) -{ - capi_cmsg_header(cmsg, applid, 0x08, 0x80, messagenumber, adr); - cmsg->calledpartynumber = calledpartynumber; - cmsg->bchannelinformation = bchannelinformation; - cmsg->keypadfacility = keypadfacility; - cmsg->useruserdata = useruserdata; - cmsg->facilitydataarray = facilitydataarray; -} - -static inline void capi_fill_listen_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u32 infomask, - __u32 cipmask, - __u32 cipmask2, - _cstruct callingpartynumber, - _cstruct callingpartysubaddress) -{ - capi_cmsg_header(cmsg, applid, 0x05, 0x80, messagenumber, adr); - cmsg->infomask = infomask; - cmsg->cipmask = cipmask; - cmsg->cipmask2 = cipmask2; - cmsg->callingpartynumber = callingpartynumber; - cmsg->callingpartysubaddress = callingpartysubaddress; -} - -static inline void capi_fill_alert_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - _cstruct bchannelinformation, - _cstruct keypadfacility, - _cstruct useruserdata, - _cstruct facilitydataarray) -{ - capi_cmsg_header(cmsg, applid, 0x01, 0x80, messagenumber, adr); - cmsg->bchannelinformation = bchannelinformation; - cmsg->keypadfacility = keypadfacility; - cmsg->useruserdata = useruserdata; - cmsg->facilitydataarray = facilitydataarray; -} - -static inline void capi_fill_connect_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 cipvalue, - _cstruct calledpartynumber, - _cstruct callingpartynumber, - _cstruct calledpartysubaddress, - _cstruct callingpartysubaddress, - __u16 b1protocol, - __u16 b2protocol, - __u16 b3protocol, - _cstruct b1configuration, - _cstruct b2configuration, - _cstruct b3configuration, - _cstruct bc, - _cstruct llc, - _cstruct hlc, - _cstruct bchannelinformation, - _cstruct keypadfacility, - _cstruct useruserdata, - _cstruct facilitydataarray) -{ - - capi_cmsg_header(cmsg, applid, 0x02, 0x80, messagenumber, adr); - cmsg->cipvalue = cipvalue; - cmsg->calledpartynumber = calledpartynumber; - cmsg->callingpartynumber = callingpartynumber; - cmsg->calledpartysubaddress = calledpartysubaddress; - cmsg->callingpartysubaddress = callingpartysubaddress; - cmsg->b1protocol = b1protocol; - cmsg->b2protocol = b2protocol; - cmsg->b3protocol = b3protocol; - cmsg->b1configuration = b1configuration; - cmsg->b2configuration = b2configuration; - cmsg->b3configuration = b3configuration; - cmsg->bc = bc; - cmsg->llc = llc; - cmsg->hlc = hlc; - cmsg->bchannelinformation = bchannelinformation; - cmsg->keypadfacility = keypadfacility; - cmsg->useruserdata = useruserdata; - cmsg->facilitydataarray = facilitydataarray; -} - -static inline void capi_fill_data_b3_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u32 data, - __u16 datalength, - __u16 datahandle, - __u16 flags) -{ - - capi_cmsg_header(cmsg, applid, 0x86, 0x80, messagenumber, adr); - cmsg->data = data; - cmsg->datalength = datalength; - cmsg->datahandle = datahandle; - cmsg->flags = flags; -} - -static inline void capi_fill_disconnect_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - _cstruct bchannelinformation, - _cstruct keypadfacility, - _cstruct useruserdata, - _cstruct facilitydataarray) -{ - - capi_cmsg_header(cmsg, applid, 0x04, 0x80, messagenumber, adr); - cmsg->bchannelinformation = bchannelinformation; - cmsg->keypadfacility = keypadfacility; - cmsg->useruserdata = useruserdata; - cmsg->facilitydataarray = facilitydataarray; -} - -static inline void capi_fill_disconnect_b3_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - _cstruct ncpi) -{ - - capi_cmsg_header(cmsg, applid, 0x84, 0x80, messagenumber, adr); - cmsg->ncpi = ncpi; -} - -static inline void capi_fill_manufacturer_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u32 manuid, - __u32 class, - __u32 function, - _cstruct manudata) -{ - - capi_cmsg_header(cmsg, applid, 0xff, 0x80, messagenumber, adr); - cmsg->manuid = manuid; - cmsg->class = class; - cmsg->function = function; - cmsg->manudata = manudata; -} - -static inline void capi_fill_reset_b3_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - _cstruct ncpi) -{ - - capi_cmsg_header(cmsg, applid, 0x87, 0x80, messagenumber, adr); - cmsg->ncpi = ncpi; -} - -static inline void capi_fill_select_b_protocol_req(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 b1protocol, - __u16 b2protocol, - __u16 b3protocol, - _cstruct b1configuration, - _cstruct b2configuration, - _cstruct b3configuration) -{ - - capi_cmsg_header(cmsg, applid, 0x41, 0x80, messagenumber, adr); - cmsg->b1protocol = b1protocol; - cmsg->b2protocol = b2protocol; - cmsg->b3protocol = b3protocol; - cmsg->b1configuration = b1configuration; - cmsg->b2configuration = b2configuration; - cmsg->b3configuration = b3configuration; -} - -static inline void capi_fill_connect_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 reject, - __u16 b1protocol, - __u16 b2protocol, - __u16 b3protocol, - _cstruct b1configuration, - _cstruct b2configuration, - _cstruct b3configuration, - _cstruct connectednumber, - _cstruct connectedsubaddress, - _cstruct llc, - _cstruct bchannelinformation, - _cstruct keypadfacility, - _cstruct useruserdata, - _cstruct facilitydataarray) -{ - capi_cmsg_header(cmsg, applid, 0x02, 0x83, messagenumber, adr); - cmsg->reject = reject; - cmsg->b1protocol = b1protocol; - cmsg->b2protocol = b2protocol; - cmsg->b3protocol = b3protocol; - cmsg->b1configuration = b1configuration; - cmsg->b2configuration = b2configuration; - cmsg->b3configuration = b3configuration; - cmsg->connectednumber = connectednumber; - cmsg->connectedsubaddress = connectedsubaddress; - cmsg->llc = llc; - cmsg->bchannelinformation = bchannelinformation; - cmsg->keypadfacility = keypadfacility; - cmsg->useruserdata = useruserdata; - cmsg->facilitydataarray = facilitydataarray; -} - -static inline void capi_fill_connect_active_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x03, 0x83, messagenumber, adr); -} - -static inline void capi_fill_connect_b3_active_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x83, 0x83, messagenumber, adr); -} - -static inline void capi_fill_connect_b3_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 reject, - _cstruct ncpi) -{ - capi_cmsg_header(cmsg, applid, 0x82, 0x83, messagenumber, adr); - cmsg->reject = reject; - cmsg->ncpi = ncpi; -} - -static inline void capi_fill_connect_b3_t90_active_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x88, 0x83, messagenumber, adr); -} - -static inline void capi_fill_data_b3_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 datahandle) -{ - - capi_cmsg_header(cmsg, applid, 0x86, 0x83, messagenumber, adr); - cmsg->datahandle = datahandle; -} - -static inline void capi_fill_disconnect_b3_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x84, 0x83, messagenumber, adr); -} - -static inline void capi_fill_disconnect_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x04, 0x83, messagenumber, adr); -} - -static inline void capi_fill_facility_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u16 facilityselector) -{ - - capi_cmsg_header(cmsg, applid, 0x80, 0x83, messagenumber, adr); - cmsg->facilityselector = facilityselector; -} - -static inline void capi_fill_info_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x08, 0x83, messagenumber, adr); -} - -static inline void capi_fill_manufacturer_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr, - __u32 manuid, - __u32 class, - __u32 function, - _cstruct manudata) -{ - - capi_cmsg_header(cmsg, applid, 0xff, 0x83, messagenumber, adr); - cmsg->manuid = manuid; - cmsg->class = class; - cmsg->function = function; - cmsg->manudata = manudata; -} - -static inline void capi_fill_reset_b3_resp(_cmsg * cmsg, __u16 applid, __u16 messagenumber, - __u32 adr) -{ - - capi_cmsg_header(cmsg, applid, 0x87, 0x83, messagenumber, adr); -} - diff --git a/include/linux/kernelcapi.h b/include/linux/kernelcapi.h --- a/include/linux/kernelcapi.h +++ b/include/linux/kernelcapi.h - -struct capi20_appl { - u16 applid; - capi_register_params rparam; - void (*recv_message)(struct capi20_appl *ap, struct sk_buff *skb); - void *private; - - /* internal to kernelcapi.o */ - unsigned long nrecvctlpkt; - unsigned long nrecvdatapkt; - unsigned long nsentctlpkt; - unsigned long nsentdatapkt; - struct mutex recv_mtx; - struct sk_buff_head recv_queue; - struct work_struct recv_work; - int release_in_progress; -}; - -u16 capi20_isinstalled(void); -u16 capi20_register(struct capi20_appl *ap); -u16 capi20_release(struct capi20_appl *ap); -u16 capi20_put_message(struct capi20_appl *ap, struct sk_buff *skb); -u16 capi20_get_manufacturer(u32 contr, u8 buf[capi_manufacturer_len]); -u16 capi20_get_version(u32 contr, struct capi_version *verp); -u16 capi20_get_serial(u32 contr, u8 serial[capi_serial_len]); -u16 capi20_get_profile(u32 contr, struct capi_profile *profp); -int capi20_manufacturer(unsigned long cmd, void __user *data); - -#define capictr_up 0 -#define capictr_down 1 - -int register_capictr_notifier(struct notifier_block *nb); -int unregister_capictr_notifier(struct notifier_block *nb); - -typedef enum { - capimessagenotsupportedincurrentstate = 0x2001, - capiillcontrplcincci = 0x2002, - capinoplciavailable = 0x2003, - capinoncciavailable = 0x2004, - capinolistenresourcesavailable = 0x2005, - capinofaxresourcesavailable = 0x2006, - capiillmessageparmcoding = 0x2007, -} resource_coding_problem; - -typedef enum { - capib1protocolnotsupported = 0x3001, - capib2protocolnotsupported = 0x3002, - capib3protocolnotsupported = 0x3003, - capib1protocolparameternotsupported = 0x3004, - capib2protocolparameternotsupported = 0x3005, - capib3protocolparameternotsupported = 0x3006, - capibprotocolcombinationnotsupported = 0x3007, - capincpinotsupported = 0x3008, - capicipvalueunknown = 0x3009, - capiflagsnotsupported = 0x300a, - capifacilitynotsupported = 0x300b, - capidatalengthnotsupportedbycurrentprotocol = 0x300c, - capiresetprocedurenotsupportedbycurrentprotocol = 0x300d, - capiteiassignmentfailed = 0x300e, -} requested_services_problem; - -typedef enum { - capisuccess = 0x0000, - capisupplementaryservicenotsupported = 0x300e, - capirequestnotallowedinthisstate = 0x3010, -} supplementary_service_info; - -typedef enum { - capiprotocolerrorlayer1 = 0x3301, - capiprotocolerrorlayer2 = 0x3302, - capiprotocolerrorlayer3 = 0x3303, - capitimeout = 0x3303, // suppservicereason - capicallgiventootherapplication = 0x3304, -} capi_reason; - diff --git a/include/uapi/linux/b1lli.h b/include/uapi/linux/b1lli.h --- a/include/uapi/linux/b1lli.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 with linux-syscall-note */ -/* $id: b1lli.h,v 1.8.8.3 2001/09/23 22:25:05 kai exp $ - * - * isdn lowlevel-module for avm b1-card. - * - * copyright 1996 by carsten paeth (calle@calle.in-berlin.de) - * - * this software may be used and distributed according to the terms - * of the gnu general public license, incorporated herein by reference. - * - */ - -#ifndef _b1lli_h_ -#define _b1lli_h_ -/* - * struct for loading t4 file - */ -typedef struct avmb1_t4file { - int len; - unsigned char *data; -} avmb1_t4file; - -typedef struct avmb1_loaddef { - int contr; - avmb1_t4file t4file; -} avmb1_loaddef; - -typedef struct avmb1_loadandconfigdef { - int contr; - avmb1_t4file t4file; - avmb1_t4file t4config; -} avmb1_loadandconfigdef; - -typedef struct avmb1_resetdef { - int contr; -} avmb1_resetdef; - -typedef struct avmb1_getdef { - int contr; - int cardtype; - int cardstate; -} avmb1_getdef; - -/* - * struct for adding new cards - */ -typedef struct avmb1_carddef { - int port; - int irq; -} avmb1_carddef; - -#define avm_cardtype_b1 0 -#define avm_cardtype_t1 1 -#define avm_cardtype_m1 2 -#define avm_cardtype_m2 3 - -typedef struct avmb1_extcarddef { - int port; - int irq; - int cardtype; - int cardnr; /* for hema/t1 */ -} avmb1_extcarddef; - -#define avmb1_load 0 /* load image to card */ -#define avmb1_addcard 1 /* add a new card - obsolete */ -#define avmb1_resetcard 2 /* reset a card */ -#define avmb1_load_and_config 3 /* load image and config to card */ -#define avmb1_addcard_with_type 4 /* add a new card, with cardtype */ -#define avmb1_get_cardinfo 5 /* get cardtype */ -#define avmb1_removecard 6 /* remove a card - obsolete */ - -#define avmb1_registercard_is_obsolete - -#endif /* _b1lli_h_ */ | Various | f59aba2f75795e5b6a4f1aa31f3e20d7b71ca804 | arnd bergmann | include | linux | capi, isdn, linux |
memory: tegra: add support for the tegra194 memory controller | the memory and external memory controllers on tegra194 are very similar to their predecessors from tegra186. add the necessary soc-specific data to support the newer versions. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for the tegra194 memory controller | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['memory', 'tegra'] | ['c', 'makefile'] | 3 | 994 | 41 | --- diff --git a/drivers/memory/tegra/makefile b/drivers/memory/tegra/makefile --- a/drivers/memory/tegra/makefile +++ b/drivers/memory/tegra/makefile +obj-$(config_arch_tegra_194_soc) += tegra186.o tegra186-emc.o diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c +#endif +#if defined(config_arch_tegra194_soc) + { .compatible = "nvidia,tegra194-emc" }, diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c +#if defined(config_arch_tegra_194_soc) +#include <dt-bindings/memory/tegra194-mc.h> +#endif + -static int tegra186_mc_probe(struct platform_device *pdev) -{ - struct tegra186_mc *mc; - struct resource *res; - int err; - - mc = devm_kzalloc(&pdev->dev, sizeof(*mc), gfp_kernel); - if (!mc) - return -enomem; - - mc->soc = of_device_get_match_data(&pdev->dev); - - res = platform_get_resource(pdev, ioresource_mem, 0); - mc->regs = devm_ioremap_resource(&pdev->dev, res); - if (is_err(mc->regs)) - return ptr_err(mc->regs); - - mc->dev = &pdev->dev; - - err = of_platform_populate(pdev->dev.of_node, null, null, &pdev->dev); - if (err < 0) - return err; - - platform_set_drvdata(pdev, mc); - tegra186_mc_program_sid(mc); - - return 0; -} - -static int tegra186_mc_remove(struct platform_device *pdev) -{ - struct tegra186_mc *mc = platform_get_drvdata(pdev); - - of_platform_depopulate(mc->dev); - - return 0; -} - -static const struct of_device_id tegra186_mc_of_match[] = { -#if defined(config_arch_tegra_186_soc) - { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#if defined(config_arch_tegra_194_soc) +static const struct tegra186_mc_client tegra194_mc_clients[] = { + { + .name = "ptcr", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x000, + .security = 0x004, + }, + }, { + .name = "miu7r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x008, + .security = 0x00c, + }, + }, { + .name = "miu7w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x010, + .security = 0x014, + }, + }, { + .name = "hdar", + .sid = tegra194_sid_hda, + .regs = { + .override = 0x0a8, + .security = 0x0ac, + }, + }, { + .name = "host1xdmar", + .sid = tegra194_sid_host1x, + .regs = { + .override = 0x0b0, + .security = 0x0b4, + }, + }, { + .name = "nvencsrd", + .sid = tegra194_sid_nvenc, + .regs = { + .override = 0x0e0, + .security = 0x0e4, + }, + }, { + .name = "satar", + .sid = tegra194_sid_sata, + .regs = { + .override = 0x0f8, + .security = 0x0fc, + }, + }, { + .name = "mpcorer", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x138, + .security = 0x13c, + }, + }, { + .name = "nvencswr", + .sid = tegra194_sid_nvenc, + .regs = { + .override = 0x158, + .security = 0x15c, + }, + }, { + .name = "hdaw", + .sid = tegra194_sid_hda, + .regs = { + .override = 0x1a8, + .security = 0x1ac, + }, + }, { + .name = "mpcorew", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x1c8, + .security = 0x1cc, + }, + }, { + .name = "sataw", + .sid = tegra194_sid_sata, + .regs = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, { + .name = "ispra", + .sid = tegra194_sid_isp, + .regs = { + .override = 0x220, + .security = 0x224, + }, + }, { + .name = "ispfalr", + .sid = tegra194_sid_isp_falcon, + .regs = { + .override = 0x228, + .security = 0x22c, + }, + }, { + .name = "ispwa", + .sid = tegra194_sid_isp, + .regs = { + .override = 0x230, + .security = 0x234, + }, + }, { + .name = "ispwb", + .sid = tegra194_sid_isp, + .regs = { + .override = 0x238, + .security = 0x23c, + }, + }, { + .name = "xusb_hostr", + .sid = tegra194_sid_xusb_host, + .regs = { + .override = 0x250, + .security = 0x254, + }, + }, { + .name = "xusb_hostw", + .sid = tegra194_sid_xusb_host, + .regs = { + .override = 0x258, + .security = 0x25c, + }, + }, { + .name = "xusb_devr", + .sid = tegra194_sid_xusb_dev, + .regs = { + .override = 0x260, + .security = 0x264, + }, + }, { + .name = "xusb_devw", + .sid = tegra194_sid_xusb_dev, + .regs = { + .override = 0x268, + .security = 0x26c, + }, + }, { + .name = "sdmmcra", + .sid = tegra194_sid_sdmmc1, + .regs = { + .override = 0x300, + .security = 0x304, + }, + }, { + .name = "sdmmcr", + .sid = tegra194_sid_sdmmc3, + .regs = { + .override = 0x310, + .security = 0x314, + }, + }, { + .name = "sdmmcrab", + .sid = tegra194_sid_sdmmc4, + .regs = { + .override = 0x318, + .security = 0x31c, + }, + }, { + .name = "sdmmcwa", + .sid = tegra194_sid_sdmmc1, + .regs = { + .override = 0x320, + .security = 0x324, + }, + }, { + .name = "sdmmcw", + .sid = tegra194_sid_sdmmc3, + .regs = { + .override = 0x330, + .security = 0x334, + }, + }, { + .name = "sdmmcwab", + .sid = tegra194_sid_sdmmc4, + .regs = { + .override = 0x338, + .security = 0x33c, + }, + }, { + .name = "vicsrd", + .sid = tegra194_sid_vic, + .regs = { + .override = 0x360, + .security = 0x364, + }, + }, { + .name = "vicswr", + .sid = tegra194_sid_vic, + .regs = { + .override = 0x368, + .security = 0x36c, + }, + }, { + .name = "viw", + .sid = tegra194_sid_vi, + .regs = { + .override = 0x390, + .security = 0x394, + }, + }, { + .name = "nvdecsrd", + .sid = tegra194_sid_nvdec, + .regs = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, { + .name = "nvdecswr", + .sid = tegra194_sid_nvdec, + .regs = { + .override = 0x3c8, + .security = 0x3cc, + }, + }, { + .name = "aper", + .sid = tegra194_sid_ape, + .regs = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, { + .name = "apew", + .sid = tegra194_sid_ape, + .regs = { + .override = 0x3d0, + .security = 0x3d4, + }, + }, { + .name = "nvjpgsrd", + .sid = tegra194_sid_nvjpg, + .regs = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, { + .name = "nvjpgswr", + .sid = tegra194_sid_nvjpg, + .regs = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, { + .name = "axiapr", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x410, + .security = 0x414, + }, + }, { + .name = "axiapw", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x418, + .security = 0x41c, + }, + }, { + .name = "etrr", + .sid = tegra194_sid_etr, + .regs = { + .override = 0x420, + .security = 0x424, + }, + }, { + .name = "etrw", + .sid = tegra194_sid_etr, + .regs = { + .override = 0x428, + .security = 0x42c, + }, + }, { + .name = "axisr", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x460, + .security = 0x464, + }, + }, { + .name = "axisw", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x468, + .security = 0x46c, + }, + }, { + .name = "eqosr", + .sid = tegra194_sid_eqos, + .regs = { + .override = 0x470, + .security = 0x474, + }, + }, { + .name = "eqosw", + .sid = tegra194_sid_eqos, + .regs = { + .override = 0x478, + .security = 0x47c, + }, + }, { + .name = "ufshcr", + .sid = tegra194_sid_ufshc, + .regs = { + .override = 0x480, + .security = 0x484, + }, + }, { + .name = "ufshcw", + .sid = tegra194_sid_ufshc, + .regs = { + .override = 0x488, + .security = 0x48c, + }, + }, { + .name = "nvdisplayr", + .sid = tegra194_sid_nvdisplay, + .regs = { + .override = 0x490, + .security = 0x494, + }, + }, { + .name = "bpmpr", + .sid = tegra194_sid_bpmp, + .regs = { + .override = 0x498, + .security = 0x49c, + }, + }, { + .name = "bpmpw", + .sid = tegra194_sid_bpmp, + .regs = { + .override = 0x4a0, + .security = 0x4a4, + }, + }, { + .name = "bpmpdmar", + .sid = tegra194_sid_bpmp, + .regs = { + .override = 0x4a8, + .security = 0x4ac, + }, + }, { + .name = "bpmpdmaw", + .sid = tegra194_sid_bpmp, + .regs = { + .override = 0x4b0, + .security = 0x4b4, + }, + }, { + .name = "aonr", + .sid = tegra194_sid_aon, + .regs = { + .override = 0x4b8, + .security = 0x4bc, + }, + }, { + .name = "aonw", + .sid = tegra194_sid_aon, + .regs = { + .override = 0x4c0, + .security = 0x4c4, + }, + }, { + .name = "aondmar", + .sid = tegra194_sid_aon, + .regs = { + .override = 0x4c8, + .security = 0x4cc, + }, + }, { + .name = "aondmaw", + .sid = tegra194_sid_aon, + .regs = { + .override = 0x4d0, + .security = 0x4d4, + }, + }, { + .name = "scer", + .sid = tegra194_sid_sce, + .regs = { + .override = 0x4d8, + .security = 0x4dc, + }, + }, { + .name = "scew", + .sid = tegra194_sid_sce, + .regs = { + .override = 0x4e0, + .security = 0x4e4, + }, + }, { + .name = "scedmar", + .sid = tegra194_sid_sce, + .regs = { + .override = 0x4e8, + .security = 0x4ec, + }, + }, { + .name = "scedmaw", + .sid = tegra194_sid_sce, + .regs = { + .override = 0x4f0, + .security = 0x4f4, + }, + }, { + .name = "apedmar", + .sid = tegra194_sid_ape, + .regs = { + .override = 0x4f8, + .security = 0x4fc, + }, + }, { + .name = "apedmaw", + .sid = tegra194_sid_ape, + .regs = { + .override = 0x500, + .security = 0x504, + }, + }, { + .name = "nvdisplayr1", + .sid = tegra194_sid_nvdisplay, + .regs = { + .override = 0x508, + .security = 0x50c, + }, + }, { + .name = "vicsrd1", + .sid = tegra194_sid_vic, + .regs = { + .override = 0x510, + .security = 0x514, + }, + }, { + .name = "nvdecsrd1", + .sid = tegra194_sid_nvdec, + .regs = { + .override = 0x518, + .security = 0x51c, + }, + }, { + .name = "miu0r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x530, + .security = 0x534, + }, + }, { + .name = "miu0w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x538, + .security = 0x53c, + }, + }, { + .name = "miu1r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x540, + .security = 0x544, + }, + }, { + .name = "miu1w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x548, + .security = 0x54c, + }, + }, { + .name = "miu2r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x570, + .security = 0x574, + }, + }, { + .name = "miu2w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x578, + .security = 0x57c, + }, + }, { + .name = "miu3r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x580, + .security = 0x584, + }, + }, { + .name = "miu3w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x588, + .security = 0x58c, + }, + }, { + .name = "miu4r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x590, + .security = 0x594, + }, + }, { + .name = "miu4w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x598, + .security = 0x59c, + }, + }, { + .name = "dpmur", + .sid = tegra194_sid_passthrough, + .regs = { + .override = 0x598, + .security = 0x59c, + }, + }, { + .name = "vifalr", + .sid = tegra194_sid_vi_falcon, + .regs = { + .override = 0x5e0, + .security = 0x5e4, + }, + }, { + .name = "vifalw", + .sid = tegra194_sid_vi_falcon, + .regs = { + .override = 0x5e8, + .security = 0x5ec, + }, + }, { + .name = "dla0rda", + .sid = tegra194_sid_nvdla0, + .regs = { + .override = 0x5f0, + .security = 0x5f4, + }, + }, { + .name = "dla0falrdb", + .sid = tegra194_sid_nvdla0, + .regs = { + .override = 0x5f8, + .security = 0x5fc, + }, + }, { + .name = "dla0wra", + .sid = tegra194_sid_nvdla0, + .regs = { + .override = 0x600, + .security = 0x604, + }, + }, { + .name = "dla0falwrb", + .sid = tegra194_sid_nvdla0, + .regs = { + .override = 0x608, + .security = 0x60c, + }, + }, { + .name = "dla1rda", + .sid = tegra194_sid_nvdla1, + .regs = { + .override = 0x610, + .security = 0x614, + }, + }, { + .name = "dla1falrdb", + .sid = tegra194_sid_nvdla1, + .regs = { + .override = 0x618, + .security = 0x61c, + }, + }, { + .name = "dla1wra", + .sid = tegra194_sid_nvdla1, + .regs = { + .override = 0x620, + .security = 0x624, + }, + }, { + .name = "dla1falwrb", + .sid = tegra194_sid_nvdla1, + .regs = { + .override = 0x628, + .security = 0x62c, + }, + }, { + .name = "pva0rda", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x630, + .security = 0x634, + }, + }, { + .name = "pva0rdb", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x638, + .security = 0x63c, + }, + }, { + .name = "pva0rdc", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x640, + .security = 0x644, + }, + }, { + .name = "pva0wra", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x648, + .security = 0x64c, + }, + }, { + .name = "pva0wrb", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x650, + .security = 0x654, + }, + }, { + .name = "pva0wrc", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x658, + .security = 0x65c, + }, + }, { + .name = "pva1rda", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x660, + .security = 0x664, + }, + }, { + .name = "pva1rdb", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x668, + .security = 0x66c, + }, + }, { + .name = "pva1rdc", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x670, + .security = 0x674, + }, + }, { + .name = "pva1wra", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x678, + .security = 0x67c, + }, + }, { + .name = "pva1wrb", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x680, + .security = 0x684, + }, + }, { + .name = "pva1wrc", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x688, + .security = 0x68c, + }, + }, { + .name = "rcer", + .sid = tegra194_sid_rce, + .regs = { + .override = 0x690, + .security = 0x694, + }, + }, { + .name = "rcew", + .sid = tegra194_sid_rce, + .regs = { + .override = 0x698, + .security = 0x69c, + }, + }, { + .name = "rcedmar", + .sid = tegra194_sid_rce, + .regs = { + .override = 0x6a0, + .security = 0x6a4, + }, + }, { + .name = "rcedmaw", + .sid = tegra194_sid_rce, + .regs = { + .override = 0x6a8, + .security = 0x6ac, + }, + }, { + .name = "nvenc1srd", + .sid = tegra194_sid_nvenc1, + .regs = { + .override = 0x6b0, + .security = 0x6b4, + }, + }, { + .name = "nvenc1swr", + .sid = tegra194_sid_nvenc1, + .regs = { + .override = 0x6b8, + .security = 0x6bc, + }, + }, { + .name = "pcie0r", + .sid = tegra194_sid_pcie0, + .regs = { + .override = 0x6c0, + .security = 0x6c4, + }, + }, { + .name = "pcie0w", + .sid = tegra194_sid_pcie0, + .regs = { + .override = 0x6c8, + .security = 0x6cc, + }, + }, { + .name = "pcie1r", + .sid = tegra194_sid_pcie1, + .regs = { + .override = 0x6d0, + .security = 0x6d4, + }, + }, { + .name = "pcie1w", + .sid = tegra194_sid_pcie1, + .regs = { + .override = 0x6d8, + .security = 0x6dc, + }, + }, { + .name = "pcie2ar", + .sid = tegra194_sid_pcie2, + .regs = { + .override = 0x6e0, + .security = 0x6e4, + }, + }, { + .name = "pcie2aw", + .sid = tegra194_sid_pcie2, + .regs = { + .override = 0x6e8, + .security = 0x6ec, + }, + }, { + .name = "pcie3r", + .sid = tegra194_sid_pcie3, + .regs = { + .override = 0x6f0, + .security = 0x6f4, + }, + }, { + .name = "pcie3w", + .sid = tegra194_sid_pcie3, + .regs = { + .override = 0x6f8, + .security = 0x6fc, + }, + }, { + .name = "pcie4r", + .sid = tegra194_sid_pcie4, + .regs = { + .override = 0x700, + .security = 0x704, + }, + }, { + .name = "pcie4w", + .sid = tegra194_sid_pcie4, + .regs = { + .override = 0x708, + .security = 0x70c, + }, + }, { + .name = "pcie5r", + .sid = tegra194_sid_pcie5, + .regs = { + .override = 0x710, + .security = 0x714, + }, + }, { + .name = "pcie5w", + .sid = tegra194_sid_pcie5, + .regs = { + .override = 0x718, + .security = 0x71c, + }, + }, { + .name = "ispfalw", + .sid = tegra194_sid_isp_falcon, + .regs = { + .override = 0x720, + .security = 0x724, + }, + }, { + .name = "dla0rda1", + .sid = tegra194_sid_nvdla0, + .regs = { + .override = 0x748, + .security = 0x74c, + }, + }, { + .name = "dla1rda1", + .sid = tegra194_sid_nvdla1, + .regs = { + .override = 0x750, + .security = 0x754, + }, + }, { + .name = "pva0rda1", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x758, + .security = 0x75c, + }, + }, { + .name = "pva0rdb1", + .sid = tegra194_sid_pva0, + .regs = { + .override = 0x760, + .security = 0x764, + }, + }, { + .name = "pva1rda1", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x768, + .security = 0x76c, + }, + }, { + .name = "pva1rdb1", + .sid = tegra194_sid_pva1, + .regs = { + .override = 0x770, + .security = 0x774, + }, + }, { + .name = "pcie5r1", + .sid = tegra194_sid_pcie5, + .regs = { + .override = 0x778, + .security = 0x77c, + }, + }, { + .name = "nvencsrd1", + .sid = tegra194_sid_nvenc, + .regs = { + .override = 0x780, + .security = 0x784, + }, + }, { + .name = "nvenc1srd1", + .sid = tegra194_sid_nvenc1, + .regs = { + .override = 0x788, + .security = 0x78c, + }, + }, { + .name = "ispra1", + .sid = tegra194_sid_isp, + .regs = { + .override = 0x790, + .security = 0x794, + }, + }, { + .name = "pcie0r1", + .sid = tegra194_sid_pcie0, + .regs = { + .override = 0x798, + .security = 0x79c, + }, + }, { + .name = "nvdec1srd", + .sid = tegra194_sid_nvdec1, + .regs = { + .override = 0x7c8, + .security = 0x7cc, + }, + }, { + .name = "nvdec1srd1", + .sid = tegra194_sid_nvdec1, + .regs = { + .override = 0x7d0, + .security = 0x7d4, + }, + }, { + .name = "nvdec1swr", + .sid = tegra194_sid_nvdec1, + .regs = { + .override = 0x7d8, + .security = 0x7dc, + }, + }, { + .name = "miu5r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x7e0, + .security = 0x7e4, + }, + }, { + .name = "miu5w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x7e8, + .security = 0x7ec, + }, + }, { + .name = "miu6r", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x7f0, + .security = 0x7f4, + }, + }, { + .name = "miu6w", + .sid = tegra194_sid_miu, + .regs = { + .override = 0x7f8, + .security = 0x7fc, + }, + }, +}; + +static const struct tegra186_mc_soc tegra194_mc_soc = { + .num_clients = array_size(tegra194_mc_clients), + .clients = tegra194_mc_clients, +}; +#endif + +static int tegra186_mc_probe(struct platform_device *pdev) +{ + struct tegra186_mc *mc; + struct resource *res; + int err; + + mc = devm_kzalloc(&pdev->dev, sizeof(*mc), gfp_kernel); + if (!mc) + return -enomem; + + mc->soc = of_device_get_match_data(&pdev->dev); + + res = platform_get_resource(pdev, ioresource_mem, 0); + mc->regs = devm_ioremap_resource(&pdev->dev, res); + if (is_err(mc->regs)) + return ptr_err(mc->regs); + + mc->dev = &pdev->dev; + + err = of_platform_populate(pdev->dev.of_node, null, null, &pdev->dev); + if (err < 0) + return err; + + platform_set_drvdata(pdev, mc); + tegra186_mc_program_sid(mc); + + return 0; +} + +static int tegra186_mc_remove(struct platform_device *pdev) +{ + struct tegra186_mc *mc = platform_get_drvdata(pdev); + + of_platform_depopulate(mc->dev); + + return 0; +} + +static const struct of_device_id tegra186_mc_of_match[] = { +#if defined(config_arch_tegra_186_soc) + { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, +#endif +#if defined(config_arch_tegra_194_soc) + { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, | Various | a127e690b051df030f5ad2e28b14e8c3a624c145 | thierry reding | drivers | memory | tegra |
memory: tegra: implement emc debugfs interface on tegra20 | a common debugfs interface is already available on tegra124, tegra186 and tegra194. implement the same interface on tegra20 to enable testing of the emc frequency scaling code using a unified interface. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | implement emc debugfs interface on tegra20 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['memory', 'tegra'] | ['c'] | 1 | 175 | 0 | --- diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c --- a/drivers/memory/tegra/tegra20-emc.c +++ b/drivers/memory/tegra/tegra20-emc.c +#include <linux/debugfs.h> + + struct { + struct dentry *root; + unsigned long min_rate; + unsigned long max_rate; + } debugfs; +/* + * debugfs interface + * + * the memory controller driver exposes some files in debugfs that can be used + * to control the emc frequency. the top-level directory can be found here: + * + * /sys/kernel/debug/emc + * + * it contains the following files: + * + * - available_rates: this file contains a list of valid, space-separated + * emc frequencies. + * + * - min_rate: writing a value to this file sets the given frequency as the + * floor of the permitted range. if this is higher than the currently + * configured emc frequency, this will cause the frequency to be + * increased so that it stays within the valid range. + * + * - max_rate: similarily to the min_rate file, writing a value to this file + * sets the given frequency as the ceiling of the permitted range. if + * the value is lower than the currently configured emc frequency, this + * will cause the frequency to be decreased so that it stays within the + * valid range. + */ + +static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) +{ + unsigned int i; + + for (i = 0; i < emc->num_timings; i++) + if (rate == emc->timings[i].rate) + return true; + + return false; +} + +static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) +{ + struct tegra_emc *emc = s->private; + const char *prefix = ""; + unsigned int i; + + for (i = 0; i < emc->num_timings; i++) { + seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); + prefix = " "; + } + + seq_puts(s, " "); + + return 0; +} + +static int tegra_emc_debug_available_rates_open(struct inode *inode, + struct file *file) +{ + return single_open(file, tegra_emc_debug_available_rates_show, + inode->i_private); +} + +static const struct file_operations tegra_emc_debug_available_rates_fops = { + .open = tegra_emc_debug_available_rates_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) +{ + struct tegra_emc *emc = data; + + *rate = emc->debugfs.min_rate; + + return 0; +} + +static int tegra_emc_debug_min_rate_set(void *data, u64 rate) +{ + struct tegra_emc *emc = data; + int err; + + if (!tegra_emc_validate_rate(emc, rate)) + return -einval; + + err = clk_set_min_rate(emc->clk, rate); + if (err < 0) + return err; + + emc->debugfs.min_rate = rate; + + return 0; +} + +define_simple_attribute(tegra_emc_debug_min_rate_fops, + tegra_emc_debug_min_rate_get, + tegra_emc_debug_min_rate_set, "%llu "); + +static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) +{ + struct tegra_emc *emc = data; + + *rate = emc->debugfs.max_rate; + + return 0; +} + +static int tegra_emc_debug_max_rate_set(void *data, u64 rate) +{ + struct tegra_emc *emc = data; + int err; + + if (!tegra_emc_validate_rate(emc, rate)) + return -einval; + + err = clk_set_max_rate(emc->clk, rate); + if (err < 0) + return err; + + emc->debugfs.max_rate = rate; + + return 0; +} + +define_simple_attribute(tegra_emc_debug_max_rate_fops, + tegra_emc_debug_max_rate_get, + tegra_emc_debug_max_rate_set, "%llu "); + +static void tegra_emc_debugfs_init(struct tegra_emc *emc) +{ + struct device *dev = emc->dev; + unsigned int i; + int err; + + emc->debugfs.min_rate = ulong_max; + emc->debugfs.max_rate = 0; + + for (i = 0; i < emc->num_timings; i++) { + if (emc->timings[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate = emc->timings[i].rate; + + if (emc->timings[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate = emc->timings[i].rate; + } + + err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, + emc->debugfs.max_rate); + if (err < 0) { + dev_err(dev, "failed to set rate range [%lu-%lu] for %pc ", + emc->debugfs.min_rate, emc->debugfs.max_rate, + emc->clk); + } + + emc->debugfs.root = debugfs_create_dir("emc", null); + if (!emc->debugfs.root) { + dev_err(emc->dev, "failed to create debugfs directory "); + return; + } + + debugfs_create_file("available_rates", s_irugo, emc->debugfs.root, + emc, &tegra_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", s_irugo | s_iwusr, emc->debugfs.root, + emc, &tegra_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", s_irugo | s_iwusr, emc->debugfs.root, + emc, &tegra_emc_debug_max_rate_fops); +} + + platform_set_drvdata(pdev, emc); + tegra_emc_debugfs_init(emc); + | Various | 8209eefa3d379dd453d67cd94484040216ffc68c | thierry reding | drivers | memory | tegra |
memory: tegra: implement emc debugfs interface on tegra30 | a common debugfs interface is already available on tegra20, tegra124, tegra186 and tegra194. implement the same interface on tegra30 to enable testing of the emc frequency scaling code using a unified interface. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | implement emc debugfs interface on tegra20 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['memory', 'tegra'] | ['c'] | 1 | 173 | 0 | --- diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c +#include <linux/debugfs.h> + + struct { + struct dentry *root; + unsigned long min_rate; + unsigned long max_rate; + } debugfs; +/* + * debugfs interface + * + * the memory controller driver exposes some files in debugfs that can be used + * to control the emc frequency. the top-level directory can be found here: + * + * /sys/kernel/debug/emc + * + * it contains the following files: + * + * - available_rates: this file contains a list of valid, space-separated + * emc frequencies. + * + * - min_rate: writing a value to this file sets the given frequency as the + * floor of the permitted range. if this is higher than the currently + * configured emc frequency, this will cause the frequency to be + * increased so that it stays within the valid range. + * + * - max_rate: similarily to the min_rate file, writing a value to this file + * sets the given frequency as the ceiling of the permitted range. if + * the value is lower than the currently configured emc frequency, this + * will cause the frequency to be decreased so that it stays within the + * valid range. + */ + +static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) +{ + unsigned int i; + + for (i = 0; i < emc->num_timings; i++) + if (rate == emc->timings[i].rate) + return true; + + return false; +} + +static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data) +{ + struct tegra_emc *emc = s->private; + const char *prefix = ""; + unsigned int i; + + for (i = 0; i < emc->num_timings; i++) { + seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); + prefix = " "; + } + + seq_puts(s, " "); + + return 0; +} + +static int tegra_emc_debug_available_rates_open(struct inode *inode, + struct file *file) +{ + return single_open(file, tegra_emc_debug_available_rates_show, + inode->i_private); +} + +static const struct file_operations tegra_emc_debug_available_rates_fops = { + .open = tegra_emc_debug_available_rates_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int tegra_emc_debug_min_rate_get(void *data, u64 *rate) +{ + struct tegra_emc *emc = data; + + *rate = emc->debugfs.min_rate; + + return 0; +} + +static int tegra_emc_debug_min_rate_set(void *data, u64 rate) +{ + struct tegra_emc *emc = data; + int err; + + if (!tegra_emc_validate_rate(emc, rate)) + return -einval; + + err = clk_set_min_rate(emc->clk, rate); + if (err < 0) + return err; + + emc->debugfs.min_rate = rate; + + return 0; +} + +define_simple_attribute(tegra_emc_debug_min_rate_fops, + tegra_emc_debug_min_rate_get, + tegra_emc_debug_min_rate_set, "%llu "); + +static int tegra_emc_debug_max_rate_get(void *data, u64 *rate) +{ + struct tegra_emc *emc = data; + + *rate = emc->debugfs.max_rate; + + return 0; +} + +static int tegra_emc_debug_max_rate_set(void *data, u64 rate) +{ + struct tegra_emc *emc = data; + int err; + + if (!tegra_emc_validate_rate(emc, rate)) + return -einval; + + err = clk_set_max_rate(emc->clk, rate); + if (err < 0) + return err; + + emc->debugfs.max_rate = rate; + + return 0; +} + +define_simple_attribute(tegra_emc_debug_max_rate_fops, + tegra_emc_debug_max_rate_get, + tegra_emc_debug_max_rate_set, "%llu "); + +static void tegra_emc_debugfs_init(struct tegra_emc *emc) +{ + struct device *dev = emc->dev; + unsigned int i; + int err; + + emc->debugfs.min_rate = ulong_max; + emc->debugfs.max_rate = 0; + + for (i = 0; i < emc->num_timings; i++) { + if (emc->timings[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate = emc->timings[i].rate; + + if (emc->timings[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate = emc->timings[i].rate; + } + + err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, + emc->debugfs.max_rate); + if (err < 0) { + dev_err(dev, "failed to set rate range [%lu-%lu] for %pc ", + emc->debugfs.min_rate, emc->debugfs.max_rate, + emc->clk); + } + + emc->debugfs.root = debugfs_create_dir("emc", null); + if (!emc->debugfs.root) { + dev_err(emc->dev, "failed to create debugfs directory "); + return; + } + + debugfs_create_file("available_rates", s_irugo, emc->debugfs.root, + emc, &tegra_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", s_irugo | s_iwusr, emc->debugfs.root, + emc, &tegra_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", s_irugo | s_iwusr, emc->debugfs.root, + emc, &tegra_emc_debug_max_rate_fops); +} + + tegra_emc_debugfs_init(emc); | Various | 8cee32b400404b7ab5219dfcbe412c90bd0c7ada | thierry reding | drivers | memory | tegra |
misc: alcor_pci: add au6625 to list of supported pci_ids | i have added the au6625 pci_id to the list of supported ids: alcor_pci.c // added au6625s id to the array of supported devices alcor_pci.h // added entry to define the pci id | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add au6625 to list of supported pci_ids | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['misc', 'alcor_pci'] | ['c', 'h'] | 2 | 8 | 1 | --- diff --git a/drivers/misc/cardreader/alcor_pci.c b/drivers/misc/cardreader/alcor_pci.c --- a/drivers/misc/cardreader/alcor_pci.c +++ b/drivers/misc/cardreader/alcor_pci.c +static const struct alcor_dev_cfg au6625_cfg = { + .dma = 0, +}; + - { }, + { pci_device(pci_id_alcor_micro, pci_id_au6625), + .driver_data = (kernel_ulong_t)&au6625_cfg }, + {}, diff --git a/include/linux/alcor_pci.h b/include/linux/alcor_pci.h --- a/include/linux/alcor_pci.h +++ b/include/linux/alcor_pci.h +#define pci_id_au6625 0x6625 | Various | 444972b2b268c3272d39105bdc8d1266177f5d42 | rhys perry | drivers | misc | cardreader |
nvmem: add qti sdam driver | qti sdam driver allows pmic peripherals to access the shared memory that is available on qti pmics. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add qti sdam driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['nvmem'] | ['c', 'kconfig', 'makefile'] | 3 | 202 | 0 | --- diff --git a/drivers/nvmem/kconfig b/drivers/nvmem/kconfig --- a/drivers/nvmem/kconfig +++ b/drivers/nvmem/kconfig +config nvmem_spmi_sdam + tristate "spmi sdam support" + depends on spmi + help + this driver supports the shared direct access memory module on + qualcomm technologies, inc. pmics. it provides the clients + an interface to read/write to the sdam module's shared memory. + diff --git a/drivers/nvmem/makefile b/drivers/nvmem/makefile --- a/drivers/nvmem/makefile +++ b/drivers/nvmem/makefile +obj-$(config_nvmem_spmi_sdam) += nvmem_qcom-spmi-sdam.o +nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o diff --git a/drivers/nvmem/qcom-spmi-sdam.c b/drivers/nvmem/qcom-spmi-sdam.c --- /dev/null +++ b/drivers/nvmem/qcom-spmi-sdam.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2017 the linux foundation. all rights reserved. + */ + +#include <linux/device.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_platform.h> +#include <linux/nvmem-provider.h> +#include <linux/regmap.h> + +#define sdam_mem_start 0x40 +#define register_map_id 0x40 +#define register_map_version 0x41 +#define sdam_size 0x44 +#define sdam_pbs_trig_set 0xe5 +#define sdam_pbs_trig_clr 0xe6 + +struct sdam_chip { + struct platform_device *pdev; + struct regmap *regmap; + struct nvmem_config sdam_config; + unsigned int base; + unsigned int size; +}; + +/* read only register offsets */ +static const u8 sdam_ro_map[] = { + register_map_id, + register_map_version, + sdam_size +}; + +static bool sdam_is_valid(struct sdam_chip *sdam, unsigned int offset, + size_t len) +{ + unsigned int sdam_mem_end = sdam_mem_start + sdam->size - 1; + + if (!len) + return false; + + if (offset >= sdam_mem_start && offset <= sdam_mem_end + && (offset + len - 1) <= sdam_mem_end) + return true; + else if ((offset == sdam_pbs_trig_set || offset == sdam_pbs_trig_clr) + && (len == 1)) + return true; + + return false; +} + +static bool sdam_is_ro(unsigned int offset, size_t len) +{ + int i; + + for (i = 0; i < array_size(sdam_ro_map); i++) + if (offset <= sdam_ro_map[i] && (offset + len) > sdam_ro_map[i]) + return true; + + return false; +} + +static int sdam_read(void *priv, unsigned int offset, void *val, + size_t bytes) +{ + struct sdam_chip *sdam = priv; + struct device *dev = &sdam->pdev->dev; + int rc; + + if (!sdam_is_valid(sdam, offset, bytes)) { + dev_err(dev, "invalid sdam offset %#x len=%zd ", + offset, bytes); + return -einval; + } + + rc = regmap_bulk_read(sdam->regmap, sdam->base + offset, val, bytes); + if (rc < 0) + dev_err(dev, "failed to read sdam offset %#x len=%zd, rc=%d ", + offset, bytes, rc); + + return rc; +} + +static int sdam_write(void *priv, unsigned int offset, void *val, + size_t bytes) +{ + struct sdam_chip *sdam = priv; + struct device *dev = &sdam->pdev->dev; + int rc; + + if (!sdam_is_valid(sdam, offset, bytes)) { + dev_err(dev, "invalid sdam offset %#x len=%zd ", + offset, bytes); + return -einval; + } + + if (sdam_is_ro(offset, bytes)) { + dev_err(dev, "invalid write offset %#x len=%zd ", + offset, bytes); + return -einval; + } + + rc = regmap_bulk_write(sdam->regmap, sdam->base + offset, val, bytes); + if (rc < 0) + dev_err(dev, "failed to write sdam offset %#x len=%zd, rc=%d ", + offset, bytes, rc); + + return rc; +} + +static int sdam_probe(struct platform_device *pdev) +{ + struct sdam_chip *sdam; + struct nvmem_device *nvmem; + unsigned int val; + int rc; + + sdam = devm_kzalloc(&pdev->dev, sizeof(*sdam), gfp_kernel); + if (!sdam) + return -enomem; + + sdam->regmap = dev_get_regmap(pdev->dev.parent, null); + if (!sdam->regmap) { + dev_err(&pdev->dev, "failed to get regmap handle "); + return -enxio; + } + + rc = of_property_read_u32(pdev->dev.of_node, "reg", &sdam->base); + if (rc < 0) { + dev_err(&pdev->dev, "failed to get sdam base, rc=%d ", rc); + return -einval; + } + + rc = regmap_read(sdam->regmap, sdam->base + sdam_size, &val); + if (rc < 0) { + dev_err(&pdev->dev, "failed to read sdam_size rc=%d ", rc); + return -einval; + } + sdam->size = val * 32; + + sdam->sdam_config.dev = &pdev->dev; + sdam->sdam_config.name = "spmi_sdam"; + sdam->sdam_config.id = pdev->id; + sdam->sdam_config.owner = this_module, + sdam->sdam_config.stride = 1; + sdam->sdam_config.word_size = 1; + sdam->sdam_config.reg_read = sdam_read; + sdam->sdam_config.reg_write = sdam_write; + sdam->sdam_config.priv = sdam; + + nvmem = devm_nvmem_register(&pdev->dev, &sdam->sdam_config); + if (is_err(nvmem)) { + dev_err(&pdev->dev, + "failed to register sdam nvmem device rc=%ld ", + ptr_err(nvmem)); + return -enxio; + } + dev_dbg(&pdev->dev, + "sdam base=%#x size=%u registered successfully ", + sdam->base, sdam->size); + + return 0; +} + +static const struct of_device_id sdam_match_table[] = { + { .compatible = "qcom,spmi-sdam" }, + {}, +}; + +static struct platform_driver sdam_driver = { + .driver = { + .name = "qcom,spmi-sdam", + .of_match_table = sdam_match_table, + }, + .probe = sdam_probe, +}; + +static int __init sdam_init(void) +{ + return platform_driver_register(&sdam_driver); +} +subsys_initcall(sdam_init); + +static void __exit sdam_exit(void) +{ + return platform_driver_unregister(&sdam_driver); +} +module_exit(sdam_exit); + +module_description("qcom spmi sdam driver"); +module_license("gpl v2"); | Various | 40ce9798794f972961b5a1c54773ae3daf42cf29 | anirudh ghayal | drivers | nvmem | |
nvmem: add support for the write-protect pin | the write-protect pin handling looks like a standard property that could benefit other users if available in the core nvmem framework. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add support for the write-protect pin | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['nvmem'] | ['c', 'h'] | 3 | 22 | 2 | --- diff --git a/drivers/nvmem/core.c b/drivers/nvmem/core.c --- a/drivers/nvmem/core.c +++ b/drivers/nvmem/core.c +#include <linux/gpio/consumer.h> - if (nvmem->reg_write) - return nvmem->reg_write(nvmem->priv, offset, val, bytes); + int ret; + + if (nvmem->reg_write) { + gpiod_set_value_cansleep(nvmem->wp_gpio, 0); + ret = nvmem->reg_write(nvmem->priv, offset, val, bytes); + gpiod_set_value_cansleep(nvmem->wp_gpio, 1); + return ret; + } + if (config->wp_gpio) + nvmem->wp_gpio = config->wp_gpio; + else + nvmem->wp_gpio = gpiod_get_optional(config->dev, "wp", + gpiod_out_high); + if (is_err(nvmem->wp_gpio)) + return ptr_err(nvmem->wp_gpio); + diff --git a/drivers/nvmem/nvmem.h b/drivers/nvmem/nvmem.h --- a/drivers/nvmem/nvmem.h +++ b/drivers/nvmem/nvmem.h +#include <linux/gpio/consumer.h> + struct gpio_desc *wp_gpio; diff --git a/include/linux/nvmem-provider.h b/include/linux/nvmem-provider.h --- a/include/linux/nvmem-provider.h +++ b/include/linux/nvmem-provider.h +#include <linux/gpio/consumer.h> + * @wp-gpio: write protect pin + struct gpio_desc *wp_gpio; | Various | 2a127da461a9d8d97782d6e82b227041393eb4d2 | khouloud touil | include | linux | |
remoteproc/mediatek: add scp support for mt8183 | provide a basic driver to control cortex m4 co-processor | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add scp support for mt8183 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['remoteproc/mediatek'] | ['h', 'kconfig', 'c', 'makefile'] | 6 | 995 | 0 | --- diff --git a/drivers/remoteproc/kconfig b/drivers/remoteproc/kconfig --- a/drivers/remoteproc/kconfig +++ b/drivers/remoteproc/kconfig +config mtk_scp + tristate "mediatek scp support" + depends on arch_mediatek + help + say y here to support mediatek's system companion processor (scp) via + the remote processor framework. + + it's safe to say n here. + diff --git a/drivers/remoteproc/makefile b/drivers/remoteproc/makefile --- a/drivers/remoteproc/makefile +++ b/drivers/remoteproc/makefile +obj-$(config_mtk_scp) += mtk_scp.o mtk_scp_ipi.o diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h --- /dev/null +++ b/drivers/remoteproc/mtk_common.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2019 mediatek inc. + */ + +#ifndef __rproc_mtk_common_h +#define __rproc_mtk_common_h + +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/remoteproc.h> +#include <linux/remoteproc/mtk_scp.h> + +#define mt8183_sw_rstn 0x0 +#define mt8183_sw_rstn_bit bit(0) +#define mt8183_scp_to_host 0x1c +#define mt8183_scp_ipc_int_bit bit(0) +#define mt8183_scp_wdt_int_bit bit(8) +#define mt8183_host_to_scp 0x28 +#define mt8183_host_ipc_int_bit bit(0) +#define mt8183_wdt_cfg 0x84 +#define mt8183_scp_clk_sw_sel 0x4000 +#define mt8183_scp_clk_div_sel 0x4024 +#define mt8183_scp_sram_pdn 0x402c +#define mt8183_scp_l1_sram_pd 0x4080 +#define mt8183_scp_tcm_tail_sram_pd 0x4094 + +#define mt8183_scp_cache_sel(x) (0x14000 + (x) * 0x3000) +#define mt8183_scp_cache_con mt8183_scp_cache_sel(0) +#define mt8183_scp_dcache_con mt8183_scp_cache_sel(1) +#define mt8183_scp_cachesize_8kb bit(8) +#define mt8183_scp_cache_con_wayen bit(10) + +#define scp_fw_ver_len 32 +#define scp_share_buffer_size 288 + +struct scp_run { + u32 signaled; + s8 fw_ver[scp_fw_ver_len]; + u32 dec_capability; + u32 enc_capability; + wait_queue_head_t wq; +}; + +struct scp_ipi_desc { + /* for protecting handler. */ + struct mutex lock; + scp_ipi_handler_t handler; + void *priv; +}; + +struct mtk_scp { + struct device *dev; + struct rproc *rproc; + struct clk *clk; + void __iomem *reg_base; + void __iomem *sram_base; + size_t sram_size; + + struct mtk_share_obj __iomem *recv_buf; + struct mtk_share_obj __iomem *send_buf; + struct scp_run run; + /* to prevent multiple ipi_send run concurrently. */ + struct mutex send_lock; + struct scp_ipi_desc ipi_desc[scp_ipi_max]; + bool ipi_id_ack[scp_ipi_max]; + wait_queue_head_t ack_wq; + + void __iomem *cpu_addr; + phys_addr_t phys_addr; + size_t dram_size; +}; + +/** + * struct mtk_share_obj - sram buffer shared with ap and scp + * + * @id: ipi id + * @len: share buffer length + * @share_buf: share buffer data + */ +struct mtk_share_obj { + u32 id; + u32 len; + u8 share_buf[scp_share_buffer_size]; +}; + +void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len); +void scp_ipi_lock(struct mtk_scp *scp, u32 id); +void scp_ipi_unlock(struct mtk_scp *scp, u32 id); + +#endif diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c --- /dev/null +++ b/drivers/remoteproc/mtk_scp.c +// spdx-license-identifier: gpl-2.0 +// +// copyright (c) 2019 mediatek inc. + +#include <asm/barrier.h> +#include <linux/clk.h> +#include <linux/dma-mapping.h> +#include <linux/err.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/of_reserved_mem.h> +#include <linux/platform_device.h> +#include <linux/remoteproc.h> +#include <linux/remoteproc/mtk_scp.h> + +#include "mtk_common.h" +#include "remoteproc_internal.h" + +#define max_code_size 0x500000 +#define scp_fw_end 0x7c000 + +/** + * scp_get() - get a reference to scp. + * + * @pdev: the platform device of the module requesting scp platform + * device for using scp api. + * + * return: return null if failed. otherwise reference to scp. + **/ +struct mtk_scp *scp_get(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *scp_node; + struct platform_device *scp_pdev; + + scp_node = of_parse_phandle(dev->of_node, "mediatek,scp", 0); + if (!scp_node) { + dev_err(dev, "can't get scp node "); + return null; + } + + scp_pdev = of_find_device_by_node(scp_node); + of_node_put(scp_node); + + if (warn_on(!scp_pdev)) { + dev_err(dev, "scp pdev failed "); + return null; + } + + return platform_get_drvdata(scp_pdev); +} +export_symbol_gpl(scp_get); + +/** + * scp_put() - "free" the scp + * + * @scp: mtk_scp structure from scp_get(). + **/ +void scp_put(struct mtk_scp *scp) +{ + put_device(scp->dev); +} +export_symbol_gpl(scp_put); + +static void scp_wdt_handler(struct mtk_scp *scp, u32 scp_to_host) +{ + dev_err(scp->dev, "scp watchdog timeout! 0x%x", scp_to_host); + rproc_report_crash(scp->rproc, rproc_watchdog); +} + +static void scp_init_ipi_handler(void *data, unsigned int len, void *priv) +{ + struct mtk_scp *scp = (struct mtk_scp *)priv; + struct scp_run *run = (struct scp_run *)data; + + scp->run.signaled = run->signaled; + strscpy(scp->run.fw_ver, run->fw_ver, scp_fw_ver_len); + scp->run.dec_capability = run->dec_capability; + scp->run.enc_capability = run->enc_capability; + wake_up_interruptible(&scp->run.wq); +} + +static void scp_ipi_handler(struct mtk_scp *scp) +{ + struct mtk_share_obj __iomem *rcv_obj = scp->recv_buf; + struct scp_ipi_desc *ipi_desc = scp->ipi_desc; + u8 tmp_data[scp_share_buffer_size]; + scp_ipi_handler_t handler; + u32 id = readl(&rcv_obj->id); + u32 len = readl(&rcv_obj->len); + + if (len > scp_share_buffer_size) { + dev_err(scp->dev, "ipi message too long (len %d, max %d)", len, + scp_share_buffer_size); + return; + } + if (id >= scp_ipi_max) { + dev_err(scp->dev, "no such ipi id = %d ", id); + return; + } + + scp_ipi_lock(scp, id); + handler = ipi_desc[id].handler; + if (!handler) { + dev_err(scp->dev, "no such ipi id = %d ", id); + scp_ipi_unlock(scp, id); + return; + } + + memcpy_fromio(tmp_data, &rcv_obj->share_buf, len); + handler(tmp_data, len, ipi_desc[id].priv); + scp_ipi_unlock(scp, id); + + scp->ipi_id_ack[id] = true; + wake_up(&scp->ack_wq); +} + +static int scp_ipi_init(struct mtk_scp *scp) +{ + size_t send_offset = scp_fw_end - sizeof(struct mtk_share_obj); + size_t recv_offset = send_offset - sizeof(struct mtk_share_obj); + + /* disable scp to host interrupt */ + writel(mt8183_scp_ipc_int_bit, scp->reg_base + mt8183_scp_to_host); + + /* shared buffer initialization */ + scp->recv_buf = + (struct mtk_share_obj __iomem *)(scp->sram_base + recv_offset); + scp->send_buf = + (struct mtk_share_obj __iomem *)(scp->sram_base + send_offset); + memset_io(scp->recv_buf, 0, sizeof(scp->recv_buf)); + memset_io(scp->send_buf, 0, sizeof(scp->send_buf)); + + return 0; +} + +static void scp_reset_assert(const struct mtk_scp *scp) +{ + u32 val; + + val = readl(scp->reg_base + mt8183_sw_rstn); + val &= ~mt8183_sw_rstn_bit; + writel(val, scp->reg_base + mt8183_sw_rstn); +} + +static void scp_reset_deassert(const struct mtk_scp *scp) +{ + u32 val; + + val = readl(scp->reg_base + mt8183_sw_rstn); + val |= mt8183_sw_rstn_bit; + writel(val, scp->reg_base + mt8183_sw_rstn); +} + +static irqreturn_t scp_irq_handler(int irq, void *priv) +{ + struct mtk_scp *scp = priv; + u32 scp_to_host; + int ret; + + ret = clk_prepare_enable(scp->clk); + if (ret) { + dev_err(scp->dev, "failed to enable clocks "); + return irq_none; + } + + scp_to_host = readl(scp->reg_base + mt8183_scp_to_host); + if (scp_to_host & mt8183_scp_ipc_int_bit) + scp_ipi_handler(scp); + else + scp_wdt_handler(scp, scp_to_host); + + /* scp won't send another interrupt until we set scp_to_host to 0. */ + writel(mt8183_scp_ipc_int_bit | mt8183_scp_wdt_int_bit, + scp->reg_base + mt8183_scp_to_host); + clk_disable_unprepare(scp->clk); + + return irq_handled; +} + +static int scp_elf_load_segments(struct rproc *rproc, const struct firmware *fw) +{ + struct device *dev = &rproc->dev; + struct elf32_hdr *ehdr; + struct elf32_phdr *phdr; + int i, ret = 0; + const u8 *elf_data = fw->data; + + ehdr = (struct elf32_hdr *)elf_data; + phdr = (struct elf32_phdr *)(elf_data + ehdr->e_phoff); + + /* go through the available elf segments */ + for (i = 0; i < ehdr->e_phnum; i++, phdr++) { + u32 da = phdr->p_paddr; + u32 memsz = phdr->p_memsz; + u32 filesz = phdr->p_filesz; + u32 offset = phdr->p_offset; + void __iomem *ptr; + + if (phdr->p_type != pt_load) + continue; + + dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x ", + phdr->p_type, da, memsz, filesz); + + if (filesz > memsz) { + dev_err(dev, "bad phdr filesz 0x%x memsz 0x%x ", + filesz, memsz); + ret = -einval; + break; + } + + if (offset + filesz > fw->size) { + dev_err(dev, "truncated fw: need 0x%x avail 0x%zx ", + offset + filesz, fw->size); + ret = -einval; + break; + } + + /* grab the kernel address for this device address */ + ptr = (void __iomem *)rproc_da_to_va(rproc, da, memsz); + if (!ptr) { + dev_err(dev, "bad phdr da 0x%x mem 0x%x ", da, memsz); + ret = -einval; + break; + } + + /* put the segment where the remote processor expects it */ + if (phdr->p_filesz) + scp_memcpy_aligned(ptr, elf_data + phdr->p_offset, + filesz); + } + + return ret; +} + +static int scp_load(struct rproc *rproc, const struct firmware *fw) +{ + const struct mtk_scp *scp = rproc->priv; + struct device *dev = scp->dev; + int ret; + + ret = clk_prepare_enable(scp->clk); + if (ret) { + dev_err(dev, "failed to enable clocks "); + return ret; + } + + /* hold scp in reset while loading fw. */ + scp_reset_assert(scp); + + /* reset clocks before loading fw */ + writel(0x0, scp->reg_base + mt8183_scp_clk_sw_sel); + writel(0x0, scp->reg_base + mt8183_scp_clk_div_sel); + + /* initialize tcm before loading fw. */ + writel(0x0, scp->reg_base + mt8183_scp_l1_sram_pd); + writel(0x0, scp->reg_base + mt8183_scp_tcm_tail_sram_pd); + + /* turn on the power of scp's sram before using it. */ + writel(0x0, scp->reg_base + mt8183_scp_sram_pdn); + + /* + * set i-cache and d-cache size before loading scp fw. + * scp sram logical address may change when cache size setting differs. + */ + writel(mt8183_scp_cache_con_wayen | mt8183_scp_cachesize_8kb, + scp->reg_base + mt8183_scp_cache_con); + writel(mt8183_scp_cachesize_8kb, scp->reg_base + mt8183_scp_dcache_con); + + ret = scp_elf_load_segments(rproc, fw); + clk_disable_unprepare(scp->clk); + + return ret; +} + +static int scp_start(struct rproc *rproc) +{ + struct mtk_scp *scp = (struct mtk_scp *)rproc->priv; + struct device *dev = scp->dev; + struct scp_run *run = &scp->run; + int ret; + + ret = clk_prepare_enable(scp->clk); + if (ret) { + dev_err(dev, "failed to enable clocks "); + return ret; + } + + run->signaled = false; + + scp_reset_deassert(scp); + + ret = wait_event_interruptible_timeout( + run->wq, + run->signaled, + msecs_to_jiffies(2000)); + + if (ret == 0) { + dev_err(dev, "wait scp initialization timeout! "); + ret = -etime; + goto stop; + } + if (ret == -erestartsys) { + dev_err(dev, "wait scp interrupted by a signal! "); + goto stop; + } + clk_disable_unprepare(scp->clk); + dev_info(dev, "scp is ready. fw version %s ", run->fw_ver); + + return 0; + +stop: + scp_reset_assert(scp); + clk_disable_unprepare(scp->clk); + return ret; +} + +static void *scp_da_to_va(struct rproc *rproc, u64 da, int len) +{ + struct mtk_scp *scp = (struct mtk_scp *)rproc->priv; + int offset; + + if (da < scp->sram_size) { + offset = da; + if (offset >= 0 && (offset + len) < scp->sram_size) + return (void __force *)scp->sram_base + offset; + } else { + offset = da - scp->phys_addr; + if (offset >= 0 && (offset + len) < scp->dram_size) + return (void __force *)scp->cpu_addr + offset; + } + + return null; +} + +static int scp_stop(struct rproc *rproc) +{ + struct mtk_scp *scp = (struct mtk_scp *)rproc->priv; + int ret; + + ret = clk_prepare_enable(scp->clk); + if (ret) { + dev_err(scp->dev, "failed to enable clocks "); + return ret; + } + + scp_reset_assert(scp); + /* disable scp watchdog */ + writel(0, scp->reg_base + mt8183_wdt_cfg); + clk_disable_unprepare(scp->clk); + + return 0; +} + +static const struct rproc_ops scp_ops = { + .start = scp_start, + .stop = scp_stop, + .load = scp_load, + .da_to_va = scp_da_to_va, +}; + +/** + * scp_get_device() - get device struct of scp + * + * @scp: mtk_scp structure + **/ +struct device *scp_get_device(struct mtk_scp *scp) +{ + return scp->dev; +} +export_symbol_gpl(scp_get_device); + +/** + * scp_get_rproc() - get rproc struct of scp + * + * @scp: mtk_scp structure + **/ +struct rproc *scp_get_rproc(struct mtk_scp *scp) +{ + return scp->rproc; +} +export_symbol_gpl(scp_get_rproc); + +/** + * scp_get_vdec_hw_capa() - get video decoder hardware capability + * + * @scp: mtk_scp structure + * + * return: video decoder hardware capability + **/ +unsigned int scp_get_vdec_hw_capa(struct mtk_scp *scp) +{ + return scp->run.dec_capability; +} +export_symbol_gpl(scp_get_vdec_hw_capa); + +/** + * scp_get_venc_hw_capa() - get video encoder hardware capability + * + * @scp: mtk_scp structure + * + * return: video encoder hardware capability + **/ +unsigned int scp_get_venc_hw_capa(struct mtk_scp *scp) +{ + return scp->run.enc_capability; +} +export_symbol_gpl(scp_get_venc_hw_capa); + +/** + * scp_mapping_dm_addr() - mapping sram/dram to kernel virtual address + * + * @scp: mtk_scp structure + * @mem_addr: scp views memory address + * + * mapping the scp's sram address / + * dmem (data extended memory) memory address / + * working buffer memory address to + * kernel virtual address. + * + * return: return err_ptr(-einval) if mapping failed, + * otherwise the mapped kernel virtual address + **/ +void *scp_mapping_dm_addr(struct mtk_scp *scp, u32 mem_addr) +{ + void *ptr; + + ptr = scp_da_to_va(scp->rproc, mem_addr, 0); + if (!ptr) + return err_ptr(-einval); + + return ptr; +} +export_symbol_gpl(scp_mapping_dm_addr); + +static int scp_map_memory_region(struct mtk_scp *scp) +{ + int ret; + + ret = of_reserved_mem_device_init(scp->dev); + if (ret) { + dev_err(scp->dev, "failed to assign memory-region: %d ", ret); + return -enomem; + } + + /* reserved scp code size */ + scp->dram_size = max_code_size; + scp->cpu_addr = dma_alloc_coherent(scp->dev, scp->dram_size, + &scp->phys_addr, gfp_kernel); + if (!scp->cpu_addr) + return -enomem; + + return 0; +} + +static void scp_unmap_memory_region(struct mtk_scp *scp) +{ + dma_free_coherent(scp->dev, scp->dram_size, scp->cpu_addr, + scp->phys_addr); + of_reserved_mem_device_release(scp->dev); +} + +static int scp_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct mtk_scp *scp; + struct rproc *rproc; + struct resource *res; + char *fw_name = "scp.img"; + int ret, i; + + rproc = rproc_alloc(dev, + np->name, + &scp_ops, + fw_name, + sizeof(*scp)); + if (!rproc) { + dev_err(dev, "unable to allocate remoteproc "); + return -enomem; + } + + scp = (struct mtk_scp *)rproc->priv; + scp->rproc = rproc; + scp->dev = dev; + platform_set_drvdata(pdev, scp); + + res = platform_get_resource_byname(pdev, ioresource_mem, "sram"); + scp->sram_base = devm_ioremap_resource(dev, res); + if (is_err((__force void *)scp->sram_base)) { + dev_err(dev, "failed to parse and map sram memory "); + ret = ptr_err((__force void *)scp->sram_base); + goto free_rproc; + } + scp->sram_size = resource_size(res); + + mutex_init(&scp->send_lock); + for (i = 0; i < scp_ipi_max; i++) + mutex_init(&scp->ipi_desc[i].lock); + + res = platform_get_resource_byname(pdev, ioresource_mem, "cfg"); + scp->reg_base = devm_ioremap_resource(dev, res); + if (is_err((__force void *)scp->reg_base)) { + dev_err(dev, "failed to parse and map cfg memory "); + ret = ptr_err((__force void *)scp->reg_base); + goto destroy_mutex; + } + + ret = scp_map_memory_region(scp); + if (ret) + goto destroy_mutex; + + scp->clk = devm_clk_get(dev, "main"); + if (is_err(scp->clk)) { + dev_err(dev, "failed to get clock "); + ret = ptr_err(scp->clk); + goto release_dev_mem; + } + + ret = clk_prepare_enable(scp->clk); + if (ret) { + dev_err(dev, "failed to enable clocks "); + goto release_dev_mem; + } + + ret = scp_ipi_init(scp); + clk_disable_unprepare(scp->clk); + if (ret) { + dev_err(dev, "failed to init ipi "); + goto release_dev_mem; + } + + /* register scp initialization ipi */ + ret = scp_ipi_register(scp, scp_ipi_init, scp_init_ipi_handler, scp); + if (ret) { + dev_err(dev, "failed to register ipi_scp_init "); + goto release_dev_mem; + } + + init_waitqueue_head(&scp->run.wq); + init_waitqueue_head(&scp->ack_wq); + + ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), null, + scp_irq_handler, irqf_oneshot, + pdev->name, scp); + + if (ret) { + dev_err(dev, "failed to request irq "); + goto unregister_ipi; + } + + ret = rproc_add(rproc); + if (ret) + goto unregister_ipi; + + return ret; + +unregister_ipi: + scp_ipi_unregister(scp, scp_ipi_init); +release_dev_mem: + scp_unmap_memory_region(scp); +destroy_mutex: + for (i = 0; i < scp_ipi_max; i++) + mutex_destroy(&scp->ipi_desc[i].lock); + mutex_destroy(&scp->send_lock); +free_rproc: + rproc_free(rproc); + + return ret; +} + +static int scp_remove(struct platform_device *pdev) +{ + struct mtk_scp *scp = platform_get_drvdata(pdev); + int i; + + rproc_del(scp->rproc); + scp_ipi_unregister(scp, scp_ipi_init); + scp_unmap_memory_region(scp); + for (i = 0; i < scp_ipi_max; i++) + mutex_destroy(&scp->ipi_desc[i].lock); + mutex_destroy(&scp->send_lock); + rproc_free(scp->rproc); + + return 0; +} + +static const struct of_device_id mtk_scp_of_match[] = { + { .compatible = "mediatek,mt8183-scp"}, + {}, +}; +module_device_table(of, mtk_scp_of_match); + +static struct platform_driver mtk_scp_driver = { + .probe = scp_probe, + .remove = scp_remove, + .driver = { + .name = "mtk-scp", + .of_match_table = of_match_ptr(mtk_scp_of_match), + }, +}; + +module_platform_driver(mtk_scp_driver); + +module_license("gpl v2"); +module_description("mediatek scp control driver"); diff --git a/drivers/remoteproc/mtk_scp_ipi.c b/drivers/remoteproc/mtk_scp_ipi.c --- /dev/null +++ b/drivers/remoteproc/mtk_scp_ipi.c +// spdx-license-identifier: gpl-2.0 +// +// copyright (c) 2019 mediatek inc. + +#include <asm/barrier.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/remoteproc/mtk_scp.h> + +#include "mtk_common.h" + +/** + * scp_ipi_register() - register an ipi function + * + * @scp: mtk_scp structure + * @id: ipi id + * @handler: ipi handler + * @priv: private data for ipi handler + * + * register an ipi function to receive ipi interrupt from scp. + * + * returns 0 if ipi registers successfully, -error on error. + */ +int scp_ipi_register(struct mtk_scp *scp, + u32 id, + scp_ipi_handler_t handler, + void *priv) +{ + if (!scp) { + dev_err(scp->dev, "scp device is not ready "); + return -eprobe_defer; + } + + if (warn_on(id >= scp_ipi_max) || warn_on(handler == null)) + return -einval; + + scp_ipi_lock(scp, id); + scp->ipi_desc[id].handler = handler; + scp->ipi_desc[id].priv = priv; + scp_ipi_unlock(scp, id); + + return 0; +} +export_symbol_gpl(scp_ipi_register); + +/** + * scp_ipi_unregister() - unregister an ipi function + * + * @scp: mtk_scp structure + * @id: ipi id + * + * unregister an ipi function to receive ipi interrupt from scp. + */ +void scp_ipi_unregister(struct mtk_scp *scp, u32 id) +{ + if (!scp) + return; + + if (warn_on(id >= scp_ipi_max)) + return; + + scp_ipi_lock(scp, id); + scp->ipi_desc[id].handler = null; + scp->ipi_desc[id].priv = null; + scp_ipi_unlock(scp, id); +} +export_symbol_gpl(scp_ipi_unregister); + +/* + * scp_memcpy_aligned() - copy src to dst, where dst is in scp sram region. + * + * @dst: pointer to the destination buffer, should be in scp sram region. + * @src: pointer to the source buffer. + * @len: length of the source buffer to be copied. + * + * since ap access of scp sram don't support byte write, this always write a + * full word at a time, and may cause some extra bytes to be written at the + * beginning & ending of dst. + */ +void scp_memcpy_aligned(void __iomem *dst, const void *src, unsigned int len) +{ + void __iomem *ptr; + u32 val; + unsigned int i = 0, remain; + + if (!is_aligned((unsigned long)dst, 4)) { + ptr = (void __iomem *)align_down((unsigned long)dst, 4); + i = 4 - (dst - ptr); + val = readl_relaxed(ptr); + memcpy((u8 *)&val + (4 - i), src, i); + writel_relaxed(val, ptr); + } + + __iowrite32_copy(dst + i, src + i, (len - i) / 4); + remain = (len - i) % 4; + + if (remain > 0) { + val = readl_relaxed(dst + len - remain); + memcpy(&val, src + len - remain, remain); + writel_relaxed(val, dst + len - remain); + } +} +export_symbol_gpl(scp_memcpy_aligned); + +/** + * scp_ipi_lock() - lock before operations of an ipi id + * + * @scp: mtk_scp structure + * @id: ipi id + * + * note: this should not be used by drivers other than mtk_scp. + */ +void scp_ipi_lock(struct mtk_scp *scp, u32 id) +{ + if (warn_on(id >= scp_ipi_max)) + return; + mutex_lock(&scp->ipi_desc[id].lock); +} +export_symbol_gpl(scp_ipi_lock); + +/** + * scp_ipi_lock() - unlock after operations of an ipi id + * + * @scp: mtk_scp structure + * @id: ipi id + * + * note: this should not be used by drivers other than mtk_scp. + */ +void scp_ipi_unlock(struct mtk_scp *scp, u32 id) +{ + if (warn_on(id >= scp_ipi_max)) + return; + mutex_unlock(&scp->ipi_desc[id].lock); +} +export_symbol_gpl(scp_ipi_unlock); + +/** + * scp_ipi_send() - send data from ap to scp. + * + * @scp: mtk_scp structure + * @id: ipi id + * @buf: the data buffer + * @len: the data buffer length + * @wait: number of msecs to wait for ack. 0 to skip waiting. + * + * this function is thread-safe. when this function returns, + * scp has received the data and starts the processing. + * when the processing completes, ipi handler registered + * by scp_ipi_register will be called in interrupt context. + * + * returns 0 if sending data successfully, -error on error. + **/ +int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, + unsigned int wait) +{ + struct mtk_share_obj __iomem *send_obj = scp->send_buf; + unsigned long timeout; + int ret; + + if (warn_on(id <= scp_ipi_init) || warn_on(id >= scp_ipi_max) || + warn_on(len > sizeof(send_obj->share_buf)) || warn_on(!buf)) + return -einval; + + mutex_lock(&scp->send_lock); + + ret = clk_prepare_enable(scp->clk); + if (ret) { + dev_err(scp->dev, "failed to enable clock "); + goto unlock_mutex; + } + + /* wait until scp receives the last command */ + timeout = jiffies + msecs_to_jiffies(2000); + do { + if (time_after(jiffies, timeout)) { + dev_err(scp->dev, "%s: ipi timeout! ", __func__); + ret = -etimedout; + goto clock_disable; + } + } while (readl(scp->reg_base + mt8183_host_to_scp)); + + scp_memcpy_aligned(send_obj->share_buf, buf, len); + + writel(len, &send_obj->len); + writel(id, &send_obj->id); + + scp->ipi_id_ack[id] = false; + /* send the command to scp */ + writel(mt8183_host_ipc_int_bit, scp->reg_base + mt8183_host_to_scp); + + if (wait) { + /* wait for scp's ack */ + timeout = msecs_to_jiffies(wait); + ret = wait_event_timeout(scp->ack_wq, + scp->ipi_id_ack[id], + timeout); + scp->ipi_id_ack[id] = false; + if (warn(!ret, "scp ipi %d ack time out !", id)) + ret = -eio; + else + ret = 0; + } + +clock_disable: + clk_disable_unprepare(scp->clk); +unlock_mutex: + mutex_unlock(&scp->send_lock); + + return ret; +} +export_symbol_gpl(scp_ipi_send); + +module_license("gpl v2"); +module_description("mediatek scp ipi interface"); diff --git a/include/linux/remoteproc/mtk_scp.h b/include/linux/remoteproc/mtk_scp.h --- /dev/null +++ b/include/linux/remoteproc/mtk_scp.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2019 mediatek inc. + */ + +#ifndef _mtk_scp_h +#define _mtk_scp_h + +#include <linux/platform_device.h> + +typedef void (*scp_ipi_handler_t) (void *data, + unsigned int len, + void *priv); +struct mtk_scp; + +/** + * enum ipi_id - the id of inter-processor interrupt + * + * @scp_ipi_init: the interrupt from scp is to notfiy kernel + * scp initialization completed. + * ipi_scp_init is sent from scp when firmware is + * loaded. ap doesn't need to send ipi_scp_init + * command to scp. + * for other ipi below, ap should send the request + * to scp to trigger the interrupt. + * @scp_ipi_max: the maximum ipi number + */ + +enum scp_ipi_id { + scp_ipi_init = 0, + scp_ipi_vdec_h264, + scp_ipi_vdec_vp8, + scp_ipi_vdec_vp9, + scp_ipi_venc_h264, + scp_ipi_venc_vp8, + scp_ipi_mdp_init, + scp_ipi_mdp_deinit, + scp_ipi_mdp_frame, + scp_ipi_dip, + scp_ipi_isp_cmd, + scp_ipi_isp_frame, + scp_ipi_fd_cmd, + scp_ipi_cros_host_cmd, + scp_ipi_max, +}; + +struct mtk_scp *scp_get(struct platform_device *pdev); +void scp_put(struct mtk_scp *scp); + +struct device *scp_get_device(struct mtk_scp *scp); +struct rproc *scp_get_rproc(struct mtk_scp *scp); + +int scp_ipi_register(struct mtk_scp *scp, u32 id, scp_ipi_handler_t handler, + void *priv); +void scp_ipi_unregister(struct mtk_scp *scp, u32 id); + +int scp_ipi_send(struct mtk_scp *scp, u32 id, void *buf, unsigned int len, + unsigned int wait); + +unsigned int scp_get_vdec_hw_capa(struct mtk_scp *scp); +unsigned int scp_get_venc_hw_capa(struct mtk_scp *scp); + +void *scp_mapping_dm_addr(struct mtk_scp *scp, u32 mem_addr); + +#endif /* _mtk_scp_h */ | Various | 63c13d61eafe4606f1c16c54da40c4eee78e9edf | erin lo | drivers | remoteproc | remoteproc |
remoteproc: mss: q6v5-mss: add modem support on sc7180 | add the out of reset sequence support for modem sub-system on sc7180 socs. it requires access to an additional halt nav register to put the modem back into reset. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add modem support on sc7180 | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['remoteproc', 'mss', 'q6v5-mss'] | ['c'] | 1 | 198 | 1 | --- diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c +#define nav_axi_haltreq_bit bit(0) +#define nav_axi_haltack_bit bit(1) +#define nav_axi_idle_bit bit(2) +#define qdsp6ss_core_cbcr 0x20 +#define qdsp6ss_boot_status 0x408 + bool has_halt_nav; + struct regmap *halt_nav_map; + struct regmap *conn_map; + + u32 halt_nav; + u32 conn_box; + bool has_halt_nav; + mss_sc7180, + } else if (qproc->has_halt_nav) { + /* swar using conn_box_spare_0 for pipeline glitch issue */ + reset_control_assert(qproc->pdc_reset); + regmap_update_bits(qproc->conn_map, qproc->conn_box, + bit(0), bit(0)); + regmap_update_bits(qproc->halt_nav_map, qproc->halt_nav, + nav_axi_haltreq_bit, 0); + reset_control_assert(qproc->mss_restart); + reset_control_deassert(qproc->pdc_reset); + regmap_update_bits(qproc->conn_map, qproc->conn_box, + bit(0), 0); + ret = reset_control_deassert(qproc->mss_restart); + } else if (qproc->has_halt_nav) { + ret = reset_control_reset(qproc->mss_restart); + goto pbl_wait; + } else if (qproc->version == mss_sc7180) { + val = readl(qproc->reg_base + qdsp6ss_sleep); + val |= 0x1; + writel(val, qproc->reg_base + qdsp6ss_sleep); + + ret = readl_poll_timeout(qproc->reg_base + qdsp6ss_sleep, + val, !(val & bit(31)), 1, + sleep_check_max_loops); + if (ret) { + dev_err(qproc->dev, "qdsp6ss sleep clock timed out "); + return -etimedout; + } + + /* turn on the xo clock needed for pll setup */ + val = readl(qproc->reg_base + qdsp6ss_xo_cbcr); + val |= 0x1; + writel(val, qproc->reg_base + qdsp6ss_xo_cbcr); + + ret = readl_poll_timeout(qproc->reg_base + qdsp6ss_xo_cbcr, + val, !(val & bit(31)), 1, + sleep_check_max_loops); + if (ret) { + dev_err(qproc->dev, "qdsp6ss xo clock timed out "); + return -etimedout; + } + + /* configure q6 core cbcr to auto-enable after reset sequence */ + val = readl(qproc->reg_base + qdsp6ss_core_cbcr); + val |= 0x1; + writel(val, qproc->reg_base + qdsp6ss_core_cbcr); + + /* de-assert the q6 stop core signal */ + writel(1, qproc->reg_base + qdsp6ss_boot_core_start); + + /* trigger the boot fsm to start the q6 out-of-reset sequence */ + writel(1, qproc->reg_base + qdsp6ss_boot_cmd); + + /* poll the qdsp6ss_boot_status for fsm completion */ + ret = readl_poll_timeout(qproc->reg_base + qdsp6ss_boot_status, + val, (val & bit(0)) != 0, 1, + sleep_check_max_loops); + if (ret) { + dev_err(qproc->dev, "boot fsm failed to complete. "); + /* reset the modem so that boot fsm is in reset state */ + q6v5_reset_deassert(qproc); + return ret; + } +static void q6v5proc_halt_nav_axi_port(struct q6v5 *qproc, + struct regmap *halt_map, + u32 offset) +{ + unsigned long timeout; + unsigned int val; + int ret; + + /* check if we're already idle */ + ret = regmap_read(halt_map, offset, &val); + if (!ret && (val & nav_axi_idle_bit)) + return; + + /* assert halt request */ + regmap_update_bits(halt_map, offset, nav_axi_haltreq_bit, + nav_axi_haltreq_bit); + + /* wait for halt ack*/ + timeout = jiffies + msecs_to_jiffies(halt_ack_timeout_ms); + for (;;) { + ret = regmap_read(halt_map, offset, &val); + if (ret || (val & nav_axi_haltack_bit) || + time_after(jiffies, timeout)) + break; + + udelay(5); + } + + ret = regmap_read(halt_map, offset, &val); + if (ret || !(val & nav_axi_idle_bit)) + dev_err(qproc->dev, "port failed halt "); +} + + if (qproc->has_halt_nav) + q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, + qproc->halt_nav); + if (qproc->has_halt_nav) + q6v5proc_halt_nav_axi_port(qproc, qproc->halt_nav_map, + qproc->halt_nav); + if (qproc->has_halt_nav) { + struct platform_device *nav_pdev; + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "qcom,halt-nav-regs", + 1, 0, &args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse halt-nav-regs "); + return -einval; + } + + nav_pdev = of_find_device_by_node(args.np); + of_node_put(args.np); + if (!nav_pdev) { + dev_err(&pdev->dev, "failed to get mss clock device "); + return -eprobe_defer; + } + + qproc->halt_nav_map = dev_get_regmap(&nav_pdev->dev, null); + if (!qproc->halt_nav_map) { + dev_err(&pdev->dev, "failed to get map from device "); + return -einval; + } + qproc->halt_nav = args.args[0]; + + ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node, + "qcom,halt-nav-regs", + 1, 1, &args); + if (ret < 0) { + dev_err(&pdev->dev, "failed to parse halt-nav-regs "); + return -einval; + } + + qproc->conn_map = syscon_node_to_regmap(args.np); + of_node_put(args.np); + if (is_err(qproc->conn_map)) + return ptr_err(qproc->conn_map); + + qproc->conn_box = args.args[0]; + } + - if (qproc->has_alt_reset) { + if (qproc->has_alt_reset || qproc->has_halt_nav) { + qproc->has_halt_nav = desc->has_halt_nav; +static const struct rproc_hexagon_res sc7180_mss = { + .hexagon_mba_image = "mba.mbn", + .proxy_clk_names = (char*[]){ + "xo", + null + }, + .reset_clk_names = (char*[]){ + "iface", + "bus", + "snoc_axi", + null + }, + .active_clk_names = (char*[]){ + "mnoc_axi", + "nav", + "mss_nav", + "mss_crypto", + null + }, + .active_pd_names = (char*[]){ + "load_state", + null + }, + .proxy_pd_names = (char*[]){ + "cx", + "mx", + "mss", + null + }, + .need_mem_protection = true, + .has_alt_reset = false, + .has_halt_nav = true, + .version = mss_sc7180, +}; + + .has_halt_nav = false, + .has_halt_nav = false, + .has_halt_nav = false, + .has_halt_nav = false, + .has_halt_nav = false, + { .compatible = "qcom,sc7180-mss-pil", .data = &sc7180_mss}, | Various | 6439b5276b9fda037698ad2e26ad18c9528154b4 | sibi sankar | drivers | remoteproc | |
remoteproc: qcom: pas: add msm8998 adsp and slpi support | add support for booting the audio and sensor dsps found in qualcomm's msm8998 socs. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add msm8998 adsp and slpi support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['remoteproc', 'qcom', 'pas'] | ['c'] | 1 | 32 | 0 | --- diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c +static const struct adsp_data msm8998_adsp_resource = { + .crash_reason_smem = 423, + .firmware_name = "adsp.mdt", + .pas_id = 1, + .has_aggre2_clk = false, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "cx", + null + }, + .ssr_name = "lpass", + .sysmon_name = "adsp", + .ssctl_id = 0x14, +}; + +static const struct adsp_data msm8998_slpi_resource = { + .crash_reason_smem = 424, + .firmware_name = "slpi.mdt", + .pas_id = 12, + .has_aggre2_clk = true, + .auto_boot = true, + .proxy_pd_names = (char*[]){ + "ssc_cx", + null + }, + .ssr_name = "dsps", + .sysmon_name = "slpi", + .ssctl_id = 0x16, +}; + + { .compatible = "qcom,msm8998-adsp-pas", .data = &msm8998_adsp_resource}, + { .compatible = "qcom,msm8998-slpi-pas", .data = &msm8998_slpi_resource}, | Various | 7c77e31733f3dbf88904be3b5e974effae32355f | sibi sankar | drivers | remoteproc | |
remoteproc: qcom: pas: add sm8150 adsp, cdsp, modem and slpi support | add support for booting the modem, audio, compute and sensor dsps found on qualcomm's sm8150 socs. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add sm8150 adsp, cdsp, modem and slpi support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['remoteproc', 'qcom', 'pas'] | ['c'] | 1 | 78 | 0 | --- diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c +static const struct adsp_data sm8150_adsp_resource = { + .crash_reason_smem = 423, + .firmware_name = "adsp.mdt", + .pas_id = 1, + .has_aggre2_clk = false, + .active_pd_names = (char*[]){ + "load_state", + null + }, + .proxy_pd_names = (char*[]){ + "cx", + null + }, + .ssr_name = "lpass", + .sysmon_name = "adsp", + .ssctl_id = 0x14, +}; + +static const struct adsp_data sm8150_cdsp_resource = { + .crash_reason_smem = 601, + .firmware_name = "cdsp.mdt", + .pas_id = 18, + .has_aggre2_clk = false, + .active_pd_names = (char*[]){ + "load_state", + null + }, + .proxy_pd_names = (char*[]){ + "cx", + null + }, + .ssr_name = "cdsp", + .sysmon_name = "cdsp", + .ssctl_id = 0x17, +}; + +static const struct adsp_data mpss_resource_init = { + .crash_reason_smem = 421, + .firmware_name = "modem.mdt", + .pas_id = 4, + .has_aggre2_clk = false, + .active_pd_names = (char*[]){ + "load_state", + null + }, + .proxy_pd_names = (char*[]){ + "cx", + "mss", + null + }, + .ssr_name = "mpss", + .sysmon_name = "modem", + .ssctl_id = 0x12, +}; + +static const struct adsp_data sm8150_slpi_resource = { + .crash_reason_smem = 424, + .firmware_name = "slpi.mdt", + .pas_id = 12, + .has_aggre2_clk = false, + .active_pd_names = (char*[]){ + "load_state", + null + }, + .proxy_pd_names = (char*[]){ + "lcx", + "lmx", + null + }, + .ssr_name = "dsps", + .sysmon_name = "slpi", + .ssctl_id = 0x16, +}; + + { .compatible = "qcom,sm8150-adsp-pas", .data = &sm8150_adsp_resource}, + { .compatible = "qcom,sm8150-cdsp-pas", .data = &sm8150_cdsp_resource}, + { .compatible = "qcom,sm8150-mpss-pas", .data = &mpss_resource_init}, + { .compatible = "qcom,sm8150-slpi-pas", .data = &sm8150_slpi_resource}, | Various | 15f4ae1e18adfa6318e657e1c42c1e598b5b882e | sibi sankar | drivers | remoteproc | |
reset: add broadcom stb rescal reset controller | on bcm7216 there is a special purpose reset controller named rescal (reset calibration) which is necessary for sata and pcie0/1 to operate correctly. this commit adds support for such a reset controller to be available. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add broadcom stb rescal reset controller | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['reset'] | ['c', 'kconfig', 'makefile'] | 3 | 115 | 0 | --- diff --git a/drivers/reset/kconfig b/drivers/reset/kconfig --- a/drivers/reset/kconfig +++ b/drivers/reset/kconfig +config reset_brcmstb_rescal + bool "broadcom stb rescal reset controller" + default arch_brcmstb || compile_test + help + this enables the rescal reset controller for sata, pcie0, or pcie1 on + bcm7216. + diff --git a/drivers/reset/makefile b/drivers/reset/makefile --- a/drivers/reset/makefile +++ b/drivers/reset/makefile +obj-$(config_reset_brcmstb_rescal) += reset-brcmstb-rescal.o diff --git a/drivers/reset/reset-brcmstb-rescal.c b/drivers/reset/reset-brcmstb-rescal.c --- /dev/null +++ b/drivers/reset/reset-brcmstb-rescal.c +// spdx-license-identifier: gpl-2.0 +/* copyright (c) 2018-2020 broadcom */ + +#include <linux/device.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> + +#define brcm_rescal_start 0x0 +#define brcm_rescal_start_bit bit(0) +#define brcm_rescal_ctrl 0x4 +#define brcm_rescal_status 0x8 +#define brcm_rescal_status_bit bit(0) + +struct brcm_rescal_reset { + void __iomem *base; + struct device *dev; + struct reset_controller_dev rcdev; +}; + +static int brcm_rescal_reset_set(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct brcm_rescal_reset *data = + container_of(rcdev, struct brcm_rescal_reset, rcdev); + void __iomem *base = data->base; + u32 reg; + int ret; + + reg = readl(base + brcm_rescal_start); + writel(reg | brcm_rescal_start_bit, base + brcm_rescal_start); + reg = readl(base + brcm_rescal_start); + if (!(reg & brcm_rescal_start_bit)) { + dev_err(data->dev, "failed to start sata/pcie rescal "); + return -eio; + } + + ret = readl_poll_timeout(base + brcm_rescal_status, reg, + !(reg & brcm_rescal_status_bit), 100, 1000); + if (ret) { + dev_err(data->dev, "time out on sata/pcie rescal "); + return ret; + } + + reg = readl(base + brcm_rescal_start); + writel(reg & ~brcm_rescal_start_bit, base + brcm_rescal_start); + + dev_dbg(data->dev, "sata/pcie rescal success "); + + return 0; +} + +static int brcm_rescal_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + /* this is needed if #reset-cells == 0. */ + return 0; +} + +static const struct reset_control_ops brcm_rescal_reset_ops = { + .reset = brcm_rescal_reset_set, +}; + +static int brcm_rescal_reset_probe(struct platform_device *pdev) +{ + struct brcm_rescal_reset *data; + struct resource *res; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + res = platform_get_resource(pdev, ioresource_mem, 0); + data->base = devm_ioremap_resource(&pdev->dev, res); + if (is_err(data->base)) + return ptr_err(data->base); + + data->rcdev.owner = this_module; + data->rcdev.nr_resets = 1; + data->rcdev.ops = &brcm_rescal_reset_ops; + data->rcdev.of_node = pdev->dev.of_node; + data->rcdev.of_xlate = brcm_rescal_reset_xlate; + data->dev = &pdev->dev; + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static const struct of_device_id brcm_rescal_reset_of_match[] = { + { .compatible = "brcm,bcm7216-pcie-sata-rescal" }, + { }, +}; +module_device_table(of, brcm_rescal_reset_of_match); + +static struct platform_driver brcm_rescal_reset_driver = { + .probe = brcm_rescal_reset_probe, + .driver = { + .name = "brcm-rescal-reset", + .of_match_table = brcm_rescal_reset_of_match, + } +}; +module_platform_driver(brcm_rescal_reset_driver); + +module_author("broadcom"); +module_description("broadcom sata/pcie rescal reset controller"); +module_license("gpl v2"); | Various | 4cf176e52397853e4a4dd37e917c5eafb47ba8d1 | jim quinlan | drivers | reset | |
reset: intel: add system reset controller driver | add driver for the reset controller present on intel gateway socs for performing reset management of the devices present on the soc. driver also registers a reset handler to peform the entire device reset. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add system reset controller driver | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['reset', 'intel'] | ['c', 'kconfig', 'makefile'] | 3 | 272 | 0 | --- diff --git a/drivers/reset/kconfig b/drivers/reset/kconfig --- a/drivers/reset/kconfig +++ b/drivers/reset/kconfig +config reset_intel_gw + bool "intel reset controller driver" + depends on of + select regmap_mmio + help + this enables the reset controller driver for intel gateway socs. + say y to control the reset signals provided by reset controller. + otherwise, say n. + diff --git a/drivers/reset/makefile b/drivers/reset/makefile --- a/drivers/reset/makefile +++ b/drivers/reset/makefile +obj-$(config_reset_intel_gw) += reset-intel-gw.o diff --git a/drivers/reset/reset-intel-gw.c b/drivers/reset/reset-intel-gw.c --- /dev/null +++ b/drivers/reset/reset-intel-gw.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019 intel corporation. + * lei chuanhua <chuanhua.lei@intel.com> + */ + +#include <linux/bitfield.h> +#include <linux/init.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/regmap.h> +#include <linux/reset-controller.h> + +#define rcu_rst_stat 0x0024 +#define rcu_rst_req 0x0048 + +#define reg_offset genmask(31, 16) +#define bit_offset genmask(15, 8) +#define stat_bit_offset genmask(7, 0) + +#define to_reset_data(x) container_of(x, struct intel_reset_data, rcdev) + +struct intel_reset_soc { + bool legacy; + u32 reset_cell_count; +}; + +struct intel_reset_data { + struct reset_controller_dev rcdev; + struct notifier_block restart_nb; + const struct intel_reset_soc *soc_data; + struct regmap *regmap; + struct device *dev; + u32 reboot_id; +}; + +static const struct regmap_config intel_rcu_regmap_config = { + .name = "intel-reset", + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, +}; + +/* + * reset status register offset relative to + * the reset control register(x) is x + 4 + */ +static u32 id_to_reg_and_bit_offsets(struct intel_reset_data *data, + unsigned long id, u32 *rst_req, + u32 *req_bit, u32 *stat_bit) +{ + *rst_req = field_get(reg_offset, id); + *req_bit = field_get(bit_offset, id); + + if (data->soc_data->legacy) + *stat_bit = field_get(stat_bit_offset, id); + else + *stat_bit = *req_bit; + + if (data->soc_data->legacy && *rst_req == rcu_rst_req) + return rcu_rst_stat; + else + return *rst_req + 0x4; +} + +static int intel_set_clr_bits(struct intel_reset_data *data, unsigned long id, + bool set) +{ + u32 rst_req, req_bit, rst_stat, stat_bit, val; + int ret; + + rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req, + &req_bit, &stat_bit); + + val = set ? bit(req_bit) : 0; + ret = regmap_update_bits(data->regmap, rst_req, bit(req_bit), val); + if (ret) + return ret; + + return regmap_read_poll_timeout(data->regmap, rst_stat, val, + set == !!(val & bit(stat_bit)), 20, + 200); +} + +static int intel_assert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct intel_reset_data *data = to_reset_data(rcdev); + int ret; + + ret = intel_set_clr_bits(data, id, true); + if (ret) + dev_err(data->dev, "reset assert failed %d ", ret); + + return ret; +} + +static int intel_deassert_device(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct intel_reset_data *data = to_reset_data(rcdev); + int ret; + + ret = intel_set_clr_bits(data, id, false); + if (ret) + dev_err(data->dev, "reset deassert failed %d ", ret); + + return ret; +} + +static int intel_reset_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct intel_reset_data *data = to_reset_data(rcdev); + u32 rst_req, req_bit, rst_stat, stat_bit, val; + int ret; + + rst_stat = id_to_reg_and_bit_offsets(data, id, &rst_req, + &req_bit, &stat_bit); + ret = regmap_read(data->regmap, rst_stat, &val); + if (ret) + return ret; + + return !!(val & bit(stat_bit)); +} + +static const struct reset_control_ops intel_reset_ops = { + .assert = intel_assert_device, + .deassert = intel_deassert_device, + .status = intel_reset_status, +}; + +static int intel_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *spec) +{ + struct intel_reset_data *data = to_reset_data(rcdev); + u32 id; + + if (spec->args[1] > 31) + return -einval; + + id = field_prep(reg_offset, spec->args[0]); + id |= field_prep(bit_offset, spec->args[1]); + + if (data->soc_data->legacy) { + if (spec->args[2] > 31) + return -einval; + + id |= field_prep(stat_bit_offset, spec->args[2]); + } + + return id; +} + +static int intel_reset_restart_handler(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct intel_reset_data *reset_data; + + reset_data = container_of(nb, struct intel_reset_data, restart_nb); + intel_assert_device(&reset_data->rcdev, reset_data->reboot_id); + + return notify_done; +} + +static int intel_reset_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; + struct intel_reset_data *data; + void __iomem *base; + u32 rb_id[3]; + int ret; + + data = devm_kzalloc(dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + data->soc_data = of_device_get_match_data(dev); + if (!data->soc_data) + return -enodev; + + base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(base)) + return ptr_err(base); + + data->regmap = devm_regmap_init_mmio(dev, base, + &intel_rcu_regmap_config); + if (is_err(data->regmap)) { + dev_err(dev, "regmap initialization failed "); + return ptr_err(data->regmap); + } + + ret = device_property_read_u32_array(dev, "intel,global-reset", rb_id, + data->soc_data->reset_cell_count); + if (ret) { + dev_err(dev, "failed to get global reset offset! "); + return ret; + } + + data->dev = dev; + data->rcdev.of_node = np; + data->rcdev.owner = dev->driver->owner; + data->rcdev.ops = &intel_reset_ops; + data->rcdev.of_xlate = intel_reset_xlate; + data->rcdev.of_reset_n_cells = data->soc_data->reset_cell_count; + ret = devm_reset_controller_register(&pdev->dev, &data->rcdev); + if (ret) + return ret; + + data->reboot_id = field_prep(reg_offset, rb_id[0]); + data->reboot_id |= field_prep(bit_offset, rb_id[1]); + + if (data->soc_data->legacy) + data->reboot_id |= field_prep(stat_bit_offset, rb_id[2]); + + data->restart_nb.notifier_call = intel_reset_restart_handler; + data->restart_nb.priority = 128; + register_restart_handler(&data->restart_nb); + + return 0; +} + +static const struct intel_reset_soc xrx200_data = { + .legacy = true, + .reset_cell_count = 3, +}; + +static const struct intel_reset_soc lgm_data = { + .legacy = false, + .reset_cell_count = 2, +}; + +static const struct of_device_id intel_reset_match[] = { + { .compatible = "intel,rcu-lgm", .data = &lgm_data }, + { .compatible = "intel,rcu-xrx200", .data = &xrx200_data }, + {} +}; + +static struct platform_driver intel_reset_driver = { + .probe = intel_reset_probe, + .driver = { + .name = "intel-reset", + .of_match_table = intel_reset_match, + }, +}; + +static int __init intel_reset_init(void) +{ + return platform_driver_register(&intel_reset_driver); +} + +/* + * rcu is system core entity which is in always on domain whose clocks + * or resource initialization happens in system core initialization. + * also, it is required for most of the platform or architecture + * specific devices to perform reset operation as part of initialization. + * so perform rcu as post core initialization. + */ +postcore_initcall(intel_reset_init); | Various | c9aef213e38cde27d4689a5cbe25a7c1b1db9fad | dilip kota | drivers | reset | |
rpmsg: add rpmsg support for mt8183 scp. | add a simple rpmsg support for mt8183 scp, that use ipi / ipc directly. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add rpmsg support for mt8183 scp | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['rpmsg'] | ['h', 'kconfig', 'c', 'makefile'] | 9 | 525 | 5 | --- diff --git a/drivers/remoteproc/kconfig b/drivers/remoteproc/kconfig --- a/drivers/remoteproc/kconfig +++ b/drivers/remoteproc/kconfig + select rpmsg_mtk_scp diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h + + struct rproc_subdev *rpmsg_subdev; diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c +#include <linux/rpmsg/mtk_rpmsg.h> +static int scp_register_ipi(struct platform_device *pdev, u32 id, + ipi_handler_t handler, void *priv) +{ + struct mtk_scp *scp = platform_get_drvdata(pdev); + + return scp_ipi_register(scp, id, handler, priv); +} + +static void scp_unregister_ipi(struct platform_device *pdev, u32 id) +{ + struct mtk_scp *scp = platform_get_drvdata(pdev); + + scp_ipi_unregister(scp, id); +} + +static int scp_send_ipi(struct platform_device *pdev, u32 id, void *buf, + unsigned int len, unsigned int wait) +{ + struct mtk_scp *scp = platform_get_drvdata(pdev); + + return scp_ipi_send(scp, id, buf, len, wait); +} + +static struct mtk_rpmsg_info mtk_scp_rpmsg_info = { + .send_ipi = scp_send_ipi, + .register_ipi = scp_register_ipi, + .unregister_ipi = scp_unregister_ipi, + .ns_ipi_id = scp_ipi_ns_service, +}; + +static void scp_add_rpmsg_subdev(struct mtk_scp *scp) +{ + scp->rpmsg_subdev = + mtk_rpmsg_create_rproc_subdev(to_platform_device(scp->dev), + &mtk_scp_rpmsg_info); + if (scp->rpmsg_subdev) + rproc_add_subdev(scp->rproc, scp->rpmsg_subdev); +} + +static void scp_remove_rpmsg_subdev(struct mtk_scp *scp) +{ + if (scp->rpmsg_subdev) { + rproc_remove_subdev(scp->rproc, scp->rpmsg_subdev); + mtk_rpmsg_destroy_rproc_subdev(scp->rpmsg_subdev); + scp->rpmsg_subdev = null; + } +} + + scp_add_rpmsg_subdev(scp); + - goto unregister_ipi; + goto remove_subdev; - goto unregister_ipi; + goto remove_subdev; - return ret; + return 0; -unregister_ipi: +remove_subdev: + scp_remove_rpmsg_subdev(scp); + scp_remove_rpmsg_subdev(scp); diff --git a/drivers/remoteproc/mtk_scp_ipi.c b/drivers/remoteproc/mtk_scp_ipi.c --- a/drivers/remoteproc/mtk_scp_ipi.c +++ b/drivers/remoteproc/mtk_scp_ipi.c + warn_on(id == scp_ipi_ns_service) || diff --git a/drivers/rpmsg/kconfig b/drivers/rpmsg/kconfig --- a/drivers/rpmsg/kconfig +++ b/drivers/rpmsg/kconfig +config rpmsg_mtk_scp + tristate "mediatek scp" + depends on mtk_scp + select rpmsg + help + say y here to enable support providing communication channels to + remote processors in mediatek platforms. + this use ipi and ipc to communicate with remote processors. + diff --git a/drivers/rpmsg/makefile b/drivers/rpmsg/makefile --- a/drivers/rpmsg/makefile +++ b/drivers/rpmsg/makefile +obj-$(config_rpmsg_mtk_scp) += mtk_rpmsg.o diff --git a/drivers/rpmsg/mtk_rpmsg.c b/drivers/rpmsg/mtk_rpmsg.c --- /dev/null +++ b/drivers/rpmsg/mtk_rpmsg.c +// spdx-license-identifier: gpl-2.0 +// +// copyright 2019 google llc. + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/remoteproc.h> +#include <linux/rpmsg/mtk_rpmsg.h> +#include <linux/workqueue.h> + +#include "rpmsg_internal.h" + +struct mtk_rpmsg_rproc_subdev { + struct platform_device *pdev; + struct mtk_rpmsg_info *info; + struct rpmsg_endpoint *ns_ept; + struct rproc_subdev subdev; + + struct work_struct register_work; + struct list_head channels; + struct mutex channels_lock; +}; + +#define to_mtk_subdev(d) container_of(d, struct mtk_rpmsg_rproc_subdev, subdev) + +struct mtk_rpmsg_channel_info { + struct rpmsg_channel_info info; + bool registered; + struct list_head list; +}; + +/** + * struct rpmsg_ns_msg - dynamic name service announcement message + * @name: name of remote service that is published + * @addr: address of remote service that is published + * + * this message is sent across to publish a new service. when we receive these + * messages, an appropriate rpmsg channel (i.e device) is created. in turn, the + * ->probe() handler of the appropriate rpmsg driver will be invoked + * (if/as-soon-as one is registered). + */ +struct rpmsg_ns_msg { + char name[rpmsg_name_size]; + u32 addr; +} __packed; + +struct mtk_rpmsg_device { + struct rpmsg_device rpdev; + struct mtk_rpmsg_rproc_subdev *mtk_subdev; +}; + +struct mtk_rpmsg_endpoint { + struct rpmsg_endpoint ept; + struct mtk_rpmsg_rproc_subdev *mtk_subdev; +}; + +#define to_mtk_rpmsg_device(r) container_of(r, struct mtk_rpmsg_device, rpdev) +#define to_mtk_rpmsg_endpoint(r) container_of(r, struct mtk_rpmsg_endpoint, ept) + +static const struct rpmsg_endpoint_ops mtk_rpmsg_endpoint_ops; + +static void __mtk_ept_release(struct kref *kref) +{ + struct rpmsg_endpoint *ept = container_of(kref, struct rpmsg_endpoint, + refcount); + kfree(to_mtk_rpmsg_endpoint(ept)); +} + +static void mtk_rpmsg_ipi_handler(void *data, unsigned int len, void *priv) +{ + struct mtk_rpmsg_endpoint *mept = priv; + struct rpmsg_endpoint *ept = &mept->ept; + int ret; + + ret = (*ept->cb)(ept->rpdev, data, len, ept->priv, ept->addr); + if (ret) + dev_warn(&ept->rpdev->dev, "rpmsg handler return error = %d", + ret); +} + +static struct rpmsg_endpoint * +__mtk_create_ept(struct mtk_rpmsg_rproc_subdev *mtk_subdev, + struct rpmsg_device *rpdev, rpmsg_rx_cb_t cb, void *priv, + u32 id) +{ + struct mtk_rpmsg_endpoint *mept; + struct rpmsg_endpoint *ept; + struct platform_device *pdev = mtk_subdev->pdev; + int ret; + + mept = kzalloc(sizeof(*mept), gfp_kernel); + if (!mept) + return null; + mept->mtk_subdev = mtk_subdev; + + ept = &mept->ept; + kref_init(&ept->refcount); + + ept->rpdev = rpdev; + ept->cb = cb; + ept->priv = priv; + ept->ops = &mtk_rpmsg_endpoint_ops; + ept->addr = id; + + ret = mtk_subdev->info->register_ipi(pdev, id, mtk_rpmsg_ipi_handler, + mept); + if (ret) { + dev_err(&pdev->dev, "ipi register failed, id = %d", id); + kref_put(&ept->refcount, __mtk_ept_release); + return null; + } + + return ept; +} + +static struct rpmsg_endpoint * +mtk_rpmsg_create_ept(struct rpmsg_device *rpdev, rpmsg_rx_cb_t cb, void *priv, + struct rpmsg_channel_info chinfo) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = + to_mtk_rpmsg_device(rpdev)->mtk_subdev; + + return __mtk_create_ept(mtk_subdev, rpdev, cb, priv, chinfo.src); +} + +static void mtk_rpmsg_destroy_ept(struct rpmsg_endpoint *ept) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = + to_mtk_rpmsg_endpoint(ept)->mtk_subdev; + + mtk_subdev->info->unregister_ipi(mtk_subdev->pdev, ept->addr); + kref_put(&ept->refcount, __mtk_ept_release); +} + +static int mtk_rpmsg_send(struct rpmsg_endpoint *ept, void *data, int len) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = + to_mtk_rpmsg_endpoint(ept)->mtk_subdev; + + return mtk_subdev->info->send_ipi(mtk_subdev->pdev, ept->addr, data, + len, 0); +} + +static int mtk_rpmsg_trysend(struct rpmsg_endpoint *ept, void *data, int len) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = + to_mtk_rpmsg_endpoint(ept)->mtk_subdev; + + /* + * todo: this currently is same as mtk_rpmsg_send, and wait until scp + * received the last command. + */ + return mtk_subdev->info->send_ipi(mtk_subdev->pdev, ept->addr, data, + len, 0); +} + +static const struct rpmsg_endpoint_ops mtk_rpmsg_endpoint_ops = { + .destroy_ept = mtk_rpmsg_destroy_ept, + .send = mtk_rpmsg_send, + .trysend = mtk_rpmsg_trysend, +}; + +static void mtk_rpmsg_release_device(struct device *dev) +{ + struct rpmsg_device *rpdev = to_rpmsg_device(dev); + struct mtk_rpmsg_device *mdev = to_mtk_rpmsg_device(rpdev); + + kfree(mdev); +} + +static const struct rpmsg_device_ops mtk_rpmsg_device_ops = { + .create_ept = mtk_rpmsg_create_ept, +}; + +static struct device_node * +mtk_rpmsg_match_device_subnode(struct device_node *node, const char *channel) +{ + struct device_node *child; + const char *name; + int ret; + + for_each_available_child_of_node(node, child) { + ret = of_property_read_string(child, "mtk,rpmsg-name", &name); + if (ret) + continue; + + if (strcmp(name, channel) == 0) + return child; + } + + return null; +} + +static int mtk_rpmsg_register_device(struct mtk_rpmsg_rproc_subdev *mtk_subdev, + struct rpmsg_channel_info *info) +{ + struct rpmsg_device *rpdev; + struct mtk_rpmsg_device *mdev; + struct platform_device *pdev = mtk_subdev->pdev; + int ret; + + mdev = kzalloc(sizeof(*mdev), gfp_kernel); + if (!mdev) + return -enomem; + + mdev->mtk_subdev = mtk_subdev; + + rpdev = &mdev->rpdev; + rpdev->ops = &mtk_rpmsg_device_ops; + rpdev->src = info->src; + rpdev->dst = info->dst; + strscpy(rpdev->id.name, info->name, rpmsg_name_size); + + rpdev->dev.of_node = + mtk_rpmsg_match_device_subnode(pdev->dev.of_node, info->name); + rpdev->dev.parent = &pdev->dev; + rpdev->dev.release = mtk_rpmsg_release_device; + + ret = rpmsg_register_device(rpdev); + if (ret) { + kfree(mdev); + return ret; + } + + return 0; +} + +static void mtk_register_device_work_function(struct work_struct *register_work) +{ + struct mtk_rpmsg_rproc_subdev *subdev = container_of( + register_work, struct mtk_rpmsg_rproc_subdev, register_work); + struct platform_device *pdev = subdev->pdev; + struct mtk_rpmsg_channel_info *info; + int ret; + + mutex_lock(&subdev->channels_lock); + list_for_each_entry(info, &subdev->channels, list) { + if (info->registered) + continue; + + ret = mtk_rpmsg_register_device(subdev, &info->info); + if (ret) { + dev_err(&pdev->dev, "can't create rpmsg_device "); + continue; + } + + info->registered = true; + } + mutex_unlock(&subdev->channels_lock); +} + +static int mtk_rpmsg_create_device(struct mtk_rpmsg_rproc_subdev *mtk_subdev, + char *name, u32 addr) +{ + struct mtk_rpmsg_channel_info *info; + + info = kzalloc(sizeof(*info), gfp_kernel); + if (!info) + return -enomem; + + strscpy(info->info.name, name, rpmsg_name_size); + info->info.src = addr; + info->info.dst = rpmsg_addr_any; + mutex_lock(&mtk_subdev->channels_lock); + list_add(&info->list, &mtk_subdev->channels); + mutex_unlock(&mtk_subdev->channels_lock); + + schedule_work(&mtk_subdev->register_work); + return 0; +} + +static int mtk_rpmsg_ns_cb(struct rpmsg_device *rpdev, void *data, int len, + void *priv, u32 src) +{ + struct rpmsg_ns_msg *msg = data; + struct mtk_rpmsg_rproc_subdev *mtk_subdev = priv; + struct device *dev = &mtk_subdev->pdev->dev; + + int ret; + + if (len != sizeof(*msg)) { + dev_err(dev, "malformed ns msg (%d) ", len); + return -einval; + } + + /* + * the name service ept does _not_ belong to a real rpmsg channel, + * and is handled by the rpmsg bus itself. + * for sanity reasons, make sure a valid rpdev has _not_ sneaked + * in somehow. + */ + if (rpdev) { + dev_err(dev, "anomaly: ns ept has an rpdev handle "); + return -einval; + } + + /* don't trust the remote processor for null terminating the name */ + msg->name[rpmsg_name_size - 1] = ''; + + dev_info(dev, "creating channel %s addr 0x%x ", msg->name, msg->addr); + + ret = mtk_rpmsg_create_device(mtk_subdev, msg->name, msg->addr); + if (ret) { + dev_err(dev, "create rpmsg device failed "); + return ret; + } + + return 0; +} + +static int mtk_rpmsg_prepare(struct rproc_subdev *subdev) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = to_mtk_subdev(subdev); + + /* a dedicated endpoint handles the name service msgs */ + if (mtk_subdev->info->ns_ipi_id >= 0) { + mtk_subdev->ns_ept = + __mtk_create_ept(mtk_subdev, null, mtk_rpmsg_ns_cb, + mtk_subdev, + mtk_subdev->info->ns_ipi_id); + if (!mtk_subdev->ns_ept) { + dev_err(&mtk_subdev->pdev->dev, + "failed to create name service endpoint "); + return -enomem; + } + } + + return 0; +} + +static void mtk_rpmsg_unprepare(struct rproc_subdev *subdev) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = to_mtk_subdev(subdev); + + if (mtk_subdev->ns_ept) { + mtk_rpmsg_destroy_ept(mtk_subdev->ns_ept); + mtk_subdev->ns_ept = null; + } +} + +static void mtk_rpmsg_stop(struct rproc_subdev *subdev, bool crashed) +{ + struct mtk_rpmsg_channel_info *info, *next; + struct mtk_rpmsg_rproc_subdev *mtk_subdev = to_mtk_subdev(subdev); + struct device *dev = &mtk_subdev->pdev->dev; + + /* + * destroy the name service endpoint here, to avoid new channel being + * created after the rpmsg_unregister_device loop below. + */ + if (mtk_subdev->ns_ept) { + mtk_rpmsg_destroy_ept(mtk_subdev->ns_ept); + mtk_subdev->ns_ept = null; + } + + cancel_work_sync(&mtk_subdev->register_work); + + mutex_lock(&mtk_subdev->channels_lock); + list_for_each_entry(info, &mtk_subdev->channels, list) { + if (!info->registered) + continue; + if (rpmsg_unregister_device(dev, &info->info)) { + dev_warn( + dev, + "rpmsg_unregister_device failed for %s.%d.%d ", + info->info.name, info->info.src, + info->info.dst); + } + } + + list_for_each_entry_safe(info, next, + &mtk_subdev->channels, list) { + list_del(&info->list); + kfree(info); + } + mutex_unlock(&mtk_subdev->channels_lock); +} + +struct rproc_subdev * +mtk_rpmsg_create_rproc_subdev(struct platform_device *pdev, + struct mtk_rpmsg_info *info) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev; + + mtk_subdev = kzalloc(sizeof(*mtk_subdev), gfp_kernel); + if (!mtk_subdev) + return null; + + mtk_subdev->pdev = pdev; + mtk_subdev->subdev.prepare = mtk_rpmsg_prepare; + mtk_subdev->subdev.stop = mtk_rpmsg_stop; + mtk_subdev->subdev.unprepare = mtk_rpmsg_unprepare; + mtk_subdev->info = info; + init_list_head(&mtk_subdev->channels); + init_work(&mtk_subdev->register_work, + mtk_register_device_work_function); + mutex_init(&mtk_subdev->channels_lock); + + return &mtk_subdev->subdev; +} +export_symbol_gpl(mtk_rpmsg_create_rproc_subdev); + +void mtk_rpmsg_destroy_rproc_subdev(struct rproc_subdev *subdev) +{ + struct mtk_rpmsg_rproc_subdev *mtk_subdev = to_mtk_subdev(subdev); + + kfree(mtk_subdev); +} +export_symbol_gpl(mtk_rpmsg_destroy_rproc_subdev); + +module_license("gpl v2"); +module_description("mediatek scp rpmsg driver"); diff --git a/include/linux/remoteproc/mtk_scp.h b/include/linux/remoteproc/mtk_scp.h --- a/include/linux/remoteproc/mtk_scp.h +++ b/include/linux/remoteproc/mtk_scp.h - scp_ipi_max, + scp_ipi_ns_service = 0xff, + scp_ipi_max = 0x100, diff --git a/include/linux/rpmsg/mtk_rpmsg.h b/include/linux/rpmsg/mtk_rpmsg.h --- /dev/null +++ b/include/linux/rpmsg/mtk_rpmsg.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright 2019 google llc. + */ + +#ifndef __linux_rpmsg_mtk_rpmsg_h +#define __linux_rpmsg_mtk_rpmsg_h + +#include <linux/platform_device.h> +#include <linux/remoteproc.h> + +typedef void (*ipi_handler_t)(void *data, unsigned int len, void *priv); + +/* + * struct mtk_rpmsg_info - ipi functions tied to the rpmsg device. + * @register_ipi: register ipi handler for an ipi id. + * @unregister_ipi: unregister ipi handler for a registered ipi id. + * @send_ipi: send ipi to an ipi id. wait is the timeout (in msecs) to wait + * until response, or 0 if there's no timeout. + * @ns_ipi_id: the ipi id used for name service, or -1 if name service isn't + * supported. + */ +struct mtk_rpmsg_info { + int (*register_ipi)(struct platform_device *pdev, u32 id, + ipi_handler_t handler, void *priv); + void (*unregister_ipi)(struct platform_device *pdev, u32 id); + int (*send_ipi)(struct platform_device *pdev, u32 id, + void *buf, unsigned int len, unsigned int wait); + int ns_ipi_id; +}; + +struct rproc_subdev * +mtk_rpmsg_create_rproc_subdev(struct platform_device *pdev, + struct mtk_rpmsg_info *info); + +void mtk_rpmsg_destroy_rproc_subdev(struct rproc_subdev *subdev); + +#endif | Various | 7017996951fde84698ddfe7fd47f92bd9d9eb85d | pi hsun shih | drivers | remoteproc | remoteproc, rpmsg |
soc/tegra: fuse: add tegra194 support | this commit adds tegra194 fuse/apbmisc support. | this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements. | add tegra194 support | ['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc'] | ['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various'] | ['soc/tegra', 'fuse'] | ['c', 'h'] | 4 | 37 | 0 | --- diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c +#ifdef config_arch_tegra_194_soc + { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc }, +#endif diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c + +#if defined(config_arch_tegra_194_soc) +static const struct nvmem_cell_lookup tegra194_fuse_lookups[] = { + { + .nvmem_name = "fuse", + .cell_name = "xusb-pad-calibration", + .dev_id = "3520000.padctl", + .con_id = "calibration", + }, { + .nvmem_name = "fuse", + .cell_name = "xusb-pad-calibration-ext", + .dev_id = "3520000.padctl", + .con_id = "calibration-ext", + }, +}; + +static const struct tegra_fuse_info tegra194_fuse_info = { + .read = tegra30_fuse_read, + .size = 0x300, + .spare = 0x280, +}; + +const struct tegra_fuse_soc tegra194_fuse_soc = { + .init = tegra30_fuse_init, + .info = &tegra194_fuse_info, + .lookups = tegra194_fuse_lookups, + .num_lookups = array_size(tegra194_fuse_lookups), +}; +#endif diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h +#ifdef config_arch_tegra_194_soc +extern const struct tegra_fuse_soc tegra194_fuse_soc; +#endif + diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c + { .compatible = "nvidia,tegra194-misc", }, | Various | 3979a4c6263397eb03c4e8995938607f4f6ba0de | jc kuo | drivers | soc | fuse, tegra |
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