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drm/amdgpu: rename amdgpu_device_is_px to amdgpu_device_supports_boco (v2)
|
baco - bus active, chip off boco - bus off, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 4
| 12
| 12
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h -bool amdgpu_device_is_px(struct drm_device *dev); +bool amdgpu_device_supports_boco(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c - * amdgpu_device_is_px - is the device is a dgpu with hg/px power control + * amdgpu_device_supports_boco - is the device a dgpu with hg/px power control -bool amdgpu_device_is_px(struct drm_device *dev) +bool amdgpu_device_supports_boco(struct drm_device *dev) - if (amdgpu_device_is_px(dev) && state == vga_switcheroo_off) + if (amdgpu_device_supports_boco(dev) && state == vga_switcheroo_off) - if (amdgpu_device_is_px(ddev)) + if (amdgpu_device_supports_boco(ddev)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c - if (amdgpu_device_is_px(drm_dev)) { + if (amdgpu_device_supports_boco(drm_dev)) { - if (!amdgpu_device_is_px(drm_dev)) { + if (!amdgpu_device_supports_boco(drm_dev)) { - if (!amdgpu_device_is_px(drm_dev)) + if (!amdgpu_device_supports_boco(drm_dev)) - if (!amdgpu_device_is_px(drm_dev)) { + if (!amdgpu_device_supports_boco(drm_dev)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c - if (amdgpu_device_is_px(dev)) { + if (amdgpu_device_supports_boco(dev)) { - if (amdgpu_device_is_px(dev)) { + if (amdgpu_device_supports_boco(dev)) { - if (adev->rmmio && amdgpu_device_is_px(dev)) + if (adev->rmmio && amdgpu_device_supports_boco(dev))
|
Graphics
|
31af062acfbd5db8b0b99d0ad418b33d4458e206
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add additional boco checks to runtime suspend/resume (v2)
|
baco - bus active, chip off boco - bus off, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 26
| 21
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c - drm_dev->switch_power_state = drm_switch_power_changing; + if (amdgpu_device_supports_boco(drm_dev)) + drm_dev->switch_power_state = drm_switch_power_changing; - pci_save_state(pdev); - pci_disable_device(pdev); - pci_ignore_hotplug(pdev); - if (amdgpu_is_atpx_hybrid()) - pci_set_power_state(pdev, pci_d3cold); - else if (!amdgpu_has_atpx_dgpu_power_cntl()) - pci_set_power_state(pdev, pci_d3hot); - drm_dev->switch_power_state = drm_switch_power_dynamic_off; + if (amdgpu_device_supports_boco(drm_dev)) { + pci_save_state(pdev); + pci_disable_device(pdev); + pci_ignore_hotplug(pdev); + if (amdgpu_is_atpx_hybrid()) + pci_set_power_state(pdev, pci_d3cold); + else if (!amdgpu_has_atpx_dgpu_power_cntl()) + pci_set_power_state(pdev, pci_d3hot); + drm_dev->switch_power_state = drm_switch_power_dynamic_off; + } - drm_dev->switch_power_state = drm_switch_power_changing; - - if (amdgpu_is_atpx_hybrid() || - !amdgpu_has_atpx_dgpu_power_cntl()) - pci_set_power_state(pdev, pci_d0); - pci_restore_state(pdev); - ret = pci_enable_device(pdev); - if (ret) - return ret; - pci_set_master(pdev); - + if (amdgpu_device_supports_boco(drm_dev)) { + drm_dev->switch_power_state = drm_switch_power_changing; + + if (amdgpu_is_atpx_hybrid() || + !amdgpu_has_atpx_dgpu_power_cntl()) + pci_set_power_state(pdev, pci_d0); + pci_restore_state(pdev); + ret = pci_enable_device(pdev); + if (ret) + return ret; + pci_set_master(pdev); + } - drm_dev->switch_power_state = drm_switch_power_on; + if (amdgpu_device_supports_boco(drm_dev)) + drm_dev->switch_power_state = drm_switch_power_on;
|
Graphics
|
b97e9d47e549caacea9504822301c34d447c5fcf
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: split swsmu baco_reset into enter and exit
|
baco - bus active, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c', 'h']
| 9
| 51
| 13
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c - ret = smu_baco_reset(smu); + ret = smu_baco_enter(smu); + if (ret) + return ret; + ret = smu_baco_exit(smu); + if (ret) + return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c + int ret; - if (smu_baco_reset(smu)) - return -eio; + ret = smu_baco_enter(smu); + if (ret) + return ret; + + ret = smu_baco_exit(smu); + if (ret) + return ret; diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c -int smu_baco_reset(struct smu_context *smu) +int smu_baco_enter(struct smu_context *smu) - if (smu->ppt_funcs->baco_reset) - ret = smu->ppt_funcs->baco_reset(smu); + if (smu->ppt_funcs->baco_enter) + ret = smu->ppt_funcs->baco_enter(smu); + + mutex_unlock(&smu->mutex); + + return ret; +} + +int smu_baco_exit(struct smu_context *smu) +{ + int ret = 0; + + mutex_lock(&smu->mutex); + + if (smu->ppt_funcs->baco_exit) + ret = smu->ppt_funcs->baco_exit(smu); diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c - .baco_reset = smu_v11_0_baco_reset, + .baco_enter = smu_v11_0_baco_enter, + .baco_exit = smu_v11_0_baco_exit, diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h - int (*baco_reset)(struct smu_context *smu); + int (*baco_enter)(struct smu_context *smu); + int (*baco_exit)(struct smu_context *smu); -int smu_baco_reset(struct smu_context *smu); +int smu_baco_enter(struct smu_context *smu); +int smu_baco_exit(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h --- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h -int smu_v11_0_baco_reset(struct smu_context *smu); +int smu_v11_0_baco_enter(struct smu_context *smu); +int smu_v11_0_baco_exit(struct smu_context *smu); diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c - .baco_reset = smu_v11_0_baco_reset, + .baco_enter = smu_v11_0_baco_enter, + .baco_exit = smu_v11_0_baco_exit, diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c -int smu_v11_0_baco_reset(struct smu_context *smu) +int smu_v11_0_baco_enter(struct smu_context *smu) + return ret; +} + +int smu_v11_0_baco_exit(struct smu_context *smu) +{ + int ret = 0; + diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c --- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c - .baco_reset = smu_v11_0_baco_reset, + .baco_enter = smu_v11_0_baco_enter, + .baco_exit = smu_v11_0_baco_exit,
|
Graphics
|
11520f27085bbab7dcb2b5998dec7e7abe3a5bd1
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm, inc, powerplay
|
drm/amdgpu: add helpers for baco entry and exit
|
baco - bus active, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 2
| 63
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +int amdgpu_device_baco_enter(struct drm_device *dev); +int amdgpu_device_baco_exit(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +int amdgpu_device_baco_enter(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + + if (!amdgpu_device_supports_baco(adev->ddev)) + return -enotsupp; + + if (is_support_sw_smu(adev)) { + struct smu_context *smu = &adev->smu; + int ret; + + ret = smu_baco_enter(smu); + if (ret) + return ret; + + return 0; + } else { + void *pp_handle = adev->powerplay.pp_handle; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + + if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) + return -enoent; + + /* enter baco state */ + if (pp_funcs->set_asic_baco_state(pp_handle, 1)) + return -eio; + + return 0; + } +} + +int amdgpu_device_baco_exit(struct drm_device *dev) +{ + struct amdgpu_device *adev = dev->dev_private; + + if (!amdgpu_device_supports_baco(adev->ddev)) + return -enotsupp; + + if (is_support_sw_smu(adev)) { + struct smu_context *smu = &adev->smu; + int ret; + + ret = smu_baco_exit(smu); + if (ret) + return ret; + + return 0; + } else { + void *pp_handle = adev->powerplay.pp_handle; + const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + + if (!pp_funcs ||!pp_funcs->get_asic_baco_state ||!pp_funcs->set_asic_baco_state) + return -enoent; + + /* exit baco state */ + if (pp_funcs->set_asic_baco_state(pp_handle, 0)) + return -eio; + + return 0; + } +}
|
Graphics
|
361dbd01a1de8bdd6bdf9a879ae23a121b8f7266
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add baco support to runtime suspend/resume
|
baco - bus active, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 6
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c - if (amdgpu_device_supports_boco(drm_dev)) { + if (amdgpu_device_supports_boco(drm_dev) || + amdgpu_device_supports_baco(drm_dev)) { + } else if (amdgpu_device_supports_baco(drm_dev)) { + amdgpu_device_baco_enter(drm_dev); + } else if (amdgpu_device_supports_baco(drm_dev)) { + amdgpu_device_baco_exit(drm_dev);
|
Graphics
|
191343172809aba0047c2eb03249cb704ad65658
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: start to disentangle boco from runtime pm
|
baco - bus active, chip off boco - bus off, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['h', 'c']
| 3
| 16
| 8
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h + /* enable runtime pm on the device */ + bool runpm; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c + struct amdgpu_device *adev = drm_dev->dev_private; - if (!amdgpu_device_supports_boco(drm_dev)) { + if (!adev->runpm) { + struct amdgpu_device *adev = drm_dev->dev_private; - if (!amdgpu_device_supports_boco(drm_dev)) + if (!adev->runpm) + struct amdgpu_device *adev = drm_dev->dev_private; - if (!amdgpu_device_supports_boco(drm_dev)) { + if (!adev->runpm) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c - if (amdgpu_device_supports_boco(dev)) { + if (adev->runpm) { - if ((amdgpu_runtime_pm != 0) && - amdgpu_has_atpx() && + if (amdgpu_has_atpx() && + if ((amdgpu_runtime_pm != 0) && + (flags & amd_is_px)) + adev->runpm = true; + - if (amdgpu_device_supports_boco(dev)) { + if (adev->runpm) { - if (adev->rmmio && amdgpu_device_supports_boco(dev)) + if (adev->rmmio && adev->runpm)
|
Graphics
|
6ae6c7d404ec3e7595c2c6bee8df211a34da5c64
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: disentangle runtime pm and vga_switcheroo
|
originally we only supported runtime pm on px/hg laptops so vga_switcheroo and runtime pm are sort of entangled.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 14
| 8
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c - bool runtime = false; + bool boco = false; - runtime = true; - if (!pci_is_thunderbolt_attached(adev->pdev)) + boco = true; + if (amdgpu_has_atpx() && + (amdgpu_is_atpx_hybrid() || + amdgpu_has_atpx_dgpu_power_cntl()) && + !pci_is_thunderbolt_attached(adev->pdev)) - &amdgpu_switcheroo_ops, runtime); - if (runtime) + &amdgpu_switcheroo_ops, boco); + if (boco) - if (runtime) + if (boco) - if (!pci_is_thunderbolt_attached(adev->pdev)) + if (amdgpu_has_atpx() && + (amdgpu_is_atpx_hybrid() || + amdgpu_has_atpx_dgpu_power_cntl()) && + !pci_is_thunderbolt_attached(adev->pdev)) - if (adev->flags & amd_is_px) + if (amdgpu_device_supports_boco(adev->ddev))
|
Graphics
|
3840c5bcc2456381ca53f3f9604915aa36249faf
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable runtime pm on baco capable boards if runpm=1
|
baco - bus active, chip off
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use baco for runtime pm power save
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 7
| 4
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c - if ((amdgpu_runtime_pm != 0) && - (flags & amd_is_px)) - adev->runpm = true; - + if (amdgpu_device_supports_boco(dev) && + (amdgpu_runtime_pm != 0)) /* enable runpm by default */ + adev->runpm = true; + else if (amdgpu_device_supports_baco(dev) && + (amdgpu_runtime_pm > 0)) /* enable runpm if runpm=1 */ + adev->runpm = true; +
|
Graphics
|
72f058b7237ede2be2d98c70bdabbe7c3e587ae9
|
alex deucher
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gfxoff feature for navi10 asic
|
enable gfxoff feature for some navi10 asics
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
gfxoff on navi10 and raven1 refresh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 19
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev) +{ + bool ret = false; + + switch (adev->pdev->revision) { + case 0xc2: + case 0xc3: + ret = true; + break; + default: + ret = false; + break; + } + + return ret ; +} + - adev->pm.pp_feature &= ~pp_gfxoff_mask; + if (!gfx_v10_0_navi10_gfxoff_should_enable(adev)) + adev->pm.pp_feature &= ~pp_gfxoff_mask;
|
Graphics
|
d549991ce5d5194d89eafe16085603b38e7cf989
|
kevin wang feifei xu feifei xu amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gfxoff for raven1 refresh
|
when smu version is larger than 0x41e2b, it will load raven_kicker_rlc.bin.to enable gfxoff for raven_kicker_rlc.bin,it needs to avoid adev->pm.pp_feature &= ~pp_gfxoff_mask when it loads raven_kicker_rlc.bin.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
gfxoff on navi10 and raven1 refresh
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 4
| 11
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c - /* disable gfxoff on original raven. there are combinations - * of sbios and platforms that are not stable. - */ - if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)) - adev->pm.pp_feature &= ~pp_gfxoff_mask; - else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) - &&((adev->gfx.rlc_fw_version != 106 && - adev->gfx.rlc_fw_version < 531) || - (adev->gfx.rlc_fw_version == 53815) || - (adev->gfx.rlc_feature_version < 1) || - !adev->gfx.rlc.is_rlc_v2_1)) + if (!(adev->rev_id >= 0x8 || + adev->pdev->device == 0x15d8) && + (adev->pm.fw_version < 0x41e2b || /* not raven1 fresh */ + !adev->gfx.rlc.is_rlc_v2_1)) /* without rlc save restore ucodes */
|
Graphics
|
aaff8b448d2ab8c0ccc8591c997663c54b074293
|
changzhu alex deucher alexander deucher amd com huang rui ray huang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
amdgpu: enable initial dcn support on power
|
dcn requires floating point support to operate. add the appropriate x86/ppc64 guards and fpu / altivec / vsx context switches to dcn.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
dcn support on power
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c', 'kconfig', 'makefile', 'h']
| 8
| 73
| 1
|
--- diff --git a/drivers/gpu/drm/amd/display/kconfig b/drivers/gpu/drm/amd/display/kconfig --- a/drivers/gpu/drm/amd/display/kconfig +++ b/drivers/gpu/drm/amd/display/kconfig - select drm_amd_dc_dcn if x86 && !(kcov_instrument_all && kcov_enable_comparisons) + select drm_amd_dc_dcn if (x86 || ppc64) && !(kcov_instrument_all && kcov_enable_comparisons) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/makefile b/drivers/gpu/drm/amd/display/dc/calcs/makefile --- a/drivers/gpu/drm/amd/display/dc/calcs/makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/makefile +# copyright 2019 raptor engineering, llc +ifdef config_x86 +endif + +ifdef config_ppc64 +calcs_ccflags := -mhard-float -maltivec +endif +ifdef config_x86 +endif diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c + * copyright 2019 raptor engineering, llc diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/makefile b/drivers/gpu/drm/amd/display/dc/dcn20/makefile --- a/drivers/gpu/drm/amd/display/dc/dcn20/makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn20/makefile +ifdef config_x86 +endif + +ifdef config_ppc64 +cflags_$(amddalpath)/dc/dcn20/dcn20_resource.o := -mhard-float -maltivec +endif +ifdef config_x86 +endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/makefile b/drivers/gpu/drm/amd/display/dc/dcn21/makefile --- a/drivers/gpu/drm/amd/display/dc/dcn21/makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn21/makefile +ifdef config_x86 +endif + +ifdef config_ppc64 +cflags_$(amddalpath)/dc/dcn21/dcn21_resource.o := -mhard-float -maltivec +endif +ifdef config_x86 +endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/makefile b/drivers/gpu/drm/amd/display/dc/dml/makefile --- a/drivers/gpu/drm/amd/display/dc/dml/makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/makefile +# copyright 2019 raptor engineering, llc +ifdef config_x86 +endif + +ifdef config_ppc64 +dml_ccflags := -mhard-float -maltivec +endif +ifdef config_x86 +endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/makefile b/drivers/gpu/drm/amd/display/dc/dsc/makefile --- a/drivers/gpu/drm/amd/display/dc/dsc/makefile +++ b/drivers/gpu/drm/amd/display/dc/dsc/makefile +ifdef config_x86 +endif + +ifdef config_ppc64 +dsc_ccflags := -mhard-float -maltivec +endif +ifdef config_x86 +endif diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h --- a/drivers/gpu/drm/amd/display/dc/os_types.h +++ b/drivers/gpu/drm/amd/display/dc/os_types.h +#if defined(config_x86) +#elif defined(config_ppc64) +#include <asm/switch_to.h> +#include <asm/cputable.h> +#define dc_fp_start() { \ + if (cpu_has_feature(cpu_ftr_vsx_comp)) { \ + preempt_disable(); \ + enable_kernel_vsx(); \ + } else if (cpu_has_feature(cpu_ftr_altivec_comp)) { \ + preempt_disable(); \ + enable_kernel_altivec(); \ + } else if (!cpu_has_feature(cpu_ftr_fpu_unavailable)) { \ + preempt_disable(); \ + enable_kernel_fp(); \ + } \ +} +#define dc_fp_end() { \ + if (cpu_has_feature(cpu_ftr_vsx_comp)) { \ + disable_kernel_vsx(); \ + preempt_enable(); \ + } else if (cpu_has_feature(cpu_ftr_altivec_comp)) { \ + disable_kernel_altivec(); \ + preempt_enable(); \ + } else if (!cpu_has_feature(cpu_ftr_fpu_unavailable)) { \ + disable_kernel_fp(); \ + preempt_enable(); \ + } \ +} +#endif
|
Graphics
|
16a9dea110a67d62401ffeac4828cabdedec7548
|
timothy pearson
|
drivers
|
gpu
|
amd, calcs, dc, dcn20, dcn21, display, dml, drm, dsc
|
amdgpu: enable kfd on power systems
|
kfd has been verified to function on power systems (talos ii / vega 64). it should be available as a kernel configuration option on these systems.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
dcn support on power
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['kconfig']
| 1
| 1
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdkfd/kconfig b/drivers/gpu/drm/amd/amdkfd/kconfig --- a/drivers/gpu/drm/amd/amdkfd/kconfig +++ b/drivers/gpu/drm/amd/amdkfd/kconfig - depends on drm_amdgpu && (x86_64 || arm64) + depends on drm_amdgpu && (x86_64 || arm64 || ppc64)
|
Graphics
|
70ebe8a48216ae2fda862cae47ff0b8af5b279b9
|
timothy pearson
|
drivers
|
gpu
|
amd, amdkfd, drm
|
drm/amd/powerplay: support custom power profile setting
|
support custom power profile mode settings on arcturus.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
support custom power profile setting
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ', 'powerplay']
|
['c', 'h']
| 2
| 128
| 10
|
--- diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c --- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c + tab_map(activity_monitor_coeff), + smu_table_init(tables, smu_table_activity_monitor_coeff, + sizeof(dpmactivitymonitorcoeffint_t), page_size, + amdgpu_gem_domain_vram); + + dpmactivitymonitorcoeffint_t activity_monitor; - "profile_index(name)"}; + "profile_index(name)", + "clock_type(name)", + "fps", + "userlcbusy", + "minactivefreqtype", + "minactivefreq", + "boosterfreqtype", + "boosterfreq", + "pd_data_limit_c", + "pd_data_error_coeff", + "pd_data_error_rate_coeff"}; + int result = 0; + uint32_t smu_version; - if (!smu->pm_enabled || !buf) + if (!buf) - size += sprintf(buf + size, "%16s ", + result = smu_get_smc_version(smu, null, &smu_version); + if (result) + return result; + + if (smu_version >= 0x360d00) + size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s ", + title[0], title[1], title[2], title[3], title[4], title[5], + title[6], title[7], title[8], title[9], title[10]); + else + size += sprintf(buf + size, "%16s ", + if (smu_version >= 0x360d00) { + result = smu_update_table(smu, + smu_table_activity_monitor_coeff, + workload_type, + (void *)(&activity_monitor), + false); + if (result) { + pr_err("[%s] failed to get activity monitor!", __func__); + return result; + } + } + + + if (smu_version >= 0x360d00) { + size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d ", + " ", + 0, + "gfxclk", + activity_monitor.gfx_fps, + activity_monitor.gfx_userlcbusy, + activity_monitor.gfx_minactivefreqtype, + activity_monitor.gfx_minactivefreq, + activity_monitor.gfx_boosterfreqtype, + activity_monitor.gfx_boosterfreq, + activity_monitor.gfx_pd_data_limit_c, + activity_monitor.gfx_pd_data_error_coeff, + activity_monitor.gfx_pd_data_error_rate_coeff); + + size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d ", + " ", + 1, + "uclk", + activity_monitor.mem_fps, + activity_monitor.mem_userlcbusy, + activity_monitor.mem_minactivefreqtype, + activity_monitor.mem_minactivefreq, + activity_monitor.mem_boosterfreqtype, + activity_monitor.mem_boosterfreq, + activity_monitor.mem_pd_data_limit_c, + activity_monitor.mem_pd_data_error_coeff, + activity_monitor.mem_pd_data_error_rate_coeff); + } + dpmactivitymonitorcoeffint_t activity_monitor; - - if (!smu->pm_enabled) - return -einval; + uint32_t smu_version; + ret = smu_get_smc_version(smu, null, &smu_version); + if (ret) + return ret; + + if ((profile_mode == pp_smc_power_profile_custom) && + (smu_version >=0x360d00)) { + ret = smu_update_table(smu, + smu_table_activity_monitor_coeff, + workload_pplib_custom_bit, + (void *)(&activity_monitor), + false); + if (ret) { + pr_err("[%s] failed to get activity monitor!", __func__); + return ret; + } + + switch (input[0]) { + case 0: /* gfxclk */ + activity_monitor.gfx_fps = input[1]; + activity_monitor.gfx_userlcbusy = input[2]; + activity_monitor.gfx_minactivefreqtype = input[3]; + activity_monitor.gfx_minactivefreq = input[4]; + activity_monitor.gfx_boosterfreqtype = input[5]; + activity_monitor.gfx_boosterfreq = input[6]; + activity_monitor.gfx_pd_data_limit_c = input[7]; + activity_monitor.gfx_pd_data_error_coeff = input[8]; + activity_monitor.gfx_pd_data_error_rate_coeff = input[9]; + break; + case 1: /* uclk */ + activity_monitor.mem_fps = input[1]; + activity_monitor.mem_userlcbusy = input[2]; + activity_monitor.mem_minactivefreqtype = input[3]; + activity_monitor.mem_minactivefreq = input[4]; + activity_monitor.mem_boosterfreqtype = input[5]; + activity_monitor.mem_boosterfreq = input[6]; + activity_monitor.mem_pd_data_limit_c = input[7]; + activity_monitor.mem_pd_data_error_coeff = input[8]; + activity_monitor.mem_pd_data_error_rate_coeff = input[9]; + break; + } + + ret = smu_update_table(smu, + smu_table_activity_monitor_coeff, + workload_pplib_custom_bit, + (void *)(&activity_monitor), + true); + if (ret) { + pr_err("[%s] failed to set activity monitor!", __func__); + return ret; + } + } + diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h --- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h -/* not currently used -*/ -//#define table_activity_monitor_coeff 7 -#define table_count 10 +#define table_activity_monitor_coeff 10 +#define table_count 11
|
Graphics
|
18d7ab9899d34e6a7f8cb4d17368b7db398323e4
|
evan quan alex deucher alexander deucher amd com
|
drivers
|
gpu
|
amd, drm, inc, powerplay
|
drm/amdgpu: enable gpu reset by default on navi
|
has been working fine for a while.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable gpu reset by default on navi
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 3
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + case chip_navi10: + case chip_navi14: + case chip_navi12:
|
Graphics
|
658c663947b04b1f8a2fd061a3ef767983c880e5
|
alex deucher andrey grodzovsky andrey grodzovsky amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: enable gpu reset by default on renoir
|
everything is in place.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable gpu reset by default on navi
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c + case chip_renoir:
|
Graphics
|
2cb44fb09305e23fe60dbfcccad3f8c4028749f1
|
alex deucher andrey grodzovsky andrey grodzovsky amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: refine the security check for ras functions
|
to avoid calling ras related functions when ras feature isn't supported in hardware. change to check supported features, instead of checking asic type.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable ras feature for the gc of arcturus
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 2
| 2
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c - if (adev->asic_type != chip_vega20) + if (!amdgpu_ras_is_supported(adev, amdgpu_ras_block__gfx)) - if (adev->asic_type != chip_vega20) + if (!amdgpu_ras_is_supported(adev, amdgpu_ras_block__gfx))
|
Graphics
|
5e66403e4d709decacf2b53e55deb55d8f6e6982
|
dennis li
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: abstract edc counter clear to a separated function
|
1. add ip prefix for the ip related codes. 2. refactor the code to clear edc counter.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable ras feature for the gc of arcturus
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c']
| 1
| 77
| 35
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +static void gfx_v9_0_clear_ras_edc_counter(struct amdgpu_device *adev); -static const struct soc15_reg_entry sec_ded_counter_registers[] = { +static const struct soc15_reg_entry gfx_v9_0_edc_counter_regs[] = { - int r, i, j, k; + int r, i; - /* read back registers to clear the counters */ - mutex_lock(&adev->grbm_idx_mutex); - for (i = 0; i < array_size(sec_ded_counter_registers); i++) { - for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) { - for (k = 0; k < sec_ded_counter_registers[i].instance; k++) { - gfx_v9_0_select_se_sh(adev, j, 0x0, k); - rreg32(soc15_reg_entry_offset(sec_ded_counter_registers[i])); - } - } - } - wreg32_soc15(gc, 0, mmgrbm_gfx_index, 0xe0000000); - mutex_unlock(&adev->grbm_idx_mutex); + gfx_v9_0_clear_ras_edc_counter(adev); -static const struct soc15_ras_field_entry gc_ras_fields_vg20[] = { +static const struct soc15_ras_field_entry gfx_v9_0_ras_fields[] = { - for (i = 0; i < 16; i++) { + for (i = 0; i < array_size(vml2_mems); i++) { - for (i = 0; i < 7; i++) { + for (i = 0; i < array_size(vml2_walker_mems); i++) { - for (i = 0; i < 4; i++) { + for (i = 0; i < array_size(atc_l2_cache_2m_mems); i++) { - for (i = 0; i < 32; i++) { + for (i = 0; i < array_size(atc_l2_cache_4k_mems); i++) { -static int __get_ras_error_count(const struct soc15_reg_entry *reg, +static int gfx_v9_0_ras_error_count(const struct soc15_reg_entry *reg, - for (i = 0; i < array_size(gc_ras_fields_vg20); i++) { - if(gc_ras_fields_vg20[i].reg_offset != reg->reg_offset || - gc_ras_fields_vg20[i].seg != reg->seg || - gc_ras_fields_vg20[i].inst != reg->inst) + for (i = 0; i < array_size(gfx_v9_0_ras_fields); i++) { + if(gfx_v9_0_ras_fields[i].reg_offset != reg->reg_offset || + gfx_v9_0_ras_fields[i].seg != reg->seg || + gfx_v9_0_ras_fields[i].inst != reg->inst) - gc_ras_fields_vg20[i].sec_count_mask) >> - gc_ras_fields_vg20[i].sec_count_shift; + gfx_v9_0_ras_fields[i].sec_count_mask) >> + gfx_v9_0_ras_fields[i].sec_count_shift; - gc_ras_fields_vg20[i].name, + gfx_v9_0_ras_fields[i].name, - gc_ras_fields_vg20[i].ded_count_mask) >> - gc_ras_fields_vg20[i].ded_count_shift; + gfx_v9_0_ras_fields[i].ded_count_mask) >> + gfx_v9_0_ras_fields[i].ded_count_shift; - gc_ras_fields_vg20[i].name, + gfx_v9_0_ras_fields[i].name, +static void gfx_v9_0_clear_ras_edc_counter(struct amdgpu_device *adev) +{ + int i, j, k; + + /* read back registers to clear the counters */ + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < array_size(gfx_v9_0_edc_counter_regs); i++) { + for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { + for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { + gfx_v9_0_select_se_sh(adev, j, 0x0, k); + rreg32(soc15_reg_entry_offset(gfx_v9_0_edc_counter_regs[i])); + } + } + } + wreg32_soc15(gc, 0, mmgrbm_gfx_index, 0xe0000000); + mutex_unlock(&adev->grbm_idx_mutex); + + wreg32_soc15(gc, 0, mmvm_l2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvm_l2_mem_ecc_cnt, 0); + wreg32_soc15(gc, 0, mmvm_l2_walker_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvm_l2_walker_mem_ecc_cnt, 0); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_edc_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_edc_cnt, 0); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_edc_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_edc_cnt, 0); + + for (i = 0; i < array_size(vml2_mems); i++) { + wreg32_soc15(gc, 0, mmvm_l2_mem_ecc_index, i); + rreg32_soc15(gc, 0, mmvm_l2_mem_ecc_cnt); + } + + for (i = 0; i < array_size(vml2_walker_mems); i++) { + wreg32_soc15(gc, 0, mmvm_l2_walker_mem_ecc_index, i); + rreg32_soc15(gc, 0, mmvm_l2_walker_mem_ecc_cnt); + } + + for (i = 0; i < array_size(atc_l2_cache_2m_mems); i++) { + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_edc_index, i); + rreg32_soc15(gc, 0, mmatc_l2_cache_2m_edc_cnt); + } + + for (i = 0; i < array_size(atc_l2_cache_4k_mems); i++) { + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_edc_index, i); + rreg32_soc15(gc, 0, mmatc_l2_cache_4k_edc_cnt); + } + + wreg32_soc15(gc, 0, mmvm_l2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvm_l2_walker_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_edc_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_edc_index, 255); +} + - for (i = 0; i < array_size(sec_ded_counter_registers); i++) { - for (j = 0; j < sec_ded_counter_registers[i].se_num; j++) { - for (k = 0; k < sec_ded_counter_registers[i].instance; k++) { + for (i = 0; i < array_size(gfx_v9_0_edc_counter_regs); i++) { + for (j = 0; j < gfx_v9_0_edc_counter_regs[i].se_num; j++) { + for (k = 0; k < gfx_v9_0_edc_counter_regs[i].instance; k++) { - rreg32(soc15_reg_entry_offset(sec_ded_counter_registers[i])); + rreg32(soc15_reg_entry_offset(gfx_v9_0_edc_counter_regs[i])); - __get_ras_error_count(&sec_ded_counter_registers[i], + gfx_v9_0_ras_error_count(&gfx_v9_0_edc_counter_regs[i],
|
Graphics
|
504c5e72d781e48946c32bf427c665ed15d532d0
|
dennis li guchun chen guchun chen amd com tao zhou tao zhou amd com hawking zhang hawking zhang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/amdgpu: add edc counter registers of gc for arcturus
|
add reg headers to gc includes
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable ras feature for the gc of arcturus
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['h']
| 2
| 1,012
| 0
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--- diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_offset.h +/* + * copyright (c) 2020 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express + * or implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) be liable for any claim, damages or other liability, whether in + * an action of contract, tort or otherwise, arising from, out of or in + * connection with the software or the use or other dealings in the software. + */ +#ifndef _gc_9_4_1_offset_header +#define _gc_9_4_1_offset_header + +// addressblock: gc_grbmdec +// base address: 0x8000 +#define mmgrbm_cntl 0x0000 +#define mmgrbm_cntl_base_idx 0 +#define mmgrbm_skew_cntl 0x0001 +#define mmgrbm_skew_cntl_base_idx 0 +#define mmgrbm_status2 0x0002 +#define mmgrbm_status2_base_idx 0 +#define mmgrbm_pwr_cntl 0x0003 +#define mmgrbm_pwr_cntl_base_idx 0 +#define mmgrbm_status 0x0004 +#define mmgrbm_status_base_idx 0 +#define mmgrbm_status_se0 0x0005 +#define mmgrbm_status_se0_base_idx 0 +#define mmgrbm_status_se1 0x0006 +#define mmgrbm_status_se1_base_idx 0 +#define mmgrbm_soft_reset 0x0008 +#define mmgrbm_soft_reset_base_idx 0 +#define mmgrbm_gfx_clken_cntl 0x000c +#define mmgrbm_gfx_clken_cntl_base_idx 0 +#define mmgrbm_wait_idle_clocks 0x000d +#define mmgrbm_wait_idle_clocks_base_idx 0 +#define mmgrbm_status_se2 0x000e +#define mmgrbm_status_se2_base_idx 0 +#define mmgrbm_status_se3 0x000f +#define mmgrbm_status_se3_base_idx 0 +#define mmgrbm_read_error 0x0016 +#define mmgrbm_read_error_base_idx 0 +#define mmgrbm_read_error2 0x0017 +#define mmgrbm_read_error2_base_idx 0 +#define mmgrbm_int_cntl 0x0018 +#define mmgrbm_int_cntl_base_idx 0 +#define mmgrbm_trap_op 0x0019 +#define mmgrbm_trap_op_base_idx 0 +#define mmgrbm_trap_addr 0x001a +#define mmgrbm_trap_addr_base_idx 0 +#define mmgrbm_trap_addr_msk 0x001b +#define mmgrbm_trap_addr_msk_base_idx 0 +#define mmgrbm_trap_wd 0x001c +#define mmgrbm_trap_wd_base_idx 0 +#define mmgrbm_trap_wd_msk 0x001d +#define mmgrbm_trap_wd_msk_base_idx 0 +#define mmgrbm_dsm_bypass 0x001e +#define mmgrbm_dsm_bypass_base_idx 0 +#define mmgrbm_write_error 0x001f +#define mmgrbm_write_error_base_idx 0 +#define mmgrbm_iov_error 0x0020 +#define mmgrbm_iov_error_base_idx 0 +#define mmgrbm_chip_revision 0x0021 +#define mmgrbm_chip_revision_base_idx 0 +#define mmgrbm_gfx_cntl 0x0022 +#define mmgrbm_gfx_cntl_base_idx 0 +#define mmgrbm_rsmu_cfg 0x0023 +#define mmgrbm_rsmu_cfg_base_idx 0 +#define mmgrbm_ih_credit 0x0024 +#define mmgrbm_ih_credit_base_idx 0 +#define mmgrbm_pwr_cntl2 0x0025 +#define mmgrbm_pwr_cntl2_base_idx 0 +#define mmgrbm_utcl2_inval_range_start 0x0026 +#define mmgrbm_utcl2_inval_range_start_base_idx 0 +#define mmgrbm_utcl2_inval_range_end 0x0027 +#define mmgrbm_utcl2_inval_range_end_base_idx 0 +#define mmgrbm_rsmu_read_error 0x0028 +#define mmgrbm_rsmu_read_error_base_idx 0 +#define mmgrbm_chicken_bits 0x0029 +#define mmgrbm_chicken_bits_base_idx 0 +#define mmgrbm_fence_range0 0x002a +#define mmgrbm_fence_range0_base_idx 0 +#define mmgrbm_fence_range1 0x002b +#define mmgrbm_fence_range1_base_idx 0 +#define mmgrbm_nowhere 0x003f +#define mmgrbm_nowhere_base_idx 0 +#define mmgrbm_scratch_reg0 0x0040 +#define mmgrbm_scratch_reg0_base_idx 0 +#define mmgrbm_scratch_reg1 0x0041 +#define mmgrbm_scratch_reg1_base_idx 0 +#define mmgrbm_scratch_reg2 0x0042 +#define mmgrbm_scratch_reg2_base_idx 0 +#define mmgrbm_scratch_reg3 0x0043 +#define mmgrbm_scratch_reg3_base_idx 0 +#define mmgrbm_scratch_reg4 0x0044 +#define mmgrbm_scratch_reg4_base_idx 0 +#define mmgrbm_scratch_reg5 0x0045 +#define mmgrbm_scratch_reg5_base_idx 0 +#define mmgrbm_scratch_reg6 0x0046 +#define mmgrbm_scratch_reg6_base_idx 0 +#define mmgrbm_scratch_reg7 0x0047 +#define mmgrbm_scratch_reg7_base_idx 0 + +// addressblock: gc_cppdec2 +// base address: 0xc600 +#define mmcpf_edc_tag_cnt 0x1189 +#define mmcpf_edc_tag_cnt_base_idx 0 +#define mmcpf_edc_roq_cnt 0x118a +#define mmcpf_edc_roq_cnt_base_idx 0 +#define mmcpg_edc_tag_cnt 0x118b +#define mmcpg_edc_tag_cnt_base_idx 0 +#define mmcpg_edc_dma_cnt 0x118d +#define mmcpg_edc_dma_cnt_base_idx 0 +#define mmcpc_edc_scratch_cnt 0x118e +#define mmcpc_edc_scratch_cnt_base_idx 0 +#define mmcpc_edc_ucode_cnt 0x118f +#define mmcpc_edc_ucode_cnt_base_idx 0 +#define mmdc_edc_state_cnt 0x1191 +#define mmdc_edc_state_cnt_base_idx 0 +#define mmdc_edc_csinvoc_cnt 0x1192 +#define mmdc_edc_csinvoc_cnt_base_idx 0 +#define mmdc_edc_restore_cnt 0x1193 +#define mmdc_edc_restore_cnt_base_idx 0 + +// addressblock: gc_gdsdec +// base address: 0x9700 +#define mmgds_edc_cnt 0x05c5 +#define mmgds_edc_cnt_base_idx 0 +#define mmgds_edc_grbm_cnt 0x05c6 +#define mmgds_edc_grbm_cnt_base_idx 0 +#define mmgds_edc_oa_ded 0x05c7 +#define mmgds_edc_oa_ded_base_idx 0 +#define mmgds_edc_oa_phy_cnt 0x05cb +#define mmgds_edc_oa_phy_cnt_base_idx 0 +#define mmgds_edc_oa_pipe_cnt 0x05cc +#define mmgds_edc_oa_pipe_cnt_base_idx 0 + +// addressblock: gc_shsdec +// base address: 0x9000 +#define mmspi_edc_cnt 0x0445 +#define mmspi_edc_cnt_base_idx 0 + +// addressblock: gc_sqdec +// base address: 0x8c00 +#define mmsqc_edc_cnt2 0x032c +#define mmsqc_edc_cnt2_base_idx 0 +#define mmsqc_edc_cnt3 0x032d +#define mmsqc_edc_cnt3_base_idx 0 +#define mmsqc_edc_parity_cnt3 0x032e +#define mmsqc_edc_parity_cnt3_base_idx 0 +#define mmsqc_edc_cnt 0x03a2 +#define mmsqc_edc_cnt_base_idx 0 +#define mmsq_edc_sec_cnt 0x03a3 +#define mmsq_edc_sec_cnt_base_idx 0 +#define mmsq_edc_ded_cnt 0x03a4 +#define mmsq_edc_ded_cnt_base_idx 0 +#define mmsq_edc_info 0x03a5 +#define mmsq_edc_info_base_idx 0 +#define mmsq_edc_cnt 0x03a6 +#define mmsq_edc_cnt_base_idx 0 + +// addressblock: gc_tpdec +// base address: 0x9400 +#define mmta_edc_cnt 0x0586 +#define mmta_edc_cnt_base_idx 0 + +// addressblock: gc_tcdec +// base address: 0xac00 +#define mmtcp_edc_cnt 0x0b17 +#define mmtcp_edc_cnt_base_idx 0 +#define mmtcp_edc_cnt_new 0x0b18 +#define mmtcp_edc_cnt_new_base_idx 0 +#define mmtcp_atc_edc_gatcl1_cnt 0x12b1 +#define mmtcp_atc_edc_gatcl1_cnt_base_idx 0 +#define mmtci_edc_cnt 0x0b60 +#define mmtci_edc_cnt_base_idx 0 +#define mmtcc_edc_cnt 0x0b82 +#define mmtcc_edc_cnt_base_idx 0 +#define mmtcc_edc_cnt2 0x0b83 +#define mmtcc_edc_cnt2_base_idx 0 +#define mmtca_edc_cnt 0x0bc5 +#define mmtca_edc_cnt_base_idx 0 + +// addressblock: gc_tpdec +// base address: 0x9400 +#define mmtd_edc_cnt 0x052e +#define mmtd_edc_cnt_base_idx 0 +#define mmta_edc_cnt 0x0586 +#define mmta_edc_cnt_base_idx 0 + +// addressblock: gc_ea_gceadec2 +// base address: 0x9c00 +#define mmgcea_edc_cnt 0x0706 +#define mmgcea_edc_cnt_base_idx 0 +#define mmgcea_edc_cnt2 0x0707 +#define mmgcea_edc_cnt2_base_idx 0 +#define mmgcea_edc_cnt3 0x071b +#define mmgcea_edc_cnt3_base_idx 0 + +// addressblock: gc_gfxudec +// base address: 0x30000 +#define mmscratch_reg0 0x2040 +#define mmscratch_reg0_base_idx 1 +#define mmscratch_reg1 0x2041 +#define mmscratch_reg1_base_idx 1 +#define mmscratch_reg2 0x2042 +#define mmscratch_reg2_base_idx 1 +#define mmscratch_reg3 0x2043 +#define mmscratch_reg3_base_idx 1 +#define mmscratch_reg4 0x2044 +#define mmscratch_reg4_base_idx 1 +#define mmscratch_reg5 0x2045 +#define mmscratch_reg5_base_idx 1 +#define mmscratch_reg6 0x2046 +#define mmscratch_reg6_base_idx 1 +#define mmscratch_reg7 0x2047 +#define mmscratch_reg7_base_idx 1 +#define mmgrbm_gfx_index 0x2200 +#define mmgrbm_gfx_index_base_idx 1 + +// addressblock: gc_utcl2_atcl2dec +// base address: 0xa000 +#define mmatc_l2_cache_4k_dsm_index 0x080e +#define mmatc_l2_cache_4k_dsm_index_base_idx 0 +#define mmatc_l2_cache_2m_dsm_index 0x080f +#define mmatc_l2_cache_2m_dsm_index_base_idx 0 +#define mmatc_l2_cache_4k_dsm_cntl 0x0810 +#define mmatc_l2_cache_4k_dsm_cntl_base_idx 0 +#define mmatc_l2_cache_2m_dsm_cntl 0x0811 +#define mmatc_l2_cache_2m_dsm_cntl_base_idx 0 + +// addressblock: gc_utcl2_vml2pfdec +// base address: 0xa100 +#define mmvml2_mem_ecc_index 0x0860 +#define mmvml2_mem_ecc_index_base_idx 0 +#define mmvml2_walker_mem_ecc_index 0x0861 +#define mmvml2_walker_mem_ecc_index_base_idx 0 +#define mmutcl2_mem_ecc_index 0x0862 +#define mmutcl2_mem_ecc_index_base_idx 0 + +#define mmvml2_mem_ecc_cntl 0x0863 +#define mmvml2_mem_ecc_cntl_base_idx 0 +#define mmvml2_walker_mem_ecc_cntl 0x0864 +#define mmvml2_walker_mem_ecc_cntl_base_idx 0 +#define mmutcl2_mem_ecc_cntl 0x0865 +#define mmutcl2_mem_ecc_cntl_base_idx 0 + +// addressblock: gc_rlcpdec +// base address: 0x3b000 +#define mmrlc_edc_cnt 0x4d40 +#define mmrlc_edc_cnt_base_idx 1 +#define mmrlc_edc_cnt2 0x4d41 +#define mmrlc_edc_cnt2_base_idx 1 + +#endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h --- /dev/null +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_4_1_sh_mask.h +/* + * copyright (c) 2020 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express + * or implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) be liable for any claim, damages or other liability, whether in + * an action of contract, tort or otherwise, arising from, out of or in + * connection with the software or the use or other dealings in the software. + */ +#ifndef _gc_9_4_1_sh_mask_header +#define _gc_9_4_1_sh_mask_header + +// addressblock: gc_cppdec2 +//cpf_edc_tag_cnt +#define cpf_edc_tag_cnt__ded_count__shift 0x0 +#define cpf_edc_tag_cnt__sec_count__shift 0x2 +#define cpf_edc_tag_cnt__ded_count_mask 0x00000003l +#define cpf_edc_tag_cnt__sec_count_mask 0x0000000cl +//cpf_edc_roq_cnt +#define cpf_edc_roq_cnt__ded_count_me1__shift 0x0 +#define cpf_edc_roq_cnt__sec_count_me1__shift 0x2 +#define cpf_edc_roq_cnt__ded_count_me2__shift 0x4 +#define cpf_edc_roq_cnt__sec_count_me2__shift 0x6 +#define cpf_edc_roq_cnt__ded_count_me1_mask 0x00000003l +#define cpf_edc_roq_cnt__sec_count_me1_mask 0x0000000cl +#define cpf_edc_roq_cnt__ded_count_me2_mask 0x00000030l +#define cpf_edc_roq_cnt__sec_count_me2_mask 0x000000c0l +//cpg_edc_tag_cnt +#define cpg_edc_tag_cnt__ded_count__shift 0x0 +#define cpg_edc_tag_cnt__sec_count__shift 0x2 +#define cpg_edc_tag_cnt__ded_count_mask 0x00000003l +#define cpg_edc_tag_cnt__sec_count_mask 0x0000000cl +//cpg_edc_dma_cnt +#define cpg_edc_dma_cnt__roq_ded_count__shift 0x0 +#define cpg_edc_dma_cnt__roq_sec_count__shift 0x2 +#define cpg_edc_dma_cnt__tag_ded_count__shift 0x4 +#define cpg_edc_dma_cnt__tag_sec_count__shift 0x6 +#define cpg_edc_dma_cnt__roq_ded_count_mask 0x00000003l +#define cpg_edc_dma_cnt__roq_sec_count_mask 0x0000000cl +#define cpg_edc_dma_cnt__tag_ded_count_mask 0x00000030l +#define cpg_edc_dma_cnt__tag_sec_count_mask 0x000000c0l +//cpc_edc_scratch_cnt +#define cpc_edc_scratch_cnt__ded_count__shift 0x0 +#define cpc_edc_scratch_cnt__sec_count__shift 0x2 +#define cpc_edc_scratch_cnt__ded_count_mask 0x00000003l +#define cpc_edc_scratch_cnt__sec_count_mask 0x0000000cl +//cpc_edc_ucode_cnt +#define cpc_edc_ucode_cnt__ded_count__shift 0x0 +#define cpc_edc_ucode_cnt__sec_count__shift 0x2 +#define cpc_edc_ucode_cnt__ded_count_mask 0x00000003l +#define cpc_edc_ucode_cnt__sec_count_mask 0x0000000cl +//dc_edc_state_cnt +#define dc_edc_state_cnt__ded_count_me1__shift 0x0 +#define dc_edc_state_cnt__sec_count_me1__shift 0x2 +#define dc_edc_state_cnt__ded_count_me1_mask 0x00000003l +#define dc_edc_state_cnt__sec_count_me1_mask 0x0000000cl +//dc_edc_csinvoc_cnt +#define dc_edc_csinvoc_cnt__ded_count_me1__shift 0x0 +#define dc_edc_csinvoc_cnt__sec_count_me1__shift 0x2 +#define dc_edc_csinvoc_cnt__ded_count1_me1__shift 0x4 +#define dc_edc_csinvoc_cnt__sec_count1_me1__shift 0x6 +#define dc_edc_csinvoc_cnt__ded_count_me1_mask 0x00000003l +#define dc_edc_csinvoc_cnt__sec_count_me1_mask 0x0000000cl +#define dc_edc_csinvoc_cnt__ded_count1_me1_mask 0x00000030l +#define dc_edc_csinvoc_cnt__sec_count1_me1_mask 0x000000c0l +//dc_edc_restore_cnt +#define dc_edc_restore_cnt__ded_count_me1__shift 0x0 +#define dc_edc_restore_cnt__sec_count_me1__shift 0x2 +#define dc_edc_restore_cnt__ded_count1_me1__shift 0x4 +#define dc_edc_restore_cnt__sec_count1_me1__shift 0x6 +#define dc_edc_restore_cnt__ded_count_me1_mask 0x00000003l +#define dc_edc_restore_cnt__sec_count_me1_mask 0x0000000cl +#define dc_edc_restore_cnt__ded_count1_me1_mask 0x00000030l +#define dc_edc_restore_cnt__sec_count1_me1_mask 0x000000c0l + +// addressblock: gc_gdsdec +//gds_edc_cnt +#define gds_edc_cnt__gds_mem_ded__shift 0x0 +#define gds_edc_cnt__gds_mem_sec__shift 0x4 +#define gds_edc_cnt__unused__shift 0x6 +#define gds_edc_cnt__gds_mem_ded_mask 0x00000003l +#define gds_edc_cnt__gds_mem_sec_mask 0x00000030l +#define gds_edc_cnt__unused_mask 0xffffffc0l +//gds_edc_grbm_cnt +#define gds_edc_grbm_cnt__ded__shift 0x0 +#define gds_edc_grbm_cnt__sec__shift 0x2 +#define gds_edc_grbm_cnt__unused__shift 0x4 +#define gds_edc_grbm_cnt__ded_mask 0x00000003l +#define gds_edc_grbm_cnt__sec_mask 0x0000000cl +#define gds_edc_grbm_cnt__unused_mask 0xfffffff0l +//gds_edc_oa_ded +#define gds_edc_oa_ded__me0_gfxhp3d_pix_ded__shift 0x0 +#define gds_edc_oa_ded__me0_gfxhp3d_vtx_ded__shift 0x1 +#define gds_edc_oa_ded__me0_cs_ded__shift 0x2 +#define gds_edc_oa_ded__me0_gfxhp3d_gs_ded__shift 0x3 +#define gds_edc_oa_ded__me1_pipe0_ded__shift 0x4 +#define gds_edc_oa_ded__me1_pipe1_ded__shift 0x5 +#define gds_edc_oa_ded__me1_pipe2_ded__shift 0x6 +#define gds_edc_oa_ded__me1_pipe3_ded__shift 0x7 +#define gds_edc_oa_ded__me2_pipe0_ded__shift 0x8 +#define gds_edc_oa_ded__me2_pipe1_ded__shift 0x9 +#define gds_edc_oa_ded__me2_pipe2_ded__shift 0xa +#define gds_edc_oa_ded__me2_pipe3_ded__shift 0xb +#define gds_edc_oa_ded__unused1__shift 0xc +#define gds_edc_oa_ded__me0_gfxhp3d_pix_ded_mask 0x00000001l +#define gds_edc_oa_ded__me0_gfxhp3d_vtx_ded_mask 0x00000002l +#define gds_edc_oa_ded__me0_cs_ded_mask 0x00000004l +#define gds_edc_oa_ded__me0_gfxhp3d_gs_ded_mask 0x00000008l +#define gds_edc_oa_ded__me1_pipe0_ded_mask 0x00000010l +#define gds_edc_oa_ded__me1_pipe1_ded_mask 0x00000020l +#define gds_edc_oa_ded__me1_pipe2_ded_mask 0x00000040l +#define gds_edc_oa_ded__me1_pipe3_ded_mask 0x00000080l +#define gds_edc_oa_ded__me2_pipe0_ded_mask 0x00000100l +#define gds_edc_oa_ded__me2_pipe1_ded_mask 0x00000200l +#define gds_edc_oa_ded__me2_pipe2_ded_mask 0x00000400l +#define gds_edc_oa_ded__me2_pipe3_ded_mask 0x00000800l +#define gds_edc_oa_ded__unused1_mask 0xfffff000l +//gds_edc_oa_phy_cnt +#define gds_edc_oa_phy_cnt__me0_cs_pipe_mem_sec__shift 0x0 +#define gds_edc_oa_phy_cnt__me0_cs_pipe_mem_ded__shift 0x2 +#define gds_edc_oa_phy_cnt__phy_cmd_ram_mem_sec__shift 0x4 +#define gds_edc_oa_phy_cnt__phy_cmd_ram_mem_ded__shift 0x6 +#define gds_edc_oa_phy_cnt__phy_data_ram_mem_sec__shift 0x8 +#define gds_edc_oa_phy_cnt__phy_data_ram_mem_ded__shift 0xa +#define gds_edc_oa_phy_cnt__unused1__shift 0xc +#define gds_edc_oa_phy_cnt__me0_cs_pipe_mem_sec_mask 0x00000003l +#define gds_edc_oa_phy_cnt__me0_cs_pipe_mem_ded_mask 0x0000000cl +#define gds_edc_oa_phy_cnt__phy_cmd_ram_mem_sec_mask 0x00000030l +#define gds_edc_oa_phy_cnt__phy_cmd_ram_mem_ded_mask 0x000000c0l +#define gds_edc_oa_phy_cnt__phy_data_ram_mem_sec_mask 0x00000300l +#define gds_edc_oa_phy_cnt__phy_data_ram_mem_ded_mask 0x00000c00l +#define gds_edc_oa_phy_cnt__unused1_mask 0xfffff000l +//gds_edc_oa_pipe_cnt +#define gds_edc_oa_pipe_cnt__me1_pipe0_pipe_mem_sec__shift 0x0 +#define gds_edc_oa_pipe_cnt__me1_pipe0_pipe_mem_ded__shift 0x2 +#define gds_edc_oa_pipe_cnt__me1_pipe1_pipe_mem_sec__shift 0x4 +#define gds_edc_oa_pipe_cnt__me1_pipe1_pipe_mem_ded__shift 0x6 +#define gds_edc_oa_pipe_cnt__me1_pipe2_pipe_mem_sec__shift 0x8 +#define gds_edc_oa_pipe_cnt__me1_pipe2_pipe_mem_ded__shift 0xa +#define gds_edc_oa_pipe_cnt__me1_pipe3_pipe_mem_sec__shift 0xc +#define gds_edc_oa_pipe_cnt__me1_pipe3_pipe_mem_ded__shift 0xe +#define gds_edc_oa_pipe_cnt__unused__shift 0x10 +#define gds_edc_oa_pipe_cnt__me1_pipe0_pipe_mem_sec_mask 0x00000003l +#define gds_edc_oa_pipe_cnt__me1_pipe0_pipe_mem_ded_mask 0x0000000cl +#define gds_edc_oa_pipe_cnt__me1_pipe1_pipe_mem_sec_mask 0x00000030l +#define gds_edc_oa_pipe_cnt__me1_pipe1_pipe_mem_ded_mask 0x000000c0l +#define gds_edc_oa_pipe_cnt__me1_pipe2_pipe_mem_sec_mask 0x00000300l +#define gds_edc_oa_pipe_cnt__me1_pipe2_pipe_mem_ded_mask 0x00000c00l +#define gds_edc_oa_pipe_cnt__me1_pipe3_pipe_mem_sec_mask 0x00003000l +#define gds_edc_oa_pipe_cnt__me1_pipe3_pipe_mem_ded_mask 0x0000c000l +#define gds_edc_oa_pipe_cnt__unused_mask 0xffff0000l + +// addressblock: gc_shsdec +//spi_edc_cnt +#define spi_edc_cnt__spi_sr_mem_sec_count__shift 0x0 +#define spi_edc_cnt__spi_sr_mem_ded_count__shift 0x2 +#define spi_edc_cnt__spi_gds_expreq_sec_count__shift 0x4 +#define spi_edc_cnt__spi_gds_expreq_ded_count__shift 0x6 +#define spi_edc_cnt__spi_wb_grant_30_sec_count__shift 0x8 +#define spi_edc_cnt__spi_wb_grant_30_ded_count__shift 0xa +#define spi_edc_cnt__spi_wb_grant_61_sec_count__shift 0xc +#define spi_edc_cnt__spi_wb_grant_61_ded_count__shift 0xe +#define spi_edc_cnt__spi_life_cnt_sec_count__shift 0x10 +#define spi_edc_cnt__spi_life_cnt_ded_count__shift 0x12 +#define spi_edc_cnt__spi_sr_mem_sec_count_mask 0x00000003l +#define spi_edc_cnt__spi_sr_mem_ded_count_mask 0x0000000cl +#define spi_edc_cnt__spi_gds_expreq_sec_count_mask 0x00000030l +#define spi_edc_cnt__spi_gds_expreq_ded_count_mask 0x000000c0l +#define spi_edc_cnt__spi_wb_grant_30_sec_count_mask 0x00000300l +#define spi_edc_cnt__spi_wb_grant_30_ded_count_mask 0x00000c00l +#define spi_edc_cnt__spi_wb_grant_61_sec_count_mask 0x00003000l +#define spi_edc_cnt__spi_wb_grant_61_ded_count_mask 0x0000c000l +#define spi_edc_cnt__spi_life_cnt_sec_count_mask 0x00030000l +#define spi_edc_cnt__spi_life_cnt_ded_count_mask 0x000c0000l + +// addressblock: gc_sqdec +//sqc_edc_cnt2 +#define sqc_edc_cnt2__inst_banka_tag_ram_sec_count__shift 0x0 +#define sqc_edc_cnt2__inst_banka_tag_ram_ded_count__shift 0x2 +#define sqc_edc_cnt2__inst_banka_bank_ram_sec_count__shift 0x4 +#define sqc_edc_cnt2__inst_banka_bank_ram_ded_count__shift 0x6 +#define sqc_edc_cnt2__data_banka_tag_ram_sec_count__shift 0x8 +#define sqc_edc_cnt2__data_banka_tag_ram_ded_count__shift 0xa +#define sqc_edc_cnt2__data_banka_bank_ram_sec_count__shift 0xc +#define sqc_edc_cnt2__data_banka_bank_ram_ded_count__shift 0xe +#define sqc_edc_cnt2__inst_utcl1_lfifo_sec_count__shift 0x10 +#define sqc_edc_cnt2__inst_utcl1_lfifo_ded_count__shift 0x12 +#define sqc_edc_cnt2__inst_banka_tag_ram_sec_count_mask 0x00000003l +#define sqc_edc_cnt2__inst_banka_tag_ram_ded_count_mask 0x0000000cl +#define sqc_edc_cnt2__inst_banka_bank_ram_sec_count_mask 0x00000030l +#define sqc_edc_cnt2__inst_banka_bank_ram_ded_count_mask 0x000000c0l +#define sqc_edc_cnt2__data_banka_tag_ram_sec_count_mask 0x00000300l +#define sqc_edc_cnt2__data_banka_tag_ram_ded_count_mask 0x00000c00l +#define sqc_edc_cnt2__data_banka_bank_ram_sec_count_mask 0x00003000l +#define sqc_edc_cnt2__data_banka_bank_ram_ded_count_mask 0x0000c000l +#define sqc_edc_cnt2__inst_utcl1_lfifo_sec_count_mask 0x00030000l +#define sqc_edc_cnt2__inst_utcl1_lfifo_ded_count_mask 0x000c0000l +//sqc_edc_cnt3 +#define sqc_edc_cnt3__inst_bankb_tag_ram_sec_count__shift 0x0 +#define sqc_edc_cnt3__inst_bankb_tag_ram_ded_count__shift 0x2 +#define sqc_edc_cnt3__inst_bankb_bank_ram_sec_count__shift 0x4 +#define sqc_edc_cnt3__inst_bankb_bank_ram_ded_count__shift 0x6 +#define sqc_edc_cnt3__data_bankb_tag_ram_sec_count__shift 0x8 +#define sqc_edc_cnt3__data_bankb_tag_ram_ded_count__shift 0xa +#define sqc_edc_cnt3__data_bankb_bank_ram_sec_count__shift 0xc +#define sqc_edc_cnt3__data_bankb_bank_ram_ded_count__shift 0xe +#define sqc_edc_cnt3__inst_bankb_tag_ram_sec_count_mask 0x00000003l +#define sqc_edc_cnt3__inst_bankb_tag_ram_ded_count_mask 0x0000000cl +#define sqc_edc_cnt3__inst_bankb_bank_ram_sec_count_mask 0x00000030l +#define sqc_edc_cnt3__inst_bankb_bank_ram_ded_count_mask 0x000000c0l +#define sqc_edc_cnt3__data_bankb_tag_ram_sec_count_mask 0x00000300l +#define sqc_edc_cnt3__data_bankb_tag_ram_ded_count_mask 0x00000c00l +#define sqc_edc_cnt3__data_bankb_bank_ram_sec_count_mask 0x00003000l +#define sqc_edc_cnt3__data_bankb_bank_ram_ded_count_mask 0x0000c000l +//sqc_edc_parity_cnt3 +#define sqc_edc_parity_cnt3__inst_banka_utcl1_miss_fifo_sec_count__shift 0x0 +#define sqc_edc_parity_cnt3__inst_banka_utcl1_miss_fifo_ded_count__shift 0x2 +#define sqc_edc_parity_cnt3__inst_banka_miss_fifo_sec_count__shift 0x4 +#define sqc_edc_parity_cnt3__inst_banka_miss_fifo_ded_count__shift 0x6 +#define sqc_edc_parity_cnt3__data_banka_hit_fifo_sec_count__shift 0x8 +#define sqc_edc_parity_cnt3__data_banka_hit_fifo_ded_count__shift 0xa +#define sqc_edc_parity_cnt3__data_banka_miss_fifo_sec_count__shift 0xc +#define sqc_edc_parity_cnt3__data_banka_miss_fifo_ded_count__shift 0xe +#define sqc_edc_parity_cnt3__inst_bankb_utcl1_miss_fifo_sec_count__shift 0x10 +#define sqc_edc_parity_cnt3__inst_bankb_utcl1_miss_fifo_ded_count__shift 0x12 +#define sqc_edc_parity_cnt3__inst_bankb_miss_fifo_sec_count__shift 0x14 +#define sqc_edc_parity_cnt3__inst_bankb_miss_fifo_ded_count__shift 0x16 +#define sqc_edc_parity_cnt3__data_bankb_hit_fifo_sec_count__shift 0x18 +#define sqc_edc_parity_cnt3__data_bankb_hit_fifo_ded_count__shift 0x1a +#define sqc_edc_parity_cnt3__data_bankb_miss_fifo_sec_count__shift 0x1c +#define sqc_edc_parity_cnt3__data_bankb_miss_fifo_ded_count__shift 0x1e +#define sqc_edc_parity_cnt3__inst_banka_utcl1_miss_fifo_sec_count_mask 0x00000003l +#define sqc_edc_parity_cnt3__inst_banka_utcl1_miss_fifo_ded_count_mask 0x0000000cl +#define sqc_edc_parity_cnt3__inst_banka_miss_fifo_sec_count_mask 0x00000030l +#define sqc_edc_parity_cnt3__inst_banka_miss_fifo_ded_count_mask 0x000000c0l +#define sqc_edc_parity_cnt3__data_banka_hit_fifo_sec_count_mask 0x00000300l +#define sqc_edc_parity_cnt3__data_banka_hit_fifo_ded_count_mask 0x00000c00l +#define sqc_edc_parity_cnt3__data_banka_miss_fifo_sec_count_mask 0x00003000l +#define sqc_edc_parity_cnt3__data_banka_miss_fifo_ded_count_mask 0x0000c000l +#define sqc_edc_parity_cnt3__inst_bankb_utcl1_miss_fifo_sec_count_mask 0x00030000l +#define sqc_edc_parity_cnt3__inst_bankb_utcl1_miss_fifo_ded_count_mask 0x000c0000l +#define sqc_edc_parity_cnt3__inst_bankb_miss_fifo_sec_count_mask 0x00300000l +#define sqc_edc_parity_cnt3__inst_bankb_miss_fifo_ded_count_mask 0x00c00000l +#define sqc_edc_parity_cnt3__data_bankb_hit_fifo_sec_count_mask 0x03000000l +#define sqc_edc_parity_cnt3__data_bankb_hit_fifo_ded_count_mask 0x0c000000l +#define sqc_edc_parity_cnt3__data_bankb_miss_fifo_sec_count_mask 0x30000000l +#define sqc_edc_parity_cnt3__data_bankb_miss_fifo_ded_count_mask 0xc0000000l +//sqc_edc_cnt +#define sqc_edc_cnt__data_cu0_write_data_buf_sec_count__shift 0x0 +#define sqc_edc_cnt__data_cu0_write_data_buf_ded_count__shift 0x2 +#define sqc_edc_cnt__data_cu0_utcl1_lfifo_sec_count__shift 0x4 +#define sqc_edc_cnt__data_cu0_utcl1_lfifo_ded_count__shift 0x6 +#define sqc_edc_cnt__data_cu1_write_data_buf_sec_count__shift 0x8 +#define sqc_edc_cnt__data_cu1_write_data_buf_ded_count__shift 0xa +#define sqc_edc_cnt__data_cu1_utcl1_lfifo_sec_count__shift 0xc +#define sqc_edc_cnt__data_cu1_utcl1_lfifo_ded_count__shift 0xe +#define sqc_edc_cnt__data_cu2_write_data_buf_sec_count__shift 0x10 +#define sqc_edc_cnt__data_cu2_write_data_buf_ded_count__shift 0x12 +#define sqc_edc_cnt__data_cu2_utcl1_lfifo_sec_count__shift 0x14 +#define sqc_edc_cnt__data_cu2_utcl1_lfifo_ded_count__shift 0x16 +#define sqc_edc_cnt__data_cu3_write_data_buf_sec_count__shift 0x18 +#define sqc_edc_cnt__data_cu3_write_data_buf_ded_count__shift 0x1a +#define sqc_edc_cnt__data_cu3_utcl1_lfifo_sec_count__shift 0x1c +#define sqc_edc_cnt__data_cu3_utcl1_lfifo_ded_count__shift 0x1e +#define sqc_edc_cnt__data_cu0_write_data_buf_sec_count_mask 0x00000003l +#define sqc_edc_cnt__data_cu0_write_data_buf_ded_count_mask 0x0000000cl +#define sqc_edc_cnt__data_cu0_utcl1_lfifo_sec_count_mask 0x00000030l +#define sqc_edc_cnt__data_cu0_utcl1_lfifo_ded_count_mask 0x000000c0l +#define sqc_edc_cnt__data_cu1_write_data_buf_sec_count_mask 0x00000300l +#define sqc_edc_cnt__data_cu1_write_data_buf_ded_count_mask 0x00000c00l +#define sqc_edc_cnt__data_cu1_utcl1_lfifo_sec_count_mask 0x00003000l +#define sqc_edc_cnt__data_cu1_utcl1_lfifo_ded_count_mask 0x0000c000l +#define sqc_edc_cnt__data_cu2_write_data_buf_sec_count_mask 0x00030000l +#define sqc_edc_cnt__data_cu2_write_data_buf_ded_count_mask 0x000c0000l +#define sqc_edc_cnt__data_cu2_utcl1_lfifo_sec_count_mask 0x00300000l +#define sqc_edc_cnt__data_cu2_utcl1_lfifo_ded_count_mask 0x00c00000l +#define sqc_edc_cnt__data_cu3_write_data_buf_sec_count_mask 0x03000000l +#define sqc_edc_cnt__data_cu3_write_data_buf_ded_count_mask 0x0c000000l +#define sqc_edc_cnt__data_cu3_utcl1_lfifo_sec_count_mask 0x30000000l +#define sqc_edc_cnt__data_cu3_utcl1_lfifo_ded_count_mask 0xc0000000l +//sq_edc_sec_cnt +#define sq_edc_sec_cnt__lds_sec__shift 0x0 +#define sq_edc_sec_cnt__sgpr_sec__shift 0x8 +#define sq_edc_sec_cnt__vgpr_sec__shift 0x10 +#define sq_edc_sec_cnt__lds_sec_mask 0x000000ffl +#define sq_edc_sec_cnt__sgpr_sec_mask 0x0000ff00l +#define sq_edc_sec_cnt__vgpr_sec_mask 0x00ff0000l +//sq_edc_ded_cnt +#define sq_edc_ded_cnt__lds_ded__shift 0x0 +#define sq_edc_ded_cnt__sgpr_ded__shift 0x8 +#define sq_edc_ded_cnt__vgpr_ded__shift 0x10 +#define sq_edc_ded_cnt__lds_ded_mask 0x000000ffl +#define sq_edc_ded_cnt__sgpr_ded_mask 0x0000ff00l +#define sq_edc_ded_cnt__vgpr_ded_mask 0x00ff0000l +//sq_edc_info +#define sq_edc_info__wave_id__shift 0x0 +#define sq_edc_info__simd_id__shift 0x4 +#define sq_edc_info__source__shift 0x6 +#define sq_edc_info__vm_id__shift 0x9 +#define sq_edc_info__wave_id_mask 0x0000000fl +#define sq_edc_info__simd_id_mask 0x00000030l +#define sq_edc_info__source_mask 0x000001c0l +#define sq_edc_info__vm_id_mask 0x00001e00l +//sq_edc_cnt +#define sq_edc_cnt__lds_d_sec_count__shift 0x0 +#define sq_edc_cnt__lds_d_ded_count__shift 0x2 +#define sq_edc_cnt__lds_i_sec_count__shift 0x4 +#define sq_edc_cnt__lds_i_ded_count__shift 0x6 +#define sq_edc_cnt__sgpr_sec_count__shift 0x8 +#define sq_edc_cnt__sgpr_ded_count__shift 0xa +#define sq_edc_cnt__vgpr0_sec_count__shift 0xc +#define sq_edc_cnt__vgpr0_ded_count__shift 0xe +#define sq_edc_cnt__vgpr1_sec_count__shift 0x10 +#define sq_edc_cnt__vgpr1_ded_count__shift 0x12 +#define sq_edc_cnt__vgpr2_sec_count__shift 0x14 +#define sq_edc_cnt__vgpr2_ded_count__shift 0x16 +#define sq_edc_cnt__vgpr3_sec_count__shift 0x18 +#define sq_edc_cnt__vgpr3_ded_count__shift 0x1a +#define sq_edc_cnt__lds_d_sec_count_mask 0x00000003l +#define sq_edc_cnt__lds_d_ded_count_mask 0x0000000cl +#define sq_edc_cnt__lds_i_sec_count_mask 0x00000030l +#define sq_edc_cnt__lds_i_ded_count_mask 0x000000c0l +#define sq_edc_cnt__sgpr_sec_count_mask 0x00000300l +#define sq_edc_cnt__sgpr_ded_count_mask 0x00000c00l +#define sq_edc_cnt__vgpr0_sec_count_mask 0x00003000l +#define sq_edc_cnt__vgpr0_ded_count_mask 0x0000c000l +#define sq_edc_cnt__vgpr1_sec_count_mask 0x00030000l +#define sq_edc_cnt__vgpr1_ded_count_mask 0x000c0000l +#define sq_edc_cnt__vgpr2_sec_count_mask 0x00300000l +#define sq_edc_cnt__vgpr2_ded_count_mask 0x00c00000l +#define sq_edc_cnt__vgpr3_sec_count_mask 0x03000000l +#define sq_edc_cnt__vgpr3_ded_count_mask 0x0c000000l + +// addressblock: gc_tpdec +//ta_edc_cnt +#define ta_edc_cnt__ta_fs_dfifo_sec_count__shift 0x0 +#define ta_edc_cnt__ta_fs_dfifo_ded_count__shift 0x2 +#define ta_edc_cnt__ta_fs_afifo_sec_count__shift 0x4 +#define ta_edc_cnt__ta_fs_afifo_ded_count__shift 0x6 +#define ta_edc_cnt__ta_fl_lfifo_sec_count__shift 0x8 +#define ta_edc_cnt__ta_fl_lfifo_ded_count__shift 0xa +#define ta_edc_cnt__ta_fx_lfifo_sec_count__shift 0xc +#define ta_edc_cnt__ta_fx_lfifo_ded_count__shift 0xe +#define ta_edc_cnt__ta_fs_cfifo_sec_count__shift 0x10 +#define ta_edc_cnt__ta_fs_cfifo_ded_count__shift 0x12 +#define ta_edc_cnt__ta_fs_dfifo_sec_count_mask 0x00000003l +#define ta_edc_cnt__ta_fs_dfifo_ded_count_mask 0x0000000cl +#define ta_edc_cnt__ta_fs_afifo_sec_count_mask 0x00000030l +#define ta_edc_cnt__ta_fs_afifo_ded_count_mask 0x000000c0l +#define ta_edc_cnt__ta_fl_lfifo_sec_count_mask 0x00000300l +#define ta_edc_cnt__ta_fl_lfifo_ded_count_mask 0x00000c00l +#define ta_edc_cnt__ta_fx_lfifo_sec_count_mask 0x00003000l +#define ta_edc_cnt__ta_fx_lfifo_ded_count_mask 0x0000c000l +#define ta_edc_cnt__ta_fs_cfifo_sec_count_mask 0x00030000l +#define ta_edc_cnt__ta_fs_cfifo_ded_count_mask 0x000c0000l + +// addressblock: gc_tcdec +//tcp_edc_cnt +#define tcp_edc_cnt__sec_count__shift 0x0 +#define tcp_edc_cnt__lfifo_sed_count__shift 0x8 +#define tcp_edc_cnt__ded_count__shift 0x10 +#define tcp_edc_cnt__sec_count_mask 0x000000ffl +#define tcp_edc_cnt__lfifo_sed_count_mask 0x0000ff00l +#define tcp_edc_cnt__ded_count_mask 0x00ff0000l +//tcp_edc_cnt_new +#define tcp_edc_cnt_new__cache_ram_sec_count__shift 0x0 +#define tcp_edc_cnt_new__cache_ram_ded_count__shift 0x2 +#define tcp_edc_cnt_new__lfifo_ram_sec_count__shift 0x4 +#define tcp_edc_cnt_new__lfifo_ram_ded_count__shift 0x6 +#define tcp_edc_cnt_new__cmd_fifo_sec_count__shift 0x8 +#define tcp_edc_cnt_new__cmd_fifo_ded_count__shift 0xa +#define tcp_edc_cnt_new__vm_fifo_sec_count__shift 0xc +#define tcp_edc_cnt_new__vm_fifo_ded_count__shift 0xe +#define tcp_edc_cnt_new__db_ram_sed_count__shift 0x10 +#define tcp_edc_cnt_new__utcl1_lfifo0_sec_count__shift 0x12 +#define tcp_edc_cnt_new__utcl1_lfifo0_ded_count__shift 0x14 +#define tcp_edc_cnt_new__utcl1_lfifo1_sec_count__shift 0x16 +#define tcp_edc_cnt_new__utcl1_lfifo1_ded_count__shift 0x18 +#define tcp_edc_cnt_new__cache_ram_sec_count_mask 0x00000003l +#define tcp_edc_cnt_new__cache_ram_ded_count_mask 0x0000000cl +#define tcp_edc_cnt_new__lfifo_ram_sec_count_mask 0x00000030l +#define tcp_edc_cnt_new__lfifo_ram_ded_count_mask 0x000000c0l +#define tcp_edc_cnt_new__cmd_fifo_sec_count_mask 0x00000300l +#define tcp_edc_cnt_new__cmd_fifo_ded_count_mask 0x00000c00l +#define tcp_edc_cnt_new__vm_fifo_sec_count_mask 0x00003000l +#define tcp_edc_cnt_new__vm_fifo_ded_count_mask 0x0000c000l +#define tcp_edc_cnt_new__db_ram_sed_count_mask 0x00030000l +#define tcp_edc_cnt_new__utcl1_lfifo0_sec_count_mask 0x000c0000l +#define tcp_edc_cnt_new__utcl1_lfifo0_ded_count_mask 0x00300000l +#define tcp_edc_cnt_new__utcl1_lfifo1_sec_count_mask 0x00c00000l +#define tcp_edc_cnt_new__utcl1_lfifo1_ded_count_mask 0x03000000l +//tcp_atc_edc_gatcl1_cnt +#define tcp_atc_edc_gatcl1_cnt__data_sec__shift 0x0 +#define tcp_atc_edc_gatcl1_cnt__data_sec_mask 0x000000ffl +//tci_edc_cnt +#define tci_edc_cnt__write_ram_sec_count__shift 0x0 +#define tci_edc_cnt__write_ram_ded_count__shift 0x2 +#define tci_edc_cnt__write_ram_sec_count_mask 0x00000003l +#define tci_edc_cnt__write_ram_ded_count_mask 0x0000000cl +//tca_edc_cnt +#define tca_edc_cnt__hole_fifo_sec_count__shift 0x0 +#define tca_edc_cnt__hole_fifo_ded_count__shift 0x2 +#define tca_edc_cnt__req_fifo_sec_count__shift 0x4 +#define tca_edc_cnt__req_fifo_ded_count__shift 0x6 +#define tca_edc_cnt__hole_fifo_sec_count_mask 0x00000003l +#define tca_edc_cnt__hole_fifo_ded_count_mask 0x0000000cl +#define tca_edc_cnt__req_fifo_sec_count_mask 0x00000030l +#define tca_edc_cnt__req_fifo_ded_count_mask 0x000000c0l +//tcc_edc_cnt +#define tcc_edc_cnt__cache_data_sec_count__shift 0x0 +#define tcc_edc_cnt__cache_data_ded_count__shift 0x2 +#define tcc_edc_cnt__cache_dirty_sec_count__shift 0x4 +#define tcc_edc_cnt__cache_dirty_ded_count__shift 0x6 +#define tcc_edc_cnt__high_rate_tag_sec_count__shift 0x8 +#define tcc_edc_cnt__high_rate_tag_ded_count__shift 0xa +#define tcc_edc_cnt__low_rate_tag_sec_count__shift 0xc +#define tcc_edc_cnt__low_rate_tag_ded_count__shift 0xe +#define tcc_edc_cnt__src_fifo_sec_count__shift 0x10 +#define tcc_edc_cnt__src_fifo_ded_count__shift 0x12 +#define tcc_edc_cnt__latency_fifo_sec_count__shift 0x14 +#define tcc_edc_cnt__latency_fifo_ded_count__shift 0x16 +#define tcc_edc_cnt__latency_fifo_next_ram_sec_count__shift 0x18 +#define tcc_edc_cnt__latency_fifo_next_ram_ded_count__shift 0x1a +#define tcc_edc_cnt__cache_data_sec_count_mask 0x00000003l +#define tcc_edc_cnt__cache_data_ded_count_mask 0x0000000cl +#define tcc_edc_cnt__cache_dirty_sec_count_mask 0x00000030l +#define tcc_edc_cnt__cache_dirty_ded_count_mask 0x000000c0l +#define tcc_edc_cnt__high_rate_tag_sec_count_mask 0x00000300l +#define tcc_edc_cnt__high_rate_tag_ded_count_mask 0x00000c00l +#define tcc_edc_cnt__low_rate_tag_sec_count_mask 0x00003000l +#define tcc_edc_cnt__low_rate_tag_ded_count_mask 0x0000c000l +#define tcc_edc_cnt__src_fifo_sec_count_mask 0x00030000l +#define tcc_edc_cnt__src_fifo_ded_count_mask 0x000c0000l +#define tcc_edc_cnt__latency_fifo_sec_count_mask 0x00300000l +#define tcc_edc_cnt__latency_fifo_ded_count_mask 0x00c00000l +#define tcc_edc_cnt__latency_fifo_next_ram_sec_count_mask 0x03000000l +#define tcc_edc_cnt__latency_fifo_next_ram_ded_count_mask 0x0c000000l +//tcc_edc_cnt2 +#define tcc_edc_cnt2__cache_tag_probe_fifo_sec_count__shift 0x0 +#define tcc_edc_cnt2__cache_tag_probe_fifo_ded_count__shift 0x2 +#define tcc_edc_cnt2__uc_atomic_fifo_sec_count__shift 0x4 +#define tcc_edc_cnt2__uc_atomic_fifo_ded_count__shift 0x6 +#define tcc_edc_cnt2__write_cache_read_sec_count__shift 0x8 +#define tcc_edc_cnt2__write_cache_read_ded_count__shift 0xa +#define tcc_edc_cnt2__return_control_sec_count__shift 0xc +#define tcc_edc_cnt2__return_control_ded_count__shift 0xe +#define tcc_edc_cnt2__in_use_transfer_sec_count__shift 0x10 +#define tcc_edc_cnt2__in_use_transfer_ded_count__shift 0x12 +#define tcc_edc_cnt2__in_use_dec_sec_count__shift 0x14 +#define tcc_edc_cnt2__in_use_dec_ded_count__shift 0x16 +#define tcc_edc_cnt2__write_return_sec_count__shift 0x18 +#define tcc_edc_cnt2__write_return_ded_count__shift 0x1a +#define tcc_edc_cnt2__return_data_sec_count__shift 0x1c +#define tcc_edc_cnt2__return_data_ded_count__shift 0x1e +#define tcc_edc_cnt2__cache_tag_probe_fifo_sec_count_mask 0x00000003l +#define tcc_edc_cnt2__cache_tag_probe_fifo_ded_count_mask 0x0000000cl +#define tcc_edc_cnt2__uc_atomic_fifo_sec_count_mask 0x00000030l +#define tcc_edc_cnt2__uc_atomic_fifo_ded_count_mask 0x000000c0l +#define tcc_edc_cnt2__write_cache_read_sec_count_mask 0x00000300l +#define tcc_edc_cnt2__write_cache_read_ded_count_mask 0x00000c00l +#define tcc_edc_cnt2__return_control_sec_count_mask 0x00003000l +#define tcc_edc_cnt2__return_control_ded_count_mask 0x0000c000l +#define tcc_edc_cnt2__in_use_transfer_sec_count_mask 0x00030000l +#define tcc_edc_cnt2__in_use_transfer_ded_count_mask 0x000c0000l +#define tcc_edc_cnt2__in_use_dec_sec_count_mask 0x00300000l +#define tcc_edc_cnt2__in_use_dec_ded_count_mask 0x00c00000l +#define tcc_edc_cnt2__write_return_sec_count_mask 0x03000000l +#define tcc_edc_cnt2__write_return_ded_count_mask 0x0c000000l +#define tcc_edc_cnt2__return_data_sec_count_mask 0x30000000l +#define tcc_edc_cnt2__return_data_ded_count_mask 0xc0000000l + +// addressblock: gc_tpdec +//td_edc_cnt +#define td_edc_cnt__ss_fifo_lo_sec_count__shift 0x0 +#define td_edc_cnt__ss_fifo_lo_ded_count__shift 0x2 +#define td_edc_cnt__ss_fifo_hi_sec_count__shift 0x4 +#define td_edc_cnt__ss_fifo_hi_ded_count__shift 0x6 +#define td_edc_cnt__cs_fifo_sec_count__shift 0x8 +#define td_edc_cnt__cs_fifo_ded_count__shift 0xa +#define td_edc_cnt__ss_fifo_lo_sec_count_mask 0x00000003l +#define td_edc_cnt__ss_fifo_lo_ded_count_mask 0x0000000cl +#define td_edc_cnt__ss_fifo_hi_sec_count_mask 0x00000030l +#define td_edc_cnt__ss_fifo_hi_ded_count_mask 0x000000c0l +#define td_edc_cnt__cs_fifo_sec_count_mask 0x00000300l +#define td_edc_cnt__cs_fifo_ded_count_mask 0x00000c00l +//ta_edc_cnt +#define ta_edc_cnt__ta_fs_dfifo_sec_count__shift 0x0 +#define ta_edc_cnt__ta_fs_dfifo_ded_count__shift 0x2 +#define ta_edc_cnt__ta_fs_afifo_sec_count__shift 0x4 +#define ta_edc_cnt__ta_fs_afifo_ded_count__shift 0x6 +#define ta_edc_cnt__ta_fl_lfifo_sec_count__shift 0x8 +#define ta_edc_cnt__ta_fl_lfifo_ded_count__shift 0xa +#define ta_edc_cnt__ta_fx_lfifo_sec_count__shift 0xc +#define ta_edc_cnt__ta_fx_lfifo_ded_count__shift 0xe +#define ta_edc_cnt__ta_fs_cfifo_sec_count__shift 0x10 +#define ta_edc_cnt__ta_fs_cfifo_ded_count__shift 0x12 +#define ta_edc_cnt__ta_fs_dfifo_sec_count_mask 0x00000003l +#define ta_edc_cnt__ta_fs_dfifo_ded_count_mask 0x0000000cl +#define ta_edc_cnt__ta_fs_afifo_sec_count_mask 0x00000030l +#define ta_edc_cnt__ta_fs_afifo_ded_count_mask 0x000000c0l +#define ta_edc_cnt__ta_fl_lfifo_sec_count_mask 0x00000300l +#define ta_edc_cnt__ta_fl_lfifo_ded_count_mask 0x00000c00l +#define ta_edc_cnt__ta_fx_lfifo_sec_count_mask 0x00003000l +#define ta_edc_cnt__ta_fx_lfifo_ded_count_mask 0x0000c000l +#define ta_edc_cnt__ta_fs_cfifo_sec_count_mask 0x00030000l +#define ta_edc_cnt__ta_fs_cfifo_ded_count_mask 0x000c0000l + +// addressblock: gc_ea_gceadec2 +//gcea_edc_cnt +#define gcea_edc_cnt__dramrd_cmdmem_sec_count__shift 0x0 +#define gcea_edc_cnt__dramrd_cmdmem_ded_count__shift 0x2 +#define gcea_edc_cnt__dramwr_cmdmem_sec_count__shift 0x4 +#define gcea_edc_cnt__dramwr_cmdmem_ded_count__shift 0x6 +#define gcea_edc_cnt__dramwr_datamem_sec_count__shift 0x8 +#define gcea_edc_cnt__dramwr_datamem_ded_count__shift 0xa +#define gcea_edc_cnt__rret_tagmem_sec_count__shift 0xc +#define gcea_edc_cnt__rret_tagmem_ded_count__shift 0xe +#define gcea_edc_cnt__wret_tagmem_sec_count__shift 0x10 +#define gcea_edc_cnt__wret_tagmem_ded_count__shift 0x12 +#define gcea_edc_cnt__dramrd_pagemem_sed_count__shift 0x14 +#define gcea_edc_cnt__dramwr_pagemem_sed_count__shift 0x16 +#define gcea_edc_cnt__iord_cmdmem_sed_count__shift 0x18 +#define gcea_edc_cnt__iowr_cmdmem_sed_count__shift 0x1a +#define gcea_edc_cnt__iowr_datamem_sed_count__shift 0x1c +#define gcea_edc_cnt__mam_afmem_sec_count__shift 0x1e +#define gcea_edc_cnt__dramrd_cmdmem_sec_count_mask 0x00000003l +#define gcea_edc_cnt__dramrd_cmdmem_ded_count_mask 0x0000000cl +#define gcea_edc_cnt__dramwr_cmdmem_sec_count_mask 0x00000030l +#define gcea_edc_cnt__dramwr_cmdmem_ded_count_mask 0x000000c0l +#define gcea_edc_cnt__dramwr_datamem_sec_count_mask 0x00000300l +#define gcea_edc_cnt__dramwr_datamem_ded_count_mask 0x00000c00l +#define gcea_edc_cnt__rret_tagmem_sec_count_mask 0x00003000l +#define gcea_edc_cnt__rret_tagmem_ded_count_mask 0x0000c000l +#define gcea_edc_cnt__wret_tagmem_sec_count_mask 0x00030000l +#define gcea_edc_cnt__wret_tagmem_ded_count_mask 0x000c0000l +#define gcea_edc_cnt__dramrd_pagemem_sed_count_mask 0x00300000l +#define gcea_edc_cnt__dramwr_pagemem_sed_count_mask 0x00c00000l +#define gcea_edc_cnt__iord_cmdmem_sed_count_mask 0x03000000l +#define gcea_edc_cnt__iowr_cmdmem_sed_count_mask 0x0c000000l +#define gcea_edc_cnt__iowr_datamem_sed_count_mask 0x30000000l +#define gcea_edc_cnt__mam_afmem_sec_count_mask 0xc0000000l +//gcea_edc_cnt2 +#define gcea_edc_cnt2__gmird_cmdmem_sec_count__shift 0x0 +#define gcea_edc_cnt2__gmird_cmdmem_ded_count__shift 0x2 +#define gcea_edc_cnt2__gmiwr_cmdmem_sec_count__shift 0x4 +#define gcea_edc_cnt2__gmiwr_cmdmem_ded_count__shift 0x6 +#define gcea_edc_cnt2__gmiwr_datamem_sec_count__shift 0x8 +#define gcea_edc_cnt2__gmiwr_datamem_ded_count__shift 0xa +#define gcea_edc_cnt2__gmird_pagemem_sed_count__shift 0xc +#define gcea_edc_cnt2__gmiwr_pagemem_sed_count__shift 0xe +#define gcea_edc_cnt2__mam_d0mem_sed_count__shift 0x10 +#define gcea_edc_cnt2__mam_d1mem_sed_count__shift 0x12 +#define gcea_edc_cnt2__mam_d2mem_sed_count__shift 0x14 +#define gcea_edc_cnt2__mam_d3mem_sed_count__shift 0x16 +#define gcea_edc_cnt2__mam_d0mem_ded_count__shift 0x18 +#define gcea_edc_cnt2__mam_d1mem_ded_count__shift 0x1a +#define gcea_edc_cnt2__mam_d2mem_ded_count__shift 0x1c +#define gcea_edc_cnt2__mam_d3mem_ded_count__shift 0x1e +#define gcea_edc_cnt2__gmird_cmdmem_sec_count_mask 0x00000003l +#define gcea_edc_cnt2__gmird_cmdmem_ded_count_mask 0x0000000cl +#define gcea_edc_cnt2__gmiwr_cmdmem_sec_count_mask 0x00000030l +#define gcea_edc_cnt2__gmiwr_cmdmem_ded_count_mask 0x000000c0l +#define gcea_edc_cnt2__gmiwr_datamem_sec_count_mask 0x00000300l +#define gcea_edc_cnt2__gmiwr_datamem_ded_count_mask 0x00000c00l +#define gcea_edc_cnt2__gmird_pagemem_sed_count_mask 0x00003000l +#define gcea_edc_cnt2__gmiwr_pagemem_sed_count_mask 0x0000c000l +#define gcea_edc_cnt2__mam_d0mem_sed_count_mask 0x00030000l +#define gcea_edc_cnt2__mam_d1mem_sed_count_mask 0x000c0000l +#define gcea_edc_cnt2__mam_d2mem_sed_count_mask 0x00300000l +#define gcea_edc_cnt2__mam_d3mem_sed_count_mask 0x00c00000l +#define gcea_edc_cnt2__mam_d0mem_ded_count_mask 0x03000000l +#define gcea_edc_cnt2__mam_d1mem_ded_count_mask 0x0c000000l +#define gcea_edc_cnt2__mam_d2mem_ded_count_mask 0x30000000l +#define gcea_edc_cnt2__mam_d3mem_ded_count_mask 0xc0000000l +//gcea_edc_cnt3 +#define gcea_edc_cnt3__dramrd_pagemem_ded_count__shift 0x0 +#define gcea_edc_cnt3__dramwr_pagemem_ded_count__shift 0x2 +#define gcea_edc_cnt3__iord_cmdmem_ded_count__shift 0x4 +#define gcea_edc_cnt3__iowr_cmdmem_ded_count__shift 0x6 +#define gcea_edc_cnt3__iowr_datamem_ded_count__shift 0x8 +#define gcea_edc_cnt3__gmird_pagemem_ded_count__shift 0xa +#define gcea_edc_cnt3__gmiwr_pagemem_ded_count__shift 0xc +#define gcea_edc_cnt3__mam_afmem_ded_count__shift 0xe +#define gcea_edc_cnt3__mam_a0mem_sec_count__shift 0x10 +#define gcea_edc_cnt3__mam_a0mem_ded_count__shift 0x12 +#define gcea_edc_cnt3__mam_a1mem_sec_count__shift 0x14 +#define gcea_edc_cnt3__mam_a1mem_ded_count__shift 0x16 +#define gcea_edc_cnt3__mam_a2mem_sec_count__shift 0x18 +#define gcea_edc_cnt3__mam_a2mem_ded_count__shift 0x1a +#define gcea_edc_cnt3__mam_a3mem_sec_count__shift 0x1c +#define gcea_edc_cnt3__mam_a3mem_ded_count__shift 0x1e +#define gcea_edc_cnt3__dramrd_pagemem_ded_count_mask 0x00000003l +#define gcea_edc_cnt3__dramwr_pagemem_ded_count_mask 0x0000000cl +#define gcea_edc_cnt3__iord_cmdmem_ded_count_mask 0x00000030l +#define gcea_edc_cnt3__iowr_cmdmem_ded_count_mask 0x000000c0l +#define gcea_edc_cnt3__iowr_datamem_ded_count_mask 0x00000300l +#define gcea_edc_cnt3__gmird_pagemem_ded_count_mask 0x00000c00l +#define gcea_edc_cnt3__gmiwr_pagemem_ded_count_mask 0x00003000l +#define gcea_edc_cnt3__mam_afmem_ded_count_mask 0x0000c000l +#define gcea_edc_cnt3__mam_a0mem_sec_count_mask 0x00030000l +#define gcea_edc_cnt3__mam_a0mem_ded_count_mask 0x000c0000l +#define gcea_edc_cnt3__mam_a1mem_sec_count_mask 0x00300000l +#define gcea_edc_cnt3__mam_a1mem_ded_count_mask 0x00c00000l +#define gcea_edc_cnt3__mam_a2mem_sec_count_mask 0x03000000l +#define gcea_edc_cnt3__mam_a2mem_ded_count_mask 0x0c000000l +#define gcea_edc_cnt3__mam_a3mem_sec_count_mask 0x30000000l +#define gcea_edc_cnt3__mam_a3mem_ded_count_mask 0xc0000000l + +// addressblock: gc_gfxudec +//grbm_gfx_index +#define grbm_gfx_index__instance_index__shift 0x0 +#define grbm_gfx_index__sh_index__shift 0x8 +#define grbm_gfx_index__se_index__shift 0x10 +#define grbm_gfx_index__sh_broadcast_writes__shift 0x1d +#define grbm_gfx_index__instance_broadcast_writes__shift 0x1e +#define grbm_gfx_index__se_broadcast_writes__shift 0x1f +#define grbm_gfx_index__instance_index_mask 0x000000ffl +#define grbm_gfx_index__sh_index_mask 0x0000ff00l +#define grbm_gfx_index__se_index_mask 0x00ff0000l +#define grbm_gfx_index__sh_broadcast_writes_mask 0x20000000l +#define grbm_gfx_index__instance_broadcast_writes_mask 0x40000000l +#define grbm_gfx_index__se_broadcast_writes_mask 0x80000000l + +// addressblock: gc_utcl2_atcl2dec +//atc_l2_cntl +//atc_l2_cache_4k_dsm_index +#define atc_l2_cache_4k_dsm_index__index__shift 0x0 +#define atc_l2_cache_4k_dsm_index__index_mask 0x000000ffl +//atc_l2_cache_2m_dsm_index +#define atc_l2_cache_2m_dsm_index__index__shift 0x0 +#define atc_l2_cache_2m_dsm_index__index_mask 0x000000ffl +//atc_l2_cache_4k_dsm_cntl +#define atc_l2_cache_4k_dsm_cntl__sec_count__shift 0xd +#define atc_l2_cache_4k_dsm_cntl__ded_count__shift 0xf +#define atc_l2_cache_4k_dsm_cntl__sec_count_mask 0x00006000l +#define atc_l2_cache_4k_dsm_cntl__ded_count_mask 0x00018000l +//atc_l2_cache_2m_dsm_cntl +#define atc_l2_cache_2m_dsm_cntl__sec_count__shift 0xd +#define atc_l2_cache_2m_dsm_cntl__ded_count__shift 0xf +#define atc_l2_cache_2m_dsm_cntl__sec_count_mask 0x00006000l +#define atc_l2_cache_2m_dsm_cntl__ded_count_mask 0x00018000l + +// addressblock: gc_utcl2_vml2pfdec +//vml2_mem_ecc_index +#define vml2_mem_ecc_index__index__shift 0x0 +#define vml2_mem_ecc_index__index_mask 0x000000ffl +//vml2_walker_mem_ecc_index +#define vml2_walker_mem_ecc_index__index__shift 0x0 +#define vml2_walker_mem_ecc_index__index_mask 0x000000ffl +//utcl2_mem_ecc_index +#define utcl2_mem_ecc_index__index__shift 0x0 +#define utcl2_mem_ecc_index__index_mask 0x000000ffl +//vml2_mem_ecc_cntl +#define vml2_mem_ecc_cntl__sec_count__shift 0xc +#define vml2_mem_ecc_cntl__ded_count__shift 0xe +#define vml2_mem_ecc_cntl__sec_count_mask 0x00003000l +#define vml2_mem_ecc_cntl__ded_count_mask 0x0000c000l +//vml2_walker_mem_ecc_cntl +#define vml2_walker_mem_ecc_cntl__sec_count__shift 0xc +#define vml2_walker_mem_ecc_cntl__ded_count__shift 0xe +#define vml2_walker_mem_ecc_cntl__sec_count_mask 0x00003000l +#define vml2_walker_mem_ecc_cntl__ded_count_mask 0x0000c000l +//utcl2_mem_ecc_cntl +#define utcl2_mem_ecc_cntl__sec_count__shift 0xc +#define utcl2_mem_ecc_cntl__ded_count__shift 0xe +#define utcl2_mem_ecc_cntl__sec_count_mask 0x00003000l +#define utcl2_mem_ecc_cntl__ded_count_mask 0x0000c000l + +// addressblock: gc_rlcpdec +//rlc_edc_cnt +#define rlc_edc_cnt__rlcg_instr_ram_sec_count__shift 0x0 +#define rlc_edc_cnt__rlcg_instr_ram_ded_count__shift 0x2 +#define rlc_edc_cnt__rlcg_scratch_ram_sec_count__shift 0x4 +#define rlc_edc_cnt__rlcg_scratch_ram_ded_count__shift 0x6 +#define rlc_edc_cnt__rlcv_instr_ram_sec_count__shift 0x8 +#define rlc_edc_cnt__rlcv_instr_ram_ded_count__shift 0xa +#define rlc_edc_cnt__rlcv_scratch_ram_sec_count__shift 0xc +#define rlc_edc_cnt__rlcv_scratch_ram_ded_count__shift 0xe +#define rlc_edc_cnt__rlc_tctag_ram_sec_count__shift 0x10 +#define rlc_edc_cnt__rlc_tctag_ram_ded_count__shift 0x12 +#define rlc_edc_cnt__rlc_spm_scratch_ram_sec_count__shift 0x14 +#define rlc_edc_cnt__rlc_spm_scratch_ram_ded_count__shift 0x16 +#define rlc_edc_cnt__rlc_srm_data_ram_sec_count__shift 0x18 +#define rlc_edc_cnt__rlc_srm_data_ram_ded_count__shift 0x1a +#define rlc_edc_cnt__rlc_srm_addr_ram_sec_count__shift 0x1c +#define rlc_edc_cnt__rlc_srm_addr_ram_ded_count__shift 0x1e +#define rlc_edc_cnt__rlcg_instr_ram_sec_count_mask 0x00000003l +#define rlc_edc_cnt__rlcg_instr_ram_ded_count_mask 0x0000000cl +#define rlc_edc_cnt__rlcg_scratch_ram_sec_count_mask 0x00000030l +#define rlc_edc_cnt__rlcg_scratch_ram_ded_count_mask 0x000000c0l +#define rlc_edc_cnt__rlcv_instr_ram_sec_count_mask 0x00000300l +#define rlc_edc_cnt__rlcv_instr_ram_ded_count_mask 0x00000c00l +#define rlc_edc_cnt__rlcv_scratch_ram_sec_count_mask 0x00003000l +#define rlc_edc_cnt__rlcv_scratch_ram_ded_count_mask 0x0000c000l +#define rlc_edc_cnt__rlc_tctag_ram_sec_count_mask 0x00030000l +#define rlc_edc_cnt__rlc_tctag_ram_ded_count_mask 0x000c0000l +#define rlc_edc_cnt__rlc_spm_scratch_ram_sec_count_mask 0x00300000l +#define rlc_edc_cnt__rlc_spm_scratch_ram_ded_count_mask 0x00c00000l +#define rlc_edc_cnt__rlc_srm_data_ram_sec_count_mask 0x03000000l +#define rlc_edc_cnt__rlc_srm_data_ram_ded_count_mask 0x0c000000l +#define rlc_edc_cnt__rlc_srm_addr_ram_sec_count_mask 0x30000000l +#define rlc_edc_cnt__rlc_srm_addr_ram_ded_count_mask 0xc0000000l +//rlc_edc_cnt2 +#define rlc_edc_cnt2__rlc_spm_se0_scratch_ram_sec_count__shift 0x0 +#define rlc_edc_cnt2__rlc_spm_se0_scratch_ram_ded_count__shift 0x2 +#define rlc_edc_cnt2__rlc_spm_se1_scratch_ram_sec_count__shift 0x4 +#define rlc_edc_cnt2__rlc_spm_se1_scratch_ram_ded_count__shift 0x6 +#define rlc_edc_cnt2__rlc_spm_se2_scratch_ram_sec_count__shift 0x8 +#define rlc_edc_cnt2__rlc_spm_se2_scratch_ram_ded_count__shift 0xa +#define rlc_edc_cnt2__rlc_spm_se3_scratch_ram_sec_count__shift 0xc +#define rlc_edc_cnt2__rlc_spm_se3_scratch_ram_ded_count__shift 0xe +#define rlc_edc_cnt2__rlc_spm_se4_scratch_ram_sec_count__shift 0x10 +#define rlc_edc_cnt2__rlc_spm_se4_scratch_ram_ded_count__shift 0x12 +#define rlc_edc_cnt2__rlc_spm_se5_scratch_ram_sec_count__shift 0x14 +#define rlc_edc_cnt2__rlc_spm_se5_scratch_ram_ded_count__shift 0x16 +#define rlc_edc_cnt2__rlc_spm_se6_scratch_ram_sec_count__shift 0x18 +#define rlc_edc_cnt2__rlc_spm_se6_scratch_ram_ded_count__shift 0x1a +#define rlc_edc_cnt2__rlc_spm_se7_scratch_ram_sec_count__shift 0x1c +#define rlc_edc_cnt2__rlc_spm_se7_scratch_ram_ded_count__shift 0x1e +#define rlc_edc_cnt2__rlc_spm_se0_scratch_ram_sec_count_mask 0x00000003l +#define rlc_edc_cnt2__rlc_spm_se0_scratch_ram_ded_count_mask 0x0000000cl +#define rlc_edc_cnt2__rlc_spm_se1_scratch_ram_sec_count_mask 0x00000030l +#define rlc_edc_cnt2__rlc_spm_se1_scratch_ram_ded_count_mask 0x000000c0l +#define rlc_edc_cnt2__rlc_spm_se2_scratch_ram_sec_count_mask 0x00000300l +#define rlc_edc_cnt2__rlc_spm_se2_scratch_ram_ded_count_mask 0x00000c00l +#define rlc_edc_cnt2__rlc_spm_se3_scratch_ram_sec_count_mask 0x00003000l +#define rlc_edc_cnt2__rlc_spm_se3_scratch_ram_ded_count_mask 0x0000c000l +#define rlc_edc_cnt2__rlc_spm_se4_scratch_ram_sec_count_mask 0x00030000l +#define rlc_edc_cnt2__rlc_spm_se4_scratch_ram_ded_count_mask 0x000c0000l +#define rlc_edc_cnt2__rlc_spm_se5_scratch_ram_sec_count_mask 0x00300000l +#define rlc_edc_cnt2__rlc_spm_se5_scratch_ram_ded_count_mask 0x00c00000l +#define rlc_edc_cnt2__rlc_spm_se6_scratch_ram_sec_count_mask 0x03000000l +#define rlc_edc_cnt2__rlc_spm_se6_scratch_ram_ded_count_mask 0x0c000000l +#define rlc_edc_cnt2__rlc_spm_se7_scratch_ram_sec_count_mask 0x30000000l +#define rlc_edc_cnt2__rlc_spm_se7_scratch_ram_ded_count_mask 0xc0000000l + +#endif
|
Graphics
|
19cf0dd4b9d2771015fc9d74ec1b0b9203cf8c5a
|
dennis li
|
drivers
|
gpu
|
amd, asic_reg, drm, gc, include
|
drm/amdgpu: add ras support for the gfx block of arcturus
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implement functions to do the ras error injection and query edc counter.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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enable ras feature for the gc of arcturus
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['amdgpu ']
|
['c', 'makefile', 'h']
| 4
| 1,039
| 1
|
--- diff --git a/drivers/gpu/drm/amd/amdgpu/makefile b/drivers/gpu/drm/amd/amdgpu/makefile --- a/drivers/gpu/drm/amd/amdgpu/makefile +++ b/drivers/gpu/drm/amd/amdgpu/makefile + gfx_v9_4.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +#include "gfx_v9_4.h" + +static const struct amdgpu_gfx_funcs gfx_v9_4_gfx_funcs = { + .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter, + .select_se_sh = &gfx_v9_0_select_se_sh, + .read_wave_data = &gfx_v9_0_read_wave_data, + .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs, + .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs, + .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q, + .ras_error_inject = &gfx_v9_4_ras_error_inject, + .query_ras_error_count = &gfx_v9_4_query_ras_error_count +}; + + adev->gfx.funcs = &gfx_v9_4_gfx_funcs; - gfx_v9_0_clear_ras_edc_counter(adev); + switch (adev->asic_type) + { + case chip_vega20: + gfx_v9_0_clear_ras_edc_counter(adev); + break; + case chip_arcturus: + gfx_v9_4_clear_ras_edc_counter(adev); + break; + default: + break; + } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c +/* + * copyright 2020 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + */ + +#include <linux/kernel.h> + +#include "amdgpu.h" +#include "amdgpu_gfx.h" +#include "soc15.h" +#include "soc15d.h" +#include "amdgpu_atomfirmware.h" +#include "amdgpu_pm.h" + +#include "gc/gc_9_4_1_offset.h" +#include "gc/gc_9_4_1_sh_mask.h" +#include "soc15_common.h" + +#include "gfx_v9_4.h" +#include "amdgpu_ras.h" + +static const struct soc15_reg_entry gfx_v9_4_edc_counter_regs[] = { + /* cpc */ + { soc15_reg_entry(gc, 0, mmcpc_edc_scratch_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmcpc_edc_ucode_cnt), 0, 1, 1 }, + /* dc */ + { soc15_reg_entry(gc, 0, mmdc_edc_state_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmdc_edc_csinvoc_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmdc_edc_restore_cnt), 0, 1, 1 }, + /* cpf */ + { soc15_reg_entry(gc, 0, mmcpf_edc_roq_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmcpf_edc_tag_cnt), 0, 1, 1 }, + /* gds */ + { soc15_reg_entry(gc, 0, mmgds_edc_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmgds_edc_grbm_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmgds_edc_oa_ded), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmgds_edc_oa_phy_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmgds_edc_oa_pipe_cnt), 0, 1, 1 }, + /* spi */ + { soc15_reg_entry(gc, 0, mmspi_edc_cnt), 0, 4, 1 }, + /* sq */ + { soc15_reg_entry(gc, 0, mmsq_edc_cnt), 0, 4, 16 }, + { soc15_reg_entry(gc, 0, mmsq_edc_ded_cnt), 0, 4, 16 }, + { soc15_reg_entry(gc, 0, mmsq_edc_info), 0, 4, 16 }, + { soc15_reg_entry(gc, 0, mmsq_edc_sec_cnt), 0, 4, 16 }, + /* sqc */ + { soc15_reg_entry(gc, 0, mmsqc_edc_cnt), 0, 4, 6 }, + { soc15_reg_entry(gc, 0, mmsqc_edc_cnt2), 0, 4, 6 }, + { soc15_reg_entry(gc, 0, mmsqc_edc_cnt3), 0, 4, 6 }, + { soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), 0, 4, 6 }, + /* ta */ + { soc15_reg_entry(gc, 0, mmta_edc_cnt), 0, 4, 16 }, + /* tca */ + { soc15_reg_entry(gc, 0, mmtca_edc_cnt), 0, 1, 2 }, + /* tcc */ + { soc15_reg_entry(gc, 0, mmtcc_edc_cnt), 0, 1, 16 }, + { soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), 0, 1, 16 }, + /* tci */ + { soc15_reg_entry(gc, 0, mmtci_edc_cnt), 0, 1, 72 }, + /* tcp */ + { soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), 0, 4, 16 }, + { soc15_reg_entry(gc, 0, mmtcp_atc_edc_gatcl1_cnt), 0, 4, 16 }, + { soc15_reg_entry(gc, 0, mmtcp_edc_cnt), 0, 4, 16 }, + /* td */ + { soc15_reg_entry(gc, 0, mmtd_edc_cnt), 0, 4, 16 }, + /* gcea */ + { soc15_reg_entry(gc, 0, mmgcea_edc_cnt), 0, 1, 32 }, + { soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), 0, 1, 32 }, + { soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 1, 32 }, + /* rlc */ + { soc15_reg_entry(gc, 0, mmrlc_edc_cnt), 0, 1, 1 }, + { soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), 0, 1, 1 }, +}; + +static void gfx_v9_4_select_se_sh(struct amdgpu_device *adev, u32 se_num, + u32 sh_num, u32 instance) +{ + u32 data; + + if (instance == 0xffffffff) + data = reg_set_field(0, grbm_gfx_index, + instance_broadcast_writes, 1); + else + data = reg_set_field(0, grbm_gfx_index, instance_index, + instance); + + if (se_num == 0xffffffff) + data = reg_set_field(data, grbm_gfx_index, se_broadcast_writes, + 1); + else + data = reg_set_field(data, grbm_gfx_index, se_index, se_num); + + if (sh_num == 0xffffffff) + data = reg_set_field(data, grbm_gfx_index, sh_broadcast_writes, + 1); + else + data = reg_set_field(data, grbm_gfx_index, sh_index, sh_num); + + wreg32_soc15_rlc_shadow(gc, 0, mmgrbm_gfx_index, data); +} + +static const struct soc15_ras_field_entry gfx_v9_4_ras_fields[] = { + /* cpc */ + { "cpc_scratch", soc15_reg_entry(gc, 0, mmcpc_edc_scratch_cnt), + soc15_reg_field(cpc_edc_scratch_cnt, sec_count), + soc15_reg_field(cpc_edc_scratch_cnt, ded_count) }, + { "cpc_ucode", soc15_reg_entry(gc, 0, mmcpc_edc_ucode_cnt), + soc15_reg_field(cpc_edc_ucode_cnt, sec_count), + soc15_reg_field(cpc_edc_ucode_cnt, ded_count) }, + { "cpc_dc_state_ram_me1", soc15_reg_entry(gc, 0, mmdc_edc_state_cnt), + soc15_reg_field(dc_edc_state_cnt, sec_count_me1), + soc15_reg_field(dc_edc_state_cnt, ded_count_me1) }, + { "cpc_dc_csinvoc_ram_me1", + soc15_reg_entry(gc, 0, mmdc_edc_csinvoc_cnt), + soc15_reg_field(dc_edc_csinvoc_cnt, sec_count_me1), + soc15_reg_field(dc_edc_csinvoc_cnt, ded_count_me1) }, + { "cpc_dc_restore_ram_me1", + soc15_reg_entry(gc, 0, mmdc_edc_restore_cnt), + soc15_reg_field(dc_edc_restore_cnt, sec_count_me1), + soc15_reg_field(dc_edc_restore_cnt, ded_count_me1) }, + { "cpc_dc_csinvoc_ram1_me1", + soc15_reg_entry(gc, 0, mmdc_edc_csinvoc_cnt), + soc15_reg_field(dc_edc_csinvoc_cnt, sec_count1_me1), + soc15_reg_field(dc_edc_csinvoc_cnt, ded_count1_me1) }, + { "cpc_dc_restore_ram1_me1", + soc15_reg_entry(gc, 0, mmdc_edc_restore_cnt), + soc15_reg_field(dc_edc_restore_cnt, sec_count1_me1), + soc15_reg_field(dc_edc_restore_cnt, ded_count1_me1) }, + + /* cpf */ + { "cpf_roq_me2", soc15_reg_entry(gc, 0, mmcpf_edc_roq_cnt), + soc15_reg_field(cpf_edc_roq_cnt, sec_count_me2), + soc15_reg_field(cpf_edc_roq_cnt, ded_count_me2) }, + { "cpf_roq_me1", soc15_reg_entry(gc, 0, mmcpf_edc_roq_cnt), + soc15_reg_field(cpf_edc_roq_cnt, sec_count_me1), + soc15_reg_field(cpf_edc_roq_cnt, ded_count_me1) }, + { "cpf_tciu_tag", soc15_reg_entry(gc, 0, mmcpf_edc_tag_cnt), + soc15_reg_field(cpf_edc_tag_cnt, sec_count), + soc15_reg_field(cpf_edc_tag_cnt, ded_count) }, + + /* gds */ + { "gds_grbm", soc15_reg_entry(gc, 0, mmgds_edc_grbm_cnt), + soc15_reg_field(gds_edc_grbm_cnt, sec), + soc15_reg_field(gds_edc_grbm_cnt, ded) }, + { "gds_mem", soc15_reg_entry(gc, 0, mmgds_edc_cnt), + soc15_reg_field(gds_edc_cnt, gds_mem_sec), + soc15_reg_field(gds_edc_cnt, gds_mem_ded) }, + { "gds_phy_cmd_ram_mem", soc15_reg_entry(gc, 0, mmgds_edc_oa_phy_cnt), + soc15_reg_field(gds_edc_oa_phy_cnt, phy_cmd_ram_mem_sec), + soc15_reg_field(gds_edc_oa_phy_cnt, phy_cmd_ram_mem_ded) }, + { "gds_phy_data_ram_mem", soc15_reg_entry(gc, 0, mmgds_edc_oa_phy_cnt), + soc15_reg_field(gds_edc_oa_phy_cnt, phy_data_ram_mem_sec), + soc15_reg_field(gds_edc_oa_phy_cnt, phy_data_ram_mem_ded) }, + { "gds_me0_cs_pipe_mem", soc15_reg_entry(gc, 0, mmgds_edc_oa_phy_cnt), + soc15_reg_field(gds_edc_oa_phy_cnt, me0_cs_pipe_mem_sec), + soc15_reg_field(gds_edc_oa_phy_cnt, me0_cs_pipe_mem_ded) }, + { "gds_me1_pipe0_pipe_mem", + soc15_reg_entry(gc, 0, mmgds_edc_oa_pipe_cnt), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe0_pipe_mem_sec), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe0_pipe_mem_ded) }, + { "gds_me1_pipe1_pipe_mem", + soc15_reg_entry(gc, 0, mmgds_edc_oa_pipe_cnt), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe1_pipe_mem_sec), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe1_pipe_mem_ded) }, + { "gds_me1_pipe2_pipe_mem", + soc15_reg_entry(gc, 0, mmgds_edc_oa_pipe_cnt), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe2_pipe_mem_sec), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe2_pipe_mem_ded) }, + { "gds_me1_pipe3_pipe_mem", + soc15_reg_entry(gc, 0, mmgds_edc_oa_pipe_cnt), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe3_pipe_mem_sec), + soc15_reg_field(gds_edc_oa_pipe_cnt, me1_pipe3_pipe_mem_ded) }, + + /* spi */ + { "spi_sr_mem", soc15_reg_entry(gc, 0, mmspi_edc_cnt), + soc15_reg_field(spi_edc_cnt, spi_sr_mem_sec_count), + soc15_reg_field(spi_edc_cnt, spi_sr_mem_ded_count) }, + { "spi_gds_expreq", soc15_reg_entry(gc, 0, mmspi_edc_cnt), + soc15_reg_field(spi_edc_cnt, spi_gds_expreq_sec_count), + soc15_reg_field(spi_edc_cnt, spi_gds_expreq_ded_count) }, + { "spi_wb_grant_30", soc15_reg_entry(gc, 0, mmspi_edc_cnt), + soc15_reg_field(spi_edc_cnt, spi_wb_grant_30_sec_count), + soc15_reg_field(spi_edc_cnt, spi_wb_grant_30_ded_count) }, + { "spi_wb_grant_61", soc15_reg_entry(gc, 0, mmspi_edc_cnt), + soc15_reg_field(spi_edc_cnt, spi_wb_grant_61_sec_count), + soc15_reg_field(spi_edc_cnt, spi_wb_grant_61_ded_count) }, + { "spi_life_cnt", soc15_reg_entry(gc, 0, mmspi_edc_cnt), + soc15_reg_field(spi_edc_cnt, spi_life_cnt_sec_count), + soc15_reg_field(spi_edc_cnt, spi_life_cnt_ded_count) }, + + /* sq */ + { "sq_sgpr", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, sgpr_sec_count), + soc15_reg_field(sq_edc_cnt, sgpr_ded_count) }, + { "sq_lds_d", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, lds_d_sec_count), + soc15_reg_field(sq_edc_cnt, lds_d_ded_count) }, + { "sq_lds_i", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, lds_i_sec_count), + soc15_reg_field(sq_edc_cnt, lds_i_ded_count) }, + { "sq_vgpr0", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, vgpr0_sec_count), + soc15_reg_field(sq_edc_cnt, vgpr0_ded_count) }, + { "sq_vgpr1", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, vgpr1_sec_count), + soc15_reg_field(sq_edc_cnt, vgpr1_ded_count) }, + { "sq_vgpr2", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, vgpr2_sec_count), + soc15_reg_field(sq_edc_cnt, vgpr2_ded_count) }, + { "sq_vgpr3", soc15_reg_entry(gc, 0, mmsq_edc_cnt), + soc15_reg_field(sq_edc_cnt, vgpr3_sec_count), + soc15_reg_field(sq_edc_cnt, vgpr3_ded_count) }, + + /* sqc */ + { "sqc_inst_utcl1_lfifo", soc15_reg_entry(gc, 0, mmsqc_edc_cnt2), + soc15_reg_field(sqc_edc_cnt2, inst_utcl1_lfifo_sec_count), + soc15_reg_field(sqc_edc_cnt2, inst_utcl1_lfifo_ded_count) }, + { "sqc_data_cu0_write_data_buf", soc15_reg_entry(gc, 0, mmsqc_edc_cnt), + soc15_reg_field(sqc_edc_cnt, data_cu0_write_data_buf_sec_count), + soc15_reg_field(sqc_edc_cnt, data_cu0_write_data_buf_ded_count) }, + { "sqc_data_cu0_utcl1_lfifo", soc15_reg_entry(gc, 0, mmsqc_edc_cnt), + soc15_reg_field(sqc_edc_cnt, data_cu0_utcl1_lfifo_sec_count), + soc15_reg_field(sqc_edc_cnt, data_cu0_utcl1_lfifo_ded_count) }, + { "sqc_data_cu1_write_data_buf", soc15_reg_entry(gc, 0, mmsqc_edc_cnt), + soc15_reg_field(sqc_edc_cnt, data_cu1_write_data_buf_sec_count), + soc15_reg_field(sqc_edc_cnt, data_cu1_write_data_buf_ded_count) }, + { "sqc_data_cu1_utcl1_lfifo", soc15_reg_entry(gc, 0, mmsqc_edc_cnt), + soc15_reg_field(sqc_edc_cnt, data_cu1_utcl1_lfifo_sec_count), + soc15_reg_field(sqc_edc_cnt, data_cu1_utcl1_lfifo_ded_count) }, + { "sqc_data_cu2_write_data_buf", soc15_reg_entry(gc, 0, mmsqc_edc_cnt), + soc15_reg_field(sqc_edc_cnt, data_cu2_write_data_buf_sec_count), + soc15_reg_field(sqc_edc_cnt, data_cu2_write_data_buf_ded_count) }, + { "sqc_data_cu2_utcl1_lfifo", soc15_reg_entry(gc, 0, mmsqc_edc_cnt), + soc15_reg_field(sqc_edc_cnt, data_cu2_utcl1_lfifo_sec_count), + soc15_reg_field(sqc_edc_cnt, data_cu2_utcl1_lfifo_ded_count) }, + { "sqc_inst_banka_tag_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt2), + soc15_reg_field(sqc_edc_cnt2, inst_banka_tag_ram_sec_count), + soc15_reg_field(sqc_edc_cnt2, inst_banka_tag_ram_ded_count) }, + { "sqc_inst_banka_utcl1_miss_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, + inst_banka_utcl1_miss_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, + inst_banka_utcl1_miss_fifo_ded_count) }, + { "sqc_inst_banka_miss_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, inst_banka_miss_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, + inst_banka_miss_fifo_ded_count) }, + { "sqc_inst_banka_bank_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt2), + soc15_reg_field(sqc_edc_cnt2, inst_banka_bank_ram_sec_count), + soc15_reg_field(sqc_edc_cnt2, inst_banka_bank_ram_ded_count) }, + { "sqc_data_banka_tag_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt2), + soc15_reg_field(sqc_edc_cnt2, data_banka_tag_ram_sec_count), + soc15_reg_field(sqc_edc_cnt2, data_banka_tag_ram_ded_count) }, + { "sqc_data_banka_hit_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, data_banka_hit_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, data_banka_hit_fifo_ded_count) }, + { "sqc_data_banka_miss_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, data_banka_miss_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, + data_banka_miss_fifo_ded_count) }, + { "sqc_data_banka_bank_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt2), + soc15_reg_field(sqc_edc_cnt2, data_banka_bank_ram_sec_count), + soc15_reg_field(sqc_edc_cnt2, data_banka_bank_ram_ded_count) }, + { "sqc_inst_bankb_tag_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt3), + soc15_reg_field(sqc_edc_cnt3, inst_bankb_tag_ram_sec_count), + soc15_reg_field(sqc_edc_cnt3, inst_bankb_tag_ram_ded_count) }, + { "sqc_inst_bankb_utcl1_miss_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, + inst_bankb_utcl1_miss_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, + inst_bankb_utcl1_miss_fifo_ded_count) }, + { "sqc_inst_bankb_miss_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, inst_bankb_miss_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, + inst_bankb_miss_fifo_ded_count) }, + { "sqc_inst_bankb_bank_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt3), + soc15_reg_field(sqc_edc_cnt3, inst_bankb_bank_ram_sec_count), + soc15_reg_field(sqc_edc_cnt3, inst_bankb_bank_ram_ded_count) }, + { "sqc_data_bankb_tag_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt3), + soc15_reg_field(sqc_edc_cnt3, data_bankb_tag_ram_sec_count), + soc15_reg_field(sqc_edc_cnt3, data_bankb_tag_ram_ded_count) }, + { "sqc_data_bankb_hit_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, data_bankb_hit_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, data_bankb_hit_fifo_ded_count) }, + { "sqc_data_bankb_miss_fifo", + soc15_reg_entry(gc, 0, mmsqc_edc_parity_cnt3), + soc15_reg_field(sqc_edc_parity_cnt3, data_bankb_miss_fifo_sec_count), + soc15_reg_field(sqc_edc_parity_cnt3, + data_bankb_miss_fifo_ded_count) }, + { "sqc_data_bankb_bank_ram", soc15_reg_entry(gc, 0, mmsqc_edc_cnt3), + soc15_reg_field(sqc_edc_cnt3, data_bankb_bank_ram_sec_count), + soc15_reg_field(sqc_edc_cnt3, data_bankb_bank_ram_ded_count) }, + + /* ta */ + { "ta_fs_dfifo", soc15_reg_entry(gc, 0, mmta_edc_cnt), + soc15_reg_field(ta_edc_cnt, ta_fs_dfifo_sec_count), + soc15_reg_field(ta_edc_cnt, ta_fs_dfifo_ded_count) }, + { "ta_fs_afifo", soc15_reg_entry(gc, 0, mmta_edc_cnt), + soc15_reg_field(ta_edc_cnt, ta_fs_afifo_sec_count), + soc15_reg_field(ta_edc_cnt, ta_fs_afifo_ded_count) }, + { "ta_fl_lfifo", soc15_reg_entry(gc, 0, mmta_edc_cnt), + soc15_reg_field(ta_edc_cnt, ta_fl_lfifo_sec_count), + soc15_reg_field(ta_edc_cnt, ta_fl_lfifo_ded_count) }, + { "ta_fx_lfifo", soc15_reg_entry(gc, 0, mmta_edc_cnt), + soc15_reg_field(ta_edc_cnt, ta_fx_lfifo_sec_count), + soc15_reg_field(ta_edc_cnt, ta_fx_lfifo_ded_count) }, + { "ta_fs_cfifo", soc15_reg_entry(gc, 0, mmta_edc_cnt), + soc15_reg_field(ta_edc_cnt, ta_fs_cfifo_sec_count), + soc15_reg_field(ta_edc_cnt, ta_fs_cfifo_ded_count) }, + + /* tca */ + { "tca_hole_fifo", soc15_reg_entry(gc, 0, mmtca_edc_cnt), + soc15_reg_field(tca_edc_cnt, hole_fifo_sec_count), + soc15_reg_field(tca_edc_cnt, hole_fifo_ded_count) }, + { "tca_req_fifo", soc15_reg_entry(gc, 0, mmtca_edc_cnt), + soc15_reg_field(tca_edc_cnt, req_fifo_sec_count), + soc15_reg_field(tca_edc_cnt, req_fifo_ded_count) }, + + /* tcc */ + { "tcc_cache_data", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, cache_data_sec_count), + soc15_reg_field(tcc_edc_cnt, cache_data_ded_count) }, + { "tcc_cache_dirty", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, cache_dirty_sec_count), + soc15_reg_field(tcc_edc_cnt, cache_dirty_ded_count) }, + { "tcc_high_rate_tag", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, high_rate_tag_sec_count), + soc15_reg_field(tcc_edc_cnt, high_rate_tag_ded_count) }, + { "tcc_low_rate_tag", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, low_rate_tag_sec_count), + soc15_reg_field(tcc_edc_cnt, low_rate_tag_ded_count) }, + { "tcc_in_use_dec", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, in_use_dec_sec_count), + soc15_reg_field(tcc_edc_cnt2, in_use_dec_ded_count) }, + { "tcc_in_use_transfer", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, in_use_transfer_sec_count), + soc15_reg_field(tcc_edc_cnt2, in_use_transfer_ded_count) }, + { "tcc_return_data", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, return_data_sec_count), + soc15_reg_field(tcc_edc_cnt2, return_data_ded_count) }, + { "tcc_return_control", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, return_control_sec_count), + soc15_reg_field(tcc_edc_cnt2, return_control_ded_count) }, + { "tcc_uc_atomic_fifo", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, uc_atomic_fifo_sec_count), + soc15_reg_field(tcc_edc_cnt2, uc_atomic_fifo_ded_count) }, + { "tcc_write_return", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, write_return_sec_count), + soc15_reg_field(tcc_edc_cnt2, write_return_ded_count) }, + { "tcc_write_cache_read", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, write_cache_read_sec_count), + soc15_reg_field(tcc_edc_cnt2, write_cache_read_ded_count) }, + { "tcc_src_fifo", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, src_fifo_sec_count), + soc15_reg_field(tcc_edc_cnt, src_fifo_ded_count) }, + { "tcc_cache_tag_probe_fifo", soc15_reg_entry(gc, 0, mmtcc_edc_cnt2), + soc15_reg_field(tcc_edc_cnt2, cache_tag_probe_fifo_sec_count), + soc15_reg_field(tcc_edc_cnt2, cache_tag_probe_fifo_ded_count) }, + { "tcc_latency_fifo", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, latency_fifo_sec_count), + soc15_reg_field(tcc_edc_cnt, latency_fifo_ded_count) }, + { "tcc_latency_fifo_next_ram", soc15_reg_entry(gc, 0, mmtcc_edc_cnt), + soc15_reg_field(tcc_edc_cnt, latency_fifo_next_ram_sec_count), + soc15_reg_field(tcc_edc_cnt, latency_fifo_next_ram_ded_count) }, + + /* tci */ + { "tci_write_ram", soc15_reg_entry(gc, 0, mmtci_edc_cnt), + soc15_reg_field(tci_edc_cnt, write_ram_sec_count), + soc15_reg_field(tci_edc_cnt, write_ram_ded_count) }, + + /* tcp */ + { "tcp_cache_ram", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, cache_ram_sec_count), + soc15_reg_field(tcp_edc_cnt_new, cache_ram_ded_count) }, + { "tcp_lfifo_ram", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, lfifo_ram_sec_count), + soc15_reg_field(tcp_edc_cnt_new, lfifo_ram_ded_count) }, + { "tcp_cmd_fifo", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, cmd_fifo_sec_count), + soc15_reg_field(tcp_edc_cnt_new, cmd_fifo_ded_count) }, + { "tcp_vm_fifo", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, vm_fifo_sec_count), + soc15_reg_field(tcp_edc_cnt_new, vm_fifo_ded_count) }, + { "tcp_db_ram", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, db_ram_sed_count), 0, 0 }, + { "tcp_utcl1_lfifo0", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, utcl1_lfifo0_sec_count), + soc15_reg_field(tcp_edc_cnt_new, utcl1_lfifo0_ded_count) }, + { "tcp_utcl1_lfifo1", soc15_reg_entry(gc, 0, mmtcp_edc_cnt_new), + soc15_reg_field(tcp_edc_cnt_new, utcl1_lfifo1_sec_count), + soc15_reg_field(tcp_edc_cnt_new, utcl1_lfifo1_ded_count) }, + + /* td */ + { "td_ss_fifo_lo", soc15_reg_entry(gc, 0, mmtd_edc_cnt), + soc15_reg_field(td_edc_cnt, ss_fifo_lo_sec_count), + soc15_reg_field(td_edc_cnt, ss_fifo_lo_ded_count) }, + { "td_ss_fifo_hi", soc15_reg_entry(gc, 0, mmtd_edc_cnt), + soc15_reg_field(td_edc_cnt, ss_fifo_hi_sec_count), + soc15_reg_field(td_edc_cnt, ss_fifo_hi_ded_count) }, + { "td_cs_fifo", soc15_reg_entry(gc, 0, mmtd_edc_cnt), + soc15_reg_field(td_edc_cnt, cs_fifo_sec_count), + soc15_reg_field(td_edc_cnt, cs_fifo_ded_count) }, + + /* ea */ + { "ea_dramrd_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, dramrd_cmdmem_sec_count), + soc15_reg_field(gcea_edc_cnt, dramrd_cmdmem_ded_count) }, + { "ea_dramwr_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, dramwr_cmdmem_sec_count), + soc15_reg_field(gcea_edc_cnt, dramwr_cmdmem_ded_count) }, + { "ea_dramwr_datamem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, dramwr_datamem_sec_count), + soc15_reg_field(gcea_edc_cnt, dramwr_datamem_ded_count) }, + { "ea_rret_tagmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, rret_tagmem_sec_count), + soc15_reg_field(gcea_edc_cnt, rret_tagmem_ded_count) }, + { "ea_wret_tagmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, wret_tagmem_sec_count), + soc15_reg_field(gcea_edc_cnt, wret_tagmem_ded_count) }, + { "ea_gmird_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, gmird_cmdmem_sec_count), + soc15_reg_field(gcea_edc_cnt2, gmird_cmdmem_ded_count) }, + { "ea_gmiwr_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, gmiwr_cmdmem_sec_count), + soc15_reg_field(gcea_edc_cnt2, gmiwr_cmdmem_ded_count) }, + { "ea_gmiwr_datamem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, gmiwr_datamem_sec_count), + soc15_reg_field(gcea_edc_cnt2, gmiwr_datamem_ded_count) }, + { "ea_dramrd_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, dramrd_pagemem_sed_count), 0, 0 }, + { "ea_dramrd_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, dramrd_pagemem_ded_count) }, + { "ea_dramwr_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, dramwr_pagemem_sed_count), 0, 0 }, + { "ea_dramwr_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, dramwr_pagemem_ded_count) }, + { "ea_iord_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, iord_cmdmem_sed_count), 0, 0 }, + { "ea_iord_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, iord_cmdmem_ded_count) }, + { "ea_iowr_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, iowr_cmdmem_sed_count), 0, 0 }, + { "ea_iowr_cmdmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, iowr_cmdmem_ded_count) }, + { "ea_iowr_datamem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, iowr_datamem_sed_count), 0, 0 }, + { "ea_iowr_datamem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, iowr_datamem_ded_count) }, + { "ea_gmird_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, gmird_pagemem_sed_count), 0, 0 }, + { "ea_gmird_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, gmird_pagemem_ded_count) }, + { "ea_gmiwr_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, gmiwr_pagemem_sed_count), 0, 0 }, + { "ea_gmiwr_pagemem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, gmiwr_pagemem_ded_count) }, + { "ea_mam_d0mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, mam_d0mem_sed_count), + soc15_reg_field(gcea_edc_cnt2, mam_d0mem_ded_count) }, + { "ea_mam_d1mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, mam_d1mem_sed_count), + soc15_reg_field(gcea_edc_cnt2, mam_d1mem_ded_count) }, + { "ea_mam_d2mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, mam_d2mem_sed_count), + soc15_reg_field(gcea_edc_cnt2, mam_d2mem_ded_count) }, + { "ea_mam_d3mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt2), + soc15_reg_field(gcea_edc_cnt2, mam_d3mem_sed_count), + soc15_reg_field(gcea_edc_cnt2, mam_d3mem_ded_count) }, + { "ea_mam_a0mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), + soc15_reg_field(gcea_edc_cnt3, mam_a0mem_sec_count), + soc15_reg_field(gcea_edc_cnt3, mam_a0mem_ded_count) }, + { "ea_mam_a1mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), + soc15_reg_field(gcea_edc_cnt3, mam_a1mem_sec_count), + soc15_reg_field(gcea_edc_cnt3, mam_a1mem_ded_count) }, + { "ea_mam_a2mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), + soc15_reg_field(gcea_edc_cnt3, mam_a2mem_sec_count), + soc15_reg_field(gcea_edc_cnt3, mam_a2mem_ded_count) }, + { "ea_mam_a3mem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), + soc15_reg_field(gcea_edc_cnt3, mam_a3mem_sec_count), + soc15_reg_field(gcea_edc_cnt3, mam_a3mem_ded_count) }, + { "ea_mam_afmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt), + soc15_reg_field(gcea_edc_cnt, mam_afmem_sec_count), 0, 0 }, + { "ea_mam_afmem", soc15_reg_entry(gc, 0, mmgcea_edc_cnt3), 0, 0, + soc15_reg_field(gcea_edc_cnt3, mam_afmem_ded_count) }, + + /* rlc */ + { "rlcg_instr_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlcg_instr_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlcg_instr_ram_ded_count) }, + { "rlcg_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlcg_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlcg_scratch_ram_ded_count) }, + { "rlcv_instr_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlcv_instr_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlcv_instr_ram_ded_count) }, + { "rlcv_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlcv_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlcv_scratch_ram_ded_count) }, + { "rlc_tctag_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlc_tctag_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlc_tctag_ram_ded_count) }, + { "rlc_spm_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlc_spm_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlc_spm_scratch_ram_ded_count) }, + { "rlc_srm_data_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlc_srm_data_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlc_srm_data_ram_ded_count) }, + { "rlc_srm_addr_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt), + soc15_reg_field(rlc_edc_cnt, rlc_srm_addr_ram_sec_count), + soc15_reg_field(rlc_edc_cnt, rlc_srm_addr_ram_ded_count) }, + { "rlc_spm_se0_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se0_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se0_scratch_ram_ded_count) }, + { "rlc_spm_se1_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se1_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se1_scratch_ram_ded_count) }, + { "rlc_spm_se2_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se2_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se2_scratch_ram_ded_count) }, + { "rlc_spm_se3_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se3_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se3_scratch_ram_ded_count) }, + { "rlc_spm_se4_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se4_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se4_scratch_ram_ded_count) }, + { "rlc_spm_se5_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se5_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se5_scratch_ram_ded_count) }, + { "rlc_spm_se6_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se6_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se6_scratch_ram_ded_count) }, + { "rlc_spm_se7_scratch_ram", soc15_reg_entry(gc, 0, mmrlc_edc_cnt2), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se7_scratch_ram_sec_count), + soc15_reg_field(rlc_edc_cnt2, rlc_spm_se7_scratch_ram_ded_count) }, +}; + +static const char * const vml2_mems[] = { + "utc_vml2_bank_cache_0_bigk_mem0", + "utc_vml2_bank_cache_0_bigk_mem1", + "utc_vml2_bank_cache_0_4k_mem0", + "utc_vml2_bank_cache_0_4k_mem1", + "utc_vml2_bank_cache_1_bigk_mem0", + "utc_vml2_bank_cache_1_bigk_mem1", + "utc_vml2_bank_cache_1_4k_mem0", + "utc_vml2_bank_cache_1_4k_mem1", + "utc_vml2_bank_cache_2_bigk_mem0", + "utc_vml2_bank_cache_2_bigk_mem1", + "utc_vml2_bank_cache_2_4k_mem0", + "utc_vml2_bank_cache_2_4k_mem1", + "utc_vml2_bank_cache_3_bigk_mem0", + "utc_vml2_bank_cache_3_bigk_mem1", + "utc_vml2_bank_cache_3_4k_mem0", + "utc_vml2_bank_cache_3_4k_mem1", + "utc_vml2_ififo_group0", + "utc_vml2_ififo_group1", + "utc_vml2_ififo_group2", + "utc_vml2_ififo_group3", + "utc_vml2_ififo_group4", + "utc_vml2_ififo_group5", + "utc_vml2_ififo_group6", + "utc_vml2_ififo_group7", + "utc_vml2_ififo_group8", + "utc_vml2_ififo_group9", + "utc_vml2_ififo_group10", + "utc_vml2_ififo_group11", + "utc_vml2_ififo_group12", + "utc_vml2_ififo_group13", + "utc_vml2_ififo_group14", + "utc_vml2_ififo_group15", + "utc_vml2_ififo_group16", + "utc_vml2_ififo_group17", + "utc_vml2_ififo_group18", + "utc_vml2_ififo_group19", + "utc_vml2_ififo_group20", + "utc_vml2_ififo_group21", + "utc_vml2_ififo_group22", + "utc_vml2_ififo_group23", + "utc_vml2_ififo_group24", +}; + +static const char * const vml2_walker_mems[] = { + "utc_vml2_cache_pde0_mem0", + "utc_vml2_cache_pde0_mem1", + "utc_vml2_cache_pde1_mem0", + "utc_vml2_cache_pde1_mem1", + "utc_vml2_cache_pde2_mem0", + "utc_vml2_cache_pde2_mem1", + "utc_vml2_rdif_araddrs", + "utc_vml2_rdif_log_fifo", + "utc_vml2_queue_req", + "utc_vml2_queue_ret", +}; + +static const char * const utcl2_router_mems[] = { + "utcl2_router_group0_vml2_req_fifo0", + "utcl2_router_group1_vml2_req_fifo1", + "utcl2_router_group2_vml2_req_fifo2", + "utcl2_router_group3_vml2_req_fifo3", + "utcl2_router_group4_vml2_req_fifo4", + "utcl2_router_group5_vml2_req_fifo5", + "utcl2_router_group6_vml2_req_fifo6", + "utcl2_router_group7_vml2_req_fifo7", + "utcl2_router_group8_vml2_req_fifo8", + "utcl2_router_group9_vml2_req_fifo9", + "utcl2_router_group10_vml2_req_fifo10", + "utcl2_router_group11_vml2_req_fifo11", + "utcl2_router_group12_vml2_req_fifo12", + "utcl2_router_group13_vml2_req_fifo13", + "utcl2_router_group14_vml2_req_fifo14", + "utcl2_router_group15_vml2_req_fifo15", + "utcl2_router_group16_vml2_req_fifo16", + "utcl2_router_group17_vml2_req_fifo17", + "utcl2_router_group18_vml2_req_fifo18", + "utcl2_router_group19_vml2_req_fifo19", + "utcl2_router_group20_vml2_req_fifo20", + "utcl2_router_group21_vml2_req_fifo21", + "utcl2_router_group22_vml2_req_fifo22", + "utcl2_router_group23_vml2_req_fifo23", + "utcl2_router_group24_vml2_req_fifo24", +}; + +static const char * const atc_l2_cache_2m_mems[] = { + "utc_atcl2_cache_2m_bank0_way0_mem", + "utc_atcl2_cache_2m_bank0_way1_mem", + "utc_atcl2_cache_2m_bank1_way0_mem", + "utc_atcl2_cache_2m_bank1_way1_mem", +}; + +static const char * const atc_l2_cache_4k_mems[] = { + "utc_atcl2_cache_4k_bank0_way0_mem0", + "utc_atcl2_cache_4k_bank0_way0_mem1", + "utc_atcl2_cache_4k_bank0_way0_mem2", + "utc_atcl2_cache_4k_bank0_way0_mem3", + "utc_atcl2_cache_4k_bank0_way0_mem4", + "utc_atcl2_cache_4k_bank0_way0_mem5", + "utc_atcl2_cache_4k_bank0_way0_mem6", + "utc_atcl2_cache_4k_bank0_way0_mem7", + "utc_atcl2_cache_4k_bank0_way1_mem0", + "utc_atcl2_cache_4k_bank0_way1_mem1", + "utc_atcl2_cache_4k_bank0_way1_mem2", + "utc_atcl2_cache_4k_bank0_way1_mem3", + "utc_atcl2_cache_4k_bank0_way1_mem4", + "utc_atcl2_cache_4k_bank0_way1_mem5", + "utc_atcl2_cache_4k_bank0_way1_mem6", + "utc_atcl2_cache_4k_bank0_way1_mem7", + "utc_atcl2_cache_4k_bank1_way0_mem0", + "utc_atcl2_cache_4k_bank1_way0_mem1", + "utc_atcl2_cache_4k_bank1_way0_mem2", + "utc_atcl2_cache_4k_bank1_way0_mem3", + "utc_atcl2_cache_4k_bank1_way0_mem4", + "utc_atcl2_cache_4k_bank1_way0_mem5", + "utc_atcl2_cache_4k_bank1_way0_mem6", + "utc_atcl2_cache_4k_bank1_way0_mem7", + "utc_atcl2_cache_4k_bank1_way1_mem0", + "utc_atcl2_cache_4k_bank1_way1_mem1", + "utc_atcl2_cache_4k_bank1_way1_mem2", + "utc_atcl2_cache_4k_bank1_way1_mem3", + "utc_atcl2_cache_4k_bank1_way1_mem4", + "utc_atcl2_cache_4k_bank1_way1_mem5", + "utc_atcl2_cache_4k_bank1_way1_mem6", + "utc_atcl2_cache_4k_bank1_way1_mem7", +}; + +static int gfx_v9_4_query_utc_edc_status(struct amdgpu_device *adev, + struct ras_err_data *err_data) +{ + uint32_t i, data; + uint32_t sec_count, ded_count; + + wreg32_soc15(gc, 0, mmvml2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvml2_mem_ecc_cntl, 0); + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_cntl, 0); + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_cntl, 0); + + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_cntl, 0); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_cntl, 0); + + for (i = 0; i < array_size(vml2_mems); i++) { + wreg32_soc15(gc, 0, mmvml2_mem_ecc_index, i); + data = rreg32_soc15(gc, 0, mmvml2_mem_ecc_cntl); + + sec_count = reg_get_field(data, vml2_mem_ecc_cntl, sec_count); + if (sec_count) { + drm_info("instance[%d]: subblock %s, sec %d ", i, + vml2_mems[i], sec_count); + err_data->ce_count += sec_count; + } + + ded_count = reg_get_field(data, vml2_mem_ecc_cntl, ded_count); + if (ded_count) { + drm_info("instance[%d]: subblock %s, ded %d ", i, + vml2_mems[i], ded_count); + err_data->ue_count += ded_count; + } + } + + for (i = 0; i < array_size(vml2_walker_mems); i++) { + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_index, i); + data = rreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_cntl); + + sec_count = reg_get_field(data, vml2_walker_mem_ecc_cntl, + sec_count); + if (sec_count) { + drm_info("instance[%d]: subblock %s, sec %d ", i, + vml2_walker_mems[i], sec_count); + err_data->ce_count += sec_count; + } + + ded_count = reg_get_field(data, vml2_walker_mem_ecc_cntl, + ded_count); + if (ded_count) { + drm_info("instance[%d]: subblock %s, ded %d ", i, + vml2_walker_mems[i], ded_count); + err_data->ue_count += ded_count; + } + } + + for (i = 0; i < array_size(utcl2_router_mems); i++) { + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_index, i); + data = rreg32_soc15(gc, 0, mmutcl2_mem_ecc_cntl); + + sec_count = reg_get_field(data, utcl2_mem_ecc_cntl, sec_count); + if (sec_count) { + drm_info("instance[%d]: subblock %s, sec %d ", i, + utcl2_router_mems[i], sec_count); + err_data->ce_count += sec_count; + } + + ded_count = reg_get_field(data, utcl2_mem_ecc_cntl, ded_count); + if (ded_count) { + drm_info("instance[%d]: subblock %s, ded %d ", i, + utcl2_router_mems[i], ded_count); + err_data->ue_count += ded_count; + } + } + + for (i = 0; i < array_size(atc_l2_cache_2m_mems); i++) { + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_index, i); + data = rreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_cntl); + + sec_count = reg_get_field(data, atc_l2_cache_2m_dsm_cntl, + sec_count); + if (sec_count) { + drm_info("instance[%d]: subblock %s, sec %d ", i, + atc_l2_cache_2m_mems[i], sec_count); + err_data->ce_count += sec_count; + } + + ded_count = reg_get_field(data, atc_l2_cache_2m_dsm_cntl, + ded_count); + if (ded_count) { + drm_info("instance[%d]: subblock %s, ded %d ", i, + atc_l2_cache_2m_mems[i], ded_count); + err_data->ue_count += ded_count; + } + } + + for (i = 0; i < array_size(atc_l2_cache_4k_mems); i++) { + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_index, i); + data = rreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_cntl); + + sec_count = reg_get_field(data, atc_l2_cache_4k_dsm_cntl, + sec_count); + if (sec_count) { + drm_info("instance[%d]: subblock %s, sec %d ", i, + atc_l2_cache_4k_mems[i], sec_count); + err_data->ce_count += sec_count; + } + + ded_count = reg_get_field(data, atc_l2_cache_4k_dsm_cntl, + ded_count); + if (ded_count) { + drm_info("instance[%d]: subblock %s, ded %d ", i, + atc_l2_cache_4k_mems[i], ded_count); + err_data->ue_count += ded_count; + } + } + + wreg32_soc15(gc, 0, mmvml2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_index, 255); + + return 0; +} + +static int gfx_v9_4_ras_error_count(const struct soc15_reg_entry *reg, + uint32_t se_id, uint32_t inst_id, + uint32_t value, uint32_t *sec_count, + uint32_t *ded_count) +{ + uint32_t i; + uint32_t sec_cnt, ded_cnt; + + for (i = 0; i < array_size(gfx_v9_4_ras_fields); i++) { + if (gfx_v9_4_ras_fields[i].reg_offset != reg->reg_offset || + gfx_v9_4_ras_fields[i].seg != reg->seg || + gfx_v9_4_ras_fields[i].inst != reg->inst) + continue; + + sec_cnt = (value & gfx_v9_4_ras_fields[i].sec_count_mask) >> + gfx_v9_4_ras_fields[i].sec_count_shift; + if (sec_cnt) { + drm_info("gfx subblock %s, instance[%d][%d], sec %d ", + gfx_v9_4_ras_fields[i].name, se_id, inst_id, + sec_cnt); + *sec_count += sec_cnt; + } + + ded_cnt = (value & gfx_v9_4_ras_fields[i].ded_count_mask) >> + gfx_v9_4_ras_fields[i].ded_count_shift; + if (ded_cnt) { + drm_info("gfx subblock %s, instance[%d][%d], ded %d ", + gfx_v9_4_ras_fields[i].name, se_id, inst_id, + ded_cnt); + *ded_count += ded_cnt; + } + } + + return 0; +} + +int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status) +{ + struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status; + uint32_t sec_count = 0, ded_count = 0; + uint32_t i, j, k; + uint32_t reg_value; + + if (!amdgpu_ras_is_supported(adev, amdgpu_ras_block__gfx)) + return -einval; + + err_data->ue_count = 0; + err_data->ce_count = 0; + + mutex_lock(&adev->grbm_idx_mutex); + + for (i = 0; i < array_size(gfx_v9_4_edc_counter_regs); i++) { + for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { + for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance; + k++) { + gfx_v9_4_select_se_sh(adev, j, 0, k); + reg_value = rreg32(soc15_reg_entry_offset( + gfx_v9_4_edc_counter_regs[i])); + if (reg_value) + gfx_v9_4_ras_error_count( + &gfx_v9_4_edc_counter_regs[i], + j, k, reg_value, &sec_count, + &ded_count); + } + } + } + + err_data->ce_count += sec_count; + err_data->ue_count += ded_count; + + gfx_v9_4_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); + mutex_unlock(&adev->grbm_idx_mutex); + + gfx_v9_4_query_utc_edc_status(adev, err_data); + + return 0; +} + +void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev) +{ + int i, j, k; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < array_size(gfx_v9_4_edc_counter_regs); i++) { + for (j = 0; j < gfx_v9_4_edc_counter_regs[i].se_num; j++) { + for (k = 0; k < gfx_v9_4_edc_counter_regs[i].instance; + k++) { + gfx_v9_4_select_se_sh(adev, j, 0x0, k); + rreg32(soc15_reg_entry_offset( + gfx_v9_4_edc_counter_regs[i])); + } + } + } + wreg32_soc15(gc, 0, mmgrbm_gfx_index, 0xe0000000); + mutex_unlock(&adev->grbm_idx_mutex); + + wreg32_soc15(gc, 0, mmvml2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvml2_mem_ecc_cntl, 0); + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_cntl, 0); + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_cntl, 0); + + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_cntl, 0); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_cntl, 0); + + for (i = 0; i < array_size(vml2_mems); i++) { + wreg32_soc15(gc, 0, mmvml2_mem_ecc_index, i); + rreg32_soc15(gc, 0, mmvml2_mem_ecc_cntl); + } + + for (i = 0; i < array_size(vml2_walker_mems); i++) { + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_index, i); + rreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_cntl); + } + + for (i = 0; i < array_size(utcl2_router_mems); i++) { + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_index, i); + rreg32_soc15(gc, 0, mmutcl2_mem_ecc_cntl); + } + + for (i = 0; i < array_size(atc_l2_cache_2m_mems); i++) { + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_index, i); + rreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_cntl); + } + + for (i = 0; i < array_size(atc_l2_cache_4k_mems); i++) { + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_index, i); + rreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_cntl); + } + + wreg32_soc15(gc, 0, mmvml2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmvml2_walker_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmutcl2_mem_ecc_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_2m_dsm_index, 255); + wreg32_soc15(gc, 0, mmatc_l2_cache_4k_dsm_index, 255); +} + +int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev, void *inject_if) +{ + struct ras_inject_if *info = (struct ras_inject_if *)inject_if; + int ret; + struct ta_ras_trigger_error_input block_info = { 0 }; + + if (!amdgpu_ras_is_supported(adev, amdgpu_ras_block__gfx)) + return -einval; + + block_info.block_id = info->head.block; + block_info.sub_block_index = info->head.sub_block_index; + block_info.inject_error_type = amdgpu_ras_error_to_ta(info->head.type); + block_info.address = info->address; + block_info.value = info->value; + + mutex_lock(&adev->grbm_idx_mutex); + ret = psp_ras_trigger_error(&adev->psp, &block_info); + mutex_unlock(&adev->grbm_idx_mutex); + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.h +/* + * copyright 2020 advanced micro devices, inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + * + */ + +#ifndef __gfx_v9_4_h__ +#define __gfx_v9_4_h__ + +void gfx_v9_4_clear_ras_edc_counter(struct amdgpu_device *adev); + +int gfx_v9_4_query_ras_error_count(struct amdgpu_device *adev, + void *ras_error_status); + +int gfx_v9_4_ras_error_inject(struct amdgpu_device *adev, + void *inject_if); + +#endif /* __gfx_v9_4_h__ */
|
Graphics
|
4c461d89db4f8f40509b044b0daf3ac6edf4fbd7
|
dennis li guchun chen guchun chen amd com tao zhou tao zhou amd com hawking zhang hawking zhang amd com
|
drivers
|
gpu
|
amd, amdgpu, drm
|
drm/i915/bios: pass devdata to parse_ddi_port
|
allow accessing the parent structure later on. drop const for allowing future modification as well.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 4
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c - const struct child_device_config *child, + struct display_device_data *devdata, + const struct child_device_config *child = &devdata->child; - const struct display_device_data *devdata; + struct display_device_data *devdata; - parse_ddi_port(dev_priv, &devdata->child, bdb_version); + parse_ddi_port(dev_priv, devdata, bdb_version);
|
Graphics
|
d1dad6f43334f8ea93b76953cef0703f8bf9d42e
|
jani nikula vandita kulkarni vandita kulkarni intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/bios: parse compression parameters block
|
check for child devices that specify compression, and store the device specific compression parameters in the display device data struct for later use. warn if compression is requested but not available.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 2
| 60
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c + struct dsc_compression_parameters_entry *dsc; +static void +parse_compression_parameters(struct drm_i915_private *i915, + const struct bdb_header *bdb) +{ + const struct bdb_compression_parameters *params; + struct display_device_data *devdata; + const struct child_device_config *child; + u16 block_size; + int index; + + if (bdb->version < 198) + return; + + params = find_section(bdb, bdb_compression_parameters); + if (params) { + /* sanity checks */ + if (params->entry_size != sizeof(params->data[0])) { + drm_debug_kms("vbt: unsupported compression param entry size "); + return; + } + + block_size = get_blocksize(params); + if (block_size < sizeof(*params)) { + drm_debug_kms("vbt: expected 16 compression param entries "); + return; + } + } + + list_for_each_entry(devdata, &i915->vbt.display_devices, node) { + child = &devdata->child; + + if (!child->compression_enable) + continue; + + if (!params) { + drm_debug_kms("vbt: compression params not available "); + continue; + } + + if (child->compression_method_cps) { + drm_debug_kms("vbt: cps compression not supported "); + continue; + } + + index = child->compression_structure_index; + + devdata->dsc = kmemdup(¶ms->data[index], + sizeof(*devdata->dsc), gfp_kernel); + } +} + - drm_debug_kms("port %c vbt info: crt:%d dvi:%d hdmi:%d dp:%d edp:%d lspcon:%d usb-type-c:%d tbt:%d ", + drm_debug_kms("port %c vbt info: crt:%d dvi:%d hdmi:%d dp:%d edp:%d lspcon:%d usb-type-c:%d tbt:%d dsc:%d ", - info->supports_typec_usb, info->supports_tbt); + info->supports_typec_usb, info->supports_tbt, + devdata->dsc != null); + /* depends on child device list */ + parse_compression_parameters(dev_priv, bdb); + + kfree(devdata->dsc); diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h - u8 compression_method:1; /* 198 */ + u8 compression_method_cps:1; /* 198 */
|
Graphics
|
6e0d46e91efd4440e00a1c5380bf9a2f933529b8
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/bios: add support for querying dsc details for encoder
|
add function for retrieving the dsc data for an encoder.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 2
| 104
| 0
|
- use crtc_state instead of pipe_config - return true by default from intel_bios_get_dsc_params() - expand the comment about rc_buffer_block_size and rc_buffer_size - make more robust, debug log errors better --- diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c +#include "display/intel_display_types.h" +static void fill_dsc(struct intel_crtc_state *crtc_state, + struct dsc_compression_parameters_entry *dsc, + int dsc_max_bpc) +{ + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + int bpc = 8; + + vdsc_cfg->dsc_version_major = dsc->version_major; + vdsc_cfg->dsc_version_minor = dsc->version_minor; + + if (dsc->support_12bpc && dsc_max_bpc >= 12) + bpc = 12; + else if (dsc->support_10bpc && dsc_max_bpc >= 10) + bpc = 10; + else if (dsc->support_8bpc && dsc_max_bpc >= 8) + bpc = 8; + else + drm_debug_kms("vbt: unsupported bpc %d for dcs ", + dsc_max_bpc); + + crtc_state->pipe_bpp = bpc * 3; + + crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, + vbt_dsc_max_bpp(dsc->max_bpp)); + + /* + * fixme: this is ugly, and slice count should take dsc engine + * throughput etc. into account. + * + * also, per spec dsi supports 1, 2, 3 or 4 horizontal slices. + */ + if (dsc->slices_per_line & bit(2)) { + crtc_state->dsc.slice_count = 4; + } else if (dsc->slices_per_line & bit(1)) { + crtc_state->dsc.slice_count = 2; + } else { + /* fixme */ + if (!(dsc->slices_per_line & bit(0))) + drm_debug_kms("vbt: unsupported dsc slice count for dsi "); + + crtc_state->dsc.slice_count = 1; + } + + if (crtc_state->hw.adjusted_mode.crtc_hdisplay % + crtc_state->dsc.slice_count != 0) + drm_debug_kms("vbt: dsc hdisplay %d not divisible by slice count %d ", + crtc_state->hw.adjusted_mode.crtc_hdisplay, + crtc_state->dsc.slice_count); + + /* + * fixme: use vbt rc_buffer_block_size and rc_buffer_size for the + * implementation specific physical rate buffer size. currently we use + * the required rate buffer model size calculated in + * drm_dsc_compute_rc_parameters() according to vesa dsc annex e. + * + * the vbt rc_buffer_block_size and rc_buffer_size definitions + * correspond to dp 1.4 dpcd offsets 0x62 and 0x63. the dp dsc + * implementation should also use the dpcd (or perhaps vbt for edp) + * provided value for the buffer size. + */ + + /* fixme: dsi spec says bpc + 1 for this one */ + vdsc_cfg->line_buf_depth = vbt_dsc_line_buffer_depth(dsc->line_buffer_depth); + + vdsc_cfg->block_pred_enable = dsc->block_prediction_enable; + + vdsc_cfg->slice_height = dsc->slice_height; +} + +/* fixme: initially dsi specific */ +bool intel_bios_get_dsc_params(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + int dsc_max_bpc) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + const struct display_device_data *devdata; + const struct child_device_config *child; + + list_for_each_entry(devdata, &i915->vbt.display_devices, node) { + child = &devdata->child; + + if (!(child->device_type & device_type_mipi_output)) + continue; + + if (child->dvo_port - dvo_port_mipia == encoder->port) { + if (!devdata->dsc) + return false; + + if (crtc_state) + fill_dsc(crtc_state, devdata->dsc, dsc_max_bpc); + + return true; + } + } + + return false; +} + diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h --- a/drivers/gpu/drm/i915/display/intel_bios.h +++ b/drivers/gpu/drm/i915/display/intel_bios.h +struct intel_crtc_state; +struct intel_encoder; +bool intel_bios_get_dsc_params(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + int dsc_max_bpc);
|
Graphics
|
1bf2f3bf29a97037e695cc3e8695746fd8d2cde0
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsc: move dp specific compute params to intel_dp.c
|
turns out future dsi specific parameters aren't workable with the approach of having the encoder specific functions in intel_vdsc.c. make intel_dsc_compute_params() a helper that does the encoder independent parts, and have encoder code call it. move intel_dsc_dp_compute_params() to intel_dp.c as intel_dp_dsc_compute_params().
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 2
| 47
| 48
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c +#define dsc_supported_version_min 1 + +static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + u8 line_buf_depth; + int ret; + + ret = intel_dsc_compute_params(encoder, crtc_state); + if (ret) + return ret; + + vdsc_cfg->dsc_version_major = + (intel_dp->dsc_dpcd[dp_dsc_rev - dp_dsc_support] & + dp_dsc_major_mask) >> dp_dsc_major_shift; + vdsc_cfg->dsc_version_minor = + min(dsc_supported_version_min, + (intel_dp->dsc_dpcd[dp_dsc_rev - dp_dsc_support] & + dp_dsc_minor_mask) >> dp_dsc_minor_shift); + + vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[dp_dsc_dec_color_format_cap - dp_dsc_support] & + dp_dsc_rgb; + + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); + if (!line_buf_depth) { + drm_debug_kms("dsc sink line buffer depth invalid "); + return -einval; + } + + if (vdsc_cfg->dsc_version_minor == 2) + vdsc_cfg->line_buf_depth = (line_buf_depth == dsc_1_2_max_linebuf_depth_bits) ? + dsc_1_2_max_linebuf_depth_val : line_buf_depth; + else + vdsc_cfg->line_buf_depth = (line_buf_depth > dsc_1_1_max_linebuf_depth_bits) ? + dsc_1_1_max_linebuf_depth_bits : line_buf_depth; + + vdsc_cfg->block_pred_enable = + intel_dp->dsc_dpcd[dp_dsc_blk_prediction_support - dp_dsc_support] & + dp_dsc_blk_prediction_is_supported; + + return drm_dsc_compute_rc_parameters(vdsc_cfg); +} + - ret = intel_dsc_compute_params(&dig_port->base, pipe_config); + ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c -#define dsc_supported_version_min 1 - -/* values filled from dsc sink dpcd */ -static int intel_dsc_dp_compute_params(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) -{ - struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); - struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config; - u8 line_buf_depth; - - vdsc_cfg->dsc_version_major = - (intel_dp->dsc_dpcd[dp_dsc_rev - dp_dsc_support] & - dp_dsc_major_mask) >> dp_dsc_major_shift; - vdsc_cfg->dsc_version_minor = - min(dsc_supported_version_min, - (intel_dp->dsc_dpcd[dp_dsc_rev - dp_dsc_support] & - dp_dsc_minor_mask) >> dp_dsc_minor_shift); - - vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[dp_dsc_dec_color_format_cap - dp_dsc_support] & - dp_dsc_rgb; - - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); - if (!line_buf_depth) { - drm_debug_kms("dsc sink line buffer depth invalid "); - return -einval; - } - - if (vdsc_cfg->dsc_version_minor == 2) - vdsc_cfg->line_buf_depth = (line_buf_depth == dsc_1_2_max_linebuf_depth_bits) ? - dsc_1_2_max_linebuf_depth_val : line_buf_depth; - else - vdsc_cfg->line_buf_depth = (line_buf_depth > dsc_1_1_max_linebuf_depth_bits) ? - dsc_1_1_max_linebuf_depth_bits : line_buf_depth; - - vdsc_cfg->block_pred_enable = - intel_dp->dsc_dpcd[dp_dsc_blk_prediction_support - dp_dsc_support] & - dp_dsc_blk_prediction_is_supported; - - return 0; -} - - int ret; - ret = intel_dsc_dp_compute_params(encoder, pipe_config); - if (ret) - return ret; - - return drm_dsc_compute_rc_parameters(vdsc_cfg); + return 0;
|
Graphics
|
7a7b5be96fb66febb50ef001c0e5d20d55c0c34b
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsc: move slice height calculation to encoder
|
turns out this isn't compatible with dsi, where we use the value from vbt. no functional changes.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 2
| 12
| 11
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c + /* + * slice height of 8 works for all currently available panels. so start + * with that if pic_height is an integral multiple of 8. eventually add + * logic to try multiple slice heights. + */ + if (vdsc_cfg->pic_height % 8 == 0) + vdsc_cfg->slice_height = 8; + else if (vdsc_cfg->pic_height % 4 == 0) + vdsc_cfg->slice_height = 4; + else + vdsc_cfg->slice_height = 2; + diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c - /* - * slice height of 8 works for all currently available panels. so start - * with that if pic_height is an integral multiple of 8. - * eventually add logic to try multiple slice heights. - */ - if (vdsc_cfg->pic_height % 8 == 0) - vdsc_cfg->slice_height = 8; - else if (vdsc_cfg->pic_height % 4 == 0) - vdsc_cfg->slice_height = 4; - else - vdsc_cfg->slice_height = 2;
|
Graphics
|
c42c38ec307b6fb81c5cb213a8f082e03ffbe166
|
jani nikula vandita kulkarni vandita kulkarni intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsc: add support for computing and writing pps for dsi encoders
|
add dsi specific computation and transmission to display of pps.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 24
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c +#include "intel_dsi.h" +static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + struct mipi_dsi_device *dsi; + struct drm_dsc_picture_parameter_set pps; + enum port port; + + drm_dsc_pps_payload_pack(&pps, vdsc_cfg); + + for_each_dsi_port(port, intel_dsi->ports) { + dsi = intel_dsi->dsi_hosts[port]->device; + + mipi_dsi_picture_parameter_set(dsi, &pps); + mipi_dsi_compression_mode(dsi, true); + } +} + - intel_dsc_dp_pps_write(encoder, crtc_state); + if (encoder->type == intel_output_dsi) + intel_dsc_dsi_pps_write(encoder, crtc_state); + else + intel_dsc_dp_pps_write(encoder, crtc_state);
|
Graphics
|
2d15f3925a4b508b6ad10078bd324da1e95960a7
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsc: make dsc source support helper generic
|
move intel_dp_source_supports_dsc() from intel_dp.c as intel_dsc_source_support() in intel_vdsc.c. the dsc source support is more about dsc than about dp, and will be needed for dp independent code.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 3
| 28
| 22
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c -static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, - const struct intel_crtc_state *pipe_config) -{ - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - - if (!intel_info(dev_priv)->display.has_dsc) - return false; - - /* on tgl, dsc is supported on all pipes */ - if (intel_gen(dev_priv) >= 12) - return true; - - if (intel_gen(dev_priv) >= 10 && - pipe_config->cpu_transcoder != transcoder_a) - return true; - - return false; -} - - const struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *crtc_state) - if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; + + if (!intel_dp_is_edp(intel_dp) && !crtc_state->fec_enable) - return intel_dp_source_supports_dsc(intel_dp, pipe_config) && + return intel_dsc_source_support(encoder, crtc_state) && diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c +bool intel_dsc_source_support(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (!intel_info(i915)->display.has_dsc) + return false; + + /* on tgl, dsc is supported on all pipes */ + if (intel_gen(i915) >= 12) + return true; + + if (intel_gen(i915) >= 10 && + crtc_state->cpu_transcoder != transcoder_a) + return true; + + return false; +} + diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h +#include <linux/types.h> + +bool intel_dsc_source_support(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state);
|
Graphics
|
deaaff49198d04c197a95bceac95efc8534f6c04
|
jani nikula manasi navare manasi d navare intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsc: add basic hardware state readout support
|
add basic hardware state readout for dsc, and check the most relevant details in the state checker.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 4
| 57
| 0
|
- check for dsc power before reading its state - check if source supports dsc at all --- diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c + intel_dsc_get_config(encoder, pipe_config); + diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c + pipe_conf_check_i(dsc.compression_enable); + pipe_conf_check_i(dsc.dsc_split); + pipe_conf_check_i(dsc.compressed_bpp); + diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c +void intel_dsc_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum pipe pipe = crtc->pipe; + enum intel_display_power_domain power_domain; + intel_wakeref_t wakeref; + u32 dss_ctl1, dss_ctl2, val; + + if (!intel_dsc_source_support(encoder, crtc_state)) + return; + + power_domain = intel_dsc_power_domain(crtc_state); + + wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); + if (!wakeref) + return; + + if (crtc_state->cpu_transcoder == transcoder_edp) { + dss_ctl1 = i915_read(dss_ctl1); + dss_ctl2 = i915_read(dss_ctl2); + } else { + dss_ctl1 = i915_read(icl_pipe_dss_ctl1(pipe)); + dss_ctl2 = i915_read(icl_pipe_dss_ctl2(pipe)); + } + + crtc_state->dsc.compression_enable = dss_ctl2 & left_branch_vdsc_enable; + if (!crtc_state->dsc.compression_enable) + goto out; + + crtc_state->dsc.dsc_split = (dss_ctl2 & right_branch_vdsc_enable) && + (dss_ctl1 & joiner_enable); + + /* fixme: add more state readout as needed */ + + /* pps1 */ + if (cpu_transcoder == transcoder_edp) + val = i915_read(dsca_picture_parameter_set_1); + else + val = i915_read(icl_dsc0_picture_parameter_set_1(pipe)); + vdsc_cfg->bits_per_pixel = val; + crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4; +out: + intel_display_power_put(dev_priv, power_domain, wakeref); +} + diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h --- a/drivers/gpu/drm/i915/display/intel_vdsc.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h +void intel_dsc_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state);
|
Graphics
|
fbacb15ea814e7badb57ebc4015d6542290d0ff8
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: set pipe_bpp on icl configure config
|
the icl dsi pipe_bpp currently comes from compute_baseline_pipe_bpp(). fix it.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 5
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c + if (intel_dsi->pixel_format == mipi_dsi_fmt_rgb888) + pipe_config->pipe_bpp = 24; + else + pipe_config->pipe_bpp = 18; +
|
Graphics
|
50003bf50d32f3ff8ead40d6d68ee5e91a693e20
|
jani nikula vandita kulkarni vandita kulkarni intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: abstract afe_clk calculation
|
we'll make more use of it in the future.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 13
| 5
|
--- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c +/* aka dsi 8x clock */ +static int afe_clk(struct intel_encoder *encoder) +{ + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); + int bpp; + + bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); + + return div_round_closest(intel_dsi->pclk * bpp, intel_dsi->lane_count); +} + - u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); - u32 afe_clk_khz; /* 8x clock */ + int afe_clk_khz; - afe_clk_khz = div_round_closest(intel_dsi->pclk * bpp, - intel_dsi->lane_count); - + afe_clk_khz = afe_clk(encoder);
|
Graphics
|
54ed6902cabc58ae58643b7d06cafa4ed5540e6d
|
jani nikula vandita kulkarni vandita kulkarni intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
|
we'll be expanding afe_clk() to take dsc into account. switch to using it where dsc matters. which is really everywhere that intel_dsi_bitrate() is currently used in icl dsi code.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 4
| 4
|
--- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c - if (intel_dsi_bitrate(intel_dsi) <= 800000) { + if (afe_clk(encoder) <= 800000) { - if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) { + if (afe_clk(encoder) >= 1500 * 1000) { - divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000; + divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000; - pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5; + pipe_config->port_clock = afe_clk(encoder) / 5;
|
Graphics
|
adf1bd3dfbaedf7100b542b92fb085f89222a349
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: take compression into account in afe_clk()
|
pass crtc_state to afe_clk() to be able to take compression into account in the computation. once we enable compression, that is.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 24
| 16
|
--- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c -static int afe_clk(struct intel_encoder *encoder) +static int afe_clk(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) - bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); + if (crtc_state->dsc.compression_enable) + bpp = crtc_state->dsc.compressed_bpp; + else + bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); -static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder) +static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) - afe_clk_khz = afe_clk(encoder); + afe_clk_khz = afe_clk(encoder, crtc_state); -static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder) +static void +gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) - if (afe_clk(encoder) <= 800000) { + if (afe_clk(encoder, crtc_state) <= 800000) { - if (afe_clk(encoder) >= 1500 * 1000) { + if (afe_clk(encoder, pipe_config) >= 1500 * 1000) { -static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder) +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder, + const struct intel_crtc_state *crtc_state) - divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000; + divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000; - const struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *crtc_state) - gen11_dsi_setup_dphy_timings(encoder); + gen11_dsi_setup_dphy_timings(encoder, crtc_state); - gen11_dsi_setup_timeouts(encoder); + gen11_dsi_setup_timeouts(encoder, crtc_state); - gen11_dsi_configure_transcoder(encoder, pipe_config); + gen11_dsi_configure_transcoder(encoder, crtc_state); - const struct intel_crtc_state *pipe_config, + const struct intel_crtc_state *crtc_state, - gen11_dsi_program_esc_clk_div(encoder); + gen11_dsi_program_esc_clk_div(encoder, crtc_state); - pipe_config->port_clock = afe_clk(encoder) / 5; + pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
|
Graphics
|
0486513935ef95a3ce429323cac8148d58057913
|
jani nikula vandita kulkarni vandita kulkarni intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: use compressed pixel format with dsc
|
when compression is enabled, configure the dsi transcoder to use compressed format.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 20
| 16
|
--- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c - switch (intel_dsi->pixel_format) { - default: - missing_case(intel_dsi->pixel_format); - /* fallthrough */ - case mipi_dsi_fmt_rgb565: - tmp |= pix_fmt_rgb565; - break; - case mipi_dsi_fmt_rgb666_packed: - tmp |= pix_fmt_rgb666_packed; - break; - case mipi_dsi_fmt_rgb666: - tmp |= pix_fmt_rgb666_loose; - break; - case mipi_dsi_fmt_rgb888: - tmp |= pix_fmt_rgb888; - break; + if (pipe_config->dsc.compression_enable) { + tmp |= pix_fmt_compressed; + } else { + switch (intel_dsi->pixel_format) { + default: + missing_case(intel_dsi->pixel_format); + /* fallthrough */ + case mipi_dsi_fmt_rgb565: + tmp |= pix_fmt_rgb565; + break; + case mipi_dsi_fmt_rgb666_packed: + tmp |= pix_fmt_rgb666_packed; + break; + case mipi_dsi_fmt_rgb666: + tmp |= pix_fmt_rgb666_loose; + break; + case mipi_dsi_fmt_rgb888: + tmp |= pix_fmt_rgb888; + break; + }
|
Graphics
|
38b898810ae92b2e78b47f513fe66bdd5687ed54
|
jani nikula vandita kulkarni vandita kulkarni intel com vandita kulkarni vandita kulkarni intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: account for dsc in horizontal timings
|
when dsc is enabled, we need to adjust the horizontal timings to account for the compressed (and therefore reduced) link speed.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 19
| 5
|
--- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c - const struct intel_crtc_state *pipe_config) + const struct intel_crtc_state *crtc_state) - &pipe_config->hw.adjusted_mode; + &crtc_state->hw.adjusted_mode; + int mul = 1, div = 1; + + /* + * adjust horizontal timings (htotal, hsync_start, hsync_end) to account + * for slower link speed if dsc is enabled. + * + * the compression frequency ratio is the ratio between compressed and + * non-compressed link speeds, and simplifies down to the ratio between + * compressed and non-compressed bpp. + */ + if (crtc_state->dsc.compression_enable) { + mul = crtc_state->dsc.compressed_bpp; + div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); + } - htotal = adjusted_mode->crtc_htotal; - hsync_start = adjusted_mode->crtc_hsync_start; - hsync_end = adjusted_mode->crtc_hsync_end; + htotal = div_round_up(adjusted_mode->crtc_htotal * mul, div); + hsync_start = div_round_up(adjusted_mode->crtc_hsync_start * mul, div); + hsync_end = div_round_up(adjusted_mode->crtc_hsync_end * mul, div);
|
Graphics
|
53693f02d80e0a909e76c2a25f8aac8515f959db
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: fix state mismatch warns for horizontal timings with dsc
|
when dsc is enabled consider the compression ratio that was used during horizontal timing calculations.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 12
| 0
|
- rebase on top of the more generic dsc state readout --- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c + if (pipe_config->dsc.compressed_bpp) { + int div = pipe_config->dsc.compressed_bpp; + int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); + + adjusted_mode->crtc_htotal = + div_round_up(adjusted_mode->crtc_htotal * mul, div); + adjusted_mode->crtc_hsync_start = + div_round_up(adjusted_mode->crtc_hsync_start * mul, div); + adjusted_mode->crtc_hsync_end = + div_round_up(adjusted_mode->crtc_hsync_end * mul, div); + } +
|
Graphics
|
c2bb35e99f4b426efdd28011655bd67ca86749b5
|
vandita kulkarni
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/dsi: add support for dsc
|
enable dsc for dsi, if specified in vbt.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
enable dsc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 66
| 3
|
- add dsc get config call - convert_rgb = true (vandita) - ignore max cdclock check (vandita) - rename pipe_config to crtc_state - take compressed bpp into account - nuke conn_state->max_requested_bpc, it's not used on dsi --- diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c +#include "intel_vdsc.h" + intel_dsc_enable(encoder, pipe_config); + +static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + /* fixme: dsc? */ + return intel_dsi_mode_valid(connector, mode); +} + + intel_dsc_get_config(encoder, pipe_config); + +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; + int dsc_max_bpc = intel_gen(dev_priv) >= 12 ? 12 : 10; + bool use_dsc; + int ret; + + use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc); + if (!use_dsc) + return 0; + + if (crtc_state->pipe_bpp < 8 * 3) + return -einval; + + /* fixme: split only when necessary */ + if (crtc_state->dsc.slice_count > 1) + crtc_state->dsc.dsc_split = true; + + vdsc_cfg->convert_rgb = true; + + ret = intel_dsc_compute_params(encoder, crtc_state); + if (ret) + return ret; + + /* dsi specific sanity checks on the common code */ + warn_on(vdsc_cfg->vbr_enable); + warn_on(vdsc_cfg->simple_422); + warn_on(vdsc_cfg->pic_width % vdsc_cfg->slice_width); + warn_on(vdsc_cfg->slice_height < 8); + warn_on(vdsc_cfg->pic_height % vdsc_cfg->slice_height); + + ret = drm_dsc_compute_rc_parameters(vdsc_cfg); + if (ret) + return ret; + + crtc_state->dsc.compression_enable = true; + + return 0; +} + + + if (gen11_dsi_dsc_compute_config(encoder, pipe_config)) + drm_debug_kms("attempting to use dsc failed "); + - get_dsi_io_power_domains(to_i915(encoder->base.dev), - enc_to_intel_dsi(&encoder->base)); + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder->base)); + + if (crtc_state->dsc.compression_enable) + intel_display_power_get(i915, + intel_dsc_power_domain(crtc_state)); - .mode_valid = intel_dsi_mode_valid, + .mode_valid = gen11_dsi_mode_valid,
|
Graphics
|
2b68392e638dfa5cf4f7b558f62e3ea4def2e605
|
jani nikula
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: coffeelake supports hdcp2.2
|
this includes other platforms that utilize the same gen graphics as cfl: aml, whl and cml.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
hdcp 2.2 for cfl
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 1
| 1
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c - is_kabylake(dev_priv)); + is_kabylake(dev_priv) || is_coffeelake(dev_priv));
|
Graphics
|
6025ba1204713a3d9667cc1a278ed180c5aa367c
|
juston li ramalingam c ramalingam c intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915/lmem: debugfs for lmem details
|
debugfs i915_gem_object is extended to enable the igts to detect the lmem's availability and the total size of lmem.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
lmem debugfs support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 6
| 36
| 2
|
--- diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c --- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c + intel_memory_region_set_name(mem, "system"); + diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c + intel_memory_region_set_name(mem, "stolen"); + diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c + struct intel_memory_region *mr; + enum intel_region_id id; - + for_each_memory_region(mr, i915, id) + seq_printf(m, "%s: total:%pa, available:%pa bytes ", + mr->name, &mr->total, &mr->avail); diff --git a/drivers/gpu/drm/i915/intel_memory_region.c b/drivers/gpu/drm/i915/intel_memory_region.c --- a/drivers/gpu/drm/i915/intel_memory_region.c +++ b/drivers/gpu/drm/i915/intel_memory_region.c - intel_memory_region_free_pages(mem, blocks); + mem->avail += intel_memory_region_free_pages(mem, blocks); + mem->avail -= size; + mem->total = size; + mem->avail = mem->total; +void intel_memory_region_set_name(struct intel_memory_region *mem, + const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + vsnprintf(mem->name, sizeof(mem->name), fmt, ap); + va_end(ap); +} + diff --git a/drivers/gpu/drm/i915/intel_memory_region.h b/drivers/gpu/drm/i915/intel_memory_region.h --- a/drivers/gpu/drm/i915/intel_memory_region.h +++ b/drivers/gpu/drm/i915/intel_memory_region.h +#define for_each_memory_region(mr, i915, id) \ + for (id = 0; id < array_size((i915)->mm.regions); id++) \ + for_each_if((mr) = (i915)->mm.regions[id]) + + resource_size_t total; + resource_size_t avail; + char name[8]; +__printf(2, 3) void +intel_memory_region_set_name(struct intel_memory_region *mem, + const char *fmt, ...); + diff --git a/drivers/gpu/drm/i915/intel_region_lmem.c b/drivers/gpu/drm/i915/intel_region_lmem.c --- a/drivers/gpu/drm/i915/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/intel_region_lmem.c + intel_memory_region_set_name(mem, "local"); +
|
Graphics
|
38f1cb68582cee59c819864affeb70752eda3f04
|
lukasz fiedorowicz
|
drivers
|
gpu
|
drm, gem, i915
|
drm/i915/gem: support discontiguous lmem object maps
|
create a vmap for discontinguous lmem objects to support i915_gem_object_pin_map().
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
lmem discontiguous object maps
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 5
| 78
| 123
|
--- diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c -/* xxx: time to vfunc your life up? */ -void __iomem * -i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj, - unsigned long n) -{ - resource_size_t offset; - - offset = i915_gem_object_get_dma_address(obj, n); - offset -= obj->mm.region->region.start; - - return io_mapping_map_wc(&obj->mm.region->iomap, offset, page_size); -} - -void __iomem * -i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj, - unsigned long n) -{ - resource_size_t offset; - - offset = i915_gem_object_get_dma_address(obj, n); - offset -= obj->mm.region->region.start; - - return io_mapping_map_atomic_wc(&obj->mm.region->iomap, offset); -} - -void __iomem * -i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj, - unsigned long n, - unsigned long size) -{ - resource_size_t offset; - - gem_bug_on(!i915_gem_object_is_contiguous(obj)); - - offset = i915_gem_object_get_dma_address(obj, n); - offset -= obj->mm.region->region.start; - - return io_mapping_map_wc(&obj->mm.region->iomap, offset, size); -} - diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h --- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.h -void __iomem *i915_gem_object_lmem_io_map(struct drm_i915_gem_object *obj, - unsigned long n, unsigned long size); -void __iomem *i915_gem_object_lmem_io_map_page(struct drm_i915_gem_object *obj, - unsigned long n); -void __iomem * -i915_gem_object_lmem_io_map_page_atomic(struct drm_i915_gem_object *obj, - unsigned long n); - diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c - if (i915_gem_object_is_lmem(obj)) - io_mapping_unmap((void __force __iomem *)ptr); - else if (is_vmalloc_addr(ptr)) + if (is_vmalloc_addr(ptr)) +static inline pte_t iomap_pte(resource_size_t base, + dma_addr_t offset, + pgprot_t prot) +{ + return pte_mkspecial(pfn_pte((base + offset) >> page_shift, prot)); +} + - unsigned long n_pages = obj->base.size >> page_shift; + unsigned long n_pte = obj->base.size >> page_shift; - struct sgt_iter sgt_iter; - struct page *page; - struct page *stack_pages[32]; - struct page **pages = stack_pages; - unsigned long i = 0; + pte_t *stack[32], **mem; + struct vm_struct *area; - void *addr; - if (i915_gem_object_is_lmem(obj)) { - void __iomem *io; - - if (type != i915_map_wc) - return null; - - io = i915_gem_object_lmem_io_map(obj, 0, obj->base.size); - return (void __force *)io; - } + if (!i915_gem_object_has_struct_page(obj) && type != i915_map_wc) + return null; - if (n_pages == 1 && type == i915_map_wb) + if (n_pte == 1 && type == i915_map_wb) - if (n_pages > array_size(stack_pages)) { + mem = stack; + if (n_pte > array_size(stack)) { - pages = kvmalloc_array(n_pages, sizeof(*pages), gfp_kernel); - if (!pages) + mem = kvmalloc_array(n_pte, sizeof(*mem), gfp_kernel); + if (!mem) - for_each_sgt_page(page, sgt_iter, sgt) - pages[i++] = page; - - /* check that we have the expected number of pages */ - gem_bug_on(i != n_pages); + area = alloc_vm_area(obj->base.size, mem); + if (!area) { + if (mem != stack) + kvfree(mem); + return null; + } - addr = vmap(pages, n_pages, 0, pgprot); - if (pages != stack_pages) - kvfree(pages); + if (i915_gem_object_has_struct_page(obj)) { + struct sgt_iter iter; + struct page *page; + pte_t **ptes = mem; + + for_each_sgt_page(page, iter, sgt) + **ptes++ = mk_pte(page, pgprot); + } else { + resource_size_t iomap; + struct sgt_iter iter; + pte_t **ptes = mem; + dma_addr_t addr; + + iomap = obj->mm.region->iomap.base; + iomap -= obj->mm.region->region.start; + + for_each_sgt_daddr(addr, iter, sgt) + **ptes++ = iomap_pte(iomap, addr, pgprot); + } + + if (mem != stack) + kvfree(mem); - return addr; + return area->addr; diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c -static int __cpu_check_lmem(struct drm_i915_gem_object *obj, u32 dword, u32 val) +static int __cpu_check_vmap(struct drm_i915_gem_object *obj, u32 dword, u32 val) - unsigned long n; + unsigned long n = obj->base.size >> page_shift; + u32 *ptr; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_wc_domain(obj, false); - i915_gem_object_unlock(obj); - if (err) - return err; - - err = i915_gem_object_pin_pages(obj); + err = i915_gem_object_wait(obj, 0, max_schedule_timeout); - for (n = 0; n < obj->base.size >> page_shift; ++n) { - u32 __iomem *base; - u32 read_val; - - base = i915_gem_object_lmem_io_map_page_atomic(obj, n); + ptr = i915_gem_object_pin_map(obj, i915_map_wc); + if (is_err(ptr)) + return ptr_err(ptr); - read_val = ioread32(base + dword); - io_mapping_unmap_atomic(base); - if (read_val != val) { - pr_err("n=%lu base[%u]=%u, val=%u ", - n, dword, read_val, val); + ptr += dword; + while (n--) { + if (*ptr != val) { + pr_err("base[%u]=%08x, val=%08x ", + dword, *ptr, val); + + ptr += page_size / sizeof(*ptr); - i915_gem_object_unpin_pages(obj); + i915_gem_object_unpin_map(obj); - else if (i915_gem_object_is_lmem(obj)) - return __cpu_check_lmem(obj, dword, val); - - return -enodev; + else + return __cpu_check_vmap(obj, dword, val); diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c b/drivers/gpu/drm/i915/selftests/intel_memory_region.c --- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c +++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c - unsigned long n; + unsigned long n = obj->base.size >> page_shift; + u32 *ptr; - i915_gem_object_lock(obj); - err = i915_gem_object_set_to_wc_domain(obj, false); - i915_gem_object_unlock(obj); - if (err) - return err; - - err = i915_gem_object_pin_pages(obj); + err = i915_gem_object_wait(obj, 0, max_schedule_timeout); - for (n = 0; n < obj->base.size >> page_shift; ++n) { - u32 __iomem *base; - u32 read_val; - - base = i915_gem_object_lmem_io_map_page_atomic(obj, n); + ptr = i915_gem_object_pin_map(obj, i915_map_wc); + if (is_err(ptr)) + return ptr_err(ptr); - read_val = ioread32(base + dword); - io_mapping_unmap_atomic(base); - if (read_val != val) { - pr_err("n=%lu base[%u]=%u, val=%u ", - n, dword, read_val, val); + ptr += dword; + while (n--) { + if (*ptr != val) { + pr_err("base[%u]=%08x, val=%08x ", + dword, *ptr, val); + + ptr += page_size / sizeof(*ptr); - i915_gem_object_unpin_pages(obj); + i915_gem_object_unpin_map(obj);
|
Graphics
|
6056e50033d9f840bc1e35cac794b13144710a25
|
chris wilson
|
drivers
|
gpu
|
drm, gem, i915, selftests
|
drm/i915: create dumb buffer from lmem
|
when lmem is supported, dumb buffer preferred to be created from lmem.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
use lmem for dumb buffers if possible
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 22
| 7
|
--- diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c +#include "gem/i915_gem_region.h" - struct drm_i915_private *dev_priv, + struct intel_memory_region *mr, - size = round_up(*size_p, page_size); + gem_bug_on(!is_power_of_2(mr->min_page_size)); + size = round_up(*size_p, mr->min_page_size); + /* for most of the abi (e.g. mmap) we think in system pages */ + gem_bug_on(!is_aligned(size, page_size)); + - obj = i915_gem_object_create_shmem(dev_priv, size); + obj = i915_gem_object_create_region(mr, size, 0); + enum intel_memory_type mem_type; - return i915_gem_create(file, to_i915(dev), + + mem_type = intel_memory_system; + if (has_lmem(to_i915(dev))) + mem_type = intel_memory_local; + + return i915_gem_create(file, + intel_memory_region_by_type(to_i915(dev), + mem_type), - struct drm_i915_private *dev_priv = to_i915(dev); + struct drm_i915_private *i915 = to_i915(dev); - i915_gem_flush_free_objects(dev_priv); + i915_gem_flush_free_objects(i915); - return i915_gem_create(file, dev_priv, + return i915_gem_create(file, + intel_memory_region_by_type(i915, + intel_memory_system),
|
Graphics
|
05e8a5f51eb5863d8c316c68091500511770bff7
|
ramalingam c
|
drivers
|
gpu
|
drm, i915
|
drm/i915/gem: extend mmap support for lmem
|
local memory objects are similar to our usual scatterlist, but instead of using the struct page stored therein, we need to use the sg->dma_address.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add lmem mmap support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 3
| 39
| 22
|
--- diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c + case -enxio: /* unable to access backing store (on device) */ + resource_size_t iomap; - if (unlikely(!i915_gem_object_has_struct_page(obj))) - return vm_fault_sigbus; - + iomap = -1; + if (!i915_gem_object_type_has(obj, i915_gem_object_has_struct_page)) { + iomap = obj->mm.region->iomap.base; + iomap -= obj->mm.region->region.start; + } + - err = remap_io_sg_page(area, - area->vm_start, area->vm_end - area->vm_start, - obj->mm.pages->sgl); + err = remap_io_sg(area, + area->vm_start, area->vm_end - area->vm_start, + obj->mm.pages->sgl, iomap); - !i915_gem_object_has_struct_page(obj)) { + !i915_gem_object_type_has(obj, + i915_gem_object_has_struct_page | + i915_gem_object_has_iomem)) { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h -int remap_io_sg_page(struct vm_area_struct *vma, - unsigned long addr, unsigned long size, - struct scatterlist *sgl); +int remap_io_sg(struct vm_area_struct *vma, + unsigned long addr, unsigned long size, + struct scatterlist *sgl, resource_size_t iobase); diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/drm/i915/i915_mm.c --- a/drivers/gpu/drm/i915/i915_mm.c +++ b/drivers/gpu/drm/i915/i915_mm.c + resource_size_t iobase; -static inline unsigned long sgt_pfn(const struct sgt_iter *sgt) +#define use_dma(io) ((io) != -1) + +static inline unsigned long sgt_pfn(const struct remap_pfn *r) - return sgt->pfn + (sgt->curr >> page_shift); + if (use_dma(r->iobase)) + return (r->sgt.dma + r->sgt.curr + r->iobase) >> page_shift; + else + return r->sgt.pfn + (r->sgt.curr >> page_shift); -static int remap_sg_page(pte_t *pte, unsigned long addr, void *data) +static int remap_sg(pte_t *pte, unsigned long addr, void *data) - pte_mkspecial(pfn_pte(sgt_pfn(&r->sgt), r->prot))); + pte_mkspecial(pfn_pte(sgt_pfn(r), r->prot))); - r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), false); + r->sgt = __sgt_iter(__sg_next(r->sgt.sgp), use_dma(r->iobase)); - * remap_io_sg_page - remap an io mapping to userspace + * remap_io_sg - remap an io mapping to userspace + * @iobase: use stored dma address offset by this address or pfn if -1 -int remap_io_sg_page(struct vm_area_struct *vma, - unsigned long addr, unsigned long size, - struct scatterlist *sgl) +int remap_io_sg(struct vm_area_struct *vma, + unsigned long addr, unsigned long size, + struct scatterlist *sgl, resource_size_t iobase) - .sgt = __sgt_iter(sgl, false), + .sgt = __sgt_iter(sgl, use_dma(iobase)), + .iobase = iobase, - flush_cache_range(vma, addr, size); - err = apply_to_page_range(r.mm, addr, size, remap_sg_page, &r); + if (!use_dma(iobase)) + flush_cache_range(vma, addr, size); + + err = apply_to_page_range(r.mm, addr, size, remap_sg, &r);
|
Graphics
|
4e598fad226be0d044d318b6c49cec2ec2b72be3
|
abdiel janulgue chris wilson chris chris wilson co uk
|
drivers
|
gpu
|
drm, gem, i915
|
drm/i915/tgl: add second tgl pch id
|
another tgp id has shown up, so let's add it to avoid south display breakage on systems that have this id.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add second tgl pch id
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 2
| 2
| 0
|
--- diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drivers/gpu/drm/i915/intel_pch.c --- a/drivers/gpu/drm/i915/intel_pch.c +++ b/drivers/gpu/drm/i915/intel_pch.c + case intel_pch_tgp2_device_id_type: diff --git a/drivers/gpu/drm/i915/intel_pch.h b/drivers/gpu/drm/i915/intel_pch.h --- a/drivers/gpu/drm/i915/intel_pch.h +++ b/drivers/gpu/drm/i915/intel_pch.h +#define intel_pch_tgp2_device_id_type 0x4380
|
Graphics
|
6cf6e590ea2e45db1fcf3ef006d5adbd7f7c06ab
|
james ausmus jos roberto de souza jose souza intel com
|
drivers
|
gpu
|
drm, i915
|
drm/i915: add 10bpc formats with alpha for icl+
|
icl+ again supports alpha blending with 10bpc pixel formats. expose them.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add 10bpc formats with alpha for icl+
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 2
| 25
| 4
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c - if (rgb_order) - return drm_format_xbgr2101010; - else - return drm_format_xrgb2101010; + if (rgb_order) { + if (alpha) + return drm_format_abgr2101010; + else + return drm_format_xbgr2101010; + } else { + if (alpha) + return drm_format_argb2101010; + else + return drm_format_xrgb2101010; + } + case drm_format_abgr2101010: + case drm_format_argb2101010: + case drm_format_argb2101010: + case drm_format_abgr2101010: diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c + drm_format_argb2101010, + drm_format_abgr2101010, + drm_format_argb2101010, + drm_format_abgr2101010, + drm_format_argb2101010, + drm_format_abgr2101010, + case drm_format_argb2101010: + case drm_format_abgr2101010: + case drm_format_argb2101010: + case drm_format_abgr2101010:
|
Graphics
|
f9c43a313f5128a977a5f699a805c155990671fc
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: add new ehl/jsl pci ids
|
adding the recently added ehl/jsl pci ids.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add new ehl/jsl pci ids
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['h']
| 1
| 5
| 2
|
--- diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h -/* ehl */ +/* ehl/jsl */ - intel_vga_device(0x4541, info) + intel_vga_device(0x4541, info), \ + intel_vga_device(0x4e71, info), \ + intel_vga_device(0x4e61, info), \ + intel_vga_device(0x4e51, info)
|
Graphics
|
651cc835d5f6855e8bca6d5d3587234d74e82864
|
jos roberto de souza matt roper matthew d roper intel com
|
include
|
drm
| |
drm/i915: expose 10:10:10 xrgb formats on snb-bdw sprites
|
snb-bdw support 10:10:10 formats on the sprite planes. let's expose them.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
expose more formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 16
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c + case drm_format_xbgr2101010: + sprctl |= sprite_format_rgbx101010 | sprite_rgb_order_rgbx; + break; + case drm_format_xrgb2101010: + sprctl |= sprite_format_rgbx101010; + break; + case drm_format_xbgr2101010: + dvscntr |= dvs_format_rgbx101010 | dvs_rgb_order_xbgr; + break; + case drm_format_xrgb2101010: + dvscntr |= dvs_format_rgbx101010; + break; + drm_format_xrgb2101010, + drm_format_xbgr2101010, + case drm_format_xrgb2101010: + case drm_format_xbgr2101010:
|
Graphics
|
ffe0fd2404f794ad24f8a68b6778036a7f4309c1
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: expose alpha formats on vlv/chv primary planes
|
currently we expose vlv/chv alpha blending only on the sprite planes, but the primary planes can do it as well. let's flip it on.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
expose more formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 2
| 60
| 3
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c +/* primary plane formats for vlv/chv */ +static const u32 vlv_primary_formats[] = { + drm_format_c8, + drm_format_rgb565, + drm_format_xrgb8888, + drm_format_xbgr8888, + drm_format_argb8888, + drm_format_abgr8888, + drm_format_xrgb2101010, + drm_format_xbgr2101010, + drm_format_argb2101010, + drm_format_abgr2101010, + drm_format_xbgr16161616f, +}; + + case dispplane_bgra555: + return drm_format_argb1555; + case dispplane_bgra888: + return drm_format_argb8888; + case dispplane_rgba888: + return drm_format_abgr8888; + case dispplane_bgra101010: + return drm_format_argb2101010; + case dispplane_rgba101010: + return drm_format_abgr2101010; + case drm_format_argb1555: + dspcntr |= dispplane_bgra555; + break; + case drm_format_argb8888: + dspcntr |= dispplane_bgra888; + break; + case drm_format_abgr8888: + dspcntr |= dispplane_rgba888; + break; + case drm_format_argb2101010: + dspcntr |= dispplane_bgra101010; + break; + case drm_format_abgr2101010: + dspcntr |= dispplane_rgba101010; + break; + case drm_format_argb8888: + case drm_format_abgr8888: + case drm_format_argb2101010: + case drm_format_abgr2101010: - if (intel_gen(dev_priv) >= 4) { + if (is_valleyview(dev_priv) || is_cherryview(dev_priv)) { + formats = vlv_primary_formats; + num_formats = array_size(vlv_primary_formats); + modifiers = i9xx_format_modifiers; + + plane->max_stride = i9xx_plane_max_stride; + plane->update_plane = i9xx_update_plane; + plane->disable_plane = i9xx_disable_plane; + plane->get_hw_state = i9xx_plane_get_hw_state; + plane->check_plane = i9xx_plane_check; + plane->min_cdclk = vlv_plane_min_cdclk; + + plane_funcs = &i965_plane_funcs; + } else if (intel_gen(dev_priv) >= 4) { + - else if (is_cherryview(dev_priv) || is_valleyview(dev_priv)) - plane->min_cdclk = vlv_plane_min_cdclk; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define dispplane_bgra101010 (0xb << 26)
|
Graphics
|
73263cb6e2fe77681e872f94999458db27d8d7bc
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: add missing 10bpc formats for pipe b sprites on chv
|
chv pipe b sprites gained support for the 10bpc x/argb pixel formats. on vlv and chv pipe a/c these are only supported by the primary plane. add the require bits to expose the new formats.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
expose more formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 2
| 39
| 8
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c + case drm_format_xrgb2101010: + sprctl |= sp_format_bgrx1010102; + break; + case drm_format_argb2101010: + sprctl |= sp_format_bgra1010102; + break; +static const u32 chv_pipe_b_sprite_formats[] = { + drm_format_rgb565, + drm_format_xrgb8888, + drm_format_xbgr8888, + drm_format_argb8888, + drm_format_abgr8888, + drm_format_xrgb2101010, + drm_format_xbgr2101010, + drm_format_argb2101010, + drm_format_abgr2101010, + drm_format_yuyv, + drm_format_yvyu, + drm_format_uyvy, + drm_format_vyuy, +}; + + case drm_format_xrgb2101010: + case drm_format_argb2101010: - formats = vlv_plane_formats; - num_formats = array_size(vlv_plane_formats); + if (is_cherryview(dev_priv) && pipe == pipe_b) { + formats = chv_pipe_b_sprite_formats; + num_formats = array_size(chv_pipe_b_sprite_formats); + } else { + formats = vlv_plane_formats; + num_formats = array_size(vlv_plane_formats); + } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h -#define sp_format_yuv422 (0 << 26) -#define sp_format_bgr565 (5 << 26) -#define sp_format_bgrx8888 (6 << 26) -#define sp_format_bgra8888 (7 << 26) -#define sp_format_rgbx1010102 (8 << 26) -#define sp_format_rgba1010102 (9 << 26) +#define sp_format_yuv422 (0x0 << 26) +#define sp_format_bgr565 (0x5 << 26) +#define sp_format_bgrx8888 (0x6 << 26) +#define sp_format_bgra8888 (0x7 << 26) +#define sp_format_rgbx1010102 (0x8 << 26) +#define sp_format_rgba1010102 (0x9 << 26) +#define sp_format_bgrx1010102 (0xa << 26) /* chv pipe b */ +#define sp_format_bgra1010102 (0xb << 26) /* chv pipe b */
|
Graphics
|
d8aa1a487b3201a1586739d3e8a1aeceaf9111f7
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: expose c8 on vlv/chv sprite planes
|
vlv/chv sprite planes also support the c8 format. let's expose that.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
expose more formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 2
| 7
| 0
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c + case drm_format_c8: + sprctl |= sp_format_8bpp; + break; + drm_format_c8, + drm_format_c8, + case drm_format_c8: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h +#define sp_format_8bpp (0x2 << 26)
|
Graphics
|
ed94034f3d6dc8c9fa1dae59f6058bbd06a97034
|
ville syrj l uma shankar uma shankar intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: sort format arrays consistently
|
let's try to keep the pixel format arrays somewhat sorted: 1. rgb before yuv 2. smaller bpp before larger bpp 3. x before a 4. rgb before bgr
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
expose more formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 2
| 4
| 4
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c - drm_format_rgb565, + drm_format_rgb565, diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c - drm_format_abgr8888, - drm_format_argb8888, - drm_format_xbgr8888, + drm_format_xbgr8888, + drm_format_argb8888, + drm_format_abgr8888,
|
Graphics
|
12fef149d755e33230108b923fcb6216a8e1e2de
|
ville syrj l juha pekka heikkila juhapekka heikkila gmail com uma shankar uma shankar intel com
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: eliminate redundancy in intel_primary_plane_create()
|
lots of redundant assignments inside intel_primary_plane_create(). get rid of them.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
expose more formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c']
| 1
| 22
| 38
|
--- diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c - const u64 *modifiers; - modifiers = i9xx_format_modifiers; - - plane->max_stride = i9xx_plane_max_stride; - plane->update_plane = i9xx_update_plane; - plane->disable_plane = i9xx_disable_plane; - plane->get_hw_state = i9xx_plane_get_hw_state; - plane->check_plane = i9xx_plane_check; - plane->min_cdclk = vlv_plane_min_cdclk; - - plane_funcs = &i965_plane_funcs; - - modifiers = i9xx_format_modifiers; - - plane->max_stride = i9xx_plane_max_stride; - plane->update_plane = i9xx_update_plane; - plane->disable_plane = i9xx_disable_plane; - plane->get_hw_state = i9xx_plane_get_hw_state; - plane->check_plane = i9xx_plane_check; - - if (is_broadwell(dev_priv) || is_haswell(dev_priv)) - plane->min_cdclk = hsw_plane_min_cdclk; - else if (is_ivybridge(dev_priv)) - plane->min_cdclk = ivb_plane_min_cdclk; - else - plane->min_cdclk = i9xx_plane_min_cdclk; - - plane_funcs = &i965_plane_funcs; - modifiers = i9xx_format_modifiers; + } - plane->max_stride = i9xx_plane_max_stride; - plane->update_plane = i9xx_update_plane; - plane->disable_plane = i9xx_disable_plane; - plane->get_hw_state = i9xx_plane_get_hw_state; - plane->check_plane = i9xx_plane_check; + if (intel_gen(dev_priv) >= 4) + plane_funcs = &i965_plane_funcs; + else + plane_funcs = &i8xx_plane_funcs; + + if (is_valleyview(dev_priv) || is_cherryview(dev_priv)) + plane->min_cdclk = vlv_plane_min_cdclk; + else if (is_broadwell(dev_priv) || is_haswell(dev_priv)) + plane->min_cdclk = hsw_plane_min_cdclk; + else if (is_ivybridge(dev_priv)) + plane->min_cdclk = ivb_plane_min_cdclk; + else - plane_funcs = &i8xx_plane_funcs; - } + plane->max_stride = i9xx_plane_max_stride; + plane->update_plane = i9xx_update_plane; + plane->disable_plane = i9xx_disable_plane; + plane->get_hw_state = i9xx_plane_get_hw_state; + plane->check_plane = i9xx_plane_check; - formats, num_formats, modifiers, + formats, num_formats, + i9xx_format_modifiers, - formats, num_formats, modifiers, + formats, num_formats, + i9xx_format_modifiers,
|
Graphics
|
dbb1a6fbbb809fe364f51293026616c58916f330
|
ville syrj l
|
drivers
|
gpu
|
display, drm, i915
|
drm/i915: introduce drm_i915_gem_mmap_offset
|
this is really just an alias of mmap_gtt. the 'mmap offset' nomenclature comes from the value returned by this ioctl which is the offset into the device fd which userpace uses with mmap(2).
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
introduce
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['intel ']
|
['c', 'h']
| 18
| 574
| 142
|
--- diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c b/drivers/gpu/drm/i915/gem/i915_gem_domain.c --- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c +#include "i915_gem_mman.h" diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h --- a/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_ioctls.h -int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, - struct drm_file *file); +int i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c +#include <linux/pfn_t.h> +#include "i915_gem_mman.h" + * 4 - support multiple fault handlers per object depending on object's + * backing storage (a.k.a. mmap_offset). + * - return 3; + return 4; -/** - * i915_gem_fault - fault a page into the gtt - * @vmf: fault info - * - * the fault handler is set up by drm_gem_mmap() when a object is gtt mapped - * from userspace. the fault handler takes care of binding the object to - * the gtt (if needed), allocating and programming a fence register (again, - * only if needed based on whether the old reg is still valid or the object - * is tiled) and inserting a new pte into the faulting process. - * - * note that the faulting process may involve evicting existing objects - * from the gtt and/or fence registers to make room. so performance may - * suffer if the gtt working set is large or there are few fence registers - * left. - * - * the current feature set supported by i915_gem_fault() and thus gtt mmaps - * is exposed via i915_param_mmap_gtt_version (see i915_gem_mmap_gtt_version). - */ -vm_fault_t i915_gem_fault(struct vm_fault *vmf) +static vm_fault_t i915_error_to_vmf_fault(int err) +{ + switch (err) { + default: + warn_once(err, "unhandled error in %s: %i ", __func__, err); + /* fallthrough */ + case -eio: /* shmemfs failure from swap device */ + case -efault: /* purged object */ + case -enodev: /* bad object, how did you get here! */ + return vm_fault_sigbus; + + case -enospc: /* shmemfs allocation failure */ + case -enomem: /* our allocation failure */ + return vm_fault_oom; + + case 0: + case -eagain: + case -erestartsys: + case -eintr: + case -ebusy: + /* + * ebusy is ok: this just means that another thread + * already did the job. + */ + return vm_fault_nopage; + } +} + +static vm_fault_t vm_fault_cpu(struct vm_fault *vmf) +{ + struct vm_area_struct *area = vmf->vma; + struct i915_mmap_offset *mmo = area->vm_private_data; + struct drm_i915_gem_object *obj = mmo->obj; + unsigned long i, size = area->vm_end - area->vm_start; + bool write = area->vm_flags & vm_write; + vm_fault_t ret = vm_fault_sigbus; + int err; + + if (!i915_gem_object_has_struct_page(obj)) + return ret; + + /* sanity check that we allow writing into this object */ + if (i915_gem_object_is_readonly(obj) && write) + return ret; + + err = i915_gem_object_pin_pages(obj); + if (err) + return i915_error_to_vmf_fault(err); + + /* ptes are revoked in obj->ops->put_pages() */ + for (i = 0; i < size >> page_shift; i++) { + struct page *page = i915_gem_object_get_page(obj, i); + + ret = vmf_insert_pfn(area, + (unsigned long)area->vm_start + i * page_size, + page_to_pfn(page)); + if (ret != vm_fault_nopage) + break; + } + + if (write) { + gem_bug_on(!i915_gem_object_has_pinned_pages(obj)); + obj->cache_dirty = true; /* xxx flush after pat update? */ + obj->mm.dirty = true; + } + + i915_gem_object_unpin_pages(obj); + + return ret; +} + +static vm_fault_t vm_fault_gtt(struct vm_fault *vmf) - struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); + struct i915_mmap_offset *mmo = area->vm_private_data; + struct drm_i915_gem_object *obj = mmo->obj; + /* track the mmo associated with the fenced vma */ + vma->mmo = mmo; + - switch (ret) { - default: - warn_once(ret, "unhandled error in %s: %i ", __func__, ret); - /* fallthrough */ - case -eio: /* shmemfs failure from swap device */ - case -efault: /* purged object */ - case -enodev: /* bad object, how did you get here! */ - return vm_fault_sigbus; - - case -enospc: /* shmemfs allocation failure */ - case -enomem: /* our allocation failure */ - return vm_fault_oom; - - case 0: - case -eagain: - case -erestartsys: - case -eintr: - case -ebusy: - /* - * ebusy is ok: this just means that another thread - * already did the job. - */ - return vm_fault_nopage; - } + return i915_error_to_vmf_fault(ret); -void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj) +void __i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj) - obj->userfault_count = 0; - list_del(&obj->userfault_link); - drm_vma_node_unmap(&obj->base.vma_node, - obj->base.dev->anon_inode->i_mapping); - - i915_vma_unset_userfault(vma); + i915_vma_revoke_mmap(vma); + + gem_bug_on(obj->userfault_count); -/** - * i915_gem_object_release_mmap - remove physical page mappings - * @obj: obj in question - * - * preserve the reservation of the mmapping with the drm core code, but - * relinquish ownership of the pages back to the system. - * +/* - * fixup by i915_gem_fault(). + * fixup by vm_fault_gtt(). -void i915_gem_object_release_mmap(struct drm_i915_gem_object *obj) +static void i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj) - /* serialisation between user gtt access and our code depends upon + /* + * serialisation between user gtt access and our code depends upon - __i915_gem_object_release_mmap(obj); + __i915_gem_object_release_mmap_gtt(obj); - /* ensure that the cpu's pte are revoked and there are not outstanding + /* + * ensure that the cpu's pte are revoked and there are not outstanding -static int create_mmap_offset(struct drm_i915_gem_object *obj) +void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj) +{ + struct i915_mmap_offset *mmo; + + spin_lock(&obj->mmo.lock); + list_for_each_entry(mmo, &obj->mmo.offsets, offset) { + /* + * vma_node_unmap for gtt mmaps handled already in + * __i915_gem_object_release_mmap_gtt + */ + if (mmo->mmap_type == i915_mmap_type_gtt) + continue; + + spin_unlock(&obj->mmo.lock); + drm_vma_node_unmap(&mmo->vma_node, + obj->base.dev->anon_inode->i_mapping); + spin_lock(&obj->mmo.lock); + } + spin_unlock(&obj->mmo.lock); +} + +/** + * i915_gem_object_release_mmap - remove physical page mappings + * @obj: obj in question + * + * preserve the reservation of the mmapping with the drm core code, but + * relinquish ownership of the pages back to the system. + */ +void i915_gem_object_release_mmap(struct drm_i915_gem_object *obj) +{ + i915_gem_object_release_mmap_gtt(obj); + i915_gem_object_release_mmap_offset(obj); +} + +static struct i915_mmap_offset * +mmap_offset_attach(struct drm_i915_gem_object *obj, + enum i915_mmap_type mmap_type, + struct drm_file *file) - struct intel_gt *gt = &i915->gt; + struct i915_mmap_offset *mmo; - err = drm_gem_create_mmap_offset(&obj->base); + mmo = kmalloc(sizeof(*mmo), gfp_kernel); + if (!mmo) + return err_ptr(-enomem); + + mmo->obj = obj; + mmo->dev = obj->base.dev; + mmo->file = file; + mmo->mmap_type = mmap_type; + drm_vma_node_reset(&mmo->vma_node); + + err = drm_vma_offset_add(mmo->dev->vma_offset_manager, &mmo->vma_node, + obj->base.size / page_size); - return 0; + goto out; - err = intel_gt_retire_requests_timeout(gt, max_schedule_timeout); + err = intel_gt_retire_requests_timeout(&i915->gt, max_schedule_timeout); - return err; + goto err; - return drm_gem_create_mmap_offset(&obj->base); + err = drm_vma_offset_add(mmo->dev->vma_offset_manager, &mmo->vma_node, + obj->base.size / page_size); + if (err) + goto err; + +out: + if (file) + drm_vma_node_allow(&mmo->vma_node, file); + + spin_lock(&obj->mmo.lock); + list_add(&mmo->offset, &obj->mmo.offsets); + spin_unlock(&obj->mmo.lock); + + return mmo; + +err: + kfree(mmo); + return err_ptr(err); -int -i915_gem_mmap_gtt(struct drm_file *file, - struct drm_device *dev, - u32 handle, - u64 *offset) +static int +__assign_mmap_offset(struct drm_file *file, + u32 handle, + enum i915_mmap_type mmap_type, + u64 *offset) - int ret; - - if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt)) - return -enodev; + struct i915_mmap_offset *mmo; + int err; - if (i915_gem_object_never_bind_ggtt(obj)) { - ret = -enodev; + if (mmap_type == i915_mmap_type_gtt && + i915_gem_object_never_bind_ggtt(obj)) { + err = -enodev; - ret = create_mmap_offset(obj); - if (ret == 0) - *offset = drm_vma_node_offset_addr(&obj->base.vma_node); + if (mmap_type != i915_mmap_type_gtt && + !i915_gem_object_has_struct_page(obj)) { + err = -enodev; + goto out; + } + + mmo = mmap_offset_attach(obj, mmap_type, file); + if (is_err(mmo)) { + err = ptr_err(mmo); + goto out; + } + *offset = drm_vma_node_offset_addr(&mmo->vma_node); + err = 0; - return ret; + return err; +} + +int +i915_gem_dumb_mmap_offset(struct drm_file *file, + struct drm_device *dev, + u32 handle, + u64 *offset) +{ + enum i915_mmap_type mmap_type; + + if (boot_cpu_has(x86_feature_pat)) + mmap_type = i915_mmap_type_wc; + else if (!i915_ggtt_has_aperture(&to_i915(dev)->ggtt)) + return -enodev; + else + mmap_type = i915_mmap_type_gtt; + + return __assign_mmap_offset(file, handle, mmap_type, offset); - * i915_gem_mmap_gtt_ioctl - prepare an object for gtt mmap'ing + * i915_gem_mmap_offset_ioctl - prepare an object for gtt mmap'ing -i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, - struct drm_file *file) +i915_gem_mmap_offset_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) - struct drm_i915_gem_mmap_gtt *args = data; + struct drm_i915_private *i915 = to_i915(dev); + struct drm_i915_gem_mmap_offset *args = data; + enum i915_mmap_type type; + + if (args->extensions) + return -einval; + + switch (args->flags) { + case i915_mmap_offset_gtt: + if (!i915_ggtt_has_aperture(&i915->ggtt)) + return -enodev; + type = i915_mmap_type_gtt; + break; + + case i915_mmap_offset_wc: + if (!boot_cpu_has(x86_feature_pat)) + return -enodev; + type = i915_mmap_type_wc; + break; + + case i915_mmap_offset_wb: + type = i915_mmap_type_wb; + break; + + case i915_mmap_offset_uc: + if (!boot_cpu_has(x86_feature_pat)) + return -enodev; + type = i915_mmap_type_uc; + break; + + default: + return -einval; + } - return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); + return __assign_mmap_offset(file, args->handle, type, &args->offset); +} + +static void vm_open(struct vm_area_struct *vma) +{ + struct i915_mmap_offset *mmo = vma->vm_private_data; + struct drm_i915_gem_object *obj = mmo->obj; + + gem_bug_on(!obj); + i915_gem_object_get(obj); +} + +static void vm_close(struct vm_area_struct *vma) +{ + struct i915_mmap_offset *mmo = vma->vm_private_data; + struct drm_i915_gem_object *obj = mmo->obj; + + gem_bug_on(!obj); + i915_gem_object_put(obj); +} + +static const struct vm_operations_struct vm_ops_gtt = { + .fault = vm_fault_gtt, + .open = vm_open, + .close = vm_close, +}; + +static const struct vm_operations_struct vm_ops_cpu = { + .fault = vm_fault_cpu, + .open = vm_open, + .close = vm_close, +}; + +/* + * this overcomes the limitation in drm_gem_mmap's assignment of a + * drm_gem_object as the vma->vm_private_data. since we need to + * be able to resolve multiple mmap offsets which could be tied + * to a single gem object. + */ +int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_vma_offset_node *node; + struct drm_file *priv = filp->private_data; + struct drm_device *dev = priv->minor->dev; + struct i915_mmap_offset *mmo = null; + struct drm_gem_object *obj = null; + + if (drm_dev_is_unplugged(dev)) + return -enodev; + + drm_vma_offset_lock_lookup(dev->vma_offset_manager); + node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, + vma->vm_pgoff, + vma_pages(vma)); + if (likely(node)) { + mmo = container_of(node, struct i915_mmap_offset, + vma_node); + /* + * in our dependency chain, the drm_vma_offset_node + * depends on the validity of the mmo, which depends on + * the gem object. however the only reference we have + * at this point is the mmo (as the parent of the node). + * try to check if the gem object was at least cleared. + */ + if (!mmo || !mmo->obj) { + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); + return -einval; + } + /* + * skip 0-refcnted objects as it is in the process of being + * destroyed and will be invalid when the vma manager lock + * is released. + */ + obj = &mmo->obj->base; + if (!kref_get_unless_zero(&obj->refcount)) + obj = null; + } + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); + if (!obj) + return -einval; + + if (!drm_vma_node_is_allowed(node, priv)) { + drm_gem_object_put_unlocked(obj); + return -eacces; + } + + if (i915_gem_object_is_readonly(to_intel_bo(obj))) { + if (vma->vm_flags & vm_write) { + drm_gem_object_put_unlocked(obj); + return -einval; + } + vma->vm_flags &= ~vm_maywrite; + } + + vma->vm_flags |= vm_pfnmap | vm_dontexpand | vm_dontdump; + vma->vm_private_data = mmo; + + switch (mmo->mmap_type) { + case i915_mmap_type_wc: + vma->vm_page_prot = + pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_ops = &vm_ops_cpu; + break; + + case i915_mmap_type_wb: + vma->vm_page_prot = vm_get_page_prot(vma->vm_flags); + vma->vm_ops = &vm_ops_cpu; + break; + + case i915_mmap_type_uc: + vma->vm_page_prot = + pgprot_noncached(vm_get_page_prot(vma->vm_flags)); + vma->vm_ops = &vm_ops_cpu; + break; + + case i915_mmap_type_gtt: + vma->vm_page_prot = + pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_ops = &vm_ops_gtt; + break; + } + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + + return 0; diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.h b/drivers/gpu/drm/i915/gem/i915_gem_mman.h --- /dev/null +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.h +/* + * spdx-license-identifier: mit + * + * copyright ©️ 2019 intel corporation + */ + +#ifndef __i915_gem_mman_h__ +#define __i915_gem_mman_h__ + +#include <linux/mm_types.h> +#include <linux/types.h> + +struct drm_device; +struct drm_file; +struct drm_i915_gem_object; +struct file; +struct i915_mmap_offset; +struct mutex; + +int i915_gem_mmap_gtt_version(void); +int i915_gem_mmap(struct file *filp, struct vm_area_struct *vma); + +int i915_gem_dumb_mmap_offset(struct drm_file *file_priv, + struct drm_device *dev, + u32 handle, u64 *offset); + +void __i915_gem_object_release_mmap_gtt(struct drm_i915_gem_object *obj); +void i915_gem_object_release_mmap(struct drm_i915_gem_object *obj); +void i915_gem_object_release_mmap_offset(struct drm_i915_gem_object *obj); + +#endif diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c b/drivers/gpu/drm/i915/gem/i915_gem_object.c --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c +#include "i915_gem_mman.h" + spin_lock_init(&obj->mmo.lock); + init_list_head(&obj->mmo.offsets); + + struct i915_mmap_offset *mmo; + spin_lock(&obj->mmo.lock); + list_for_each_entry(mmo, &obj->mmo.offsets, offset) { + if (mmo->file != file) + continue; + + spin_unlock(&obj->mmo.lock); + drm_vma_node_revoke(&mmo->vma_node, file); + spin_lock(&obj->mmo.lock); + } + spin_unlock(&obj->mmo.lock); + + struct i915_mmap_offset *mmo, *mn; + + i915_gem_object_release_mmap(obj); + + list_for_each_entry_safe(mmo, mn, &obj->mmo.offsets, offset) { + drm_vma_offset_remove(obj->base.dev->vma_offset_manager, + &mmo->vma_node); + kfree(mmo); + } + init_list_head(&obj->mmo.offsets); + diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h - obj->base.vma_node.readonly = true; + obj->flags |= i915_bo_readonly; - return obj->base.vma_node.readonly; + return obj->flags & i915_bo_readonly; -void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj); -void i915_gem_object_release_mmap(struct drm_i915_gem_object *obj); - diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h +enum i915_mmap_type { + i915_mmap_type_gtt = 0, + i915_mmap_type_wc, + i915_mmap_type_wb, + i915_mmap_type_uc, +}; + +struct i915_mmap_offset { + struct drm_device *dev; + struct drm_vma_offset_node vma_node; + struct drm_i915_gem_object *obj; + struct drm_file *file; + enum i915_mmap_type mmap_type; + + struct list_head offset; +}; + + struct { + spinlock_t lock; /* protects access to mmo offsets */ + struct list_head offsets; + } mmo; + +#define i915_bo_readonly bit(2) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c +#include "i915_gem_mman.h" + i915_gem_object_release_mmap_offset(obj); + diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c +#include "i915_gem_mman.h" diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c - int err; + struct i915_mmap_offset *mmo; - err = create_mmap_offset(obj); + mmo = mmap_offset_attach(obj, i915_mmap_offset_gtt, null); - return err == expected; + return ptr_err_or_zero(mmo) == expected; - int loop, err; + struct i915_mmap_offset *mmo; + int loop, err = 0; - err = create_mmap_offset(obj); - if (err) { + mmo = mmap_offset_attach(obj, i915_mmap_offset_gtt, null); + if (is_err(mmo)) { + err = ptr_err(mmo); -static int igt_mmap_gtt(void *arg) +static int igt_mmap(void *arg, enum i915_mmap_type type) + struct i915_mmap_offset *mmo; - int err, i; + int err = 0, i; - err = create_mmap_offset(obj); - if (err) + mmo = mmap_offset_attach(obj, type, null); + if (is_err(mmo)) { + err = ptr_err(mmo); + } - addr = igt_mmap_node(i915, &obj->base.vma_node, - 0, prot_write, map_shared); + addr = igt_mmap_node(i915, &mmo->vma_node, 0, prot_write, map_shared); - pr_debug("igt_mmap(obj:gtt) @ %lx ", addr); + pr_debug("igt_mmap() @ %lx ", addr); - if (area->vm_private_data != obj) { - pr_err("vm_area_struct did not point back to our object! "); + if (area->vm_private_data != mmo) { + pr_err("vm_area_struct did not point back to our mmap_offset object! "); - pr_err("unable to read from gtt mmap, offset:%zd ", + pr_err("unable to read from mmap, offset:%zd ", - pr_err("read incorrect value from gtt mmap, offset:%zd, found:%x, expected:%x ", + pr_err("read incorrect value from mmap, offset:%zd, found:%x, expected:%x ", - pr_err("unable to write to gtt mmap, offset:%zd ", + pr_err("unable to write to mmap, offset:%zd ", - pr_err("write via ggtt mmap did not land in backing store "); + pr_err("write via mmap did not land in backing store "); +static int igt_mmap_gtt(void *arg) +{ + return igt_mmap(arg, i915_mmap_type_gtt); +} + +static int igt_mmap_cpu(void *arg) +{ + return igt_mmap(arg, i915_mmap_type_wc); +} + -static int igt_mmap_gtt_revoke(void *arg) +static int igt_mmap_revoke(void *arg, enum i915_mmap_type type) + struct i915_mmap_offset *mmo; - err = create_mmap_offset(obj); - if (err) + mmo = mmap_offset_attach(obj, type, null); + if (is_err(mmo)) { + err = ptr_err(mmo); + } - addr = igt_mmap_node(i915, &obj->base.vma_node, - 0, prot_write, map_shared); + addr = igt_mmap_node(i915, &mmo->vma_node, 0, prot_write, map_shared); - gem_bug_on(!atomic_read(&obj->bind_count)); + gem_bug_on(mmo->mmap_type == i915_mmap_type_gtt && + !atomic_read(&obj->bind_count)); + if (type != i915_mmap_type_gtt) { + __i915_gem_object_put_pages(obj); + if (i915_gem_object_has_pages(obj)) { + pr_err("failed to put-pages object! "); + err = -einval; + goto out_unmap; + } + } + +static int igt_mmap_gtt_revoke(void *arg) +{ + return igt_mmap_revoke(arg, i915_mmap_type_gtt); +} + +static int igt_mmap_cpu_revoke(void *arg) +{ + return igt_mmap_revoke(arg, i915_mmap_type_wc); +} + + subtest(igt_mmap_cpu), + subtest(igt_mmap_cpu_revoke), diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c --- a/drivers/gpu/drm/i915/gt/intel_reset.c +++ b/drivers/gpu/drm/i915/gt/intel_reset.c - node = &vma->obj->base.vma_node; + + if (!vma->mmo) + continue; + + node = &vma->mmo->vma_node; + diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c +#include "gem/i915_gem_mman.h" -static const struct vm_operations_struct i915_gem_vm_ops = { - .fault = i915_gem_fault, - .open = drm_gem_vm_open, - .close = drm_gem_vm_close, -}; - - .mmap = drm_gem_mmap, + .mmap = i915_gem_mmap, - drm_ioctl_def_drv(i915_gem_mmap_gtt, i915_gem_mmap_gtt_ioctl, drm_render_allow), + drm_ioctl_def_drv(i915_gem_mmap_offset, i915_gem_mmap_offset_ioctl, drm_render_allow), - .gem_vm_ops = &i915_gem_vm_ops, - .dumb_map_offset = i915_gem_mmap_gtt, + .dumb_map_offset = i915_gem_dumb_mmap_offset, + diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h -int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, - u32 handle, u64 *offset); -int i915_gem_mmap_gtt_version(void); -vm_fault_t i915_gem_fault(struct vm_fault *vmf); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c +#include "gem/i915_gem_mman.h" - __i915_gem_object_release_mmap(obj); + __i915_gem_object_release_mmap_gtt(obj); diff --git a/drivers/gpu/drm/i915/i915_getparam.c b/drivers/gpu/drm/i915/i915_getparam.c --- a/drivers/gpu/drm/i915/i915_getparam.c +++ b/drivers/gpu/drm/i915/i915_getparam.c +#include "gem/i915_gem_mman.h" diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c - struct drm_vma_offset_node *node = &vma->obj->base.vma_node; + struct drm_vma_offset_node *node; - lockdep_assert_held(&vma->vm->mutex); - + node = &vma->mmo->vma_node; diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h + /* mmap-offset associated with fencing for this vma */ + struct i915_mmap_offset *mmo; + diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h +#define drm_ioctl_i915_gem_mmap_offset drm_iowr(drm_command_base + drm_i915_gem_mmap_gtt, struct drm_i915_gem_mmap_offset) +struct drm_i915_gem_mmap_offset { + /** handle for the object being mapped. */ + __u32 handle; + __u32 pad; + /** + * fake offset to use for subsequent mmap call + * + * this is a fixed-size type for 32/64 compatibility. + */ + __u64 offset; + + /** + * flags for extended behaviour. + * + * it is mandatory that one of the mmap_offset types + * (gtt, wc, wb, uc, etc) should be included. + */ + __u64 flags; +#define i915_mmap_offset_gtt 0 +#define i915_mmap_offset_wc 1 +#define i915_mmap_offset_wb 2 +#define i915_mmap_offset_uc 3 + + /* + * zero-terminated chain of extensions. + * + * no current extensions defined; mbz. + */ + __u64 extensions; +}; +
|
Graphics
|
cc662126b4134e25fcfb6cad480de0fa95a4d3d8
|
abdiel janulgue
|
include
|
uapi
|
drm, gem, gt, i915, selftests
|
drm/panel: simple: add logic pd type 28 display support
|
previously, there was an omap panel-dpi driver that would read generic timings from the device tree and set the display timing accordingly. this driver was removed so the screen no longer functions. this patch modifies the panel-simple file to setup the timings to the same values previously used.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
logic pd type 28 panel support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ']
|
['c']
| 1
| 37
| 0
|
--- diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c +static const struct drm_display_mode logicpd_type_28_mode = { + .clock = 9000, + .hdisplay = 480, + .hsync_start = 480 + 3, + .hsync_end = 480 + 3 + 42, + .htotal = 480 + 3 + 42 + 2, + + .vdisplay = 272, + .vsync_start = 272 + 2, + .vsync_end = 272 + 2 + 11, + .vtotal = 272 + 2 + 11 + 3, + .vrefresh = 60, + .flags = drm_mode_flag_phsync | drm_mode_flag_pvsync, +}; + +static const struct panel_desc logicpd_type_28 = { + .modes = &logicpd_type_28_mode, + .num_modes = 1, + .bpc = 8, + .size = { + .width = 105, + .height = 67, + }, + .delay = { + .prepare = 200, + .enable = 200, + .unprepare = 200, + .disable = 200, + }, + .bus_format = media_bus_fmt_rgb888_1x24, + .bus_flags = drm_bus_flag_de_high | drm_bus_flag_pixdata_drive_posedge | + drm_bus_flag_sync_drive_negedge, +}; + + }, { + .compatible = "logicpd,type28", + .data = &logicpd_type_28,
|
Graphics
|
0d35408afbeb603bc9972ae91e4dd2638bcffe52
|
adam ford
|
drivers
|
gpu
|
drm, panel
|
gpu/drm: ingenic: add support for the jz4770
|
the lcd controller in the jz4770 supports up to 720p. while there has been many new features added since the old jz4740, which are not yet handled here, this driver still works fine.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for the jz4770
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ', 'ingenic']
|
['c']
| 1
| 7
| 0
|
--- diff --git a/drivers/gpu/drm/ingenic/ingenic-drm.c b/drivers/gpu/drm/ingenic/ingenic-drm.c --- a/drivers/gpu/drm/ingenic/ingenic-drm.c +++ b/drivers/gpu/drm/ingenic/ingenic-drm.c +static const struct jz_soc_info jz4770_soc_info = { + .needs_dev_clk = false, + .max_width = 1280, + .max_height = 720, +}; + + { .compatible = "ingenic,jz4770-lcd", .data = &jz4770_soc_info },
|
Graphics
|
d4e6a62d3769ef09bfe116b261a61ef871dea4f9
|
paul cercueil
|
drivers
|
gpu
|
drm, ingenic
|
drm/panel: add driver for sony acx424akp panel
|
the sony acx424akp is a command/videomode dsi panel for mobile devices. it is used on the st-ericsson href520 reference design. we support video mode by default, but it is possible to switch the panel into command mode by using the bool property "dsi-command-mode".
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add driver for sony acx424akp panel
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ']
|
['c', 'kconfig', 'makefile', 'maintainers']
| 4
| 568
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +drm driver for sony acx424akp panels +m: linus walleij <linus.walleij@linaro.org> +t: git git://anongit.freedesktop.org/drm/drm-misc +s: maintained +f: drivers/gpu/drm/panel/panel-sony-acx424akp.c + diff --git a/drivers/gpu/drm/panel/kconfig b/drivers/gpu/drm/panel/kconfig --- a/drivers/gpu/drm/panel/kconfig +++ b/drivers/gpu/drm/panel/kconfig +config drm_panel_sony_acx424akp + tristate "sony acx424akp dsi command mode panel" + depends on of + depends on drm_mipi_dsi + depends on backlight_class_device + select videomode_helpers + help + say y here if you want to enable the sony acx424 display + panel. this panel supports dsi in both command and video + mode. + diff --git a/drivers/gpu/drm/panel/makefile b/drivers/gpu/drm/panel/makefile --- a/drivers/gpu/drm/panel/makefile +++ b/drivers/gpu/drm/panel/makefile +obj-$(config_drm_panel_sony_acx424akp) += panel-sony-acx424akp.o diff --git a/drivers/gpu/drm/panel/panel-sony-acx424akp.c b/drivers/gpu/drm/panel/panel-sony-acx424akp.c --- /dev/null +++ b/drivers/gpu/drm/panel/panel-sony-acx424akp.c +// spdx-license-identifier: gpl-2.0+ +/* + * mipi-dsi sony acx424akp panel driver. this is a 480x864 + * amoled panel with a command-only dsi interface. + * + * copyright (c) linaro ltd. 2019 + * author: linus walleij + * based on code and know-how from marcus lorentzon + * copyright (c) st-ericsson sa 2010 + */ +#include <linux/backlight.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +#define acx424_dcs_read_id1 0xda +#define acx424_dcs_read_id2 0xdb +#define acx424_dcs_read_id3 0xdc +#define acx424_dcs_set_mddi 0xae + +/* + * sony seems to use vendor id 0x81 + */ +#define display_sony_acx424akp_id1 0x811b +#define display_sony_acx424akp_id2 0x811a +/* + * the third id looks like a bug, vendor ids begin at 0x80 + * and panel 00 ... seems like default values. + */ +#define display_sony_acx424akp_id3 0x8000 + +struct acx424akp { + struct drm_panel panel; + struct device *dev; + struct backlight_device *bl; + struct regulator *supply; + struct gpio_desc *reset_gpio; + bool video_mode; +}; + +static const struct drm_display_mode sony_acx424akp_vid_mode = { + .clock = 330000, + .hdisplay = 480, + .hsync_start = 480 + 15, + .hsync_end = 480 + 15 + 0, + .htotal = 480 + 15 + 0 + 15, + .vdisplay = 864, + .vsync_start = 864 + 14, + .vsync_end = 864 + 14 + 1, + .vtotal = 864 + 14 + 1 + 11, + .vrefresh = 60, + .width_mm = 48, + .height_mm = 84, + .flags = drm_mode_flag_pvsync, +}; + +/* + * the timings are not very helpful as the display is used in + * command mode using the maximum hs frequency. + */ +static const struct drm_display_mode sony_acx424akp_cmd_mode = { + .clock = 420160, + .hdisplay = 480, + .hsync_start = 480 + 154, + .hsync_end = 480 + 154 + 16, + .htotal = 480 + 154 + 16 + 32, + .vdisplay = 864, + .vsync_start = 864 + 1, + .vsync_end = 864 + 1 + 1, + .vtotal = 864 + 1 + 1 + 1, + /* + * some desired refresh rate, experiments at the maximum "pixel" + * clock speed (hs clock 420 mhz) yields around 117hz. + */ + .vrefresh = 60, + .width_mm = 48, + .height_mm = 84, +}; + +static inline struct acx424akp *panel_to_acx424akp(struct drm_panel *panel) +{ + return container_of(panel, struct acx424akp, panel); +} + +#define fosc 20 /* 20mhz */ +#define scale_factor_ns_div_mhz 1000 + +static int acx424akp_set_brightness(struct backlight_device *bl) +{ + struct acx424akp *acx = bl_get_data(bl); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(acx->dev); + int period_ns = 1023; + int duty_ns = bl->props.brightness; + u8 pwm_ratio; + u8 pwm_div; + u8 par; + int ret; + + /* calculate the pwm duty cycle in n/256's */ + pwm_ratio = max(((duty_ns * 256) / period_ns) - 1, 1); + pwm_div = max(1, + ((fosc * period_ns) / 256) / + scale_factor_ns_div_mhz); + + /* set up pwm dutycycle one byte (differs from the standard) */ + drm_dev_debug(acx->dev, "calculated duty cycle %02x ", pwm_ratio); + ret = mipi_dsi_dcs_write(dsi, mipi_dcs_set_display_brightness, + &pwm_ratio, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to set display pwm ratio (%d) ", + ret); + return ret; + } + + /* + * sequence to write pwmdiv: + * address data + * 0xf3 0xaa cmd2 unlock + * 0x00 0x01 enter cmd2 page 0 + * 0x7d 0x01 no reload mtp of cmd2 p1 + * 0x22 pwmdiv + * 0x7f 0xaa cmd2 page 1 lock + */ + par = 0xaa; + ret = mipi_dsi_dcs_write(dsi, 0xf3, &par, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to unlock cmd 2 (%d) ", + ret); + return ret; + } + par = 0x01; + ret = mipi_dsi_dcs_write(dsi, 0x00, &par, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to enter page 1 (%d) ", + ret); + return ret; + } + par = 0x01; + ret = mipi_dsi_dcs_write(dsi, 0x7d, &par, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to disable mtp reload (%d) ", + ret); + return ret; + } + ret = mipi_dsi_dcs_write(dsi, 0x22, &pwm_div, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to set pwm divisor (%d) ", + ret); + return ret; + } + par = 0xaa; + ret = mipi_dsi_dcs_write(dsi, 0x7f, &par, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to lock cmd 2 (%d) ", + ret); + return ret; + } + + /* enable backlight */ + par = 0x24; + ret = mipi_dsi_dcs_write(dsi, mipi_dcs_write_control_display, + &par, 1); + if (ret < 0) { + drm_dev_error(acx->dev, + "failed to enable display backlight (%d) ", + ret); + return ret; + } + + return 0; +} + +static const struct backlight_ops acx424akp_bl_ops = { + .update_status = acx424akp_set_brightness, +}; + +static int acx424akp_read_id(struct acx424akp *acx) +{ + struct mipi_dsi_device *dsi = to_mipi_dsi_device(acx->dev); + u8 vendor, version, panel; + u16 val; + int ret; + + ret = mipi_dsi_dcs_read(dsi, acx424_dcs_read_id1, &vendor, 1); + if (ret < 0) { + drm_dev_error(acx->dev, "could not vendor id byte "); + return ret; + } + ret = mipi_dsi_dcs_read(dsi, acx424_dcs_read_id2, &version, 1); + if (ret < 0) { + drm_dev_error(acx->dev, "could not read device version byte "); + return ret; + } + ret = mipi_dsi_dcs_read(dsi, acx424_dcs_read_id3, &panel, 1); + if (ret < 0) { + drm_dev_error(acx->dev, "could not read panel id byte "); + return ret; + } + + if (vendor == 0x00) { + drm_dev_error(acx->dev, "device vendor id is zero "); + return -enodev; + } + + val = (vendor << 8) | panel; + switch (val) { + case display_sony_acx424akp_id1: + case display_sony_acx424akp_id2: + case display_sony_acx424akp_id3: + drm_dev_info(acx->dev, + "mtp vendor: %02x, version: %02x, panel: %02x ", + vendor, version, panel); + break; + default: + drm_dev_info(acx->dev, + "unknown vendor: %02x, version: %02x, panel: %02x ", + vendor, version, panel); + break; + } + + return 0; +} + +static int acx424akp_power_on(struct acx424akp *acx) +{ + int ret; + + ret = regulator_enable(acx->supply); + if (ret) { + drm_dev_error(acx->dev, "failed to enable supply (%d) ", ret); + return ret; + } + + /* assert reset */ + gpiod_set_value_cansleep(acx->reset_gpio, 1); + udelay(20); + /* de-assert reset */ + gpiod_set_value_cansleep(acx->reset_gpio, 0); + usleep_range(11000, 20000); + + return 0; +} + +static void acx424akp_power_off(struct acx424akp *acx) +{ + /* assert reset */ + gpiod_set_value_cansleep(acx->reset_gpio, 1); + usleep_range(11000, 20000); + + regulator_disable(acx->supply); +} + +static int acx424akp_prepare(struct drm_panel *panel) +{ + struct acx424akp *acx = panel_to_acx424akp(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(acx->dev); + const u8 mddi = 3; + int ret; + + ret = acx424akp_power_on(acx); + if (ret) + return ret; + + ret = acx424akp_read_id(acx); + if (ret) { + drm_dev_error(acx->dev, "failed to read panel id (%d) ", ret); + goto err_power_off; + } + + /* enabe tearing mode: send te (tearing effect) at vblank */ + ret = mipi_dsi_dcs_set_tear_on(dsi, + mipi_dsi_dcs_tear_mode_vblank); + if (ret) { + drm_dev_error(acx->dev, "failed to enable vblank te (%d) ", + ret); + goto err_power_off; + } + + /* + * set mddi + * + * this presumably deactivates the qualcomm mddi interface and + * selects dsi, similar code is found in other drivers such as the + * sharp ls043t1le01 which makes us suspect that this panel may be + * using a novatek nt35565 or similar display driver chip that shares + * this command. due to the lack of documentation we cannot know for + * sure. + */ + ret = mipi_dsi_dcs_write(dsi, acx424_dcs_set_mddi, + &mddi, sizeof(mddi)); + if (ret < 0) { + drm_dev_error(acx->dev, "failed to set mddi (%d) ", ret); + goto err_power_off; + } + + /* exit sleep mode */ + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret) { + drm_dev_error(acx->dev, "failed to exit sleep mode (%d) ", + ret); + goto err_power_off; + } + msleep(140); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret) { + drm_dev_error(acx->dev, "failed to turn display on (%d) ", + ret); + goto err_power_off; + } + if (acx->video_mode) { + /* in video mode turn peripheral on */ + ret = mipi_dsi_turn_on_peripheral(dsi); + if (ret) { + dev_err(acx->dev, "failed to turn on peripheral "); + goto err_power_off; + } + } + + acx->bl->props.power = fb_blank_normal; + + return 0; + +err_power_off: + acx424akp_power_off(acx); + return ret; +} + +static int acx424akp_unprepare(struct drm_panel *panel) +{ + struct acx424akp *acx = panel_to_acx424akp(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(acx->dev); + u8 par; + int ret; + + /* disable backlight */ + par = 0x00; + ret = mipi_dsi_dcs_write(dsi, mipi_dcs_write_control_display, + &par, 1); + if (ret) { + drm_dev_error(acx->dev, + "failed to disable display backlight (%d) ", + ret); + return ret; + } + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret) { + drm_dev_error(acx->dev, "failed to turn display off (%d) ", + ret); + return ret; + } + + /* enter sleep mode */ + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret) { + drm_dev_error(acx->dev, "failed to enter sleep mode (%d) ", + ret); + return ret; + } + msleep(85); + + acx424akp_power_off(acx); + acx->bl->props.power = fb_blank_powerdown; + + return 0; +} + +static int acx424akp_enable(struct drm_panel *panel) +{ + struct acx424akp *acx = panel_to_acx424akp(panel); + + /* + * the backlight is on as long as the display is on + * so no use to call backlight_enable() here. + */ + acx->bl->props.power = fb_blank_unblank; + + return 0; +} + +static int acx424akp_disable(struct drm_panel *panel) +{ + struct acx424akp *acx = panel_to_acx424akp(panel); + + /* + * the backlight is on as long as the display is on + * so no use to call backlight_disable() here. + */ + acx->bl->props.power = fb_blank_normal; + + return 0; +} + +static int acx424akp_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct acx424akp *acx = panel_to_acx424akp(panel); + struct drm_display_mode *mode; + + if (acx->video_mode) + mode = drm_mode_duplicate(connector->dev, + &sony_acx424akp_vid_mode); + else + mode = drm_mode_duplicate(connector->dev, + &sony_acx424akp_cmd_mode); + if (!mode) { + drm_error("bad mode or failed to add mode "); + return -einval; + } + drm_mode_set_name(mode); + mode->type = drm_mode_type_driver | drm_mode_type_preferred; + + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + + drm_mode_probed_add(connector, mode); + + return 1; /* number of modes */ +} + +static const struct drm_panel_funcs acx424akp_drm_funcs = { + .disable = acx424akp_disable, + .unprepare = acx424akp_unprepare, + .prepare = acx424akp_prepare, + .enable = acx424akp_enable, + .get_modes = acx424akp_get_modes, +}; + +static int acx424akp_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct acx424akp *acx; + int ret; + + acx = devm_kzalloc(dev, sizeof(struct acx424akp), gfp_kernel); + if (!acx) + return -enomem; + acx->video_mode = of_property_read_bool(dev->of_node, + "enforce-video-mode"); + + mipi_dsi_set_drvdata(dsi, acx); + acx->dev = dev; + + dsi->lanes = 2; + dsi->format = mipi_dsi_fmt_rgb888; + /* + * fixme: these come from the st-ericsson vendor driver for the + * href520 and seems to reflect limitations in the plls on that + * platform, if you have the datasheet, please cross-check the + * actual max rates. + */ + dsi->lp_rate = 19200000; + dsi->hs_rate = 420160000; + + if (acx->video_mode) + /* burst mode using event for sync */ + dsi->mode_flags = + mipi_dsi_mode_video | + mipi_dsi_mode_video_burst; + else + dsi->mode_flags = + mipi_dsi_clock_non_continuous | + mipi_dsi_mode_eot_packet; + + acx->supply = devm_regulator_get(dev, "vddi"); + if (is_err(acx->supply)) + return ptr_err(acx->supply); + + /* this asserts reset by default */ + acx->reset_gpio = devm_gpiod_get_optional(dev, "reset", + gpiod_out_high); + if (is_err(acx->reset_gpio)) { + ret = ptr_err(acx->reset_gpio); + if (ret != -eprobe_defer) + drm_dev_error(dev, "failed to request gpio (%d) ", + ret); + return ret; + } + + drm_panel_init(&acx->panel, dev, &acx424akp_drm_funcs, + drm_mode_connector_dsi); + + acx->bl = devm_backlight_device_register(dev, "acx424akp", dev, acx, + &acx424akp_bl_ops, null); + if (is_err(acx->bl)) { + drm_dev_error(dev, "failed to register backlight device "); + return ptr_err(acx->bl); + } + acx->bl->props.max_brightness = 1023; + acx->bl->props.brightness = 512; + acx->bl->props.power = fb_blank_powerdown; + + ret = drm_panel_add(&acx->panel); + if (ret < 0) + return ret; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_panel_remove(&acx->panel); + return ret; + } + + return 0; +} + +static int acx424akp_remove(struct mipi_dsi_device *dsi) +{ + struct acx424akp *acx = mipi_dsi_get_drvdata(dsi); + + mipi_dsi_detach(dsi); + drm_panel_remove(&acx->panel); + + return 0; +} + +static const struct of_device_id acx424akp_of_match[] = { + { .compatible = "sony,acx424akp" }, + { /* sentinel */ } +}; +module_device_table(of, acx424akp_of_match); + +static struct mipi_dsi_driver acx424akp_driver = { + .probe = acx424akp_probe, + .remove = acx424akp_remove, + .driver = { + .name = "panel-sony-acx424akp", + .of_match_table = acx424akp_of_match, + }, +}; +module_mipi_dsi_driver(acx424akp_driver); + +module_author("linus wallei <linus.walleij@linaro.org>"); +module_description("mipi-dsi sony acx424akp panel driver"); +module_license("gpl v2");
|
Graphics
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8152c2bfd780398773435bf6eb1e3841f83de209
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linus walleij
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drivers
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gpu
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drm, panel
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drm/panel: add panel driver for leadtek ltk500hd1829
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the ltk500hd1829 is 5.5" dsi display.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add panel driver for leadtek ltk500hd1829
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['panel ']
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['c', 'kconfig', 'makefile']
| 3
| 543
| 0
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- fix some trivial checkpatch warnings while applying (sam) - drop error message if backlight not found, no other panel - drop one more overlooked panel->drm access --- diff --git a/drivers/gpu/drm/panel/kconfig b/drivers/gpu/drm/panel/kconfig --- a/drivers/gpu/drm/panel/kconfig +++ b/drivers/gpu/drm/panel/kconfig +config drm_panel_leadtek_ltk500hd1829 + tristate "leadtek ltk500hd1829 panel" + depends on of + depends on drm_mipi_dsi + depends on backlight_class_device + help + say y here if you want to enable support for kingdisplay kd097d04 + tft-lcd modules. the panel has a 1536x2048 resolution and uses + 24 bit rgb per pixel. it provides a mipi dsi interface to + the host and has a built-in led backlight. + diff --git a/drivers/gpu/drm/panel/makefile b/drivers/gpu/drm/panel/makefile --- a/drivers/gpu/drm/panel/makefile +++ b/drivers/gpu/drm/panel/makefile +obj-$(config_drm_panel_leadtek_ltk500hd1829) += panel-leadtek-ltk500hd1829.o diff --git a/drivers/gpu/drm/panel/panel-leadtek-ltk500hd1829.c b/drivers/gpu/drm/panel/panel-leadtek-ltk500hd1829.c --- /dev/null +++ b/drivers/gpu/drm/panel/panel-leadtek-ltk500hd1829.c +// spdx-license-identifier: gpl-2.0+ +/* + * copyright (c) 2019 theobroma systems design und consulting gmbh + * + * base on panel-kingdisplay-kd097d04.c + * copyright (c) 2017, fuzhou rockchip electronics co., ltd + */ + +#include <linux/backlight.h> +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> + +#include <video/mipi_display.h> + +#include <drm/drm_crtc.h> +#include <drm/drm_device.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +struct ltk500hd1829 { + struct device *dev; + struct drm_panel panel; + struct gpio_desc *reset_gpio; + struct regulator *vcc; + struct regulator *iovcc; + bool prepared; +}; + +struct ltk500hd1829_cmd { + char cmd; + char data; +}; + +/* + * there is no description in the reference manual about these commands. + * we received them from the vendor, so just use them as is. + */ +static const struct ltk500hd1829_cmd init_code[] = { + { 0xe0, 0x00 }, + { 0xe1, 0x93 }, + { 0xe2, 0x65 }, + { 0xe3, 0xf8 }, + { 0x80, 0x03 }, + { 0xe0, 0x04 }, + { 0x2d, 0x03 }, + { 0xe0, 0x01 }, + { 0x00, 0x00 }, + { 0x01, 0xb6 }, + { 0x03, 0x00 }, + { 0x04, 0xc5 }, + { 0x17, 0x00 }, + { 0x18, 0xbf }, + { 0x19, 0x01 }, + { 0x1a, 0x00 }, + { 0x1b, 0xbf }, + { 0x1c, 0x01 }, + { 0x1f, 0x7c }, + { 0x20, 0x26 }, + { 0x21, 0x26 }, + { 0x22, 0x4e }, + { 0x37, 0x09 }, + { 0x38, 0x04 }, + { 0x39, 0x08 }, + { 0x3a, 0x1f }, + { 0x3b, 0x1f }, + { 0x3c, 0x78 }, + { 0x3d, 0xff }, + { 0x3e, 0xff }, + { 0x3f, 0x00 }, + { 0x40, 0x04 }, + { 0x41, 0xa0 }, + { 0x43, 0x0f }, + { 0x44, 0x0a }, + { 0x45, 0x24 }, + { 0x55, 0x01 }, + { 0x56, 0x01 }, + { 0x57, 0xa5 }, + { 0x58, 0x0a }, + { 0x59, 0x4a }, + { 0x5a, 0x38 }, + { 0x5b, 0x10 }, + { 0x5c, 0x19 }, + { 0x5d, 0x7c }, + { 0x5e, 0x64 }, + { 0x5f, 0x54 }, + { 0x60, 0x48 }, + { 0x61, 0x44 }, + { 0x62, 0x35 }, + { 0x63, 0x3a }, + { 0x64, 0x24 }, + { 0x65, 0x3b }, + { 0x66, 0x39 }, + { 0x67, 0x37 }, + { 0x68, 0x56 }, + { 0x69, 0x41 }, + { 0x6a, 0x47 }, + { 0x6b, 0x2f }, + { 0x6c, 0x23 }, + { 0x6d, 0x13 }, + { 0x6e, 0x02 }, + { 0x6f, 0x08 }, + { 0x70, 0x7c }, + { 0x71, 0x64 }, + { 0x72, 0x54 }, + { 0x73, 0x48 }, + { 0x74, 0x44 }, + { 0x75, 0x35 }, + { 0x76, 0x3a }, + { 0x77, 0x22 }, + { 0x78, 0x3b }, + { 0x79, 0x39 }, + { 0x7a, 0x38 }, + { 0x7b, 0x52 }, + { 0x7c, 0x41 }, + { 0x7d, 0x47 }, + { 0x7e, 0x2f }, + { 0x7f, 0x23 }, + { 0x80, 0x13 }, + { 0x81, 0x02 }, + { 0x82, 0x08 }, + { 0xe0, 0x02 }, + { 0x00, 0x57 }, + { 0x01, 0x77 }, + { 0x02, 0x44 }, + { 0x03, 0x46 }, + { 0x04, 0x48 }, + { 0x05, 0x4a }, + { 0x06, 0x4c }, + { 0x07, 0x4e }, + { 0x08, 0x50 }, + { 0x09, 0x55 }, + { 0x0a, 0x52 }, + { 0x0b, 0x55 }, + { 0x0c, 0x55 }, + { 0x0d, 0x55 }, + { 0x0e, 0x55 }, + { 0x0f, 0x55 }, + { 0x10, 0x55 }, + { 0x11, 0x55 }, + { 0x12, 0x55 }, + { 0x13, 0x40 }, + { 0x14, 0x55 }, + { 0x15, 0x55 }, + { 0x16, 0x57 }, + { 0x17, 0x77 }, + { 0x18, 0x45 }, + { 0x19, 0x47 }, + { 0x1a, 0x49 }, + { 0x1b, 0x4b }, + { 0x1c, 0x4d }, + { 0x1d, 0x4f }, + { 0x1e, 0x51 }, + { 0x1f, 0x55 }, + { 0x20, 0x53 }, + { 0x21, 0x55 }, + { 0x22, 0x55 }, + { 0x23, 0x55 }, + { 0x24, 0x55 }, + { 0x25, 0x55 }, + { 0x26, 0x55 }, + { 0x27, 0x55 }, + { 0x28, 0x55 }, + { 0x29, 0x41 }, + { 0x2a, 0x55 }, + { 0x2b, 0x55 }, + { 0x2c, 0x57 }, + { 0x2d, 0x77 }, + { 0x2e, 0x4f }, + { 0x2f, 0x4d }, + { 0x30, 0x4b }, + { 0x31, 0x49 }, + { 0x32, 0x47 }, + { 0x33, 0x45 }, + { 0x34, 0x41 }, + { 0x35, 0x55 }, + { 0x36, 0x53 }, + { 0x37, 0x55 }, + { 0x38, 0x55 }, + { 0x39, 0x55 }, + { 0x3a, 0x55 }, + { 0x3b, 0x55 }, + { 0x3c, 0x55 }, + { 0x3d, 0x55 }, + { 0x3e, 0x55 }, + { 0x3f, 0x51 }, + { 0x40, 0x55 }, + { 0x41, 0x55 }, + { 0x42, 0x57 }, + { 0x43, 0x77 }, + { 0x44, 0x4e }, + { 0x45, 0x4c }, + { 0x46, 0x4a }, + { 0x47, 0x48 }, + { 0x48, 0x46 }, + { 0x49, 0x44 }, + { 0x4a, 0x40 }, + { 0x4b, 0x55 }, + { 0x4c, 0x52 }, + { 0x4d, 0x55 }, + { 0x4e, 0x55 }, + { 0x4f, 0x55 }, + { 0x50, 0x55 }, + { 0x51, 0x55 }, + { 0x52, 0x55 }, + { 0x53, 0x55 }, + { 0x54, 0x55 }, + { 0x55, 0x50 }, + { 0x56, 0x55 }, + { 0x57, 0x55 }, + { 0x58, 0x40 }, + { 0x59, 0x00 }, + { 0x5a, 0x00 }, + { 0x5b, 0x10 }, + { 0x5c, 0x09 }, + { 0x5d, 0x30 }, + { 0x5e, 0x01 }, + { 0x5f, 0x02 }, + { 0x60, 0x30 }, + { 0x61, 0x03 }, + { 0x62, 0x04 }, + { 0x63, 0x06 }, + { 0x64, 0x6a }, + { 0x65, 0x75 }, + { 0x66, 0x0f }, + { 0x67, 0xb3 }, + { 0x68, 0x0b }, + { 0x69, 0x06 }, + { 0x6a, 0x6a }, + { 0x6b, 0x10 }, + { 0x6c, 0x00 }, + { 0x6d, 0x04 }, + { 0x6e, 0x04 }, + { 0x6f, 0x88 }, + { 0x70, 0x00 }, + { 0x71, 0x00 }, + { 0x72, 0x06 }, + { 0x73, 0x7b }, + { 0x74, 0x00 }, + { 0x75, 0xbc }, + { 0x76, 0x00 }, + { 0x77, 0x05 }, + { 0x78, 0x2e }, + { 0x79, 0x00 }, + { 0x7a, 0x00 }, + { 0x7b, 0x00 }, + { 0x7c, 0x00 }, + { 0x7d, 0x03 }, + { 0x7e, 0x7b }, + { 0xe0, 0x04 }, + { 0x09, 0x10 }, + { 0x2b, 0x2b }, + { 0x2e, 0x44 }, + { 0xe0, 0x00 }, + { 0xe6, 0x02 }, + { 0xe7, 0x02 }, + { 0x35, 0x00 }, +}; + +static inline +struct ltk500hd1829 *panel_to_ltk500hd1829(struct drm_panel *panel) +{ + return container_of(panel, struct ltk500hd1829, panel); +} + +static int ltk500hd1829_unprepare(struct drm_panel *panel) +{ + struct ltk500hd1829 *ctx = panel_to_ltk500hd1829(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int ret; + + if (!ctx->prepared) + return 0; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) + drm_dev_error(panel->dev, "failed to set display off: %d ", + ret); + + ret = mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + drm_dev_error(panel->dev, "failed to enter sleep mode: %d ", + ret); + } + + /* 120ms to enter sleep mode */ + msleep(120); + + regulator_disable(ctx->iovcc); + regulator_disable(ctx->vcc); + + ctx->prepared = false; + + return 0; +} + +static int ltk500hd1829_prepare(struct drm_panel *panel) +{ + struct ltk500hd1829 *ctx = panel_to_ltk500hd1829(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + unsigned int i; + int ret; + + if (ctx->prepared) + return 0; + + ret = regulator_enable(ctx->vcc); + if (ret < 0) { + drm_dev_error(ctx->dev, + "failed to enable vci supply: %d ", ret); + return ret; + } + ret = regulator_enable(ctx->iovcc); + if (ret < 0) { + drm_dev_error(ctx->dev, + "failed to enable iovcc supply: %d ", ret); + goto disable_vcc; + } + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + /* trw: 10us */ + usleep_range(10, 20); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + + /* trt: >= 5ms */ + usleep_range(5000, 6000); + + for (i = 0; i < array_size(init_code); i++) { + ret = mipi_dsi_generic_write(dsi, &init_code[i], + sizeof(struct ltk500hd1829_cmd)); + if (ret < 0) { + drm_dev_error(panel->dev, + "failed to write init cmds: %d ", ret); + goto disable_iovcc; + } + } + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + drm_dev_error(panel->dev, "failed to exit sleep mode: %d ", + ret); + goto disable_iovcc; + } + + /* 120ms to exit sleep mode */ + msleep(120); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + drm_dev_error(panel->dev, "failed to set display on: %d ", + ret); + goto disable_iovcc; + } + + ctx->prepared = true; + + return 0; + +disable_iovcc: + regulator_disable(ctx->iovcc); +disable_vcc: + regulator_disable(ctx->vcc); + return ret; +} + +static const struct drm_display_mode default_mode = { + .hdisplay = 720, + .hsync_start = 720 + 50, + .hsync_end = 720 + 50 + 50, + .htotal = 720 + 50 + 50 + 50, + .vdisplay = 1280, + .vsync_start = 1280 + 30, + .vsync_end = 1280 + 30 + 4, + .vtotal = 1280 + 30 + 4 + 12, + .vrefresh = 60, + .clock = 41600, + .width_mm = 62, + .height_mm = 110, +}; + +static int ltk500hd1829_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct ltk500hd1829 *ctx = panel_to_ltk500hd1829(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &default_mode); + if (!mode) { + drm_dev_error(ctx->dev, "failed to add mode %ux%ux@%u ", + default_mode.hdisplay, default_mode.vdisplay, + default_mode.vrefresh); + return -enomem; + } + + drm_mode_set_name(mode); + + mode->type = drm_mode_type_driver | drm_mode_type_preferred; + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_panel_funcs ltk500hd1829_funcs = { + .unprepare = ltk500hd1829_unprepare, + .prepare = ltk500hd1829_prepare, + .get_modes = ltk500hd1829_get_modes, +}; + +static int ltk500hd1829_probe(struct mipi_dsi_device *dsi) +{ + struct ltk500hd1829 *ctx; + struct device *dev = &dsi->dev; + int ret; + + ctx = devm_kzalloc(&dsi->dev, sizeof(*ctx), gfp_kernel); + if (!ctx) + return -enomem; + + ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", gpiod_out_low); + if (is_err(ctx->reset_gpio)) { + drm_dev_error(dev, "cannot get reset gpio "); + return ptr_err(ctx->reset_gpio); + } + + ctx->vcc = devm_regulator_get(dev, "vcc"); + if (is_err(ctx->vcc)) { + ret = ptr_err(ctx->vcc); + if (ret != -eprobe_defer) + drm_dev_error(dev, + "failed to request vcc regulator: %d ", + ret); + return ret; + } + + ctx->iovcc = devm_regulator_get(dev, "iovcc"); + if (is_err(ctx->iovcc)) { + ret = ptr_err(ctx->iovcc); + if (ret != -eprobe_defer) + drm_dev_error(dev, + "failed to request iovcc regulator: %d ", + ret); + return ret; + } + + mipi_dsi_set_drvdata(dsi, ctx); + + ctx->dev = dev; + + dsi->lanes = 4; + dsi->format = mipi_dsi_fmt_rgb888; + dsi->mode_flags = mipi_dsi_mode_video | mipi_dsi_mode_video_burst | + mipi_dsi_mode_lpm | mipi_dsi_mode_eot_packet; + + drm_panel_init(&ctx->panel, &dsi->dev, <k500hd1829_funcs, + drm_mode_connector_dsi); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_dev_error(dev, "mipi_dsi_attach failed: %d ", ret); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void ltk500hd1829_shutdown(struct mipi_dsi_device *dsi) +{ + struct ltk500hd1829 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = drm_panel_unprepare(&ctx->panel); + if (ret < 0) + drm_dev_error(&dsi->dev, "failed to unprepare panel: %d ", + ret); + + ret = drm_panel_disable(&ctx->panel); + if (ret < 0) + drm_dev_error(&dsi->dev, "failed to disable panel: %d ", + ret); +} + +static int ltk500hd1829_remove(struct mipi_dsi_device *dsi) +{ + struct ltk500hd1829 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ltk500hd1829_shutdown(dsi); + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + drm_dev_error(&dsi->dev, "failed to detach from dsi host: %d ", + ret); + + drm_panel_remove(&ctx->panel); + + return 0; +} + +static const struct of_device_id ltk500hd1829_of_match[] = { + { .compatible = "leadtek,ltk500hd1829", }, + { /* sentinel */ } +}; +module_device_table(of, ltk500hd1829_of_match); + +static struct mipi_dsi_driver ltk500hd1829_driver = { + .driver = { + .name = "panel-leadtek-ltk500hd1829", + .of_match_table = ltk500hd1829_of_match, + }, + .probe = ltk500hd1829_probe, + .remove = ltk500hd1829_remove, + .shutdown = ltk500hd1829_shutdown, +}; +module_mipi_dsi_driver(ltk500hd1829_driver); + +module_author("heiko stuebner <heiko.stuebner@theobroma-systems.com>"); +module_description("leadtek ltk500hd1829 panel driver"); +module_license("gpl v2");
|
Graphics
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e98910bee6097b7c0f7beb76ab1d70ee52931d40
|
heiko stuebner
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drivers
|
gpu
|
drm, panel
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drm/panel: add panel driver for xinpeng xpp055c272 panels
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base on the somewhat similar rocktech driver but adapted for panel-specific init of the xpp055c272.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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xinpeng xpp055c272
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['panel ']
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['c', 'kconfig', 'makefile']
| 3
| 409
| 0
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- drop error message when backlight not found, no other panel - remove wrong negative sync flags from display-mode to fix a display - move to drm-panel-internal backlight handling (sam) - adapt to changes that happened to drm_panel structs+functions (sam) - sort includes (sam) - drop unnecessary drv_name constant (sam) - do mipi_dsi_dcs_exit_sleep_mode and mipi_dsi_dcs_set_display_on --- diff --git a/drivers/gpu/drm/panel/kconfig b/drivers/gpu/drm/panel/kconfig --- a/drivers/gpu/drm/panel/kconfig +++ b/drivers/gpu/drm/panel/kconfig + +config drm_panel_xinpeng_xpp055c272 + tristate "xinpeng xpp055c272 panel driver" + depends on of + depends on drm_mipi_dsi + depends on backlight_class_device + help + say y here if you want to enable support for the xinpeng + xpp055c272 controller for 720x1280 lcd panels with mipi/rgb/spi + system interfaces. diff --git a/drivers/gpu/drm/panel/makefile b/drivers/gpu/drm/panel/makefile --- a/drivers/gpu/drm/panel/makefile +++ b/drivers/gpu/drm/panel/makefile +obj-$(config_drm_panel_xinpeng_xpp055c272) += panel-xinpeng-xpp055c272.o diff --git a/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c b/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c --- /dev/null +++ b/drivers/gpu/drm/panel/panel-xinpeng-xpp055c272.c +// spdx-license-identifier: gpl-2.0 +/* + * xinpeng xpp055c272 5.5" mipi-dsi panel driver + * copyright (c) 2019 theobroma systems design und consulting gmbh + * + * based on + * + * rockteck jh057n00900 5.5" mipi-dsi panel driver + * copyright (c) purism spc 2019 + */ + +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +#include <video/display_timing.h> +#include <video/mipi_display.h> + +#include <linux/delay.h> +#include <linux/gpio/consumer.h> +#include <linux/media-bus-format.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> + +/* manufacturer specific commands send via dsi */ +#define xpp055c272_cmd_all_pixel_off 0x22 +#define xpp055c272_cmd_all_pixel_on 0x23 +#define xpp055c272_cmd_setdisp 0xb2 +#define xpp055c272_cmd_setrgbif 0xb3 +#define xpp055c272_cmd_setcyc 0xb4 +#define xpp055c272_cmd_setbgp 0xb5 +#define xpp055c272_cmd_setvcom 0xb6 +#define xpp055c272_cmd_setotp 0xb7 +#define xpp055c272_cmd_setpower_ext 0xb8 +#define xpp055c272_cmd_setextc 0xb9 +#define xpp055c272_cmd_setmipi 0xba +#define xpp055c272_cmd_setvdc 0xbc +#define xpp055c272_cmd_setpcr 0xbf +#define xpp055c272_cmd_setscr 0xc0 +#define xpp055c272_cmd_setpower 0xc1 +#define xpp055c272_cmd_seteco 0xc6 +#define xpp055c272_cmd_setpanel 0xcc +#define xpp055c272_cmd_setgamma 0xe0 +#define xpp055c272_cmd_seteq 0xe3 +#define xpp055c272_cmd_setgip1 0xe9 +#define xpp055c272_cmd_setgip2 0xea + +struct xpp055c272 { + struct device *dev; + struct drm_panel panel; + struct gpio_desc *reset_gpio; + struct regulator *vci; + struct regulator *iovcc; + bool prepared; +}; + +static inline struct xpp055c272 *panel_to_xpp055c272(struct drm_panel *panel) +{ + return container_of(panel, struct xpp055c272, panel); +} + +#define dsi_generic_write_seq(dsi, cmd, seq...) do { \ + static const u8 d[] = { seq }; \ + int ret; \ + ret = mipi_dsi_dcs_write(dsi, cmd, d, array_size(d)); \ + if (ret < 0) \ + return ret; \ + } while (0) + +static int xpp055c272_init_sequence(struct xpp055c272 *ctx) +{ + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + struct device *dev = ctx->dev; + + /* + * init sequence was supplied by the panel vendor without much + * documentation. + */ + dsi_generic_write_seq(dsi, xpp055c272_cmd_setextc, 0xf1, 0x12, 0x83); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setmipi, + 0x33, 0x81, 0x05, 0xf9, 0x0e, 0x0e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x25, + 0x00, 0x91, 0x0a, 0x00, 0x00, 0x02, 0x4f, 0x01, + 0x00, 0x00, 0x37); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setpower_ext, 0x25); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setpcr, 0x02, 0x11, 0x00); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setrgbif, + 0x0c, 0x10, 0x0a, 0x50, 0x03, 0xff, 0x00, 0x00, + 0x00, 0x00); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setscr, + 0x73, 0x73, 0x50, 0x50, 0x00, 0x00, 0x08, 0x70, + 0x00); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setvdc, 0x46); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setpanel, 0x0b); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setcyc, 0x80); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setdisp, 0xc8, 0x12, 0x30); + dsi_generic_write_seq(dsi, xpp055c272_cmd_seteq, + 0x07, 0x07, 0x0b, 0x0b, 0x03, 0x0b, 0x00, 0x00, + 0x00, 0x00, 0xff, 0x00, 0xc0, 0x10); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setpower, + 0x53, 0x00, 0x1e, 0x1e, 0x77, 0xe1, 0xcc, 0xdd, + 0x67, 0x77, 0x33, 0x33); + dsi_generic_write_seq(dsi, xpp055c272_cmd_seteco, 0x00, 0x00, 0xff, + 0xff, 0x01, 0xff); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setbgp, 0x09, 0x09); + msleep(20); + + dsi_generic_write_seq(dsi, xpp055c272_cmd_setvcom, 0x87, 0x95); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setgip1, + 0xc2, 0x10, 0x05, 0x05, 0x10, 0x05, 0xa0, 0x12, + 0x31, 0x23, 0x3f, 0x81, 0x0a, 0xa0, 0x37, 0x18, + 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x01, 0x00, 0x00, 0x00, 0x48, 0xf8, 0x86, 0x42, + 0x08, 0x88, 0x88, 0x80, 0x88, 0x88, 0x88, 0x58, + 0xf8, 0x87, 0x53, 0x18, 0x88, 0x88, 0x81, 0x88, + 0x88, 0x88, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setgip2, + 0x00, 0x1a, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x1f, 0x88, 0x81, 0x35, + 0x78, 0x88, 0x88, 0x85, 0x88, 0x88, 0x88, 0x0f, + 0x88, 0x80, 0x24, 0x68, 0x88, 0x88, 0x84, 0x88, + 0x88, 0x88, 0x23, 0x10, 0x00, 0x00, 0x1c, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x05, + 0xa0, 0x00, 0x00, 0x00, 0x00); + dsi_generic_write_seq(dsi, xpp055c272_cmd_setgamma, + 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, 0x36, + 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, 0x11, + 0x18, 0x00, 0x06, 0x08, 0x2a, 0x31, 0x3f, 0x38, + 0x36, 0x07, 0x0c, 0x0d, 0x11, 0x13, 0x12, 0x13, + 0x11, 0x18); + + msleep(60); + + drm_dev_debug_driver(dev, "panel init sequence done "); + return 0; +} + +static int xpp055c272_unprepare(struct drm_panel *panel) +{ + struct xpp055c272 *ctx = panel_to_xpp055c272(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int ret; + + if (!ctx->prepared) + return 0; + + ret = mipi_dsi_dcs_set_display_off(dsi); + if (ret < 0) + drm_dev_error(ctx->dev, "failed to set display off: %d ", + ret); + + mipi_dsi_dcs_enter_sleep_mode(dsi); + if (ret < 0) { + drm_dev_error(ctx->dev, "failed to enter sleep mode: %d ", + ret); + return ret; + } + + regulator_disable(ctx->iovcc); + regulator_disable(ctx->vci); + + ctx->prepared = false; + + return 0; +} + +static int xpp055c272_prepare(struct drm_panel *panel) +{ + struct xpp055c272 *ctx = panel_to_xpp055c272(panel); + struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); + int ret; + + if (ctx->prepared) + return 0; + + drm_dev_debug_driver(ctx->dev, "resetting the panel "); + ret = regulator_enable(ctx->vci); + if (ret < 0) { + drm_dev_error(ctx->dev, + "failed to enable vci supply: %d ", ret); + return ret; + } + ret = regulator_enable(ctx->iovcc); + if (ret < 0) { + drm_dev_error(ctx->dev, + "failed to enable iovcc supply: %d ", ret); + goto disable_vci; + } + + gpiod_set_value_cansleep(ctx->reset_gpio, 1); + /* t6: 10us */ + usleep_range(10, 20); + gpiod_set_value_cansleep(ctx->reset_gpio, 0); + + /* t8: 20ms */ + msleep(20); + + ret = xpp055c272_init_sequence(ctx); + if (ret < 0) { + drm_dev_error(ctx->dev, "panel init sequence failed: %d ", + ret); + goto disable_iovcc; + } + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + drm_dev_error(ctx->dev, "failed to exit sleep mode: %d ", ret); + goto disable_iovcc; + } + + /* t9: 120ms */ + msleep(120); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + drm_dev_error(ctx->dev, "failed to set display on: %d ", ret); + goto disable_iovcc; + } + + msleep(50); + + ctx->prepared = true; + + return 0; + +disable_iovcc: + regulator_disable(ctx->iovcc); +disable_vci: + regulator_disable(ctx->vci); + return ret; +} + +static const struct drm_display_mode default_mode = { + .hdisplay = 720, + .hsync_start = 720 + 40, + .hsync_end = 720 + 40 + 10, + .htotal = 720 + 40 + 10 + 40, + .vdisplay = 1280, + .vsync_start = 1280 + 22, + .vsync_end = 1280 + 22 + 4, + .vtotal = 1280 + 22 + 4 + 11, + .vrefresh = 60, + .clock = 64000, + .width_mm = 68, + .height_mm = 121, +}; + +static int xpp055c272_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct xpp055c272 *ctx = panel_to_xpp055c272(panel); + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, &default_mode); + if (!mode) { + drm_dev_error(ctx->dev, "failed to add mode %ux%u@%u ", + default_mode.hdisplay, default_mode.vdisplay, + default_mode.vrefresh); + return -enomem; + } + + drm_mode_set_name(mode); + + mode->type = drm_mode_type_driver | drm_mode_type_preferred; + connector->display_info.width_mm = mode->width_mm; + connector->display_info.height_mm = mode->height_mm; + drm_mode_probed_add(connector, mode); + + return 1; +} + +static const struct drm_panel_funcs xpp055c272_funcs = { + .unprepare = xpp055c272_unprepare, + .prepare = xpp055c272_prepare, + .get_modes = xpp055c272_get_modes, +}; + +static int xpp055c272_probe(struct mipi_dsi_device *dsi) +{ + struct device *dev = &dsi->dev; + struct xpp055c272 *ctx; + int ret; + + ctx = devm_kzalloc(dev, sizeof(*ctx), gfp_kernel); + if (!ctx) + return -enomem; + + ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", gpiod_out_low); + if (is_err(ctx->reset_gpio)) { + drm_dev_error(dev, "cannot get reset gpio "); + return ptr_err(ctx->reset_gpio); + } + + ctx->vci = devm_regulator_get(dev, "vci"); + if (is_err(ctx->vci)) { + ret = ptr_err(ctx->vci); + if (ret != -eprobe_defer) + drm_dev_error(dev, + "failed to request vci regulator: %d ", + ret); + return ret; + } + + ctx->iovcc = devm_regulator_get(dev, "iovcc"); + if (is_err(ctx->iovcc)) { + ret = ptr_err(ctx->iovcc); + if (ret != -eprobe_defer) + drm_dev_error(dev, + "failed to request iovcc regulator: %d ", + ret); + return ret; + } + + mipi_dsi_set_drvdata(dsi, ctx); + + ctx->dev = dev; + + dsi->lanes = 4; + dsi->format = mipi_dsi_fmt_rgb888; + dsi->mode_flags = mipi_dsi_mode_video | mipi_dsi_mode_video_burst | + mipi_dsi_mode_lpm | mipi_dsi_mode_eot_packet; + + drm_panel_init(&ctx->panel, &dsi->dev, &xpp055c272_funcs, + drm_mode_connector_dsi); + + ret = drm_panel_of_backlight(&ctx->panel); + if (ret) + return ret; + + drm_panel_add(&ctx->panel); + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_dev_error(dev, "mipi_dsi_attach failed: %d ", ret); + drm_panel_remove(&ctx->panel); + return ret; + } + + return 0; +} + +static void xpp055c272_shutdown(struct mipi_dsi_device *dsi) +{ + struct xpp055c272 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + ret = drm_panel_unprepare(&ctx->panel); + if (ret < 0) + drm_dev_error(&dsi->dev, "failed to unprepare panel: %d ", + ret); + + ret = drm_panel_disable(&ctx->panel); + if (ret < 0) + drm_dev_error(&dsi->dev, "failed to disable panel: %d ", + ret); +} + +static int xpp055c272_remove(struct mipi_dsi_device *dsi) +{ + struct xpp055c272 *ctx = mipi_dsi_get_drvdata(dsi); + int ret; + + xpp055c272_shutdown(dsi); + + ret = mipi_dsi_detach(dsi); + if (ret < 0) + drm_dev_error(&dsi->dev, "failed to detach from dsi host: %d ", + ret); + + drm_panel_remove(&ctx->panel); + + return 0; +} + +static const struct of_device_id xpp055c272_of_match[] = { + { .compatible = "xinpeng,xpp055c272" }, + { /* sentinel */ } +}; +module_device_table(of, xpp055c272_of_match); + +static struct mipi_dsi_driver xpp055c272_driver = { + .driver = { + .name = "panel-xinpeng-xpp055c272", + .of_match_table = xpp055c272_of_match, + }, + .probe = xpp055c272_probe, + .remove = xpp055c272_remove, + .shutdown = xpp055c272_shutdown, +}; +module_mipi_dsi_driver(xpp055c272_driver); + +module_author("heiko stuebner <heiko.stuebner@theobroma-systems.com>"); +module_description("drm driver for xinpeng xpp055c272 mipi dsi panel"); +module_license("gpl v2");
|
Graphics
|
d1479d028af2e7e7b7a7ebb393a7e88763cd4587
|
heiko stuebner
|
drivers
|
gpu
|
drm, panel
|
drm/panel: add support for auo b116xak01 panel
|
signed-off-by: rob clark <robdclark@chromium.org> signed-off-by: sam ravnborg <sam@ravnborg.org> link: https://patchwork.freedesktop.org/patch/msgid/20200108235356.918189-2-robdclark@gmail.com
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for auo b116xak01 panel
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ']
|
['c']
| 1
| 32
| 0
|
--- diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c +static const struct drm_display_mode auo_b116xak01_mode = { + .clock = 69300, + .hdisplay = 1366, + .hsync_start = 1366 + 48, + .hsync_end = 1366 + 48 + 32, + .htotal = 1366 + 48 + 32 + 10, + .vdisplay = 768, + .vsync_start = 768 + 4, + .vsync_end = 768 + 4 + 6, + .vtotal = 768 + 4 + 6 + 15, + .vrefresh = 60, + .flags = drm_mode_flag_nvsync | drm_mode_flag_nhsync, +}; + +static const struct panel_desc auo_b116xak01 = { + .modes = &auo_b116xak01_mode, + .num_modes = 1, + .bpc = 6, + .size = { + .width = 256, + .height = 144, + }, + .delay = { + .hpd_absent_delay = 200, + }, + .bus_format = media_bus_fmt_rgb666_1x18, + .connector_type = drm_mode_connector_edp, +}; + + }, { + .compatible = "auo,b116xa01", + .data = &auo_b116xak01,
|
Graphics
|
da458286a5e288ad18500f89ae28cbbc7512b3e1
|
rob clark
|
drivers
|
gpu
|
drm, panel
|
drm/panel: add support for boe nv140fhm-n49 panel to panel-simple
|
this patch adds support for the boe nv140fhm-n49 panel to the panel-simple driver. the panel is used by the pine64 pinebook pro.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for boe nv140fhm-n49 panel to panel-simple
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ']
|
['c']
| 1
| 35
| 0
|
--- diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c +static const struct drm_display_mode boe_nv140fhmn49_modes[] = { + { + .clock = 148500, + .hdisplay = 1920, + .hsync_start = 1920 + 48, + .hsync_end = 1920 + 48 + 32, + .htotal = 2200, + .vdisplay = 1080, + .vsync_start = 1080 + 3, + .vsync_end = 1080 + 3 + 5, + .vtotal = 1125, + .vrefresh = 60, + }, +}; + +static const struct panel_desc boe_nv140fhmn49 = { + .modes = boe_nv140fhmn49_modes, + .num_modes = array_size(boe_nv140fhmn49_modes), + .bpc = 6, + .size = { + .width = 309, + .height = 174, + }, + .delay = { + .prepare = 210, + .enable = 50, + .unprepare = 160, + }, + .bus_format = media_bus_fmt_rgb666_1x18, + .connector_type = drm_mode_connector_edp, +}; + + }, { + .compatible = "boe,nv140fhmn49", + .data = &boe_nv140fhmn49,
|
Graphics
|
a511981847ce8bb8d189f218fc4daa6c137abfc0
|
tobias schramm
|
drivers
|
gpu
|
drm, panel
|
drm/panel: simple: add satoz sat050at40h12r2 panel support
|
add support for the satoz sat050at40h12r2 panel.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add satoz sat050at40h12r2 panel support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ', 'simple']
|
['c']
| 1
| 27
| 0
|
--- diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c +static const struct display_timing satoz_sat050at40h12r2_timing = { + .pixelclock = {33300000, 33300000, 50000000}, + .hactive = {800, 800, 800}, + .hfront_porch = {16, 210, 354}, + .hback_porch = {46, 46, 46}, + .hsync_len = {1, 1, 40}, + .vactive = {480, 480, 480}, + .vfront_porch = {7, 22, 147}, + .vback_porch = {23, 23, 23}, + .vsync_len = {1, 1, 20}, +}; + +static const struct panel_desc satoz_sat050at40h12r2 = { + .timings = &satoz_sat050at40h12r2_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 108, + .height = 65, + }, + .bus_format = media_bus_fmt_rgb888_1x24, + .connector_type = drm_mode_connector_lvds, +}; + + }, { + .compatible = "satoz,sat050at40h12r2", + .data = &satoz_sat050at40h12r2,
|
Graphics
|
44c58c520ffc4b1f75241e5029c5ae6b223d0623
|
miquel raynal
|
drivers
|
gpu
|
drm, panel
|
dt-bindings: panel-simple: add compatible for giantplus gpm940b0
|
add a compatible string for the giantplus gpm740b0 3" qvga tft lcd panel, and remove the old giantplus,gpm740b0.txt documentation which is now obsolete.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add compatible for giantplus gpm940b0
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ', 'simple']
|
['yaml', 'txt']
| 2
| 2
| 12
|
--- diff --git a/documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt b/documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt --- a/documentation/devicetree/bindings/display/panel/giantplus,gpm940b0.txt +++ /dev/null -giantplus 3.0" (320x240 pixels) 24-bit tft lcd panel - -required properties: -- compatible: should be "giantplus,gpm940b0" -- power-supply: as specified in the base binding - -optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -this binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory. diff --git a/documentation/devicetree/bindings/display/panel/panel-simple.yaml b/documentation/devicetree/bindings/display/panel/panel-simple.yaml --- a/documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/documentation/devicetree/bindings/display/panel/panel-simple.yaml - ampire,am800480r3tmqwa1h - auo,b116xa01 + # giantplus gpm940b0 3.0" qvga tft lcd panel + - giantplus,gpm940b0
|
Graphics
|
2ae4829d222e9ad066b1bcbdabefc3e5d039d46c
|
paul cercueil
|
documentation
|
devicetree
|
bindings, display, panel
|
dt-bindings: panel-simple: add compatible for sharp ls020b1dd01d
|
add a compatible string for the sharp ls020b1dd01d 2" hqvga tft lcd panel, and remove the old sharp,ls020b1dd01d.txt documentation which is now obsolete.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
sharp ls020b1dd01d panels
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ']
|
['yaml', 'txt']
| 2
| 2
| 12
|
--- diff --git a/documentation/devicetree/bindings/display/panel/panel-simple.yaml b/documentation/devicetree/bindings/display/panel/panel-simple.yaml --- a/documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/documentation/devicetree/bindings/display/panel/panel-simple.yaml - auo,b116xa01 - giantplus,gpm940b0 + # sharp ls020b1dd01d 2.0" hqvga tft lcd panel + - sharp,ls020b1dd01d diff --git a/documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt b/documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt --- a/documentation/devicetree/bindings/display/panel/sharp,ls020b1dd01d.txt +++ /dev/null -sharp 2.0" (240x160 pixels) 16-bit tft lcd panel - -required properties: -- compatible: should be "sharp,ls020b1dd01d" -- power-supply: as specified in the base binding - -optional properties: -- backlight: as specified in the base binding -- enable-gpios: as specified in the base binding - -this binding is compatible with the simple-panel binding, which is specified -in simple-panel.txt in this directory.
|
Graphics
|
240a25720925b5033a27863fb051a2c384a4dd64
|
paul cercueil
|
documentation
|
devicetree
|
bindings, display, panel
|
drm/panel: add boe himax8279d mipi-dsi lcd panel
|
support boe himax8279d 8.0" 1200x1920 tft lcd panel, it is a mipi dsi panel.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add boe himax8279d mipi-dsi lcd panel
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['panel ']
|
['c', 'kconfig', 'makefile', 'maintainers']
| 4
| 996
| 0
|
- use the backlight support in drm_panel to simplify the driver (sam) - adjust init code, make the format more concise (emil) - kill off default_off_cmds (emil) - use mipi_dsi_dcs_set_display_{on,off} in their enable/disable - adjusting the delay function (emil) - modify parenthesis_alignment format (sam) - use gpios are required api replace optional gpio api (emil) - modify communication address - add the information of the reviewer - remove unnecessary delays, the udelay_range code gracefully returns - merge the same data structures, like display_mode and off_cmds (derek) - optimize the processing of results returned by - add the information of the reviewer (sam) - delete unnecessary header files #include <linux/fb.h> (sam) - the config drm_panel_boe_himax8279d appears twice. drop one of them (sam) - add static, set_gpios function is not used outside this module (sam) - frefix all function maes with boe_ (sam) - fsed "enable_gpio" replace "reset_gpio", make it look clearer (sam) - sort include lines alphabetically (sam) - fixed entries in the makefile must be sorted alphabetically (sam) - add send_mipi_cmds function to avoid duplicating the code (sam) - add the necessary delay(reset_delay_t5) between reset and sending - remove unnecessary delays in sending initialization commands (jitao shi) - use spdx identifier (sam) - use necessary header files replace drmp.h (sam) - delete unnecessary header files #include <linux/err.h> (sam) - specifies a gpios array to control the reset timing, - delete backlight_disable() function when already disabled (sam) - use devm_of_find_backlight() replace of_find_backlight_by_node() (sam) - move the necessary data in the dts to the current file, - add compatible device "boe,himax8279d10p" (sam) - support boe himax8279d 8.0" 1200x1920 tft lcd panel, it is a mipi dsi --- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +drm driver for boe himax8279d panels +m: jerry han <hanxu5@huaqin.corp-partner.google.com> +s: maintained +f: drivers/gpu/drm/panel/panel-boe-himax8279d.c +f: documentation/devicetree/bindings/display/panel/boe,himax8279d.txt + diff --git a/drivers/gpu/drm/panel/kconfig b/drivers/gpu/drm/panel/kconfig --- a/drivers/gpu/drm/panel/kconfig +++ b/drivers/gpu/drm/panel/kconfig +config drm_panel_boe_himax8279d + tristate "boe himax8279d panel" + depends on of + depends on drm_mipi_dsi + depends on backlight_class_device + help + say y here if you want to enable support for boe himax8279d + tft-lcd modules. the panel has a 1200x1920 resolution and uses + 24 bit rgb per pixel. it provides a mipi dsi interface to + the host and has a built-in led backlight. + diff --git a/drivers/gpu/drm/panel/makefile b/drivers/gpu/drm/panel/makefile --- a/drivers/gpu/drm/panel/makefile +++ b/drivers/gpu/drm/panel/makefile +obj-$(config_drm_panel_boe_himax8279d) += panel-boe-himax8279d.o diff --git a/drivers/gpu/drm/panel/panel-boe-himax8279d.c b/drivers/gpu/drm/panel/panel-boe-himax8279d.c --- /dev/null +++ b/drivers/gpu/drm/panel/panel-boe-himax8279d.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2019, huaqin telecom technology co., ltd + * + * author: jerry han <jerry.han.hq@gmail.com> + * + */ + +#include <linux/delay.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> + +#include <linux/gpio/consumer.h> +#include <linux/regulator/consumer.h> + +#include <drm/drm_device.h> +#include <drm/drm_mipi_dsi.h> +#include <drm/drm_modes.h> +#include <drm/drm_panel.h> +#include <drm/drm_print.h> + +#include <video/mipi_display.h> + +struct panel_cmd { + char cmd; + char data; +}; + +struct panel_desc { + const struct drm_display_mode *display_mode; + unsigned int bpc; + unsigned int width_mm; + unsigned int height_mm; + + unsigned long mode_flags; + enum mipi_dsi_pixel_format format; + unsigned int lanes; + const struct panel_cmd *on_cmds; + unsigned int on_cmds_num; +}; + +struct panel_info { + struct drm_panel base; + struct mipi_dsi_device *link; + const struct panel_desc *desc; + + struct gpio_desc *enable_gpio; + struct gpio_desc *pp33_gpio; + struct gpio_desc *pp18_gpio; + + bool prepared; + bool enabled; +}; + +static inline struct panel_info *to_panel_info(struct drm_panel *panel) +{ + return container_of(panel, struct panel_info, base); +} + +static void disable_gpios(struct panel_info *pinfo) +{ + gpiod_set_value(pinfo->enable_gpio, 0); + gpiod_set_value(pinfo->pp33_gpio, 0); + gpiod_set_value(pinfo->pp18_gpio, 0); +} + +static int send_mipi_cmds(struct drm_panel *panel, const struct panel_cmd *cmds) +{ + struct panel_info *pinfo = to_panel_info(panel); + unsigned int i = 0; + int err; + + for (i = 0; i < pinfo->desc->on_cmds_num; i++) { + err = mipi_dsi_dcs_write_buffer(pinfo->link, &cmds[i], + sizeof(struct panel_cmd)); + + if (err < 0) + return err; + } + + return 0; +} + +static int boe_panel_disable(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + int err; + + if (!pinfo->enabled) + return 0; + + err = mipi_dsi_dcs_set_display_off(pinfo->link); + if (err < 0) { + drm_dev_error(panel->dev, "failed to set display off: %d ", + err); + return err; + } + + pinfo->enabled = false; + + return 0; +} + +static int boe_panel_unprepare(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + int err; + + if (!pinfo->prepared) + return 0; + + err = mipi_dsi_dcs_set_display_off(pinfo->link); + if (err < 0) + drm_dev_error(panel->dev, "failed to set display off: %d ", + err); + + err = mipi_dsi_dcs_enter_sleep_mode(pinfo->link); + if (err < 0) + drm_dev_error(panel->dev, "failed to enter sleep mode: %d ", + err); + + /* sleep_mode_delay: 1ms - 2ms */ + usleep_range(1000, 2000); + + disable_gpios(pinfo); + + pinfo->prepared = false; + + return 0; +} + +static int boe_panel_prepare(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + int err; + + if (pinfo->prepared) + return 0; + + gpiod_set_value(pinfo->pp18_gpio, 1); + /* t1: 5ms - 6ms */ + usleep_range(5000, 6000); + gpiod_set_value(pinfo->pp33_gpio, 1); + + /* reset sequence */ + /* t2: 14ms - 15ms */ + usleep_range(14000, 15000); + gpiod_set_value(pinfo->enable_gpio, 1); + + /* t3: 1ms - 2ms */ + usleep_range(1000, 2000); + gpiod_set_value(pinfo->enable_gpio, 0); + + /* t4: 1ms - 2ms */ + usleep_range(1000, 2000); + gpiod_set_value(pinfo->enable_gpio, 1); + + /* t5: 5ms - 6ms */ + usleep_range(5000, 6000); + + /* send init code */ + err = send_mipi_cmds(panel, pinfo->desc->on_cmds); + if (err < 0) { + drm_dev_error(panel->dev, "failed to send dcs init code: %d ", + err); + goto poweroff; + } + + err = mipi_dsi_dcs_exit_sleep_mode(pinfo->link); + if (err < 0) { + drm_dev_error(panel->dev, "failed to exit sleep mode: %d ", + err); + goto poweroff; + } + + /* t6: 120ms - 121ms */ + usleep_range(120000, 121000); + + err = mipi_dsi_dcs_set_display_on(pinfo->link); + if (err < 0) { + drm_dev_error(panel->dev, "failed to set display on: %d ", + err); + goto poweroff; + } + + /* t7: 20ms - 21ms */ + usleep_range(20000, 21000); + + pinfo->prepared = true; + + return 0; + +poweroff: + disable_gpios(pinfo); + return err; +} + +static int boe_panel_enable(struct drm_panel *panel) +{ + struct panel_info *pinfo = to_panel_info(panel); + int ret; + + if (pinfo->enabled) + return 0; + + usleep_range(120000, 121000); + + ret = mipi_dsi_dcs_set_display_on(pinfo->link); + if (ret < 0) { + drm_dev_error(panel->dev, "failed to set display on: %d ", + ret); + return ret; + } + + pinfo->enabled = true; + + return 0; +} + +static int boe_panel_get_modes(struct drm_panel *panel, + struct drm_connector *connector) +{ + struct panel_info *pinfo = to_panel_info(panel); + const struct drm_display_mode *m = pinfo->desc->display_mode; + struct drm_display_mode *mode; + + mode = drm_mode_duplicate(connector->dev, m); + if (!mode) { + drm_dev_error(pinfo->base.dev, "failed to add mode %ux%u@%u ", + m->hdisplay, m->vdisplay, m->vrefresh); + return -enomem; + } + + drm_mode_set_name(mode); + + drm_mode_probed_add(connector, mode); + + connector->display_info.width_mm = pinfo->desc->width_mm; + connector->display_info.height_mm = pinfo->desc->height_mm; + connector->display_info.bpc = pinfo->desc->bpc; + + return 1; +} + +static const struct drm_panel_funcs panel_funcs = { + .disable = boe_panel_disable, + .unprepare = boe_panel_unprepare, + .prepare = boe_panel_prepare, + .enable = boe_panel_enable, + .get_modes = boe_panel_get_modes, +}; + +static const struct drm_display_mode default_display_mode = { + .clock = 159420, + .hdisplay = 1200, + .hsync_start = 1200 + 80, + .hsync_end = 1200 + 80 + 60, + .htotal = 1200 + 80 + 60 + 24, + .vdisplay = 1920, + .vsync_start = 1920 + 10, + .vsync_end = 1920 + 10 + 14, + .vtotal = 1920 + 10 + 14 + 4, + .vrefresh = 60, +}; + +/* 8 inch */ +static const struct panel_cmd boe_himax8279d8p_on_cmds[] = { + { 0xb0, 0x05 }, + { 0xb1, 0xe5 }, + { 0xb3, 0x52 }, + { 0xc0, 0x00 }, + { 0xc2, 0x57 }, + { 0xd9, 0x85 }, + { 0xb0, 0x01 }, + { 0xc8, 0x00 }, + { 0xc9, 0x00 }, + { 0xcc, 0x26 }, + { 0xcd, 0x26 }, + { 0xdc, 0x00 }, + { 0xdd, 0x00 }, + { 0xe0, 0x26 }, + { 0xe1, 0x26 }, + { 0xb0, 0x03 }, + { 0xc3, 0x2a }, + { 0xe7, 0x2a }, + { 0xc5, 0x2a }, + { 0xde, 0x2a }, + { 0xbc, 0x02 }, + { 0xcb, 0x02 }, + { 0xb0, 0x00 }, + { 0xb6, 0x03 }, + { 0xba, 0x8b }, + { 0xbf, 0x15 }, + { 0xc0, 0x18 }, + { 0xc2, 0x14 }, + { 0xc3, 0x02 }, + { 0xc4, 0x14 }, + { 0xc5, 0x02 }, + { 0xcc, 0x0a }, + { 0xb0, 0x06 }, + { 0xc0, 0xa5 }, + { 0xd5, 0x20 }, + { 0xc0, 0x00 }, + { 0xb0, 0x02 }, + { 0xc0, 0x00 }, + { 0xc1, 0x02 }, + { 0xc2, 0x06 }, + { 0xc3, 0x16 }, + { 0xc4, 0x0e }, + { 0xc5, 0x18 }, + { 0xc6, 0x26 }, + { 0xc7, 0x32 }, + { 0xc8, 0x3f }, + { 0xc9, 0x3f }, + { 0xca, 0x3f }, + { 0xcb, 0x3f }, + { 0xcc, 0x3d }, + { 0xcd, 0x2f }, + { 0xce, 0x2f }, + { 0xcf, 0x2f }, + { 0xd0, 0x07 }, + { 0xd2, 0x00 }, + { 0xd3, 0x02 }, + { 0xd4, 0x06 }, + { 0xd5, 0x12 }, + { 0xd6, 0x0a }, + { 0xd7, 0x14 }, + { 0xd8, 0x22 }, + { 0xd9, 0x2e }, + { 0xda, 0x3d }, + { 0xdb, 0x3f }, + { 0xdc, 0x3f }, + { 0xdd, 0x3f }, + { 0xde, 0x3d }, + { 0xdf, 0x2f }, + { 0xe0, 0x2f }, + { 0xe1, 0x2f }, + { 0xe2, 0x07 }, + { 0xb0, 0x07 }, + { 0xb1, 0x18 }, + { 0xb2, 0x19 }, + { 0xb3, 0x2e }, + { 0xb4, 0x52 }, + { 0xb5, 0x72 }, + { 0xb6, 0x8c }, + { 0xb7, 0xbd }, + { 0xb8, 0xeb }, + { 0xb9, 0x47 }, + { 0xba, 0x96 }, + { 0xbb, 0x1e }, + { 0xbc, 0x90 }, + { 0xbd, 0x93 }, + { 0xbe, 0xfa }, + { 0xbf, 0x56 }, + { 0xc0, 0x8c }, + { 0xc1, 0xb7 }, + { 0xc2, 0xcc }, + { 0xc3, 0xdf }, + { 0xc4, 0xe8 }, + { 0xc5, 0xf0 }, + { 0xc6, 0xf8 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x5a }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x08 }, + { 0xb1, 0x04 }, + { 0xb2, 0x15 }, + { 0xb3, 0x2d }, + { 0xb4, 0x51 }, + { 0xb5, 0x72 }, + { 0xb6, 0x8d }, + { 0xb7, 0xbe }, + { 0xb8, 0xed }, + { 0xb9, 0x4a }, + { 0xba, 0x9a }, + { 0xbb, 0x23 }, + { 0xbc, 0x95 }, + { 0xbd, 0x98 }, + { 0xbe, 0xff }, + { 0xbf, 0x59 }, + { 0xc0, 0x8e }, + { 0xc1, 0xb9 }, + { 0xc2, 0xcd }, + { 0xc3, 0xdf }, + { 0xc4, 0xe8 }, + { 0xc5, 0xf0 }, + { 0xc6, 0xf8 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x5a }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x09 }, + { 0xb1, 0x04 }, + { 0xb2, 0x2c }, + { 0xb3, 0x36 }, + { 0xb4, 0x53 }, + { 0xb5, 0x73 }, + { 0xb6, 0x8e }, + { 0xb7, 0xc0 }, + { 0xb8, 0xef }, + { 0xb9, 0x4c }, + { 0xba, 0x9d }, + { 0xbb, 0x25 }, + { 0xbc, 0x96 }, + { 0xbd, 0x9a }, + { 0xbe, 0x01 }, + { 0xbf, 0x59 }, + { 0xc0, 0x8e }, + { 0xc1, 0xb9 }, + { 0xc2, 0xcd }, + { 0xc3, 0xdf }, + { 0xc4, 0xe8 }, + { 0xc5, 0xf0 }, + { 0xc6, 0xf8 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x5a }, + { 0xcc, 0xbf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x0a }, + { 0xb1, 0x18 }, + { 0xb2, 0x19 }, + { 0xb3, 0x2e }, + { 0xb4, 0x52 }, + { 0xb5, 0x72 }, + { 0xb6, 0x8c }, + { 0xb7, 0xbd }, + { 0xb8, 0xeb }, + { 0xb9, 0x47 }, + { 0xba, 0x96 }, + { 0xbb, 0x1e }, + { 0xbc, 0x90 }, + { 0xbd, 0x93 }, + { 0xbe, 0xfa }, + { 0xbf, 0x56 }, + { 0xc0, 0x8c }, + { 0xc1, 0xb7 }, + { 0xc2, 0xcc }, + { 0xc3, 0xdf }, + { 0xc4, 0xe8 }, + { 0xc5, 0xf0 }, + { 0xc6, 0xf8 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x5a }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x0b }, + { 0xb1, 0x04 }, + { 0xb2, 0x15 }, + { 0xb3, 0x2d }, + { 0xb4, 0x51 }, + { 0xb5, 0x72 }, + { 0xb6, 0x8d }, + { 0xb7, 0xbe }, + { 0xb8, 0xed }, + { 0xb9, 0x4a }, + { 0xba, 0x9a }, + { 0xbb, 0x23 }, + { 0xbc, 0x95 }, + { 0xbd, 0x98 }, + { 0xbe, 0xff }, + { 0xbf, 0x59 }, + { 0xc0, 0x8e }, + { 0xc1, 0xb9 }, + { 0xc2, 0xcd }, + { 0xc3, 0xdf }, + { 0xc4, 0xe8 }, + { 0xc5, 0xf0 }, + { 0xc6, 0xf8 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x5a }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x0c }, + { 0xb1, 0x04 }, + { 0xb2, 0x2c }, + { 0xb3, 0x36 }, + { 0xb4, 0x53 }, + { 0xb5, 0x73 }, + { 0xb6, 0x8e }, + { 0xb7, 0xc0 }, + { 0xb8, 0xef }, + { 0xb9, 0x4c }, + { 0xba, 0x9d }, + { 0xbb, 0x25 }, + { 0xbc, 0x96 }, + { 0xbd, 0x9a }, + { 0xbe, 0x01 }, + { 0xbf, 0x59 }, + { 0xc0, 0x8e }, + { 0xc1, 0xb9 }, + { 0xc2, 0xcd }, + { 0xc3, 0xdf }, + { 0xc4, 0xe8 }, + { 0xc5, 0xf0 }, + { 0xc6, 0xf8 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x5a }, + { 0xcc, 0xbf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x04 }, + { 0xb5, 0x02 }, + { 0xb6, 0x01 }, +}; + +static const struct panel_desc boe_himax8279d8p_panel_desc = { + .display_mode = &default_display_mode, + .bpc = 8, + .width_mm = 107, + .height_mm = 172, + .mode_flags = mipi_dsi_mode_video | mipi_dsi_mode_video_sync_pulse | + mipi_dsi_clock_non_continuous | mipi_dsi_mode_lpm, + .format = mipi_dsi_fmt_rgb888, + .lanes = 4, + .on_cmds = boe_himax8279d8p_on_cmds, + .on_cmds_num = 260, +}; + +/* 10 inch */ +static const struct panel_cmd boe_himax8279d10p_on_cmds[] = { + { 0xb0, 0x05 }, + { 0xb1, 0xe5 }, + { 0xb3, 0x52 }, + { 0xb0, 0x00 }, + { 0xb6, 0x03 }, + { 0xba, 0x8b }, + { 0xbf, 0x1a }, + { 0xc0, 0x0f }, + { 0xc2, 0x0c }, + { 0xc3, 0x02 }, + { 0xc4, 0x0c }, + { 0xc5, 0x02 }, + { 0xb0, 0x01 }, + { 0xe0, 0x26 }, + { 0xe1, 0x26 }, + { 0xdc, 0x00 }, + { 0xdd, 0x00 }, + { 0xcc, 0x26 }, + { 0xcd, 0x26 }, + { 0xc8, 0x00 }, + { 0xc9, 0x00 }, + { 0xd2, 0x03 }, + { 0xd3, 0x03 }, + { 0xe6, 0x04 }, + { 0xe7, 0x04 }, + { 0xc4, 0x09 }, + { 0xc5, 0x09 }, + { 0xd8, 0x0a }, + { 0xd9, 0x0a }, + { 0xc2, 0x0b }, + { 0xc3, 0x0b }, + { 0xd6, 0x0c }, + { 0xd7, 0x0c }, + { 0xc0, 0x05 }, + { 0xc1, 0x05 }, + { 0xd4, 0x06 }, + { 0xd5, 0x06 }, + { 0xca, 0x07 }, + { 0xcb, 0x07 }, + { 0xde, 0x08 }, + { 0xdf, 0x08 }, + { 0xb0, 0x02 }, + { 0xc0, 0x00 }, + { 0xc1, 0x0d }, + { 0xc2, 0x17 }, + { 0xc3, 0x26 }, + { 0xc4, 0x31 }, + { 0xc5, 0x1c }, + { 0xc6, 0x2c }, + { 0xc7, 0x33 }, + { 0xc8, 0x31 }, + { 0xc9, 0x37 }, + { 0xca, 0x37 }, + { 0xcb, 0x37 }, + { 0xcc, 0x39 }, + { 0xcd, 0x2e }, + { 0xce, 0x2f }, + { 0xcf, 0x2f }, + { 0xd0, 0x07 }, + { 0xd2, 0x00 }, + { 0xd3, 0x0d }, + { 0xd4, 0x17 }, + { 0xd5, 0x26 }, + { 0xd6, 0x31 }, + { 0xd7, 0x3f }, + { 0xd8, 0x3f }, + { 0xd9, 0x3f }, + { 0xda, 0x3f }, + { 0xdb, 0x37 }, + { 0xdc, 0x37 }, + { 0xdd, 0x37 }, + { 0xde, 0x39 }, + { 0xdf, 0x2e }, + { 0xe0, 0x2f }, + { 0xe1, 0x2f }, + { 0xe2, 0x07 }, + { 0xb0, 0x03 }, + { 0xc8, 0x0b }, + { 0xc9, 0x07 }, + { 0xc3, 0x00 }, + { 0xe7, 0x00 }, + { 0xc5, 0x2a }, + { 0xde, 0x2a }, + { 0xca, 0x43 }, + { 0xc9, 0x07 }, + { 0xe4, 0xc0 }, + { 0xe5, 0x0d }, + { 0xcb, 0x01 }, + { 0xbc, 0x01 }, + { 0xb0, 0x06 }, + { 0xb8, 0xa5 }, + { 0xc0, 0xa5 }, + { 0xc7, 0x0f }, + { 0xd5, 0x32 }, + { 0xb8, 0x00 }, + { 0xc0, 0x00 }, + { 0xbc, 0x00 }, + { 0xb0, 0x07 }, + { 0xb1, 0x00 }, + { 0xb2, 0x05 }, + { 0xb3, 0x10 }, + { 0xb4, 0x22 }, + { 0xb5, 0x36 }, + { 0xb6, 0x4a }, + { 0xb7, 0x6c }, + { 0xb8, 0x9a }, + { 0xb9, 0xd7 }, + { 0xba, 0x17 }, + { 0xbb, 0x92 }, + { 0xbc, 0x15 }, + { 0xbd, 0x18 }, + { 0xbe, 0x8c }, + { 0xbf, 0x00 }, + { 0xc0, 0x3a }, + { 0xc1, 0x72 }, + { 0xc2, 0x8c }, + { 0xc3, 0xa5 }, + { 0xc4, 0xb1 }, + { 0xc5, 0xbe }, + { 0xc6, 0xca }, + { 0xc7, 0xd1 }, + { 0xc8, 0xd4 }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x16 }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x08 }, + { 0xb1, 0x04 }, + { 0xb2, 0x05 }, + { 0xb3, 0x11 }, + { 0xb4, 0x24 }, + { 0xb5, 0x39 }, + { 0xb6, 0x4e }, + { 0xb7, 0x72 }, + { 0xb8, 0xa3 }, + { 0xb9, 0xe1 }, + { 0xba, 0x25 }, + { 0xbb, 0xa8 }, + { 0xbc, 0x2e }, + { 0xbd, 0x32 }, + { 0xbe, 0xad }, + { 0xbf, 0x28 }, + { 0xc0, 0x63 }, + { 0xc1, 0x9b }, + { 0xc2, 0xb5 }, + { 0xc3, 0xcf }, + { 0xc4, 0xdb }, + { 0xc5, 0xe8 }, + { 0xc6, 0xf5 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x16 }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x09 }, + { 0xb1, 0x04 }, + { 0xb2, 0x04 }, + { 0xb3, 0x0f }, + { 0xb4, 0x22 }, + { 0xb5, 0x37 }, + { 0xb6, 0x4d }, + { 0xb7, 0x71 }, + { 0xb8, 0xa2 }, + { 0xb9, 0xe1 }, + { 0xba, 0x26 }, + { 0xbb, 0xa9 }, + { 0xbc, 0x2f }, + { 0xbd, 0x33 }, + { 0xbe, 0xac }, + { 0xbf, 0x24 }, + { 0xc0, 0x5d }, + { 0xc1, 0x94 }, + { 0xc2, 0xac }, + { 0xc3, 0xc5 }, + { 0xc4, 0xd1 }, + { 0xc5, 0xdc }, + { 0xc6, 0xe8 }, + { 0xc7, 0xed }, + { 0xc8, 0xf0 }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x16 }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x0a }, + { 0xb1, 0x00 }, + { 0xb2, 0x05 }, + { 0xb3, 0x10 }, + { 0xb4, 0x22 }, + { 0xb5, 0x36 }, + { 0xb6, 0x4a }, + { 0xb7, 0x6c }, + { 0xb8, 0x9a }, + { 0xb9, 0xd7 }, + { 0xba, 0x17 }, + { 0xbb, 0x92 }, + { 0xbc, 0x15 }, + { 0xbd, 0x18 }, + { 0xbe, 0x8c }, + { 0xbf, 0x00 }, + { 0xc0, 0x3a }, + { 0xc1, 0x72 }, + { 0xc2, 0x8c }, + { 0xc3, 0xa5 }, + { 0xc4, 0xb1 }, + { 0xc5, 0xbe }, + { 0xc6, 0xca }, + { 0xc7, 0xd1 }, + { 0xc8, 0xd4 }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x16 }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x0b }, + { 0xb1, 0x04 }, + { 0xb2, 0x05 }, + { 0xb3, 0x11 }, + { 0xb4, 0x24 }, + { 0xb5, 0x39 }, + { 0xb6, 0x4e }, + { 0xb7, 0x72 }, + { 0xb8, 0xa3 }, + { 0xb9, 0xe1 }, + { 0xba, 0x25 }, + { 0xbb, 0xa8 }, + { 0xbc, 0x2e }, + { 0xbd, 0x32 }, + { 0xbe, 0xad }, + { 0xbf, 0x28 }, + { 0xc0, 0x63 }, + { 0xc1, 0x9b }, + { 0xc2, 0xb5 }, + { 0xc3, 0xcf }, + { 0xc4, 0xdb }, + { 0xc5, 0xe8 }, + { 0xc6, 0xf5 }, + { 0xc7, 0xfa }, + { 0xc8, 0xfc }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x16 }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, + { 0xb0, 0x0c }, + { 0xb1, 0x04 }, + { 0xb2, 0x04 }, + { 0xb3, 0x0f }, + { 0xb4, 0x22 }, + { 0xb5, 0x37 }, + { 0xb6, 0x4d }, + { 0xb7, 0x71 }, + { 0xb8, 0xa2 }, + { 0xb9, 0xe1 }, + { 0xba, 0x26 }, + { 0xbb, 0xa9 }, + { 0xbc, 0x2f }, + { 0xbd, 0x33 }, + { 0xbe, 0xac }, + { 0xbf, 0x24 }, + { 0xc0, 0x5d }, + { 0xc1, 0x94 }, + { 0xc2, 0xac }, + { 0xc3, 0xc5 }, + { 0xc4, 0xd1 }, + { 0xc5, 0xdc }, + { 0xc6, 0xe8 }, + { 0xc7, 0xed }, + { 0xc8, 0xf0 }, + { 0xc9, 0x00 }, + { 0xca, 0x00 }, + { 0xcb, 0x16 }, + { 0xcc, 0xaf }, + { 0xcd, 0xff }, + { 0xce, 0xff }, +}; + +static const struct panel_desc boe_himax8279d10p_panel_desc = { + .display_mode = &default_display_mode, + .bpc = 8, + .width_mm = 135, + .height_mm = 216, + .mode_flags = mipi_dsi_mode_video | mipi_dsi_mode_video_sync_pulse | + mipi_dsi_clock_non_continuous | mipi_dsi_mode_lpm, + .format = mipi_dsi_fmt_rgb888, + .lanes = 4, + .on_cmds = boe_himax8279d10p_on_cmds, + .on_cmds_num = 283, +}; + +static const struct of_device_id panel_of_match[] = { + { + .compatible = "boe,himax8279d8p", + .data = &boe_himax8279d8p_panel_desc, + }, + { + .compatible = "boe,himax8279d10p", + .data = &boe_himax8279d10p_panel_desc, + }, + { + /* sentinel */ + } +}; +module_device_table(of, panel_of_match); + +static int panel_add(struct panel_info *pinfo) +{ + struct device *dev = &pinfo->link->dev; + int ret; + + pinfo->pp18_gpio = devm_gpiod_get(dev, "pp18", gpiod_out_high); + if (is_err(pinfo->pp18_gpio)) { + ret = ptr_err(pinfo->pp18_gpio); + if (ret != -eprobe_defer) + drm_dev_error(dev, "failed to get pp18 gpio: %d ", + ret); + return ret; + } + + pinfo->pp33_gpio = devm_gpiod_get(dev, "pp33", gpiod_out_high); + if (is_err(pinfo->pp33_gpio)) { + ret = ptr_err(pinfo->pp33_gpio); + if (ret != -eprobe_defer) + drm_dev_error(dev, "failed to get pp33 gpio: %d ", + ret); + return ret; + } + + pinfo->enable_gpio = devm_gpiod_get(dev, "enable", gpiod_out_high); + if (is_err(pinfo->enable_gpio)) { + ret = ptr_err(pinfo->enable_gpio); + if (ret != -eprobe_defer) + drm_dev_error(dev, "failed to get enable gpio: %d ", + ret); + return ret; + } + + drm_panel_init(&pinfo->base, dev, &panel_funcs, + drm_mode_connector_dsi); + + ret = drm_panel_of_backlight(&pinfo->base); + if (ret) + return ret; + + return drm_panel_add(&pinfo->base); +} + +static int panel_probe(struct mipi_dsi_device *dsi) +{ + struct panel_info *pinfo; + const struct panel_desc *desc; + int err; + + pinfo = devm_kzalloc(&dsi->dev, sizeof(*pinfo), gfp_kernel); + if (!pinfo) + return -enomem; + + desc = of_device_get_match_data(&dsi->dev); + dsi->mode_flags = desc->mode_flags; + dsi->format = desc->format; + dsi->lanes = desc->lanes; + pinfo->desc = desc; + + pinfo->link = dsi; + mipi_dsi_set_drvdata(dsi, pinfo); + + err = panel_add(pinfo); + if (err < 0) + return err; + + err = mipi_dsi_attach(dsi); + if (err < 0) + drm_panel_remove(&pinfo->base); + + return err; +} + +static int panel_remove(struct mipi_dsi_device *dsi) +{ + struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi); + int err; + + err = boe_panel_disable(&pinfo->base); + if (err < 0) + drm_dev_error(&dsi->dev, "failed to disable panel: %d ", + err); + + err = boe_panel_unprepare(&pinfo->base); + if (err < 0) + drm_dev_error(&dsi->dev, "failed to unprepare panel: %d ", + err); + + err = mipi_dsi_detach(dsi); + if (err < 0) + drm_dev_error(&dsi->dev, "failed to detach from dsi host: %d ", + err); + + drm_panel_remove(&pinfo->base); + + return 0; +} + +static void panel_shutdown(struct mipi_dsi_device *dsi) +{ + struct panel_info *pinfo = mipi_dsi_get_drvdata(dsi); + + boe_panel_disable(&pinfo->base); + boe_panel_unprepare(&pinfo->base); +} + +static struct mipi_dsi_driver panel_driver = { + .driver = { + .name = "panel-boe-himax8279d", + .of_match_table = panel_of_match, + }, + .probe = panel_probe, + .remove = panel_remove, + .shutdown = panel_shutdown, +}; +module_mipi_dsi_driver(panel_driver); + +module_author("jerry han <jerry.han.hq@gmail.com>"); +module_description("boe himax8279d driver"); +module_license("gpl v2");
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Graphics
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4b6dd3cae3cb53a2c45e5238d7c1af7c39cd4685
|
jerry han
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drivers
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gpu
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drm, panel
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drm/panel: add backlight support
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panels often support backlight as specified in a device tree. update the drm_panel infrastructure to support this to simplify the drivers.
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this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
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add backlight support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
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['panel ']
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['c', 'h']
| 2
| 85
| 2
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- improve comments, fix grammar (laurent) - do not fail in drm_panel_of_backlight() if no dt support (laurent) - log if backlight_(enable|disable) fails (laurent) - improve drm_panel_of_backlight() docs - updated changelog with backlight analysis (triggered by laurent) - drop test of config_drm_panel in header-file (laurent) - do not enable backlight if ->enable() returns an error --- diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c --- a/drivers/gpu/drm/drm_panel.c +++ b/drivers/gpu/drm/drm_panel.c +#include <linux/backlight.h> +#include <drm/drm_print.h> + int ret; + - if (panel->funcs && panel->funcs->enable) - return panel->funcs->enable(panel); + if (panel->funcs && panel->funcs->enable) { + ret = panel->funcs->enable(panel); + if (ret < 0) + return ret; + } + + ret = backlight_enable(panel->backlight); + if (ret < 0) + drm_dev_info(panel->dev, "failed to enable backlight: %d ", + ret); + int ret; + + ret = backlight_disable(panel->backlight); + if (ret < 0) + drm_dev_info(panel->dev, "failed to disable backlight: %d ", + ret); + +#ifdef config_backlight_class_device +/** + * drm_panel_of_backlight - use backlight device node for backlight + * @panel: drm panel + * + * use this function to enable backlight handling if your panel + * uses device tree and has a backlight phandle. + * + * when the panel is enabled backlight will be enabled after a + * successful call to &drm_panel_funcs.enable() + * + * when the panel is disabled backlight will be disabled before the + * call to &drm_panel_funcs.disable(). + * + * a typical implementation for a panel driver supporting device tree + * will call this function at probe time. backlight will then be handled + * transparently without requiring any intervention from the driver. + * drm_panel_of_backlight() must be called after the call to drm_panel_init(). + * + * return: 0 on success or a negative error code on failure. + */ +int drm_panel_of_backlight(struct drm_panel *panel) +{ + struct backlight_device *backlight; + + if (!panel || !panel->dev) + return -einval; + + backlight = devm_of_find_backlight(panel->dev); + + if (is_err(backlight)) + return ptr_err(backlight); + + panel->backlight = backlight; + return 0; +} +export_symbol(drm_panel_of_backlight); +#endif + diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h --- a/include/drm/drm_panel.h +++ b/include/drm/drm_panel.h +struct backlight_device; + * + * backlight can be handled automatically if configured using + * drm_panel_of_backlight(). then the driver does not need to implement the + * functionality to enable/disable backlight. + /** + * @backlight: + * + * backlight device, used to turn on backlight after the call + * to enable(), and to turn off backlight before the call to + * disable(). + * backlight is set by drm_panel_of_backlight() and drivers + * shall not assign it. + */ + struct backlight_device *backlight; + +#if is_enabled(config_backlight_class_device) +int drm_panel_of_backlight(struct drm_panel *panel); +#else +static inline int drm_panel_of_backlight(struct drm_panel *panel) +{ + return 0; +} +#endif +
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Graphics
|
152dbdeab1b2571c107357a7bd59f5cd5be52e30
|
sam ravnborg
|
include
|
drm
|
drm
|
drm/nouveau/acr/tu10x: initial support
|
signed-off-by: ben skeggs <bskeggs@redhat.com>
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
tu10x graphics engine support (tu11x pending)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['nouveau ']
|
['h', 'kbuild', 'c']
| 6
| 229
| 0
|
--- diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h +int tu102_acr_new(struct nvkm_device *, int, struct nvkm_acr **); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c + .acr = tu102_acr_new, + .acr = tu102_acr_new, + .acr = tu102_acr_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/kbuild --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/kbuild +nvkm-y += nvkm/subdev/acr/tu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.c + if (list_empty(&acr->hsfw)) { + nvkm_debug(subdev, "no hsfw(s) "); + nvkm_acr_cleanup(acr); + return 0; + } + diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c +/* + * copyright 2019 red hat inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + */ +#include "priv.h" + +#include <core/firmware.h> +#include <core/memory.h> +#include <subdev/gsp.h> +#include <subdev/pmu.h> +#include <engine/sec2.h> + +#include <nvfw/acr.h> + +static int +tu102_acr_init(struct nvkm_acr *acr) +{ + int ret = nvkm_acr_hsf_boot(acr, "ahesasc"); + if (ret) + return ret; + + return nvkm_acr_hsf_boot(acr, "asb"); +} + +static int +tu102_acr_wpr_build(struct nvkm_acr *acr, struct nvkm_acr_lsf *rtos) +{ + struct nvkm_acr_lsfw *lsfw; + u32 offset = 0; + int ret; + + /*xxx: shared sub-wpr headers, fill terminator for now. */ + nvkm_wo32(acr->wpr, 0x200, 0xffffffff); + + /* fill per-lsf structures. */ + list_for_each_entry(lsfw, &acr->lsfw, head) { + struct lsf_signature_v1 *sig = (void *)lsfw->sig->data; + struct wpr_header_v1 hdr = { + .falcon_id = lsfw->id, + .lsb_offset = lsfw->offset.lsb, + .bootstrap_owner = nvkm_acr_lsf_gsplite, + .lazy_bootstrap = 1, + .bin_version = sig->version, + .status = wpr_header_v1_status_copy, + }; + + /* write wpr header. */ + nvkm_wobj(acr->wpr, offset, &hdr, sizeof(hdr)); + offset += sizeof(hdr); + + /* write lsb header. */ + ret = gp102_acr_wpr_build_lsb(acr, lsfw); + if (ret) + return ret; + + /* write ucode image. */ + nvkm_wobj(acr->wpr, lsfw->offset.img, + lsfw->img.data, + lsfw->img.size); + + /* write bootloader data. */ + lsfw->func->bld_write(acr, lsfw->offset.bld, lsfw); + } + + /* finalise wpr. */ + nvkm_wo32(acr->wpr, offset, wpr_header_v1_falcon_id_invalid); + return 0; +} + +static int +tu102_acr_hsfw_boot(struct nvkm_acr *acr, struct nvkm_acr_hsf *hsf) +{ + return gm200_acr_hsfw_boot(acr, hsf, 0, 0); +} + +static int +tu102_acr_hsfw_nofw(struct nvkm_acr *acr, const char *bl, const char *fw, + const char *name, int version, + const struct nvkm_acr_hsf_fwif *fwif) +{ + return 0; +} + +module_firmware("nvidia/tu102/acr/unload_bl.bin"); +module_firmware("nvidia/tu102/acr/ucode_unload.bin"); + +module_firmware("nvidia/tu104/acr/unload_bl.bin"); +module_firmware("nvidia/tu104/acr/ucode_unload.bin"); + +module_firmware("nvidia/tu106/acr/unload_bl.bin"); +module_firmware("nvidia/tu106/acr/ucode_unload.bin"); + +static const struct nvkm_acr_hsf_fwif +tu102_acr_unload_fwif[] = { + { 0, nvkm_acr_hsfw_load, &gp108_acr_unload_0 }, + { -1, tu102_acr_hsfw_nofw }, + {} +}; + +static int +tu102_acr_asb_load(struct nvkm_acr *acr, struct nvkm_acr_hsfw *hsfw) +{ + return gm200_acr_hsfw_load(acr, hsfw, &acr->subdev.device->gsp->falcon); +} + +static const struct nvkm_acr_hsf_func +tu102_acr_asb_0 = { + .load = tu102_acr_asb_load, + .boot = tu102_acr_hsfw_boot, + .bld = gp108_acr_hsfw_bld, +}; + +module_firmware("nvidia/tu102/acr/ucode_asb.bin"); +module_firmware("nvidia/tu104/acr/ucode_asb.bin"); +module_firmware("nvidia/tu106/acr/ucode_asb.bin"); + +static const struct nvkm_acr_hsf_fwif +tu102_acr_asb_fwif[] = { + { 0, nvkm_acr_hsfw_load, &tu102_acr_asb_0 }, + { -1, tu102_acr_hsfw_nofw }, + {} +}; + +static const struct nvkm_acr_hsf_func +tu102_acr_ahesasc_0 = { + .load = gp102_acr_load_load, + .boot = tu102_acr_hsfw_boot, + .bld = gp108_acr_hsfw_bld, +}; + +module_firmware("nvidia/tu102/acr/bl.bin"); +module_firmware("nvidia/tu102/acr/ucode_ahesasc.bin"); + +module_firmware("nvidia/tu104/acr/bl.bin"); +module_firmware("nvidia/tu104/acr/ucode_ahesasc.bin"); + +module_firmware("nvidia/tu106/acr/bl.bin"); +module_firmware("nvidia/tu106/acr/ucode_ahesasc.bin"); + +static const struct nvkm_acr_hsf_fwif +tu102_acr_ahesasc_fwif[] = { + { 0, nvkm_acr_hsfw_load, &tu102_acr_ahesasc_0 }, + { -1, tu102_acr_hsfw_nofw }, + {} +}; + +static const struct nvkm_acr_func +tu102_acr = { + .ahesasc = tu102_acr_ahesasc_fwif, + .asb = tu102_acr_asb_fwif, + .unload = tu102_acr_unload_fwif, + .wpr_parse = gp102_acr_wpr_parse, + .wpr_layout = gp102_acr_wpr_layout, + .wpr_alloc = gp102_acr_wpr_alloc, + .wpr_patch = gp102_acr_wpr_patch, + .wpr_build = tu102_acr_wpr_build, + .wpr_check = gm200_acr_wpr_check, + .init = tu102_acr_init, +}; + +static int +tu102_acr_load(struct nvkm_acr *acr, int version, + const struct nvkm_acr_fwif *fwif) +{ + struct nvkm_subdev *subdev = &acr->subdev; + const struct nvkm_acr_hsf_fwif *hsfwif; + + hsfwif = nvkm_firmware_load(subdev, fwif->func->ahesasc, "acrahesasc", + acr, "acr/bl", "acr/ucode_ahesasc", + "ahesasc"); + if (is_err(hsfwif)) + return ptr_err(hsfwif); + + hsfwif = nvkm_firmware_load(subdev, fwif->func->asb, "acrasb", + acr, "acr/bl", "acr/ucode_asb", "asb"); + if (is_err(hsfwif)) + return ptr_err(hsfwif); + + hsfwif = nvkm_firmware_load(subdev, fwif->func->unload, "acrunload", + acr, "acr/unload_bl", "acr/ucode_unload", + "unload"); + if (is_err(hsfwif)) + return ptr_err(hsfwif); + + return 0; +} + +static const struct nvkm_acr_fwif +tu102_acr_fwif[] = { + { 0, tu102_acr_load, &tu102_acr }, + {} +}; + +int +tu102_acr_new(struct nvkm_device *device, int index, struct nvkm_acr **pacr) +{ + return nvkm_acr_new_(tu102_acr_fwif, device, index, pacr); +} diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c +module_firmware("nvidia/tu102/nvdec/scrubber.bin"); +module_firmware("nvidia/tu104/nvdec/scrubber.bin"); +module_firmware("nvidia/tu106/nvdec/scrubber.bin");
|
Graphics
|
3fa8fe1572bc708596318280a22669dfc9eaf805
|
ben skeggs
|
drivers
|
gpu
|
acr, device, drm, engine, fb, include, nouveau, nvkm, subdev
|
drm/nouveau/acr/tu11x: initial support
|
signed-off-by: ben skeggs <bskeggs@redhat.com>
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
tu10x graphics engine support (tu11x pending)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['nouveau ']
|
['c']
| 3
| 18
| 0
|
--- diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c + .acr = tu102_acr_new, + .acr = tu102_acr_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c --- a/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.c +module_firmware("nvidia/tu116/acr/unload_bl.bin"); +module_firmware("nvidia/tu116/acr/ucode_unload.bin"); + +module_firmware("nvidia/tu117/acr/unload_bl.bin"); +module_firmware("nvidia/tu117/acr/ucode_unload.bin"); + +module_firmware("nvidia/tu116/acr/ucode_asb.bin"); +module_firmware("nvidia/tu117/acr/ucode_asb.bin"); +module_firmware("nvidia/tu116/acr/bl.bin"); +module_firmware("nvidia/tu116/acr/ucode_ahesasc.bin"); + +module_firmware("nvidia/tu117/acr/bl.bin"); +module_firmware("nvidia/tu117/acr/ucode_ahesasc.bin"); + diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.c +module_firmware("nvidia/tu116/nvdec/scrubber.bin"); +module_firmware("nvidia/tu117/nvdec/scrubber.bin");
|
Graphics
|
072663f86d62571fe540d9e1d24eb873a1b1182f
|
ben skeggs
|
drivers
|
gpu
|
acr, device, drm, engine, fb, nouveau, nvkm, subdev
|
drm/nouveau/gr/tu10x: initial support
|
signed-off-by: ben skeggs <bskeggs@redhat.com>
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
tu10x graphics engine support (tu11x pending)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['nouveau ']
|
['h', 'kbuild', 'c']
| 12
| 313
| 11
|
--- diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h --- a/drivers/gpu/drm/nouveau/include/nvif/class.h +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h +#define turing_a /* cl9097.h */ 0x0000c597 + +#define turing_compute_a 0x0000c5c0 diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/gr.h +int tu102_gr_new(struct nvkm_device *, int, struct nvkm_gr **); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c + .gr = tu102_gr_new, + .gr = tu102_gr_new, + .gr = tu102_gr_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/gr/kbuild --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/kbuild +nvkm-y += nvkm/engine/gr/tu102.o +nvkm-y += nvkm/engine/gr/ctxtu102.o diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c - gf100_gr_init_num_tpc_per_gpc(gr, true, false); + if (!func->skip_pd_num_tpc_per_gpc) + gf100_gr_init_num_tpc_per_gpc(gr, true, false); + if (grctx->r419c0c) + grctx->r419c0c(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h + bool skip_pd_num_tpc_per_gpc; + void (*r419c0c)(struct gf100_gr *); +extern const struct gf100_grctx_func tu102_grctx; +void gv100_grctx_unkn88c(struct gf100_gr *, bool); +void gv100_grctx_generate_unkn(struct gf100_gr *); +extern const struct gf100_gr_init gv100_grctx_init_sw_veid_bundle_init_0[]; +void gv100_grctx_generate_attrib(struct gf100_grctx *); +void gv100_grctx_generate_rop_mapping(struct gf100_gr *); +void gv100_grctx_generate_r400088(struct gf100_gr *, bool); + diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgv100.c -static const struct gf100_gr_init +const struct gf100_gr_init -static void +void -static void +void -static void +void -static void +void -static void +void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxtu102.c +/* + * copyright 2019 red hat inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + */ +#include "ctxgf100.h" + +static void +tu102_grctx_generate_r419c0c(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_mask(device, 0x419c0c, 0x80000000, 0x80000000); + nvkm_mask(device, 0x40584c, 0x00000008, 0x00000000); + nvkm_mask(device, 0x400080, 0x00000000, 0x00000000); +} + +static void +tu102_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + nvkm_wr32(device, tpc_unit(gpc, tpc, 0x608), sm); + nvkm_wr32(device, tpc_unit(gpc, tpc, 0x088), sm); +} + +static const struct gf100_gr_init +tu102_grctx_init_unknown_bundle_init_0[] = { + { 0x00001000, 1, 0x00000001, 0x00000004 }, + { 0x00002020, 64, 0x00000001, 0x00000000 }, + { 0x0001e100, 1, 0x00000001, 0x00000001 }, + {} +}; + +static const struct gf100_gr_pack +tu102_grctx_pack_sw_veid_bundle_init[] = { + { gv100_grctx_init_sw_veid_bundle_init_0 }, + { tu102_grctx_init_unknown_bundle_init_0 }, + {} +}; + +static void +tu102_grctx_generate_attrib(struct gf100_grctx *info) +{ + const u64 size = 0x80000; /*xxx: educated guess */ + const int s = 8; + const int b = mmio_vram(info, size, (1 << s), true); + + gv100_grctx_generate_attrib(info); + + mmio_refn(info, 0x408070, 0x00000000, s, b); + mmio_wr32(info, 0x408074, size >> s); /*xxx: guess */ + mmio_refn(info, 0x419034, 0x00000000, s, b); + mmio_wr32(info, 0x408078, 0x00000000); +} + +const struct gf100_grctx_func +tu102_grctx = { + .unkn88c = gv100_grctx_unkn88c, + .main = gf100_grctx_generate_main, + .unkn = gv100_grctx_generate_unkn, + .sw_veid_bundle_init = tu102_grctx_pack_sw_veid_bundle_init, + .bundle = gm107_grctx_generate_bundle, + .bundle_size = 0x3000, + .bundle_min_gpm_fifo_depth = 0x180, + .bundle_token_limit = 0xa80, + .pagepool = gp100_grctx_generate_pagepool, + .pagepool_size = 0x20000, + .attrib = tu102_grctx_generate_attrib, + .attrib_nr_max = 0x800, + .attrib_nr = 0x700, + .alpha_nr_max = 0xc00, + .alpha_nr = 0x800, + .gfxp_nr = 0xfa8, + .sm_id = tu102_grctx_generate_sm_id, + .skip_pd_num_tpc_per_gpc = true, + .rop_mapping = gv100_grctx_generate_rop_mapping, + .r406500 = gm200_grctx_generate_r406500, + .r400088 = gv100_grctx_generate_r400088, + .r419c0c = tu102_grctx_generate_r419c0c, +}; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c + if (gr->func->init_fs) + gr->func->init_fs(gr); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h + void (*init_fs)(struct gf100_gr *); +void gv100_gr_init_419bd8(struct gf100_gr *); +void gv100_gr_init_504430(struct gf100_gr *, int, int); +void gv100_gr_init_shader_exceptions(struct gf100_gr *, int, int); +void gv100_gr_trap_mp(struct gf100_gr *, int, int); + diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c -static void +void -static void +void -static void +void -static void +void diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c --- /dev/null +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c +/* + * copyright 2019 red hat inc. + * + * permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "software"), + * to deal in the software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the software, and to permit persons to whom the + * software is furnished to do so, subject to the following conditions: + * + * the above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the software. + * + * the software is provided "as is", without warranty of any kind, express or + * implied, including but not limited to the warranties of merchantability, + * fitness for a particular purpose and noninfringement. in no event shall + * the copyright holder(s) or author(s) be liable for any claim, damages or + * other liability, whether in an action of contract, tort or otherwise, + * arising from, out of or in connection with the software or the use or + * other dealings in the software. + */ +#include "gf100.h" +#include "ctxgf100.h" + +#include <nvif/class.h> + +static void +tu102_gr_init_fecs_exceptions(struct gf100_gr *gr) +{ + nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x006f0002); +} + +static void +tu102_gr_init_fs(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + int sm; + + gp100_grctx_generate_smid_config(gr); + gk104_grctx_generate_gpc_tpc_nr(gr); + + for (sm = 0; sm < gr->sm_nr; sm++) { + nvkm_wr32(device, gpc_unit(gr->sm[sm].gpc, 0x0c10 + + gr->sm[sm].tpc * 4), sm); + } + + gm200_grctx_generate_dist_skip_table(gr); + gf100_gr_init_num_tpc_per_gpc(gr, true, true); +} + +static void +tu102_gr_init_zcull(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + const u32 magicgpc918 = div_round_up(0x00800000, gr->tpc_total); + const u8 tile_nr = align(gr->tpc_total, 64); + u8 bank[gpc_max] = {}, gpc, i, j; + u32 data; + + for (i = 0; i < tile_nr; i += 8) { + for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) { + data |= bank[gr->tile[i + j]] << (j * 4); + bank[gr->tile[i + j]]++; + } + nvkm_wr32(device, gpc_bcast(0x0980 + ((i / 8) * 4)), data); + } + + for (gpc = 0; gpc < gr->gpc_nr; gpc++) { + nvkm_wr32(device, gpc_unit(gpc, 0x0914), + gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]); + nvkm_wr32(device, gpc_unit(gpc, 0x0910), 0x00040000 | + gr->tpc_total); + nvkm_wr32(device, gpc_unit(gpc, 0x0918), magicgpc918); + } + + nvkm_wr32(device, gpc_bcast(0x3fd4), magicgpc918); +} + +static void +tu102_gr_init_gpc_mmu(struct gf100_gr *gr) +{ + struct nvkm_device *device = gr->base.engine.subdev.device; + + nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf8001fff); + nvkm_wr32(device, 0x418890, 0x00000000); + nvkm_wr32(device, 0x418894, 0x00000000); + + nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); + nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); + nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); +} + +static const struct gf100_gr_func +tu102_gr = { + .oneinit_tiles = gm200_gr_oneinit_tiles, + .oneinit_sm_id = gm200_gr_oneinit_sm_id, + .init = gf100_gr_init, + .init_419bd8 = gv100_gr_init_419bd8, + .init_gpc_mmu = tu102_gr_init_gpc_mmu, + .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, + .init_zcull = tu102_gr_init_zcull, + .init_num_active_ltcs = gf100_gr_init_num_active_ltcs, + .init_rop_active_fbps = gp100_gr_init_rop_active_fbps, + .init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask, + .init_fs = tu102_gr_init_fs, + .init_fecs_exceptions = tu102_gr_init_fecs_exceptions, + .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, + .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, + .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, + .init_504430 = gv100_gr_init_504430, + .init_shader_exceptions = gv100_gr_init_shader_exceptions, + .trap_mp = gv100_gr_trap_mp, + .rops = gm200_gr_rops, + .gpc_nr = 6, + .tpc_nr = 5, + .ppc_nr = 3, + .grctx = &tu102_grctx, + .zbc = &gp102_gr_zbc, + .sclass = { + { -1, -1, fermi_twod_a }, + { -1, -1, kepler_inline_to_memory_b }, + { -1, -1, turing_a, &gf100_fermi }, + { -1, -1, turing_compute_a }, + {} + } +}; + +module_firmware("nvidia/tu102/gr/fecs_bl.bin"); +module_firmware("nvidia/tu102/gr/fecs_inst.bin"); +module_firmware("nvidia/tu102/gr/fecs_data.bin"); +module_firmware("nvidia/tu102/gr/fecs_sig.bin"); +module_firmware("nvidia/tu102/gr/gpccs_bl.bin"); +module_firmware("nvidia/tu102/gr/gpccs_inst.bin"); +module_firmware("nvidia/tu102/gr/gpccs_data.bin"); +module_firmware("nvidia/tu102/gr/gpccs_sig.bin"); +module_firmware("nvidia/tu102/gr/sw_ctx.bin"); +module_firmware("nvidia/tu102/gr/sw_nonctx.bin"); +module_firmware("nvidia/tu102/gr/sw_bundle_init.bin"); +module_firmware("nvidia/tu102/gr/sw_method_init.bin"); + +module_firmware("nvidia/tu104/gr/fecs_bl.bin"); +module_firmware("nvidia/tu104/gr/fecs_inst.bin"); +module_firmware("nvidia/tu104/gr/fecs_data.bin"); +module_firmware("nvidia/tu104/gr/fecs_sig.bin"); +module_firmware("nvidia/tu104/gr/gpccs_bl.bin"); +module_firmware("nvidia/tu104/gr/gpccs_inst.bin"); +module_firmware("nvidia/tu104/gr/gpccs_data.bin"); +module_firmware("nvidia/tu104/gr/gpccs_sig.bin"); +module_firmware("nvidia/tu104/gr/sw_ctx.bin"); +module_firmware("nvidia/tu104/gr/sw_nonctx.bin"); +module_firmware("nvidia/tu104/gr/sw_bundle_init.bin"); +module_firmware("nvidia/tu104/gr/sw_method_init.bin"); + +module_firmware("nvidia/tu106/gr/fecs_bl.bin"); +module_firmware("nvidia/tu106/gr/fecs_inst.bin"); +module_firmware("nvidia/tu106/gr/fecs_data.bin"); +module_firmware("nvidia/tu106/gr/fecs_sig.bin"); +module_firmware("nvidia/tu106/gr/gpccs_bl.bin"); +module_firmware("nvidia/tu106/gr/gpccs_inst.bin"); +module_firmware("nvidia/tu106/gr/gpccs_data.bin"); +module_firmware("nvidia/tu106/gr/gpccs_sig.bin"); +module_firmware("nvidia/tu106/gr/sw_ctx.bin"); +module_firmware("nvidia/tu106/gr/sw_nonctx.bin"); +module_firmware("nvidia/tu106/gr/sw_bundle_init.bin"); +module_firmware("nvidia/tu106/gr/sw_method_init.bin"); + +static const struct gf100_gr_fwif +tu102_gr_fwif[] = { + { 0, gm200_gr_load, &tu102_gr, &gp108_gr_fecs_acr, &gp108_gr_gpccs_acr }, + {} +}; + +int +tu102_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) +{ + return gf100_gr_new_(tu102_gr_fwif, device, index, pgr); +}
|
Graphics
|
afa3b96b058d87c2c44d1c83dadb2ba6998d03ce
|
ben skeggs
|
drivers
|
gpu
|
device, drm, engine, gr, include, nouveau, nvif, nvkm
|
drm/nouveau/gr/tu11x: initial support
|
signed-off-by: ben skeggs <bskeggs@redhat.com>
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
tu10x graphics engine support (tu11x pending)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['nouveau ']
|
['c']
| 2
| 28
| 0
|
--- diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c + .gr = tu102_gr_new, + .gr = tu102_gr_new, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/tu102.c +module_firmware("nvidia/tu117/gr/fecs_bl.bin"); +module_firmware("nvidia/tu117/gr/fecs_inst.bin"); +module_firmware("nvidia/tu117/gr/fecs_data.bin"); +module_firmware("nvidia/tu117/gr/fecs_sig.bin"); +module_firmware("nvidia/tu117/gr/gpccs_bl.bin"); +module_firmware("nvidia/tu117/gr/gpccs_inst.bin"); +module_firmware("nvidia/tu117/gr/gpccs_data.bin"); +module_firmware("nvidia/tu117/gr/gpccs_sig.bin"); +module_firmware("nvidia/tu117/gr/sw_ctx.bin"); +module_firmware("nvidia/tu117/gr/sw_nonctx.bin"); +module_firmware("nvidia/tu117/gr/sw_bundle_init.bin"); +module_firmware("nvidia/tu117/gr/sw_method_init.bin"); + +module_firmware("nvidia/tu116/gr/fecs_bl.bin"); +module_firmware("nvidia/tu116/gr/fecs_inst.bin"); +module_firmware("nvidia/tu116/gr/fecs_data.bin"); +module_firmware("nvidia/tu116/gr/fecs_sig.bin"); +module_firmware("nvidia/tu116/gr/gpccs_bl.bin"); +module_firmware("nvidia/tu116/gr/gpccs_inst.bin"); +module_firmware("nvidia/tu116/gr/gpccs_data.bin"); +module_firmware("nvidia/tu116/gr/gpccs_sig.bin"); +module_firmware("nvidia/tu116/gr/sw_ctx.bin"); +module_firmware("nvidia/tu116/gr/sw_nonctx.bin"); +module_firmware("nvidia/tu116/gr/sw_bundle_init.bin"); +module_firmware("nvidia/tu116/gr/sw_method_init.bin"); +
|
Graphics
|
b99ef12b80cfe48a14e7918c2f799c37d2195aca
|
ben skeggs
|
drivers
|
gpu
|
device, drm, engine, gr, nouveau, nvkm
|
drm/rockchip: dsi: add px30 support
|
add the compatible and grf definitions for the px30 soc.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
dsi/px30 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rockchip ']
|
['c']
| 1
| 27
| 0
|
- rebased on top of 5.5-rc1 - merged with dsi timing change to prevent ordering conflicts --- diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +#define px30_grf_pd_vo_con1 0x0438 +#define px30_dsi_forcetxstopmode (0xf << 7) +#define px30_dsi_forcerxmode bit(6) +#define px30_dsi_turndisable bit(5) +#define px30_dsi_lcdc_sel bit(0) + +static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { + { + .reg = 0xff450000, + .lcdsel_grf_reg = px30_grf_pd_vo_con1, + .lcdsel_big = hiword_update(0, px30_dsi_lcdc_sel), + .lcdsel_lit = hiword_update(px30_dsi_lcdc_sel, + px30_dsi_lcdc_sel), + + .lanecfg1_grf_reg = px30_grf_pd_vo_con1, + .lanecfg1 = hiword_update(0, px30_dsi_turndisable | + px30_dsi_forcerxmode | + px30_dsi_forcetxstopmode), + + .max_data_lanes = 4, + }, + { /* sentinel */ } +}; + + .compatible = "rockchip,px30-mipi-dsi", + .data = &px30_chip_data, + }, {
|
Graphics
|
49a37dc393d774b7f7b8ba3944b75c7f8673b43a
|
heiko stuebner
|
drivers
|
gpu
|
drm, rockchip
|
drm/rockchip: lvds: add px30 support
|
introduce px30 lvds support. this means adding the relevant helper functions, a specific probe and also the initialization of a specific phy.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
dsi/px30 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rockchip ']
|
['c', 'h']
| 2
| 157
| 0
|
--- diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c +#include <linux/phy/phy.h> + struct phy *dphy; +static int px30_lvds_poweron(struct rockchip_lvds *lvds) +{ + int ret; + + ret = pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + drm_dev_error(lvds->dev, "failed to get pm runtime: %d ", ret); + return ret; + } + + /* enable lvds mode */ + return regmap_update_bits(lvds->grf, px30_lvds_grf_pd_vo_con1, + px30_lvds_mode_en(1) | px30_lvds_p2s_en(1), + px30_lvds_mode_en(1) | px30_lvds_p2s_en(1)); +} + +static void px30_lvds_poweroff(struct rockchip_lvds *lvds) +{ + regmap_update_bits(lvds->grf, px30_lvds_grf_pd_vo_con1, + px30_lvds_mode_en(1) | px30_lvds_p2s_en(1), + px30_lvds_mode_en(0) | px30_lvds_p2s_en(0)); + + pm_runtime_put(lvds->dev); +} + +static int px30_lvds_grf_config(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); + + if (lvds->output != display_output_lvds) { + drm_dev_error(lvds->dev, "unsupported display output %d ", + lvds->output); + return -einval; + } + + /* set format */ + return regmap_update_bits(lvds->grf, px30_lvds_grf_pd_vo_con1, + px30_lvds_format(lvds->format), + px30_lvds_format(lvds->format)); +} + +static int px30_lvds_set_vop_source(struct rockchip_lvds *lvds, + struct drm_encoder *encoder) +{ + int vop; + + vop = drm_of_encoder_active_endpoint_id(lvds->dev->of_node, encoder); + if (vop < 0) + return vop; + + return regmap_update_bits(lvds->grf, px30_lvds_grf_pd_vo_con1, + px30_lvds_vop_sel(1), + px30_lvds_vop_sel(vop)); +} + +static void px30_lvds_encoder_enable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); + struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; + int ret; + + drm_panel_prepare(lvds->panel); + + ret = px30_lvds_poweron(lvds); + if (ret) { + drm_dev_error(lvds->dev, "failed to power on lvds: %d ", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + ret = px30_lvds_grf_config(encoder, mode); + if (ret) { + drm_dev_error(lvds->dev, "failed to configure lvds: %d ", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + ret = px30_lvds_set_vop_source(lvds, encoder); + if (ret) { + drm_dev_error(lvds->dev, "failed to set vop source: %d ", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + drm_panel_enable(lvds->panel); +} + +static void px30_lvds_encoder_disable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds = encoder_to_lvds(encoder); + + drm_panel_disable(lvds->panel); + px30_lvds_poweroff(lvds); + drm_panel_unprepare(lvds->panel); +} + +static const +struct drm_encoder_helper_funcs px30_lvds_encoder_helper_funcs = { + .enable = px30_lvds_encoder_enable, + .disable = px30_lvds_encoder_disable, + .atomic_check = rockchip_lvds_encoder_atomic_check, +}; + +static int px30_lvds_probe(struct platform_device *pdev, + struct rockchip_lvds *lvds) +{ + int ret; + + /* msb */ + ret = regmap_update_bits(lvds->grf, px30_lvds_grf_pd_vo_con1, + px30_lvds_msbsel(1), + px30_lvds_msbsel(1)); + if (ret) + return ret; + + /* phy */ + lvds->dphy = devm_phy_get(&pdev->dev, "dphy"); + if (is_err(lvds->dphy)) + return ptr_err(lvds->dphy); + + phy_init(lvds->dphy); + if (ret) + return ret; + + phy_set_mode(lvds->dphy, phy_mode_lvds); + if (ret) + return ret; + + return phy_power_on(lvds->dphy); +} + +static const struct rockchip_lvds_soc_data px30_lvds_data = { + .probe = px30_lvds_probe, + .helper_funcs = &px30_lvds_encoder_helper_funcs, +}; + + { + .compatible = "rockchip,px30-lvds", + .data = &px30_lvds_data + }, diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/rockchip/rockchip_lvds.h --- a/drivers/gpu/drm/rockchip/rockchip_lvds.h +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h +#define hiword_update(v, h, l) ((genmask(h, l) << 16) | ((v) << (l))) + +#define px30_lvds_grf_pd_vo_con0 0x434 +#define px30_lvds_tie_clks(val) hiword_update(val, 8, 8) +#define px30_lvds_invert_clks(val) hiword_update(val, 9, 9) +#define px30_lvds_invert_dclk(val) hiword_update(val, 5, 5) + +#define px30_lvds_grf_pd_vo_con1 0x438 +#define px30_lvds_format(val) hiword_update(val, 14, 13) +#define px30_lvds_mode_en(val) hiword_update(val, 12, 12) +#define px30_lvds_msbsel(val) hiword_update(val, 11, 11) +#define px30_lvds_p2s_en(val) hiword_update(val, 6, 6) +#define px30_lvds_vop_sel(val) hiword_update(val, 1, 1) +
|
Graphics
|
cca1705c3d895fcb67892fc8710005afd6d38541
|
miquel raynal
|
drivers
|
gpu
|
drm, rockchip
|
drm/virtio: use damage info for display updates.
|
v2: remove shift by src_{x,y}, drm_atomic_helper_damage_merged() handles that for us (chia-i wu).
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
fb damage support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['virtio-gpu ']
|
['c']
| 1
| 24
| 17
|
--- diff --git a/drivers/gpu/drm/virtio/virtgpu_plane.c b/drivers/gpu/drm/virtio/virtgpu_plane.c --- a/drivers/gpu/drm/virtio/virtgpu_plane.c +++ b/drivers/gpu/drm/virtio/virtgpu_plane.c +#include <drm/drm_damage_helper.h> - struct virtio_gpu_object *bo, - struct drm_plane_state *state) + struct drm_plane_state *state, + struct drm_rect *rect) + struct virtio_gpu_object *bo = + gem_to_virtio_gpu_obj(state->fb->obj[0]); + uint32_t w = rect->x2 - rect->x1; + uint32_t h = rect->y2 - rect->y1; + uint32_t x = rect->x1; + uint32_t y = rect->y1; + uint32_t off = x * state->fb->format->cpp[0] + + y * state->fb->pitches[0]; - virtio_gpu_cmd_transfer_to_host_2d - (vgdev, 0, - state->src_w >> 16, - state->src_h >> 16, - state->src_x >> 16, - state->src_y >> 16, - objs, null); + + virtio_gpu_cmd_transfer_to_host_2d(vgdev, off, w, h, x, y, + objs, null); - struct virtio_gpu_framebuffer *vgfb; + struct drm_rect rect; + if (!drm_atomic_helper_damage_merged(old_state, plane->state, &rect)) + return; + - vgfb = to_virtio_gpu_framebuffer(plane->state->fb); - bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); + bo = gem_to_virtio_gpu_obj(plane->state->fb->obj[0]); - virtio_gpu_update_dumb_bo(vgdev, bo, plane->state); + virtio_gpu_update_dumb_bo(vgdev, plane->state, &rect); - plane->state->src_x >> 16, - plane->state->src_y >> 16, - plane->state->src_w >> 16, - plane->state->src_h >> 16); + rect.x1, + rect.y1, + rect.x2 - rect.x1, + rect.y2 - rect.y1);
|
Graphics
|
c096761718de0a6ac3205d80b12292c943235c4b
|
gerd hoffmann chia i wu olvaffe gmail com
|
drivers
|
gpu
|
drm, virtio
|
dt-bindings: msm:disp: add sc7180 dpu variant
|
add a compatible string to support sc7180 dpu version.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for sc7180 display
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['txt']
| 1
| 2
| 2
|
--- diff --git a/documentation/devicetree/bindings/display/msm/dpu.txt b/documentation/devicetree/bindings/display/msm/dpu.txt --- a/documentation/devicetree/bindings/display/msm/dpu.txt +++ b/documentation/devicetree/bindings/display/msm/dpu.txt -- compatible: "qcom,sdm845-mdss" +- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss" - reg: physical base address and length of contoller's registers. - reg-names: register region names. the following region is required: -- compatible: "qcom,sdm845-dpu" +- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu" - reg: physical base address and length of controller's registers. - reg-names : register region names. the following region is required:
|
Graphics
|
854f94226a91010e81e09d79ba7ea253e64e6091
|
kalyan thota rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, display, msm
|
msm:disp:dpu1: add support for display for sc7180 target
|
add display hw catalog changes for sc7180 target.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for sc7180 display
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c', 'h']
| 5
| 188
| 13
|
- configure register offsets and capabilities for the - mdss_irq data type has changed in the dependent - add co-developed-by tags in the commit msg (stephen boyd). - fix kernel checkpatch errors in v2 - move documentation into seperate patch (rob herring). --- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c -#define vig_sdm845_mask \ - (bit(dpu_sspp_src) | bit(dpu_sspp_scaler_qseed3) | bit(dpu_sspp_qos) |\ +#define vig_mask \ + (bit(dpu_sspp_src) | bit(dpu_sspp_qos) |\ +#define vig_sdm845_mask \ + (vig_mask | bit(dpu_sspp_scaler_qseed3)) + +#define vig_sc7180_mask \ + (vig_mask | bit(dpu_sspp_scaler_qseed4)) + +#define mixer_sc7180_mask \ + (bit(dpu_dim_layer)) + +static const struct dpu_caps sc7180_dpu_caps = { + .max_mixer_width = default_dpu_output_line_width, + .max_mixer_blendstages = 0x9, + .qseed_type = dpu_sspp_scaler_qseed4, + .smart_dma_rev = dpu_sspp_smart_dma_v2, + .ubwc_version = dpu_hw_ubwc_ver_20, + .has_dim_layer = true, + .has_idle_pc = true, +}; + +static const struct dpu_mdp_cfg sc7180_mdp[] = { + { + .name = "top_0", .id = mdp_top, + .base = 0x0, .len = 0x494, + .features = 0, + .highest_bank_bit = 0x3, + .clk_ctrls[dpu_clk_ctrl_vig0] = { + .reg_off = 0x2ac, .bit_off = 0}, + .clk_ctrls[dpu_clk_ctrl_dma0] = { + .reg_off = 0x2ac, .bit_off = 8}, + .clk_ctrls[dpu_clk_ctrl_dma1] = { + .reg_off = 0x2b4, .bit_off = 8}, + .clk_ctrls[dpu_clk_ctrl_cursor0] = { + .reg_off = 0x2bc, .bit_off = 8}, + }, +}; + +static const struct dpu_ctl_cfg sc7180_ctl[] = { + { + .name = "ctl_0", .id = ctl_0, + .base = 0x1000, .len = 0xe4, + .features = bit(dpu_ctl_active_cfg) + }, + { + .name = "ctl_1", .id = ctl_1, + .base = 0x1200, .len = 0xe4, + .features = bit(dpu_ctl_active_cfg) + }, + { + .name = "ctl_2", .id = ctl_2, + .base = 0x1400, .len = 0xe4, + .features = bit(dpu_ctl_active_cfg) + }, +}; + +static const struct dpu_sspp_cfg sc7180_sspp[] = { + sspp_blk("sspp_0", sspp_vig0, 0x4000, vig_sc7180_mask, + sdm845_vig_sblk_0, 0, sspp_type_vig, dpu_clk_ctrl_vig0), + sspp_blk("sspp_8", sspp_dma0, 0x24000, dma_sdm845_mask, + sdm845_dma_sblk_0, 1, sspp_type_dma, dpu_clk_ctrl_dma0), + sspp_blk("sspp_9", sspp_dma1, 0x26000, dma_sdm845_mask, + sdm845_dma_sblk_1, 5, sspp_type_dma, dpu_clk_ctrl_dma1), + sspp_blk("sspp_10", sspp_dma2, 0x28000, dma_cursor_sdm845_mask, + sdm845_dma_sblk_2, 9, sspp_type_dma, dpu_clk_ctrl_cursor0), +}; + + +/* sdm845 */ + -#define lm_blk(_name, _id, _base, _pp, _lmpair) \ +#define lm_blk(_name, _id, _base, _fmask, _sblk, _pp, _lmpair) \ - .features = mixer_sdm845_mask, \ - .sblk = &sdm845_lm_sblk, \ + .features = _fmask, \ + .sblk = _sblk, \ - lm_blk("lm_0", lm_0, 0x44000, pingpong_0, lm_1), - lm_blk("lm_1", lm_1, 0x45000, pingpong_1, lm_0), - lm_blk("lm_2", lm_2, 0x46000, pingpong_2, lm_5), - lm_blk("lm_3", lm_3, 0x0, pingpong_max, 0), - lm_blk("lm_4", lm_4, 0x0, pingpong_max, 0), - lm_blk("lm_5", lm_5, 0x49000, pingpong_3, lm_2), + lm_blk("lm_0", lm_0, 0x44000, mixer_sdm845_mask, + &sdm845_lm_sblk, pingpong_0, lm_1), + lm_blk("lm_1", lm_1, 0x45000, mixer_sdm845_mask, + &sdm845_lm_sblk, pingpong_1, lm_0), + lm_blk("lm_2", lm_2, 0x46000, mixer_sdm845_mask, + &sdm845_lm_sblk, pingpong_2, lm_5), + lm_blk("lm_3", lm_3, 0x0, mixer_sdm845_mask, + &sdm845_lm_sblk, pingpong_max, 0), + lm_blk("lm_4", lm_4, 0x0, mixer_sdm845_mask, + &sdm845_lm_sblk, pingpong_max, 0), + lm_blk("lm_5", lm_5, 0x49000, mixer_sdm845_mask, + &sdm845_lm_sblk, pingpong_3, lm_2), +}; + +/* sc7180 */ + +static const struct dpu_lm_sub_blks sc7180_lm_sblk = { + .maxwidth = default_dpu_output_line_width, + .maxblendstages = 7, /* excluding base layer */ + .blendstage_base = { /* offsets relative to mixer base */ + 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 + }, +}; + +static const struct dpu_lm_cfg sc7180_lm[] = { + lm_blk("lm_0", lm_0, 0x44000, mixer_sc7180_mask, + &sc7180_lm_sblk, pingpong_0, lm_1), + lm_blk("lm_1", lm_1, 0x45000, mixer_sc7180_mask, + &sc7180_lm_sblk, pingpong_1, lm_0), +static struct dpu_pingpong_cfg sc7180_pp[] = { + pp_blk_te("pingpong_0", pingpong_0, 0x70000), + pp_blk_te("pingpong_1", pingpong_1, 0x70800), +}; + +static const struct dpu_intf_cfg sc7180_intf[] = { + intf_blk("intf_0", intf_0, 0x6a000, intf_dp, 0), + intf_blk("intf_1", intf_1, 0x6a800, intf_dsi, 0), +}; + +static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { + {.fl = 0, .lut = 0x0011222222335777}, +}; + +static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { + {.fl = 0, .lut = 0x0011223344556677}, +}; + +static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { + {.fl = 0, .lut = 0x0}, +}; + +static const struct dpu_perf_cfg sc7180_perf_data = { + .max_bw_low = 3900000, + .max_bw_high = 5500000, + .min_core_ib = 2400000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .danger_lut_tbl = {0xff, 0xffff, 0x0}, + .qos_lut_tbl = { + {.nentry = array_size(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = array_size(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = array_size(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, +}; + +/* + * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets + * and instance counts. + */ +static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) +{ + *dpu_cfg = (struct dpu_mdss_cfg){ + .caps = &sc7180_dpu_caps, + .mdp_count = array_size(sc7180_mdp), + .mdp = sc7180_mdp, + .ctl_count = array_size(sc7180_ctl), + .ctl = sc7180_ctl, + .sspp_count = array_size(sc7180_sspp), + .sspp = sc7180_sspp, + .mixer_count = array_size(sc7180_lm), + .mixer = sc7180_lm, + .pingpong_count = array_size(sc7180_pp), + .pingpong = sc7180_pp, + .intf_count = array_size(sc7180_intf), + .intf = sc7180_intf, + .vbif_count = array_size(sdm845_vbif), + .vbif = sdm845_vbif, + .reg_dma_count = 1, + .dma_cfg = sdm845_regdma, + .perf = sc7180_perf_data, + .mdss_irqs = 0x3f, + }; +} + + { .hw_rev = dpu_hw_ver_620, .cfg_init = sc7180_cfg_init}, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +#define dpu_hw_ver_620 dpu_hw_ver(6, 2, 0) /* sc7180 v1.0 */ +#define is_sc7180_target(rev) is_dpu_major_minor_same((rev), dpu_hw_ver_620) + dpu_sspp_scaler_qseed4, + dpu_ctl_active_cfg, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c - if (is_sdm845_target(m->hwversion) || is_sdm670_target(m->hwversion)) + if (is_sdm845_target(m->hwversion) || is_sdm670_target(m->hwversion) + || is_sc7180_target(m->hwversion)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c + { .compatible = "qcom,sc7180-dpu", }, diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c - of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss")) { + of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") || + of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) { + { .compatible = "qcom,sc7180-mdss", .data = (void *)kms_dpu },
|
Graphics
|
7bdc0c4b812602fb5678dcc477fe03679721e892
|
kalyan thota
|
drivers
|
gpu
|
disp, dpu1, drm, msm
|
msm:disp:dpu1: setup display datapath for sc7180 target
|
add changes to setup display datapath on sc7180 target.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for sc7180 display
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c', 'h']
| 6
| 159
| 5
|
- add changes to support ctl_active on sc7180 target. - while selecting the number of mixers in the topology - spawn topology mixer selection into separate patch (rob clark). - add co-developed-by tags in the commit msg (stephen boyd). - fix kernel checkpatch errors in v2. --- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c + + /* setup which pp blk will connect to this intf */ + if (phys_enc->hw_intf->ops.bind_pingpong_blk) + phys_enc->hw_intf->ops.bind_pingpong_blk( + phys_enc->hw_intf, + true, + phys_enc->hw_pp->idx); + + u32 intf_flush_mask = 0; + if (ctl->ops.get_bitmask_active_intf) + ctl->ops.get_bitmask_active_intf(ctl, &intf_flush_mask, + phys_enc->hw_intf->idx); + + if (ctl->ops.update_pending_intf_flush) + ctl->ops.update_pending_intf_flush(ctl, intf_flush_mask); + - "update pending flush ctl %d flush_mask %x ", - ctl->idx - ctl_0, flush_mask); + "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x ", + ctl->idx - ctl_0, flush_mask, intf_flush_mask); + diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c + .features = bit(dpu_ctl_active_cfg), \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +#define ctl_intf_active 0x0f4 +#define ctl_intf_flush 0x110 +#define ctl_intf_master 0x134 +#define intf_idx 31 +static inline void dpu_hw_ctl_update_pending_intf_flush(struct dpu_hw_ctl *ctx, + u32 flushbits) +{ + ctx->pending_intf_flush_mask |= flushbits; +} + +static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) +{ + + if (ctx->pending_flush_mask & bit(intf_idx)) + dpu_reg_write(&ctx->hw, ctl_intf_flush, + ctx->pending_intf_flush_mask); + + dpu_reg_write(&ctx->hw, ctl_flush, ctx->pending_flush_mask); +} + +static int dpu_hw_ctl_get_bitmask_intf_v1(struct dpu_hw_ctl *ctx, + u32 *flushbits, enum dpu_intf intf) +{ + switch (intf) { + case intf_0: + case intf_1: + *flushbits |= bit(31); + break; + default: + return 0; + } + return 0; +} + +static int dpu_hw_ctl_active_get_bitmask_intf(struct dpu_hw_ctl *ctx, + u32 *flushbits, enum dpu_intf intf) +{ + switch (intf) { + case intf_0: + *flushbits |= bit(0); + break; + case intf_1: + *flushbits |= bit(1); + break; + default: + return 0; + } + return 0; +} + + +static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx, + struct dpu_hw_intf_cfg *cfg) +{ + struct dpu_hw_blk_reg_map *c = &ctx->hw; + u32 intf_active = 0; + u32 mode_sel = 0; + + if (cfg->intf_mode_sel == dpu_ctl_mode_sel_cmd) + mode_sel |= bit(17); + + intf_active = dpu_reg_read(c, ctl_intf_active); + intf_active |= bit(cfg->intf - intf_0); + + dpu_reg_write(c, ctl_top, mode_sel); + dpu_reg_write(c, ctl_intf_active, intf_active); +} + + if (cap & bit(dpu_ctl_active_cfg)) { + ops->trigger_flush = dpu_hw_ctl_trigger_flush_v1; + ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1; + ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf_v1; + ops->get_bitmask_active_intf = + dpu_hw_ctl_active_get_bitmask_intf; + ops->update_pending_intf_flush = + dpu_hw_ctl_update_pending_intf_flush; + } else { + ops->trigger_flush = dpu_hw_ctl_trigger_flush; + ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg; + ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf; + } - ops->trigger_flush = dpu_hw_ctl_trigger_flush; - ops->setup_intf_cfg = dpu_hw_ctl_intf_cfg; - ops->get_bitmask_intf = dpu_hw_ctl_get_bitmask_intf; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h + /** + * or in the given flushbits to the cached pending_intf_flush_mask + * no effect on hardware + * @ctx : ctl path ctx pointer + * @flushbits : module flushmask + */ + void (*update_pending_intf_flush)(struct dpu_hw_ctl *ctx, + u32 flushbits); + + /** + * query the value of the intf flush mask + * no effect on hardware + * @ctx : ctl path ctx pointer + */ + /** + * query the value of the intf active flush mask + * no effect on hardware + * @ctx : ctl path ctx pointer + */ + int (*get_bitmask_active_intf)(struct dpu_hw_ctl *ctx, + u32 *flushbits, enum dpu_intf blk); + + * @pending_intf_flush_mask: pending intf flush + u32 pending_intf_flush_mask; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +#define intf_mux 0x25c + +static void dpu_hw_intf_bind_pingpong_blk( + struct dpu_hw_intf *intf, + bool enable, + const enum dpu_pingpong pp) +{ + struct dpu_hw_blk_reg_map *c; + u32 mux_cfg; + + if (!intf) + return; + + c = &intf->hw; + + mux_cfg = dpu_reg_read(c, intf_mux); + mux_cfg &= ~0xf; + + if (enable) + mux_cfg |= (pp - pingpong_0) & 0x7; + else + mux_cfg |= 0xf; + + dpu_reg_write(c, intf_mux, mux_cfg); +} + + if (cap & bit(dpu_ctl_active_cfg)) + ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h + * @bind_pingpong_blk: enable/disable the connection with pingpong which will + * feed pixels to this interface + + void (*bind_pingpong_blk)(struct dpu_hw_intf *intf, + bool enable, + const enum dpu_pingpong pp);
|
Graphics
|
73bfb790ac786ca55fa2786a06f59402a72b4163
|
kalyan thota
|
drivers
|
gpu
|
disp, dpu1, drm, msm
|
msm:disp:dpu1: add mixer selection for display topology
|
mixer selection in the display topology is based on multiple factors 1) mixers available in the hw 2) interfaces to be enabled 3) merge capability
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for sc7180 display
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c', 'h']
| 3
| 21
| 3
|
--- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c -#define max_vdisplay_split 1080 +#define max_hdisplay_split 1080 - /* user split topology for width > 1080 */ - topology.num_lm = (mode->vdisplay > max_vdisplay_split) ? 2 : 1; + /* datapath topology selection + * + * dual display + * 2 lm, 2 intf ( split display using 2 interfaces) + * + * single display + * 1 lm, 1 intf + * 2 lm, 1 intf (stream merge to support high resolution interfaces) + * + */ + if (intf_count == 2) + topology.num_lm = 2; + else if (!dpu_kms->catalog->caps->has_3d_merge) + topology.num_lm = 1; + else + topology.num_lm = (mode->hdisplay > max_hdisplay_split) ? 2 : 1; + diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c + .has_3d_merge = true, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h + * @has_3d_merge indicate if 3d merge is supported + bool has_3d_merge;
|
Graphics
|
42a558b71c9ead911a1486ca118c927e46e9d889
|
kalyan thota
|
drivers
|
gpu
|
disp, dpu1, drm, msm
|
drm/msm: add dsi support for sc7180
|
add support for v2.4.1 dsi block in the sc7180 soc.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add dsi support for sc7180
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c', 'h']
| 2
| 22
| 0
|
-modify commit text to indicate dsi version and soc detail(jeffrey hugo). -splitting visionox panel driver code out into a -update commit text accordingly(matthias kaehlcke). --- diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c +static const char * const dsi_sc7180_bus_clk_names[] = { + "iface", "bus", +}; + +static const struct msm_dsi_config sc7180_dsi_cfg = { + .io_offset = dsi_6g_reg_shift, + .reg_cfg = { + .num = 1, + .regs = { + {"vdda", 21800, 4 }, /* 1.2 v */ + }, + }, + .bus_clk_names = dsi_sc7180_bus_clk_names, + .num_bus_clks = array_size(dsi_sc7180_bus_clk_names), + .io_start = { 0xae94000 }, + .num_dsi = 1, +}; + + {msm_dsi_ver_major_6g, msm_dsi_6g_ver_minor_v2_4_1, + &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h +#define msm_dsi_6g_ver_minor_v2_4_1 0x20040001
|
Graphics
|
6125bd327e16a451efb5a00bc4224e164d19f77e
|
harigovindan p
|
drivers
|
gpu
|
drm, dsi, msm
|
msm:disp:dpu1: add ubwc support for display on sc7180
|
add ubwc global configuration for display on sc7180 target.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add ubwc support for display on sc7180
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c']
| 1
| 57
| 1
|
--- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c +#define hw_rev 0x0 +struct dpu_hw_cfg { + u32 val; + u32 offset; +}; + +struct dpu_mdss_hw_init_handler { + u32 hw_rev; + u32 hw_reg_count; + struct dpu_hw_cfg* hw_cfg; +}; + +static struct dpu_hw_cfg hw_cfg[] = { + { + /* ubwc global settings */ + .val = 0x1e, + .offset = 0x144, + } +}; + +static struct dpu_mdss_hw_init_handler cfg_handler[] = { + { .hw_rev = dpu_hw_ver_620, + .hw_reg_count = array_size(hw_cfg), + .hw_cfg = hw_cfg + }, +}; + +static void dpu_mdss_hw_init(struct dpu_mdss *dpu_mdss, u32 hw_rev) +{ + int i; + u32 count = 0; + struct dpu_hw_cfg *hw_cfg = null; + + for (i = 0; i < array_size(cfg_handler); i++) { + if (cfg_handler[i].hw_rev == hw_rev) { + hw_cfg = cfg_handler[i].hw_cfg; + count = cfg_handler[i].hw_reg_count; + break; + } + } + + for (i = 0; i < count; i++ ) { + writel_relaxed(hw_cfg->val, + dpu_mdss->mmio + hw_cfg->offset); + hw_cfg++; + } + + return; +} + + u32 mdss_rev; - if (ret) + if (ret) { + return ret; + } + + mdss_rev = readl_relaxed(dpu_mdss->mmio + hw_rev); + dpu_mdss_hw_init(dpu_mdss, mdss_rev);
|
Graphics
|
e4f9bbe9f8beab9a1ce460e7e194595b76868595
|
kalyan thota douglas anderson dianders chromium org
|
drivers
|
gpu
|
disp, dpu1, drm, msm
|
msm:disp:dpu1: add scaler support on sc7180 display
|
add scaler support for display driver.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add scaler support on sc7180 display
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c', 'h']
| 5
| 39
| 12
|
--- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c -#define _vig_sblk(num, sdma_pri) \ +#define _vig_sblk(num, sdma_pri, qseed_ver) \ - .id = dpu_sspp_scaler_qseed3, \ + .id = qseed_ver, \ -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _vig_sblk("0", 5); -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _vig_sblk("1", 6); -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _vig_sblk("2", 7); -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _vig_sblk("3", 8); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = + _vig_sblk("0", 5, dpu_sspp_scaler_qseed3); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = + _vig_sblk("1", 6, dpu_sspp_scaler_qseed3); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = + _vig_sblk("2", 7, dpu_sspp_scaler_qseed3); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = + _vig_sblk("3", 8, dpu_sspp_scaler_qseed3); +static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = + _vig_sblk("0", 4, dpu_sspp_scaler_qseed4); + - sdm845_vig_sblk_0, 0, sspp_type_vig, dpu_clk_ctrl_vig0), + sc7180_vig_sblk_0, 0, sspp_type_vig, dpu_clk_ctrl_vig0), diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h + * @dpu_sspp_scaler_qseed4, qseed4 algorithm support + * @qseed_ver: qseed version + u32 qseed_ver; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c + - if (test_bit(dpu_sspp_scaler_qseed3, &features)) { + if (test_bit(dpu_sspp_scaler_qseed3, &features) || + test_bit(dpu_sspp_scaler_qseed4, &features)) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h - (1ul << dpu_sspp_scaler_qseed3)) + (1ul << dpu_sspp_scaler_qseed3) | \ + (1ul << dpu_sspp_scaler_qseed4)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +/* + * default preload values + */ +#define dpu_qseed4_default_preload_v 0x2 +#define dpu_qseed4_default_preload_h 0x4 - scale_cfg->preload_x[i] = dpu_qseed3_default_preload_h; - scale_cfg->preload_y[i] = dpu_qseed3_default_preload_v; + + if (pdpu->pipe_hw->cap->features & + bit(dpu_sspp_scaler_qseed4)) { + scale_cfg->preload_x[i] = dpu_qseed4_default_preload_h; + scale_cfg->preload_y[i] = dpu_qseed4_default_preload_v; + } else { + scale_cfg->preload_x[i] = dpu_qseed3_default_preload_h; + scale_cfg->preload_y[i] = dpu_qseed3_default_preload_v; + } + - cfg->features & bit(dpu_sspp_scaler_qseed2)) { + cfg->features & bit(dpu_sspp_scaler_qseed2) || + cfg->features & bit(dpu_sspp_scaler_qseed4)) {
|
Graphics
|
b75ab05a34792fc203262a2f4a272f2a47257369
|
shubhashree dhar
|
drivers
|
gpu
|
disp, dpu1, drm, msm
|
drm: msm: add 618 gpu to the adreno gpu list
|
this patch adds adreno 618 entry and its associated properties to the gpulist entries.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
a618 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c']
| 1
| 11
| 0
|
--- diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c + }, { + .rev = adreno_rev(6, 1, 8, any_id), + .revn = 618, + .name = "a618", + .fw = { + [adreno_fw_sqe] = "a630_sqe.fw", + [adreno_fw_gmu] = "a630_gmu.bin", + }, + .gmem = sz_512k, + .inactive_period = drm_msm_inactive_period, + .init = a6xx_gpu_init,
|
Graphics
|
358ffda520db32e8719db4424edd72c25298decb
|
sharat masetty
|
drivers
|
gpu
|
adreno, drm, msm
|
drm: msm: a6xx: add support for a618
|
this patch adds support for enabling graphics bus interface(gbif) used in multiple a6xx series chipets. also makes changes to the pdc/rsc sequencing specifically required for a618. this is needed for proper interfacing with rpmh.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
a618 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['h', 'c']
| 5
| 154
| 13
|
--- diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13) - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13) - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54) -- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54) +- /home/smasetty/playarea/envytools/rnndb/adreno/a6xx.xml ( 161969 bytes, from 2019-11-29 07:18:16) - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07) - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13) -copyright (c) 2013-2018 by the following authors: +copyright (c) 2013-2019 by the following authors: - rob clark <robdclark@gmail.com> (robclark) - ilia mirkin <imirkin@alum.mit.edu> (imirkin) +#define reg_a6xx_gbif_scache_cntl1 0x00003c02 + +#define reg_a6xx_gbif_qsb_side0 0x00003c03 + +#define reg_a6xx_gbif_qsb_side1 0x00003c04 + +#define reg_a6xx_gbif_qsb_side2 0x00003c05 + +#define reg_a6xx_gbif_qsb_side3 0x00003c06 + +#define reg_a6xx_gbif_halt 0x00003c45 + +#define reg_a6xx_gbif_halt_ack 0x00003c46 + +#define reg_a6xx_gbif_perf_pwr_cnt_en 0x00003cc0 + +#define reg_a6xx_gbif_perf_cnt_sel 0x00003cc2 + +#define reg_a6xx_gbif_perf_pwr_cnt_sel 0x00003cc3 + +#define reg_a6xx_gbif_perf_cnt_low0 0x00003cc4 + +#define reg_a6xx_gbif_perf_cnt_low1 0x00003cc5 + +#define reg_a6xx_gbif_perf_cnt_low2 0x00003cc6 + +#define reg_a6xx_gbif_perf_cnt_low3 0x00003cc7 + +#define reg_a6xx_gbif_perf_cnt_high0 0x00003cc8 + +#define reg_a6xx_gbif_perf_cnt_high1 0x00003cc9 + +#define reg_a6xx_gbif_perf_cnt_high2 0x00003cca + +#define reg_a6xx_gbif_perf_cnt_high3 0x00003ccb + +#define reg_a6xx_gbif_pwr_cnt_low0 0x00003ccc + +#define reg_a6xx_gbif_pwr_cnt_low1 0x00003ccd + +#define reg_a6xx_gbif_pwr_cnt_low2 0x00003cce + +#define reg_a6xx_gbif_pwr_cnt_high0 0x00003ccf + +#define reg_a6xx_gbif_pwr_cnt_high1 0x00003cd0 + +#define reg_a6xx_gbif_pwr_cnt_high2 0x00003cd1 + diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c -/* copyright (c) 2017-2018 the linux foundation. all rights reserved. */ +/* copyright (c) 2017-2019 the linux foundation. all rights reserved. */ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + - pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs1_cmd0_addr + 8, 0x30080); + if (adreno_is_a618(adreno_gpu)) + pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs1_cmd0_addr + 8, 0x30090); + else + pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs1_cmd0_addr + 8, 0x30080); + + - pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs3_cmd0_data + 4, 0x3); + if (adreno_is_a618(adreno_gpu)) + pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs3_cmd0_data + 4, 0x2); + else + pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs3_cmd0_data + 4, 0x3); + + - pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs3_cmd0_addr + 8, 0x30080); + if (adreno_is_a618(adreno_gpu)) + pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs3_cmd0_addr + 8, 0x30090); + else + pdc_write(pdcptr, reg_a6xx_pdc_gpu_tcs3_cmd0_addr + 8, 0x30080); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c -/* copyright (c) 2017-2018 the linux foundation. all rights reserved. */ +/* copyright (c) 2017-2019 the linux foundation. all rights reserved. */ + /* + * during a previous slumber, gbif halt is asserted to ensure + * no further transaction can go through gpu before gpu + * headswitch is turned off. + * + * this halt is deasserted once headswitch goes off but + * incase headswitch doesn't goes off clear gbif halt + * here to ensure gpu wake-up doesn't fail because of + * halted gpu transactions. + */ + gpu_write(gpu, reg_a6xx_gbif_halt, 0x0); + - /* enable hardware clockgating */ - a6xx_set_hwcg(gpu, true); + /* + * enable hardware clockgating + * for now enable clock gating only for a630 + */ + if (adreno_is_a630(adreno_gpu)) + a6xx_set_hwcg(gpu, true); - /* vbif start */ - gpu_write(gpu, reg_a6xx_vbif_gate_off_wrreq_en, 0x00000009); + /* vbif/gbif start*/ + if (adreno_is_a630(adreno_gpu)) + gpu_write(gpu, reg_a6xx_vbif_gate_off_wrreq_en, 0x00000009); +#define gbif_client_halt_mask bit(0) +#define gbif_arb_halt_mask bit(1) + +static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu) +{ + struct msm_gpu *gpu = &adreno_gpu->base; + + if(!a6xx_has_gbif(adreno_gpu)){ + gpu_write(gpu, reg_a6xx_vbif_xin_halt_ctrl0, 0xf); + spin_until((gpu_read(gpu, reg_a6xx_vbif_xin_halt_ctrl1) & + 0xf) == 0xf); + gpu_write(gpu, reg_a6xx_vbif_xin_halt_ctrl0, 0); + + return; + } + + /* halt new client requests on gbif */ + gpu_write(gpu, reg_a6xx_gbif_halt, gbif_client_halt_mask); + spin_until((gpu_read(gpu, reg_a6xx_gbif_halt_ack) & + (gbif_client_halt_mask)) == gbif_client_halt_mask); + + /* halt all axi requests on gbif */ + gpu_write(gpu, reg_a6xx_gbif_halt, gbif_arb_halt_mask); + spin_until((gpu_read(gpu, reg_a6xx_gbif_halt_ack) & + (gbif_arb_halt_mask)) == gbif_arb_halt_mask); + + /* + * gmu needs ddr access in slumber path. deassert gbif halt now + * to allow for gmu to access system memory. + */ + gpu_write(gpu, reg_a6xx_gbif_halt, 0x0); +} + + /* + * make sure the gmu is idle before continuing (because some transitions + * may use vbif + */ + a6xx_gmu_wait_for_idle(&a6xx_gpu->gmu); + + /* clear the vbif pipe before shutting down */ + /* fixme: this accesses the gpu - do we need to make sure it is on? */ + a6xx_bus_clear_pending_transactions(adreno_gpu); + diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h -/* copyright (c) 2017 the linux foundation. all rights reserved. */ +/* copyright (c) 2017, 2019 the linux foundation. all rights reserved. */ +static inline bool a6xx_has_gbif(struct adreno_gpu *gpu) +{ + if(adreno_is_a630(gpu)) + return false; + + return true; +} diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h - * copyright (c) 2014,2017 the linux foundation. all rights reserved. + * copyright (c) 2014,2017, 2019 the linux foundation. all rights reserved. +static inline int adreno_is_a618(struct adreno_gpu *gpu) +{ + return gpu->revn == 618; +} + +static inline int adreno_is_a630(struct adreno_gpu *gpu) +{ + return gpu->revn == 630; +} +
|
Graphics
|
e812744c5f953cb8bbce2d8cfbcb2e8e7df7535d
|
sharat masetty
|
drivers
|
gpu
|
adreno, drm, msm
|
drm/msm/dpu: add ubwc support for rgb8888 formats
|
hardware only natively supports bgr8888 ubwc. ubwc support for rgb8888 can be had by pretending that the buffer is bgr.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add ubwc support for rgb8888 formats
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c', 'h']
| 2
| 20
| 0
|
--- diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c + /* argb8888 and abgr8888 purposely have the same color + * ordering. the hardware only supports abgr8888 ubwc + * natively. + */ + interleaved_rgb_fmt_tiled(argb8888, + color_8bit, color_8bit, color_8bit, color_8bit, + c2_r_cr, c0_g_y, c1_b_cb, c3_alpha, 4, + true, 4, dpu_format_flag_compressed, + dpu_fetch_ubwc, 2, dpu_tile_height_ubwc), + + interleaved_rgb_fmt_tiled(xrgb8888, + color_8bit, color_8bit, color_8bit, color_8bit, + c2_r_cr, c0_g_y, c1_b_cb, c3_alpha, 4, + false, 4, dpu_format_flag_compressed, + dpu_fetch_ubwc, 2, dpu_tile_height_ubwc), + + {drm_format_argb8888, color_fmt_rgba8888_ubwc}, + {drm_format_xrgb8888, color_fmt_rgba8888_ubwc}, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h + drm_format_argb8888, + drm_format_xrgb8888,
|
Graphics
|
cb929b8f5faa2a94c2f28e656e243e3ec173b480
|
fritz koenig daniel vetter daniel vetter ffwll ch rob clark robdclark gmail com
|
drivers
|
gpu
|
disp, dpu1, drm, msm
|
drm/msm: support firmware-name for zap fw (v2)
|
since zap firmware can be device specific, allow for a firmware-name property in the zap node to specify which firmware to load, similarly to the scheme used for dsp/wifi/etc.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
support firmware-name for zap fw
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['msm ']
|
['c']
| 1
| 27
| 3
|
--- diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c + const char *signed_fwname = null; - /* request the mdt file for the firmware */ - fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); + /* + * check for a firmware-name property. this is the new scheme + * to handle firmware that may be signed with device specific + * keys, allowing us to have a different zap fw path for different + * devices. + * + * if the firmware-name property is found, we bypass the + * adreno_request_fw() mechanism, because we don't need to handle + * the /lib/firmware/qcom/* vs /lib/firmware/* case. + * + * if the firmware-name property is not found, for backwards + * compatibility we fall back to the fwname from the gpulist + * table. + */ + of_property_read_string_index(np, "firmware-name", 0, &signed_fwname); + if (signed_fwname) { + fwname = signed_fwname; + ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); + if (ret) + fw = err_ptr(ret); + } else { + /* request the mdt file from the default location: */ + fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); + } + - if (to_adreno_gpu(gpu)->fwloc == fw_location_legacy) { + if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == fw_location_legacy)) {
|
Graphics
|
6a0dea02c2c4fabacaef639b215b1cbbbea662a6
|
rob clark
|
drivers
|
gpu
|
adreno, drm, msm
|
drm/vmwgfx: add ioctl for messaging from/to guest userspace to/from host
|
up to now, guest userspace does logging directly to host using essentially the same rather complex port assembly stuff as the kernel. we'd rather use the same mechanism than duplicate it (it may also change in the future), hence add a new ioctl for relaying guest/host messaging (logging is just one application of it).
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add ioctl for messaging from/to guest userspace to/from host
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['vmwgfx ']
|
['c', 'h']
| 4
| 108
| 0
|
--- diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +#define drm_ioctl_vmw_msg \ + drm_iowr(drm_command_base + drm_vmw_msg, \ + struct drm_vmw_msg_arg) + vmw_ioctl_def(vmw_msg, + vmw_msg_ioctl, + drm_render_allow), diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +int vmw_msg_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c --- a/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_msg.c +#define max_user_msg_length page_size + + + +/** + * vmw_msg_ioctl: sends and receveives a message to/from host from/to user-space + * + * sends a message from user-space to host. + * can also receive a result from host and return that to user-space. + * + * @dev: identifies the drm device. + * @data: pointer to the ioctl argument. + * @file_priv: identifies the caller. + * return: zero on success, negative error code on error. + */ + +int vmw_msg_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv) +{ + struct drm_vmw_msg_arg *arg = + (struct drm_vmw_msg_arg *) data; + struct rpc_channel channel; + char *msg; + int length; + + msg = kmalloc(max_user_msg_length, gfp_kernel); + if (!msg) { + drm_error("cannot allocate memory for log message. "); + return -enomem; + } + + length = strncpy_from_user(msg, (void __user *)((unsigned long)arg->send), + max_user_msg_length); + if (length < 0 || length >= max_user_msg_length) { + drm_error("userspace message access failure. "); + kfree(msg); + return -einval; + } + + + if (vmw_open_channel(&channel, rpci_protocol_num)) { + drm_error("failed to open channel. "); + goto out_open; + } + + if (vmw_send_msg(&channel, msg)) { + drm_error("failed to send message to host. "); + goto out_msg; + } + + if (!arg->send_only) { + char *reply = null; + size_t reply_len = 0; + + if (vmw_recv_msg(&channel, (void *) &reply, &reply_len)) { + drm_error("failed to receive message from host. "); + goto out_msg; + } + if (reply && reply_len > 0) { + if (copy_to_user((void __user *)((unsigned long)arg->receive), + reply, reply_len)) { + drm_error("failed to copy message to userspace. "); + kfree(reply); + goto out_msg; + } + arg->receive_len = (__u32)reply_len; + } + kfree(reply); + } + + vmw_close_channel(&channel); + kfree(msg); + + return 0; + +out_msg: + vmw_close_channel(&channel); +out_open: + kfree(msg); + + return -einval; +} + diff --git a/include/uapi/drm/vmwgfx_drm.h b/include/uapi/drm/vmwgfx_drm.h --- a/include/uapi/drm/vmwgfx_drm.h +++ b/include/uapi/drm/vmwgfx_drm.h +#define drm_vmw_msg 29 +/** + * struct drm_vmw_msg_arg + * + * @send: pointer to user-space msg string (null terminated). + * @receive: pointer to user-space receive buffer. + * @send_only: boolean whether this is only sending or receiving too. + * + * argument to the drm_vmw_msg ioctl. + */ +struct drm_vmw_msg_arg { + __u64 send; + __u64 receive; + __s32 send_only; + __u32 receive_len; +}; +
|
Graphics
|
cb92a3235956442c5ff211291865e219dc4cf4a0
|
roland scheidegger thomas hellstrom thellstrom vmware com
|
drivers
|
gpu
|
drm, vmwgfx
|
drm/mediatek: support cmdq interface in ddp component
|
the cmdq (command queue) in some mediatek soc is used to help update all relevant display controller registers with critical time limation. this patch add cmdq interface in ddp_comp interface, let all ddp_comp interface can support cpu/cmdq function at the same time.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
support cmdq interface in ddp component
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['mediatek ']
|
['c', 'h']
| 6
| 186
| 94
|
--- diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c --- a/drivers/gpu/drm/mediatek/mtk_disp_color.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c +#include <linux/soc/mediatek/mtk-cmdq.h> - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel(w, comp->regs + disp_color_width(color)); - writel(h, comp->regs + disp_color_height(color)); + mtk_ddp_write(cmdq_pkt, w, comp, disp_color_width(color)); + mtk_ddp_write(cmdq_pkt, h, comp, disp_color_height(color)); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +#include <linux/soc/mediatek/mtk-cmdq.h> - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel_relaxed(h << 16 | w, comp->regs + disp_reg_ovl_roi_size); - writel_relaxed(0x0, comp->regs + disp_reg_ovl_roi_bgclr); + mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp, + disp_reg_ovl_roi_size); + mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, disp_reg_ovl_roi_bgclr); - writel(0x1, comp->regs + disp_reg_ovl_rst); - writel(0x0, comp->regs + disp_reg_ovl_rst); + mtk_ddp_write(cmdq_pkt, 0x1, comp, disp_reg_ovl_rst); + mtk_ddp_write(cmdq_pkt, 0x0, comp, disp_reg_ovl_rst); -static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) +static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx, + struct cmdq_pkt *cmdq_pkt) - unsigned int reg; - writel(0x1, comp->regs + disp_reg_ovl_rdma_ctrl(idx)); - + mtk_ddp_write(cmdq_pkt, 0x1, comp, + disp_reg_ovl_rdma_ctrl(idx)); - writel(gmc_value, comp->regs + disp_reg_ovl_rdma_gmc(idx)); - - reg = readl(comp->regs + disp_reg_ovl_src_con); - reg = reg | bit(idx); - writel(reg, comp->regs + disp_reg_ovl_src_con); + mtk_ddp_write(cmdq_pkt, gmc_value, + comp, disp_reg_ovl_rdma_gmc(idx)); + mtk_ddp_write_mask(cmdq_pkt, bit(idx), comp, + disp_reg_ovl_src_con, bit(idx)); -static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) +static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx, + struct cmdq_pkt *cmdq_pkt) - unsigned int reg; - - reg = readl(comp->regs + disp_reg_ovl_src_con); - reg = reg & ~bit(idx); - writel(reg, comp->regs + disp_reg_ovl_src_con); - - writel(0x0, comp->regs + disp_reg_ovl_rdma_ctrl(idx)); + mtk_ddp_write_mask(cmdq_pkt, 0, comp, + disp_reg_ovl_src_con, bit(idx)); + mtk_ddp_write(cmdq_pkt, 0, comp, + disp_reg_ovl_rdma_ctrl(idx)); - struct mtk_plane_state *state) + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) - mtk_ovl_layer_off(comp, idx); + mtk_ovl_layer_off(comp, idx, cmdq_pkt); - writel_relaxed(con, comp->regs + disp_reg_ovl_con(idx)); - writel_relaxed(pitch, comp->regs + disp_reg_ovl_pitch(idx)); - writel_relaxed(src_size, comp->regs + disp_reg_ovl_src_size(idx)); - writel_relaxed(offset, comp->regs + disp_reg_ovl_offset(idx)); - writel_relaxed(addr, comp->regs + disp_reg_ovl_addr(ovl, idx)); + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, + disp_reg_ovl_con(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, + disp_reg_ovl_pitch(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp, + disp_reg_ovl_src_size(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, offset, comp, + disp_reg_ovl_offset(idx)); + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, + disp_reg_ovl_addr(ovl, idx)); - mtk_ovl_layer_on(comp, idx); + mtk_ovl_layer_on(comp, idx, cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +#include <linux/soc/mediatek/mtk-cmdq.h> - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - rdma_update_bits(comp, disp_reg_rdma_size_con_0, 0xfff, width); - rdma_update_bits(comp, disp_reg_rdma_size_con_1, 0xfffff, height); + mtk_ddp_write_mask(cmdq_pkt, width, comp, + disp_reg_rdma_size_con_0, 0xfff); + mtk_ddp_write_mask(cmdq_pkt, height, comp, + disp_reg_rdma_size_con_1, 0xfffff); - writel(reg, comp->regs + disp_reg_rdma_fifo_con); + mtk_ddp_write(cmdq_pkt, reg, comp, disp_reg_rdma_fifo_con); - struct mtk_plane_state *state) + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) - writel_relaxed(con, comp->regs + disp_rdma_mem_con); + mtk_ddp_write_relaxed(cmdq_pkt, con, comp, disp_rdma_mem_con); - rdma_update_bits(comp, disp_reg_rdma_size_con_0, - rdma_matrix_enable, rdma_matrix_enable); - rdma_update_bits(comp, disp_reg_rdma_size_con_0, - rdma_matrix_int_mtx_sel, - rdma_matrix_int_mtx_bt601_to_rgb); + mtk_ddp_write_mask(cmdq_pkt, rdma_matrix_enable, comp, + disp_reg_rdma_size_con_0, + rdma_matrix_enable); + mtk_ddp_write_mask(cmdq_pkt, rdma_matrix_int_mtx_bt601_to_rgb, + comp, disp_reg_rdma_size_con_0, + rdma_matrix_int_mtx_sel); - rdma_update_bits(comp, disp_reg_rdma_size_con_0, - rdma_matrix_enable, 0); + mtk_ddp_write_mask(cmdq_pkt, 0, comp, + disp_reg_rdma_size_con_0, + rdma_matrix_enable); + mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, disp_rdma_mem_start_addr); + mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, disp_rdma_mem_src_pitch); + mtk_ddp_write(cmdq_pkt, rdma_mem_gmc, comp, + disp_rdma_mem_gmc_setting_0); + mtk_ddp_write_mask(cmdq_pkt, rdma_mode_memory, comp, + disp_reg_rdma_global_con, rdma_mode_memory); - writel_relaxed(addr, comp->regs + disp_rdma_mem_start_addr); - writel_relaxed(pitch, comp->regs + disp_rdma_mem_src_pitch); - writel(rdma_mem_gmc, comp->regs + disp_rdma_mem_gmc_setting_0); - rdma_update_bits(comp, disp_reg_rdma_global_con, - rdma_mode_memory, rdma_mode_memory); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c - mtk_ddp_comp_config(comp, width, height, vrefresh, bpc); + mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, null); - plane_state); + plane_state, null); - state->pending_vrefresh, 0); + state->pending_vrefresh, 0, null); - plane_state); + plane_state, null); - plane_state); + plane_state, null); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c - +#include <linux/soc/mediatek/mtk-cmdq.h> +void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset) +{ +#if is_reachable(config_mtk_cmdq) + if (cmdq_pkt) + cmdq_pkt_write(cmdq_pkt, comp->subsys, + comp->regs_pa + offset, value); + else +#endif + writel(value, comp->regs + offset); +} + +void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, + unsigned int offset) +{ +#if is_reachable(config_mtk_cmdq) + if (cmdq_pkt) + cmdq_pkt_write(cmdq_pkt, comp->subsys, + comp->regs_pa + offset, value); + else +#endif + writel_relaxed(value, comp->regs + offset); +} + +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, + unsigned int value, + struct mtk_ddp_comp *comp, + unsigned int offset, + unsigned int mask) +{ +#if is_reachable(config_mtk_cmdq) + if (cmdq_pkt) { + cmdq_pkt_write_mask(cmdq_pkt, comp->subsys, + comp->regs_pa + offset, value, mask); + } else { +#endif + u32 tmp = readl(comp->regs + offset); + + tmp = (tmp & ~mask) | (value & mask); + writel(tmp, comp->regs + offset); +#if is_reachable(config_mtk_cmdq) + } +#endif +} + - unsigned int cfg) + unsigned int cfg, struct cmdq_pkt *cmdq_pkt) - writel(0, comp->regs + disp_dither_5); - writel(0, comp->regs + disp_dither_7); - writel(dither_lsb_err_shift_r(mtk_max_bpc - bpc) | - dither_add_lshift_r(mtk_max_bpc - bpc) | - dither_new_bit_mode, - comp->regs + disp_dither_15); - writel(dither_lsb_err_shift_b(mtk_max_bpc - bpc) | - dither_add_lshift_b(mtk_max_bpc - bpc) | - dither_lsb_err_shift_g(mtk_max_bpc - bpc) | - dither_add_lshift_g(mtk_max_bpc - bpc), - comp->regs + disp_dither_16); - writel(disp_dithering, comp->regs + cfg); + mtk_ddp_write(cmdq_pkt, 0, comp, disp_dither_5); + mtk_ddp_write(cmdq_pkt, 0, comp, disp_dither_7); + mtk_ddp_write(cmdq_pkt, + dither_lsb_err_shift_r(mtk_max_bpc - bpc) | + dither_add_lshift_r(mtk_max_bpc - bpc) | + dither_new_bit_mode, + comp, disp_dither_15); + mtk_ddp_write(cmdq_pkt, + dither_lsb_err_shift_b(mtk_max_bpc - bpc) | + dither_add_lshift_b(mtk_max_bpc - bpc) | + dither_lsb_err_shift_g(mtk_max_bpc - bpc) | + dither_add_lshift_g(mtk_max_bpc - bpc), + comp, disp_dither_16); + mtk_ddp_write(cmdq_pkt, disp_dithering, comp, cfg); - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel(w << 16 | h, comp->regs + disp_od_size); - writel(od_relaymode, comp->regs + disp_od_cfg); - mtk_dither_set(comp, bpc, disp_od_cfg); + mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, disp_od_size); + mtk_ddp_write(cmdq_pkt, od_relaymode, comp, disp_od_cfg); + mtk_dither_set(comp, bpc, disp_od_cfg, cmdq_pkt); - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel(h << 16 | w, comp->regs + disp_aal_size); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, disp_aal_size); - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel(h << 16 | w, comp->regs + disp_ccorr_size); - writel(ccorr_relay_mode, comp->regs + disp_ccorr_cfg); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, disp_ccorr_size); + mtk_ddp_write(cmdq_pkt, ccorr_relay_mode, comp, disp_ccorr_cfg); - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel(h << 16 | w, comp->regs + disp_dither_size); - writel(dither_relay_mode, comp->regs + disp_dither_cfg); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, disp_dither_size); + mtk_ddp_write(cmdq_pkt, dither_relay_mode, comp, disp_dither_cfg); - unsigned int bpc) + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) - writel(h << 16 | w, comp->regs + disp_gamma_size); - mtk_dither_set(comp, bpc, disp_gamma_cfg); + mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, disp_gamma_size); + mtk_dither_set(comp, bpc, disp_gamma_cfg, cmdq_pkt); +#if is_reachable(config_mtk_cmdq) + struct resource res; + struct cmdq_client_reg cmdq_reg; + int ret; +#endif +#if is_reachable(config_mtk_cmdq) + if (of_address_to_resource(node, 0, &res) != 0) { + dev_err(dev, "missing reg in %s node ", node->full_name); + return -einval; + } + comp->regs_pa = res.start; + + ret = cmdq_dev_get_client_reg(dev, &cmdq_reg, 0); + if (ret) + dev_dbg(dev, "get mediatek,gce-client-reg fail! "); + else + comp->subsys = cmdq_reg.subsys; +#endif diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h - +struct cmdq_pkt; - unsigned int h, unsigned int vrefresh, unsigned int bpc); + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt); - struct mtk_plane_state *state); + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt); + resource_size_t regs_pa; + u8 subsys; - unsigned int vrefresh, unsigned int bpc) + unsigned int vrefresh, unsigned int bpc, + struct cmdq_pkt *cmdq_pkt) - comp->funcs->config(comp, w, h, vrefresh, bpc); + comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt); - struct mtk_plane_state *state) + struct mtk_plane_state *state, + struct cmdq_pkt *cmdq_pkt) - comp->funcs->layer_config(comp, idx, state); + comp->funcs->layer_config(comp, idx, state, cmdq_pkt); - unsigned int cfg); - + unsigned int cfg, struct cmdq_pkt *cmdq_pkt); +enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id); +void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset); +void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset); +void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, + struct mtk_ddp_comp *comp, unsigned int offset, + unsigned int mask);
|
Graphics
|
d0afe37f5209c7b51a5646ffef578b9d9b383d90
|
bibby hsieh
|
drivers
|
gpu
|
drm, mediatek
|
drm/mediatek: add ctm property support
|
add ctm property support
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add ctm property support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['mediatek ']
|
['c', 'h']
| 3
| 82
| 5
|
--- diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c - for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) + for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) { + mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state); + } + bool has_ctm = false; - if (comp->funcs && comp->funcs->gamma_set) - gamma_lut_size = mtk_lut_size; + if (comp->funcs) { + if (comp->funcs->gamma_set) + gamma_lut_size = mtk_lut_size; + + if (comp->funcs->ctm_set) + has_ctm = true; + } - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size); + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +#define ccorr_engine_en bit(1) +#define ccorr_gamma_off bit(2) +#define ccorr_wgamut_src_clip bit(3) +#define disp_ccorr_coef_0 0x0080 +#define disp_ccorr_coef_1 0x0084 +#define disp_ccorr_coef_2 0x0088 +#define disp_ccorr_coef_3 0x008c +#define disp_ccorr_coef_4 0x0090 - mtk_ddp_write(cmdq_pkt, ccorr_relay_mode, comp, disp_ccorr_cfg); + mtk_ddp_write(cmdq_pkt, ccorr_engine_en, comp, disp_ccorr_cfg); +/* converts a drm s31.32 value to the hw s1.10 format. */ +static u16 mtk_ctm_s31_32_to_s1_10(u64 in) +{ + u16 r; + + /* sign bit. */ + r = in & bit_ull(63) ? bit(11) : 0; + + if ((in & genmask_ull(62, 33)) > 0) { + /* identity value 0x100000000 -> 0x400, */ + /* if bigger this, set it to max 0x7ff. */ + r |= genmask(10, 0); + } else { + /* take the 11 most important bits. */ + r |= (in >> 22) & genmask(10, 0); + } + + return r; +} + +static void mtk_ccorr_ctm_set(struct mtk_ddp_comp *comp, + struct drm_crtc_state *state) +{ + struct drm_property_blob *blob = state->ctm; + struct drm_color_ctm *ctm; + const u64 *input; + uint16_t coeffs[9] = { 0 }; + int i; + struct cmdq_pkt *cmdq_pkt = null; + + if (!blob) + return; + + ctm = (struct drm_color_ctm *)blob->data; + input = ctm->matrix; + + for (i = 0; i < array_size(coeffs); i++) + coeffs[i] = mtk_ctm_s31_32_to_s1_10(input[i]); + + mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1], + comp, disp_ccorr_coef_0); + mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3], + comp, disp_ccorr_coef_1); + mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5], + comp, disp_ccorr_coef_2); + mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7], + comp, disp_ccorr_coef_3); + mtk_ddp_write(cmdq_pkt, coeffs[8] << 16, + comp, disp_ccorr_coef_4); +} + + .ctm_set = mtk_ccorr_ctm_set, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h + void (*ctm_set)(struct mtk_ddp_comp *comp, + struct drm_crtc_state *state); +static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp, + struct drm_crtc_state *state) +{ + if (comp->funcs && comp->funcs->ctm_set) + comp->funcs->ctm_set(comp, state); +} +
|
Graphics
|
84abcf1234bbfbcc0b8749bcf9c9ca01525eea50
|
yongqiang niu
|
drivers
|
gpu
|
drm, mediatek
|
drm/mediatek: add gamma property according to hardware capability
|
if there is no gamma function in the crtc display path, don't add gamma property for crtc
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add gamma property according to hardware capability
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['mediatek ']
|
['c']
| 1
| 8
| 2
|
--- diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c + uint gamma_lut_size = 0; + + if (comp->funcs && comp->funcs->gamma_set) + gamma_lut_size = mtk_lut_size; - drm_mode_crtc_set_gamma_size(&mtk_crtc->base, mtk_lut_size); - drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, mtk_lut_size); + + if (gamma_lut_size) + drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size); + drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, gamma_lut_size);
|
Graphics
|
4cebc1de506fa753301266a5a23bb21bca52ad3a
|
yongqiang niu
|
drivers
|
gpu
|
drm, mediatek
|
drm: sun4i: add support for suspending the display driver
|
shut down the display engine during suspend.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
add support for suspending the display driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['sun4i ']
|
['c']
| 1
| 22
| 0
|
--- diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c --- a/drivers/gpu/drm/sun4i/sun4i_drv.c +++ b/drivers/gpu/drm/sun4i/sun4i_drv.c +#ifdef config_pm_sleep +static int sun4i_drv_drm_sys_suspend(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + + return drm_mode_config_helper_suspend(drm); +} + +static int sun4i_drv_drm_sys_resume(struct device *dev) +{ + struct drm_device *drm = dev_get_drvdata(dev); + + return drm_mode_config_helper_resume(drm); +} +#endif + +static const struct dev_pm_ops sun4i_drv_drm_pm_ops = { + set_system_sleep_pm_ops(sun4i_drv_drm_sys_suspend, + sun4i_drv_drm_sys_resume) +}; + + .pm = &sun4i_drv_drm_pm_ops,
|
Graphics
|
624b4b48d9d870c2858c016d8709715495409654
|
ondrej jirman
|
drivers
|
gpu
|
drm, sun4i
|
drm/sun4i: dsi: add allwinner a64 mipi dsi support
|
the mipi dsi controller in allwinner a64 is similar to a33.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
a64 mipi dsi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['sun4i ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c + { .compatible = "allwinner,sun50i-a64-mipi-dsi" },
|
Graphics
|
52028bfcb2330189c5e4ab943b3530b2117b8525
|
jagan teki
|
drivers
|
gpu
|
drm, sun4i
|
dt-bindings: display: renesas,cmm: add r-car cmm documentation
|
add device tree bindings documentation for the renesas r-car display unit color management module.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
color management module support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['yaml']
| 1
| 67
| 0
|
--- diff --git a/documentation/devicetree/bindings/display/renesas,cmm.yaml b/documentation/devicetree/bindings/display/renesas,cmm.yaml --- /dev/null +++ b/documentation/devicetree/bindings/display/renesas,cmm.yaml +# spdx-license-identifier: gpl-2.0-only +%yaml 1.2 +--- +$id: http://devicetree.org/schemas/display/renesas,cmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: renesas r-car color management module (cmm) + +maintainers: + - laurent pinchart <laurent.pinchart@ideasonboard.com> + - kieran bingham <kieran.bingham+renesas@ideasonboard.com> + - jacopo mondi <jacopo+renesas@jmondi.org> + +description: |+ + renesas r-car color management module connected to r-car du video channels. + it provides image enhancement functions such as 1-d look-up tables (lut), + 3-d look-up tables (clu), 1d-histogram generation (hgo), and color + space conversion (csc). + +properties: + compatible: + oneof: + - items: + - enum: + - renesas,r8a7795-cmm + - renesas,r8a7796-cmm + - renesas,r8a77965-cmm + - renesas,r8a77990-cmm + - renesas,r8a77995-cmm + - const: renesas,rcar-gen3-cmm + - items: + - const: renesas,rcar-gen2-cmm + + reg: + maxitems: 1 + + clocks: + maxitems: 1 + + resets: + maxitems: 1 + + power-domains: + maxitems: 1 + +required: + - compatible + - reg + - clocks + - resets + - power-domains + +additionalproperties: false + +examples: + - | + #include <dt-bindings/clock/r8a7796-cpg-mssr.h> + #include <dt-bindings/power/r8a7796-sysc.h> + + cmm0: cmm@fea40000 { + compatible = "renesas,r8a7796-cmm", + "renesas,rcar-gen3-cmm"; + reg = <0 0xfea40000 0 0x1000>; + power-domains = <&sysc r8a7796_pd_always_on>; + clocks = <&cpg cpg_mod 711>; + resets = <&cpg 711>; + };
|
Graphics
|
7f7b9455b35290a1032c73222261bfd784cc3702
|
jacopo mondi
|
documentation
|
devicetree
|
bindings, display
|
dt-bindings: display: renesas,du: document cmms property
|
document the newly added 'renesas,cmms' property which accepts a list of phandle and channel index pairs that point to the cmm units available for each display unit output video channel.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
color management module support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['txt']
| 1
| 5
| 0
|
--- diff --git a/documentation/devicetree/bindings/display/renesas,du.txt b/documentation/devicetree/bindings/display/renesas,du.txt --- a/documentation/devicetree/bindings/display/renesas,du.txt +++ b/documentation/devicetree/bindings/display/renesas,du.txt + - renesas,cmms: a list of phandles to the cmm instances present in the soc, + one for each available du channel. the property shall not be specified for + socs that do not provide any cmm (such as v3m and v3h). + + renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>;
|
Graphics
|
6e2258b58f819e73aad229fd0af7d8274ef22669
|
jacopo mondi rob herring robh kernel org kieran bingham kieran bingham renesas ideasonboard com laurent pinchart laurent pinchart ideasonboard com
|
documentation
|
devicetree
|
bindings, display
|
drm: rcar-du: add support for cmm
|
add a driver for the r-car display unit color correction module.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
color management module support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['c', 'kconfig', 'makefile', 'h']
| 4
| 284
| 0
|
--- diff --git a/drivers/gpu/drm/rcar-du/kconfig b/drivers/gpu/drm/rcar-du/kconfig --- a/drivers/gpu/drm/rcar-du/kconfig +++ b/drivers/gpu/drm/rcar-du/kconfig + imply drm_rcar_cmm +config drm_rcar_cmm + tristate "r-car du color management module (cmm) support" + depends on drm && of + depends on drm_rcar_du + help + enable support for r-car color management module (cmm). + diff --git a/drivers/gpu/drm/rcar-du/makefile b/drivers/gpu/drm/rcar-du/makefile --- a/drivers/gpu/drm/rcar-du/makefile +++ b/drivers/gpu/drm/rcar-du/makefile +obj-$(config_drm_rcar_cmm) += rcar_cmm.o diff --git a/drivers/gpu/drm/rcar-du/rcar_cmm.c b/drivers/gpu/drm/rcar-du/rcar_cmm.c --- /dev/null +++ b/drivers/gpu/drm/rcar-du/rcar_cmm.c +// spdx-license-identifier: gpl-2.0+ +/* + * rcar_cmm.c -- r-car display unit color management module + * + * copyright (c) 2019 jacopo mondi <jacopo+renesas@jmondi.org> + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> + +#include <drm/drm_color_mgmt.h> + +#include "rcar_cmm.h" + +#define cm2_lut_ctrl 0x0000 +#define cm2_lut_ctrl_lut_en bit(0) +#define cm2_lut_tbl_base 0x0600 +#define cm2_lut_tbl(__i) (cm2_lut_tbl_base + (__i) * 4) + +struct rcar_cmm { + void __iomem *base; + + /* + * @lut: 1d-lut state + * @lut.enabled: 1d-lut enabled flag + */ + struct { + bool enabled; + } lut; +}; + +static inline int rcar_cmm_read(struct rcar_cmm *rcmm, u32 reg) +{ + return ioread32(rcmm->base + reg); +} + +static inline void rcar_cmm_write(struct rcar_cmm *rcmm, u32 reg, u32 data) +{ + iowrite32(data, rcmm->base + reg); +} + +/* + * rcar_cmm_lut_write() - scale the drm lut table entries to hardware precision + * and write to the cmm registers + * @rcmm: pointer to the cmm device + * @drm_lut: pointer to the drm lut table + */ +static void rcar_cmm_lut_write(struct rcar_cmm *rcmm, + const struct drm_color_lut *drm_lut) +{ + unsigned int i; + + for (i = 0; i < cm2_lut_size; ++i) { + u32 entry = drm_color_lut_extract(drm_lut[i].red, 8) << 16 + | drm_color_lut_extract(drm_lut[i].green, 8) << 8 + | drm_color_lut_extract(drm_lut[i].blue, 8); + + rcar_cmm_write(rcmm, cm2_lut_tbl(i), entry); + } +} + +/* + * rcar_cmm_setup() - configure the cmm unit + * @pdev: the platform device associated with the cmm instance + * @config: the cmm unit configuration + * + * configure the cmm unit with the given configuration. currently enabling, + * disabling and programming of the 1-d lut unit is supported. + * + * as rcar_cmm_setup() accesses the cmm registers the unit should be powered + * and its functional clock enabled. to guarantee this, before any call to + * this function is made, the cmm unit has to be enabled by calling + * rcar_cmm_enable() first. + * + * todo: add support for lut double buffer operations to avoid updating the + * lut table entries while a frame is being displayed. + */ +int rcar_cmm_setup(struct platform_device *pdev, + const struct rcar_cmm_config *config) +{ + struct rcar_cmm *rcmm = platform_get_drvdata(pdev); + + /* disable lut if no table is provided. */ + if (!config->lut.table) { + if (rcmm->lut.enabled) { + rcar_cmm_write(rcmm, cm2_lut_ctrl, 0); + rcmm->lut.enabled = false; + } + + return 0; + } + + /* enable lut and program the new gamma table values. */ + if (!rcmm->lut.enabled) { + rcar_cmm_write(rcmm, cm2_lut_ctrl, cm2_lut_ctrl_lut_en); + rcmm->lut.enabled = true; + } + + rcar_cmm_lut_write(rcmm, config->lut.table); + + return 0; +} +export_symbol_gpl(rcar_cmm_setup); + +/* + * rcar_cmm_enable() - enable the cmm unit + * @pdev: the platform device associated with the cmm instance + * + * when the output of the corresponding du channel is routed to the cmm unit, + * the unit shall be enabled before the du channel is started, and remain + * enabled until the channel is stopped. the cmm unit shall be disabled with + * rcar_cmm_disable(). + * + * calls to rcar_cmm_enable() and rcar_cmm_disable() are not reference-counted. + * it is an error to attempt to enable an already enabled cmm unit, or to + * attempt to disable a disabled unit. + */ +int rcar_cmm_enable(struct platform_device *pdev) +{ + int ret; + + ret = pm_runtime_get_sync(&pdev->dev); + if (ret < 0) + return ret; + + return 0; +} +export_symbol_gpl(rcar_cmm_enable); + +/* + * rcar_cmm_disable() - disable the cmm unit + * @pdev: the platform device associated with the cmm instance + * + * see rcar_cmm_enable() for usage information. + * + * disabling the cmm unit disable all the internal processing blocks. the cmm + * state shall thus be restored with rcar_cmm_setup() when re-enabling the cmm + * unit after the next rcar_cmm_enable() call. + */ +void rcar_cmm_disable(struct platform_device *pdev) +{ + struct rcar_cmm *rcmm = platform_get_drvdata(pdev); + + rcar_cmm_write(rcmm, cm2_lut_ctrl, 0); + rcmm->lut.enabled = false; + + pm_runtime_put(&pdev->dev); +} +export_symbol_gpl(rcar_cmm_disable); + +/* + * rcar_cmm_init() - initialize the cmm unit + * @pdev: the platform device associated with the cmm instance + * + * return: 0 on success, -eprobe_defer if the cmm is not available yet, + * -enodev if the drm_rcar_cmm config option is disabled + */ +int rcar_cmm_init(struct platform_device *pdev) +{ + struct rcar_cmm *rcmm = platform_get_drvdata(pdev); + + if (!rcmm) + return -eprobe_defer; + + return 0; +} +export_symbol_gpl(rcar_cmm_init); + +static int rcar_cmm_probe(struct platform_device *pdev) +{ + struct rcar_cmm *rcmm; + + rcmm = devm_kzalloc(&pdev->dev, sizeof(*rcmm), gfp_kernel); + if (!rcmm) + return -enomem; + platform_set_drvdata(pdev, rcmm); + + rcmm->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(rcmm->base)) + return ptr_err(rcmm->base); + + pm_runtime_enable(&pdev->dev); + + return 0; +} + +static int rcar_cmm_remove(struct platform_device *pdev) +{ + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct of_device_id rcar_cmm_of_table[] = { + { .compatible = "renesas,rcar-gen3-cmm", }, + { .compatible = "renesas,rcar-gen2-cmm", }, + { }, +}; +module_device_table(of, rcar_cmm_of_table); + +static struct platform_driver rcar_cmm_platform_driver = { + .probe = rcar_cmm_probe, + .remove = rcar_cmm_remove, + .driver = { + .name = "rcar-cmm", + .of_match_table = rcar_cmm_of_table, + }, +}; + +module_platform_driver(rcar_cmm_platform_driver); + +module_author("jacopo mondi <jacopo+renesas@jmondi.org>"); +module_description("renesas r-car cmm driver"); +module_license("gpl v2"); diff --git a/drivers/gpu/drm/rcar-du/rcar_cmm.h b/drivers/gpu/drm/rcar-du/rcar_cmm.h --- /dev/null +++ b/drivers/gpu/drm/rcar-du/rcar_cmm.h +/* spdx-license-identifier: gpl-2.0+ */ +/* + * rcar_cmm.h -- r-car display unit color management module + * + * copyright (c) 2019 jacopo mondi <jacopo+renesas@jmondi.org> + */ + +#ifndef __rcar_cmm_h__ +#define __rcar_cmm_h__ + +#define cm2_lut_size 256 + +struct drm_color_lut; +struct platform_device; + +/** + * struct rcar_cmm_config - cmm configuration + * + * @lut: 1d-lut configuration + * @lut.table: 1d-lut table entries. disable lut operations when null + */ +struct rcar_cmm_config { + struct { + struct drm_color_lut *table; + } lut; +}; + +#if is_enabled(config_drm_rcar_cmm) +int rcar_cmm_init(struct platform_device *pdev); + +int rcar_cmm_enable(struct platform_device *pdev); +void rcar_cmm_disable(struct platform_device *pdev); + +int rcar_cmm_setup(struct platform_device *pdev, + const struct rcar_cmm_config *config); +#else +static inline int rcar_cmm_init(struct platform_device *pdev) +{ + return -enodev; +} + +static inline int rcar_cmm_enable(struct platform_device *pdev) +{ + return 0; +} + +static inline void rcar_cmm_disable(struct platform_device *pdev) +{ +} + +static inline int rcar_cmm_setup(struct platform_device *pdev, + const struct rcar_cmm_config *config) +{ + return 0; +} +#endif /* is_enabled(config_drm_rcar_cmm) */ + +#endif /* __rcar_cmm_h__ */
|
Graphics
|
e08e934d6c289ed0d6bc222271f69dc35fb2caa5
|
jacopo mondi
|
drivers
|
gpu
|
drm, rcar-du
|
drm: rcar-du: kms: initialize cmm instances
|
implement device tree parsing to collect the available cmm instances described by the 'renesas,cmms' property. associate cmms with crtcs and store a mask of active cmms in the du group for later enablement.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
color management module support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['c', 'h']
| 5
| 88
| 0
|
--- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c + /* cmm might be disabled for this crtc. */ + if (rcdu->cmms[swindex]) { + rcrtc->cmm = rcdu->cmms[swindex]; + rgrp->cmms_mask |= bit(hwindex % 2); + } + diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h + * @cmm: cmm associated with this crtc + struct platform_device *cmm; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h +#include "rcar_cmm.h" + struct platform_device *cmms[rcar_du_max_crtcs]; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.h b/drivers/gpu/drm/rcar-du/rcar_du_group.h --- a/drivers/gpu/drm/rcar-du/rcar_du_group.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.h + * @cmms_mask: bitmask of available cmms in this group + unsigned int cmms_mask; diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c +#include <linux/device.h> +#include <linux/of_platform.h> +static int rcar_du_cmm_init(struct rcar_du_device *rcdu) +{ + const struct device_node *np = rcdu->dev->of_node; + unsigned int i; + int cells; + + cells = of_property_count_u32_elems(np, "renesas,cmms"); + if (cells == -einval) + return 0; + + if (cells > rcdu->num_crtcs) { + dev_err(rcdu->dev, + "invalid number of entries in 'renesas,cmms' "); + return -einval; + } + + for (i = 0; i < cells; ++i) { + struct platform_device *pdev; + struct device_link *link; + struct device_node *cmm; + int ret; + + cmm = of_parse_phandle(np, "renesas,cmms", i); + if (is_err(cmm)) { + dev_err(rcdu->dev, + "failed to parse 'renesas,cmms' property "); + return ptr_err(cmm); + } + + if (!of_device_is_available(cmm)) { + /* it's fine to have a phandle to a non-enabled cmm. */ + of_node_put(cmm); + continue; + } + + pdev = of_find_device_by_node(cmm); + if (is_err(pdev)) { + dev_err(rcdu->dev, "no device found for cmm%u ", i); + of_node_put(cmm); + return ptr_err(pdev); + } + + of_node_put(cmm); + + /* + * -enodev is used to report that the cmm config option is + * disabled: return 0 and let the du continue probing. + */ + ret = rcar_cmm_init(pdev); + if (ret) + return ret == -enodev ? 0 : ret; + + /* + * enforce suspend/resume ordering by making the cmm a provider + * of the du: cmm is suspended after and resumed before the du. + */ + link = device_link_add(rcdu->dev, &pdev->dev, dl_flag_stateless); + if (!link) { + dev_err(rcdu->dev, + "failed to create device link to cmm%u ", i); + return -einval; + } + + rcdu->cmms[i] = pdev; + } + + return 0; +} + + /* initialize the color management modules. */ + ret = rcar_du_cmm_init(rcdu); + if (ret) + return ret; +
|
Graphics
|
8de707aeb4524140d9c37a3cf607e57e753d8529
|
jacopo mondi
|
drivers
|
gpu
|
drm, rcar-du
|
drm: rcar-du: crtc: control cmm operations
|
implement cmm handling in the crtc begin and enable atomic callbacks, and enable cmm unit through the display extensional functions register at group setup time.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
color management module support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['c', 'h']
| 3
| 76
| 0
|
--- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +#include "rcar_cmm.h" +/* ----------------------------------------------------------------------------- + * color management module (cmm) + */ + +static int rcar_du_cmm_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct drm_property_blob *drm_lut = state->gamma_lut; + struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); + struct device *dev = rcrtc->dev->dev; + + if (!drm_lut) + return 0; + + /* we only accept fully populated lut tables. */ + if (drm_color_lut_size(drm_lut) != cm2_lut_size) { + dev_err(dev, "invalid gamma lut size: %zu bytes ", + drm_lut->length); + return -einval; + } + + return 0; +} + +static void rcar_du_cmm_setup(struct drm_crtc *crtc) +{ + struct drm_property_blob *drm_lut = crtc->state->gamma_lut; + struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc); + struct rcar_cmm_config cmm_config = {}; + + if (!rcrtc->cmm) + return; + + if (drm_lut) + cmm_config.lut.table = (struct drm_color_lut *)drm_lut->data; + + rcar_cmm_setup(rcrtc->cmm, &cmm_config); +} + + if (rcrtc->cmm) + rcar_cmm_disable(rcrtc->cmm); + + int ret; + + ret = rcar_du_cmm_check(crtc, state); + if (ret) + return ret; + if (rcrtc->cmm) + rcar_cmm_enable(rcrtc->cmm); + + /* + * todo: the chip manual indicates that cmm tables should be written + * after the du channel has been activated. investigate the impact + * of this restriction on the first displayed frame. + */ + rcar_du_cmm_setup(crtc); + /* if the active state changed, we let .atomic_enable handle cmm. */ + if (crtc->state->color_mgmt_changed && !crtc->state->active_changed) + rcar_du_cmm_setup(crtc); + diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c + u32 defr7 = defr7_code; + /* + * todo: handle routing of the du output to cmm dynamically, as we + * should bypass cmm completely when no color management feature is + * used. + */ + defr7 |= (rgrp->cmms_mask & bit(1) ? defr7_cmme1 : 0) | + (rgrp->cmms_mask & bit(0) ? defr7_cmme0 : 0); + rcar_du_group_write(rgrp, defr7, defr7); + diff --git a/drivers/gpu/drm/rcar-du/rcar_du_regs.h b/drivers/gpu/drm/rcar-du/rcar_du_regs.h --- a/drivers/gpu/drm/rcar-du/rcar_du_regs.h +++ b/drivers/gpu/drm/rcar-du/rcar_du_regs.h +#define defr7 0x000ec +#define defr7_code (0x7779 << 16) +#define defr7_cmme1 bit(6) +#define defr7_cmme0 bit(4) +
|
Graphics
|
78b6bb1d24dbf094a4743bae1ee7c020e8193f25
|
jacopo mondi laurent pinchart laurent pinchart ideasonboard com kieran bingham kieran bingham renesas ideasonboard com
|
drivers
|
gpu
|
drm, rcar-du
|
drm: rcar-du: crtc: register gamma_lut properties
|
enable the gamma_lut kms property using the framework helpers to register the property and set the associated gamma table maximum size.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
color management module support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c + .gamma_set = drm_atomic_helper_legacy_gamma_set, + + drm_mode_crtc_set_gamma_size(crtc, cm2_lut_size); + drm_crtc_enable_color_mgmt(crtc, 0, false, cm2_lut_size);
|
Graphics
|
b28a931476bcc4552936bfa47194cae2ad6a15a5
|
jacopo mondi kieran bingham kieran bingham renesas ideasonboard com ulrich hecht uli renesas fpond eu laurent pinchart laurent pinchart ideasonboard com
|
drivers
|
gpu
|
drm, rcar-du
|
drm: rcar-du: lvds: get dual link configuration from dt
|
for dual-lvds configurations, it is now possible to mark the dt port nodes for the sink with boolean properties (like dual-lvds-even-pixels and dual-lvds-odd-pixels) to let drivers know the encoders need to be configured in dual-lvds mode.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
lvds encoder dual-link support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['c']
| 1
| 46
| 8
|
--- diff --git a/drivers/gpu/drm/rcar-du/rcar_lvds.c b/drivers/gpu/drm/rcar-du/rcar_lvds.c --- a/drivers/gpu/drm/rcar-du/rcar_lvds.c +++ b/drivers/gpu/drm/rcar-du/rcar_lvds.c + struct device_node *port0, *port1; + struct rcar_lvds *companion_lvds; + int dual_link; + /* + * we need to work out if the sink is expecting us to function in + * dual-link mode. we do this by looking at the dt port nodes we are + * connected to, if they are marked as expecting even pixels and + * odd pixels than we need to enable vertical stripe output. + */ + port0 = of_graph_get_port_by_id(dev->of_node, 1); + port1 = of_graph_get_port_by_id(companion, 1); + dual_link = drm_of_lvds_get_dual_link_pixel_order(port0, port1); + of_node_put(port0); + of_node_put(port1); + + if (dual_link >= drm_lvds_dual_link_even_odd_pixels) + lvds->dual_link = true; + else if (lvds->next_bridge && lvds->next_bridge->timings) + /* + * early dual-link bridge specific implementations populate the + * timings field of drm_bridge, read the dual_link flag off the + * bridge directly for backward compatibility. + */ + lvds->dual_link = lvds->next_bridge->timings->dual_link; + + if (!lvds->dual_link) { + dev_dbg(dev, "single-link configuration detected "); + goto done; + } + - dev_dbg(dev, "found companion encoder %pof ", companion); + dev_dbg(dev, + "dual-link configuration detected (companion encoder %pof) ", + companion); + + /* + * fixme: we should not be messing with the companion encoder private + * data from the primary encoder, we should rather let the companion + * encoder work things out on its own. however, the companion encoder + * doesn't hold a reference to the primary encoder, and + * drm_of_lvds_get_dual_link_pixel_order needs to be given references + * to the output ports of both encoders, therefore leave it like this + * for the time being. + */ + companion_lvds = bridge_to_rcar_lvds(lvds->companion); + companion_lvds->dual_link = true; - if ((lvds->info->quirks & rcar_lvds_quirk_dual_link) && - lvds->next_bridge) - lvds->dual_link = lvds->next_bridge->timings - ? lvds->next_bridge->timings->dual_link - : false; - - if (lvds->dual_link) + if (lvds->info->quirks & rcar_lvds_quirk_dual_link)
|
Graphics
|
65112cfa56c32030a7f04a8a4c28251b89b5cf26
|
fabrizio castro
|
drivers
|
gpu
|
drm, rcar-du
|
drm: rcar-du: add r8a77980 support
|
add direct support for the r8a77980 (v3h).
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
r8a77980 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['rcar-du ']
|
['c']
| 1
| 5
| 1
|
--- diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c - /* r8a77970 has one rgb output and one lvds output. */ + /* + * r8a77970 and r8a77980 have one rgb output and one lvds + * output. + */ + { .compatible = "renesas,du-r8a77980", .data = &rcar_du_r8a77970_info },
|
Graphics
|
c267782c5f0efbd20c560101738e68bb30d4fad5
|
kieran bingham
|
drivers
|
gpu
|
drm, rcar-du
|
drm/ast: add cursor plane
|
the cursor plane uses an internal format of argb4444. to userspace, we announce argb8888 and do the transformation internally.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
atomic modeset support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['ast ']
|
['h', 'c']
| 2
| 155
| 1
|
--- diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h + struct drm_plane cursor_plane; diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c +static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height); +static int ast_cursor_update(void *dst, void *src, unsigned int width, + unsigned int height); +static void ast_cursor_set_base(struct ast_private *ast, u64 address); +static int ast_show_cursor(struct drm_crtc *crtc, void *src, + unsigned int width, unsigned int height); +static void ast_hide_cursor(struct drm_crtc *crtc); +static int ast_cursor_move(struct drm_crtc *crtc, + int x, int y); + +/* + * cursor plane + */ + +static const uint32_t ast_cursor_plane_formats[] = { + drm_format_argb8888, +}; + +static int +ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane, + struct drm_plane_state *new_state) +{ + struct drm_framebuffer *fb = new_state->fb; + struct drm_crtc *crtc = new_state->crtc; + struct drm_gem_vram_object *gbo; + struct ast_private *ast; + int ret; + void *src, *dst; + + if (!crtc || !fb) + return 0; + + if (fb->width > ast_max_hwc_width || fb->height > ast_max_hwc_height) + return -einval; + + ast = crtc->dev->dev_private; + + gbo = drm_gem_vram_of_gem(fb->obj[0]); + src = drm_gem_vram_vmap(gbo); + if (is_err(src)) { + ret = ptr_err(src); + goto err_drm_gem_vram_unpin; + } + + dst = drm_gem_vram_vmap(ast->cursor.gbo[ast->cursor.next_index]); + if (is_err(dst)) { + ret = ptr_err(dst); + goto err_drm_gem_vram_vunmap_src; + } + + ret = ast_cursor_update(dst, src, fb->width, fb->height); + if (ret) + goto err_drm_gem_vram_vunmap_dst; + + /* always unmap buffers here. destination buffers are + * perma-pinned while the driver is active. we're only + * changing ref-counters here. + */ + drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); + drm_gem_vram_vunmap(gbo, src); + + return 0; + +err_drm_gem_vram_vunmap_dst: + drm_gem_vram_vunmap(ast->cursor.gbo[ast->cursor.next_index], dst); +err_drm_gem_vram_vunmap_src: + drm_gem_vram_vunmap(gbo, src); +err_drm_gem_vram_unpin: + drm_gem_vram_unpin(gbo); + return ret; +} + +static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + return 0; +} + +static void +ast_cursor_plane_helper_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct drm_plane_state *state = plane->state; + struct drm_crtc *crtc = state->crtc; + struct drm_framebuffer *fb = state->fb; + struct ast_private *ast = plane->dev->dev_private; + struct ast_crtc *ast_crtc = to_ast_crtc(crtc); + struct drm_gem_vram_object *gbo; + s64 off; + u8 jreg; + + ast_crtc->offset_x = ast_max_hwc_width - fb->width; + ast_crtc->offset_y = ast_max_hwc_width - fb->height; + + if (state->fb != old_state->fb) { + /* a new cursor image was installed. */ + gbo = ast->cursor.gbo[ast->cursor.next_index]; + off = drm_gem_vram_offset(gbo); + if (warn_on_once(off < 0)) + return; /* bug: we didn't pin cursor hw bo to vram. */ + ast_cursor_set_base(ast, off); + + ++ast->cursor.next_index; + ast->cursor.next_index %= array_size(ast->cursor.gbo); + } + + ast_cursor_move(crtc, state->crtc_x, state->crtc_y); + + jreg = 0x2; + /* enable argb cursor */ + jreg |= 1; + ast_set_index_reg_mask(ast, ast_io_crtc_port, 0xcb, 0xfc, jreg); +} + +static void +ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct ast_private *ast = plane->dev->dev_private; + + ast_set_index_reg_mask(ast, ast_io_crtc_port, 0xcb, 0xfc, 0x00); +} + +static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = { + .prepare_fb = ast_cursor_plane_helper_prepare_fb, + .cleanup_fb = null, /* not required for cursor plane */ + .atomic_check = ast_cursor_plane_helper_atomic_check, + .atomic_update = ast_cursor_plane_helper_atomic_update, + .atomic_disable = ast_cursor_plane_helper_atomic_disable, +}; + +static const struct drm_plane_funcs ast_cursor_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = drm_plane_cleanup, + .reset = drm_atomic_helper_plane_reset, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + - null, &ast_crtc_funcs, null); + &ast->cursor_plane, &ast_crtc_funcs, + null); + ret = drm_universal_plane_init(dev, &ast->cursor_plane, 0x01, + &ast_cursor_plane_funcs, + ast_cursor_plane_formats, + array_size(ast_cursor_plane_formats), + null, drm_plane_type_cursor, null); + if (ret) { + drm_error("drm_universal_plane_failed(): %d ", ret); + return ret; + } + drm_plane_helper_add(&ast->cursor_plane, + &ast_cursor_plane_helper_funcs); +
|
Graphics
|
02f3bb751a46230f9a49d2a55b304a5847c67788
|
thomas zimmermann
|
drivers
|
gpu
|
ast, drm
|
drm/ast: add primary plane
|
like the original mode-setting code, the primary plane supports xrgb888, rgb565 and c8. the plane itself only pins bos and sets the base address and scanline offset. the mode-setting code will be located in the crtc's atomic helpers.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
atomic modeset support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['ast ']
|
['h', 'c']
| 2
| 89
| 2
|
--- diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h --- a/drivers/gpu/drm/ast/ast_drv.h +++ b/drivers/gpu/drm/ast/ast_drv.h + struct drm_plane primary_plane; + diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c +#include <drm/drm_atomic_helper.h> +#include <drm/drm_atomic_state_helper.h> + +/* + * primary plane + */ + +static const uint32_t ast_primary_plane_formats[] = { + drm_format_xrgb8888, + drm_format_rgb565, + drm_format_c8, +}; + +int ast_primary_plane_helper_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + return 0; +} + +void ast_primary_plane_helper_atomic_update(struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct drm_plane_state *state = plane->state; + struct drm_crtc *crtc = state->crtc; + struct drm_gem_vram_object *gbo; + s64 gpu_addr; + + if (!crtc || !state->fb) + return; + + gbo = drm_gem_vram_of_gem(state->fb->obj[0]); + gpu_addr = drm_gem_vram_offset(gbo); + if (warn_on_once(gpu_addr < 0)) + return; /* bug: we didn't pin the bo to vram in prepare_fb. */ + + ast_set_offset_reg(crtc); + ast_set_start_address_crt1(crtc, (u32)gpu_addr); +} + +static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = { + .prepare_fb = drm_gem_vram_plane_helper_prepare_fb, + .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb, + .atomic_check = ast_primary_plane_helper_atomic_check, + .atomic_update = ast_primary_plane_helper_atomic_update, +}; + +static const struct drm_plane_funcs ast_primary_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = drm_plane_cleanup, + .reset = drm_atomic_helper_plane_reset, + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, +}; + +/* + * crtc + */ + + struct ast_private *ast = dev->dev_private; + int ret; - drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs); + ret = drm_crtc_init_with_planes(dev, &crtc->base, &ast->primary_plane, + null, &ast_crtc_funcs, null); + if (ret) + goto err_kfree; + + +err_kfree: + kfree(crtc); + return ret; - + struct ast_private *ast = dev->dev_private; + int ret; + + memset(&ast->primary_plane, 0, sizeof(ast->primary_plane)); + ret = drm_universal_plane_init(dev, &ast->primary_plane, 0x01, + &ast_primary_plane_funcs, + ast_primary_plane_formats, + array_size(ast_primary_plane_formats), + null, drm_plane_type_primary, null); + if (ret) { + drm_error("ast: drm_universal_plane_init() failed: %d ", ret); + return ret; + } + drm_plane_helper_add(&ast->primary_plane, + &ast_primary_plane_helper_funcs); + +
|
Graphics
|
a6ff807b71e3ffa85c1ba133d8a9fa11fcfe186d
|
thomas zimmermann
|
drivers
|
gpu
|
ast, drm
|
drm/ast: enable atomic modesetting
|
this commit sets the remaining atomic-modesetting helpers and the flag driver_atomic. legacy cursor functions are removed in favor of the cursor plane. for power management, atomic helpers replace the indvidual operations that the driver currently runs.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
atomic modeset support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['ast ']
|
['c']
| 3
| 33
| 286
|
--- diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c --- a/drivers/gpu/drm/ast/ast_drv.c +++ b/drivers/gpu/drm/ast/ast_drv.c - - - drm_kms_helper_poll_disable(dev); - pci_save_state(dev->pdev); - drm_fb_helper_set_suspend_unlocked(dev->fb_helper, true); + int error; + error = drm_mode_config_helper_suspend(dev); + if (error) + return error; + pci_save_state(dev->pdev); - drm_mode_config_reset(dev); - drm_helper_resume_force_mode(dev); - drm_fb_helper_set_suspend_unlocked(dev->fb_helper, false); - - return 0; + return drm_mode_config_helper_resume(dev); - - drm_kms_helper_poll_enable(dev); + - - .driver_features = driver_modeset | driver_gem, + .driver_features = driver_atomic | + driver_gem | + driver_modeset, diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c --- a/drivers/gpu/drm/ast/ast_main.c +++ b/drivers/gpu/drm/ast/ast_main.c +#include <drm/drm_atomic_helper.h> + .atomic_check = drm_atomic_helper_check, + .atomic_commit = drm_atomic_helper_commit, + drm_mode_config_reset(dev); + diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c --- a/drivers/gpu/drm/ast/ast_mode.c +++ b/drivers/gpu/drm/ast/ast_mode.c -static int ast_cursor_set(struct drm_crtc *crtc, - struct drm_file *file_priv, - uint32_t handle, - uint32_t width, - uint32_t height); -static int ast_show_cursor(struct drm_crtc *crtc, void *src, - unsigned int width, unsigned int height); -static void ast_hide_cursor(struct drm_crtc *crtc); - const struct drm_framebuffer *fb = crtc->primary->fb; + const struct drm_framebuffer *fb = crtc->primary->state->fb; - const struct drm_framebuffer *fb = crtc->primary->fb; + const struct drm_framebuffer *fb = crtc->primary->state->fb; -static int ast_crtc_do_set_base(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - int x, int y, int atomic) -{ - struct drm_gem_vram_object *gbo; - int ret; - s64 gpu_addr; - - if (!atomic && fb) { - gbo = drm_gem_vram_of_gem(fb->obj[0]); - drm_gem_vram_unpin(gbo); - } - - gbo = drm_gem_vram_of_gem(crtc->primary->fb->obj[0]); - - ret = drm_gem_vram_pin(gbo, drm_gem_vram_pl_flag_vram); - if (ret) - return ret; - gpu_addr = drm_gem_vram_offset(gbo); - if (gpu_addr < 0) { - ret = (int)gpu_addr; - goto err_drm_gem_vram_unpin; - } - - ast_set_offset_reg(crtc); - ast_set_start_address_crt1(crtc, (u32)gpu_addr); - - return 0; - -err_drm_gem_vram_unpin: - drm_gem_vram_unpin(gbo); - return ret; -} - -static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, - struct drm_framebuffer *old_fb) -{ - return ast_crtc_do_set_base(crtc, old_fb, x, y, 0); -} - -static int ast_crtc_mode_set(struct drm_crtc *crtc, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode, - int x, int y, - struct drm_framebuffer *old_fb) -{ - struct drm_device *dev = crtc->dev; - struct ast_private *ast = crtc->dev->dev_private; - const struct drm_framebuffer *fb = crtc->primary->fb; - struct ast_vbios_mode_info vbios_mode; - bool succ; - - if (ast->chip == ast1180) { - drm_error("ast 1180 modesetting not supported "); - return -einval; - } - - succ = ast_get_vbios_mode_info(fb, mode, adjusted_mode, &vbios_mode); - if (!succ) - return -einval; - - ast_open_key(ast); - - ast_set_vbios_color_reg(crtc, fb, &vbios_mode); - ast_set_vbios_mode_reg(crtc, adjusted_mode, &vbios_mode); - ast_set_index_reg(ast, ast_io_crtc_port, 0xa1, 0x06); - ast_set_std_reg(crtc, adjusted_mode, &vbios_mode); - ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode); - ast_set_offset_reg(crtc); - ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode); - ast_set_color_reg(crtc, fb); - ast_set_crtthd_reg(crtc); - ast_set_sync_reg(dev, adjusted_mode, &vbios_mode); - ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode); - - ast_crtc_mode_set_base(crtc, x, y, old_fb); - - return 0; -} - -static void ast_crtc_disable(struct drm_crtc *crtc) -{ - drm_debug_kms(" "); - ast_crtc_dpms(crtc, drm_mode_dpms_off); - if (crtc->primary->fb) { - struct drm_framebuffer *fb = crtc->primary->fb; - struct drm_gem_vram_object *gbo = - drm_gem_vram_of_gem(fb->obj[0]); - - drm_gem_vram_unpin(gbo); - } - crtc->primary->fb = null; -} - -static void ast_crtc_prepare(struct drm_crtc *crtc) -{ - -} - -static void ast_crtc_commit(struct drm_crtc *crtc) -{ - struct ast_private *ast = crtc->dev->dev_private; - ast_set_index_reg_mask(ast, ast_io_seq_port, 0x1, 0xdf, 0); - ast_crtc_load_lut(crtc); -} - - .dpms = ast_crtc_dpms, - .mode_set = ast_crtc_mode_set, - .mode_set_base = ast_crtc_mode_set_base, - .disable = ast_crtc_disable, - .prepare = ast_crtc_prepare, - .commit = ast_crtc_commit, -static void ast_crtc_reset(struct drm_crtc *crtc) -{ - -} - -static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size, - struct drm_modeset_acquire_ctx *ctx) -{ - ast_crtc_load_lut(crtc); - - return 0; -} - - - .cursor_set = ast_cursor_set, - .cursor_move = ast_cursor_move, - .reset = ast_crtc_reset, + .reset = drm_atomic_helper_crtc_reset, - .gamma_set = ast_crtc_gamma_set, + .gamma_set = drm_atomic_helper_legacy_gamma_set, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, +/* + * encoder + */ + -static void ast_encoder_dpms(struct drm_encoder *encoder, int mode) -{ - -} - -static void ast_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ -} - -static void ast_encoder_prepare(struct drm_encoder *encoder) -{ - -} - -static void ast_encoder_commit(struct drm_encoder *encoder) -{ - -} - -static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = { - .dpms = ast_encoder_dpms, - .prepare = ast_encoder_prepare, - .commit = ast_encoder_commit, - .mode_set = ast_encoder_mode_set, -}; - - drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs); +/* + * connector + */ + - .mode_valid = ast_mode_valid, + .mode_valid = ast_mode_valid, - .dpms = drm_helper_connector_dpms, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -static int ast_show_cursor(struct drm_crtc *crtc, void *src, - unsigned int width, unsigned int height) -{ - struct ast_private *ast = crtc->dev->dev_private; - struct ast_crtc *ast_crtc = to_ast_crtc(crtc); - struct drm_gem_vram_object *gbo; - void *dst; - s64 off; - int ret; - u8 jreg; - - gbo = ast->cursor.gbo[ast->cursor.next_index]; - dst = drm_gem_vram_vmap(gbo); - if (is_err(dst)) - return ptr_err(dst); - off = drm_gem_vram_offset(gbo); - if (off < 0) { - ret = (int)off; - goto err_drm_gem_vram_vunmap; - } - - ret = ast_cursor_update(dst, src, width, height); - if (ret) - goto err_drm_gem_vram_vunmap; - ast_cursor_set_base(ast, off); - - ast_crtc->offset_x = ast_max_hwc_width - width; - ast_crtc->offset_y = ast_max_hwc_width - height; - - jreg = 0x2; - /* enable argb cursor */ - jreg |= 1; - ast_set_index_reg_mask(ast, ast_io_crtc_port, 0xcb, 0xfc, jreg); - - ++ast->cursor.next_index; - ast->cursor.next_index %= array_size(ast->cursor.gbo); - - drm_gem_vram_vunmap(gbo, dst); - - return 0; - -err_drm_gem_vram_vunmap: - drm_gem_vram_vunmap(gbo, dst); - return ret; -} - -static void ast_hide_cursor(struct drm_crtc *crtc) -{ - struct ast_private *ast = crtc->dev->dev_private; - - ast_set_index_reg_mask(ast, ast_io_crtc_port, 0xcb, 0xfc, 0x00); -} - -static int ast_cursor_set(struct drm_crtc *crtc, - struct drm_file *file_priv, - uint32_t handle, - uint32_t width, - uint32_t height) -{ - struct drm_gem_object *obj; - struct drm_gem_vram_object *gbo; - u8 *src; - int ret; - - if (!handle) { - ast_hide_cursor(crtc); - return 0; - } - - if (width > ast_max_hwc_width || height > ast_max_hwc_height) - return -einval; - - obj = drm_gem_object_lookup(file_priv, handle); - if (!obj) { - drm_error("cannot find cursor object %x for crtc ", handle); - return -enoent; - } - gbo = drm_gem_vram_of_gem(obj); - src = drm_gem_vram_vmap(gbo); - if (is_err(src)) { - ret = ptr_err(src); - goto err_drm_gem_object_put_unlocked; - } - - ret = ast_show_cursor(crtc, src, width, height); - if (ret) - goto err_drm_gem_vram_vunmap; - - drm_gem_vram_vunmap(gbo, src); - drm_gem_object_put_unlocked(obj); - - return 0; - -err_drm_gem_vram_vunmap: - drm_gem_vram_vunmap(gbo, src); -err_drm_gem_object_put_unlocked: - drm_gem_object_put_unlocked(obj); - return ret; -} -
|
Graphics
|
4961eb60f14553363a0a7a9fb7b20d9c57d3ebba
|
thomas zimmermann
|
drivers
|
gpu
|
ast, drm
|
drm/mcde: provide vblank handling unconditionally
|
at the moment, vblank handling is only enabled together with te synchronization. however, the vblank irq is also working with on displays without te synchronization (e.g. dsi video mode panels). it seems like the vblank irq is actually generated by the mcde hardware for the channel.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
vblank support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['mcde ']
|
['c']
| 2
| 9
| 22
|
--- diff --git a/drivers/gpu/drm/mcde/mcde_display.c b/drivers/gpu/drm/mcde/mcde_display.c --- a/drivers/gpu/drm/mcde/mcde_display.c +++ b/drivers/gpu/drm/mcde/mcde_display.c - - drm_crtc_vblank_on(crtc); + drm_crtc_vblank_on(crtc); + - if (mcde->te_sync) - drm_crtc_vblank_off(crtc); + drm_crtc_vblank_off(crtc); + .enable_vblank = mcde_display_enable_vblank, + .disable_vblank = mcde_display_disable_vblank, - /* provide vblank only when we have te enabled */ - if (mcde->te_sync) { - mcde_display_funcs.enable_vblank = mcde_display_enable_vblank; - mcde_display_funcs.disable_vblank = mcde_display_disable_vblank; - } - diff --git a/drivers/gpu/drm/mcde/mcde_drv.c b/drivers/gpu/drm/mcde/mcde_drv.c --- a/drivers/gpu/drm/mcde/mcde_drv.c +++ b/drivers/gpu/drm/mcde/mcde_drv.c - /* - * currently we only support vblank handling on the dsi bridge, using - * te synchronization. if te sync is not set up, it is still possible - * to push out a single update on demand, but this is hard for drm to - * exploit. - */ - if (mcde->te_sync) { - ret = drm_vblank_init(drm, 1); - if (ret) { - dev_err(drm->dev, "failed to init vblank "); - goto out_config; - } + ret = drm_vblank_init(drm, 1); + if (ret) { + dev_err(drm->dev, "failed to init vblank "); + goto out_config;
|
Graphics
|
768859c239922264f91d8a49ff8b1b227e7ad7d9
|
stephan gerhold
|
drivers
|
gpu
|
drm, mcde
|
drm/meson: add afbc decoder registers for gxm and g12a
|
add the registers used to program the arm framebuffer compression decoders used in the amlogic gxm and g12a socs families.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
osd1 plane afbc commit
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['meson ']
|
['h']
| 2
| 77
| 0
|
--- diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h +#define viu_sw_reset_osd1_afbcd bit(31) +#define viu_sw_reset_g12a_osd1_afbcd bit(21) +#define viu_sw_reset_g12a_afbc_arb bit(19) +#define mali_afbc_misc genmask(15, 8) +#define viu_osd1_osd_mem_mode_linear bit(2) +#define viu_osd1_cfg_syn_en bit(31) +#define viu_osd1_mali_unpack_ctrl 0x1a2f +#define viu_osd1_mali_unpack_en bit(31) +#define viu_osd1_mali_afbcd_r_reorder genmask(15, 12) +#define viu_osd1_mali_afbcd_g_reorder genmask(11, 8) +#define viu_osd1_mali_afbcd_b_reorder genmask(7, 4) +#define viu_osd1_mali_afbcd_a_reorder genmask(3, 0) +#define viu_osd1_mali_reorder_r 1 +#define viu_osd1_mali_reorder_g 2 +#define viu_osd1_mali_reorder_b 3 +#define viu_osd1_mali_reorder_a 4 +#define osd1_afbcd_id_fifo_thrd genmask(15, 9) +#define osd1_afbcd_dec_enable bit(8) +#define osd1_afbcd_frm_start bit(0) +#define osd1_afbcd_soft_reset bit(31) +#define osd1_afbcd_axi_reorder_mode bit(28) +#define osd1_afbcd_mif_urgent genmask(25, 24) +#define osd1_afbcd_hold_line_num genmask(22, 16) +#define osd1_afbcd_rgba_exchan_ctrl genmask(15, 8) +#define osd1_afbcd_hreg_block_split bit(6) +#define osd1_afbcd_hreg_half_block bit(5) +#define osd1_afbcd_hreg_pixel_packing_fmt genmask(4, 0) +#define osd1_afbcd_hreg_vsize_in genmask(31, 16) +#define osd1_afbcd_hreg_hsize_in genmask(15, 0) +#define osd1_afbcd_conv_lbuf_len genmask(15, 0) +#define osd1_afbcd_dec_pixel_bgn_h genmask(31, 16) +#define osd1_afbcd_dec_pixel_end_h genmask(15, 0) +#define osd1_afbcd_dec_pixel_bgn_v genmask(31, 16) +#define osd1_afbcd_dec_pixel_end_v genmask(15, 0) +#define vpu_mafbc_irq_secure_id_error bit(5) +#define vpu_mafbc_irq_axi_error bit(4) +#define vpu_mafbc_irq_detiling_error bit(3) +#define vpu_mafbc_irq_decode_error bit(2) +#define vpu_mafbc_irq_configuration_swapped bit(1) +#define vpu_mafbc_irq_surfaces_completed bit(0) +#define vpu_mafbc_pending_swap bit(1) +#define vpu_mafbc_direct_swap bit(0) +#define vpu_mafbc_error bit(2) +#define vpu_mafbc_swapping bit(1) +#define vpu_mafbc_active bit(0) +#define vpu_mafbc_continuous_decoding_enable bit(16) +#define vpu_mafbc_s3_enable bit(3) +#define vpu_mafbc_s2_enable bit(2) +#define vpu_mafbc_s1_enable bit(1) +#define vpu_mafbc_s0_enable bit(0) +#define vpu_mafbc_payload_limit_en bit(19) +#define vpu_mafbc_tiled_header_en bit(18) +#define vpu_mafbc_super_block_aspect genmask(17, 16) +#define vpu_mafbc_block_split bit(9) +#define vpu_mafbc_yuv_transform bit(8) +#define vpu_mafbc_pixel_format genmask(3, 0) +#define vpu_mafbc_prefetch_read_direction_y bit(1) +#define vpu_mafbc_prefetch_read_direction_x bit(0) +#define osd_path_osd_axi_sel_osd1_afbcd bit(4) +#define osd_path_osd_axi_sel_osd2_afbcd bit(5) +#define osd_path_osd_axi_sel_osd3_afbcd bit(6) +#define mali_afbcd_manual_reset bit(23) diff --git a/drivers/gpu/drm/meson/meson_viu.h b/drivers/gpu/drm/meson/meson_viu.h --- a/drivers/gpu/drm/meson/meson_viu.h +++ b/drivers/gpu/drm/meson/meson_viu.h +#define osd_mali_src_en bit(30) + +#define osd_mali_color_mode_r8 (0 << 8) +#define osd_mali_color_mode_yuv422 (1 << 8) +#define osd_mali_color_mode_rgb565 (2 << 8) +#define osd_mali_color_mode_rgba5551 (3 << 8) +#define osd_mali_color_mode_rgba4444 (4 << 8) +#define osd_mali_color_mode_rgba8888 (5 << 8) +#define osd_mali_color_mode_rgb888 (7 << 8) +#define osd_mali_color_mode_yuv422_10b (8 << 8) +#define osd_mali_color_mode_rgba1010102 (9 << 8) + +#define osd_mem_linear_addr bit(2) +#define osd_dpath_mali_afbcd bit(15) +#define osd_pending_stat_clean bit(1)
|
Graphics
|
26a7abd4883b71b33371e6ded32422d4e5f9c1c5
|
neil armstrong
|
drivers
|
gpu
|
drm, meson
|
drm/meson: add rdma register bits defines
|
the amlogic vpu embeds a "register dma" that can write a sequence of registers on the vpu ahb bus, either manually or triggered by an internal irq event like vsync or a line input counter.
|
this release adds wireguard, an fast and secure vpn design that aims to replace other vpns; initial support for usb 4; support for time namespaces; asynchronous ssd trimming in btrfs; initial merge of the multipath tcp support; support for virtualbox guest shared folders; a simple file system to expose the zones of zoned storage devices as files; boot-time tracing, which lets to trace the boot-time process with all the features of ftrace; and bootconfig, created to configure boot-time tracing, which lets to extend the command line in a file attached to initrds. as always, there are many other new drivers and improvements.
|
osd1 plane afbc commit
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'power management', 'cryptography', 'security', 'networking', 'architectures x86 s390 riscv mips powerpc csky microblaze sparc uml arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'hardware random number generator (hwrng)', 'cryptography hardware acceleration', 'pci', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'various']
|
['meson ']
|
['h']
| 1
| 48
| 0
|
--- diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h --- a/drivers/gpu/drm/meson/meson_registers.h +++ b/drivers/gpu/drm/meson/meson_registers.h +#define rdma_access_trigger_chan3 genmask(31, 24) +#define rdma_access_trigger_chan2 genmask(23, 16) +#define rdma_access_trigger_chan1 genmask(15, 8) +#define rdma_access_trigger_stop 0 +#define rdma_access_trigger_vsync 1 +#define rdma_access_trigger_line 32 +#define rdma_access_rw_flag_chan3 bit(7) +#define rdma_access_rw_flag_chan2 bit(6) +#define rdma_access_rw_flag_chan1 bit(5) +#define rdma_access_addr_inc_chan3 bit(3) +#define rdma_access_addr_inc_chan2 bit(2) +#define rdma_access_addr_inc_chan1 bit(1) +#define rdma_access_rw_flag_chan7 bit(7) +#define rdma_access_rw_flag_chan6 bit(6) +#define rdma_access_rw_flag_chan5 bit(5) +#define rdma_access_rw_flag_chan4 bit(4) +#define rdma_access_addr_inc_chan7 bit(3) +#define rdma_access_addr_inc_chan6 bit(2) +#define rdma_access_addr_inc_chan5 bit(1) +#define rdma_access_addr_inc_chan4 bit(0) +#define rdma_access_trigger_chan7 genmask(31, 24) +#define rdma_access_trigger_chan6 genmask(23, 16) +#define rdma_access_trigger_chan5 genmask(15, 8) +#define rdma_access_trigger_chan4 genmask(7, 0) +#define rdma_access_man_rw_flag bit(2) +#define rdma_access_man_addr_inc bit(1) +#define rdma_access_man_start bit(0) +#define rdma_irq_clear_chan7 bit(31) +#define rdma_irq_clear_chan6 bit(30) +#define rdma_irq_clear_chan5 bit(29) +#define rdma_irq_clear_chan4 bit(28) +#define rdma_irq_clear_chan3 bit(27) +#define rdma_irq_clear_chan2 bit(26) +#define rdma_irq_clear_chan1 bit(25) +#define rdma_irq_clear_chan_man bit(24) +#define rdma_default_config (bit(7) | bit(6)) +#define rdma_ctrl_ahb_wr_burst genmask(5, 4) +#define rdma_ctrl_ahb_rd_burst genmask(3, 2) +#define rdma_ctrl_sw_reset bit(1) +#define rdma_ctrl_free_clk_en bit(0) +#define rdma_irq_stat_chan7 bit(31) +#define rdma_irq_stat_chan6 bit(30) +#define rdma_irq_stat_chan5 bit(29) +#define rdma_irq_stat_chan4 bit(28) +#define rdma_irq_stat_chan3 bit(27) +#define rdma_irq_stat_chan2 bit(26) +#define rdma_irq_stat_chan1 bit(25) +#define rdma_irq_stat_chan_man bit(24)
|
Graphics
|
7704ddc6a59077088c8b2a43550b7b5be1877385
|
neil armstrong
|
drivers
|
gpu
|
drm, meson
|
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