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hwmon: (pmbus) add support for 2nd gen renesas digital multiphase
|
extend the isl68137 driver to provide support for 2nd generation renesas digital multiphase voltage regulators.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for 2nd gen renesas digital multiphase
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['pmbus']
|
['kconfig', 'c']
| 2
| 99
| 18
|
--- diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - tristate "intersil isl68137" + tristate "renesas digital multiphase voltage regulators" - if you say yes here you get hardware monitoring support for intersil - isl68137. + if you say yes here you get hardware monitoring support for renesas + digital multiphase voltage regulators. diff --git a/drivers/hwmon/pmbus/isl68137.c b/drivers/hwmon/pmbus/isl68137.c --- a/drivers/hwmon/pmbus/isl68137.c +++ b/drivers/hwmon/pmbus/isl68137.c - * hardware monitoring driver for intersil isl68137 + * hardware monitoring driver for renesas digital multiphase voltage regulators + * copyright (c) 2020 renesas electronics america + +#define raa_dmpvr2_read_vmon 0xc8 + +enum versions { + isl68137, + raa_dmpvr2_1rail, + raa_dmpvr2_2rail, + raa_dmpvr2_3rail, + raa_dmpvr2_hv, +}; -static const struct attribute_group *attribute_groups[] = { +static const struct attribute_group *isl68137_attribute_groups[] = { -static struct pmbus_driver_info isl68137_info = { - .pages = 2, +static int raa_dmpvr2_read_word_data(struct i2c_client *client, int page, + int phase, int reg) +{ + int ret; + + switch (reg) { + case pmbus_virt_read_vmon: + ret = pmbus_read_word_data(client, page, phase, + raa_dmpvr2_read_vmon); + break; + default: + ret = -enodata; + break; + } + + return ret; +} + +static struct pmbus_driver_info raa_dmpvr_info = { + .pages = 3, - .r[psc_voltage_in] = 3, + .r[psc_voltage_in] = 2, - | pmbus_have_iout | pmbus_have_status_iout | pmbus_have_pout, - .func[1] = pmbus_have_vout | pmbus_have_status_vout - | pmbus_have_iout | pmbus_have_status_iout | pmbus_have_pout, - .groups = attribute_groups, + | pmbus_have_iout | pmbus_have_status_iout | pmbus_have_pout + | pmbus_have_vmon, + .func[1] = pmbus_have_iin | pmbus_have_pin | pmbus_have_status_input + | pmbus_have_temp | pmbus_have_temp3 | pmbus_have_status_temp + | pmbus_have_vout | pmbus_have_status_vout | pmbus_have_iout + | pmbus_have_status_iout | pmbus_have_pout, + .func[2] = pmbus_have_iin | pmbus_have_pin | pmbus_have_status_input + | pmbus_have_temp | pmbus_have_temp3 | pmbus_have_status_temp + | pmbus_have_vout | pmbus_have_status_vout | pmbus_have_iout + | pmbus_have_status_iout | pmbus_have_pout, - return pmbus_do_probe(client, id, &isl68137_info); + struct pmbus_driver_info *info; + + info = devm_kzalloc(&client->dev, sizeof(*info), gfp_kernel); + if (!info) + return -enomem; + memcpy(info, &raa_dmpvr_info, sizeof(*info)); + + switch (id->driver_data) { + case isl68137: + info->pages = 2; + info->r[psc_voltage_in] = 3; + info->func[0] &= ~pmbus_have_vmon; + info->func[1] = pmbus_have_vout | pmbus_have_status_vout + | pmbus_have_iout | pmbus_have_status_iout + | pmbus_have_pout; + info->groups = isl68137_attribute_groups; + break; + case raa_dmpvr2_1rail: + info->pages = 1; + info->read_word_data = raa_dmpvr2_read_word_data; + break; + case raa_dmpvr2_2rail: + info->pages = 2; + info->read_word_data = raa_dmpvr2_read_word_data; + break; + case raa_dmpvr2_3rail: + info->read_word_data = raa_dmpvr2_read_word_data; + break; + case raa_dmpvr2_hv: + info->pages = 1; + info->r[psc_voltage_in] = 1; + info->m[psc_voltage_out] = 2; + info->r[psc_voltage_out] = 2; + info->m[psc_current_in] = 2; + info->m[psc_power] = 2; + info->r[psc_power] = -1; + info->read_word_data = raa_dmpvr2_read_word_data; + break; + default: + return -enodev; + } + + return pmbus_do_probe(client, id, info); -static const struct i2c_device_id isl68137_id[] = { - {"isl68137", 0}, +static const struct i2c_device_id raa_dmpvr_id[] = { + {"isl68137", isl68137}, + {"raa_dmpvr2_1rail", raa_dmpvr2_1rail}, + {"raa_dmpvr2_2rail", raa_dmpvr2_2rail}, + {"raa_dmpvr2_3rail", raa_dmpvr2_3rail}, + {"raa_dmpvr2_hv", raa_dmpvr2_hv}, -module_device_table(i2c, isl68137_id); +module_device_table(i2c, raa_dmpvr_id); - .id_table = isl68137_id, + .id_table = raa_dmpvr_id, -module_description("pmbus driver for intersil isl68137"); +module_description("pmbus driver for renesas digital multiphase voltage regulators");
|
Hardware monitoring (hwmon)
|
f621d61fd59f402ff3d24f4161e6b782e3be31a6
|
grant peltier
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus) implement multi-phase support
|
some pmbus chips support multiple phases, and report telemetry such as input current, output current, or temperature for each phase. add support for such chips to the pmbus core.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for tps53647 and tps53667
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['pmbus/tps53679']
|
['h', 'c', 'rst']
| 3
| 74
| 25
|
--- diff --git a/documentation/hwmon/pmbus.rst b/documentation/hwmon/pmbus.rst --- a/documentation/hwmon/pmbus.rst +++ b/documentation/hwmon/pmbus.rst -currx_label "iin" or "iouty" +currx_label "iin", "iiny", "iiny.z", "iouty", or "iouty.z", + where y reflects the page number and z reflects the + phase. -powerx_label "pin" or "pouty" +powerx_label "pin", "piny", "piny.z", "pouty", or "pouty.z", + where y reflects the page number and z reflects the + phase. diff --git a/drivers/hwmon/pmbus/pmbus.h b/drivers/hwmon/pmbus/pmbus.h --- a/drivers/hwmon/pmbus/pmbus.h +++ b/drivers/hwmon/pmbus/pmbus.h +#define pmbus_phases 8 /* maximum number of phases per page */ -#define pmbus_page_virtual bit(31) +#define pmbus_phase_virtual bit(30) /* phases on this page are virtual */ +#define pmbus_page_virtual bit(31) /* page is virtual */ + u8 phases[pmbus_pages]; /* number of phases per page */ + u32 pfunc[pmbus_phases];/* functionality, per phase */ diff --git a/drivers/hwmon/pmbus/pmbus_core.c b/drivers/hwmon/pmbus/pmbus_core.c --- a/drivers/hwmon/pmbus/pmbus_core.c +++ b/drivers/hwmon/pmbus/pmbus_core.c + u8 phase; /* phase number, 0xff for all phases */ + u8 currphase; /* current phase, 0xff for all */ - if (page < 0 || page == data->currpage) + if (page < 0) - if (!(data->info->func[page] & pmbus_page_virtual)) { + if (!(data->info->func[page] & pmbus_page_virtual) && + data->info->pages > 1 && page != data->currpage) { - + if (data->info->phases[page] && data->currphase != phase && + !(data->info->func[page] & pmbus_phase_virtual)) { + rv = i2c_smbus_write_byte_data(client, pmbus_phase, + phase); + if (rv) + return rv; + } + data->currphase = phase; + - 0xff, + sensor->phase, - int seq, int page, int reg, + int seq, int page, int phase, + int reg, + sensor->phase = phase; - const char *lstring, int index) + const char *lstring, int index, int phase) - if (!index) - strncpy(label->label, lstring, sizeof(label->label) - 1); - else - snprintf(label->label, sizeof(label->label), "%s%d", lstring, - index); + if (!index) { + if (phase == 0xff) + strncpy(label->label, lstring, + sizeof(label->label) - 1); + else + snprintf(label->label, sizeof(label->label), "%s.%d", + lstring, phase); + } else { + if (phase == 0xff) + snprintf(label->label, sizeof(label->label), "%s%d", + lstring, index); + else + snprintf(label->label, sizeof(label->label), "%s%d.%d", + lstring, index, phase); + } - page, l->reg, attr->class, + page, 0xff, l->reg, attr->class, - int index, int page, + int index, int page, int phase, - paged ? page + 1 : 0); + paged ? page + 1 : 0, phase); - base = pmbus_add_sensor(data, name, "input", index, page, attr->reg, - attr->class, true, true, true); + base = pmbus_add_sensor(data, name, "input", index, page, phase, + attr->reg, attr->class, true, true, true); - if (attr->sfunc) { + /* no limit and alarm attributes for phase specific sensors */ + if (attr->sfunc && phase == 0xff) { - attrs, paged); + 0xff, attrs, paged); + if (info->phases[page]) { + int phase; + + for (phase = 0; phase < info->phases[page]; + phase++) { + if (!(info->pfunc[phase] & attrs->func)) + continue; + ret = pmbus_add_sensor_attrs_one(client, + data, info, name, index, page, + phase, attrs, paged); + if (ret) + return ret; + index++; + } + } - pmbus_virt_fan_target_1 + id, psc_fan, + pmbus_virt_fan_target_1 + id, 0xff, psc_fan, - pmbus_virt_pwm_1 + id, psc_pwm, + pmbus_virt_pwm_1 + id, 0xff, psc_pwm, - pmbus_virt_pwm_enable_1 + id, psc_pwm, + pmbus_virt_pwm_enable_1 + id, 0xff, psc_pwm, - page, pmbus_fan_registers[f], + page, pmbus_fan_registers[f], 0xff, + data->currpage = 0xff; + data->currphase = 0xfe;
|
Hardware monitoring (hwmon)
|
16358542f32f47f372ad48e4cdf61ab245c9f49d
|
guenter roeck
|
documentation
|
hwmon
|
pmbus
|
hwmon: (pmbus/tps53679) add support for multiple chips ids
|
chip specific support will be needed in the driver to be able to support additional chips of the same series. add support for it to the driver.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for tps53647 and tps53667
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['pmbus/tps53679']
|
['c']
| 1
| 31
| 10
|
--- diff --git a/drivers/hwmon/pmbus/tps53679.c b/drivers/hwmon/pmbus/tps53679.c --- a/drivers/hwmon/pmbus/tps53679.c +++ b/drivers/hwmon/pmbus/tps53679.c +#include <linux/of_device.h> +enum chips { + tps53679, tps53688, +}; + - .pages = tps53679_page_num, - .func[0] = pmbus_have_vin | pmbus_have_vout | pmbus_have_status_vout | + .func[0] = pmbus_have_vin | + pmbus_have_vout | pmbus_have_status_vout | - .func[1] = pmbus_have_vin | pmbus_have_vout | pmbus_have_status_vout | + .func[1] = pmbus_have_vin | + pmbus_have_vout | pmbus_have_status_vout | - .identify = tps53679_identify, + struct device *dev = &client->dev; + enum chips chip_id; + + if (dev->of_node) + chip_id = (enum chips)of_device_get_match_data(dev); + else + chip_id = id->driver_data; - info = devm_kmemdup(&client->dev, &tps53679_info, sizeof(*info), - gfp_kernel); + info = devm_kmemdup(dev, &tps53679_info, sizeof(*info), gfp_kernel); + switch (chip_id) { + case tps53679: + case tps53688: + info->pages = tps53679_page_num; + info->identify = tps53679_identify; + break; + default: + return -enodev; + } + - {"tps53679", 0}, - {"tps53688", 0}, + {"tps53679", tps53679}, + {"tps53688", tps53688}, - {.compatible = "ti,tps53679"}, - {.compatible = "ti,tps53688"}, + {.compatible = "ti,tps53679", .data = (void *)tps53679}, + {.compatible = "ti,tps53688", .data = (void *)tps53688},
|
Hardware monitoring (hwmon)
|
63eb4587f62457a49530442484f05b035c7bdf38
|
guenter roeck
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/tps53679) add support for tps53647 and tps53667
|
tps53647 and tps53667 are single channel, step-down buck controllers. tps53647 supports 4 phases, tps53667 supports 6 phases. the chips do not support per-phase output telemetry.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for tps53647 and tps53667
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['pmbus/tps53679']
|
['kconfig', 'c']
| 2
| 15
| 4
|
--- diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - tristate "ti tps53679, tps53681, tps53688" + tristate "ti tps53647, tps53667, tps53679, tps53681, tps53688" - tps53679, tps53681, and tps53688. + tps53647, tps53667, tps53679, tps53681, and tps53688. diff --git a/drivers/hwmon/pmbus/tps53679.c b/drivers/hwmon/pmbus/tps53679.c --- a/drivers/hwmon/pmbus/tps53679.c +++ b/drivers/hwmon/pmbus/tps53679.c - tps53679, tps53681, tps53688 + tps53647, tps53667, tps53679, tps53681, tps53688 +#define tps53647_page_num 1 + - for (i = 0; i < tps53679_page_num; i++) { + for (i = 0; i < info->pages; i++) { + case tps53647: + case tps53667: + info->pages = tps53647_page_num; + info->identify = tps53679_identify; + break; + {"tps53647", tps53647}, + {"tps53667", tps53667}, + {.compatible = "ti,tps53647", .data = (void *)tps53647}, + {.compatible = "ti,tps53667", .data = (void *)tps53667},
|
Hardware monitoring (hwmon)
|
6f944004f873e3036fabc4b3f14a96899fefbff5
|
guenter roeck
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/tps53679) add support for tps53681
|
tps53681 is a dual-channel multiphase step-down controller supporting per-phase and per-channel output telemetry.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for tps53647 and tps53667
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['pmbus/tps53679']
|
['kconfig', 'c']
| 2
| 119
| 5
|
--- diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - tristate "ti tps53679, tps53688" + tristate "ti tps53679, tps53681, tps53688" - tps53679, tps53688 + tps53679, tps53681, and tps53688. diff --git a/drivers/hwmon/pmbus/tps53679.c b/drivers/hwmon/pmbus/tps53679.c --- a/drivers/hwmon/pmbus/tps53679.c +++ b/drivers/hwmon/pmbus/tps53679.c +#include <linux/bits.h> - tps53679, tps53688, + tps53679, tps53681, tps53688 -static int tps53679_identify(struct i2c_client *client, - struct pmbus_driver_info *info) +#define tps53681_device_id 0x81 + +#define tps53681_pmbus_revision 0x33 + +#define tps53681_mfr_specific_20 0xe4 /* number of phases, per page */ + +static int tps53679_identify_mode(struct i2c_client *client, + struct pmbus_driver_info *info) +static int tps53679_identify_phases(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + int ret; + + /* on tps53681, only channel a provides per-phase output current */ + ret = pmbus_read_byte_data(client, 0, tps53681_mfr_specific_20); + if (ret < 0) + return ret; + info->phases[0] = (ret & 0x07) + 1; + + return 0; +} + +static int tps53679_identify_chip(struct i2c_client *client, + u8 revision, u16 id) +{ + u8 buf[i2c_smbus_block_max]; + int ret; + + ret = pmbus_read_byte_data(client, 0, pmbus_revision); + if (ret < 0) + return ret; + if (ret != revision) { + dev_err(&client->dev, "unexpected pmbus revision 0x%x ", ret); + return -enodev; + } + + ret = i2c_smbus_read_block_data(client, pmbus_ic_device_id, buf); + if (ret < 0) + return ret; + if (ret != 1 || buf[0] != id) { + dev_err(&client->dev, "unexpected device id 0x%x ", buf[0]); + return -enodev; + } + return 0; +} + +/* + * common identification function for chips with multi-phase support. + * since those chips have special configuration registers, we want to have + * some level of reassurance that we are really talking with the chip + * being probed. check pmbus revision and chip id. + */ +static int tps53679_identify_multiphase(struct i2c_client *client, + struct pmbus_driver_info *info, + int pmbus_rev, int device_id) +{ + int ret; + + ret = tps53679_identify_chip(client, pmbus_rev, device_id); + if (ret < 0) + return ret; + + ret = tps53679_identify_mode(client, info); + if (ret < 0) + return ret; + + return tps53679_identify_phases(client, info); +} + +static int tps53679_identify(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + return tps53679_identify_mode(client, info); +} + +static int tps53681_identify(struct i2c_client *client, + struct pmbus_driver_info *info) +{ + return tps53679_identify_multiphase(client, info, + tps53681_pmbus_revision, + tps53681_device_id); +} + +static int tps53681_read_word_data(struct i2c_client *client, int page, + int phase, int reg) +{ + /* + * for reading the total output current (read_iout) for all phases, + * the chip datasheet is a bit vague. it says "phase must be set to + * ffh to access all phases simultaneously. phase may also be set to + * 80h readack (!) the total phase current". + * experiments show that the command does _not_ report the total + * current for all phases if the phase is set to 0xff. instead, it + * appears to report the current of one of the phases. override phase + * parameter with 0x80 when reading the total output current on page 0. + */ + if (reg == pmbus_read_iout && page == 0 && phase == 0xff) + return pmbus_read_word_data(client, page, 0x80, reg); + return -enodata; +} + + .pfunc[0] = pmbus_have_iout, + .pfunc[1] = pmbus_have_iout, + .pfunc[2] = pmbus_have_iout, + .pfunc[3] = pmbus_have_iout, + .pfunc[4] = pmbus_have_iout, + .pfunc[5] = pmbus_have_iout, + case tps53681: + info->pages = tps53679_page_num; + info->phases[0] = 6; + info->identify = tps53681_identify; + info->read_word_data = tps53681_read_word_data; + break; + {"tps53681", tps53681}, + {.compatible = "ti,tps53681", .data = (void *)tps53681},
|
Hardware monitoring (hwmon)
|
53030bcc87e4a4b5f3bbdd6851c592ea57485769
|
guenter roeck
|
drivers
|
hwmon
|
pmbus
|
hwmon: (pmbus/ltc2978) add support for more parts.
|
ltc2972, ltc2979, ltc3884, ltc3889, ltc7880, ltm4664, ltm4677, ltm4678, ltm4680, ltm4700.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for more parts
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['pmbus/ltc2978']
|
['kconfig', 'c', 'rst']
| 3
| 228
| 47
|
--- diff --git a/documentation/hwmon/ltc2978.rst b/documentation/hwmon/ltc2978.rst --- a/documentation/hwmon/ltc2978.rst +++ b/documentation/hwmon/ltc2978.rst + * linear technology ltc2972 + + prefix: 'ltc2972' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltc2972.html + + * linear technology ltc2979 + + prefix: 'ltc2979' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltc2979 + + * linear technology ltc3884 + + prefix: 'ltc3884' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltc3884 + + * linear technology ltc3889 + + prefix: 'ltc3889' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltc3889 + + * linear technology ltc7880 + + prefix: 'ltc7880' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltc7880 + - * linear technology ltm4675 + * linear technology ltm4644 + + prefix: 'ltm4644' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltm4644 + + * linear technology ltm4675 + * linear technology ltm4677 + + prefix: 'ltm4677' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltm4677 + + * linear technology ltm4678 + + prefix: 'ltm4678' + + addresses scanned: - + + datasheet: https://www.analog.com/en/products/ltm4678 + + * analog devices ltm4680 + + prefix: 'ltm4680' + + addresses scanned: - + + datasheet: http://www.analog.com/ltm4680 + + * analog devices ltm4700 + + prefix: 'ltm4700' + + addresses scanned: - + + datasheet: http://www.analog.com/ltm4700 + + - ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, and - ltm2987 only. + ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, + ltc2979 and ltm2987 only. - ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, and - ltm2987 only. + ltc2972, ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, + ltc2979 and ltm2987 only. - ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, and - ltm2987 only. + ltc2972, ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, + ltc2979 and ltm2987 only. + - ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, and - ltm2987 only. + ltc2972, ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, + ltc2979 and ltm2987 only. + - ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, and - ltm2987 only. + ltc2972, ltc2974, ltc2975, ltc2977, ltc2980, ltc2978, + and ltm2987 only. + + - ltc2972: n=2-3 - ltc2974, ltc2975: n=2-5 - - ltc2977, ltc2980, ltm2987: n=2-9 + - ltc2977, ltc2979, ltc2980, ltm2987: n=2-9 - ltc2978: n=2-9 - - ltc3880, ltc3882, ltc23886 ltc3887, ltm4675, ltm4676: - n=2-3 + - ltc3880, ltc3882, ltc3884, ltc23886 ltc3887, ltc3889, + ltc7880, ltm4644, ltm4675, ltm4676, ltm4677, ltm4678, + ltm4680, ltm4700: n=2-3 - ltc3883: n=2 - - ltc2974, ltc2975,and ltc2978 only. + ltc2972, ltc2974, ltc2975,and ltc2978 only. + - on ltc2972, temp[1-2] report external temperatures, + and temp 3 reports the chip temperature. - on ltc2974 and ltc2975, temp[1-4] report external - - on ltc2977, ltc2980, ltc2978, and ltm2987, only one - temperature measurement is supported and reports - the chip temperature. - - on ltc3880, ltc3882, ltc3887, ltm4675, and ltm4676, - temp1 and temp2 report external temperatures, and - temp3 reports the chip temperature. + - on ltc2977, ltc2979, ltc2980, ltc2978, and ltm2987, + only one temperature measurement is supported and + reports the chip temperature. + - on ltc3880, ltc3882, ltc3886, ltc3887, ltc3889, + ltm4664, ltm4675, ltm4676, ltm4677, ltm4678, ltm4680, + and ltm4700, temp1 and temp2 report external + temperatures, and temp3 reports the chip temperature. - on ltc3883, temp1 reports an external temperature, - ltc2974, lct2977, ltm2980, ltc2978, and ltm2987 only. + ltc2972, ltc2974, lct2977, ltm2980, ltc2978, + ltc2979, and ltm2987 only. - ltc2974, ltc2975, ltc2977, ltm2980, ltc2978, and - ltm2987 only. + ltc2972, ltc2974, ltc2975, ltc2977, ltm2980, ltc2978, + ltc2979, and ltm2987 only. - - ltc2974, ltc2975, ltc2977, ltm2980, ltc2978, and - ltm2987 only. + - ltc2972, ltc2974, ltc2975, ltc2977, ltm2980, ltc2978, + ltc2979, and ltm2987 only. - not supported for chip temperature sensor on ltc2974 + - ltc2972: n=1-2 - ltc2974, ltc2975: n=1-4 - - ltc2977, ltc2980, ltm2987: not supported + - ltc2977, ltc2979, ltc2980, ltm2987: not supported - ltc2978: not supported - - ltc3880, ltc3882, ltc3886, ltc3887, ltm4675, ltm4676: - n=1-2 + - ltc3880, ltc3882, ltc3884, ltc3886, ltc3887, ltc3889, + ltm4664, ltm4675, ltm4676, ltm4677, ltm4678, ltm4680, + ltm4700: n=1-2 - ltc3883: n=2 - ltc3880, ltc3883, ltc3886, ltc3887, ltm4675, - and ltm4676 only. + ltc3880, ltc3883, ltc3884, ltc3886, ltc3887, ltc3889, + ltm4644, ltm4675, ltm4676, ltm4677, ltm4678, ltm4680, + and ltm4700 only. + - ltc2972: n-1-2 - ltc2974, ltc2975: n=1-4 - - ltc2977, ltc2980, ltm2987: not supported + - ltc2977, ltc2979, ltc2980, ltm2987: not supported - ltc2978: not supported - - ltc3880, ltc3882, ltc3886, ltc3887, ltm4675, ltm4676: - n=2-3 + - ltc3880, ltc3882, ltc3884, ltc3886, ltc3887, ltc3889, + ltm4664, ltm4675, ltm4676, ltm4677, ltm4678, ltm4680, + ltm4700: n=2-3 - ltc3883: n=2 - ltc2974 and ltc2975 only. + ltc2972, ltc2974 and ltc2975 only. - ltc2974 and ltc2975 only. + ltc2972, ltc2974 and ltc2975 only. - ltc2974 and ltc2975 only. + ltc2972, ltc2974 and ltc2975 only. diff --git a/drivers/hwmon/pmbus/kconfig b/drivers/hwmon/pmbus/kconfig --- a/drivers/hwmon/pmbus/kconfig +++ b/drivers/hwmon/pmbus/kconfig - technology ltc2974, ltc2975, ltc2977, ltc2978, ltc2980, ltc3880, - ltc3883, ltc3886, ltc3887, ltcm2987, ltm4675, and ltm4676. + technology ltc2972, ltc2974, ltc2975, ltc2977, ltc2978, ltc2979, + ltc2980, and ltm2987. - if you say yes here you get regulator support for linear - technology ltc2974, ltc2977, ltc2978, ltc3880, ltc3883, ltm4676 - and ltm4686. + if you say yes here you get regulator support for linear technology + ltc3880, ltc3883, ltc3884, ltc3886, ltc3887, ltc3889, ltc7880, + ltm4644, ltm4675, ltm4676, ltm4677, ltm4678, ltm4680, ltm4686, + and ltm4700. diff --git a/drivers/hwmon/pmbus/ltc2978.c b/drivers/hwmon/pmbus/ltc2978.c --- a/drivers/hwmon/pmbus/ltc2978.c +++ b/drivers/hwmon/pmbus/ltc2978.c -enum chips { ltc2974, ltc2975, ltc2977, ltc2978, ltc2980, ltc3880, ltc3882, - ltc3883, ltc3886, ltc3887, ltm2987, ltm4675, ltm4676, ltm4686 }; +enum chips { + /* managers */ + ltc2972, ltc2974, ltc2975, ltc2977, ltc2978, ltc2979, ltc2980, + /* controllers */ + ltc3880, ltc3882, ltc3883, ltc3884, ltc3886, ltc3887, ltc3889, ltc7880, + /* modules */ + ltm2987, ltm4664, ltm4675, ltm4676, ltm4677, ltm4678, ltm4680, ltm4686, + ltm4700, +}; -/* ltc3883 and ltc3886 only */ +/* ltc3883, ltc3884, ltc3886, ltc3889 and ltc7880 only */ + +#define ltc2972_id 0x0310 +#define ltc2979_id_a 0x8060 +#define ltc2979_id_b 0x8070 +#define ltc3884_id 0x4c00 +#define ltc3889_id 0x4900 +#define ltc7880_id 0x49e0 +#define ltm4664_id 0x4120 +#define ltm4677_id_rev1 0x47b0 +#define ltm4677_id_rev2 0x47d0 +#define ltm4678_id_rev1 0x4100 +#define ltm4678_id_rev2 0x4110 +#define ltm4680_id 0x4140 +#define ltm4700_id 0x4130 +#define ltc2972_num_pages 2 + {"ltc2972", ltc2972}, + {"ltc2979", ltc2979}, + {"ltc3884", ltc3884}, + {"ltc3889", ltc3889}, + {"ltc7880", ltc7880}, + {"ltm4664", ltm4664}, + {"ltm4677", ltm4677}, + {"ltm4678", ltm4678}, + {"ltm4680", ltm4680}, + {"ltm4700", ltm4700}, - if (chip_id == ltc2974_id) + if (chip_id == ltc2972_id) + return ltc2972; + else if (chip_id == ltc2974_id) + else if (chip_id == ltc2979_id_a || chip_id == ltc2979_id_b) + return ltc2979; + else if (chip_id == ltc3884_id) + return ltc3884; + else if (chip_id == ltc3889_id) + return ltc3889; + else if (chip_id == ltc7880_id) + return ltc7880; + else if (chip_id == ltm4664_id) + return ltm4664; + else if (chip_id == ltm4677_id_rev1 || chip_id == ltm4677_id_rev2) + return ltm4677; + else if (chip_id == ltm4678_id_rev1 || chip_id == ltm4678_id_rev2) + return ltm4678; + else if (chip_id == ltm4680_id) + return ltm4680; + else if (chip_id == ltm4700_id) + return ltm4700; + case ltc2972: + info->read_word_data = ltc2975_read_word_data; + info->pages = ltc2972_num_pages; + info->func[0] = pmbus_have_iin | pmbus_have_pin + | pmbus_have_vin | pmbus_have_status_input + | pmbus_have_temp2; + for (i = 0; i < info->pages; i++) { + info->func[i] |= pmbus_have_vout + | pmbus_have_status_vout | pmbus_have_pout + | pmbus_have_temp | pmbus_have_status_temp + | pmbus_have_iout | pmbus_have_status_iout; + } + break; + + case ltc2979: + case ltm4677: + case ltc3884: + case ltc3889: + case ltc7880: + case ltm4664: + case ltm4678: + case ltm4680: + case ltm4700: + + { .compatible = "lltc,ltc2972" }, + { .compatible = "lltc,ltc2979" }, + { .compatible = "lltc,ltc3884" }, + { .compatible = "lltc,ltc3889" }, + { .compatible = "lltc,ltc7880" }, + { .compatible = "lltc,ltm4664" }, + { .compatible = "lltc,ltm4677" }, + { .compatible = "lltc,ltm4678" }, + { .compatible = "lltc,ltm4680" }, + { .compatible = "lltc,ltm4700" },
|
Hardware monitoring (hwmon)
|
ee44fafb38869e89ff1012134ea80d55e6e346fc
|
mike jones
|
documentation
|
hwmon
|
pmbus
|
gpiolib: add new ioctl() for monitoring changes in line info
|
currently there is no way for user-space to be informed about changes in status of gpio lines e.g. when someone else requests the line or its config changes. we can only periodically re-read the line-info. this is fine for simple one-off user-space tools, but any daemon that provides a centralized access to gpio chips would benefit hugely from an event driven line info synchronization.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add new ioctl that allows user-space processes to reuse the file descriptor associated with the character device for watching any changes in line properties. every such event contains the updated line information
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['core']
|
['h', 'c']
| 3
| 209
| 8
|
--- diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c + + atomic_notifier_call_chain(&desc->gdev->notifier, + gpioline_changed_config, desc); +struct gpio_chardev_data { + struct gpio_device *gdev; + wait_queue_head_t wait; + declare_kfifo(events, struct gpioline_info_changed, 32); + struct notifier_block lineinfo_changed_nb; + unsigned long *watched_lines; +}; + - struct gpio_device *gdev = filp->private_data; + struct gpio_chardev_data *priv = filp->private_data; + struct gpio_device *gdev = priv->gdev; + struct gpio_desc *desc; + __u32 offset; - } else if (cmd == gpio_get_lineinfo_ioctl) { + } else if (cmd == gpio_get_lineinfo_ioctl || + cmd == gpio_get_lineinfo_watch_ioctl) { - struct gpio_desc *desc; + + if (cmd == gpio_get_lineinfo_watch_ioctl) + set_bit(desc_to_gpio(desc), priv->watched_lines); + + } else if (cmd == gpio_get_lineinfo_unwatch_ioctl) { + if (copy_from_user(&offset, ip, sizeof(offset))) + return -efault; + + desc = gpiochip_get_desc(chip, offset); + if (is_err(desc)) + return ptr_err(desc); + + clear_bit(desc_to_gpio(desc), &desc->flags); + return 0; +static struct gpio_chardev_data * +to_gpio_chardev_data(struct notifier_block *nb) +{ + return container_of(nb, struct gpio_chardev_data, lineinfo_changed_nb); +} + +static int lineinfo_changed_notify(struct notifier_block *nb, + unsigned long action, void *data) +{ + struct gpio_chardev_data *priv = to_gpio_chardev_data(nb); + struct gpioline_info_changed chg; + struct gpio_desc *desc = data; + int ret; + + if (!test_bit(desc_to_gpio(desc), priv->watched_lines)) + return notify_done; + + memset(&chg, 0, sizeof(chg)); + chg.info.line_offset = gpio_chip_hwgpio(desc); + chg.event_type = action; + chg.timestamp = ktime_get_ns(); + gpio_desc_to_lineinfo(desc, &chg.info); + + ret = kfifo_in_spinlocked(&priv->events, &chg, 1, &priv->wait.lock); + if (ret) + wake_up_poll(&priv->wait, epollin); + else + pr_debug_ratelimited("lineinfo event fifo is full - event dropped "); + + return notify_ok; +} + +static __poll_t lineinfo_watch_poll(struct file *filep, + struct poll_table_struct *pollt) +{ + struct gpio_chardev_data *priv = filep->private_data; + __poll_t events = 0; + + poll_wait(filep, &priv->wait, pollt); + + if (!kfifo_is_empty_spinlocked_noirqsave(&priv->events, + &priv->wait.lock)) + events = epollin | epollrdnorm; + + return events; +} + +static ssize_t lineinfo_watch_read(struct file *filep, char __user *buf, + size_t count, loff_t *off) +{ + struct gpio_chardev_data *priv = filep->private_data; + struct gpioline_info_changed event; + ssize_t bytes_read = 0; + int ret; + + if (count < sizeof(event)) + return -einval; + + do { + spin_lock(&priv->wait.lock); + if (kfifo_is_empty(&priv->events)) { + if (bytes_read) { + spin_unlock(&priv->wait.lock); + return bytes_read; + } + + if (filep->f_flags & o_nonblock) { + spin_unlock(&priv->wait.lock); + return -eagain; + } + + ret = wait_event_interruptible_locked(priv->wait, + !kfifo_is_empty(&priv->events)); + if (ret) { + spin_unlock(&priv->wait.lock); + return ret; + } + } + + ret = kfifo_out(&priv->events, &event, 1); + spin_unlock(&priv->wait.lock); + if (ret != 1) { + ret = -eio; + break; + /* we should never get here. see lineevent_read(). */ + } + + if (copy_to_user(buf + bytes_read, &event, sizeof(event))) + return -efault; + bytes_read += sizeof(event); + } while (count >= bytes_read + sizeof(event)); + + return bytes_read; +} + + struct gpio_chardev_data *priv; + int ret = -enomem; + + priv = kzalloc(sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + priv->watched_lines = bitmap_zalloc(gdev->chip->ngpio, gfp_kernel); + if (!priv->watched_lines) + goto out_free_priv; + + init_waitqueue_head(&priv->wait); + init_kfifo(priv->events); + priv->gdev = gdev; + + priv->lineinfo_changed_nb.notifier_call = lineinfo_changed_notify; + ret = atomic_notifier_chain_register(&gdev->notifier, + &priv->lineinfo_changed_nb); + if (ret) + goto out_free_bitmap; + - filp->private_data = gdev; + filp->private_data = priv; - return nonseekable_open(inode, filp); + ret = nonseekable_open(inode, filp); + if (ret) + goto out_unregister_notifier; + + return ret; + +out_unregister_notifier: + atomic_notifier_chain_unregister(&gdev->notifier, + &priv->lineinfo_changed_nb); +out_free_bitmap: + bitmap_free(priv->watched_lines); +out_free_priv: + kfree(priv); + return ret; - struct gpio_device *gdev = container_of(inode->i_cdev, - struct gpio_device, chrdev); + struct gpio_chardev_data *priv = filp->private_data; + struct gpio_device *gdev = priv->gdev; + bitmap_free(priv->watched_lines); + atomic_notifier_chain_unregister(&gdev->notifier, + &priv->lineinfo_changed_nb); + kfree(priv); + - + .poll = lineinfo_watch_poll, + .read = lineinfo_watch_read, + atomic_init_notifier_head(&gdev->notifier); + + atomic_notifier_call_chain(&desc->gdev->notifier, + gpioline_changed_requested, desc); + atomic_notifier_call_chain(&desc->gdev->notifier, + gpioline_changed_released, desc); + diff --git a/drivers/gpio/gpiolib.h b/drivers/gpio/gpiolib.h --- a/drivers/gpio/gpiolib.h +++ b/drivers/gpio/gpiolib.h + struct atomic_notifier_head notifier; diff --git a/include/uapi/linux/gpio.h b/include/uapi/linux/gpio.h --- a/include/uapi/linux/gpio.h +++ b/include/uapi/linux/gpio.h +/* possible line status change events */ +enum { + gpioline_changed_requested = 1, + gpioline_changed_released, + gpioline_changed_config, +}; + +/** + * struct gpioline_info_changed - information about a change in status + * of a gpio line + * @info: updated line information + * @timestamp: estimate of time of status change occurrence, in nanoseconds + * and gpioline_changed_config + * @event_type: one of gpioline_changed_requested, gpioline_changed_released + * + * note: struct gpioline_info embedded here has 32-bit alignment on its own, + * but it works fine with 64-bit alignment too. with its 72 byte size, we can + * guarantee there are no implicit holes between it and subsequent members. + * the 20-byte padding at the end makes sure we don't add any implicit padding + * at the end of the structure on 64-bit architectures. + */ +struct gpioline_info_changed { + struct gpioline_info info; + __u64 timestamp; + __u32 event_type; + __u32 padding[5]; /* for future use */ +}; + +#define gpio_get_lineinfo_watch_ioctl _iowr(0xb4, 0x0b, struct gpioline_info) +#define gpio_get_lineinfo_unwatch_ioctl _iowr(0xb4, 0x0c, __u32)
|
General Purpose I/O (gpio)
|
51c1064e82e77b39a49889287ca50709303e2f26
|
bartosz golaszewski
|
include
|
uapi
|
linux
|
tools: gpio: implement gpio-watch
|
add a simple program that allows to test the new linechanged_fd ioctl().
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add gpio-watch program for monitoring changes in line info
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['tools']
|
['gitignore', 'c', 'build', 'makefile']
| 4
| 111
| 1
|
--- diff --git a/tools/gpio/.gitignore b/tools/gpio/.gitignore --- a/tools/gpio/.gitignore +++ b/tools/gpio/.gitignore +gpio-watch diff --git a/tools/gpio/build b/tools/gpio/build --- a/tools/gpio/build +++ b/tools/gpio/build +gpio-watch-y += gpio-watch.o diff --git a/tools/gpio/makefile b/tools/gpio/makefile --- a/tools/gpio/makefile +++ b/tools/gpio/makefile -all_targets := lsgpio gpio-hammer gpio-event-mon +all_targets := lsgpio gpio-hammer gpio-event-mon gpio-watch +# +# gpio-watch +# +gpio_watch_in := $(output)gpio-watch-in.o +$(gpio_watch_in): prepare force + $(q)$(make) $(build)=gpio-watch +$(output)gpio-watch: $(gpio_watch_in) + $(quiet_link)$(cc) $(cflags) $(ldflags) $< -o $@ + diff --git a/tools/gpio/gpio-watch.c b/tools/gpio/gpio-watch.c --- /dev/null +++ b/tools/gpio/gpio-watch.c +// spdx-license-identifier: gpl-2.0-only +/* + * gpio-watch - monitor unrequested lines for property changes using the + * character device + * + * copyright (c) 2019 baylibre sas + * author: bartosz golaszewski <bgolaszewski@baylibre.com> + */ + +#include <ctype.h> +#include <errno.h> +#include <fcntl.h> +#include <linux/gpio.h> +#include <poll.h> +#include <stdbool.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <sys/ioctl.h> +#include <unistd.h> + +int main(int argc, char **argv) +{ + struct gpioline_info_changed chg; + struct gpioline_info req; + struct pollfd pfd; + int fd, i, j, ret; + char *event, *end; + ssize_t rd; + + if (argc < 3) + goto err_usage; + + fd = open(argv[1], o_rdwr | o_cloexec); + if (fd < 0) { + perror("unable to open gpiochip"); + return exit_failure; + } + + for (i = 0, j = 2; i < argc - 2; i++, j++) { + memset(&req, 0, sizeof(req)); + + req.line_offset = strtoul(argv[j], &end, 0); + if (*end != '') + goto err_usage; + + ret = ioctl(fd, gpio_get_lineinfo_watch_ioctl, &req); + if (ret) { + perror("unable to set up line watch"); + return exit_failure; + } + } + + pfd.fd = fd; + pfd.events = pollin | pollpri; + + for (;;) { + ret = poll(&pfd, 1, 5000); + if (ret < 0) { + perror("error polling the linechanged fd"); + return exit_failure; + } else if (ret > 0) { + memset(&chg, 0, sizeof(chg)); + rd = read(pfd.fd, &chg, sizeof(chg)); + if (rd < 0 || rd != sizeof(chg)) { + if (rd != sizeof(chg)) + errno = eio; + + perror("error reading line change event"); + return exit_failure; + } + + switch (chg.event_type) { + case gpioline_changed_requested: + event = "requested"; + break; + case gpioline_changed_released: + event = "released"; + break; + case gpioline_changed_config: + event = "config changed"; + break; + default: + fprintf(stderr, + "invalid event type received from the kernel "); + return exit_failure; + } + + printf("line %u: %s at %llu ", + chg.info.line_offset, event, chg.timestamp); + } + } + + return 0; + +err_usage: + printf("%s: <gpiochip> <line0> <line1> ... ", argv[0]); + return exit_failure; +}
|
General Purpose I/O (gpio)
|
33f0c47b8fb4724792b16351a32b24902a5d3b07
|
bartosz golaszewski andy shevchenko andriy shevchenko linux intel com
|
tools
|
gpio
| |
gpio: add driver for mellanox bluefield 2 gpio controller
|
this patch adds support for the gpio controller used by mellanox bluefield 2 socs.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add driver for mellanox bluefield 2 gpio controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 343
| 0
|
--- diff --git a/drivers/gpio/kconfig b/drivers/gpio/kconfig --- a/drivers/gpio/kconfig +++ b/drivers/gpio/kconfig +config gpio_mlxbf2 + tristate "mellanox bluefield 2 soc gpio" + depends on (mellanox_platform && arm64 && acpi) || (64bit && compile_test) + select gpio_generic + help + say y here if you want gpio support on mellanox bluefield 2 soc. + diff --git a/drivers/gpio/makefile b/drivers/gpio/makefile --- a/drivers/gpio/makefile +++ b/drivers/gpio/makefile +obj-$(config_gpio_mlxbf2) += gpio-mlxbf2.o diff --git a/drivers/gpio/gpio-mlxbf2.c b/drivers/gpio/gpio-mlxbf2.c --- /dev/null +++ b/drivers/gpio/gpio-mlxbf2.c +// spdx-license-identifier: gpl-2.0 + +#include <linux/acpi.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/gpio/driver.h> +#include <linux/io.h> +#include <linux/ioport.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/resource.h> +#include <linux/spinlock.h> +#include <linux/types.h> +#include <linux/version.h> + +/* + * there are 3 yu gpio blocks: + * gpio[0]: host_gpio0->host_gpio31 + * gpio[1]: host_gpio32->host_gpio63 + * gpio[2]: host_gpio64->host_gpio69 + */ +#define mlxbf2_gpio_max_pins_per_block 32 + +/* + * arm_gpio_lock register: + * bit[31] lock status: active if set + * bit[15:0] set lock + * the lock is enabled only if 0xd42f is written to this field + */ +#define yu_arm_gpio_lock_addr 0x2801088 +#define yu_arm_gpio_lock_size 0x8 +#define yu_lock_active_bit(val) (val >> 31) +#define yu_arm_gpio_lock_acquire 0xd42f +#define yu_arm_gpio_lock_release 0x0 + +/* + * gpio[x] block registers and their offset + */ +#define yu_gpio_datain 0x04 +#define yu_gpio_mode1 0x08 +#define yu_gpio_mode0 0x0c +#define yu_gpio_dataset 0x14 +#define yu_gpio_dataclear 0x18 +#define yu_gpio_mode1_clear 0x50 +#define yu_gpio_mode0_set 0x54 +#define yu_gpio_mode0_clear 0x58 + +#ifdef config_pm +struct mlxbf2_gpio_context_save_regs { + u32 gpio_mode0; + u32 gpio_mode1; +}; +#endif + +/* bluefield-2 gpio block context structure. */ +struct mlxbf2_gpio_context { + struct gpio_chip gc; + + /* yu gpio blocks address */ + void __iomem *gpio_io; + +#ifdef config_pm + struct mlxbf2_gpio_context_save_regs *csave_regs; +#endif +}; + +/* bluefield-2 gpio shared structure. */ +struct mlxbf2_gpio_param { + void __iomem *io; + struct resource *res; + struct mutex *lock; +}; + +static struct resource yu_arm_gpio_lock_res = { + .start = yu_arm_gpio_lock_addr, + .end = yu_arm_gpio_lock_addr + yu_arm_gpio_lock_size - 1, + .name = "yu_arm_gpio_lock", +}; + +static define_mutex(yu_arm_gpio_lock_mutex); + +static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = { + .res = &yu_arm_gpio_lock_res, + .lock = &yu_arm_gpio_lock_mutex, +}; + +/* request memory region and map yu_arm_gpio_lock resource */ +static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct resource *res; + resource_size_t size; + int ret = 0; + + mutex_lock(yu_arm_gpio_lock_param.lock); + + /* check if the memory map already exists */ + if (yu_arm_gpio_lock_param.io) + goto exit; + + res = yu_arm_gpio_lock_param.res; + size = resource_size(res); + + if (!devm_request_mem_region(dev, res->start, size, res->name)) { + ret = -efault; + goto exit; + } + + yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size); + if (is_err(yu_arm_gpio_lock_param.io)) + ret = ptr_err(yu_arm_gpio_lock_param.io); + +exit: + mutex_unlock(yu_arm_gpio_lock_param.lock); + + return ret; +} + +/* + * acquire the yu arm_gpio_lock to be able to change the direction + * mode. if the lock_active bit is already set, return an error. + */ +static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs) +{ + u32 arm_gpio_lock_val; + + spin_lock(&gs->gc.bgpio_lock); + mutex_lock(yu_arm_gpio_lock_param.lock); + + arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io); + + /* + * when lock active bit[31] is set, modex is write enabled + */ + if (yu_lock_active_bit(arm_gpio_lock_val)) { + mutex_unlock(yu_arm_gpio_lock_param.lock); + spin_unlock(&gs->gc.bgpio_lock); + return -einval; + } + + writel(yu_arm_gpio_lock_acquire, yu_arm_gpio_lock_param.io); + + return 0; +} + +/* + * release the yu arm_gpio_lock after changing the direction mode. + */ +static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs) +{ + writel(yu_arm_gpio_lock_release, yu_arm_gpio_lock_param.io); + mutex_unlock(yu_arm_gpio_lock_param.lock); + spin_unlock(&gs->gc.bgpio_lock); +} + +/* + * mode0 and mode1 are both locked by the gpio_lock field. + * + * together, mode0 and mode1 define the gpio mode dependeing also + * on reg_dataout. + * + * {mode1,mode0}:{reg_dataout=0,reg_dataout=1}->{dataout=0,dataout=1} + * + * {0,0}:reg_dataout{0,1}->{z,z} input pad + * {0,1}:reg_dataout{0,1}->{0,1} full drive output pad + * {1,0}:reg_dataout{0,1}->{0,z} 0-set pad to low, 1-float + * {1,1}:reg_dataout{0,1}->{z,1} 0-float, 1-set pad to high + */ + +/* + * set input direction: + * {mode1,mode0} = {0,0} + */ +static int mlxbf2_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip); + int ret; + + /* + * although the arm_gpio_lock was set in the probe function, check again + * if it is still enabled to be able to write to the modex registers. + */ + ret = mlxbf2_gpio_lock_acquire(gs); + if (ret < 0) + return ret; + + writel(bit(offset), gs->gpio_io + yu_gpio_mode0_clear); + writel(bit(offset), gs->gpio_io + yu_gpio_mode1_clear); + + mlxbf2_gpio_lock_release(gs); + + return ret; +} + +/* + * set output direction: + * {mode1,mode0} = {0,1} + */ +static int mlxbf2_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, + int value) +{ + struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip); + int ret = 0; + + /* + * although the arm_gpio_lock was set in the probe function, + * check again it is still enabled to be able to write to the + * modex registers. + */ + ret = mlxbf2_gpio_lock_acquire(gs); + if (ret < 0) + return ret; + + writel(bit(offset), gs->gpio_io + yu_gpio_mode1_clear); + writel(bit(offset), gs->gpio_io + yu_gpio_mode0_set); + + mlxbf2_gpio_lock_release(gs); + + return ret; +} + +/* bluefield-2 gpio driver initialization routine. */ +static int +mlxbf2_gpio_probe(struct platform_device *pdev) +{ + struct mlxbf2_gpio_context *gs; + struct device *dev = &pdev->dev; + struct gpio_chip *gc; + struct resource *res; + unsigned int npins; + int ret; + + gs = devm_kzalloc(dev, sizeof(*gs), gfp_kernel); + if (!gs) + return -enomem; + + /* yu gpio block address */ + res = platform_get_resource(pdev, ioresource_mem, 0); + if (!res) + return -enodev; + + gs->gpio_io = devm_ioremap(dev, res->start, resource_size(res)); + if (!gs->gpio_io) + return -enomem; + + ret = mlxbf2_gpio_get_lock_res(pdev); + if (ret) { + dev_err(dev, "failed to get yu_arm_gpio_lock resource "); + return ret; + } + + if (device_property_read_u32(dev, "npins", &npins)) + npins = mlxbf2_gpio_max_pins_per_block; + + gc = &gs->gc; + + ret = bgpio_init(gc, dev, 4, + gs->gpio_io + yu_gpio_datain, + gs->gpio_io + yu_gpio_dataset, + gs->gpio_io + yu_gpio_dataclear, + null, + null, + 0); + + gc->direction_input = mlxbf2_gpio_direction_input; + gc->direction_output = mlxbf2_gpio_direction_output; + gc->ngpio = npins; + gc->owner = this_module; + + platform_set_drvdata(pdev, gs); + + ret = devm_gpiochip_add_data(dev, &gs->gc, gs); + if (ret) { + dev_err(dev, "failed adding memory mapped gpiochip "); + return ret; + } + + return 0; +} + +#ifdef config_pm +static int mlxbf2_gpio_suspend(struct platform_device *pdev, + pm_message_t state) +{ + struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev); + + gs->csave_regs->gpio_mode0 = readl(gs->gpio_io + + yu_gpio_mode0); + gs->csave_regs->gpio_mode1 = readl(gs->gpio_io + + yu_gpio_mode1); + + return 0; +} + +static int mlxbf2_gpio_resume(struct platform_device *pdev) +{ + struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev); + + writel(gs->csave_regs->gpio_mode0, gs->gpio_io + + yu_gpio_mode0); + writel(gs->csave_regs->gpio_mode1, gs->gpio_io + + yu_gpio_mode1); + + return 0; +} +#endif + +static const struct acpi_device_id mlxbf2_gpio_acpi_match[] = { + { "mlnxbf22", 0 }, + {}, +}; +module_device_table(acpi, mlxbf2_gpio_acpi_match); + +static struct platform_driver mlxbf2_gpio_driver = { + .driver = { + .name = "mlxbf2_gpio", + .acpi_match_table = acpi_ptr(mlxbf2_gpio_acpi_match), + }, + .probe = mlxbf2_gpio_probe, +#ifdef config_pm + .suspend = mlxbf2_gpio_suspend, + .resume = mlxbf2_gpio_resume, +#endif +}; + +module_platform_driver(mlxbf2_gpio_driver); + +module_description("mellanox bluefield-2 gpio driver"); +module_author("mellanox technologies"); +module_license("gpl v2");
|
General Purpose I/O (gpio)
|
bc0ae0e737f5167348579612493e2754e2122dfb
|
asmaa mnebhi
|
drivers
|
gpio
| |
leds: add sgi ip30 led support
|
this patch implemenets a driver to support the front panel leds of sgi octane (ip30) workstations.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add sgi ip30 led support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 98
| 0
|
--- diff --git a/drivers/leds/kconfig b/drivers/leds/kconfig --- a/drivers/leds/kconfig +++ b/drivers/leds/kconfig +config leds_ip30 + tristate "led support for sgi octane machines" + depends on leds_class + depends on sgi_mfd_ioc3 + help + this option enables support for the red and white leds of + sgi octane machines. + + to compile this driver as a module, choose m here: the module + will be called leds-ip30. + diff --git a/drivers/leds/makefile b/drivers/leds/makefile --- a/drivers/leds/makefile +++ b/drivers/leds/makefile +obj-$(config_leds_ip30) += leds-ip30.o diff --git a/drivers/leds/leds-ip30.c b/drivers/leds/leds-ip30.c --- /dev/null +++ b/drivers/leds/leds-ip30.c +// spdx-license-identifier: gpl-2.0 +/* + * led driver for sgi octane machines + */ + +#include <linux/module.h> +#include <linux/kernel.h> +#include <linux/platform_device.h> +#include <linux/leds.h> + +#define ip30_led_system 0 +#define ip30_led_fault 1 + +struct ip30_led { + struct led_classdev cdev; + u32 __iomem *reg; +}; + +static void ip30led_set(struct led_classdev *led_cdev, + enum led_brightness value) +{ + struct ip30_led *led = container_of(led_cdev, struct ip30_led, cdev); + + writel(value, led->reg); +} + +static int ip30led_create(struct platform_device *pdev, int num) +{ + struct resource *res; + struct ip30_led *data; + + res = platform_get_resource(pdev, ioresource_mem, num); + if (!res) + return -ebusy; + + data = devm_kzalloc(&pdev->dev, sizeof(*data), gfp_kernel); + if (!data) + return -enomem; + + data->reg = devm_ioremap_resource(&pdev->dev, res); + if (is_err(data->reg)) + return ptr_err(data->reg); + + + switch (num) { + case ip30_led_system: + data->cdev.name = "white:system"; + break; + case ip30_led_fault: + data->cdev.name = "red:fault"; + break; + default: + return -einval; + } + + data->cdev.brightness = readl(data->reg); + data->cdev.max_brightness = 1; + data->cdev.brightness_set = ip30led_set; + + return devm_led_classdev_register(&pdev->dev, &data->cdev); +} + +static int ip30led_probe(struct platform_device *pdev) +{ + int ret; + + ret = ip30led_create(pdev, ip30_led_system); + if (ret < 0) + return ret; + + return ip30led_create(pdev, ip30_led_fault); +} + +static struct platform_driver ip30led_driver = { + .probe = ip30led_probe, + .driver = { + .name = "ip30-leds", + }, +}; + +module_platform_driver(ip30led_driver); + +module_author("thomas bogendoerfer <tbogendoerfer@suse.de>"); +module_description("sgi octane led driver"); +module_license("gpl"); +module_alias("platform:ip30-leds");
|
LEDs
|
64d7e23115dd91997858eb0c370d798a0d6bf118
|
thomas bogendoerfer jacek anaszewski jacek anaszewski gmail com dan murphy dmurphy ti com
|
drivers
|
leds
| |
dmaengine: add basic debugfs support
|
via the /sys/kernel/debug/dmaengine/summary users can get information about the dma devices and the used channels.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add basic debugfs support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 2
| 87
| 2
|
--- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c +/* --- debugfs implementation --- */ +#ifdef config_debug_fs +#include <linux/debugfs.h> + +static void dmaengine_dbg_summary_show(struct seq_file *s, + struct dma_device *dma_dev) +{ + struct dma_chan *chan; + + list_for_each_entry(chan, &dma_dev->channels, device_node) { + if (chan->client_count) { + seq_printf(s, " %-13s| %s", dma_chan_name(chan), + chan->dbg_client_name ?: "in-use"); + + if (chan->router) + seq_printf(s, " (via router: %s) ", + dev_name(chan->router->dev)); + else + seq_puts(s, " "); + } + } +} + +static int dmaengine_summary_show(struct seq_file *s, void *data) +{ + struct dma_device *dma_dev = null; + + mutex_lock(&dma_list_mutex); + list_for_each_entry(dma_dev, &dma_device_list, global_node) { + seq_printf(s, "dma%d (%s): number of channels: %u ", + dma_dev->dev_id, dev_name(dma_dev->dev), + dma_dev->chancnt); + + if (dma_dev->dbg_summary_show) + dma_dev->dbg_summary_show(s, dma_dev); + else + dmaengine_dbg_summary_show(s, dma_dev); + + if (!list_is_last(&dma_dev->global_node, &dma_device_list)) + seq_puts(s, " "); + } + mutex_unlock(&dma_list_mutex); + + return 0; +} +define_show_attribute(dmaengine_summary); + +static void __init dmaengine_debugfs_init(void) +{ + struct dentry *rootdir = debugfs_create_dir("dmaengine", null); + + /* /sys/kernel/debug/dmaengine/summary */ + debugfs_create_file("summary", 0444, rootdir, null, + &dmaengine_summary_fops); +} +#else +static inline void dmaengine_debugfs_init(void) { } +#endif /* debug_fs */ + +#ifdef config_debug_fs + chan->dbg_client_name = kasprintf(gfp_kernel, "%s:%s", dev_name(dev), + name); +#endif + + +#ifdef config_debug_fs + kfree(chan->dbg_client_name); + chan->dbg_client_name = null; +#endif - return class_register(&dma_devclass); + + err = class_register(&dma_devclass); + if (!err) + dmaengine_debugfs_init(); + + return err; diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h + * @dbg_client_name: slave name for debugfs in format: + * dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx" +#ifdef config_debug_fs + char *dbg_client_name; +#endif - * + * @dbg_summary_show: optional routine to show contents in debugfs; default code + * will be used when this is omitted, but custom code can show extra, + * controller specific information. + /* debugfs support */ +#ifdef config_debug_fs + void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev); +#endif
|
DMA engines
|
e937cc1dd7966df33a478943817302502a164e25
|
peter ujfalusi
|
include
|
linux
| |
dmaengine: ti: k3-udma: implement support for atype (for virtualization)
|
the dt for virtualized hosts have dma-cells == 2 where the second parameter is the atype for the channel.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
implement support for atype (for virtualization)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['ti', 'k3-udma']
|
['c']
| 2
| 58
| 10
|
--- diff --git a/drivers/dma/ti/k3-udma-glue.c b/drivers/dma/ti/k3-udma-glue.c --- a/drivers/dma/ti/k3-udma-glue.c +++ b/drivers/dma/ti/k3-udma-glue.c + u32 atype; + if (dma_spec.args_count == 2) { + if (dma_spec.args[1] > 2) { + dev_err(common->dev, "invalid channel atype: %u ", + dma_spec.args[1]); + ret = -einval; + goto out_put_spec; + } + common->atype = dma_spec.args[1]; + } - ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid; + ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid | + ti_sci_msg_value_rm_udmap_ch_atype_valid; + req.tx_atype = tx_chn->common.atype; - ti_sci_msg_value_rm_udmap_ch_rx_flowid_cnt_valid; + ti_sci_msg_value_rm_udmap_ch_rx_flowid_cnt_valid | + ti_sci_msg_value_rm_udmap_ch_atype_valid; + req.rx_atype = rx_chn->common.atype; diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c --- a/drivers/dma/ti/k3-udma.c +++ b/drivers/dma/ti/k3-udma.c + u32 atype; + u32 atype; - ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid) + ti_sci_msg_value_rm_udmap_ch_cq_qnum_valid | \ + ti_sci_msg_value_rm_udmap_ch_atype_valid) - ti_sci_msg_value_rm_udmap_ch_rx_flowid_cnt_valid) + ti_sci_msg_value_rm_udmap_ch_rx_flowid_cnt_valid | \ + ti_sci_msg_value_rm_udmap_ch_atype_valid) + req_tx.tx_atype = ud->atype; + req_rx.rx_atype = ud->atype; + req_tx.tx_atype = uc->config.atype; + req_rx.rx_atype = uc->config.atype; +struct udma_filter_param { + int remote_thread_id; + u32 atype; +}; + + struct udma_filter_param *filter_param; - u32 *args; - args = param; + filter_param = param; + + if (filter_param->atype > 2) { + dev_err(ud->dev, "invalid channel atype: %u ", + filter_param->atype); + return false; + } - ucc->remote_thread_id = args[0]; + ucc->remote_thread_id = filter_param->remote_thread_id; + ucc->atype = filter_param->atype; + ucc->atype = 0; + struct udma_filter_param filter_param; - if (dma_spec->args_count != 1) + if (dma_spec->args_count != 1 && dma_spec->args_count != 2) - chan = __dma_request_channel(&mask, udma_dma_filter_fn, - &dma_spec->args[0], ofdma->of_node); + filter_param.remote_thread_id = dma_spec->args[0]; + if (dma_spec->args_count == 2) + filter_param.atype = dma_spec->args[1]; + else + filter_param.atype = 0; + + chan = __dma_request_channel(&mask, udma_dma_filter_fn, &filter_param, + ofdma->of_node); + ret = of_property_read_u32(navss_node, "ti,udma-atype", &ud->atype); + if (!ret && ud->atype > 2) { + dev_err(dev, "invalid atype: %u ", ud->atype); + return -einval; + } +
|
DMA engines
|
0ebcf1a274c5467c8ed55d0e01db4b414fe4518d
|
peter ujfalusi
|
drivers
|
dma
|
ti
|
dmaengine: uniphier-xdmac: add uniphier external dma controller driver
|
this adds external dma controller driver implemented in socionext uniphier socs. this driver supports dma_memcpy and dma_slave modes.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add uniphier external dma controller driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['uniphier-xdmac']
|
['kconfig', 'c', 'makefile']
| 3
| 623
| 0
|
--- diff --git a/drivers/dma/kconfig b/drivers/dma/kconfig --- a/drivers/dma/kconfig +++ b/drivers/dma/kconfig +config uniphier_xdmac + tristate "uniphier xdmac support" + depends on arch_uniphier || compile_test + depends on of + select dma_engine + select dma_virtual_channels + help + enable support for the xdmac (external dma controller) on the + uniphier platform. this dma controller can transfer data from + memory to memory, memory to peripheral and peripheral to memory. + diff --git a/drivers/dma/makefile b/drivers/dma/makefile --- a/drivers/dma/makefile +++ b/drivers/dma/makefile +obj-$(config_uniphier_xdmac) += uniphier-xdmac.o diff --git a/drivers/dma/uniphier-xdmac.c b/drivers/dma/uniphier-xdmac.c --- /dev/null +++ b/drivers/dma/uniphier-xdmac.c +// spdx-license-identifier: gpl-2.0 +/* + * external dma controller driver for uniphier socs + * copyright 2019 socionext inc. + * author: kunihiko hayashi <hayashi.kunihiko@socionext.com> + */ + +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_dma.h> +#include <linux/platform_device.h> + +#include "dmaengine.h" +#include "virt-dma.h" + +#define xdmac_ch_width 0x100 + +#define xdmac_tfa 0x08 +#define xdmac_tfa_mcnt_mask genmask(23, 16) +#define xdmac_tfa_mask genmask(5, 0) +#define xdmac_sadm 0x10 +#define xdmac_sadm_stw_mask genmask(25, 24) +#define xdmac_sadm_sam bit(4) +#define xdmac_sadm_sam_fixed xdmac_sadm_sam +#define xdmac_sadm_sam_inc 0 +#define xdmac_dadm 0x14 +#define xdmac_dadm_dtw_mask xdmac_sadm_stw_mask +#define xdmac_dadm_dam xdmac_sadm_sam +#define xdmac_dadm_dam_fixed xdmac_sadm_sam_fixed +#define xdmac_dadm_dam_inc xdmac_sadm_sam_inc +#define xdmac_exsad 0x18 +#define xdmac_exdad 0x1c +#define xdmac_sad 0x20 +#define xdmac_dad 0x24 +#define xdmac_its 0x28 +#define xdmac_its_mask genmask(25, 0) +#define xdmac_tnum 0x2c +#define xdmac_tnum_mask genmask(15, 0) +#define xdmac_tss 0x30 +#define xdmac_tss_req bit(0) +#define xdmac_ien 0x34 +#define xdmac_ien_errien bit(1) +#define xdmac_ien_endien bit(0) +#define xdmac_stat 0x40 +#define xdmac_stat_tenf bit(0) +#define xdmac_ir 0x44 +#define xdmac_ir_errf bit(1) +#define xdmac_ir_endf bit(0) +#define xdmac_id 0x48 +#define xdmac_id_erridf bit(1) +#define xdmac_id_endidf bit(0) + +#define xdmac_max_chans 16 +#define xdmac_interval_clks 20 +#define xdmac_max_words xdmac_tnum_mask + +/* cut lower bit for maintain alignment of maximum transfer size */ +#define xdmac_max_word_size (xdmac_its_mask & ~genmask(3, 0)) + +#define uniphier_xdmac_buswidths \ + (bit(dma_slave_buswidth_1_byte) | \ + bit(dma_slave_buswidth_2_bytes) | \ + bit(dma_slave_buswidth_4_bytes) | \ + bit(dma_slave_buswidth_8_bytes)) + +struct uniphier_xdmac_desc_node { + dma_addr_t src; + dma_addr_t dst; + u32 burst_size; + u32 nr_burst; +}; + +struct uniphier_xdmac_desc { + struct virt_dma_desc vd; + + unsigned int nr_node; + unsigned int cur_node; + enum dma_transfer_direction dir; + struct uniphier_xdmac_desc_node nodes[]; +}; + +struct uniphier_xdmac_chan { + struct virt_dma_chan vc; + struct uniphier_xdmac_device *xdev; + struct uniphier_xdmac_desc *xd; + void __iomem *reg_ch_base; + struct dma_slave_config sconfig; + int id; + unsigned int req_factor; +}; + +struct uniphier_xdmac_device { + struct dma_device ddev; + void __iomem *reg_base; + int nr_chans; + struct uniphier_xdmac_chan channels[]; +}; + +static struct uniphier_xdmac_chan * +to_uniphier_xdmac_chan(struct virt_dma_chan *vc) +{ + return container_of(vc, struct uniphier_xdmac_chan, vc); +} + +static struct uniphier_xdmac_desc * +to_uniphier_xdmac_desc(struct virt_dma_desc *vd) +{ + return container_of(vd, struct uniphier_xdmac_desc, vd); +} + +/* xc->vc.lock must be held by caller */ +static struct uniphier_xdmac_desc * +uniphier_xdmac_next_desc(struct uniphier_xdmac_chan *xc) +{ + struct virt_dma_desc *vd; + + vd = vchan_next_desc(&xc->vc); + if (!vd) + return null; + + list_del(&vd->node); + + return to_uniphier_xdmac_desc(vd); +} + +/* xc->vc.lock must be held by caller */ +static void uniphier_xdmac_chan_start(struct uniphier_xdmac_chan *xc, + struct uniphier_xdmac_desc *xd) +{ + u32 src_mode, src_addr, src_width; + u32 dst_mode, dst_addr, dst_width; + u32 val, its, tnum; + enum dma_slave_buswidth buswidth; + + src_addr = xd->nodes[xd->cur_node].src; + dst_addr = xd->nodes[xd->cur_node].dst; + its = xd->nodes[xd->cur_node].burst_size; + tnum = xd->nodes[xd->cur_node].nr_burst; + + /* + * the width of mem side must be 4 or 8 bytes, that does not + * affect that of dev side and transfer size. + */ + if (xd->dir == dma_dev_to_mem) { + src_mode = xdmac_sadm_sam_fixed; + buswidth = xc->sconfig.src_addr_width; + } else { + src_mode = xdmac_sadm_sam_inc; + buswidth = dma_slave_buswidth_8_bytes; + } + src_width = field_prep(xdmac_sadm_stw_mask, __ffs(buswidth)); + + if (xd->dir == dma_mem_to_dev) { + dst_mode = xdmac_dadm_dam_fixed; + buswidth = xc->sconfig.dst_addr_width; + } else { + dst_mode = xdmac_dadm_dam_inc; + buswidth = dma_slave_buswidth_8_bytes; + } + dst_width = field_prep(xdmac_dadm_dtw_mask, __ffs(buswidth)); + + /* setup transfer factor */ + val = field_prep(xdmac_tfa_mcnt_mask, xdmac_interval_clks); + val |= field_prep(xdmac_tfa_mask, xc->req_factor); + writel(val, xc->reg_ch_base + xdmac_tfa); + + /* setup the channel */ + writel(lower_32_bits(src_addr), xc->reg_ch_base + xdmac_sad); + writel(upper_32_bits(src_addr), xc->reg_ch_base + xdmac_exsad); + + writel(lower_32_bits(dst_addr), xc->reg_ch_base + xdmac_dad); + writel(upper_32_bits(dst_addr), xc->reg_ch_base + xdmac_exdad); + + src_mode |= src_width; + dst_mode |= dst_width; + writel(src_mode, xc->reg_ch_base + xdmac_sadm); + writel(dst_mode, xc->reg_ch_base + xdmac_dadm); + + writel(its, xc->reg_ch_base + xdmac_its); + writel(tnum, xc->reg_ch_base + xdmac_tnum); + + /* enable interrupt */ + writel(xdmac_ien_endien | xdmac_ien_errien, + xc->reg_ch_base + xdmac_ien); + + /* start xdmac */ + val = readl(xc->reg_ch_base + xdmac_tss); + val |= xdmac_tss_req; + writel(val, xc->reg_ch_base + xdmac_tss); +} + +/* xc->vc.lock must be held by caller */ +static int uniphier_xdmac_chan_stop(struct uniphier_xdmac_chan *xc) +{ + u32 val; + + /* disable interrupt */ + val = readl(xc->reg_ch_base + xdmac_ien); + val &= ~(xdmac_ien_endien | xdmac_ien_errien); + writel(val, xc->reg_ch_base + xdmac_ien); + + /* stop xdmac */ + val = readl(xc->reg_ch_base + xdmac_tss); + val &= ~xdmac_tss_req; + writel(0, xc->reg_ch_base + xdmac_tss); + + /* wait until transfer is stopped */ + return readl_poll_timeout(xc->reg_ch_base + xdmac_stat, val, + !(val & xdmac_stat_tenf), 100, 1000); +} + +/* xc->vc.lock must be held by caller */ +static void uniphier_xdmac_start(struct uniphier_xdmac_chan *xc) +{ + struct uniphier_xdmac_desc *xd; + + xd = uniphier_xdmac_next_desc(xc); + if (xd) + uniphier_xdmac_chan_start(xc, xd); + + /* set desc to chan regardless of xd is null */ + xc->xd = xd; +} + +static void uniphier_xdmac_chan_irq(struct uniphier_xdmac_chan *xc) +{ + u32 stat; + int ret; + + spin_lock(&xc->vc.lock); + + stat = readl(xc->reg_ch_base + xdmac_id); + + if (stat & xdmac_id_erridf) { + ret = uniphier_xdmac_chan_stop(xc); + if (ret) + dev_err(xc->xdev->ddev.dev, + "dma transfer error with aborting issue "); + else + dev_err(xc->xdev->ddev.dev, + "dma transfer error "); + + } else if ((stat & xdmac_id_endidf) && xc->xd) { + xc->xd->cur_node++; + if (xc->xd->cur_node >= xc->xd->nr_node) { + vchan_cookie_complete(&xc->xd->vd); + uniphier_xdmac_start(xc); + } else { + uniphier_xdmac_chan_start(xc, xc->xd); + } + } + + /* write bits to clear */ + writel(stat, xc->reg_ch_base + xdmac_ir); + + spin_unlock(&xc->vc.lock); +} + +static irqreturn_t uniphier_xdmac_irq_handler(int irq, void *dev_id) +{ + struct uniphier_xdmac_device *xdev = dev_id; + int i; + + for (i = 0; i < xdev->nr_chans; i++) + uniphier_xdmac_chan_irq(&xdev->channels[i]); + + return irq_handled; +} + +static void uniphier_xdmac_free_chan_resources(struct dma_chan *chan) +{ + vchan_free_chan_resources(to_virt_chan(chan)); +} + +static struct dma_async_tx_descriptor * +uniphier_xdmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dst, + dma_addr_t src, size_t len, unsigned long flags) +{ + struct virt_dma_chan *vc = to_virt_chan(chan); + struct uniphier_xdmac_desc *xd; + unsigned int nr; + size_t burst_size, tlen; + int i; + + if (len > xdmac_max_word_size * xdmac_max_words) + return null; + + nr = 1 + len / xdmac_max_word_size; + + xd = kzalloc(struct_size(xd, nodes, nr), gfp_nowait); + if (!xd) + return null; + + for (i = 0; i < nr; i++) { + burst_size = min_t(size_t, len, xdmac_max_word_size); + xd->nodes[i].src = src; + xd->nodes[i].dst = dst; + xd->nodes[i].burst_size = burst_size; + xd->nodes[i].nr_burst = len / burst_size; + tlen = rounddown(len, burst_size); + src += tlen; + dst += tlen; + len -= tlen; + } + + xd->dir = dma_mem_to_mem; + xd->nr_node = nr; + xd->cur_node = 0; + + return vchan_tx_prep(vc, &xd->vd, flags); +} + +static struct dma_async_tx_descriptor * +uniphier_xdmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, + enum dma_transfer_direction direction, + unsigned long flags, void *context) +{ + struct virt_dma_chan *vc = to_virt_chan(chan); + struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc); + struct uniphier_xdmac_desc *xd; + struct scatterlist *sg; + enum dma_slave_buswidth buswidth; + u32 maxburst; + int i; + + if (!is_slave_direction(direction)) + return null; + + if (direction == dma_dev_to_mem) { + buswidth = xc->sconfig.src_addr_width; + maxburst = xc->sconfig.src_maxburst; + } else { + buswidth = xc->sconfig.dst_addr_width; + maxburst = xc->sconfig.dst_maxburst; + } + + if (!maxburst) + maxburst = 1; + if (maxburst > xc->xdev->ddev.max_burst) { + dev_err(xc->xdev->ddev.dev, + "exceed maximum number of burst words "); + return null; + } + + xd = kzalloc(struct_size(xd, nodes, sg_len), gfp_nowait); + if (!xd) + return null; + + for_each_sg(sgl, sg, sg_len, i) { + xd->nodes[i].src = (direction == dma_dev_to_mem) + ? xc->sconfig.src_addr : sg_dma_address(sg); + xd->nodes[i].dst = (direction == dma_mem_to_dev) + ? xc->sconfig.dst_addr : sg_dma_address(sg); + xd->nodes[i].burst_size = maxburst * buswidth; + xd->nodes[i].nr_burst = + sg_dma_len(sg) / xd->nodes[i].burst_size; + + /* + * currently transfer that size doesn't align the unit size + * (the number of burst words * bus-width) is not allowed, + * because the driver does not support the way to transfer + * residue size. as a matter of fact, in order to transfer + * arbitrary size, 'src_maxburst' or 'dst_maxburst' of + * dma_slave_config must be 1. + */ + if (sg_dma_len(sg) % xd->nodes[i].burst_size) { + dev_err(xc->xdev->ddev.dev, + "unaligned transfer size: %d", sg_dma_len(sg)); + kfree(xd); + return null; + } + + if (xd->nodes[i].nr_burst > xdmac_max_words) { + dev_err(xc->xdev->ddev.dev, + "exceed maximum transfer size"); + kfree(xd); + return null; + } + } + + xd->dir = direction; + xd->nr_node = sg_len; + xd->cur_node = 0; + + return vchan_tx_prep(vc, &xd->vd, flags); +} + +static int uniphier_xdmac_slave_config(struct dma_chan *chan, + struct dma_slave_config *config) +{ + struct virt_dma_chan *vc = to_virt_chan(chan); + struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc); + + memcpy(&xc->sconfig, config, sizeof(*config)); + + return 0; +} + +static int uniphier_xdmac_terminate_all(struct dma_chan *chan) +{ + struct virt_dma_chan *vc = to_virt_chan(chan); + struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc); + unsigned long flags; + int ret = 0; + list_head(head); + + spin_lock_irqsave(&vc->lock, flags); + + if (xc->xd) { + vchan_terminate_vdesc(&xc->xd->vd); + xc->xd = null; + ret = uniphier_xdmac_chan_stop(xc); + } + + vchan_get_all_descriptors(vc, &head); + + spin_unlock_irqrestore(&vc->lock, flags); + + vchan_dma_desc_free_list(vc, &head); + + return ret; +} + +static void uniphier_xdmac_synchronize(struct dma_chan *chan) +{ + vchan_synchronize(to_virt_chan(chan)); +} + +static void uniphier_xdmac_issue_pending(struct dma_chan *chan) +{ + struct virt_dma_chan *vc = to_virt_chan(chan); + struct uniphier_xdmac_chan *xc = to_uniphier_xdmac_chan(vc); + unsigned long flags; + + spin_lock_irqsave(&vc->lock, flags); + + if (vchan_issue_pending(vc) && !xc->xd) + uniphier_xdmac_start(xc); + + spin_unlock_irqrestore(&vc->lock, flags); +} + +static void uniphier_xdmac_desc_free(struct virt_dma_desc *vd) +{ + kfree(to_uniphier_xdmac_desc(vd)); +} + +static void uniphier_xdmac_chan_init(struct uniphier_xdmac_device *xdev, + int ch) +{ + struct uniphier_xdmac_chan *xc = &xdev->channels[ch]; + + xc->xdev = xdev; + xc->reg_ch_base = xdev->reg_base + xdmac_ch_width * ch; + xc->vc.desc_free = uniphier_xdmac_desc_free; + + vchan_init(&xc->vc, &xdev->ddev); +} + +static struct dma_chan *of_dma_uniphier_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct uniphier_xdmac_device *xdev = ofdma->of_dma_data; + int chan_id = dma_spec->args[0]; + + if (chan_id >= xdev->nr_chans) + return null; + + xdev->channels[chan_id].id = chan_id; + xdev->channels[chan_id].req_factor = dma_spec->args[1]; + + return dma_get_slave_channel(&xdev->channels[chan_id].vc.chan); +} + +static int uniphier_xdmac_probe(struct platform_device *pdev) +{ + struct uniphier_xdmac_device *xdev; + struct device *dev = &pdev->dev; + struct dma_device *ddev; + int irq; + int nr_chans; + int i, ret; + + if (of_property_read_u32(dev->of_node, "dma-channels", &nr_chans)) + return -einval; + if (nr_chans > xdmac_max_chans) + nr_chans = xdmac_max_chans; + + xdev = devm_kzalloc(dev, struct_size(xdev, channels, nr_chans), + gfp_kernel); + if (!xdev) + return -enomem; + + xdev->nr_chans = nr_chans; + xdev->reg_base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(xdev->reg_base)) + return ptr_err(xdev->reg_base); + + ddev = &xdev->ddev; + ddev->dev = dev; + dma_cap_zero(ddev->cap_mask); + dma_cap_set(dma_memcpy, ddev->cap_mask); + dma_cap_set(dma_slave, ddev->cap_mask); + ddev->src_addr_widths = uniphier_xdmac_buswidths; + ddev->dst_addr_widths = uniphier_xdmac_buswidths; + ddev->directions = bit(dma_dev_to_mem) | bit(dma_mem_to_dev) | + bit(dma_mem_to_mem); + ddev->residue_granularity = dma_residue_granularity_burst; + ddev->max_burst = xdmac_max_words; + ddev->device_free_chan_resources = uniphier_xdmac_free_chan_resources; + ddev->device_prep_dma_memcpy = uniphier_xdmac_prep_dma_memcpy; + ddev->device_prep_slave_sg = uniphier_xdmac_prep_slave_sg; + ddev->device_config = uniphier_xdmac_slave_config; + ddev->device_terminate_all = uniphier_xdmac_terminate_all; + ddev->device_synchronize = uniphier_xdmac_synchronize; + ddev->device_tx_status = dma_cookie_status; + ddev->device_issue_pending = uniphier_xdmac_issue_pending; + init_list_head(&ddev->channels); + + for (i = 0; i < nr_chans; i++) + uniphier_xdmac_chan_init(xdev, i); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "failed to get irq "); + return irq; + } + + ret = devm_request_irq(dev, irq, uniphier_xdmac_irq_handler, + irqf_shared, "xdmac", xdev); + if (ret) { + dev_err(dev, "failed to request irq "); + return ret; + } + + ret = dma_async_device_register(ddev); + if (ret) { + dev_err(dev, "failed to register xdma device "); + return ret; + } + + ret = of_dma_controller_register(dev->of_node, + of_dma_uniphier_xlate, xdev); + if (ret) { + dev_err(dev, "failed to register xdma controller "); + goto out_unregister_dmac; + } + + platform_set_drvdata(pdev, xdev); + + dev_info(&pdev->dev, "uniphier xdmac driver (%d channels) ", + nr_chans); + + return 0; + +out_unregister_dmac: + dma_async_device_unregister(ddev); + + return ret; +} + +static int uniphier_xdmac_remove(struct platform_device *pdev) +{ + struct uniphier_xdmac_device *xdev = platform_get_drvdata(pdev); + struct dma_device *ddev = &xdev->ddev; + struct dma_chan *chan; + int ret; + + /* + * before reaching here, almost all descriptors have been freed by the + * ->device_free_chan_resources() hook. however, each channel might + * be still holding one descriptor that was on-flight at that moment. + * terminate it to make sure this hardware is no longer running. then, + * free the channel resources once again to avoid memory leak. + */ + list_for_each_entry(chan, &ddev->channels, device_node) { + ret = dmaengine_terminate_sync(chan); + if (ret) + return ret; + uniphier_xdmac_free_chan_resources(chan); + } + + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(ddev); + + return 0; +} + +static const struct of_device_id uniphier_xdmac_match[] = { + { .compatible = "socionext,uniphier-xdmac" }, + { /* sentinel */ } +}; +module_device_table(of, uniphier_xdmac_match); + +static struct platform_driver uniphier_xdmac_driver = { + .probe = uniphier_xdmac_probe, + .remove = uniphier_xdmac_remove, + .driver = { + .name = "uniphier-xdmac", + .of_match_table = uniphier_xdmac_match, + }, +}; +module_platform_driver(uniphier_xdmac_driver); + +module_author("kunihiko hayashi <hayashi.kunihiko@socionext.com>"); +module_description("uniphier external dma controller driver"); +module_license("gpl v2");
|
DMA engines
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667b9251440b762ebc8cd3348a6e6ab29401bb97
|
kunihiko hayashi
|
drivers
|
dma
| |
crypto: caam - refactor skcipher/aead/gcm/chachapoly {en,de}crypt functions
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create a common crypt function for each skcipher/aead/gcm/chachapoly algorithms and call it for encrypt/decrypt with the specific boolean - true for encrypt and false for decrypt.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for skcipher, hash, rsa and aead algorithms
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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['caam']
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['c']
| 1
| 53
| 215
|
--- diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c -static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) +static void aead_crypt_done(struct device *jrdev, u32 *desc, u32 err, + void *context) -static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) -{ - struct aead_request *req = context; - struct aead_edesc *edesc; - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x ", __func__, __line__, err); - - edesc = container_of(desc, struct aead_edesc, hw_desc[0]); - - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - aead_unmap(jrdev, edesc, req); - - kfree(edesc); - - aead_request_complete(req, ecode); -} - -static void skcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) -{ - struct skcipher_request *req = context; - struct skcipher_edesc *edesc; - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); - int ivsize = crypto_skcipher_ivsize(skcipher); - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x ", __func__, __line__, err); - - edesc = container_of(desc, struct skcipher_edesc, hw_desc[0]); - - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - skcipher_unmap(jrdev, edesc, req); - - /* - * the crypto api expects us to set the iv (req->iv) to the last - * ciphertext block (cbc mode) or last counter (ctr mode). - * this is used e.g. by the cts mode. - */ - if (ivsize && !ecode) { - memcpy(req->iv, (u8 *)edesc->sec4_sg + edesc->sec4_sg_bytes, - ivsize); - print_hex_dump_debug("dstiv @"__stringify(__line__)": ", - dump_prefix_address, 16, 4, req->iv, - edesc->src_nents > 1 ? 100 : ivsize, 1); - } - - caam_dump_sg("dst @" __stringify(__line__)": ", - dump_prefix_address, 16, 4, req->dst, - edesc->dst_nents > 1 ? 100 : req->cryptlen, 1); - - kfree(edesc); - - skcipher_request_complete(req, ecode); -} - -static void skcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err, - void *context) +static void skcipher_crypt_done(struct device *jrdev, u32 *desc, u32 err, + void *context) -static int gcm_encrypt(struct aead_request *req) -{ - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - bool all_contig; - u32 *desc; - int ret = 0; - - /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, gcm_desc_job_io_len, &all_contig, true); - if (is_err(edesc)) - return ptr_err(edesc); - - /* create and submit job descriptor */ - init_gcm_job(req, edesc, all_contig, true); - - print_hex_dump_debug("aead jobdesc@"__stringify(__line__)": ", - dump_prefix_address, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); - if (!ret) { - ret = -einprogress; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; -} - -static int chachapoly_encrypt(struct aead_request *req) +static inline int chachapoly_crypt(struct aead_request *req, bool encrypt) - true); + encrypt); - init_chachapoly_job(req, edesc, all_contig, true); + init_chachapoly_job(req, edesc, all_contig, encrypt); - ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); + ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); -static int chachapoly_decrypt(struct aead_request *req) +static int chachapoly_encrypt(struct aead_request *req) - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - bool all_contig; - u32 *desc; - int ret; - - edesc = aead_edesc_alloc(req, chachapoly_desc_job_io_len, &all_contig, - false); - if (is_err(edesc)) - return ptr_err(edesc); - - desc = edesc->hw_desc; - - init_chachapoly_job(req, edesc, all_contig, false); - print_hex_dump_debug("chachapoly jobdesc@" __stringify(__line__)": ", - dump_prefix_address, 16, 4, desc, desc_bytes(desc), - 1); - - ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); - if (!ret) { - ret = -einprogress; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; + return chachapoly_crypt(req, true); -static int ipsec_gcm_encrypt(struct aead_request *req) +static int chachapoly_decrypt(struct aead_request *req) - return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_encrypt(req); + return chachapoly_crypt(req, false); -static int aead_encrypt(struct aead_request *req) +static inline int aead_crypt(struct aead_request *req, bool encrypt) - &all_contig, true); + &all_contig, encrypt); - init_authenc_job(req, edesc, all_contig, true); + init_authenc_job(req, edesc, all_contig, encrypt); - ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req); + ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); -static int gcm_decrypt(struct aead_request *req) +static int aead_encrypt(struct aead_request *req) +{ + return aead_crypt(req, true); +} + +static int aead_decrypt(struct aead_request *req) +{ + return aead_crypt(req, false); +} + +static inline int gcm_crypt(struct aead_request *req, bool encrypt) - edesc = aead_edesc_alloc(req, gcm_desc_job_io_len, &all_contig, false); + edesc = aead_edesc_alloc(req, gcm_desc_job_io_len, &all_contig, + encrypt); - /* create and submit job descriptor*/ - init_gcm_job(req, edesc, all_contig, false); + /* create and submit job descriptor */ + init_gcm_job(req, edesc, all_contig, encrypt); - ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); + ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); -static int ipsec_gcm_decrypt(struct aead_request *req) +static int gcm_encrypt(struct aead_request *req) - return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_decrypt(req); + return gcm_crypt(req, true); -static int aead_decrypt(struct aead_request *req) +static int gcm_decrypt(struct aead_request *req) - struct aead_edesc *edesc; - struct crypto_aead *aead = crypto_aead_reqtfm(req); - struct caam_ctx *ctx = crypto_aead_ctx(aead); - struct device *jrdev = ctx->jrdev; - bool all_contig; - u32 *desc; - int ret = 0; - - caam_dump_sg("dec src@" __stringify(__line__)": ", - dump_prefix_address, 16, 4, req->src, - req->assoclen + req->cryptlen, 1); - - /* allocate extended descriptor */ - edesc = aead_edesc_alloc(req, authenc_desc_job_io_len, - &all_contig, false); - if (is_err(edesc)) - return ptr_err(edesc); - - /* create and submit job descriptor*/ - init_authenc_job(req, edesc, all_contig, false); - - print_hex_dump_debug("aead jobdesc@"__stringify(__line__)": ", - dump_prefix_address, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); + return gcm_crypt(req, false); +} - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req); - if (!ret) { - ret = -einprogress; - } else { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } +static int ipsec_gcm_encrypt(struct aead_request *req) +{ + return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_encrypt(req); +} - return ret; +static int ipsec_gcm_decrypt(struct aead_request *req) +{ + return crypto_ipsec_check_assoclen(req->assoclen) ? : gcm_decrypt(req); -static int skcipher_encrypt(struct skcipher_request *req) +static inline int skcipher_crypt(struct skcipher_request *req, bool encrypt) - init_skcipher_job(req, edesc, true); + init_skcipher_job(req, edesc, encrypt); - ret = caam_jr_enqueue(jrdev, desc, skcipher_encrypt_done, req); + ret = caam_jr_enqueue(jrdev, desc, skcipher_crypt_done, req); -static int skcipher_decrypt(struct skcipher_request *req) +static int skcipher_encrypt(struct skcipher_request *req) - struct skcipher_edesc *edesc; - struct crypto_skcipher *skcipher = crypto_skcipher_reqtfm(req); - struct caam_ctx *ctx = crypto_skcipher_ctx(skcipher); - struct device *jrdev = ctx->jrdev; - u32 *desc; - int ret = 0; - - if (!req->cryptlen) - return 0; - - /* allocate extended descriptor */ - edesc = skcipher_edesc_alloc(req, desc_job_io_len * caam_cmd_sz); - if (is_err(edesc)) - return ptr_err(edesc); - - /* create and submit job descriptor*/ - init_skcipher_job(req, edesc, false); - desc = edesc->hw_desc; - - print_hex_dump_debug("skcipher jobdesc@" __stringify(__line__)": ", - dump_prefix_address, 16, 4, edesc->hw_desc, - desc_bytes(edesc->hw_desc), 1); - - ret = caam_jr_enqueue(jrdev, desc, skcipher_decrypt_done, req); - if (!ret) { - ret = -einprogress; - } else { - skcipher_unmap(jrdev, edesc, req); - kfree(edesc); - } + return skcipher_crypt(req, true); +} - return ret; +static int skcipher_decrypt(struct skcipher_request *req) +{ + return skcipher_crypt(req, false);
|
Cryptography hardware acceleration
|
b7f17fe281442de420cbd9b4a6ad34b1d498aec6
|
iuliana prodan horia geanta horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - refactor ahash_done callbacks
|
create two common ahash_done_* functions with the dma direction as parameter. then, these 2 are called with the proper direction for unmap.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['c']
| 1
| 22
| 66
|
--- diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c -static void ahash_done(struct device *jrdev, u32 *desc, u32 err, - void *context) +static inline void ahash_done_cpy(struct device *jrdev, u32 *desc, u32 err, + void *context, enum dma_data_direction dir) - ahash_unmap_ctx(jrdev, edesc, req, digestsize, dma_from_device); + ahash_unmap_ctx(jrdev, edesc, req, digestsize, dir); -static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err, - void *context) +static void ahash_done(struct device *jrdev, u32 *desc, u32 err, + void *context) - struct ahash_request *req = context; - struct ahash_edesc *edesc; - struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); - struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); - struct caam_hash_state *state = ahash_request_ctx(req); - int digestsize = crypto_ahash_digestsize(ahash); - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x ", __func__, __line__, err); - - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, dma_bidirectional); - kfree(edesc); - - scatterwalk_map_and_copy(state->buf, req->src, - req->nbytes - state->next_buflen, - state->next_buflen, 0); - state->buflen = state->next_buflen; - - print_hex_dump_debug("buf@" __stringify(__line__)": ", - dump_prefix_address, 16, 4, state->buf, - state->buflen, 1); - - print_hex_dump_debug("ctx@"__stringify(__line__)": ", - dump_prefix_address, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - if (req->result) - print_hex_dump_debug("result@"__stringify(__line__)": ", - dump_prefix_address, 16, 4, req->result, - digestsize, 1); - - req->base.complete(&req->base, ecode); + ahash_done_cpy(jrdev, desc, err, context, dma_from_device); - struct ahash_request *req = context; - struct ahash_edesc *edesc; - struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); - int digestsize = crypto_ahash_digestsize(ahash); - struct caam_hash_state *state = ahash_request_ctx(req); - struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); - int ecode = 0; - - dev_dbg(jrdev, "%s %d: err 0x%x ", __func__, __line__, err); - - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); - if (err) - ecode = caam_jr_strstatus(jrdev, err); - - ahash_unmap_ctx(jrdev, edesc, req, digestsize, dma_bidirectional); - memcpy(req->result, state->caam_ctx, digestsize); - kfree(edesc); - - print_hex_dump_debug("ctx@"__stringify(__line__)": ", - dump_prefix_address, 16, 4, state->caam_ctx, - ctx->ctx_len, 1); - - req->base.complete(&req->base, ecode); + ahash_done_cpy(jrdev, desc, err, context, dma_bidirectional); -static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, - void *context) +static inline void ahash_done_switch(struct device *jrdev, u32 *desc, u32 err, + void *context, enum dma_data_direction dir) - ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, dma_from_device); + ahash_unmap_ctx(jrdev, edesc, req, ctx->ctx_len, dir); +static void ahash_done_bi(struct device *jrdev, u32 *desc, u32 err, + void *context) +{ + ahash_done_switch(jrdev, desc, err, context, dma_bidirectional); +} + +static void ahash_done_ctx_dst(struct device *jrdev, u32 *desc, u32 err, + void *context) +{ + ahash_done_switch(jrdev, desc, err, context, dma_from_device); +} +
|
Cryptography hardware acceleration
|
c3f7394eb9546cad7e2ff28aeccdd4655d15fd17
|
iuliana prodan horia geanta horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - refactor ahash_edesc_alloc
|
changed parameters for ahash_edesc_alloc function: - remove flags since they can be computed in ahash_edesc_alloc, the only place they are needed; - use ahash_request instead of caam_hash_ctx, to be able to compute gfp flags.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['c']
| 1
| 22
| 40
|
- remove flags since they can be computed in - use ahash_request instead of caam_hash_ctx, to be --- diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c -static struct ahash_edesc *ahash_edesc_alloc(struct caam_hash_ctx *ctx, +static struct ahash_edesc *ahash_edesc_alloc(struct ahash_request *req, - dma_addr_t sh_desc_dma, - gfp_t flags) + dma_addr_t sh_desc_dma) + struct crypto_ahash *ahash = crypto_ahash_reqtfm(req); + struct caam_hash_ctx *ctx = crypto_ahash_ctx(ahash); + gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? + gfp_kernel : gfp_atomic; - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, pad_nents, ctx->sh_desc_update, - ctx->sh_desc_update_dma, flags); + edesc = ahash_edesc_alloc(req, pad_nents, ctx->sh_desc_update, + ctx->sh_desc_update_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, 4, ctx->sh_desc_fin, - ctx->sh_desc_fin_dma, flags); + edesc = ahash_edesc_alloc(req, 4, ctx->sh_desc_fin, + ctx->sh_desc_fin_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents, - ctx->sh_desc_fin, ctx->sh_desc_fin_dma, - flags); + edesc = ahash_edesc_alloc(req, sec4_sg_src_index + mapped_nents, + ctx->sh_desc_fin, ctx->sh_desc_fin_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, mapped_nents > 1 ? mapped_nents : 0, - ctx->sh_desc_digest, ctx->sh_desc_digest_dma, - flags); + edesc = ahash_edesc_alloc(req, mapped_nents > 1 ? mapped_nents : 0, + ctx->sh_desc_digest, ctx->sh_desc_digest_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, 0, ctx->sh_desc_digest, - ctx->sh_desc_digest_dma, flags); + edesc = ahash_edesc_alloc(req, 0, ctx->sh_desc_digest, + ctx->sh_desc_digest_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, pad_nents, + edesc = ahash_edesc_alloc(req, pad_nents, - ctx->sh_desc_update_first_dma, - flags); + ctx->sh_desc_update_first_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, sec4_sg_src_index + mapped_nents, - ctx->sh_desc_digest, ctx->sh_desc_digest_dma, - flags); + edesc = ahash_edesc_alloc(req, sec4_sg_src_index + mapped_nents, + ctx->sh_desc_digest, ctx->sh_desc_digest_dma); - gfp_t flags = (req->base.flags & crypto_tfm_req_may_sleep) ? - gfp_kernel : gfp_atomic; - edesc = ahash_edesc_alloc(ctx, mapped_nents > 1 ? + edesc = ahash_edesc_alloc(req, mapped_nents > 1 ? - ctx->sh_desc_update_first_dma, - flags); + ctx->sh_desc_update_first_dma);
|
Cryptography hardware acceleration
|
2ba1e79831aa0388d0d08ad649ecb933f317b61d
|
iuliana prodan horia geanta horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - refactor rsa private key _done callbacks
|
create a common rsa_priv_f_done function, which based on private key form calls the specific unmap function.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['c']
| 1
| 18
| 43
|
--- diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c -static void rsa_priv_f1_done(struct device *dev, u32 *desc, u32 err, - void *context) -{ - struct akcipher_request *req = context; - struct rsa_edesc *edesc; - int ecode = 0; - - if (err) - ecode = caam_jr_strstatus(dev, err); - - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); - - rsa_priv_f1_unmap(dev, edesc, req); - rsa_io_unmap(dev, edesc, req); - kfree(edesc); - - akcipher_request_complete(req, ecode); -} - -static void rsa_priv_f2_done(struct device *dev, u32 *desc, u32 err, - void *context) +static void rsa_priv_f_done(struct device *dev, u32 *desc, u32 err, + void *context) + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); + struct caam_rsa_key *key = &ctx->key; - rsa_priv_f2_unmap(dev, edesc, req); - rsa_io_unmap(dev, edesc, req); - kfree(edesc); - - akcipher_request_complete(req, ecode); -} - -static void rsa_priv_f3_done(struct device *dev, u32 *desc, u32 err, - void *context) -{ - struct akcipher_request *req = context; - struct rsa_edesc *edesc; - int ecode = 0; - - if (err) - ecode = caam_jr_strstatus(dev, err); - - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); + switch (key->priv_form) { + case form1: + rsa_priv_f1_unmap(dev, edesc, req); + break; + case form2: + rsa_priv_f2_unmap(dev, edesc, req); + break; + case form3: + rsa_priv_f3_unmap(dev, edesc, req); + } - rsa_priv_f3_unmap(dev, edesc, req); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f1_done, req); + ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f_done, req); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f2_done, req); + ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f_done, req); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f3_done, req); + ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f_done, req);
|
Cryptography hardware acceleration
|
d53e44fe980ba7325ac60f85312c9facf78fbba1
|
iuliana prodan horia geanta horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - change return code in caam_jr_enqueue function
|
based on commit 6b80ea389a0b ("crypto: change transient busy return code to -enospc"), change the return code of caam_jr_enqueue function to -einprogress, in case of success, -enospc in case the caam is busy (has no space left in job ring queue), -eio if it cannot map the caller's descriptor.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['c']
| 6
| 30
| 50
|
--- diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c - if (!ret) { + if (ret == -einprogress) { - if (ret) + if (ret != -einprogress) - - ret = -einprogress; - if (ret) - goto unmap_ctx; + if (ret == -einprogress) + return ret; - return -einprogress; - if (ret) - goto unmap_ctx; + if (ret == -einprogress) + return ret; - return -einprogress; - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { - if (ret) + if (ret != -einprogress) - ret = -einprogress; - if (!ret) { - ret = -einprogress; - } else { + if (ret != -einprogress) { - if (ret) + if (ret != -einprogress) - ret = -einprogress; diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c - if (!ret) - return -einprogress; + if (ret == -einprogress) + return ret; - if (!ret) - return -einprogress; + if (ret == -einprogress) + return ret; - if (!ret) - return -einprogress; + if (ret == -einprogress) + return ret; - if (!ret) - return -einprogress; + if (ret == -einprogress) + return ret; diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c --- a/drivers/crypto/caam/caamrng.c +++ b/drivers/crypto/caam/caamrng.c - if (err) + if (err != -einprogress) - if (err) + if (err != -einprogress) diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c - * caam_jr_enqueue() - enqueue a job descriptor head. returns 0 if ok, - * -ebusy if the queue is full, -eio if it cannot map the caller's + * caam_jr_enqueue() - enqueue a job descriptor head. returns -einprogress + * if ok, -enospc if the queue is full, -eio if it cannot map the caller's - return -ebusy; + return -enospc; - return 0; + return -einprogress; diff --git a/drivers/crypto/caam/key_gen.c b/drivers/crypto/caam/key_gen.c --- a/drivers/crypto/caam/key_gen.c +++ b/drivers/crypto/caam/key_gen.c - if (!ret) { + if (ret == -einprogress) {
|
Cryptography hardware acceleration
|
4d370a1036958d7df9f1492c345b4984a4eba7f6
|
iuliana prodan
|
drivers
|
crypto
|
caam
|
crypto: caam - support crypto_engine framework for skcipher algorithms
|
integrate crypto_engine into caam, to make use of the engine queue. add support for skcipher algorithms.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['h', 'kconfig', 'c']
| 4
| 101
| 8
|
-einprogress if ok, -ebusy if request is backlogged (via --- diff --git a/drivers/crypto/caam/kconfig b/drivers/crypto/caam/kconfig --- a/drivers/crypto/caam/kconfig +++ b/drivers/crypto/caam/kconfig + select crypto_engine diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c +#include <crypto/engine.h> + struct crypto_engine_ctx enginectx; +struct caam_skcipher_req_ctx { + struct skcipher_edesc *edesc; +}; + + * @bklog: stored to determine if the request needs backlog + bool bklog; + struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); - edesc = container_of(desc, struct skcipher_edesc, hw_desc[0]); + edesc = rctx->edesc; - skcipher_request_complete(req, ecode); + /* + * if no backlog flag, the completion of the request is done + * by caam, not crypto engine. + */ + if (!edesc->bklog) + skcipher_request_complete(req, ecode); + else + crypto_finalize_skcipher_request(jrp->engine, req, ecode); + struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req); + rctx->edesc = edesc; +static int skcipher_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct skcipher_request *req = skcipher_request_cast(areq); + struct caam_ctx *ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)); + struct caam_skcipher_req_ctx *rctx = skcipher_request_ctx(req); + u32 *desc = rctx->edesc->hw_desc; + int ret; + + rctx->edesc->bklog = true; + + ret = caam_jr_enqueue(ctx->jrdev, desc, skcipher_crypt_done, req); + + if (ret != -einprogress) { + skcipher_unmap(ctx->jrdev, rctx->edesc, req); + kfree(rctx->edesc); + } else { + ret = 0; + } + + return ret; +} + + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); - ret = caam_jr_enqueue(jrdev, desc, skcipher_crypt_done, req); + /* + * only the backlog request are sent to crypto-engine since the others + * can be handled by caam, if free, especially since jr has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & crypto_tfm_req_may_backlog) + ret = crypto_transfer_skcipher_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, skcipher_crypt_done, req); - if (ret != -einprogress) { + if ((ret != -einprogress) && (ret != -ebusy)) { + const size_t sh_desc_enc_offset = offsetof(struct caam_ctx, + sh_desc_enc); - sh_desc_enc_dma), + sh_desc_enc_dma) - + sh_desc_enc_offset, - sh_desc_dec); - ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key); + sh_desc_dec) - + sh_desc_enc_offset; + ctx->key_dma = dma_addr + offsetof(struct caam_ctx, key) - + sh_desc_enc_offset; + struct caam_ctx *ctx = crypto_skcipher_ctx(tfm); + + crypto_skcipher_set_reqsize(tfm, sizeof(struct caam_skcipher_req_ctx)); + + ctx->enginectx.op.do_one_request = skcipher_do_one_req; - offsetof(struct caam_ctx, sh_desc_enc_dma), + offsetof(struct caam_ctx, sh_desc_enc_dma) - + offsetof(struct caam_ctx, sh_desc_enc), diff --git a/drivers/crypto/caam/intern.h b/drivers/crypto/caam/intern.h --- a/drivers/crypto/caam/intern.h +++ b/drivers/crypto/caam/intern.h +#include <crypto/engine.h> + struct crypto_engine *engine; diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c --- a/drivers/crypto/caam/jr.c +++ b/drivers/crypto/caam/jr.c +static void caam_jr_crypto_engine_exit(void *data) +{ + struct device *jrdev = data; + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + + /* free the resources of crypto-engine */ + crypto_engine_exit(jrpriv->engine); +} + + /* initialize crypto engine */ + jrpriv->engine = crypto_engine_alloc_init(jrdev, false); + if (!jrpriv->engine) { + dev_err(jrdev, "could not init crypto-engine "); + return -enomem; + } + + error = devm_add_action_or_reset(jrdev, caam_jr_crypto_engine_exit, + jrdev); + if (error) + return error; + + /* start crypto engine */ + error = crypto_engine_start(jrpriv->engine); + if (error) { + dev_err(jrdev, "could not start crypto-engine "); + return error; + } +
|
Cryptography hardware acceleration
|
ee38767f152a3310aabee7074848911f43bf5d69
|
iuliana prodan
|
drivers
|
crypto
|
caam
|
crypto: caam - add crypto_engine support for aead algorithms
|
add crypto_engine support for aead algorithms, to make use of the engine queue. the requests, with backlog flag, will be listed into crypto-engine queue and processed by caam when free. if sending just the backlog request to crypto-engine, and non-blocking directly to caam, the latter requests have a better chance to be executed since jr has up to 1024 entries, more than the 10 entries from crypto-engine.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['c']
| 1
| 77
| 30
|
--- diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c --- a/drivers/crypto/caam/caamalg.c +++ b/drivers/crypto/caam/caamalg.c +struct caam_aead_req_ctx { + struct aead_edesc *edesc; +}; + + * @bklog: stored to determine if the request needs backlog + bool bklog; + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); - edesc = container_of(desc, struct aead_edesc, hw_desc[0]); + edesc = rctx->edesc; - aead_request_complete(req, ecode); + /* + * if no backlog flag, the completion of the request is done + * by caam, not crypto engine. + */ + if (!edesc->bklog) + aead_request_complete(req, ecode); + else + crypto_finalize_aead_request(jrp->engine, req, ecode); + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + + rctx->edesc = edesc; + +static int aead_enqueue_req(struct device *jrdev, struct aead_request *req) +{ + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + struct aead_edesc *edesc = rctx->edesc; + u32 *desc = edesc->hw_desc; + int ret; + + /* + * only the backlog request are sent to crypto-engine since the others + * can be handled by caam, if free, especially since jr has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & crypto_tfm_req_may_backlog) + ret = crypto_transfer_aead_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); + + if ((ret != -einprogress) && (ret != -ebusy)) { + aead_unmap(jrdev, edesc, req); + kfree(rctx->edesc); + } + + return ret; +} + - int ret; - ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); - if (ret != -einprogress) { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; + return aead_enqueue_req(jrdev, req); - u32 *desc; - int ret = 0; - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); - if (ret != -einprogress) { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; + return aead_enqueue_req(jrdev, req); +static int aead_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct aead_request *req = aead_request_cast(areq); + struct caam_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req)); + struct caam_aead_req_ctx *rctx = aead_request_ctx(req); + u32 *desc = rctx->edesc->hw_desc; + int ret; + + rctx->edesc->bklog = true; + + ret = caam_jr_enqueue(ctx->jrdev, desc, aead_crypt_done, req); + + if (ret != -einprogress) { + aead_unmap(ctx->jrdev, rctx->edesc, req); + kfree(rctx->edesc); + } else { + ret = 0; + } + + return ret; +} + - u32 *desc; - int ret = 0; - desc = edesc->hw_desc; - ret = caam_jr_enqueue(jrdev, desc, aead_crypt_done, req); - if (ret != -einprogress) { - aead_unmap(jrdev, edesc, req); - kfree(edesc); - } - - return ret; + return aead_enqueue_req(jrdev, req); + crypto_aead_set_reqsize(tfm, sizeof(struct caam_aead_req_ctx)); + + ctx->enginectx.op.do_one_request = aead_do_one_req; +
|
Cryptography hardware acceleration
|
1c24022667130eefe15d49b906373807f181305c
|
iuliana prodan horia geant horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - add crypto_engine support for rsa algorithms
|
add crypto_engine support for rsa algorithms, to make use of the engine queue. the requests, with backlog flag, will be listed into crypto-engine queue and processed by caam when free. in case the queue is empty, the request is directly sent to caam. only the backlog request are sent to crypto-engine since the others can be handled by caam, if free, especially since jr has up to 1024 entries (more than the 10 entries from crypto-engine).
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['h', 'c']
| 2
| 114
| 24
|
--- diff --git a/drivers/crypto/caam/caampkc.c b/drivers/crypto/caam/caampkc.c --- a/drivers/crypto/caam/caampkc.c +++ b/drivers/crypto/caam/caampkc.c + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); + edesc = req_ctx->edesc; - akcipher_request_complete(req, ecode); + /* + * if no backlog flag, the completion of the request is done + * by caam, not crypto engine. + */ + if (!edesc->bklog) + akcipher_request_complete(req, ecode); + else + crypto_finalize_akcipher_request(jrp->engine, req, ecode); + struct caam_drv_private_jr *jrp = dev_get_drvdata(dev); + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); - edesc = container_of(desc, struct rsa_edesc, hw_desc[0]); + edesc = req_ctx->edesc; - akcipher_request_complete(req, ecode); + /* + * if no backlog flag, the completion of the request is done + * by caam, not crypto engine. + */ + if (!edesc->bklog) + akcipher_request_complete(req, ecode); + else + crypto_finalize_akcipher_request(jrp->engine, req, ecode); + req_ctx->edesc = edesc; + +static int akcipher_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct akcipher_request *req = container_of(areq, + struct akcipher_request, + base); + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); + struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); + struct device *jrdev = ctx->dev; + u32 *desc = req_ctx->edesc->hw_desc; + int ret; + + req_ctx->edesc->bklog = true; + + ret = caam_jr_enqueue(jrdev, desc, req_ctx->akcipher_op_done, req); + + if (ret != -einprogress) { + rsa_pub_unmap(jrdev, req_ctx->edesc, req); + rsa_io_unmap(jrdev, req_ctx->edesc, req); + kfree(req_ctx->edesc); + } else { + ret = 0; + } + + return ret; +} + +static int akcipher_enqueue_req(struct device *jrdev, + void (*cbk)(struct device *jrdev, u32 *desc, + u32 err, void *context), + struct akcipher_request *req) +{ + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + struct crypto_akcipher *tfm = crypto_akcipher_reqtfm(req); + struct caam_rsa_ctx *ctx = akcipher_tfm_ctx(tfm); + struct caam_rsa_key *key = &ctx->key; + struct caam_rsa_req_ctx *req_ctx = akcipher_request_ctx(req); + struct rsa_edesc *edesc = req_ctx->edesc; + u32 *desc = edesc->hw_desc; + int ret; + + req_ctx->akcipher_op_done = cbk; + /* + * only the backlog request are sent to crypto-engine since the others + * can be handled by caam, if free, especially since jr has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & crypto_tfm_req_may_backlog) + ret = crypto_transfer_akcipher_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, cbk, req); + + if ((ret != -einprogress) && (ret != -ebusy)) { + switch (key->priv_form) { + case form1: + rsa_priv_f1_unmap(jrdev, edesc, req); + break; + case form2: + rsa_priv_f2_unmap(jrdev, edesc, req); + break; + case form3: + rsa_priv_f3_unmap(jrdev, edesc, req); + break; + default: + rsa_pub_unmap(jrdev, edesc, req); + } + rsa_io_unmap(jrdev, edesc, req); + kfree(edesc); + } + + return ret; +} + - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_pub_done, req); - if (ret == -einprogress) - return ret; - - rsa_pub_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_pub_done, req); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f_done, req); - if (ret == -einprogress) - return ret; - - rsa_priv_f1_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_priv_f_done, req); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f_done, req); - if (ret == -einprogress) - return ret; - - rsa_priv_f2_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_priv_f_done, req); - ret = caam_jr_enqueue(jrdev, edesc->hw_desc, rsa_priv_f_done, req); - if (ret == -einprogress) - return ret; - - rsa_priv_f3_unmap(jrdev, edesc, req); + return akcipher_enqueue_req(jrdev, rsa_priv_f_done, req); + ctx->enginectx.op.do_one_request = akcipher_do_one_req; + diff --git a/drivers/crypto/caam/caampkc.h b/drivers/crypto/caam/caampkc.h --- a/drivers/crypto/caam/caampkc.h +++ b/drivers/crypto/caam/caampkc.h +#include <crypto/engine.h> + * @enginectx : crypto engine context + struct crypto_engine_ctx enginectx; + * @edesc : s/w-extended rsa descriptor + * @akcipher_op_done : callback used when operation is done + struct rsa_edesc *edesc; + void (*akcipher_op_done)(struct device *jrdev, u32 *desc, u32 err, + void *context); + * @bklog : stored to determine if the request needs backlog + bool bklog;
|
Cryptography hardware acceleration
|
bf53795025a2b026c89b45be1d832a325a2a9258
|
iuliana prodan horia geant horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - add crypto_engine support for hash algorithms
|
add crypto_engine support for hash algorithms, to make use of the engine queue. the requests, with backlog flag, will be listed into crypto-engine queue and processed by caam when free. only the backlog request are sent to crypto-engine since the others can be handled by caam, if free, especially since jr has up to 1024 entries (more than the 10 entries from crypto-engine).
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for skcipher, hash, rsa and aead algorithms
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['c']
| 1
| 123
| 51
|
--- diff --git a/drivers/crypto/caam/caamhash.c b/drivers/crypto/caam/caamhash.c --- a/drivers/crypto/caam/caamhash.c +++ b/drivers/crypto/caam/caamhash.c +#include <crypto/engine.h> + struct crypto_engine_ctx enginectx; - int (*update)(struct ahash_request *req); + int (*update)(struct ahash_request *req) ____cacheline_aligned; + struct ahash_edesc *edesc; + void (*ahash_op_done)(struct device *jrdev, u32 *desc, u32 err, + void *context); + * @bklog: stored to determine if the request needs backlog + bool bklog; + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); + edesc = state->edesc; + - req->base.complete(&req->base, ecode); + /* + * if no backlog flag, the completion of the request is done + * by caam, not crypto engine. + */ + if (!edesc->bklog) + req->base.complete(&req->base, ecode); + else + crypto_finalize_hash_request(jrp->engine, req, ecode); + struct caam_drv_private_jr *jrp = dev_get_drvdata(jrdev); - edesc = container_of(desc, struct ahash_edesc, hw_desc[0]); + edesc = state->edesc; - req->base.complete(&req->base, ecode); + /* + * if no backlog flag, the completion of the request is done + * by caam, not crypto engine. + */ + if (!edesc->bklog) + req->base.complete(&req->base, ecode); + else + crypto_finalize_hash_request(jrp->engine, req, ecode); + + struct caam_hash_state *state = ahash_request_ctx(req); + state->edesc = edesc; + +static int ahash_do_one_req(struct crypto_engine *engine, void *areq) +{ + struct ahash_request *req = ahash_request_cast(areq); + struct caam_hash_ctx *ctx = crypto_ahash_ctx(crypto_ahash_reqtfm(req)); + struct caam_hash_state *state = ahash_request_ctx(req); + struct device *jrdev = ctx->jrdev; + u32 *desc = state->edesc->hw_desc; + int ret; + + state->edesc->bklog = true; + + ret = caam_jr_enqueue(jrdev, desc, state->ahash_op_done, req); + + if (ret != -einprogress) { + ahash_unmap(jrdev, state->edesc, req, 0); + kfree(state->edesc); + } else { + ret = 0; + } + + return ret; +} + +static int ahash_enqueue_req(struct device *jrdev, + void (*cbk)(struct device *jrdev, u32 *desc, + u32 err, void *context), + struct ahash_request *req, + int dst_len, enum dma_data_direction dir) +{ + struct caam_drv_private_jr *jrpriv = dev_get_drvdata(jrdev); + struct caam_hash_state *state = ahash_request_ctx(req); + struct ahash_edesc *edesc = state->edesc; + u32 *desc = edesc->hw_desc; + int ret; + + state->ahash_op_done = cbk; + + /* + * only the backlog request are sent to crypto-engine since the others + * can be handled by caam, if free, especially since jr has up to 1024 + * entries (more than the 10 entries from crypto-engine). + */ + if (req->base.flags & crypto_tfm_req_may_backlog) + ret = crypto_transfer_hash_request_to_engine(jrpriv->engine, + req); + else + ret = caam_jr_enqueue(jrdev, desc, cbk, req); + + if ((ret != -einprogress) && (ret != -ebusy)) { + ahash_unmap_ctx(jrdev, edesc, req, dst_len, dir); + kfree(edesc); + } + + return ret; +} + - ret = caam_jr_enqueue(jrdev, desc, ahash_done_bi, req); - if (ret != -einprogress) - goto unmap_ctx; + ret = ahash_enqueue_req(jrdev, ahash_done_bi, req, + ctx->ctx_len, dma_bidirectional); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req); - if (ret == -einprogress) - return ret; - + return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req, + digestsize, dma_bidirectional); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_src, req); - if (ret == -einprogress) - return ret; - + return ahash_enqueue_req(jrdev, ahash_done_ctx_src, req, + digestsize, dma_bidirectional); - ret = caam_jr_enqueue(jrdev, desc, ahash_done, req); - if (ret != -einprogress) { - ahash_unmap_ctx(jrdev, edesc, req, digestsize, dma_from_device); - kfree(edesc); - } - - return ret; + return ahash_enqueue_req(jrdev, ahash_done, req, digestsize, + dma_from_device); - ret = caam_jr_enqueue(jrdev, desc, ahash_done, req); - if (ret != -einprogress) { - ahash_unmap_ctx(jrdev, edesc, req, digestsize, dma_from_device); - kfree(edesc); - } - - return ret; + return ahash_enqueue_req(jrdev, ahash_done, req, + digestsize, dma_from_device); - - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req); - if (ret != -einprogress) - goto unmap_ctx; - + ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req, + ctx->ctx_len, dma_to_device); + if ((ret != -einprogress) && (ret != -ebusy)) + return ret; - ret = caam_jr_enqueue(jrdev, desc, ahash_done, req); - if (ret != -einprogress) { - ahash_unmap_ctx(jrdev, edesc, req, digestsize, dma_from_device); - kfree(edesc); - } - - return ret; + return ahash_enqueue_req(jrdev, ahash_done, req, + digestsize, dma_from_device); - ret = caam_jr_enqueue(jrdev, desc, ahash_done_ctx_dst, req); - if (ret != -einprogress) - goto unmap_ctx; - + ret = ahash_enqueue_req(jrdev, ahash_done_ctx_dst, req, + ctx->ctx_len, dma_to_device); + if ((ret != -einprogress) && (ret != -ebusy)) + return ret; + const size_t sh_desc_update_offset = offsetof(struct caam_hash_ctx, + sh_desc_update); - offsetof(struct caam_hash_ctx, key), + offsetof(struct caam_hash_ctx, key) - + sh_desc_update_offset, - sh_desc_update_first); + sh_desc_update_first) - + sh_desc_update_offset; - sh_desc_fin); + sh_desc_fin) - + sh_desc_update_offset; - sh_desc_digest); + sh_desc_digest) - + sh_desc_update_offset; + + ctx->enginectx.op.do_one_request = ahash_do_one_req; - offsetof(struct caam_hash_ctx, key), + offsetof(struct caam_hash_ctx, key) - + offsetof(struct caam_hash_ctx, sh_desc_update),
|
Cryptography hardware acceleration
|
21b014f038d384ca66bc4644cc10a1f6436787ae
|
iuliana prodan horia geant horia geanta nxp com
|
drivers
|
crypto
|
caam
|
crypto: caam - enable prediction resistance in hrwng
|
instantiate caam rng with prediction resistance enabled to improve its quality (with pr on drng is forced to reseed from trng every time random data is generated).
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
enable prediction resistance in hrwng
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['caam']
|
['h', 'kconfig', 'c']
| 5
| 68
| 15
|
--- diff --git a/drivers/crypto/caam/kconfig b/drivers/crypto/caam/kconfig --- a/drivers/crypto/caam/kconfig +++ b/drivers/crypto/caam/kconfig + imply fsl_mc_bus diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c --- a/drivers/crypto/caam/caamrng.c +++ b/drivers/crypto/caam/caamrng.c - append_operation(desc, op_alg_algsel_rng | op_type_class1_alg); + append_operation(desc, op_alg_algsel_rng | op_type_class1_alg | + op_alg_pr_on); diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c +#include <linux/fsl/mc.h> - (handle << op_alg_aai_shift) | op_alg_as_init; + (handle << op_alg_aai_shift) | op_alg_as_init | + op_alg_pr_on; + const u32 rdsta_if = rdsta_if0 << sh_idx; + const u32 rdsta_pr = rdsta_pr0 << sh_idx; + const u32 rdsta_mask = rdsta_if | rdsta_pr; - if ((1 << sh_idx) & state_handle_mask) - continue; + if (rdsta_if & state_handle_mask) { + if (rdsta_pr & state_handle_mask) + continue; + + dev_info(ctrldev, + "rng4 sh%d was previously instantiated without prediction resistance. tearing it down ", + sh_idx); + + ret = deinstantiate_rng(ctrldev, rdsta_if); + if (ret) + break; + } - rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & rdsta_ifmask; + rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & rdsta_mask; - !(rdsta_val & (1 << sh_idx))) { + (rdsta_val & rdsta_mask) != rdsta_mask) { +#ifdef config_fsl_mc_bus +static bool check_version(struct fsl_mc_version *mc_version, u32 major, + u32 minor, u32 revision) +{ + if (mc_version->major > major) + return true; + + if (mc_version->major == major) { + if (mc_version->minor > minor) + return true; + + if (mc_version->minor == minor && + mc_version->revision > revision) + return true; + } + + return false; +} +#endif + + bool pr_support = false; + np = of_find_compatible_node(null, null, "fsl,qoriq-mc"); + ctrlpriv->mc_en = !!np; + of_node_put(np); + +#ifdef config_fsl_mc_bus + if (ctrlpriv->mc_en) { + struct fsl_mc_version *mc_version; + + mc_version = fsl_mc_get_version(); + if (mc_version) + pr_support = check_version(mc_version, 10, 20, 0); + else + return -eprobe_defer; + } +#endif - np = of_find_compatible_node(null, null, "fsl,qoriq-mc"); - ctrlpriv->mc_en = !!np; - of_node_put(np); - - if (!ctrlpriv->mc_en && rng_vid >= 4) { + if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) { - ctrlpriv->rng4_sh_init &= rdsta_ifmask; + ctrlpriv->rng4_sh_init &= rdsta_mask; - rdsta_ifmask; + rdsta_mask; - ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & rdsta_ifmask; + ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & rdsta_mask; diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h --- a/drivers/crypto/caam/desc.h +++ b/drivers/crypto/caam/desc.h +#define op_alg_pr_on bit(1) + diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h --- a/drivers/crypto/caam/regs.h +++ b/drivers/crypto/caam/regs.h +#define rdsta_pr0 bit(4) +#define rdsta_pr1 bit(5) -#define rdsta_ifmask (rdsta_if1 | rdsta_if0) +#define rdsta_mask (rdsta_pr1 | rdsta_pr0 | rdsta_if1 | rdsta_if0)
|
Cryptography hardware acceleration
|
358ba762d9f1d4ba99ab31ef12bc28014b22f4c9
|
andrey smirnov
|
drivers
|
crypto
|
caam
|
crypto/chtls: add/delete tls header in driver
|
kernel tls forms tls header in kernel during encryption and removes while decryption before giving packet back to user application. the similar logic is introduced in chtls code as well.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add/delete tls header in driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['chtls']
|
['c']
| 1
| 59
| 14
|
- tls_proccess_cmsg() uses tls_handle_open_record() which is not required --- diff --git a/drivers/crypto/chelsio/chtls/chtls_io.c b/drivers/crypto/chelsio/chtls/chtls_io.c --- a/drivers/crypto/chelsio/chtls/chtls_io.c +++ b/drivers/crypto/chelsio/chtls/chtls_io.c -/* read tls header to find content type and data length */ -static int tls_header_read(struct tls_hdr *thdr, struct iov_iter *from) -{ - if (copy_from_iter(thdr, sizeof(*thdr), from) != sizeof(*thdr)) - return -efault; - return (__force int)cpu_to_be16(thdr->length); -} - +static int chtls_proccess_cmsg(struct sock *sk, struct msghdr *msg, + unsigned char *record_type) +{ + struct cmsghdr *cmsg; + int rc = -einval; + + for_each_cmsghdr(cmsg, msg) { + if (!cmsg_ok(msg, cmsg)) + return -einval; + if (cmsg->cmsg_level != sol_tls) + continue; + + switch (cmsg->cmsg_type) { + case tls_set_record_type: + if (cmsg->cmsg_len < cmsg_len(sizeof(*record_type))) + return -einval; + + if (msg->msg_flags & msg_more) + return -einval; + + *record_type = *(unsigned char *)cmsg_data(cmsg); + rc = 0; + break; + default: + return -einval; + } + } + + return rc; +} + - struct tls_hdr hdr; + unsigned char record_type = tls_record_type_data; - recordsz = tls_header_read(&hdr, &msg->msg_iter); - size -= tls_header_length; - copied += tls_header_length; + if (unlikely(msg->msg_controllen)) { + err = chtls_proccess_cmsg(sk, msg, + &record_type); + if (err) + goto out_err; + } + + recordsz = size; - csk->tlshws.type = hdr.type; + csk->tlshws.type = record_type; + - ulp_skb_cb(skb)->ulp.tls.type = hdr.type; + ulp_skb_cb(skb)->ulp.tls.type = record_type; + /* set record type if not already done. for a non-data record, + * do not proceed if record type could not be copied. + */ + if (ulp_skb_cb(skb)->flags & ulpcb_flag_tls_hdr) { + struct tls_hdr *thdr = (struct tls_hdr *)skb->data; + int cerr = 0; + + cerr = put_cmsg(msg, sol_tls, tls_get_record_type, + sizeof(thdr->type), &thdr->type); + + if (cerr && thdr->type != tls_record_type_data) + return -eio; + /* don't send tls header, skip copy */ + goto skip_copy; + } +
|
Cryptography hardware acceleration
|
6919a8264a3248dc0d7f945bb42f2c380f76b01e
|
rohit maheshwari
|
drivers
|
crypto
|
chelsio, chtls
|
crypto: marvell - add support for octeon tx cpt engine
|
add support for the cryptographic acceleration unit (cpt) on octeontx cn83xx soc.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
support for marvell octeontx cpt driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['marvell']
|
['h', 'maintainers', 'c', 'makefile']
| 9
| 2,765
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +m: srujana challa <schalla@marvell.com> diff --git a/drivers/crypto/marvell/octeontx/makefile b/drivers/crypto/marvell/octeontx/makefile --- /dev/null +++ b/drivers/crypto/marvell/octeontx/makefile +# spdx-license-identifier: gpl-2.0 +obj-$(config_crypto_dev_octeontx_cpt) += octeontx-cpt.o + +octeontx-cpt-objs := otx_cptpf_main.o otx_cptpf_mbox.o otx_cptpf_ucode.o diff --git a/drivers/crypto/marvell/octeontx/otx_cpt_common.h b/drivers/crypto/marvell/octeontx/otx_cpt_common.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cpt_common.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cpt_common_h +#define __otx_cpt_common_h + +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/device.h> + +#define otx_cpt_max_mbox_data_str_size 64 + +enum otx_cptpf_type { + otx_cpt_ae = 2, + otx_cpt_se = 3, + bad_otx_cptpf_type, +}; + +enum otx_cptvf_type { + otx_cpt_ae_types = 1, + otx_cpt_se_types = 2, + bad_otx_cptvf_type, +}; + +/* vf-pf message opcodes */ +enum otx_cpt_mbox_opcode { + otx_cpt_msg_vf_up = 1, + otx_cpt_msg_vf_down, + otx_cpt_msg_ready, + otx_cpt_msg_qlen, + otx_cpt_msg_qbind_grp, + otx_cpt_msg_vq_priority, + otx_cpt_msg_pf_type, + otx_cpt_msg_ack, + otx_cpt_msg_nack +}; + +/* octeontx cpt mailbox structure */ +struct otx_cpt_mbox { + u64 msg; /* message type mbox[0] */ + u64 data;/* data mbox[1] */ +}; + +#endif /* __otx_cpt_common_h */ diff --git a/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h b/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cpt_hw_types_h +#define __otx_cpt_hw_types_h + +#include <linux/types.h> + +/* device ids */ +#define otx_cpt_pci_pf_device_id 0xa040 + +#define otx_cpt_pci_pf_subsys_id 0xa340 + +/* configuration and status registers are in bar0 on octeontx platform */ +#define otx_cpt_pf_pci_cfg_bar 0 +/* mailbox interrupts offset */ +#define otx_cpt_pf_mbox_int 3 +#define otx_cpt_pf_int_vec_e_mboxx(x, a) ((x) + (a)) +/* number of msix supported in pf */ +#define otx_cpt_pf_msix_vectors 4 +/* maximum supported microcode groups */ +#define otx_cpt_max_engine_groups 8 + +/* octeontx cpt pf registers */ +#define otx_cpt_pf_constants (0x0ll) +#define otx_cpt_pf_reset (0x100ll) +#define otx_cpt_pf_diag (0x120ll) +#define otx_cpt_pf_bist_status (0x160ll) +#define otx_cpt_pf_ecc0_ctl (0x200ll) +#define otx_cpt_pf_ecc0_flip (0x210ll) +#define otx_cpt_pf_ecc0_int (0x220ll) +#define otx_cpt_pf_ecc0_int_w1s (0x230ll) +#define otx_cpt_pf_ecc0_ena_w1s (0x240ll) +#define otx_cpt_pf_ecc0_ena_w1c (0x250ll) +#define otx_cpt_pf_mbox_intx(b) (0x400ll | (u64)(b) << 3) +#define otx_cpt_pf_mbox_int_w1sx(b) (0x420ll | (u64)(b) << 3) +#define otx_cpt_pf_mbox_ena_w1cx(b) (0x440ll | (u64)(b) << 3) +#define otx_cpt_pf_mbox_ena_w1sx(b) (0x460ll | (u64)(b) << 3) +#define otx_cpt_pf_exec_int (0x500ll) +#define otx_cpt_pf_exec_int_w1s (0x520ll) +#define otx_cpt_pf_exec_ena_w1c (0x540ll) +#define otx_cpt_pf_exec_ena_w1s (0x560ll) +#define otx_cpt_pf_gx_en(b) (0x600ll | (u64)(b) << 3) +#define otx_cpt_pf_exec_info (0x700ll) +#define otx_cpt_pf_exec_busy (0x800ll) +#define otx_cpt_pf_exec_info0 (0x900ll) +#define otx_cpt_pf_exec_info1 (0x910ll) +#define otx_cpt_pf_inst_req_pc (0x10000ll) +#define otx_cpt_pf_inst_latency_pc (0x10020ll) +#define otx_cpt_pf_rd_req_pc (0x10040ll) +#define otx_cpt_pf_rd_latency_pc (0x10060ll) +#define otx_cpt_pf_rd_uc_pc (0x10080ll) +#define otx_cpt_pf_active_cycles_pc (0x10100ll) +#define otx_cpt_pf_exe_ctl (0x4000000ll) +#define otx_cpt_pf_exe_status (0x4000008ll) +#define otx_cpt_pf_exe_clk (0x4000010ll) +#define otx_cpt_pf_exe_dbg_ctl (0x4000018ll) +#define otx_cpt_pf_exe_dbg_data (0x4000020ll) +#define otx_cpt_pf_exe_bist_status (0x4000028ll) +#define otx_cpt_pf_exe_req_timer (0x4000030ll) +#define otx_cpt_pf_exe_mem_ctl (0x4000038ll) +#define otx_cpt_pf_exe_perf_ctl (0x4001000ll) +#define otx_cpt_pf_exe_dbg_cntx(b) (0x4001100ll | (u64)(b) << 3) +#define otx_cpt_pf_exe_perf_event_cnt (0x4001180ll) +#define otx_cpt_pf_exe_epci_inbx_cnt(b) (0x4001200ll | (u64)(b) << 3) +#define otx_cpt_pf_exe_epci_outbx_cnt(b) (0x4001240ll | (u64)(b) << 3) +#define otx_cpt_pf_engx_ucode_base(b) (0x4002000ll | (u64)(b) << 3) +#define otx_cpt_pf_qx_ctl(b) (0x8000000ll | (u64)(b) << 20) +#define otx_cpt_pf_qx_gmctl(b) (0x8000020ll | (u64)(b) << 20) +#define otx_cpt_pf_qx_ctl2(b) (0x8000100ll | (u64)(b) << 20) +#define otx_cpt_pf_vfx_mboxx(b, c) (0x8001000ll | (u64)(b) << 20 | \ + (u64)(c) << 8) + +/* + * register (ncb) otx_cpt#_pf_bist_status + * + * cpt pf control bist status register + * this register has the bist status of memories. each bit is the bist result + * of an individual memory (per bit, 0 = pass and 1 = fail). + * otx_cptx_pf_bist_status_s + * word0 + * bstatus [29:0](ro/h) bist status. one bit per memory, enumerated by + * cpt_rams_e. + */ +union otx_cptx_pf_bist_status { + u64 u; + struct otx_cptx_pf_bist_status_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_30_63:34; + u64 bstatus:30; +#else /* word 0 - little endian */ + u64 bstatus:30; + u64 reserved_30_63:34; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_pf_constants + * + * cpt pf constants register + * this register contains implementation-related parameters of cpt in cnxxxx. + * otx_cptx_pf_constants_s + * word 0 + * reserved_40_63:24 [63:40] reserved. + * epcis:8 [39:32](ro) number of epci busses. + * grps:8 [31:24](ro) number of engine groups implemented. + * ae:8 [23:16](ro/h) number of aes. in cnxxxx, for cpt0 returns 0x0, + * for cpt1 returns 0x18, or less if there are fuse-disables. + * se:8 [15:8](ro/h) number of ses. in cnxxxx, for cpt0 returns 0x30, + * or less if there are fuse-disables, for cpt1 returns 0x0. + * vq:8 [7:0](ro) number of vqs. + */ +union otx_cptx_pf_constants { + u64 u; + struct otx_cptx_pf_constants_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_40_63:24; + u64 epcis:8; + u64 grps:8; + u64 ae:8; + u64 se:8; + u64 vq:8; +#else /* word 0 - little endian */ + u64 vq:8; + u64 se:8; + u64 ae:8; + u64 grps:8; + u64 epcis:8; + u64 reserved_40_63:24; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_pf_exe_bist_status + * + * cpt pf engine bist status register + * this register has the bist status of each engine. each bit is the + * bist result of an individual engine (per bit, 0 = pass and 1 = fail). + * otx_cptx_pf_exe_bist_status_s + * word0 + * reserved_48_63:16 [63:48] reserved + * bstatus:48 [47:0](ro/h) bist status. one bit per engine. + * + */ +union otx_cptx_pf_exe_bist_status { + u64 u; + struct otx_cptx_pf_exe_bist_status_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_48_63:16; + u64 bstatus:48; +#else /* word 0 - little endian */ + u64 bstatus:48; + u64 reserved_48_63:16; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_pf_q#_ctl + * + * cpt queue control register + * this register configures queues. this register should be changed only + * when quiescent (see cpt()_vq()_inprog[inflight]). + * otx_cptx_pf_qx_ctl_s + * word0 + * reserved_60_63:4 [63:60] reserved. + * aura:12; [59:48](r/w) guest-aura for returning this queue's + * instruction-chunk buffers to fpa. only used when [inst_free] is set. + * for the fpa to not discard the request, fpa_pf_map() must map + * [aura] and cpt()_pf_q()_gmctl[gmid] as valid. + * reserved_45_47:3 [47:45] reserved. + * size:13 [44:32](r/w) command-buffer size, in number of 64-bit words per + * command buffer segment. must be 8*n + 1, where n is the number of + * instructions per buffer segment. + * reserved_11_31:21 [31:11] reserved. + * cont_err:1 [10:10](r/w) continue on error. + * 0 = when cpt()_vq()_misc_int[nwrp], cpt()_vq()_misc_int[irde] or + * cpt()_vq()_misc_int[dovf] are set by hardware or software via + * cpt()_vq()_misc_int_w1s, then cpt()_vq()_ctl[ena] is cleared. due to + * pipelining, additional instructions may have been processed between the + * instruction causing the error and the next instruction in the disabled + * queue (the instruction at cpt()_vq()_saddr). + * 1 = ignore errors and continue processing instructions. + * for diagnostic use only. + * inst_free:1 [9:9](r/w) instruction fpa free. when set, when cpt reaches the + * end of an instruction chunk, that chunk will be freed to the fpa. + * inst_be:1 [8:8](r/w) instruction big-endian control. when set, instructions, + * instruction next chunk pointers, and result structures are stored in + * big-endian format in memory. + * iqb_ldwb:1 [7:7](r/w) instruction load don't write back. + * 0 = the hardware issues ncb transient load (ldt) towards the cache, + * which if the line hits and is is dirty will cause the line to be + * written back before being replaced. + * 1 = the hardware issues ncb ldwb read-and-invalidate command towards + * the cache when fetching the last word of instructions; as a result the + * line will not be written back when replaced. this improves + * performance, but software must not read the instructions after they are + * posted to the hardware. reads that do not consume the last word of a + * cache line always use ldi. + * reserved_4_6:3 [6:4] reserved. + * grp:3; [3:1](r/w) engine group. + * pri:1; [0:0](r/w) queue priority. + * 1 = this queue has higher priority. round-robin between higher + * priority queues. + * 0 = this queue has lower priority. round-robin between lower + * priority queues. + */ +union otx_cptx_pf_qx_ctl { + u64 u; + struct otx_cptx_pf_qx_ctl_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_60_63:4; + u64 aura:12; + u64 reserved_45_47:3; + u64 size:13; + u64 reserved_11_31:21; + u64 cont_err:1; + u64 inst_free:1; + u64 inst_be:1; + u64 iqb_ldwb:1; + u64 reserved_4_6:3; + u64 grp:3; + u64 pri:1; +#else /* word 0 - little endian */ + u64 pri:1; + u64 grp:3; + u64 reserved_4_6:3; + u64 iqb_ldwb:1; + u64 inst_be:1; + u64 inst_free:1; + u64 cont_err:1; + u64 reserved_11_31:21; + u64 size:13; + u64 reserved_45_47:3; + u64 aura:12; + u64 reserved_60_63:4; +#endif /* word 0 - end */ + } s; +}; +#endif /* __otx_cpt_hw_types_h */ diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf.h b/drivers/crypto/marvell/octeontx/otx_cptpf.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptpf.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cptpf_h +#define __otx_cptpf_h + +#include <linux/types.h> +#include <linux/device.h> +#include "otx_cptpf_ucode.h" + +/* + * octeontx cpt device structure + */ +struct otx_cpt_device { + void __iomem *reg_base; /* register start address */ + struct pci_dev *pdev; /* pci device handle */ + struct otx_cpt_eng_grps eng_grps;/* engine groups information */ + struct list_head list; + u8 pf_type; /* pf type se or ae */ + u8 max_vfs; /* maximum number of vfs supported by the cpt */ + u8 vfs_enabled; /* number of enabled vfs */ +}; + +void otx_cpt_mbox_intr_handler(struct otx_cpt_device *cpt, int mbx); +void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt); + +#endif /* __otx_cptpf_h */ diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf_main.c b/drivers/crypto/marvell/octeontx/otx_cptpf_main.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptpf_main.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include "otx_cpt_common.h" +#include "otx_cptpf.h" + +#define drv_name "octeontx-cpt" +#define drv_version "1.0" + +static void otx_cpt_disable_mbox_interrupts(struct otx_cpt_device *cpt) +{ + /* disable mbox(0) interrupts for all vfs */ + writeq(~0ull, cpt->reg_base + otx_cpt_pf_mbox_ena_w1cx(0)); +} + +static void otx_cpt_enable_mbox_interrupts(struct otx_cpt_device *cpt) +{ + /* enable mbox(0) interrupts for all vfs */ + writeq(~0ull, cpt->reg_base + otx_cpt_pf_mbox_ena_w1sx(0)); +} + +static irqreturn_t otx_cpt_mbx0_intr_handler(int __always_unused irq, + void *cpt) +{ + otx_cpt_mbox_intr_handler(cpt, 0); + + return irq_handled; +} + +static void otx_cpt_reset(struct otx_cpt_device *cpt) +{ + writeq(1, cpt->reg_base + otx_cpt_pf_reset); +} + +static void otx_cpt_find_max_enabled_cores(struct otx_cpt_device *cpt) +{ + union otx_cptx_pf_constants pf_cnsts = {0}; + + pf_cnsts.u = readq(cpt->reg_base + otx_cpt_pf_constants); + cpt->eng_grps.avail.max_se_cnt = pf_cnsts.s.se; + cpt->eng_grps.avail.max_ae_cnt = pf_cnsts.s.ae; +} + +static u32 otx_cpt_check_bist_status(struct otx_cpt_device *cpt) +{ + union otx_cptx_pf_bist_status bist_sts = {0}; + + bist_sts.u = readq(cpt->reg_base + otx_cpt_pf_bist_status); + return bist_sts.u; +} + +static u64 otx_cpt_check_exe_bist_status(struct otx_cpt_device *cpt) +{ + union otx_cptx_pf_exe_bist_status bist_sts = {0}; + + bist_sts.u = readq(cpt->reg_base + otx_cpt_pf_exe_bist_status); + return bist_sts.u; +} + +static int otx_cpt_device_init(struct otx_cpt_device *cpt) +{ + struct device *dev = &cpt->pdev->dev; + u16 sdevid; + u64 bist; + + /* reset the pf when probed first */ + otx_cpt_reset(cpt); + mdelay(100); + + pci_read_config_word(cpt->pdev, pci_subsystem_id, &sdevid); + + /* check bist status */ + bist = (u64)otx_cpt_check_bist_status(cpt); + if (bist) { + dev_err(dev, "ram bist failed with code 0x%llx", bist); + return -enodev; + } + + bist = otx_cpt_check_exe_bist_status(cpt); + if (bist) { + dev_err(dev, "engine bist failed with code 0x%llx", bist); + return -enodev; + } + + /* get max enabled cores */ + otx_cpt_find_max_enabled_cores(cpt); + + if ((sdevid == otx_cpt_pci_pf_subsys_id) && + (cpt->eng_grps.avail.max_se_cnt == 0)) { + cpt->pf_type = otx_cpt_ae; + } else if ((sdevid == otx_cpt_pci_pf_subsys_id) && + (cpt->eng_grps.avail.max_ae_cnt == 0)) { + cpt->pf_type = otx_cpt_se; + } + + /* get max vqs/vfs supported by the device */ + cpt->max_vfs = pci_sriov_get_totalvfs(cpt->pdev); + + /* disable all cores */ + otx_cpt_disable_all_cores(cpt); + + return 0; +} + +static int otx_cpt_register_interrupts(struct otx_cpt_device *cpt) +{ + struct device *dev = &cpt->pdev->dev; + u32 mbox_int_idx = otx_cpt_pf_mbox_int; + u32 num_vec = otx_cpt_pf_msix_vectors; + int ret; + + /* enable msi-x */ + ret = pci_alloc_irq_vectors(cpt->pdev, num_vec, num_vec, pci_irq_msix); + if (ret < 0) { + dev_err(&cpt->pdev->dev, + "request for #%d msix vectors failed ", + num_vec); + return ret; + } + + /* register mailbox interrupt handlers */ + ret = request_irq(pci_irq_vector(cpt->pdev, + otx_cpt_pf_int_vec_e_mboxx(mbox_int_idx, 0)), + otx_cpt_mbx0_intr_handler, 0, "cpt mbox0", cpt); + if (ret) { + dev_err(dev, "request irq failed "); + pci_free_irq_vectors(cpt->pdev); + return ret; + } + /* enable mailbox interrupt */ + otx_cpt_enable_mbox_interrupts(cpt); + return 0; +} + +static void otx_cpt_unregister_interrupts(struct otx_cpt_device *cpt) +{ + u32 mbox_int_idx = otx_cpt_pf_mbox_int; + + otx_cpt_disable_mbox_interrupts(cpt); + free_irq(pci_irq_vector(cpt->pdev, + otx_cpt_pf_int_vec_e_mboxx(mbox_int_idx, 0)), + cpt); + pci_free_irq_vectors(cpt->pdev); +} + + +static int otx_cpt_sriov_configure(struct pci_dev *pdev, int numvfs) +{ + struct otx_cpt_device *cpt = pci_get_drvdata(pdev); + int ret = 0; + + if (numvfs > cpt->max_vfs) + numvfs = cpt->max_vfs; + + if (numvfs > 0) { + ret = otx_cpt_try_create_default_eng_grps(cpt->pdev, + &cpt->eng_grps, + cpt->pf_type); + if (ret) + return ret; + + cpt->vfs_enabled = numvfs; + ret = pci_enable_sriov(pdev, numvfs); + if (ret) { + cpt->vfs_enabled = 0; + return ret; + } + otx_cpt_set_eng_grps_is_rdonly(&cpt->eng_grps, true); + try_module_get(this_module); + ret = numvfs; + } else { + pci_disable_sriov(pdev); + otx_cpt_set_eng_grps_is_rdonly(&cpt->eng_grps, false); + module_put(this_module); + cpt->vfs_enabled = 0; + } + dev_notice(&cpt->pdev->dev, "vfs enabled: %d ", ret); + + return ret; +} + +static int otx_cpt_probe(struct pci_dev *pdev, + const struct pci_device_id __always_unused *ent) +{ + struct device *dev = &pdev->dev; + struct otx_cpt_device *cpt; + int err; + + cpt = devm_kzalloc(dev, sizeof(*cpt), gfp_kernel); + if (!cpt) + return -enomem; + + pci_set_drvdata(pdev, cpt); + cpt->pdev = pdev; + + err = pci_enable_device(pdev); + if (err) { + dev_err(dev, "failed to enable pci device "); + goto err_clear_drvdata; + } + + err = pci_request_regions(pdev, drv_name); + if (err) { + dev_err(dev, "pci request regions failed 0x%x ", err); + goto err_disable_device; + } + + err = pci_set_dma_mask(pdev, dma_bit_mask(48)); + if (err) { + dev_err(dev, "unable to get usable dma configuration "); + goto err_release_regions; + } + + err = pci_set_consistent_dma_mask(pdev, dma_bit_mask(48)); + if (err) { + dev_err(dev, "unable to get 48-bit dma for consistent allocations "); + goto err_release_regions; + } + + /* map pf's configuration registers */ + cpt->reg_base = pci_iomap(pdev, otx_cpt_pf_pci_cfg_bar, 0); + if (!cpt->reg_base) { + dev_err(dev, "cannot map config register space, aborting "); + err = -enomem; + goto err_release_regions; + } + + /* cpt device hw initialization */ + err = otx_cpt_device_init(cpt); + if (err) + goto err_unmap_region; + + /* register interrupts */ + err = otx_cpt_register_interrupts(cpt); + if (err) + goto err_unmap_region; + + /* initialize engine groups */ + err = otx_cpt_init_eng_grps(pdev, &cpt->eng_grps, cpt->pf_type); + if (err) + goto err_unregister_interrupts; + + return 0; + +err_unregister_interrupts: + otx_cpt_unregister_interrupts(cpt); +err_unmap_region: + pci_iounmap(pdev, cpt->reg_base); +err_release_regions: + pci_release_regions(pdev); +err_disable_device: + pci_disable_device(pdev); +err_clear_drvdata: + pci_set_drvdata(pdev, null); + + return err; +} + +static void otx_cpt_remove(struct pci_dev *pdev) +{ + struct otx_cpt_device *cpt = pci_get_drvdata(pdev); + + if (!cpt) + return; + + /* disable vfs */ + pci_disable_sriov(pdev); + /* cleanup engine groups */ + otx_cpt_cleanup_eng_grps(pdev, &cpt->eng_grps); + /* disable cpt pf interrupts */ + otx_cpt_unregister_interrupts(cpt); + /* disengage se and ae cores from all groups */ + otx_cpt_disable_all_cores(cpt); + pci_iounmap(pdev, cpt->reg_base); + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, null); +} + +/* supported devices */ +static const struct pci_device_id otx_cpt_id_table[] = { + { pci_device(pci_vendor_id_cavium, otx_cpt_pci_pf_device_id) }, + { 0, } /* end of table */ +}; + +static struct pci_driver otx_cpt_pci_driver = { + .name = drv_name, + .id_table = otx_cpt_id_table, + .probe = otx_cpt_probe, + .remove = otx_cpt_remove, + .sriov_configure = otx_cpt_sriov_configure +}; + +module_pci_driver(otx_cpt_pci_driver); + +module_author("marvell international ltd."); +module_description("marvell octeontx cpt physical function driver"); +module_license("gpl v2"); +module_version(drv_version); +module_device_table(pci, otx_cpt_id_table); diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c b/drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptpf_mbox.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include "otx_cpt_common.h" +#include "otx_cptpf.h" + +static char *get_mbox_opcode_str(int msg_opcode) +{ + char *str = "unknown"; + + switch (msg_opcode) { + case otx_cpt_msg_vf_up: + str = "up"; + break; + + case otx_cpt_msg_vf_down: + str = "down"; + break; + + case otx_cpt_msg_ready: + str = "ready"; + break; + + case otx_cpt_msg_qlen: + str = "qlen"; + break; + + case otx_cpt_msg_qbind_grp: + str = "qbind_grp"; + break; + + case otx_cpt_msg_vq_priority: + str = "vq_priority"; + break; + + case otx_cpt_msg_pf_type: + str = "pf_type"; + break; + + case otx_cpt_msg_ack: + str = "ack"; + break; + + case otx_cpt_msg_nack: + str = "nack"; + break; + } + + return str; +} + +static void dump_mbox_msg(struct otx_cpt_mbox *mbox_msg, int vf_id) +{ + char raw_data_str[otx_cpt_max_mbox_data_str_size]; + + hex_dump_to_buffer(mbox_msg, sizeof(struct otx_cpt_mbox), 16, 8, + raw_data_str, otx_cpt_max_mbox_data_str_size, false); + if (vf_id >= 0) + pr_debug("mbox opcode %s received from vf%d raw_data %s", + get_mbox_opcode_str(mbox_msg->msg), vf_id, + raw_data_str); + else + pr_debug("mbox opcode %s received from pf raw_data %s", + get_mbox_opcode_str(mbox_msg->msg), raw_data_str); +} + +static void otx_cpt_send_msg_to_vf(struct otx_cpt_device *cpt, int vf, + struct otx_cpt_mbox *mbx) +{ + /* writing mbox(0) causes interrupt */ + writeq(mbx->data, cpt->reg_base + otx_cpt_pf_vfx_mboxx(vf, 1)); + writeq(mbx->msg, cpt->reg_base + otx_cpt_pf_vfx_mboxx(vf, 0)); +} + +/* + * acks vf's mailbox message + * @vf: vf to which ack to be sent + */ +static void otx_cpt_mbox_send_ack(struct otx_cpt_device *cpt, int vf, + struct otx_cpt_mbox *mbx) +{ + mbx->data = 0ull; + mbx->msg = otx_cpt_msg_ack; + otx_cpt_send_msg_to_vf(cpt, vf, mbx); +} + +/* nacks vf's mailbox message that pf is not able to complete the action */ +static void otx_cptpf_mbox_send_nack(struct otx_cpt_device *cpt, int vf, + struct otx_cpt_mbox *mbx) +{ + mbx->data = 0ull; + mbx->msg = otx_cpt_msg_nack; + otx_cpt_send_msg_to_vf(cpt, vf, mbx); +} + +static void otx_cpt_clear_mbox_intr(struct otx_cpt_device *cpt, u32 vf) +{ + /* w1c for the vf */ + writeq(1ull << vf, cpt->reg_base + otx_cpt_pf_mbox_intx(0)); +} + +/* + * configure qlen/chunk sizes for vf + */ +static void otx_cpt_cfg_qlen_for_vf(struct otx_cpt_device *cpt, int vf, + u32 size) +{ + union otx_cptx_pf_qx_ctl pf_qx_ctl; + + pf_qx_ctl.u = readq(cpt->reg_base + otx_cpt_pf_qx_ctl(vf)); + pf_qx_ctl.s.size = size; + pf_qx_ctl.s.cont_err = true; + writeq(pf_qx_ctl.u, cpt->reg_base + otx_cpt_pf_qx_ctl(vf)); +} + +/* + * configure vq priority + */ +static void otx_cpt_cfg_vq_priority(struct otx_cpt_device *cpt, int vf, u32 pri) +{ + union otx_cptx_pf_qx_ctl pf_qx_ctl; + + pf_qx_ctl.u = readq(cpt->reg_base + otx_cpt_pf_qx_ctl(vf)); + pf_qx_ctl.s.pri = pri; + writeq(pf_qx_ctl.u, cpt->reg_base + otx_cpt_pf_qx_ctl(vf)); +} + +static int otx_cpt_bind_vq_to_grp(struct otx_cpt_device *cpt, u8 q, u8 grp) +{ + struct device *dev = &cpt->pdev->dev; + struct otx_cpt_eng_grp_info *eng_grp; + union otx_cptx_pf_qx_ctl pf_qx_ctl; + struct otx_cpt_ucode *ucode; + + if (q >= cpt->max_vfs) { + dev_err(dev, "requested queue %d is > than maximum avail %d", + q, cpt->max_vfs); + return -einval; + } + + if (grp >= otx_cpt_max_engine_groups) { + dev_err(dev, "requested group %d is > than maximum avail %d", + grp, otx_cpt_max_engine_groups); + return -einval; + } + + eng_grp = &cpt->eng_grps.grp[grp]; + if (!eng_grp->is_enabled) { + dev_err(dev, "requested engine group %d is disabled", grp); + return -einval; + } + + pf_qx_ctl.u = readq(cpt->reg_base + otx_cpt_pf_qx_ctl(q)); + pf_qx_ctl.s.grp = grp; + writeq(pf_qx_ctl.u, cpt->reg_base + otx_cpt_pf_qx_ctl(q)); + + if (eng_grp->mirror.is_ena) + ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; + else + ucode = &eng_grp->ucode[0]; + + if (otx_cpt_uc_supports_eng_type(ucode, otx_cpt_se_types)) + return otx_cpt_se_types; + else if (otx_cpt_uc_supports_eng_type(ucode, otx_cpt_ae_types)) + return otx_cpt_ae_types; + else + return bad_otx_cptvf_type; +} + +/* interrupt handler to handle mailbox messages from vfs */ +static void otx_cpt_handle_mbox_intr(struct otx_cpt_device *cpt, int vf) +{ + int vftype = 0; + struct otx_cpt_mbox mbx = {}; + struct device *dev = &cpt->pdev->dev; + /* + * mbox[0] contains msg + * mbox[1] contains data + */ + mbx.msg = readq(cpt->reg_base + otx_cpt_pf_vfx_mboxx(vf, 0)); + mbx.data = readq(cpt->reg_base + otx_cpt_pf_vfx_mboxx(vf, 1)); + + dump_mbox_msg(&mbx, vf); + + switch (mbx.msg) { + case otx_cpt_msg_vf_up: + mbx.msg = otx_cpt_msg_vf_up; + mbx.data = cpt->vfs_enabled; + otx_cpt_send_msg_to_vf(cpt, vf, &mbx); + break; + case otx_cpt_msg_ready: + mbx.msg = otx_cpt_msg_ready; + mbx.data = vf; + otx_cpt_send_msg_to_vf(cpt, vf, &mbx); + break; + case otx_cpt_msg_vf_down: + /* first msg in vf teardown sequence */ + otx_cpt_mbox_send_ack(cpt, vf, &mbx); + break; + case otx_cpt_msg_qlen: + otx_cpt_cfg_qlen_for_vf(cpt, vf, mbx.data); + otx_cpt_mbox_send_ack(cpt, vf, &mbx); + break; + case otx_cpt_msg_qbind_grp: + vftype = otx_cpt_bind_vq_to_grp(cpt, vf, (u8)mbx.data); + if ((vftype != otx_cpt_ae_types) && + (vftype != otx_cpt_se_types)) { + dev_err(dev, "vf%d binding to eng group %llu failed", + vf, mbx.data); + otx_cptpf_mbox_send_nack(cpt, vf, &mbx); + } else { + mbx.msg = otx_cpt_msg_qbind_grp; + mbx.data = vftype; + otx_cpt_send_msg_to_vf(cpt, vf, &mbx); + } + break; + case otx_cpt_msg_pf_type: + mbx.msg = otx_cpt_msg_pf_type; + mbx.data = cpt->pf_type; + otx_cpt_send_msg_to_vf(cpt, vf, &mbx); + break; + case otx_cpt_msg_vq_priority: + otx_cpt_cfg_vq_priority(cpt, vf, mbx.data); + otx_cpt_mbox_send_ack(cpt, vf, &mbx); + break; + default: + dev_err(&cpt->pdev->dev, "invalid msg from vf%d, msg 0x%llx ", + vf, mbx.msg); + break; + } +} + +void otx_cpt_mbox_intr_handler (struct otx_cpt_device *cpt, int mbx) +{ + u64 intr; + u8 vf; + + intr = readq(cpt->reg_base + otx_cpt_pf_mbox_intx(0)); + pr_debug("pf interrupt mbox%d mask 0x%llx ", mbx, intr); + for (vf = 0; vf < cpt->max_vfs; vf++) { + if (intr & (1ull << vf)) { + otx_cpt_handle_mbox_intr(cpt, vf); + otx_cpt_clear_mbox_intr(cpt, vf); + } + } +} diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include <linux/ctype.h> +#include <linux/firmware.h> +#include "otx_cpt_common.h" +#include "otx_cptpf_ucode.h" +#include "otx_cptpf.h" + +#define csr_delay 30 +/* tar archive defines */ +#define tar_magic "ustar" +#define tar_magic_len 6 +#define tar_block_len 512 +#define regtype '0' +#define aregtype '' + +/* tar header as defined in posix 1003.1-1990. */ +struct tar_hdr_t { + char name[100]; + char mode[8]; + char uid[8]; + char gid[8]; + char size[12]; + char mtime[12]; + char chksum[8]; + char typeflag; + char linkname[100]; + char magic[6]; + char version[2]; + char uname[32]; + char gname[32]; + char devmajor[8]; + char devminor[8]; + char prefix[155]; +}; + +struct tar_blk_t { + union { + struct tar_hdr_t hdr; + char block[tar_block_len]; + }; +}; + +struct tar_arch_info_t { + struct list_head ucodes; + const struct firmware *fw; +}; + +static struct otx_cpt_bitmap get_cores_bmap(struct device *dev, + struct otx_cpt_eng_grp_info *eng_grp) +{ + struct otx_cpt_bitmap bmap = { {0} }; + bool found = false; + int i; + + if (eng_grp->g->engs_num > otx_cpt_max_engines) { + dev_err(dev, "unsupported number of engines %d on octeontx", + eng_grp->g->engs_num); + return bmap; + } + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + if (eng_grp->engs[i].type) { + bitmap_or(bmap.bits, bmap.bits, + eng_grp->engs[i].bmap, + eng_grp->g->engs_num); + bmap.size = eng_grp->g->engs_num; + found = true; + } + } + + if (!found) + dev_err(dev, "no engines reserved for engine group %d", + eng_grp->idx); + return bmap; +} + +static int is_eng_type(int val, int eng_type) +{ + return val & (1 << eng_type); +} + +static int dev_supports_eng_type(struct otx_cpt_eng_grps *eng_grps, + int eng_type) +{ + return is_eng_type(eng_grps->eng_types_supported, eng_type); +} + +static void set_ucode_filename(struct otx_cpt_ucode *ucode, + const char *filename) +{ + strlcpy(ucode->filename, filename, otx_cpt_ucode_name_length); +} + +static char *get_eng_type_str(int eng_type) +{ + char *str = "unknown"; + + switch (eng_type) { + case otx_cpt_se_types: + str = "se"; + break; + + case otx_cpt_ae_types: + str = "ae"; + break; + } + return str; +} + +static char *get_ucode_type_str(int ucode_type) +{ + char *str = "unknown"; + + switch (ucode_type) { + case (1 << otx_cpt_se_types): + str = "se"; + break; + + case (1 << otx_cpt_ae_types): + str = "ae"; + break; + } + return str; +} + +static int get_ucode_type(struct otx_cpt_ucode_hdr *ucode_hdr, int *ucode_type) +{ + char tmp_ver_str[otx_cpt_ucode_ver_str_sz]; + u32 i, val = 0; + u8 nn; + + strlcpy(tmp_ver_str, ucode_hdr->ver_str, otx_cpt_ucode_ver_str_sz); + for (i = 0; i < strlen(tmp_ver_str); i++) + tmp_ver_str[i] = tolower(tmp_ver_str[i]); + + nn = ucode_hdr->ver_num.nn; + if (strnstr(tmp_ver_str, "se-", otx_cpt_ucode_ver_str_sz) && + (nn == otx_cpt_se_uc_type1 || nn == otx_cpt_se_uc_type2 || + nn == otx_cpt_se_uc_type3)) + val |= 1 << otx_cpt_se_types; + if (strnstr(tmp_ver_str, "ae", otx_cpt_ucode_ver_str_sz) && + nn == otx_cpt_ae_uc_type) + val |= 1 << otx_cpt_ae_types; + + *ucode_type = val; + + if (!val) + return -einval; + if (is_eng_type(val, otx_cpt_ae_types) && + is_eng_type(val, otx_cpt_se_types)) + return -einval; + return 0; +} + +static int is_mem_zero(const char *ptr, int size) +{ + int i; + + for (i = 0; i < size; i++) { + if (ptr[i]) + return 0; + } + return 1; +} + +static int cpt_set_ucode_base(struct otx_cpt_eng_grp_info *eng_grp, void *obj) +{ + struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; + dma_addr_t dma_addr; + struct otx_cpt_bitmap bmap; + int i; + + bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); + if (!bmap.size) + return -einval; + + if (eng_grp->mirror.is_ena) + dma_addr = + eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].align_dma; + else + dma_addr = eng_grp->ucode[0].align_dma; + + /* + * set ucode_base only for the cores which are not used, + * other cores should have already valid ucode_base set + */ + for_each_set_bit(i, bmap.bits, bmap.size) + if (!eng_grp->g->eng_ref_cnt[i]) + writeq((u64) dma_addr, cpt->reg_base + + otx_cpt_pf_engx_ucode_base(i)); + return 0; +} + +static int cpt_detach_and_disable_cores(struct otx_cpt_eng_grp_info *eng_grp, + void *obj) +{ + struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; + struct otx_cpt_bitmap bmap = { {0} }; + int timeout = 10; + int i, busy; + u64 reg; + + bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); + if (!bmap.size) + return -einval; + + /* detach the cores from group */ + reg = readq(cpt->reg_base + otx_cpt_pf_gx_en(eng_grp->idx)); + for_each_set_bit(i, bmap.bits, bmap.size) { + if (reg & (1ull << i)) { + eng_grp->g->eng_ref_cnt[i]--; + reg &= ~(1ull << i); + } + } + writeq(reg, cpt->reg_base + otx_cpt_pf_gx_en(eng_grp->idx)); + + /* wait for cores to become idle */ + do { + busy = 0; + usleep_range(10000, 20000); + if (timeout-- < 0) + return -ebusy; + + reg = readq(cpt->reg_base + otx_cpt_pf_exec_busy); + for_each_set_bit(i, bmap.bits, bmap.size) + if (reg & (1ull << i)) { + busy = 1; + break; + } + } while (busy); + + /* disable the cores only if they are not used anymore */ + reg = readq(cpt->reg_base + otx_cpt_pf_exe_ctl); + for_each_set_bit(i, bmap.bits, bmap.size) + if (!eng_grp->g->eng_ref_cnt[i]) + reg &= ~(1ull << i); + writeq(reg, cpt->reg_base + otx_cpt_pf_exe_ctl); + + return 0; +} + +static int cpt_attach_and_enable_cores(struct otx_cpt_eng_grp_info *eng_grp, + void *obj) +{ + struct otx_cpt_device *cpt = (struct otx_cpt_device *) obj; + struct otx_cpt_bitmap bmap; + u64 reg; + int i; + + bmap = get_cores_bmap(&cpt->pdev->dev, eng_grp); + if (!bmap.size) + return -einval; + + /* attach the cores to the group */ + reg = readq(cpt->reg_base + otx_cpt_pf_gx_en(eng_grp->idx)); + for_each_set_bit(i, bmap.bits, bmap.size) { + if (!(reg & (1ull << i))) { + eng_grp->g->eng_ref_cnt[i]++; + reg |= 1ull << i; + } + } + writeq(reg, cpt->reg_base + otx_cpt_pf_gx_en(eng_grp->idx)); + + /* enable the cores */ + reg = readq(cpt->reg_base + otx_cpt_pf_exe_ctl); + for_each_set_bit(i, bmap.bits, bmap.size) + reg |= 1ull << i; + writeq(reg, cpt->reg_base + otx_cpt_pf_exe_ctl); + + return 0; +} + +static int process_tar_file(struct device *dev, + struct tar_arch_info_t *tar_arch, char *filename, + const u8 *data, u32 size) +{ + struct tar_ucode_info_t *tar_info; + struct otx_cpt_ucode_hdr *ucode_hdr; + int ucode_type, ucode_size; + + /* + * if size is less than microcode header size then don't report + * an error because it might not be microcode file, just process + * next file from archive + */ + if (size < sizeof(struct otx_cpt_ucode_hdr)) + return 0; + + ucode_hdr = (struct otx_cpt_ucode_hdr *) data; + /* + * if microcode version can't be found don't report an error + * because it might not be microcode file, just process next file + */ + if (get_ucode_type(ucode_hdr, &ucode_type)) + return 0; + + ucode_size = ntohl(ucode_hdr->code_length) * 2; + if (!ucode_size || (size < round_up(ucode_size, 16) + + sizeof(struct otx_cpt_ucode_hdr) + otx_cpt_ucode_sign_len)) { + dev_err(dev, "ucode %s invalid size", filename); + return -einval; + } + + tar_info = kzalloc(sizeof(struct tar_ucode_info_t), gfp_kernel); + if (!tar_info) + return -enomem; + + tar_info->ucode_ptr = data; + set_ucode_filename(&tar_info->ucode, filename); + memcpy(tar_info->ucode.ver_str, ucode_hdr->ver_str, + otx_cpt_ucode_ver_str_sz); + tar_info->ucode.ver_num = ucode_hdr->ver_num; + tar_info->ucode.type = ucode_type; + tar_info->ucode.size = ucode_size; + list_add_tail(&tar_info->list, &tar_arch->ucodes); + + return 0; +} + +static void release_tar_archive(struct tar_arch_info_t *tar_arch) +{ + struct tar_ucode_info_t *curr, *temp; + + if (!tar_arch) + return; + + list_for_each_entry_safe(curr, temp, &tar_arch->ucodes, list) { + list_del(&curr->list); + kfree(curr); + } + + if (tar_arch->fw) + release_firmware(tar_arch->fw); + kfree(tar_arch); +} + +static struct tar_ucode_info_t *get_uc_from_tar_archive( + struct tar_arch_info_t *tar_arch, + int ucode_type) +{ + struct tar_ucode_info_t *curr, *uc_found = null; + + list_for_each_entry(curr, &tar_arch->ucodes, list) { + if (!is_eng_type(curr->ucode.type, ucode_type)) + continue; + + if (!uc_found) { + uc_found = curr; + continue; + } + + switch (ucode_type) { + case otx_cpt_ae_types: + break; + + case otx_cpt_se_types: + if (uc_found->ucode.ver_num.nn == otx_cpt_se_uc_type2 || + (uc_found->ucode.ver_num.nn == otx_cpt_se_uc_type3 + && curr->ucode.ver_num.nn == otx_cpt_se_uc_type1)) + uc_found = curr; + break; + } + } + + return uc_found; +} + +static void print_tar_dbg_info(struct tar_arch_info_t *tar_arch, + char *tar_filename) +{ + struct tar_ucode_info_t *curr; + + pr_debug("tar archive filename %s", tar_filename); + pr_debug("tar archive pointer %p, size %ld", tar_arch->fw->data, + tar_arch->fw->size); + list_for_each_entry(curr, &tar_arch->ucodes, list) { + pr_debug("ucode filename %s", curr->ucode.filename); + pr_debug("ucode version string %s", curr->ucode.ver_str); + pr_debug("ucode version %d.%d.%d.%d", + curr->ucode.ver_num.nn, curr->ucode.ver_num.xx, + curr->ucode.ver_num.yy, curr->ucode.ver_num.zz); + pr_debug("ucode type (%d) %s", curr->ucode.type, + get_ucode_type_str(curr->ucode.type)); + pr_debug("ucode size %d", curr->ucode.size); + pr_debug("ucode ptr %p ", curr->ucode_ptr); + } +} + +static struct tar_arch_info_t *load_tar_archive(struct device *dev, + char *tar_filename) +{ + struct tar_arch_info_t *tar_arch = null; + struct tar_blk_t *tar_blk; + unsigned int cur_size; + size_t tar_offs = 0; + size_t tar_size; + int ret; + + tar_arch = kzalloc(sizeof(struct tar_arch_info_t), gfp_kernel); + if (!tar_arch) + return null; + + init_list_head(&tar_arch->ucodes); + + /* load tar archive */ + ret = request_firmware(&tar_arch->fw, tar_filename, dev); + if (ret) + goto release_tar_arch; + + if (tar_arch->fw->size < tar_block_len) { + dev_err(dev, "invalid tar archive %s ", tar_filename); + goto release_tar_arch; + } + + tar_size = tar_arch->fw->size; + tar_blk = (struct tar_blk_t *) tar_arch->fw->data; + if (strncmp(tar_blk->hdr.magic, tar_magic, tar_magic_len - 1)) { + dev_err(dev, "unsupported format of tar archive %s", + tar_filename); + goto release_tar_arch; + } + + while (1) { + /* read current file size */ + ret = kstrtouint(tar_blk->hdr.size, 8, &cur_size); + if (ret) + goto release_tar_arch; + + if (tar_offs + cur_size > tar_size || + tar_offs + 2*tar_block_len > tar_size) { + dev_err(dev, "invalid tar archive %s ", tar_filename); + goto release_tar_arch; + } + + tar_offs += tar_block_len; + if (tar_blk->hdr.typeflag == regtype || + tar_blk->hdr.typeflag == aregtype) { + ret = process_tar_file(dev, tar_arch, + tar_blk->hdr.name, + &tar_arch->fw->data[tar_offs], + cur_size); + if (ret) + goto release_tar_arch; + } + + tar_offs += (cur_size/tar_block_len) * tar_block_len; + if (cur_size % tar_block_len) + tar_offs += tar_block_len; + + /* check for the end of the archive */ + if (tar_offs + 2*tar_block_len > tar_size) { + dev_err(dev, "invalid tar archive %s ", tar_filename); + goto release_tar_arch; + } + + if (is_mem_zero(&tar_arch->fw->data[tar_offs], + 2*tar_block_len)) + break; + + /* read next block from tar archive */ + tar_blk = (struct tar_blk_t *) &tar_arch->fw->data[tar_offs]; + } + + print_tar_dbg_info(tar_arch, tar_filename); + return tar_arch; +release_tar_arch: + release_tar_archive(tar_arch); + return null; +} + +static struct otx_cpt_engs_rsvd *find_engines_by_type( + struct otx_cpt_eng_grp_info *eng_grp, + int eng_type) +{ + int i; + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + if (!eng_grp->engs[i].type) + continue; + + if (eng_grp->engs[i].type == eng_type) + return &eng_grp->engs[i]; + } + return null; +} + +int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type) +{ + return is_eng_type(ucode->type, eng_type); +} +export_symbol_gpl(otx_cpt_uc_supports_eng_type); + +int otx_cpt_eng_grp_has_eng_type(struct otx_cpt_eng_grp_info *eng_grp, + int eng_type) +{ + struct otx_cpt_engs_rsvd *engs; + + engs = find_engines_by_type(eng_grp, eng_type); + + return (engs != null ? 1 : 0); +} +export_symbol_gpl(otx_cpt_eng_grp_has_eng_type); + +static void print_ucode_info(struct otx_cpt_eng_grp_info *eng_grp, + char *buf, int size) +{ + if (eng_grp->mirror.is_ena) { + scnprintf(buf, size, "%s (shared with engine_group%d)", + eng_grp->g->grp[eng_grp->mirror.idx].ucode[0].ver_str, + eng_grp->mirror.idx); + } else { + scnprintf(buf, size, "%s", eng_grp->ucode[0].ver_str); + } +} + +static void print_engs_info(struct otx_cpt_eng_grp_info *eng_grp, + char *buf, int size, int idx) +{ + struct otx_cpt_engs_rsvd *mirrored_engs = null; + struct otx_cpt_engs_rsvd *engs; + int len, i; + + buf[0] = ''; + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + engs = &eng_grp->engs[i]; + if (!engs->type) + continue; + if (idx != -1 && idx != i) + continue; + + if (eng_grp->mirror.is_ena) + mirrored_engs = find_engines_by_type( + &eng_grp->g->grp[eng_grp->mirror.idx], + engs->type); + if (i > 0 && idx == -1) { + len = strlen(buf); + scnprintf(buf+len, size-len, ", "); + } + + len = strlen(buf); + scnprintf(buf+len, size-len, "%d %s ", mirrored_engs ? + engs->count + mirrored_engs->count : engs->count, + get_eng_type_str(engs->type)); + if (mirrored_engs) { + len = strlen(buf); + scnprintf(buf+len, size-len, + "(%d shared with engine_group%d) ", + engs->count <= 0 ? engs->count + + mirrored_engs->count : mirrored_engs->count, + eng_grp->mirror.idx); + } + } +} + +static void print_ucode_dbg_info(struct otx_cpt_ucode *ucode) +{ + pr_debug("ucode info"); + pr_debug("ucode version string %s", ucode->ver_str); + pr_debug("ucode version %d.%d.%d.%d", ucode->ver_num.nn, + ucode->ver_num.xx, ucode->ver_num.yy, ucode->ver_num.zz); + pr_debug("ucode type %s", get_ucode_type_str(ucode->type)); + pr_debug("ucode size %d", ucode->size); + pr_debug("ucode virt address %16.16llx", (u64)ucode->align_va); + pr_debug("ucode phys address %16.16llx ", ucode->align_dma); +} + +static void cpt_print_engines_mask(struct otx_cpt_eng_grp_info *eng_grp, + struct device *dev, char *buf, int size) +{ + struct otx_cpt_bitmap bmap; + u32 mask[2]; + + bmap = get_cores_bmap(dev, eng_grp); + if (!bmap.size) { + scnprintf(buf, size, "unknown"); + return; + } + bitmap_to_arr32(mask, bmap.bits, bmap.size); + scnprintf(buf, size, "%8.8x %8.8x", mask[1], mask[0]); +} + + +static void print_dbg_info(struct device *dev, + struct otx_cpt_eng_grps *eng_grps) +{ + char engs_info[2*otx_cpt_ucode_name_length]; + struct otx_cpt_eng_grp_info *mirrored_grp; + char engs_mask[otx_cpt_ucode_name_length]; + struct otx_cpt_eng_grp_info *grp; + struct otx_cpt_engs_rsvd *engs; + u32 mask[4]; + int i, j; + + pr_debug("engine groups global info"); + pr_debug("max se %d, max ae %d", + eng_grps->avail.max_se_cnt, eng_grps->avail.max_ae_cnt); + pr_debug("free se %d", eng_grps->avail.se_cnt); + pr_debug("free ae %d", eng_grps->avail.ae_cnt); + + for (i = 0; i < otx_cpt_max_engine_groups; i++) { + grp = &eng_grps->grp[i]; + pr_debug("engine_group%d, state %s", i, grp->is_enabled ? + "enabled" : "disabled"); + if (grp->is_enabled) { + mirrored_grp = &eng_grps->grp[grp->mirror.idx]; + pr_debug("ucode0 filename %s, version %s", + grp->mirror.is_ena ? + mirrored_grp->ucode[0].filename : + grp->ucode[0].filename, + grp->mirror.is_ena ? + mirrored_grp->ucode[0].ver_str : + grp->ucode[0].ver_str); + } + + for (j = 0; j < otx_cpt_max_etypes_per_grp; j++) { + engs = &grp->engs[j]; + if (engs->type) { + print_engs_info(grp, engs_info, + 2*otx_cpt_ucode_name_length, j); + pr_debug("slot%d: %s", j, engs_info); + bitmap_to_arr32(mask, engs->bmap, + eng_grps->engs_num); + pr_debug("mask: %8.8x %8.8x %8.8x %8.8x", + mask[3], mask[2], mask[1], mask[0]); + } else + pr_debug("slot%d not used", j); + } + if (grp->is_enabled) { + cpt_print_engines_mask(grp, dev, engs_mask, + otx_cpt_ucode_name_length); + pr_debug("cmask: %s", engs_mask); + } + } +} + +static int update_engines_avail_count(struct device *dev, + struct otx_cpt_engs_available *avail, + struct otx_cpt_engs_rsvd *engs, int val) +{ + switch (engs->type) { + case otx_cpt_se_types: + avail->se_cnt += val; + break; + + case otx_cpt_ae_types: + avail->ae_cnt += val; + break; + + default: + dev_err(dev, "invalid engine type %d ", engs->type); + return -einval; + } + + return 0; +} + +static int update_engines_offset(struct device *dev, + struct otx_cpt_engs_available *avail, + struct otx_cpt_engs_rsvd *engs) +{ + switch (engs->type) { + case otx_cpt_se_types: + engs->offset = 0; + break; + + case otx_cpt_ae_types: + engs->offset = avail->max_se_cnt; + break; + + default: + dev_err(dev, "invalid engine type %d ", engs->type); + return -einval; + } + + return 0; +} + +static int release_engines(struct device *dev, struct otx_cpt_eng_grp_info *grp) +{ + int i, ret = 0; + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + if (!grp->engs[i].type) + continue; + + if (grp->engs[i].count > 0) { + ret = update_engines_avail_count(dev, &grp->g->avail, + &grp->engs[i], + grp->engs[i].count); + if (ret) + return ret; + } + + grp->engs[i].type = 0; + grp->engs[i].count = 0; + grp->engs[i].offset = 0; + grp->engs[i].ucode = null; + bitmap_zero(grp->engs[i].bmap, grp->g->engs_num); + } + + return 0; +} + +static int do_reserve_engines(struct device *dev, + struct otx_cpt_eng_grp_info *grp, + struct otx_cpt_engines *req_engs) +{ + struct otx_cpt_engs_rsvd *engs = null; + int i, ret; + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + if (!grp->engs[i].type) { + engs = &grp->engs[i]; + break; + } + } + + if (!engs) + return -enomem; + + engs->type = req_engs->type; + engs->count = req_engs->count; + + ret = update_engines_offset(dev, &grp->g->avail, engs); + if (ret) + return ret; + + if (engs->count > 0) { + ret = update_engines_avail_count(dev, &grp->g->avail, engs, + -engs->count); + if (ret) + return ret; + } + + return 0; +} + +static int check_engines_availability(struct device *dev, + struct otx_cpt_eng_grp_info *grp, + struct otx_cpt_engines *req_eng) +{ + int avail_cnt = 0; + + switch (req_eng->type) { + case otx_cpt_se_types: + avail_cnt = grp->g->avail.se_cnt; + break; + + case otx_cpt_ae_types: + avail_cnt = grp->g->avail.ae_cnt; + break; + + default: + dev_err(dev, "invalid engine type %d ", req_eng->type); + return -einval; + } + + if (avail_cnt < req_eng->count) { + dev_err(dev, + "error available %s engines %d < than requested %d", + get_eng_type_str(req_eng->type), + avail_cnt, req_eng->count); + return -ebusy; + } + + return 0; +} + +static int reserve_engines(struct device *dev, struct otx_cpt_eng_grp_info *grp, + struct otx_cpt_engines *req_engs, int req_cnt) +{ + int i, ret; + + /* validate if a number of requested engines is available */ + for (i = 0; i < req_cnt; i++) { + ret = check_engines_availability(dev, grp, &req_engs[i]); + if (ret) + return ret; + } + + /* reserve requested engines for this engine group */ + for (i = 0; i < req_cnt; i++) { + ret = do_reserve_engines(dev, grp, &req_engs[i]); + if (ret) + return ret; + } + return 0; +} + +static ssize_t eng_grp_info_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + char ucode_info[2*otx_cpt_ucode_name_length]; + char engs_info[2*otx_cpt_ucode_name_length]; + char engs_mask[otx_cpt_ucode_name_length]; + struct otx_cpt_eng_grp_info *eng_grp; + int ret; + + eng_grp = container_of(attr, struct otx_cpt_eng_grp_info, info_attr); + mutex_lock(&eng_grp->g->lock); + + print_engs_info(eng_grp, engs_info, 2*otx_cpt_ucode_name_length, -1); + print_ucode_info(eng_grp, ucode_info, 2*otx_cpt_ucode_name_length); + cpt_print_engines_mask(eng_grp, dev, engs_mask, + otx_cpt_ucode_name_length); + ret = scnprintf(buf, page_size, + "microcode : %s engines: %s engines mask: %s ", + ucode_info, engs_info, engs_mask); + + mutex_unlock(&eng_grp->g->lock); + return ret; +} + +static int create_sysfs_eng_grps_info(struct device *dev, + struct otx_cpt_eng_grp_info *eng_grp) +{ + int ret; + + eng_grp->info_attr.show = eng_grp_info_show; + eng_grp->info_attr.store = null; + eng_grp->info_attr.attr.name = eng_grp->sysfs_info_name; + eng_grp->info_attr.attr.mode = 0440; + sysfs_attr_init(&eng_grp->info_attr.attr); + ret = device_create_file(dev, &eng_grp->info_attr); + if (ret) + return ret; + + return 0; +} + +static void ucode_unload(struct device *dev, struct otx_cpt_ucode *ucode) +{ + if (ucode->va) { + dma_free_coherent(dev, ucode->size + otx_cpt_ucode_alignment, + ucode->va, ucode->dma); + ucode->va = null; + ucode->align_va = null; + ucode->dma = 0; + ucode->align_dma = 0; + ucode->size = 0; + } + + memset(&ucode->ver_str, 0, otx_cpt_ucode_ver_str_sz); + memset(&ucode->ver_num, 0, sizeof(struct otx_cpt_ucode_ver_num)); + set_ucode_filename(ucode, ""); + ucode->type = 0; +} + +static int copy_ucode_to_dma_mem(struct device *dev, + struct otx_cpt_ucode *ucode, + const u8 *ucode_data) +{ + u32 i; + + /* allocate dmaable space */ + ucode->va = dma_alloc_coherent(dev, ucode->size + + otx_cpt_ucode_alignment, + &ucode->dma, gfp_kernel); + if (!ucode->va) { + dev_err(dev, "unable to allocate space for microcode"); + return -enomem; + } + ucode->align_va = ptr_align(ucode->va, otx_cpt_ucode_alignment); + ucode->align_dma = ptr_align(ucode->dma, otx_cpt_ucode_alignment); + + memcpy((void *) ucode->align_va, (void *) ucode_data + + sizeof(struct otx_cpt_ucode_hdr), ucode->size); + + /* byte swap 64-bit */ + for (i = 0; i < (ucode->size / 8); i++) + ((u64 *)ucode->align_va)[i] = + cpu_to_be64(((u64 *)ucode->align_va)[i]); + /* ucode needs 16-bit swap */ + for (i = 0; i < (ucode->size / 2); i++) + ((u16 *)ucode->align_va)[i] = + cpu_to_be16(((u16 *)ucode->align_va)[i]); + return 0; +} + +static int ucode_load(struct device *dev, struct otx_cpt_ucode *ucode, + const char *ucode_filename) +{ + struct otx_cpt_ucode_hdr *ucode_hdr; + const struct firmware *fw; + int ret; + + set_ucode_filename(ucode, ucode_filename); + ret = request_firmware(&fw, ucode->filename, dev); + if (ret) + return ret; + + ucode_hdr = (struct otx_cpt_ucode_hdr *) fw->data; + memcpy(ucode->ver_str, ucode_hdr->ver_str, otx_cpt_ucode_ver_str_sz); + ucode->ver_num = ucode_hdr->ver_num; + ucode->size = ntohl(ucode_hdr->code_length) * 2; + if (!ucode->size || (fw->size < round_up(ucode->size, 16) + + sizeof(struct otx_cpt_ucode_hdr) + otx_cpt_ucode_sign_len)) { + dev_err(dev, "ucode %s invalid size", ucode_filename); + ret = -einval; + goto release_fw; + } + + ret = get_ucode_type(ucode_hdr, &ucode->type); + if (ret) { + dev_err(dev, "microcode %s unknown type 0x%x", ucode->filename, + ucode->type); + goto release_fw; + } + + ret = copy_ucode_to_dma_mem(dev, ucode, fw->data); + if (ret) + goto release_fw; + + print_ucode_dbg_info(ucode); +release_fw: + release_firmware(fw); + return ret; +} + +static int enable_eng_grp(struct otx_cpt_eng_grp_info *eng_grp, + void *obj) +{ + int ret; + + ret = cpt_set_ucode_base(eng_grp, obj); + if (ret) + return ret; + + ret = cpt_attach_and_enable_cores(eng_grp, obj); + return ret; +} + +static int disable_eng_grp(struct device *dev, + struct otx_cpt_eng_grp_info *eng_grp, + void *obj) +{ + int i, ret; + + ret = cpt_detach_and_disable_cores(eng_grp, obj); + if (ret) + return ret; + + /* unload ucode used by this engine group */ + ucode_unload(dev, &eng_grp->ucode[0]); + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + if (!eng_grp->engs[i].type) + continue; + + eng_grp->engs[i].ucode = &eng_grp->ucode[0]; + } + + ret = cpt_set_ucode_base(eng_grp, obj); + + return ret; +} + +static void setup_eng_grp_mirroring(struct otx_cpt_eng_grp_info *dst_grp, + struct otx_cpt_eng_grp_info *src_grp) +{ + /* setup fields for engine group which is mirrored */ + src_grp->mirror.is_ena = false; + src_grp->mirror.idx = 0; + src_grp->mirror.ref_count++; + + /* setup fields for mirroring engine group */ + dst_grp->mirror.is_ena = true; + dst_grp->mirror.idx = src_grp->idx; + dst_grp->mirror.ref_count = 0; +} + +static void remove_eng_grp_mirroring(struct otx_cpt_eng_grp_info *dst_grp) +{ + struct otx_cpt_eng_grp_info *src_grp; + + if (!dst_grp->mirror.is_ena) + return; + + src_grp = &dst_grp->g->grp[dst_grp->mirror.idx]; + + src_grp->mirror.ref_count--; + dst_grp->mirror.is_ena = false; + dst_grp->mirror.idx = 0; + dst_grp->mirror.ref_count = 0; +} + +static void update_requested_engs(struct otx_cpt_eng_grp_info *mirrored_eng_grp, + struct otx_cpt_engines *engs, int engs_cnt) +{ + struct otx_cpt_engs_rsvd *mirrored_engs; + int i; + + for (i = 0; i < engs_cnt; i++) { + mirrored_engs = find_engines_by_type(mirrored_eng_grp, + engs[i].type); + if (!mirrored_engs) + continue; + + /* + * if mirrored group has this type of engines attached then + * there are 3 scenarios possible: + * 1) mirrored_engs.count == engs[i].count then all engines + * from mirrored engine group will be shared with this engine + * group + * 2) mirrored_engs.count > engs[i].count then only a subset of + * engines from mirrored engine group will be shared with this + * engine group + * 3) mirrored_engs.count < engs[i].count then all engines + * from mirrored engine group will be shared with this group + * and additional engines will be reserved for exclusively use + * by this engine group + */ + engs[i].count -= mirrored_engs->count; + } +} + +static struct otx_cpt_eng_grp_info *find_mirrored_eng_grp( + struct otx_cpt_eng_grp_info *grp) +{ + struct otx_cpt_eng_grps *eng_grps = grp->g; + int i; + + for (i = 0; i < otx_cpt_max_engine_groups; i++) { + if (!eng_grps->grp[i].is_enabled) + continue; + if (eng_grps->grp[i].ucode[0].type) + continue; + if (grp->idx == i) + continue; + if (!strncasecmp(eng_grps->grp[i].ucode[0].ver_str, + grp->ucode[0].ver_str, + otx_cpt_ucode_ver_str_sz)) + return &eng_grps->grp[i]; + } + + return null; +} + +static struct otx_cpt_eng_grp_info *find_unused_eng_grp( + struct otx_cpt_eng_grps *eng_grps) +{ + int i; + + for (i = 0; i < otx_cpt_max_engine_groups; i++) { + if (!eng_grps->grp[i].is_enabled) + return &eng_grps->grp[i]; + } + return null; +} + +static int eng_grp_update_masks(struct device *dev, + struct otx_cpt_eng_grp_info *eng_grp) +{ + struct otx_cpt_engs_rsvd *engs, *mirrored_engs; + struct otx_cpt_bitmap tmp_bmap = { {0} }; + int i, j, cnt, max_cnt; + int bit; + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + engs = &eng_grp->engs[i]; + if (!engs->type) + continue; + if (engs->count <= 0) + continue; + + switch (engs->type) { + case otx_cpt_se_types: + max_cnt = eng_grp->g->avail.max_se_cnt; + break; + + case otx_cpt_ae_types: + max_cnt = eng_grp->g->avail.max_ae_cnt; + break; + + default: + dev_err(dev, "invalid engine type %d", engs->type); + return -einval; + } + + cnt = engs->count; + warn_on(engs->offset + max_cnt > otx_cpt_max_engines); + bitmap_zero(tmp_bmap.bits, eng_grp->g->engs_num); + for (j = engs->offset; j < engs->offset + max_cnt; j++) { + if (!eng_grp->g->eng_ref_cnt[j]) { + bitmap_set(tmp_bmap.bits, j, 1); + cnt--; + if (!cnt) + break; + } + } + + if (cnt) + return -enospc; + + bitmap_copy(engs->bmap, tmp_bmap.bits, eng_grp->g->engs_num); + } + + if (!eng_grp->mirror.is_ena) + return 0; + + for (i = 0; i < otx_cpt_max_etypes_per_grp; i++) { + engs = &eng_grp->engs[i]; + if (!engs->type) + continue; + + mirrored_engs = find_engines_by_type( + &eng_grp->g->grp[eng_grp->mirror.idx], + engs->type); + warn_on(!mirrored_engs && engs->count <= 0); + if (!mirrored_engs) + continue; + + bitmap_copy(tmp_bmap.bits, mirrored_engs->bmap, + eng_grp->g->engs_num); + if (engs->count < 0) { + bit = find_first_bit(mirrored_engs->bmap, + eng_grp->g->engs_num); + bitmap_clear(tmp_bmap.bits, bit, -engs->count); + } + bitmap_or(engs->bmap, engs->bmap, tmp_bmap.bits, + eng_grp->g->engs_num); + } + return 0; +} + +static int delete_engine_group(struct device *dev, + struct otx_cpt_eng_grp_info *eng_grp) +{ + int i, ret; + + if (!eng_grp->is_enabled) + return -einval; + + if (eng_grp->mirror.ref_count) { + dev_err(dev, "can't delete engine_group%d as it is used by:", + eng_grp->idx); + for (i = 0; i < otx_cpt_max_engine_groups; i++) { + if (eng_grp->g->grp[i].mirror.is_ena && + eng_grp->g->grp[i].mirror.idx == eng_grp->idx) + dev_err(dev, "engine_group%d", i); + } + return -einval; + } + + /* removing engine group mirroring if enabled */ + remove_eng_grp_mirroring(eng_grp); + + /* disable engine group */ + ret = disable_eng_grp(dev, eng_grp, eng_grp->g->obj); + if (ret) + return ret; + + /* release all engines held by this engine group */ + ret = release_engines(dev, eng_grp); + if (ret) + return ret; + + device_remove_file(dev, &eng_grp->info_attr); + eng_grp->is_enabled = false; + + return 0; +} + +static int validate_1_ucode_scenario(struct device *dev, + struct otx_cpt_eng_grp_info *eng_grp, + struct otx_cpt_engines *engs, int engs_cnt) +{ + int i; + + /* verify that ucode loaded supports requested engine types */ + for (i = 0; i < engs_cnt; i++) { + if (!otx_cpt_uc_supports_eng_type(&eng_grp->ucode[0], + engs[i].type)) { + dev_err(dev, + "microcode %s does not support %s engines", + eng_grp->ucode[0].filename, + get_eng_type_str(engs[i].type)); + return -einval; + } + } + return 0; +} + +static void update_ucode_ptrs(struct otx_cpt_eng_grp_info *eng_grp) +{ + struct otx_cpt_ucode *ucode; + + if (eng_grp->mirror.is_ena) + ucode = &eng_grp->g->grp[eng_grp->mirror.idx].ucode[0]; + else + ucode = &eng_grp->ucode[0]; + warn_on(!eng_grp->engs[0].type); + eng_grp->engs[0].ucode = ucode; +} + +static int create_engine_group(struct device *dev, + struct otx_cpt_eng_grps *eng_grps, + struct otx_cpt_engines *engs, int engs_cnt, + void *ucode_data[], int ucodes_cnt, + bool use_uc_from_tar_arch) +{ + struct otx_cpt_eng_grp_info *mirrored_eng_grp; + struct tar_ucode_info_t *tar_info; + struct otx_cpt_eng_grp_info *eng_grp; + int i, ret = 0; + + if (ucodes_cnt > otx_cpt_max_etypes_per_grp) + return -einval; + + /* validate if requested engine types are supported by this device */ + for (i = 0; i < engs_cnt; i++) + if (!dev_supports_eng_type(eng_grps, engs[i].type)) { + dev_err(dev, "device does not support %s engines", + get_eng_type_str(engs[i].type)); + return -eperm; + } + + /* find engine group which is not used */ + eng_grp = find_unused_eng_grp(eng_grps); + if (!eng_grp) { + dev_err(dev, "error all engine groups are being used"); + return -enospc; + } + + /* load ucode */ + for (i = 0; i < ucodes_cnt; i++) { + if (use_uc_from_tar_arch) { + tar_info = (struct tar_ucode_info_t *) ucode_data[i]; + eng_grp->ucode[i] = tar_info->ucode; + ret = copy_ucode_to_dma_mem(dev, &eng_grp->ucode[i], + tar_info->ucode_ptr); + } else + ret = ucode_load(dev, &eng_grp->ucode[i], + (char *) ucode_data[i]); + if (ret) + goto err_ucode_unload; + } + + /* validate scenario where 1 ucode is used */ + ret = validate_1_ucode_scenario(dev, eng_grp, engs, engs_cnt); + if (ret) + goto err_ucode_unload; + + /* check if this group mirrors another existing engine group */ + mirrored_eng_grp = find_mirrored_eng_grp(eng_grp); + if (mirrored_eng_grp) { + /* setup mirroring */ + setup_eng_grp_mirroring(eng_grp, mirrored_eng_grp); + + /* + * update count of requested engines because some + * of them might be shared with mirrored group + */ + update_requested_engs(mirrored_eng_grp, engs, engs_cnt); + } + + /* reserve engines */ + ret = reserve_engines(dev, eng_grp, engs, engs_cnt); + if (ret) + goto err_ucode_unload; + + /* update ucode pointers used by engines */ + update_ucode_ptrs(eng_grp); + + /* update engine masks used by this group */ + ret = eng_grp_update_masks(dev, eng_grp); + if (ret) + goto err_release_engs; + + /* create sysfs entry for engine group info */ + ret = create_sysfs_eng_grps_info(dev, eng_grp); + if (ret) + goto err_release_engs; + + /* enable engine group */ + ret = enable_eng_grp(eng_grp, eng_grps->obj); + if (ret) + goto err_release_engs; + + /* + * if this engine group mirrors another engine group + * then we need to unload ucode as we will use ucode + * from mirrored engine group + */ + if (eng_grp->mirror.is_ena) + ucode_unload(dev, &eng_grp->ucode[0]); + + eng_grp->is_enabled = true; + if (eng_grp->mirror.is_ena) + dev_info(dev, + "engine_group%d: reuse microcode %s from group %d", + eng_grp->idx, mirrored_eng_grp->ucode[0].ver_str, + mirrored_eng_grp->idx); + else + dev_info(dev, "engine_group%d: microcode loaded %s", + eng_grp->idx, eng_grp->ucode[0].ver_str); + + return 0; + +err_release_engs: + release_engines(dev, eng_grp); +err_ucode_unload: + ucode_unload(dev, &eng_grp->ucode[0]); + return ret; +} + +static ssize_t ucode_load_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct otx_cpt_engines engs[otx_cpt_max_etypes_per_grp] = { {0} }; + char *ucode_filename[otx_cpt_max_etypes_per_grp]; + char tmp_buf[otx_cpt_ucode_name_length] = { 0 }; + char *start, *val, *err_msg, *tmp; + struct otx_cpt_eng_grps *eng_grps; + int grp_idx = 0, ret = -einval; + bool has_se, has_ie, has_ae; + int del_grp_idx = -1; + int ucode_idx = 0; + + if (strlen(buf) > otx_cpt_ucode_name_length) + return -einval; + + eng_grps = container_of(attr, struct otx_cpt_eng_grps, ucode_load_attr); + err_msg = "invalid engine group format"; + strlcpy(tmp_buf, buf, otx_cpt_ucode_name_length); + start = tmp_buf; + + has_se = has_ie = has_ae = false; + + for (;;) { + val = strsep(&start, ";"); + if (!val) + break; + val = strim(val); + if (!*val) + continue; + + if (!strncasecmp(val, "engine_group", 12)) { + if (del_grp_idx != -1) + goto err_print; + tmp = strim(strsep(&val, ":")); + if (!val) + goto err_print; + if (strlen(tmp) != 13) + goto err_print; + if (kstrtoint((tmp + 12), 10, &del_grp_idx)) + goto err_print; + val = strim(val); + if (strncasecmp(val, "null", 4)) + goto err_print; + if (strlen(val) != 4) + goto err_print; + } else if (!strncasecmp(val, "se", 2) && strchr(val, ':')) { + if (has_se || ucode_idx) + goto err_print; + tmp = strim(strsep(&val, ":")); + if (!val) + goto err_print; + if (strlen(tmp) != 2) + goto err_print; + if (kstrtoint(strim(val), 10, &engs[grp_idx].count)) + goto err_print; + engs[grp_idx++].type = otx_cpt_se_types; + has_se = true; + } else if (!strncasecmp(val, "ae", 2) && strchr(val, ':')) { + if (has_ae || ucode_idx) + goto err_print; + tmp = strim(strsep(&val, ":")); + if (!val) + goto err_print; + if (strlen(tmp) != 2) + goto err_print; + if (kstrtoint(strim(val), 10, &engs[grp_idx].count)) + goto err_print; + engs[grp_idx++].type = otx_cpt_ae_types; + has_ae = true; + } else { + if (ucode_idx > 1) + goto err_print; + if (!strlen(val)) + goto err_print; + if (strnstr(val, " ", strlen(val))) + goto err_print; + ucode_filename[ucode_idx++] = val; + } + } + + /* validate input parameters */ + if (del_grp_idx == -1) { + if (!(grp_idx && ucode_idx)) + goto err_print; + + if (ucode_idx > 1 && grp_idx < 2) + goto err_print; + + if (grp_idx > otx_cpt_max_etypes_per_grp) { + err_msg = "error max 2 engine types can be attached"; + goto err_print; + } + + } else { + if (del_grp_idx < 0 || + del_grp_idx >= otx_cpt_max_engine_groups) { + dev_err(dev, "invalid engine group index %d", + del_grp_idx); + ret = -einval; + return ret; + } + + if (!eng_grps->grp[del_grp_idx].is_enabled) { + dev_err(dev, "error engine_group%d is not configured", + del_grp_idx); + ret = -einval; + return ret; + } + + if (grp_idx || ucode_idx) + goto err_print; + } + + mutex_lock(&eng_grps->lock); + + if (eng_grps->is_rdonly) { + dev_err(dev, "disable vfs before modifying engine groups "); + ret = -eacces; + goto err_unlock; + } + + if (del_grp_idx == -1) + /* create engine group */ + ret = create_engine_group(dev, eng_grps, engs, grp_idx, + (void **) ucode_filename, + ucode_idx, false); + else + /* delete engine group */ + ret = delete_engine_group(dev, &eng_grps->grp[del_grp_idx]); + if (ret) + goto err_unlock; + + print_dbg_info(dev, eng_grps); +err_unlock: + mutex_unlock(&eng_grps->lock); + return ret ? ret : count; +err_print: + dev_err(dev, "%s ", err_msg); + + return ret; +} + +int otx_cpt_try_create_default_eng_grps(struct pci_dev *pdev, + struct otx_cpt_eng_grps *eng_grps, + int pf_type) +{ + struct tar_ucode_info_t *tar_info[otx_cpt_max_etypes_per_grp] = { 0 }; + struct otx_cpt_engines engs[otx_cpt_max_etypes_per_grp] = { {0} }; + struct tar_arch_info_t *tar_arch = null; + char *tar_filename; + int i, ret = 0; + + mutex_lock(&eng_grps->lock); + + /* + * we don't create engine group for kernel crypto if attempt to create + * it was already made (when user enabled vfs for the first time) + */ + if (eng_grps->is_first_try) + goto unlock_mutex; + eng_grps->is_first_try = true; + + /* we create group for kcrypto only if no groups are configured */ + for (i = 0; i < otx_cpt_max_engine_groups; i++) + if (eng_grps->grp[i].is_enabled) + goto unlock_mutex; + + switch (pf_type) { + case otx_cpt_ae: + case otx_cpt_se: + tar_filename = otx_cpt_ucode_tar_file_name; + break; + + default: + dev_err(&pdev->dev, "unknown pf type %d ", pf_type); + ret = -einval; + goto unlock_mutex; + } + + tar_arch = load_tar_archive(&pdev->dev, tar_filename); + if (!tar_arch) + goto unlock_mutex; + + /* + * if device supports se engines and there is se microcode in tar + * archive try to create engine group with se engines for kernel + * crypto functionality (symmetric crypto) + */ + tar_info[0] = get_uc_from_tar_archive(tar_arch, otx_cpt_se_types); + if (tar_info[0] && + dev_supports_eng_type(eng_grps, otx_cpt_se_types)) { + + engs[0].type = otx_cpt_se_types; + engs[0].count = eng_grps->avail.max_se_cnt; + + ret = create_engine_group(&pdev->dev, eng_grps, engs, 1, + (void **) tar_info, 1, true); + if (ret) + goto release_tar_arch; + } + /* + * if device supports ae engines and there is ae microcode in tar + * archive try to create engine group with ae engines for asymmetric + * crypto functionality. + */ + tar_info[0] = get_uc_from_tar_archive(tar_arch, otx_cpt_ae_types); + if (tar_info[0] && + dev_supports_eng_type(eng_grps, otx_cpt_ae_types)) { + + engs[0].type = otx_cpt_ae_types; + engs[0].count = eng_grps->avail.max_ae_cnt; + + ret = create_engine_group(&pdev->dev, eng_grps, engs, 1, + (void **) tar_info, 1, true); + if (ret) + goto release_tar_arch; + } + + print_dbg_info(&pdev->dev, eng_grps); +release_tar_arch: + release_tar_archive(tar_arch); +unlock_mutex: + mutex_unlock(&eng_grps->lock); + return ret; +} + +void otx_cpt_set_eng_grps_is_rdonly(struct otx_cpt_eng_grps *eng_grps, + bool is_rdonly) +{ + mutex_lock(&eng_grps->lock); + + eng_grps->is_rdonly = is_rdonly; + + mutex_unlock(&eng_grps->lock); +} + +void otx_cpt_disable_all_cores(struct otx_cpt_device *cpt) +{ + int grp, timeout = 100; + u64 reg; + + /* disengage the cores from groups */ + for (grp = 0; grp < otx_cpt_max_engine_groups; grp++) { + writeq(0, cpt->reg_base + otx_cpt_pf_gx_en(grp)); + udelay(csr_delay); + } + + reg = readq(cpt->reg_base + otx_cpt_pf_exec_busy); + while (reg) { + udelay(csr_delay); + reg = readq(cpt->reg_base + otx_cpt_pf_exec_busy); + if (timeout--) { + dev_warn(&cpt->pdev->dev, "cores still busy"); + break; + } + } + + /* disable the cores */ + writeq(0, cpt->reg_base + otx_cpt_pf_exe_ctl); +} + +void otx_cpt_cleanup_eng_grps(struct pci_dev *pdev, + struct otx_cpt_eng_grps *eng_grps) +{ + struct otx_cpt_eng_grp_info *grp; + int i, j; + + mutex_lock(&eng_grps->lock); + if (eng_grps->is_ucode_load_created) { + device_remove_file(&pdev->dev, + &eng_grps->ucode_load_attr); + eng_grps->is_ucode_load_created = false; + } + + /* first delete all mirroring engine groups */ + for (i = 0; i < otx_cpt_max_engine_groups; i++) + if (eng_grps->grp[i].mirror.is_ena) + delete_engine_group(&pdev->dev, &eng_grps->grp[i]); + + /* delete remaining engine groups */ + for (i = 0; i < otx_cpt_max_engine_groups; i++) + delete_engine_group(&pdev->dev, &eng_grps->grp[i]); + + /* release memory */ + for (i = 0; i < otx_cpt_max_engine_groups; i++) { + grp = &eng_grps->grp[i]; + for (j = 0; j < otx_cpt_max_etypes_per_grp; j++) { + kfree(grp->engs[j].bmap); + grp->engs[j].bmap = null; + } + } + + mutex_unlock(&eng_grps->lock); +} + +int otx_cpt_init_eng_grps(struct pci_dev *pdev, + struct otx_cpt_eng_grps *eng_grps, int pf_type) +{ + struct otx_cpt_eng_grp_info *grp; + int i, j, ret = 0; + + mutex_init(&eng_grps->lock); + eng_grps->obj = pci_get_drvdata(pdev); + eng_grps->avail.se_cnt = eng_grps->avail.max_se_cnt; + eng_grps->avail.ae_cnt = eng_grps->avail.max_ae_cnt; + + eng_grps->engs_num = eng_grps->avail.max_se_cnt + + eng_grps->avail.max_ae_cnt; + if (eng_grps->engs_num > otx_cpt_max_engines) { + dev_err(&pdev->dev, + "number of engines %d > than max supported %d", + eng_grps->engs_num, otx_cpt_max_engines); + ret = -einval; + goto err; + } + + for (i = 0; i < otx_cpt_max_engine_groups; i++) { + grp = &eng_grps->grp[i]; + grp->g = eng_grps; + grp->idx = i; + + snprintf(grp->sysfs_info_name, otx_cpt_ucode_name_length, + "engine_group%d", i); + for (j = 0; j < otx_cpt_max_etypes_per_grp; j++) { + grp->engs[j].bmap = + kcalloc(bits_to_longs(eng_grps->engs_num), + sizeof(long), gfp_kernel); + if (!grp->engs[j].bmap) { + ret = -enomem; + goto err; + } + } + } + + switch (pf_type) { + case otx_cpt_se: + /* octeontx 83xx se cpt pf has only se engines attached */ + eng_grps->eng_types_supported = 1 << otx_cpt_se_types; + break; + + case otx_cpt_ae: + /* octeontx 83xx ae cpt pf has only ae engines attached */ + eng_grps->eng_types_supported = 1 << otx_cpt_ae_types; + break; + + default: + dev_err(&pdev->dev, "unknown pf type %d ", pf_type); + ret = -einval; + goto err; + } + + eng_grps->ucode_load_attr.show = null; + eng_grps->ucode_load_attr.store = ucode_load_store; + eng_grps->ucode_load_attr.attr.name = "ucode_load"; + eng_grps->ucode_load_attr.attr.mode = 0220; + sysfs_attr_init(&eng_grps->ucode_load_attr.attr); + ret = device_create_file(&pdev->dev, + &eng_grps->ucode_load_attr); + if (ret) + goto err; + eng_grps->is_ucode_load_created = true; + + print_dbg_info(&pdev->dev, eng_grps); + return ret; +err: + otx_cpt_cleanup_eng_grps(pdev, eng_grps); + return ret; +} diff --git a/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.h b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptpf_ucode.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cptpf_ucode_h +#define __otx_cptpf_ucode_h + +#include <linux/pci.h> +#include <linux/types.h> +#include <linux/module.h> +#include "otx_cpt_hw_types.h" + +/* cpt ucode name maximum length */ +#define otx_cpt_ucode_name_length 64 +/* + * on octeontx 83xx platform, only one type of engines is allowed to be + * attached to an engine group. + */ +#define otx_cpt_max_etypes_per_grp 1 + +/* default tar archive file names */ +#define otx_cpt_ucode_tar_file_name "cpt8x-mc.tar" + +/* cpt ucode alignment */ +#define otx_cpt_ucode_alignment 128 + +/* cpt ucode signature size */ +#define otx_cpt_ucode_sign_len 256 + +/* microcode version string length */ +#define otx_cpt_ucode_ver_str_sz 44 + +/* maximum number of supported engines/cores on octeontx 83xx platform */ +#define otx_cpt_max_engines 64 + +#define otx_cpt_engs_bitmask_len (otx_cpt_max_engines/(bits_per_byte * \ + sizeof(unsigned long))) + +/* microcode types */ +enum otx_cpt_ucode_type { + otx_cpt_ae_uc_type = 1, /* ae-main */ + otx_cpt_se_uc_type1 = 20, /* se-main - combination of 21 and 22 */ + otx_cpt_se_uc_type2 = 21, /* fast path ipsec + aircrypto */ + otx_cpt_se_uc_type3 = 22, /* + * hash + hmac + flexicrypto + rng + full + * feature ipsec + aircrypto + kasumi + */ +}; + +struct otx_cpt_bitmap { + unsigned long bits[otx_cpt_engs_bitmask_len]; + int size; +}; + +struct otx_cpt_engines { + int type; + int count; +}; + +/* microcode version number */ +struct otx_cpt_ucode_ver_num { + u8 nn; + u8 xx; + u8 yy; + u8 zz; +}; + +struct otx_cpt_ucode_hdr { + struct otx_cpt_ucode_ver_num ver_num; + u8 ver_str[otx_cpt_ucode_ver_str_sz]; + u32 code_length; + u32 padding[3]; +}; + +struct otx_cpt_ucode { + u8 ver_str[otx_cpt_ucode_ver_str_sz];/* + * ucode version in readable format + */ + struct otx_cpt_ucode_ver_num ver_num;/* ucode version number */ + char filename[otx_cpt_ucode_name_length]; /* ucode filename */ + dma_addr_t dma; /* phys address of ucode image */ + dma_addr_t align_dma; /* aligned phys address of ucode image */ + void *va; /* virt address of ucode image */ + void *align_va; /* aligned virt address of ucode image */ + u32 size; /* ucode image size */ + int type; /* ucode image type se or ae */ +}; + +struct tar_ucode_info_t { + struct list_head list; + struct otx_cpt_ucode ucode;/* microcode information */ + const u8 *ucode_ptr; /* pointer to microcode in tar archive */ +}; + +/* maximum and current number of engines available for all engine groups */ +struct otx_cpt_engs_available { + int max_se_cnt; + int max_ae_cnt; + int se_cnt; + int ae_cnt; +}; + +/* engines reserved to an engine group */ +struct otx_cpt_engs_rsvd { + int type; /* engine type */ + int count; /* number of engines attached */ + int offset; /* constant offset of engine type in the bitmap */ + unsigned long *bmap; /* attached engines bitmap */ + struct otx_cpt_ucode *ucode; /* ucode used by these engines */ +}; + +struct otx_cpt_mirror_info { + int is_ena; /* + * is mirroring enabled, it is set only for engine + * group which mirrors another engine group + */ + int idx; /* + * index of engine group which is mirrored by this + * group, set only for engine group which mirrors + * another group + */ + int ref_count; /* + * number of times this engine group is mirrored by + * other groups, this is set only for engine group + * which is mirrored by other group(s) + */ +}; + +struct otx_cpt_eng_grp_info { + struct otx_cpt_eng_grps *g; /* pointer to engine_groups structure */ + struct device_attribute info_attr; /* group info entry attr */ + /* engines attached */ + struct otx_cpt_engs_rsvd engs[otx_cpt_max_etypes_per_grp]; + /* microcode information */ + struct otx_cpt_ucode ucode[otx_cpt_max_etypes_per_grp]; + /* sysfs info entry name */ + char sysfs_info_name[otx_cpt_ucode_name_length]; + /* engine group mirroring information */ + struct otx_cpt_mirror_info mirror; + int idx; /* engine group index */ + bool is_enabled; /* + * is engine group enabled, engine group is enabled + * when it has engines attached and ucode loaded + */ +}; + +struct otx_cpt_eng_grps { + struct otx_cpt_eng_grp_info grp[otx_cpt_max_engine_groups]; + struct device_attribute ucode_load_attr;/* ucode load attr */ + struct otx_cpt_engs_available avail; + struct mutex lock; + void *obj; + int engs_num; /* total number of engines supported */ + int eng_types_supported; /* engine types supported se, ae */ + u8 eng_ref_cnt[otx_cpt_max_engines];/* engines reference count */ + bool is_ucode_load_created; /* is ucode_load sysfs entry created */ + bool is_first_try; /* is this first try to create kcrypto engine grp */ + bool is_rdonly; /* do engine groups configuration can be modified */ +}; + +int otx_cpt_init_eng_grps(struct pci_dev *pdev, + struct otx_cpt_eng_grps *eng_grps, int pf_type); +void otx_cpt_cleanup_eng_grps(struct pci_dev *pdev, + struct otx_cpt_eng_grps *eng_grps); +int otx_cpt_try_create_default_eng_grps(struct pci_dev *pdev, + struct otx_cpt_eng_grps *eng_grps, + int pf_type); +void otx_cpt_set_eng_grps_is_rdonly(struct otx_cpt_eng_grps *eng_grps, + bool is_rdonly); +int otx_cpt_uc_supports_eng_type(struct otx_cpt_ucode *ucode, int eng_type); +int otx_cpt_eng_grp_has_eng_type(struct otx_cpt_eng_grp_info *eng_grp, + int eng_type); + +#endif /* __otx_cptpf_ucode_h */
|
Cryptography hardware acceleration
|
d9110b0b01ff1cd02751cd5c2c94e938a8906083
|
srujanachalla
|
drivers
|
crypto
|
marvell, octeontx
|
crypto: marvell - add the virtual function driver for cpt
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add support for the cryptographic accelerator unit virtual functions on octeontx 83xx soc.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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support for marvell octeontx cpt driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['marvell']
|
['h', 'c', 'makefile']
| 9
| 4,686
| 2
|
--- diff --git a/drivers/crypto/marvell/octeontx/makefile b/drivers/crypto/marvell/octeontx/makefile --- a/drivers/crypto/marvell/octeontx/makefile +++ b/drivers/crypto/marvell/octeontx/makefile -obj-$(config_crypto_dev_octeontx_cpt) += octeontx-cpt.o +obj-$(config_crypto_dev_octeontx_cpt) += octeontx-cpt.o octeontx-cptvf.o +octeontx-cptvf-objs := otx_cptvf_main.o otx_cptvf_mbox.o otx_cptvf_reqmgr.o \ + otx_cptvf_algs.o diff --git a/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h b/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h --- a/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h +++ b/drivers/crypto/marvell/octeontx/otx_cpt_hw_types.h +#define otx_cpt_pci_vf_device_id 0xa041 +#define otx_cpt_pci_vf_subsys_id 0xa341 +#define otx_cpt_vf_pci_cfg_bar 0 + +#define otx_cpt_bar_e_cptx_vfx_bar0_offset(a, b) \ + (0x000020000000ll + 0x1000000000ll * (a) + 0x100000ll * (b)) +#define otx_cpt_bar_e_cptx_vfx_bar0_size 0x400000 + +/* cpt instruction size in bytes */ +#define otx_cpt_inst_size 64 +/* cpt queue next chunk pointer size in bytes */ +#define otx_cpt_next_chunk_ptr_size 8 + +/* octeontx cpt vf msix vectors and their offsets */ +#define otx_cpt_vf_msix_vectors 2 +#define otx_cpt_vf_intr_mbox_mask bit(0) +#define otx_cpt_vf_intr_dovf_mask bit(1) +#define otx_cpt_vf_intr_irde_mask bit(2) +#define otx_cpt_vf_intr_nwrp_mask bit(3) +#define otx_cpt_vf_intr_serr_mask bit(4) + +/* octeontx cpt vf registers */ +#define otx_cpt_vqx_ctl(b) (0x100ll | (u64)(b) << 20) +#define otx_cpt_vqx_saddr(b) (0x200ll | (u64)(b) << 20) +#define otx_cpt_vqx_done_wait(b) (0x400ll | (u64)(b) << 20) +#define otx_cpt_vqx_inprog(b) (0x410ll | (u64)(b) << 20) +#define otx_cpt_vqx_done(b) (0x420ll | (u64)(b) << 20) +#define otx_cpt_vqx_done_ack(b) (0x440ll | (u64)(b) << 20) +#define otx_cpt_vqx_done_int_w1s(b) (0x460ll | (u64)(b) << 20) +#define otx_cpt_vqx_done_int_w1c(b) (0x468ll | (u64)(b) << 20) +#define otx_cpt_vqx_done_ena_w1s(b) (0x470ll | (u64)(b) << 20) +#define otx_cpt_vqx_done_ena_w1c(b) (0x478ll | (u64)(b) << 20) +#define otx_cpt_vqx_misc_int(b) (0x500ll | (u64)(b) << 20) +#define otx_cpt_vqx_misc_int_w1s(b) (0x508ll | (u64)(b) << 20) +#define otx_cpt_vqx_misc_ena_w1s(b) (0x510ll | (u64)(b) << 20) +#define otx_cpt_vqx_misc_ena_w1c(b) (0x518ll | (u64)(b) << 20) +#define otx_cpt_vqx_doorbell(b) (0x600ll | (u64)(b) << 20) +#define otx_cpt_vfx_pf_mboxx(b, c) (0x1000ll | ((b) << 20) | ((c) << 3)) + +/* + * enumeration otx_cpt_ucode_error_code_e + * + * enumerates ucode errors + */ +enum otx_cpt_ucode_error_code_e { + cpt_no_ucode_error = 0x00, + err_opcode_unsupported = 0x01, + + /* scatter gather */ + err_scatter_gather_write_length = 0x02, + err_scatter_gather_list = 0x03, + err_scatter_gather_not_supported = 0x04, + +}; + +/* + * enumeration otx_cpt_comp_e + * + * cpt octeontx completion enumeration + * enumerates the values of cpt_res_s[compcode]. + */ +enum otx_cpt_comp_e { + cpt_comp_e_notdone = 0x00, + cpt_comp_e_good = 0x01, + cpt_comp_e_fault = 0x02, + cpt_comp_e_swerr = 0x03, + cpt_comp_e_hwerr = 0x04, + cpt_comp_e_last_entry = 0x05 +}; + +/* + * enumeration otx_cpt_vf_int_vec_e + * + * cpt octeontx vf msi-x vector enumeration + * enumerates the msi-x interrupt vectors. + */ +enum otx_cpt_vf_int_vec_e { + cpt_vf_int_vec_e_misc = 0x00, + cpt_vf_int_vec_e_done = 0x01 +}; + +/* + * structure cpt_inst_s + * + * cpt instruction structure + * this structure specifies the instruction layout. instructions are + * stored in memory as little-endian unless cpt()_pf_q()_ctl[inst_be] is set. + * cpt_inst_s_s + * word 0 + * doneint:1 done interrupt. + * 0 = no interrupts related to this instruction. + * 1 = when the instruction completes, cpt()_vq()_done[done] will be + * incremented,and based on the rules described there an interrupt may + * occur. + * word 1 + * res_addr [127: 64] result iova. + * if nonzero, specifies where to write cpt_res_s. + * if zero, no result structure will be written. + * address must be 16-byte aligned. + * bits <63:49> are ignored by hardware; software should use a + * sign-extended bit <48> for forward compatibility. + * word 2 + * grp:10 [171:162] if [wq_ptr] is nonzero, the sso guest-group to use when + * cpt submits work sso. + * for the sso to not discard the add-work request, fpa_pf_map() must map + * [grp] and cpt()_pf_q()_gmctl[gmid] as valid. + * tt:2 [161:160] if [wq_ptr] is nonzero, the sso tag type to use when cpt + * submits work to sso + * tag:32 [159:128] if [wq_ptr] is nonzero, the sso tag to use when cpt + * submits work to sso. + * word 3 + * wq_ptr [255:192] if [wq_ptr] is nonzero, it is a pointer to a + * work-queue entry that cpt submits work to sso after all context, + * output data, and result write operations are visible to other + * cnxxxx units and the cores. bits <2:0> must be zero. + * bits <63:49> are ignored by hardware; software should + * use a sign-extended bit <48> for forward compatibility. + * internal: + * bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0. + * word 4 + * ei0; [319:256] engine instruction word 0. passed to the ae/se. + * word 5 + * ei1; [383:320] engine instruction word 1. passed to the ae/se. + * word 6 + * ei2; [447:384] engine instruction word 1. passed to the ae/se. + * word 7 + * ei3; [511:448] engine instruction word 1. passed to the ae/se. + * + */ +union otx_cpt_inst_s { + u64 u[8]; + + struct { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_17_63:47; + u64 doneint:1; + u64 reserved_0_15:16; +#else /* word 0 - little endian */ + u64 reserved_0_15:16; + u64 doneint:1; + u64 reserved_17_63:47; +#endif /* word 0 - end */ + u64 res_addr; +#if defined(__big_endian_bitfield) /* word 2 - big endian */ + u64 reserved_172_191:20; + u64 grp:10; + u64 tt:2; + u64 tag:32; +#else /* word 2 - little endian */ + u64 tag:32; + u64 tt:2; + u64 grp:10; + u64 reserved_172_191:20; +#endif /* word 2 - end */ + u64 wq_ptr; + u64 ei0; + u64 ei1; + u64 ei2; + u64 ei3; + } s; +}; + +/* + * structure cpt_res_s + * + * cpt result structure + * the cpt coprocessor writes the result structure after it completes a + * cpt_inst_s instruction. the result structure is exactly 16 bytes, and + * each instruction completion produces exactly one result structure. + * + * this structure is stored in memory as little-endian unless + * cpt()_pf_q()_ctl[inst_be] is set. + * cpt_res_s_s + * word 0 + * doneint:1 [16:16] done interrupt. this bit is copied from the + * corresponding instruction's cpt_inst_s[doneint]. + * compcode:8 [7:0] indicates completion/error status of the cpt coprocessor + * for the associated instruction, as enumerated by cpt_comp_e. + * core software may write the memory location containing [compcode] to + * 0x0 before ringing the doorbell, and then poll for completion by + * checking for a nonzero value. + * once the core observes a nonzero [compcode] value in this case,the cpt + * coprocessor will have also completed l2/dram write operations. + * word 1 + * reserved + * + */ +union otx_cpt_res_s { + u64 u[2]; + struct { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_17_63:47; + u64 doneint:1; + u64 reserved_8_15:8; + u64 compcode:8; +#else /* word 0 - little endian */ + u64 compcode:8; + u64 reserved_8_15:8; + u64 doneint:1; + u64 reserved_17_63:47; +#endif /* word 0 - end */ + u64 reserved_64_127; + } s; +}; + -#endif /* __otx_cpt_hw_types_h */ + +/* + * register (ncb) otx_cpt#_vq#_saddr + * + * cpt queue starting buffer address registers + * these registers set the instruction buffer starting address. + * otx_cptx_vqx_saddr_s + * word0 + * reserved_49_63:15 [63:49] reserved. + * ptr:43 [48:6](r/w/h) instruction buffer iova <48:6> (64-byte aligned). + * when written, it is the initial buffer starting address; when read, + * it is the next read pointer to be requested from l2c. the ptr field + * is overwritten with the next pointer each time that the command buffer + * segment is exhausted. new commands will then be read from the newly + * specified command buffer pointer. + * reserved_0_5:6 [5:0] reserved. + * + */ +union otx_cptx_vqx_saddr { + u64 u; + struct otx_cptx_vqx_saddr_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_49_63:15; + u64 ptr:43; + u64 reserved_0_5:6; +#else /* word 0 - little endian */ + u64 reserved_0_5:6; + u64 ptr:43; + u64 reserved_49_63:15; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_misc_ena_w1s + * + * cpt queue misc interrupt enable set register + * this register sets interrupt enable bits. + * otx_cptx_vqx_misc_ena_w1s_s + * word0 + * reserved_5_63:59 [63:5] reserved. + * swerr:1 [4:4](r/w1s/h) reads or sets enable for + * cpt(0..1)_vq(0..63)_misc_int[swerr]. + * nwrp:1 [3:3](r/w1s/h) reads or sets enable for + * cpt(0..1)_vq(0..63)_misc_int[nwrp]. + * irde:1 [2:2](r/w1s/h) reads or sets enable for + * cpt(0..1)_vq(0..63)_misc_int[irde]. + * dovf:1 [1:1](r/w1s/h) reads or sets enable for + * cpt(0..1)_vq(0..63)_misc_int[dovf]. + * mbox:1 [0:0](r/w1s/h) reads or sets enable for + * cpt(0..1)_vq(0..63)_misc_int[mbox]. + * + */ +union otx_cptx_vqx_misc_ena_w1s { + u64 u; + struct otx_cptx_vqx_misc_ena_w1s_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_5_63:59; + u64 swerr:1; + u64 nwrp:1; + u64 irde:1; + u64 dovf:1; + u64 mbox:1; +#else /* word 0 - little endian */ + u64 mbox:1; + u64 dovf:1; + u64 irde:1; + u64 nwrp:1; + u64 swerr:1; + u64 reserved_5_63:59; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_doorbell + * + * cpt queue doorbell registers + * doorbells for the cpt instruction queues. + * otx_cptx_vqx_doorbell_s + * word0 + * reserved_20_63:44 [63:20] reserved. + * dbell_cnt:20 [19:0](r/w/h) number of instruction queue 64-bit words to add + * to the cpt instruction doorbell count. readback value is the the + * current number of pending doorbell requests. if counter overflows + * cpt()_vq()_misc_int[dbell_dovf] is set. to reset the count back to + * zero, write one to clear cpt()_vq()_misc_int_ena_w1c[dbell_dovf], + * then write a value of 2^20 minus the read [dbell_cnt], then write one + * to cpt()_vq()_misc_int_w1c[dbell_dovf] and + * cpt()_vq()_misc_int_ena_w1s[dbell_dovf]. must be a multiple of 8. + * all cpt instructions are 8 words and require a doorbell count of + * multiple of 8. + */ +union otx_cptx_vqx_doorbell { + u64 u; + struct otx_cptx_vqx_doorbell_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_20_63:44; + u64 dbell_cnt:20; +#else /* word 0 - little endian */ + u64 dbell_cnt:20; + u64 reserved_20_63:44; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_inprog + * + * cpt queue in progress count registers + * these registers contain the per-queue instruction in flight registers. + * otx_cptx_vqx_inprog_s + * word0 + * reserved_8_63:56 [63:8] reserved. + * inflight:8 [7:0](ro/h) inflight count. counts the number of instructions + * for the vf for which cpt is fetching, executing or responding to + * instructions. however this does not include any interrupts that are + * awaiting software handling (cpt()_vq()_done[done] != 0x0). + * a queue may not be reconfigured until: + * 1. cpt()_vq()_ctl[ena] is cleared by software. + * 2. [inflight] is polled until equals to zero. + */ +union otx_cptx_vqx_inprog { + u64 u; + struct otx_cptx_vqx_inprog_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_8_63:56; + u64 inflight:8; +#else /* word 0 - little endian */ + u64 inflight:8; + u64 reserved_8_63:56; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_misc_int + * + * cpt queue misc interrupt register + * these registers contain the per-queue miscellaneous interrupts. + * otx_cptx_vqx_misc_int_s + * word 0 + * reserved_5_63:59 [63:5] reserved. + * swerr:1 [4:4](r/w1c/h) software error from engines. + * nwrp:1 [3:3](r/w1c/h) ncb result write response error. + * irde:1 [2:2](r/w1c/h) instruction ncb read response error. + * dovf:1 [1:1](r/w1c/h) doorbell overflow. + * mbox:1 [0:0](r/w1c/h) pf to vf mailbox interrupt. set when + * cpt()_vf()_pf_mbox(0) is written. + * + */ +union otx_cptx_vqx_misc_int { + u64 u; + struct otx_cptx_vqx_misc_int_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_5_63:59; + u64 swerr:1; + u64 nwrp:1; + u64 irde:1; + u64 dovf:1; + u64 mbox:1; +#else /* word 0 - little endian */ + u64 mbox:1; + u64 dovf:1; + u64 irde:1; + u64 nwrp:1; + u64 swerr:1; + u64 reserved_5_63:59; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_done_ack + * + * cpt queue done count ack registers + * this register is written by software to acknowledge interrupts. + * otx_cptx_vqx_done_ack_s + * word0 + * reserved_20_63:44 [63:20] reserved. + * done_ack:20 [19:0](r/w/h) number of decrements to cpt()_vq()_done[done]. + * reads cpt()_vq()_done[done]. written by software to acknowledge + * interrupts. if cpt()_vq()_done[done] is still nonzero the interrupt + * will be re-sent if the conditions described in cpt()_vq()_done[done] + * are satisfied. + * + */ +union otx_cptx_vqx_done_ack { + u64 u; + struct otx_cptx_vqx_done_ack_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_20_63:44; + u64 done_ack:20; +#else /* word 0 - little endian */ + u64 done_ack:20; + u64 reserved_20_63:44; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_done + * + * cpt queue done count registers + * these registers contain the per-queue instruction done count. + * cptx_vqx_done_s + * word0 + * reserved_20_63:44 [63:20] reserved. + * done:20 [19:0](r/w/h) done count. when cpt_inst_s[doneint] set and that + * instruction completes, cpt()_vq()_done[done] is incremented when the + * instruction finishes. write to this field are for diagnostic use only; + * instead software writes cpt()_vq()_done_ack with the number of + * decrements for this field. + * interrupts are sent as follows: + * * when cpt()_vq()_done[done] = 0, then no results are pending, the + * interrupt coalescing timer is held to zero, and an interrupt is not + * sent. + * * when cpt()_vq()_done[done] != 0, then the interrupt coalescing timer + * counts. if the counter is >= cpt()_vq()_done_wait[time_wait]*1024, or + * cpt()_vq()_done[done] >= cpt()_vq()_done_wait[num_wait], i.e. enough + * time has passed or enough results have arrived, then the interrupt is + * sent. + * * when cpt()_vq()_done_ack is written (or cpt()_vq()_done is written + * but this is not typical), the interrupt coalescing timer restarts. + * note after decrementing this interrupt equation is recomputed, + * for example if cpt()_vq()_done[done] >= cpt()_vq()_done_wait[num_wait] + * and because the timer is zero, the interrupt will be resent immediately. + * (this covers the race case between software acknowledging an interrupt + * and a result returning.) + * * when cpt()_vq()_done_ena_w1s[done] = 0, interrupts are not sent, + * but the counting described above still occurs. + * since cpt instructions complete out-of-order, if software is using + * completion interrupts the suggested scheme is to request a doneint on + * each request, and when an interrupt arrives perform a "greedy" scan for + * completions; even if a later command is acknowledged first this will + * not result in missing a completion. + * software is responsible for making sure [done] does not overflow; + * for example by insuring there are not more than 2^20-1 instructions in + * flight that may request interrupts. + * + */ +union otx_cptx_vqx_done { + u64 u; + struct otx_cptx_vqx_done_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_20_63:44; + u64 done:20; +#else /* word 0 - little endian */ + u64 done:20; + u64 reserved_20_63:44; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_done_wait + * + * cpt queue done interrupt coalescing wait registers + * specifies the per queue interrupt coalescing settings. + * cptx_vqx_done_wait_s + * word0 + * reserved_48_63:16 [63:48] reserved. + * time_wait:16; [47:32](r/w) time hold-off. when cpt()_vq()_done[done] = 0 + * or cpt()_vq()_done_ack is written a timer is cleared. when the timer + * reaches [time_wait]*1024 then interrupt coalescing ends. + * see cpt()_vq()_done[done]. if 0x0, time coalescing is disabled. + * reserved_20_31:12 [31:20] reserved. + * num_wait:20 [19:0](r/w) number of messages hold-off. + * when cpt()_vq()_done[done] >= [num_wait] then interrupt coalescing ends + * see cpt()_vq()_done[done]. if 0x0, same behavior as 0x1. + * + */ +union otx_cptx_vqx_done_wait { + u64 u; + struct otx_cptx_vqx_done_wait_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_48_63:16; + u64 time_wait:16; + u64 reserved_20_31:12; + u64 num_wait:20; +#else /* word 0 - little endian */ + u64 num_wait:20; + u64 reserved_20_31:12; + u64 time_wait:16; + u64 reserved_48_63:16; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_done_ena_w1s + * + * cpt queue done interrupt enable set registers + * write 1 to these registers will enable the doneint interrupt for the queue. + * cptx_vqx_done_ena_w1s_s + * word0 + * reserved_1_63:63 [63:1] reserved. + * done:1 [0:0](r/w1s/h) write 1 will enable doneint for this queue. + * write 0 has no effect. read will return the enable bit. + */ +union otx_cptx_vqx_done_ena_w1s { + u64 u; + struct otx_cptx_vqx_done_ena_w1s_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_1_63:63; + u64 done:1; +#else /* word 0 - little endian */ + u64 done:1; + u64 reserved_1_63:63; +#endif /* word 0 - end */ + } s; +}; + +/* + * register (ncb) otx_cpt#_vq#_ctl + * + * cpt vf queue control registers + * this register configures queues. this register should be changed (other than + * clearing [ena]) only when quiescent (see cpt()_vq()_inprog[inflight]). + * cptx_vqx_ctl_s + * word0 + * reserved_1_63:63 [63:1] reserved. + * ena:1 [0:0](r/w/h) enables the logical instruction queue. + * see also cpt()_pf_q()_ctl[cont_err] and cpt()_vq()_inprog[inflight]. + * 1 = queue is enabled. + * 0 = queue is disabled. + */ +union otx_cptx_vqx_ctl { + u64 u; + struct otx_cptx_vqx_ctl_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + u64 reserved_1_63:63; + u64 ena:1; +#else /* word 0 - little endian */ + u64 ena:1; + u64 reserved_1_63:63; +#endif /* word 0 - end */ + } s; +}; + +/* + * error address/error codes + * + * in the event of a severe error, microcode writes an 8-byte error code + * value (ecode) to host memory at the rptr address specified by the host + * system (in the 64-byte request). + * + * word0 + * [63:56](r) 8-bit completion code + * [55:48](r) number of the core that reported the severe error + * [47:0] lower 6 bytes of m-inst word2. used to assist in uniquely + * identifying which specific instruction caused the error. this assumes + * that each instruction has a unique result location (rptr), at least + * for a given period of time. + */ +union otx_cpt_error_code { + u64 u; + struct otx_cpt_error_code_s { +#if defined(__big_endian_bitfield) /* word 0 - big endian */ + uint64_t ccode:8; + uint64_t coreid:8; + uint64_t rptr6:48; +#else /* word 0 - little endian */ + uint64_t rptr6:48; + uint64_t coreid:8; + uint64_t ccode:8; +#endif /* word 0 - end */ + } s; +}; + +#endif /*__otx_cpt_hw_types_h */ diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf.h b/drivers/crypto/marvell/octeontx/otx_cptvf.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cptvf_h +#define __otx_cptvf_h + +#include <linux/list.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include "otx_cpt_common.h" +#include "otx_cptvf_reqmgr.h" + +/* flags to indicate the features supported */ +#define otx_cpt_flag_device_ready bit(1) +#define otx_cpt_device_ready(cpt) ((cpt)->flags & otx_cpt_flag_device_ready) +/* default command queue length */ +#define otx_cpt_cmd_qlen (4*2046) +#define otx_cpt_cmd_qchunk_size 1023 +#define otx_cpt_num_qs_per_vf 1 + +struct otx_cpt_cmd_chunk { + u8 *head; + dma_addr_t dma_addr; + u32 size; /* chunk size, max otx_cpt_inst_chunk_max_size */ + struct list_head nextchunk; +}; + +struct otx_cpt_cmd_queue { + u32 idx; /* command queue host write idx */ + u32 num_chunks; /* number of command chunks */ + struct otx_cpt_cmd_chunk *qhead;/* + * command queue head, instructions + * are inserted here + */ + struct otx_cpt_cmd_chunk *base; + struct list_head chead; +}; + +struct otx_cpt_cmd_qinfo { + u32 qchunksize; /* command queue chunk size */ + struct otx_cpt_cmd_queue queue[otx_cpt_num_qs_per_vf]; +}; + +struct otx_cpt_pending_qinfo { + u32 num_queues; /* number of queues supported */ + struct otx_cpt_pending_queue queue[otx_cpt_num_qs_per_vf]; +}; + +#define for_each_pending_queue(qinfo, q, i) \ + for (i = 0, q = &qinfo->queue[i]; i < qinfo->num_queues; i++, \ + q = &qinfo->queue[i]) + +struct otx_cptvf_wqe { + struct tasklet_struct twork; + struct otx_cptvf *cptvf; +}; + +struct otx_cptvf_wqe_info { + struct otx_cptvf_wqe vq_wqe[otx_cpt_num_qs_per_vf]; +}; + +struct otx_cptvf { + u16 flags; /* flags to hold device status bits */ + u8 vfid; /* device index 0...otx_cpt_max_vf_num */ + u8 num_vfs; /* number of enabled vfs */ + u8 vftype; /* vf type of se_type(2) or ae_type(1) */ + u8 vfgrp; /* vf group (0 - 8) */ + u8 node; /* operating node: bits (46:44) in bar0 address */ + u8 priority; /* + * vf priority ring: 1-high proirity round + * robin ring;0-low priority round robin ring; + */ + struct pci_dev *pdev; /* pci device handle */ + void __iomem *reg_base; /* register start address */ + void *wqe_info; /* bh worker info */ + /* msi-x */ + cpumask_var_t affinity_mask[otx_cpt_vf_msix_vectors]; + /* command and pending queues */ + u32 qsize; + u32 num_queues; + struct otx_cpt_cmd_qinfo cqinfo; /* command queue information */ + struct otx_cpt_pending_qinfo pqinfo; /* pending queue information */ + /* vf-pf mailbox communication */ + bool pf_acked; + bool pf_nacked; +}; + +int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf); +int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf); +int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group); +int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf); +int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf); +int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf); +void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf); +void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val); + +#endif /* __otx_cptvf_h */ diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include <crypto/aes.h> +#include <crypto/authenc.h> +#include <crypto/cryptd.h> +#include <crypto/des.h> +#include <crypto/internal/aead.h> +#include <crypto/sha.h> +#include <crypto/xts.h> +#include <crypto/scatterwalk.h> +#include <linux/rtnetlink.h> +#include <linux/sort.h> +#include <linux/module.h> +#include "otx_cptvf.h" +#include "otx_cptvf_algs.h" +#include "otx_cptvf_reqmgr.h" + +#define cpt_max_vf_num 64 +/* size of salt in aes gcm mode */ +#define aes_gcm_salt_size 4 +/* size of iv in aes gcm mode */ +#define aes_gcm_iv_size 8 +/* size of icv (integrity check value) in aes gcm mode */ +#define aes_gcm_icv_size 16 +/* offset of iv in aes gcm mode */ +#define aes_gcm_iv_offset 8 +#define control_word_len 8 +#define key2_offset 48 +#define dma_mode_flag(dma_mode) \ + (((dma_mode) == otx_cpt_dma_gather_scatter) ? (1 << 7) : 0) + +/* truncated sha digest size */ +#define sha1_trunc_digest_size 12 +#define sha256_trunc_digest_size 16 +#define sha384_trunc_digest_size 24 +#define sha512_trunc_digest_size 32 + +static define_mutex(mutex); +static int is_crypto_registered; + +struct cpt_device_desc { + enum otx_cptpf_type pf_type; + struct pci_dev *dev; + int num_queues; +}; + +struct cpt_device_table { + atomic_t count; + struct cpt_device_desc desc[cpt_max_vf_num]; +}; + +static struct cpt_device_table se_devices = { + .count = atomic_init(0) +}; + +static struct cpt_device_table ae_devices = { + .count = atomic_init(0) +}; + +static inline int get_se_device(struct pci_dev **pdev, int *cpu_num) +{ + int count, ret = 0; + + count = atomic_read(&se_devices.count); + if (count < 1) + return -enodev; + + *cpu_num = get_cpu(); + + if (se_devices.desc[0].pf_type == otx_cpt_se) { + /* + * on octeontx platform there is one cpt instruction queue bound + * to each vf. we get maximum performance if one cpt queue + * is available for each cpu otherwise cpt queues need to be + * shared between cpus. + */ + if (*cpu_num >= count) + *cpu_num %= count; + *pdev = se_devices.desc[*cpu_num].dev; + } else { + pr_err("unknown pf type %d ", se_devices.desc[0].pf_type); + ret = -einval; + } + put_cpu(); + + return ret; +} + +static inline int validate_hmac_cipher_null(struct otx_cpt_req_info *cpt_req) +{ + struct otx_cpt_req_ctx *rctx; + struct aead_request *req; + struct crypto_aead *tfm; + + req = container_of(cpt_req->areq, struct aead_request, base); + tfm = crypto_aead_reqtfm(req); + rctx = aead_request_ctx(req); + if (memcmp(rctx->fctx.hmac.s.hmac_calc, + rctx->fctx.hmac.s.hmac_recv, + crypto_aead_authsize(tfm)) != 0) + return -ebadmsg; + + return 0; +} + +static void otx_cpt_aead_callback(int status, void *arg1, void *arg2) +{ + struct otx_cpt_info_buffer *cpt_info = arg2; + struct crypto_async_request *areq = arg1; + struct otx_cpt_req_info *cpt_req; + struct pci_dev *pdev; + + cpt_req = cpt_info->req; + if (!status) { + /* + * when selected cipher is null we need to manually + * verify whether calculated hmac value matches + * received hmac value + */ + if (cpt_req->req_type == otx_cpt_aead_enc_dec_null_req && + !cpt_req->is_enc) + status = validate_hmac_cipher_null(cpt_req); + } + if (cpt_info) { + pdev = cpt_info->pdev; + do_request_cleanup(pdev, cpt_info); + } + if (areq) + areq->complete(areq, status); +} + +static void output_iv_copyback(struct crypto_async_request *areq) +{ + struct otx_cpt_req_info *req_info; + struct skcipher_request *sreq; + struct crypto_skcipher *stfm; + struct otx_cpt_req_ctx *rctx; + struct otx_cpt_enc_ctx *ctx; + u32 start, ivsize; + + sreq = container_of(areq, struct skcipher_request, base); + stfm = crypto_skcipher_reqtfm(sreq); + ctx = crypto_skcipher_ctx(stfm); + if (ctx->cipher_type == otx_cpt_aes_cbc || + ctx->cipher_type == otx_cpt_des3_cbc) { + rctx = skcipher_request_ctx(sreq); + req_info = &rctx->cpt_req; + ivsize = crypto_skcipher_ivsize(stfm); + start = sreq->cryptlen - ivsize; + + if (req_info->is_enc) { + scatterwalk_map_and_copy(sreq->iv, sreq->dst, start, + ivsize, 0); + } else { + if (sreq->src != sreq->dst) { + scatterwalk_map_and_copy(sreq->iv, sreq->src, + start, ivsize, 0); + } else { + memcpy(sreq->iv, req_info->iv_out, ivsize); + kfree(req_info->iv_out); + } + } + } +} + +static void otx_cpt_skcipher_callback(int status, void *arg1, void *arg2) +{ + struct otx_cpt_info_buffer *cpt_info = arg2; + struct crypto_async_request *areq = arg1; + struct pci_dev *pdev; + + if (areq) { + if (!status) + output_iv_copyback(areq); + if (cpt_info) { + pdev = cpt_info->pdev; + do_request_cleanup(pdev, cpt_info); + } + areq->complete(areq, status); + } +} + +static inline void update_input_data(struct otx_cpt_req_info *req_info, + struct scatterlist *inp_sg, + u32 nbytes, u32 *argcnt) +{ + req_info->req.dlen += nbytes; + + while (nbytes) { + u32 len = min(nbytes, inp_sg->length); + u8 *ptr = sg_virt(inp_sg); + + req_info->in[*argcnt].vptr = (void *)ptr; + req_info->in[*argcnt].size = len; + nbytes -= len; + ++(*argcnt); + inp_sg = sg_next(inp_sg); + } +} + +static inline void update_output_data(struct otx_cpt_req_info *req_info, + struct scatterlist *outp_sg, + u32 offset, u32 nbytes, u32 *argcnt) +{ + req_info->rlen += nbytes; + + while (nbytes) { + u32 len = min(nbytes, outp_sg->length - offset); + u8 *ptr = sg_virt(outp_sg); + + req_info->out[*argcnt].vptr = (void *) (ptr + offset); + req_info->out[*argcnt].size = len; + nbytes -= len; + ++(*argcnt); + offset = 0; + outp_sg = sg_next(outp_sg); + } +} + +static inline u32 create_ctx_hdr(struct skcipher_request *req, u32 enc, + u32 *argcnt) +{ + struct crypto_skcipher *stfm = crypto_skcipher_reqtfm(req); + struct otx_cpt_req_ctx *rctx = skcipher_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + struct crypto_tfm *tfm = crypto_skcipher_tfm(stfm); + struct otx_cpt_enc_ctx *ctx = crypto_tfm_ctx(tfm); + struct otx_cpt_fc_ctx *fctx = &rctx->fctx; + int ivsize = crypto_skcipher_ivsize(stfm); + u32 start = req->cryptlen - ivsize; + u64 *ctrl_flags = null; + gfp_t flags; + + flags = (req->base.flags & crypto_tfm_req_may_sleep) ? + gfp_kernel : gfp_atomic; + req_info->ctrl.s.dma_mode = otx_cpt_dma_gather_scatter; + req_info->ctrl.s.se_req = otx_cpt_se_core_req; + + req_info->req.opcode.s.major = otx_cpt_major_op_fc | + dma_mode_flag(otx_cpt_dma_gather_scatter); + if (enc) { + req_info->req.opcode.s.minor = 2; + } else { + req_info->req.opcode.s.minor = 3; + if ((ctx->cipher_type == otx_cpt_aes_cbc || + ctx->cipher_type == otx_cpt_des3_cbc) && + req->src == req->dst) { + req_info->iv_out = kmalloc(ivsize, flags); + if (!req_info->iv_out) + return -enomem; + + scatterwalk_map_and_copy(req_info->iv_out, req->src, + start, ivsize, 0); + } + } + /* encryption data length */ + req_info->req.param1 = req->cryptlen; + /* authentication data length */ + req_info->req.param2 = 0; + + fctx->enc.enc_ctrl.e.enc_cipher = ctx->cipher_type; + fctx->enc.enc_ctrl.e.aes_key = ctx->key_type; + fctx->enc.enc_ctrl.e.iv_source = otx_cpt_from_cptr; + + if (ctx->cipher_type == otx_cpt_aes_xts) + memcpy(fctx->enc.encr_key, ctx->enc_key, ctx->key_len * 2); + else + memcpy(fctx->enc.encr_key, ctx->enc_key, ctx->key_len); + + memcpy(fctx->enc.encr_iv, req->iv, crypto_skcipher_ivsize(stfm)); + + ctrl_flags = (u64 *)&fctx->enc.enc_ctrl.flags; + *ctrl_flags = cpu_to_be64(*ctrl_flags); + + /* + * storing packet data information in offset + * control word first 8 bytes + */ + req_info->in[*argcnt].vptr = (u8 *)&rctx->ctrl_word; + req_info->in[*argcnt].size = control_word_len; + req_info->req.dlen += control_word_len; + ++(*argcnt); + + req_info->in[*argcnt].vptr = (u8 *)fctx; + req_info->in[*argcnt].size = sizeof(struct otx_cpt_fc_ctx); + req_info->req.dlen += sizeof(struct otx_cpt_fc_ctx); + + ++(*argcnt); + + return 0; +} + +static inline u32 create_input_list(struct skcipher_request *req, u32 enc, + u32 enc_iv_len) +{ + struct otx_cpt_req_ctx *rctx = skcipher_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + u32 argcnt = 0; + int ret; + + ret = create_ctx_hdr(req, enc, &argcnt); + if (ret) + return ret; + + update_input_data(req_info, req->src, req->cryptlen, &argcnt); + req_info->incnt = argcnt; + + return 0; +} + +static inline void create_output_list(struct skcipher_request *req, + u32 enc_iv_len) +{ + struct otx_cpt_req_ctx *rctx = skcipher_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + u32 argcnt = 0; + + /* + * output buffer processing + * aes encryption/decryption output would be + * received in the following format + * + * ------iv--------|------encrypted/decrypted data-----| + * [ 16 bytes/ [ request enc/dec/ data len aes cbc ] + */ + update_output_data(req_info, req->dst, 0, req->cryptlen, &argcnt); + req_info->outcnt = argcnt; +} + +static inline int cpt_enc_dec(struct skcipher_request *req, u32 enc) +{ + struct crypto_skcipher *stfm = crypto_skcipher_reqtfm(req); + struct otx_cpt_req_ctx *rctx = skcipher_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + u32 enc_iv_len = crypto_skcipher_ivsize(stfm); + struct pci_dev *pdev; + int status, cpu_num; + + /* validate that request doesn't exceed maximum cpt supported size */ + if (req->cryptlen > otx_cpt_max_req_size) + return -e2big; + + /* clear control words */ + rctx->ctrl_word.flags = 0; + rctx->fctx.enc.enc_ctrl.flags = 0; + + status = create_input_list(req, enc, enc_iv_len); + if (status) + return status; + create_output_list(req, enc_iv_len); + + status = get_se_device(&pdev, &cpu_num); + if (status) + return status; + + req_info->callback = (void *)otx_cpt_skcipher_callback; + req_info->areq = &req->base; + req_info->req_type = otx_cpt_enc_dec_req; + req_info->is_enc = enc; + req_info->is_trunc_hmac = false; + req_info->ctrl.s.grp = 0; + + /* + * we perform an asynchronous send and once + * the request is completed the driver would + * intimate through registered call back functions + */ + status = otx_cpt_do_request(pdev, req_info, cpu_num); + + return status; +} + +static int otx_cpt_skcipher_encrypt(struct skcipher_request *req) +{ + return cpt_enc_dec(req, true); +} + +static int otx_cpt_skcipher_decrypt(struct skcipher_request *req) +{ + return cpt_enc_dec(req, false); +} + +static int otx_cpt_skcipher_xts_setkey(struct crypto_skcipher *tfm, + const u8 *key, u32 keylen) +{ + struct otx_cpt_enc_ctx *ctx = crypto_skcipher_ctx(tfm); + const u8 *key2 = key + (keylen / 2); + const u8 *key1 = key; + int ret; + + ret = xts_check_key(crypto_skcipher_tfm(tfm), key, keylen); + if (ret) + return ret; + ctx->key_len = keylen; + memcpy(ctx->enc_key, key1, keylen / 2); + memcpy(ctx->enc_key + key2_offset, key2, keylen / 2); + ctx->cipher_type = otx_cpt_aes_xts; + switch (ctx->key_len) { + case 2 * aes_keysize_128: + ctx->key_type = otx_cpt_aes_128_bit; + break; + case 2 * aes_keysize_256: + ctx->key_type = otx_cpt_aes_256_bit; + break; + default: + return -einval; + } + + return 0; +} + +static int cpt_des_setkey(struct crypto_skcipher *tfm, const u8 *key, + u32 keylen, u8 cipher_type) +{ + struct otx_cpt_enc_ctx *ctx = crypto_skcipher_ctx(tfm); + + if (keylen != des3_ede_key_size) + return -einval; + + ctx->key_len = keylen; + ctx->cipher_type = cipher_type; + + memcpy(ctx->enc_key, key, keylen); + + return 0; +} + +static int cpt_aes_setkey(struct crypto_skcipher *tfm, const u8 *key, + u32 keylen, u8 cipher_type) +{ + struct otx_cpt_enc_ctx *ctx = crypto_skcipher_ctx(tfm); + + switch (keylen) { + case aes_keysize_128: + ctx->key_type = otx_cpt_aes_128_bit; + break; + case aes_keysize_192: + ctx->key_type = otx_cpt_aes_192_bit; + break; + case aes_keysize_256: + ctx->key_type = otx_cpt_aes_256_bit; + break; + default: + return -einval; + } + ctx->key_len = keylen; + ctx->cipher_type = cipher_type; + + memcpy(ctx->enc_key, key, keylen); + + return 0; +} + +static int otx_cpt_skcipher_cbc_aes_setkey(struct crypto_skcipher *tfm, + const u8 *key, u32 keylen) +{ + return cpt_aes_setkey(tfm, key, keylen, otx_cpt_aes_cbc); +} + +static int otx_cpt_skcipher_ecb_aes_setkey(struct crypto_skcipher *tfm, + const u8 *key, u32 keylen) +{ + return cpt_aes_setkey(tfm, key, keylen, otx_cpt_aes_ecb); +} + +static int otx_cpt_skcipher_cfb_aes_setkey(struct crypto_skcipher *tfm, + const u8 *key, u32 keylen) +{ + return cpt_aes_setkey(tfm, key, keylen, otx_cpt_aes_cfb); +} + +static int otx_cpt_skcipher_cbc_des3_setkey(struct crypto_skcipher *tfm, + const u8 *key, u32 keylen) +{ + return cpt_des_setkey(tfm, key, keylen, otx_cpt_des3_cbc); +} + +static int otx_cpt_skcipher_ecb_des3_setkey(struct crypto_skcipher *tfm, + const u8 *key, u32 keylen) +{ + return cpt_des_setkey(tfm, key, keylen, otx_cpt_des3_ecb); +} + +static int otx_cpt_enc_dec_init(struct crypto_skcipher *tfm) +{ + struct otx_cpt_enc_ctx *ctx = crypto_skcipher_ctx(tfm); + + memset(ctx, 0, sizeof(*ctx)); + /* + * additional memory for skcipher_request is + * allocated since the cryptd daemon uses + * this memory for request_ctx information + */ + crypto_skcipher_set_reqsize(tfm, sizeof(struct otx_cpt_req_ctx) + + sizeof(struct skcipher_request)); + + return 0; +} + +static int cpt_aead_init(struct crypto_aead *tfm, u8 cipher_type, u8 mac_type) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(tfm); + + ctx->cipher_type = cipher_type; + ctx->mac_type = mac_type; + + /* + * when selected cipher is null we use hmac opcode instead of + * flexicrypto opcode therefore we don't need to use hash algorithms + * for calculating ipad and opad + */ + if (ctx->cipher_type != otx_cpt_cipher_null) { + switch (ctx->mac_type) { + case otx_cpt_sha1: + ctx->hashalg = crypto_alloc_shash("sha1", 0, + crypto_alg_async); + if (is_err(ctx->hashalg)) + return ptr_err(ctx->hashalg); + break; + + case otx_cpt_sha256: + ctx->hashalg = crypto_alloc_shash("sha256", 0, + crypto_alg_async); + if (is_err(ctx->hashalg)) + return ptr_err(ctx->hashalg); + break; + + case otx_cpt_sha384: + ctx->hashalg = crypto_alloc_shash("sha384", 0, + crypto_alg_async); + if (is_err(ctx->hashalg)) + return ptr_err(ctx->hashalg); + break; + + case otx_cpt_sha512: + ctx->hashalg = crypto_alloc_shash("sha512", 0, + crypto_alg_async); + if (is_err(ctx->hashalg)) + return ptr_err(ctx->hashalg); + break; + } + } + + crypto_aead_set_reqsize(tfm, sizeof(struct otx_cpt_req_ctx)); + + return 0; +} + +static int otx_cpt_aead_cbc_aes_sha1_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_aes_cbc, otx_cpt_sha1); +} + +static int otx_cpt_aead_cbc_aes_sha256_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_aes_cbc, otx_cpt_sha256); +} + +static int otx_cpt_aead_cbc_aes_sha384_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_aes_cbc, otx_cpt_sha384); +} + +static int otx_cpt_aead_cbc_aes_sha512_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_aes_cbc, otx_cpt_sha512); +} + +static int otx_cpt_aead_ecb_null_sha1_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_cipher_null, otx_cpt_sha1); +} + +static int otx_cpt_aead_ecb_null_sha256_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_cipher_null, otx_cpt_sha256); +} + +static int otx_cpt_aead_ecb_null_sha384_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_cipher_null, otx_cpt_sha384); +} + +static int otx_cpt_aead_ecb_null_sha512_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_cipher_null, otx_cpt_sha512); +} + +static int otx_cpt_aead_gcm_aes_init(struct crypto_aead *tfm) +{ + return cpt_aead_init(tfm, otx_cpt_aes_gcm, otx_cpt_mac_null); +} + +static void otx_cpt_aead_exit(struct crypto_aead *tfm) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(tfm); + + kfree(ctx->ipad); + kfree(ctx->opad); + if (ctx->hashalg) + crypto_free_shash(ctx->hashalg); + kfree(ctx->sdesc); +} + +/* + * this is the integrity check value validation (aka the authentication tag + * length) + */ +static int otx_cpt_aead_set_authsize(struct crypto_aead *tfm, + unsigned int authsize) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(tfm); + + switch (ctx->mac_type) { + case otx_cpt_sha1: + if (authsize != sha1_digest_size && + authsize != sha1_trunc_digest_size) + return -einval; + + if (authsize == sha1_trunc_digest_size) + ctx->is_trunc_hmac = true; + break; + + case otx_cpt_sha256: + if (authsize != sha256_digest_size && + authsize != sha256_trunc_digest_size) + return -einval; + + if (authsize == sha256_trunc_digest_size) + ctx->is_trunc_hmac = true; + break; + + case otx_cpt_sha384: + if (authsize != sha384_digest_size && + authsize != sha384_trunc_digest_size) + return -einval; + + if (authsize == sha384_trunc_digest_size) + ctx->is_trunc_hmac = true; + break; + + case otx_cpt_sha512: + if (authsize != sha512_digest_size && + authsize != sha512_trunc_digest_size) + return -einval; + + if (authsize == sha512_trunc_digest_size) + ctx->is_trunc_hmac = true; + break; + + case otx_cpt_mac_null: + if (ctx->cipher_type == otx_cpt_aes_gcm) { + if (authsize != aes_gcm_icv_size) + return -einval; + } else + return -einval; + break; + + default: + return -einval; + } + + tfm->authsize = authsize; + return 0; +} + +static struct otx_cpt_sdesc *alloc_sdesc(struct crypto_shash *alg) +{ + struct otx_cpt_sdesc *sdesc; + int size; + + size = sizeof(struct shash_desc) + crypto_shash_descsize(alg); + sdesc = kmalloc(size, gfp_kernel); + if (!sdesc) + return null; + + sdesc->shash.tfm = alg; + + return sdesc; +} + +static inline void swap_data32(void *buf, u32 len) +{ + u32 *store = (u32 *) buf; + int i = 0; + + for (i = 0 ; i < len/sizeof(u32); i++, store++) + *store = cpu_to_be32(*store); +} + +static inline void swap_data64(void *buf, u32 len) +{ + u64 *store = (u64 *) buf; + int i = 0; + + for (i = 0 ; i < len/sizeof(u64); i++, store++) + *store = cpu_to_be64(*store); +} + +static int copy_pad(u8 mac_type, u8 *out_pad, u8 *in_pad) +{ + struct sha512_state *sha512; + struct sha256_state *sha256; + struct sha1_state *sha1; + + switch (mac_type) { + case otx_cpt_sha1: + sha1 = (struct sha1_state *) in_pad; + swap_data32(sha1->state, sha1_digest_size); + memcpy(out_pad, &sha1->state, sha1_digest_size); + break; + + case otx_cpt_sha256: + sha256 = (struct sha256_state *) in_pad; + swap_data32(sha256->state, sha256_digest_size); + memcpy(out_pad, &sha256->state, sha256_digest_size); + break; + + case otx_cpt_sha384: + case otx_cpt_sha512: + sha512 = (struct sha512_state *) in_pad; + swap_data64(sha512->state, sha512_digest_size); + memcpy(out_pad, &sha512->state, sha512_digest_size); + break; + + default: + return -einval; + } + + return 0; +} + +static int aead_hmac_init(struct crypto_aead *cipher) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(cipher); + int state_size = crypto_shash_statesize(ctx->hashalg); + int ds = crypto_shash_digestsize(ctx->hashalg); + int bs = crypto_shash_blocksize(ctx->hashalg); + int authkeylen = ctx->auth_key_len; + u8 *ipad = null, *opad = null; + int ret = 0, icount = 0; + + ctx->sdesc = alloc_sdesc(ctx->hashalg); + if (!ctx->sdesc) + return -enomem; + + ctx->ipad = kzalloc(bs, gfp_kernel); + if (!ctx->ipad) { + ret = -enomem; + goto calc_fail; + } + + ctx->opad = kzalloc(bs, gfp_kernel); + if (!ctx->opad) { + ret = -enomem; + goto calc_fail; + } + + ipad = kzalloc(state_size, gfp_kernel); + if (!ipad) { + ret = -enomem; + goto calc_fail; + } + + opad = kzalloc(state_size, gfp_kernel); + if (!opad) { + ret = -enomem; + goto calc_fail; + } + + if (authkeylen > bs) { + ret = crypto_shash_digest(&ctx->sdesc->shash, ctx->key, + authkeylen, ipad); + if (ret) + goto calc_fail; + + authkeylen = ds; + } else { + memcpy(ipad, ctx->key, authkeylen); + } + + memset(ipad + authkeylen, 0, bs - authkeylen); + memcpy(opad, ipad, bs); + + for (icount = 0; icount < bs; icount++) { + ipad[icount] ^= 0x36; + opad[icount] ^= 0x5c; + } + + /* + * partial hash calculated from the software + * algorithm is retrieved for ipad & opad + */ + + /* ipad calculation */ + crypto_shash_init(&ctx->sdesc->shash); + crypto_shash_update(&ctx->sdesc->shash, ipad, bs); + crypto_shash_export(&ctx->sdesc->shash, ipad); + ret = copy_pad(ctx->mac_type, ctx->ipad, ipad); + if (ret) + goto calc_fail; + + /* opad calculation */ + crypto_shash_init(&ctx->sdesc->shash); + crypto_shash_update(&ctx->sdesc->shash, opad, bs); + crypto_shash_export(&ctx->sdesc->shash, opad); + ret = copy_pad(ctx->mac_type, ctx->opad, opad); + if (ret) + goto calc_fail; + + kfree(ipad); + kfree(opad); + + return 0; + +calc_fail: + kfree(ctx->ipad); + ctx->ipad = null; + kfree(ctx->opad); + ctx->opad = null; + kfree(ipad); + kfree(opad); + kfree(ctx->sdesc); + ctx->sdesc = null; + + return ret; +} + +static int otx_cpt_aead_cbc_aes_sha_setkey(struct crypto_aead *cipher, + const unsigned char *key, + unsigned int keylen) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(cipher); + struct crypto_authenc_key_param *param; + int enckeylen = 0, authkeylen = 0; + struct rtattr *rta = (void *)key; + int status = -einval; + + if (!rta_ok(rta, keylen)) + goto badkey; + + if (rta->rta_type != crypto_authenc_keya_param) + goto badkey; + + if (rta_payload(rta) < sizeof(*param)) + goto badkey; + + param = rta_data(rta); + enckeylen = be32_to_cpu(param->enckeylen); + key += rta_align(rta->rta_len); + keylen -= rta_align(rta->rta_len); + if (keylen < enckeylen) + goto badkey; + + if (keylen > otx_cpt_max_key_size) + goto badkey; + + authkeylen = keylen - enckeylen; + memcpy(ctx->key, key, keylen); + + switch (enckeylen) { + case aes_keysize_128: + ctx->key_type = otx_cpt_aes_128_bit; + break; + case aes_keysize_192: + ctx->key_type = otx_cpt_aes_192_bit; + break; + case aes_keysize_256: + ctx->key_type = otx_cpt_aes_256_bit; + break; + default: + /* invalid key length */ + goto badkey; + } + + ctx->enc_key_len = enckeylen; + ctx->auth_key_len = authkeylen; + + status = aead_hmac_init(cipher); + if (status) + goto badkey; + + return 0; +badkey: + return status; +} + +static int otx_cpt_aead_ecb_null_sha_setkey(struct crypto_aead *cipher, + const unsigned char *key, + unsigned int keylen) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(cipher); + struct crypto_authenc_key_param *param; + struct rtattr *rta = (void *)key; + int enckeylen = 0; + + if (!rta_ok(rta, keylen)) + goto badkey; + + if (rta->rta_type != crypto_authenc_keya_param) + goto badkey; + + if (rta_payload(rta) < sizeof(*param)) + goto badkey; + + param = rta_data(rta); + enckeylen = be32_to_cpu(param->enckeylen); + key += rta_align(rta->rta_len); + keylen -= rta_align(rta->rta_len); + if (enckeylen != 0) + goto badkey; + + if (keylen > otx_cpt_max_key_size) + goto badkey; + + memcpy(ctx->key, key, keylen); + ctx->enc_key_len = enckeylen; + ctx->auth_key_len = keylen; + return 0; +badkey: + return -einval; +} + +static int otx_cpt_aead_gcm_aes_setkey(struct crypto_aead *cipher, + const unsigned char *key, + unsigned int keylen) +{ + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(cipher); + + /* + * for aes gcm we expect to get encryption key (16, 24, 32 bytes) + * and salt (4 bytes) + */ + switch (keylen) { + case aes_keysize_128 + aes_gcm_salt_size: + ctx->key_type = otx_cpt_aes_128_bit; + ctx->enc_key_len = aes_keysize_128; + break; + case aes_keysize_192 + aes_gcm_salt_size: + ctx->key_type = otx_cpt_aes_192_bit; + ctx->enc_key_len = aes_keysize_192; + break; + case aes_keysize_256 + aes_gcm_salt_size: + ctx->key_type = otx_cpt_aes_256_bit; + ctx->enc_key_len = aes_keysize_256; + break; + default: + /* invalid key and salt length */ + return -einval; + } + + /* store encryption key and salt */ + memcpy(ctx->key, key, keylen); + + return 0; +} + +static inline u32 create_aead_ctx_hdr(struct aead_request *req, u32 enc, + u32 *argcnt) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct crypto_aead *tfm = crypto_aead_reqtfm(req); + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(tfm); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + struct otx_cpt_fc_ctx *fctx = &rctx->fctx; + int mac_len = crypto_aead_authsize(tfm); + int ds; + + rctx->ctrl_word.e.enc_data_offset = req->assoclen; + + switch (ctx->cipher_type) { + case otx_cpt_aes_cbc: + fctx->enc.enc_ctrl.e.iv_source = otx_cpt_from_cptr; + /* copy encryption key to context */ + memcpy(fctx->enc.encr_key, ctx->key + ctx->auth_key_len, + ctx->enc_key_len); + /* copy iv to context */ + memcpy(fctx->enc.encr_iv, req->iv, crypto_aead_ivsize(tfm)); + + ds = crypto_shash_digestsize(ctx->hashalg); + if (ctx->mac_type == otx_cpt_sha384) + ds = sha512_digest_size; + if (ctx->ipad) + memcpy(fctx->hmac.e.ipad, ctx->ipad, ds); + if (ctx->opad) + memcpy(fctx->hmac.e.opad, ctx->opad, ds); + break; + + case otx_cpt_aes_gcm: + fctx->enc.enc_ctrl.e.iv_source = otx_cpt_from_dptr; + /* copy encryption key to context */ + memcpy(fctx->enc.encr_key, ctx->key, ctx->enc_key_len); + /* copy salt to context */ + memcpy(fctx->enc.encr_iv, ctx->key + ctx->enc_key_len, + aes_gcm_salt_size); + + rctx->ctrl_word.e.iv_offset = req->assoclen - aes_gcm_iv_offset; + break; + + default: + /* unknown cipher type */ + return -einval; + } + rctx->ctrl_word.flags = cpu_to_be64(rctx->ctrl_word.flags); + + req_info->ctrl.s.dma_mode = otx_cpt_dma_gather_scatter; + req_info->ctrl.s.se_req = otx_cpt_se_core_req; + req_info->req.opcode.s.major = otx_cpt_major_op_fc | + dma_mode_flag(otx_cpt_dma_gather_scatter); + if (enc) { + req_info->req.opcode.s.minor = 2; + req_info->req.param1 = req->cryptlen; + req_info->req.param2 = req->cryptlen + req->assoclen; + } else { + req_info->req.opcode.s.minor = 3; + req_info->req.param1 = req->cryptlen - mac_len; + req_info->req.param2 = req->cryptlen + req->assoclen - mac_len; + } + + fctx->enc.enc_ctrl.e.enc_cipher = ctx->cipher_type; + fctx->enc.enc_ctrl.e.aes_key = ctx->key_type; + fctx->enc.enc_ctrl.e.mac_type = ctx->mac_type; + fctx->enc.enc_ctrl.e.mac_len = mac_len; + fctx->enc.enc_ctrl.flags = cpu_to_be64(fctx->enc.enc_ctrl.flags); + + /* + * storing packet data information in offset + * control word first 8 bytes + */ + req_info->in[*argcnt].vptr = (u8 *)&rctx->ctrl_word; + req_info->in[*argcnt].size = control_word_len; + req_info->req.dlen += control_word_len; + ++(*argcnt); + + req_info->in[*argcnt].vptr = (u8 *)fctx; + req_info->in[*argcnt].size = sizeof(struct otx_cpt_fc_ctx); + req_info->req.dlen += sizeof(struct otx_cpt_fc_ctx); + ++(*argcnt); + + return 0; +} + +static inline u32 create_hmac_ctx_hdr(struct aead_request *req, u32 *argcnt, + u32 enc) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct crypto_aead *tfm = crypto_aead_reqtfm(req); + struct otx_cpt_aead_ctx *ctx = crypto_aead_ctx(tfm); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + + req_info->ctrl.s.dma_mode = otx_cpt_dma_gather_scatter; + req_info->ctrl.s.se_req = otx_cpt_se_core_req; + req_info->req.opcode.s.major = otx_cpt_major_op_hmac | + dma_mode_flag(otx_cpt_dma_gather_scatter); + req_info->is_trunc_hmac = ctx->is_trunc_hmac; + + req_info->req.opcode.s.minor = 0; + req_info->req.param1 = ctx->auth_key_len; + req_info->req.param2 = ctx->mac_type << 8; + + /* add authentication key */ + req_info->in[*argcnt].vptr = ctx->key; + req_info->in[*argcnt].size = round_up(ctx->auth_key_len, 8); + req_info->req.dlen += round_up(ctx->auth_key_len, 8); + ++(*argcnt); + + return 0; +} + +static inline u32 create_aead_input_list(struct aead_request *req, u32 enc) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + u32 inputlen = req->cryptlen + req->assoclen; + u32 status, argcnt = 0; + + status = create_aead_ctx_hdr(req, enc, &argcnt); + if (status) + return status; + update_input_data(req_info, req->src, inputlen, &argcnt); + req_info->incnt = argcnt; + + return 0; +} + +static inline u32 create_aead_output_list(struct aead_request *req, u32 enc, + u32 mac_len) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + u32 argcnt = 0, outputlen = 0; + + if (enc) + outputlen = req->cryptlen + req->assoclen + mac_len; + else + outputlen = req->cryptlen + req->assoclen - mac_len; + + update_output_data(req_info, req->dst, 0, outputlen, &argcnt); + req_info->outcnt = argcnt; + + return 0; +} + +static inline u32 create_aead_null_input_list(struct aead_request *req, + u32 enc, u32 mac_len) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + u32 inputlen, argcnt = 0; + + if (enc) + inputlen = req->cryptlen + req->assoclen; + else + inputlen = req->cryptlen + req->assoclen - mac_len; + + create_hmac_ctx_hdr(req, &argcnt, enc); + update_input_data(req_info, req->src, inputlen, &argcnt); + req_info->incnt = argcnt; + + return 0; +} + +static inline u32 create_aead_null_output_list(struct aead_request *req, + u32 enc, u32 mac_len) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + struct scatterlist *dst; + u8 *ptr = null; + int argcnt = 0, status, offset; + u32 inputlen; + + if (enc) + inputlen = req->cryptlen + req->assoclen; + else + inputlen = req->cryptlen + req->assoclen - mac_len; + + /* + * if source and destination are different + * then copy payload to destination + */ + if (req->src != req->dst) { + + ptr = kmalloc(inputlen, (req_info->areq->flags & + crypto_tfm_req_may_sleep) ? + gfp_kernel : gfp_atomic); + if (!ptr) { + status = -enomem; + goto error; + } + + status = sg_copy_to_buffer(req->src, sg_nents(req->src), ptr, + inputlen); + if (status != inputlen) { + status = -einval; + goto error; + } + status = sg_copy_from_buffer(req->dst, sg_nents(req->dst), ptr, + inputlen); + if (status != inputlen) { + status = -einval; + goto error; + } + kfree(ptr); + } + + if (enc) { + /* + * in an encryption scenario hmac needs + * to be appended after payload + */ + dst = req->dst; + offset = inputlen; + while (offset >= dst->length) { + offset -= dst->length; + dst = sg_next(dst); + if (!dst) { + status = -enoent; + goto error; + } + } + + update_output_data(req_info, dst, offset, mac_len, &argcnt); + } else { + /* + * in a decryption scenario calculated hmac for received + * payload needs to be compare with hmac received + */ + status = sg_copy_buffer(req->src, sg_nents(req->src), + rctx->fctx.hmac.s.hmac_recv, mac_len, + inputlen, true); + if (status != mac_len) { + status = -einval; + goto error; + } + + req_info->out[argcnt].vptr = rctx->fctx.hmac.s.hmac_calc; + req_info->out[argcnt].size = mac_len; + argcnt++; + } + + req_info->outcnt = argcnt; + return 0; +error: + kfree(ptr); + return status; +} + +static u32 cpt_aead_enc_dec(struct aead_request *req, u8 reg_type, u8 enc) +{ + struct otx_cpt_req_ctx *rctx = aead_request_ctx(req); + struct otx_cpt_req_info *req_info = &rctx->cpt_req; + struct crypto_aead *tfm = crypto_aead_reqtfm(req); + struct pci_dev *pdev; + u32 status, cpu_num; + + /* clear control words */ + rctx->ctrl_word.flags = 0; + rctx->fctx.enc.enc_ctrl.flags = 0; + + req_info->callback = otx_cpt_aead_callback; + req_info->areq = &req->base; + req_info->req_type = reg_type; + req_info->is_enc = enc; + req_info->is_trunc_hmac = false; + + switch (reg_type) { + case otx_cpt_aead_enc_dec_req: + status = create_aead_input_list(req, enc); + if (status) + return status; + status = create_aead_output_list(req, enc, + crypto_aead_authsize(tfm)); + if (status) + return status; + break; + + case otx_cpt_aead_enc_dec_null_req: + status = create_aead_null_input_list(req, enc, + crypto_aead_authsize(tfm)); + if (status) + return status; + status = create_aead_null_output_list(req, enc, + crypto_aead_authsize(tfm)); + if (status) + return status; + break; + + default: + return -einval; + } + + /* validate that request doesn't exceed maximum cpt supported size */ + if (req_info->req.param1 > otx_cpt_max_req_size || + req_info->req.param2 > otx_cpt_max_req_size) + return -e2big; + + status = get_se_device(&pdev, &cpu_num); + if (status) + return status; + + req_info->ctrl.s.grp = 0; + + status = otx_cpt_do_request(pdev, req_info, cpu_num); + /* + * we perform an asynchronous send and once + * the request is completed the driver would + * intimate through registered call back functions + */ + return status; +} + +static int otx_cpt_aead_encrypt(struct aead_request *req) +{ + return cpt_aead_enc_dec(req, otx_cpt_aead_enc_dec_req, true); +} + +static int otx_cpt_aead_decrypt(struct aead_request *req) +{ + return cpt_aead_enc_dec(req, otx_cpt_aead_enc_dec_req, false); +} + +static int otx_cpt_aead_null_encrypt(struct aead_request *req) +{ + return cpt_aead_enc_dec(req, otx_cpt_aead_enc_dec_null_req, true); +} + +static int otx_cpt_aead_null_decrypt(struct aead_request *req) +{ + return cpt_aead_enc_dec(req, otx_cpt_aead_enc_dec_null_req, false); +} + +static struct skcipher_alg otx_cpt_skciphers[] = { { + .base.cra_name = "xts(aes)", + .base.cra_driver_name = "cpt_xts_aes", + .base.cra_flags = crypto_alg_async, + .base.cra_blocksize = aes_block_size, + .base.cra_ctxsize = sizeof(struct otx_cpt_enc_ctx), + .base.cra_alignmask = 7, + .base.cra_priority = 4001, + .base.cra_module = this_module, + + .init = otx_cpt_enc_dec_init, + .ivsize = aes_block_size, + .min_keysize = 2 * aes_min_key_size, + .max_keysize = 2 * aes_max_key_size, + .setkey = otx_cpt_skcipher_xts_setkey, + .encrypt = otx_cpt_skcipher_encrypt, + .decrypt = otx_cpt_skcipher_decrypt, +}, { + .base.cra_name = "cbc(aes)", + .base.cra_driver_name = "cpt_cbc_aes", + .base.cra_flags = crypto_alg_async, + .base.cra_blocksize = aes_block_size, + .base.cra_ctxsize = sizeof(struct otx_cpt_enc_ctx), + .base.cra_alignmask = 7, + .base.cra_priority = 4001, + .base.cra_module = this_module, + + .init = otx_cpt_enc_dec_init, + .ivsize = aes_block_size, + .min_keysize = aes_min_key_size, + .max_keysize = aes_max_key_size, + .setkey = otx_cpt_skcipher_cbc_aes_setkey, + .encrypt = otx_cpt_skcipher_encrypt, + .decrypt = otx_cpt_skcipher_decrypt, +}, { + .base.cra_name = "ecb(aes)", + .base.cra_driver_name = "cpt_ecb_aes", + .base.cra_flags = crypto_alg_async, + .base.cra_blocksize = aes_block_size, + .base.cra_ctxsize = sizeof(struct otx_cpt_enc_ctx), + .base.cra_alignmask = 7, + .base.cra_priority = 4001, + .base.cra_module = this_module, + + .init = otx_cpt_enc_dec_init, + .ivsize = 0, + .min_keysize = aes_min_key_size, + .max_keysize = aes_max_key_size, + .setkey = otx_cpt_skcipher_ecb_aes_setkey, + .encrypt = otx_cpt_skcipher_encrypt, + .decrypt = otx_cpt_skcipher_decrypt, +}, { + .base.cra_name = "cfb(aes)", + .base.cra_driver_name = "cpt_cfb_aes", + .base.cra_flags = crypto_alg_async, + .base.cra_blocksize = aes_block_size, + .base.cra_ctxsize = sizeof(struct otx_cpt_enc_ctx), + .base.cra_alignmask = 7, + .base.cra_priority = 4001, + .base.cra_module = this_module, + + .init = otx_cpt_enc_dec_init, + .ivsize = aes_block_size, + .min_keysize = aes_min_key_size, + .max_keysize = aes_max_key_size, + .setkey = otx_cpt_skcipher_cfb_aes_setkey, + .encrypt = otx_cpt_skcipher_encrypt, + .decrypt = otx_cpt_skcipher_decrypt, +}, { + .base.cra_name = "cbc(des3_ede)", + .base.cra_driver_name = "cpt_cbc_des3_ede", + .base.cra_flags = crypto_alg_async, + .base.cra_blocksize = des3_ede_block_size, + .base.cra_ctxsize = sizeof(struct otx_cpt_des3_ctx), + .base.cra_alignmask = 7, + .base.cra_priority = 4001, + .base.cra_module = this_module, + + .init = otx_cpt_enc_dec_init, + .min_keysize = des3_ede_key_size, + .max_keysize = des3_ede_key_size, + .ivsize = des_block_size, + .setkey = otx_cpt_skcipher_cbc_des3_setkey, + .encrypt = otx_cpt_skcipher_encrypt, + .decrypt = otx_cpt_skcipher_decrypt, +}, { + .base.cra_name = "ecb(des3_ede)", + .base.cra_driver_name = "cpt_ecb_des3_ede", + .base.cra_flags = crypto_alg_async, + .base.cra_blocksize = des3_ede_block_size, + .base.cra_ctxsize = sizeof(struct otx_cpt_des3_ctx), + .base.cra_alignmask = 7, + .base.cra_priority = 4001, + .base.cra_module = this_module, + + .init = otx_cpt_enc_dec_init, + .min_keysize = des3_ede_key_size, + .max_keysize = des3_ede_key_size, + .ivsize = 0, + .setkey = otx_cpt_skcipher_ecb_des3_setkey, + .encrypt = otx_cpt_skcipher_encrypt, + .decrypt = otx_cpt_skcipher_decrypt, +} }; + +static struct aead_alg otx_cpt_aeads[] = { { + .base = { + .cra_name = "authenc(hmac(sha1),cbc(aes))", + .cra_driver_name = "cpt_hmac_sha1_cbc_aes", + .cra_blocksize = aes_block_size, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_cbc_aes_sha1_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_cbc_aes_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_encrypt, + .decrypt = otx_cpt_aead_decrypt, + .ivsize = aes_block_size, + .maxauthsize = sha1_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha256),cbc(aes))", + .cra_driver_name = "cpt_hmac_sha256_cbc_aes", + .cra_blocksize = aes_block_size, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_cbc_aes_sha256_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_cbc_aes_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_encrypt, + .decrypt = otx_cpt_aead_decrypt, + .ivsize = aes_block_size, + .maxauthsize = sha256_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha384),cbc(aes))", + .cra_driver_name = "cpt_hmac_sha384_cbc_aes", + .cra_blocksize = aes_block_size, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_cbc_aes_sha384_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_cbc_aes_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_encrypt, + .decrypt = otx_cpt_aead_decrypt, + .ivsize = aes_block_size, + .maxauthsize = sha384_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha512),cbc(aes))", + .cra_driver_name = "cpt_hmac_sha512_cbc_aes", + .cra_blocksize = aes_block_size, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_cbc_aes_sha512_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_cbc_aes_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_encrypt, + .decrypt = otx_cpt_aead_decrypt, + .ivsize = aes_block_size, + .maxauthsize = sha512_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha1),ecb(cipher_null))", + .cra_driver_name = "cpt_hmac_sha1_ecb_null", + .cra_blocksize = 1, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_ecb_null_sha1_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_ecb_null_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_null_encrypt, + .decrypt = otx_cpt_aead_null_decrypt, + .ivsize = 0, + .maxauthsize = sha1_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha256),ecb(cipher_null))", + .cra_driver_name = "cpt_hmac_sha256_ecb_null", + .cra_blocksize = 1, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_ecb_null_sha256_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_ecb_null_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_null_encrypt, + .decrypt = otx_cpt_aead_null_decrypt, + .ivsize = 0, + .maxauthsize = sha256_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha384),ecb(cipher_null))", + .cra_driver_name = "cpt_hmac_sha384_ecb_null", + .cra_blocksize = 1, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_ecb_null_sha384_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_ecb_null_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_null_encrypt, + .decrypt = otx_cpt_aead_null_decrypt, + .ivsize = 0, + .maxauthsize = sha384_digest_size, +}, { + .base = { + .cra_name = "authenc(hmac(sha512),ecb(cipher_null))", + .cra_driver_name = "cpt_hmac_sha512_ecb_null", + .cra_blocksize = 1, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_ecb_null_sha512_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_ecb_null_sha_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_null_encrypt, + .decrypt = otx_cpt_aead_null_decrypt, + .ivsize = 0, + .maxauthsize = sha512_digest_size, +}, { + .base = { + .cra_name = "rfc4106(gcm(aes))", + .cra_driver_name = "cpt_rfc4106_gcm_aes", + .cra_blocksize = 1, + .cra_flags = crypto_alg_async, + .cra_ctxsize = sizeof(struct otx_cpt_aead_ctx), + .cra_priority = 4001, + .cra_alignmask = 0, + .cra_module = this_module, + }, + .init = otx_cpt_aead_gcm_aes_init, + .exit = otx_cpt_aead_exit, + .setkey = otx_cpt_aead_gcm_aes_setkey, + .setauthsize = otx_cpt_aead_set_authsize, + .encrypt = otx_cpt_aead_encrypt, + .decrypt = otx_cpt_aead_decrypt, + .ivsize = aes_gcm_iv_size, + .maxauthsize = aes_gcm_icv_size, +} }; + +static inline int is_any_alg_used(void) +{ + int i; + + for (i = 0; i < array_size(otx_cpt_skciphers); i++) + if (refcount_read(&otx_cpt_skciphers[i].base.cra_refcnt) != 1) + return true; + for (i = 0; i < array_size(otx_cpt_aeads); i++) + if (refcount_read(&otx_cpt_aeads[i].base.cra_refcnt) != 1) + return true; + return false; +} + +static inline int cpt_register_algs(void) +{ + int i, err = 0; + + if (!is_enabled(config_dm_crypt)) { + for (i = 0; i < array_size(otx_cpt_skciphers); i++) + otx_cpt_skciphers[i].base.cra_flags &= ~crypto_alg_dead; + + err = crypto_register_skciphers(otx_cpt_skciphers, + array_size(otx_cpt_skciphers)); + if (err) + return err; + } + + for (i = 0; i < array_size(otx_cpt_aeads); i++) + otx_cpt_aeads[i].base.cra_flags &= ~crypto_alg_dead; + + err = crypto_register_aeads(otx_cpt_aeads, array_size(otx_cpt_aeads)); + if (err) { + crypto_unregister_skciphers(otx_cpt_skciphers, + array_size(otx_cpt_skciphers)); + return err; + } + + return 0; +} + +static inline void cpt_unregister_algs(void) +{ + crypto_unregister_skciphers(otx_cpt_skciphers, + array_size(otx_cpt_skciphers)); + crypto_unregister_aeads(otx_cpt_aeads, array_size(otx_cpt_aeads)); +} + +static int compare_func(const void *lptr, const void *rptr) +{ + struct cpt_device_desc *ldesc = (struct cpt_device_desc *) lptr; + struct cpt_device_desc *rdesc = (struct cpt_device_desc *) rptr; + + if (ldesc->dev->devfn < rdesc->dev->devfn) + return -1; + if (ldesc->dev->devfn > rdesc->dev->devfn) + return 1; + return 0; +} + +static void swap_func(void *lptr, void *rptr, int size) +{ + struct cpt_device_desc *ldesc = (struct cpt_device_desc *) lptr; + struct cpt_device_desc *rdesc = (struct cpt_device_desc *) rptr; + struct cpt_device_desc desc; + + desc = *ldesc; + *ldesc = *rdesc; + *rdesc = desc; +} + +int otx_cpt_crypto_init(struct pci_dev *pdev, struct module *mod, + enum otx_cptpf_type pf_type, + enum otx_cptvf_type engine_type, + int num_queues, int num_devices) +{ + int ret = 0; + int count; + + mutex_lock(&mutex); + switch (engine_type) { + case otx_cpt_se_types: + count = atomic_read(&se_devices.count); + if (count >= cpt_max_vf_num) { + dev_err(&pdev->dev, "no space to add a new device"); + ret = -enospc; + goto err; + } + se_devices.desc[count].pf_type = pf_type; + se_devices.desc[count].num_queues = num_queues; + se_devices.desc[count++].dev = pdev; + atomic_inc(&se_devices.count); + + if (atomic_read(&se_devices.count) == num_devices && + is_crypto_registered == false) { + if (cpt_register_algs()) { + dev_err(&pdev->dev, + "error in registering crypto algorithms "); + ret = -einval; + goto err; + } + try_module_get(mod); + is_crypto_registered = true; + } + sort(se_devices.desc, count, sizeof(struct cpt_device_desc), + compare_func, swap_func); + break; + + case otx_cpt_ae_types: + count = atomic_read(&ae_devices.count); + if (count >= cpt_max_vf_num) { + dev_err(&pdev->dev, "no space to a add new device"); + ret = -enospc; + goto err; + } + ae_devices.desc[count].pf_type = pf_type; + ae_devices.desc[count].num_queues = num_queues; + ae_devices.desc[count++].dev = pdev; + atomic_inc(&ae_devices.count); + sort(ae_devices.desc, count, sizeof(struct cpt_device_desc), + compare_func, swap_func); + break; + + default: + dev_err(&pdev->dev, "unknown vf type %d ", engine_type); + ret = bad_otx_cptvf_type; + } +err: + mutex_unlock(&mutex); + return ret; +} + +void otx_cpt_crypto_exit(struct pci_dev *pdev, struct module *mod, + enum otx_cptvf_type engine_type) +{ + struct cpt_device_table *dev_tbl; + bool dev_found = false; + int i, j, count; + + mutex_lock(&mutex); + + dev_tbl = (engine_type == otx_cpt_ae_types) ? &ae_devices : &se_devices; + count = atomic_read(&dev_tbl->count); + for (i = 0; i < count; i++) + if (pdev == dev_tbl->desc[i].dev) { + for (j = i; j < count-1; j++) + dev_tbl->desc[j] = dev_tbl->desc[j+1]; + dev_found = true; + break; + } + + if (!dev_found) { + dev_err(&pdev->dev, "%s device not found", __func__); + goto exit; + } + + if (engine_type != otx_cpt_ae_types) { + if (atomic_dec_and_test(&se_devices.count) && + !is_any_alg_used()) { + cpt_unregister_algs(); + module_put(mod); + is_crypto_registered = false; + } + } else + atomic_dec(&ae_devices.count); +exit: + mutex_unlock(&mutex); +} diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_algs.h b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_algs.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cpt_algs_h +#define __otx_cpt_algs_h + +#include <crypto/hash.h> +#include "otx_cpt_common.h" + +#define otx_cpt_max_enc_key_size 32 +#define otx_cpt_max_hash_key_size 64 +#define otx_cpt_max_key_size (otx_cpt_max_enc_key_size + \ + otx_cpt_max_hash_key_size) +enum otx_cpt_request_type { + otx_cpt_enc_dec_req = 0x1, + otx_cpt_aead_enc_dec_req = 0x2, + otx_cpt_aead_enc_dec_null_req = 0x3, + otx_cpt_passthrough_req = 0x4 +}; + +enum otx_cpt_major_opcodes { + otx_cpt_major_op_misc = 0x01, + otx_cpt_major_op_fc = 0x33, + otx_cpt_major_op_hmac = 0x35, +}; + +enum otx_cpt_req_type { + otx_cpt_ae_core_req, + otx_cpt_se_core_req +}; + +enum otx_cpt_cipher_type { + otx_cpt_cipher_null = 0x0, + otx_cpt_des3_cbc = 0x1, + otx_cpt_des3_ecb = 0x2, + otx_cpt_aes_cbc = 0x3, + otx_cpt_aes_ecb = 0x4, + otx_cpt_aes_cfb = 0x5, + otx_cpt_aes_ctr = 0x6, + otx_cpt_aes_gcm = 0x7, + otx_cpt_aes_xts = 0x8 +}; + +enum otx_cpt_mac_type { + otx_cpt_mac_null = 0x0, + otx_cpt_md5 = 0x1, + otx_cpt_sha1 = 0x2, + otx_cpt_sha224 = 0x3, + otx_cpt_sha256 = 0x4, + otx_cpt_sha384 = 0x5, + otx_cpt_sha512 = 0x6, + otx_cpt_gmac = 0x7 +}; + +enum otx_cpt_aes_key_len { + otx_cpt_aes_128_bit = 0x1, + otx_cpt_aes_192_bit = 0x2, + otx_cpt_aes_256_bit = 0x3 +}; + +union otx_cpt_encr_ctrl { + u64 flags; + struct { +#if defined(__big_endian_bitfield) + u64 enc_cipher:4; + u64 reserved1:1; + u64 aes_key:2; + u64 iv_source:1; + u64 mac_type:4; + u64 reserved2:3; + u64 auth_input_type:1; + u64 mac_len:8; + u64 reserved3:8; + u64 encr_offset:16; + u64 iv_offset:8; + u64 auth_offset:8; +#else + u64 auth_offset:8; + u64 iv_offset:8; + u64 encr_offset:16; + u64 reserved3:8; + u64 mac_len:8; + u64 auth_input_type:1; + u64 reserved2:3; + u64 mac_type:4; + u64 iv_source:1; + u64 aes_key:2; + u64 reserved1:1; + u64 enc_cipher:4; +#endif + } e; +}; + +struct otx_cpt_cipher { + const char *name; + u8 value; +}; + +struct otx_cpt_enc_context { + union otx_cpt_encr_ctrl enc_ctrl; + u8 encr_key[32]; + u8 encr_iv[16]; +}; + +union otx_cpt_fchmac_ctx { + struct { + u8 ipad[64]; + u8 opad[64]; + } e; + struct { + u8 hmac_calc[64]; /* hmac calculated */ + u8 hmac_recv[64]; /* hmac received */ + } s; +}; + +struct otx_cpt_fc_ctx { + struct otx_cpt_enc_context enc; + union otx_cpt_fchmac_ctx hmac; +}; + +struct otx_cpt_enc_ctx { + u32 key_len; + u8 enc_key[otx_cpt_max_key_size]; + u8 cipher_type; + u8 key_type; +}; + +struct otx_cpt_des3_ctx { + u32 key_len; + u8 des3_key[otx_cpt_max_key_size]; +}; + +union otx_cpt_offset_ctrl_word { + u64 flags; + struct { +#if defined(__big_endian_bitfield) + u64 reserved:32; + u64 enc_data_offset:16; + u64 iv_offset:8; + u64 auth_offset:8; +#else + u64 auth_offset:8; + u64 iv_offset:8; + u64 enc_data_offset:16; + u64 reserved:32; +#endif + } e; +}; + +struct otx_cpt_req_ctx { + struct otx_cpt_req_info cpt_req; + union otx_cpt_offset_ctrl_word ctrl_word; + struct otx_cpt_fc_ctx fctx; +}; + +struct otx_cpt_sdesc { + struct shash_desc shash; +}; + +struct otx_cpt_aead_ctx { + u8 key[otx_cpt_max_key_size]; + struct crypto_shash *hashalg; + struct otx_cpt_sdesc *sdesc; + u8 *ipad; + u8 *opad; + u32 enc_key_len; + u32 auth_key_len; + u8 cipher_type; + u8 mac_type; + u8 key_type; + u8 is_trunc_hmac; +}; +int otx_cpt_crypto_init(struct pci_dev *pdev, struct module *mod, + enum otx_cptpf_type pf_type, + enum otx_cptvf_type engine_type, + int num_queues, int num_devices); +void otx_cpt_crypto_exit(struct pci_dev *pdev, struct module *mod, + enum otx_cptvf_type engine_type); +void otx_cpt_callback(int status, void *arg, void *req); + +#endif /* __otx_cpt_algs_h */ diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_main.c b/drivers/crypto/marvell/octeontx/otx_cptvf_main.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_main.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include <linux/interrupt.h> +#include <linux/module.h> +#include "otx_cptvf.h" +#include "otx_cptvf_algs.h" +#include "otx_cptvf_reqmgr.h" + +#define drv_name "octeontx-cptvf" +#define drv_version "1.0" + +static void vq_work_handler(unsigned long data) +{ + struct otx_cptvf_wqe_info *cwqe_info = + (struct otx_cptvf_wqe_info *) data; + + otx_cpt_post_process(&cwqe_info->vq_wqe[0]); +} + +static int init_worker_threads(struct otx_cptvf *cptvf) +{ + struct pci_dev *pdev = cptvf->pdev; + struct otx_cptvf_wqe_info *cwqe_info; + int i; + + cwqe_info = kzalloc(sizeof(*cwqe_info), gfp_kernel); + if (!cwqe_info) + return -enomem; + + if (cptvf->num_queues) { + dev_dbg(&pdev->dev, "creating vq worker threads (%d) ", + cptvf->num_queues); + } + + for (i = 0; i < cptvf->num_queues; i++) { + tasklet_init(&cwqe_info->vq_wqe[i].twork, vq_work_handler, + (u64)cwqe_info); + cwqe_info->vq_wqe[i].cptvf = cptvf; + } + cptvf->wqe_info = cwqe_info; + + return 0; +} + +static void cleanup_worker_threads(struct otx_cptvf *cptvf) +{ + struct pci_dev *pdev = cptvf->pdev; + struct otx_cptvf_wqe_info *cwqe_info; + int i; + + cwqe_info = (struct otx_cptvf_wqe_info *)cptvf->wqe_info; + if (!cwqe_info) + return; + + if (cptvf->num_queues) { + dev_dbg(&pdev->dev, "cleaning vq worker threads (%u) ", + cptvf->num_queues); + } + + for (i = 0; i < cptvf->num_queues; i++) + tasklet_kill(&cwqe_info->vq_wqe[i].twork); + + kzfree(cwqe_info); + cptvf->wqe_info = null; +} + +static void free_pending_queues(struct otx_cpt_pending_qinfo *pqinfo) +{ + struct otx_cpt_pending_queue *queue; + int i; + + for_each_pending_queue(pqinfo, queue, i) { + if (!queue->head) + continue; + + /* free single queue */ + kzfree((queue->head)); + queue->front = 0; + queue->rear = 0; + queue->qlen = 0; + } + pqinfo->num_queues = 0; +} + +static int alloc_pending_queues(struct otx_cpt_pending_qinfo *pqinfo, u32 qlen, + u32 num_queues) +{ + struct otx_cpt_pending_queue *queue = null; + size_t size; + int ret; + u32 i; + + pqinfo->num_queues = num_queues; + size = (qlen * sizeof(struct otx_cpt_pending_entry)); + + for_each_pending_queue(pqinfo, queue, i) { + queue->head = kzalloc((size), gfp_kernel); + if (!queue->head) { + ret = -enomem; + goto pending_qfail; + } + + queue->pending_count = 0; + queue->front = 0; + queue->rear = 0; + queue->qlen = qlen; + + /* init queue spin lock */ + spin_lock_init(&queue->lock); + } + return 0; + +pending_qfail: + free_pending_queues(pqinfo); + + return ret; +} + +static int init_pending_queues(struct otx_cptvf *cptvf, u32 qlen, + u32 num_queues) +{ + struct pci_dev *pdev = cptvf->pdev; + int ret; + + if (!num_queues) + return 0; + + ret = alloc_pending_queues(&cptvf->pqinfo, qlen, num_queues); + if (ret) { + dev_err(&pdev->dev, "failed to setup pending queues (%u) ", + num_queues); + return ret; + } + return 0; +} + +static void cleanup_pending_queues(struct otx_cptvf *cptvf) +{ + struct pci_dev *pdev = cptvf->pdev; + + if (!cptvf->num_queues) + return; + + dev_dbg(&pdev->dev, "cleaning vq pending queue (%u) ", + cptvf->num_queues); + free_pending_queues(&cptvf->pqinfo); +} + +static void free_command_queues(struct otx_cptvf *cptvf, + struct otx_cpt_cmd_qinfo *cqinfo) +{ + struct otx_cpt_cmd_queue *queue = null; + struct otx_cpt_cmd_chunk *chunk = null; + struct pci_dev *pdev = cptvf->pdev; + int i; + + /* clean up for each queue */ + for (i = 0; i < cptvf->num_queues; i++) { + queue = &cqinfo->queue[i]; + + while (!list_empty(&cqinfo->queue[i].chead)) { + chunk = list_first_entry(&cqinfo->queue[i].chead, + struct otx_cpt_cmd_chunk, nextchunk); + + dma_free_coherent(&pdev->dev, chunk->size, + chunk->head, + chunk->dma_addr); + chunk->head = null; + chunk->dma_addr = 0; + list_del(&chunk->nextchunk); + kzfree(chunk); + } + queue->num_chunks = 0; + queue->idx = 0; + + } +} + +static int alloc_command_queues(struct otx_cptvf *cptvf, + struct otx_cpt_cmd_qinfo *cqinfo, + u32 qlen) +{ + struct otx_cpt_cmd_chunk *curr, *first, *last; + struct otx_cpt_cmd_queue *queue = null; + struct pci_dev *pdev = cptvf->pdev; + size_t q_size, c_size, rem_q_size; + u32 qcsize_bytes; + int i; + + + /* qsize in dwords, needed for saddr config, 1-next chunk pointer */ + cptvf->qsize = min(qlen, cqinfo->qchunksize) * + otx_cpt_next_chunk_ptr_size + 1; + /* qsize in bytes to create space for alignment */ + q_size = qlen * otx_cpt_inst_size; + + qcsize_bytes = cqinfo->qchunksize * otx_cpt_inst_size; + + /* per queue initialization */ + for (i = 0; i < cptvf->num_queues; i++) { + c_size = 0; + rem_q_size = q_size; + first = null; + last = null; + + queue = &cqinfo->queue[i]; + init_list_head(&queue->chead); + do { + curr = kzalloc(sizeof(*curr), gfp_kernel); + if (!curr) + goto cmd_qfail; + + c_size = (rem_q_size > qcsize_bytes) ? qcsize_bytes : + rem_q_size; + curr->head = dma_alloc_coherent(&pdev->dev, + c_size + otx_cpt_next_chunk_ptr_size, + &curr->dma_addr, gfp_kernel); + if (!curr->head) { + dev_err(&pdev->dev, + "command q (%d) chunk (%d) allocation failed ", + i, queue->num_chunks); + goto free_curr; + } + curr->size = c_size; + + if (queue->num_chunks == 0) { + first = curr; + queue->base = first; + } + list_add_tail(&curr->nextchunk, + &cqinfo->queue[i].chead); + + queue->num_chunks++; + rem_q_size -= c_size; + if (last) + *((u64 *)(&last->head[last->size])) = + (u64)curr->dma_addr; + + last = curr; + } while (rem_q_size); + + /* + * make the queue circular, tie back last chunk entry to head + */ + curr = first; + *((u64 *)(&last->head[last->size])) = (u64)curr->dma_addr; + queue->qhead = curr; + } + return 0; +free_curr: + kfree(curr); +cmd_qfail: + free_command_queues(cptvf, cqinfo); + return -enomem; +} + +static int init_command_queues(struct otx_cptvf *cptvf, u32 qlen) +{ + struct pci_dev *pdev = cptvf->pdev; + int ret; + + /* setup command queues */ + ret = alloc_command_queues(cptvf, &cptvf->cqinfo, qlen); + if (ret) { + dev_err(&pdev->dev, "failed to allocate command queues (%u) ", + cptvf->num_queues); + return ret; + } + return ret; +} + +static void cleanup_command_queues(struct otx_cptvf *cptvf) +{ + struct pci_dev *pdev = cptvf->pdev; + + if (!cptvf->num_queues) + return; + + dev_dbg(&pdev->dev, "cleaning vq command queue (%u) ", + cptvf->num_queues); + free_command_queues(cptvf, &cptvf->cqinfo); +} + +static void cptvf_sw_cleanup(struct otx_cptvf *cptvf) +{ + cleanup_worker_threads(cptvf); + cleanup_pending_queues(cptvf); + cleanup_command_queues(cptvf); +} + +static int cptvf_sw_init(struct otx_cptvf *cptvf, u32 qlen, u32 num_queues) +{ + struct pci_dev *pdev = cptvf->pdev; + u32 max_dev_queues = 0; + int ret; + + max_dev_queues = otx_cpt_num_qs_per_vf; + /* possible cpus */ + num_queues = min_t(u32, num_queues, max_dev_queues); + cptvf->num_queues = num_queues; + + ret = init_command_queues(cptvf, qlen); + if (ret) { + dev_err(&pdev->dev, "failed to setup command queues (%u) ", + num_queues); + return ret; + } + + ret = init_pending_queues(cptvf, qlen, num_queues); + if (ret) { + dev_err(&pdev->dev, "failed to setup pending queues (%u) ", + num_queues); + goto setup_pqfail; + } + + /* create worker threads for bh processing */ + ret = init_worker_threads(cptvf); + if (ret) { + dev_err(&pdev->dev, "failed to setup worker threads "); + goto init_work_fail; + } + return 0; + +init_work_fail: + cleanup_worker_threads(cptvf); + cleanup_pending_queues(cptvf); + +setup_pqfail: + cleanup_command_queues(cptvf); + + return ret; +} + +static void cptvf_free_irq_affinity(struct otx_cptvf *cptvf, int vec) +{ + irq_set_affinity_hint(pci_irq_vector(cptvf->pdev, vec), null); + free_cpumask_var(cptvf->affinity_mask[vec]); +} + +static void cptvf_write_vq_ctl(struct otx_cptvf *cptvf, bool val) +{ + union otx_cptx_vqx_ctl vqx_ctl; + + vqx_ctl.u = readq(cptvf->reg_base + otx_cpt_vqx_ctl(0)); + vqx_ctl.s.ena = val; + writeq(vqx_ctl.u, cptvf->reg_base + otx_cpt_vqx_ctl(0)); +} + +void otx_cptvf_write_vq_doorbell(struct otx_cptvf *cptvf, u32 val) +{ + union otx_cptx_vqx_doorbell vqx_dbell; + + vqx_dbell.u = readq(cptvf->reg_base + otx_cpt_vqx_doorbell(0)); + vqx_dbell.s.dbell_cnt = val * 8; /* num of instructions * 8 words */ + writeq(vqx_dbell.u, cptvf->reg_base + otx_cpt_vqx_doorbell(0)); +} + +static void cptvf_write_vq_inprog(struct otx_cptvf *cptvf, u8 val) +{ + union otx_cptx_vqx_inprog vqx_inprg; + + vqx_inprg.u = readq(cptvf->reg_base + otx_cpt_vqx_inprog(0)); + vqx_inprg.s.inflight = val; + writeq(vqx_inprg.u, cptvf->reg_base + otx_cpt_vqx_inprog(0)); +} + +static void cptvf_write_vq_done_numwait(struct otx_cptvf *cptvf, u32 val) +{ + union otx_cptx_vqx_done_wait vqx_dwait; + + vqx_dwait.u = readq(cptvf->reg_base + otx_cpt_vqx_done_wait(0)); + vqx_dwait.s.num_wait = val; + writeq(vqx_dwait.u, cptvf->reg_base + otx_cpt_vqx_done_wait(0)); +} + +static u32 cptvf_read_vq_done_numwait(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_done_wait vqx_dwait; + + vqx_dwait.u = readq(cptvf->reg_base + otx_cpt_vqx_done_wait(0)); + return vqx_dwait.s.num_wait; +} + +static void cptvf_write_vq_done_timewait(struct otx_cptvf *cptvf, u16 time) +{ + union otx_cptx_vqx_done_wait vqx_dwait; + + vqx_dwait.u = readq(cptvf->reg_base + otx_cpt_vqx_done_wait(0)); + vqx_dwait.s.time_wait = time; + writeq(vqx_dwait.u, cptvf->reg_base + otx_cpt_vqx_done_wait(0)); +} + + +static u16 cptvf_read_vq_done_timewait(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_done_wait vqx_dwait; + + vqx_dwait.u = readq(cptvf->reg_base + otx_cpt_vqx_done_wait(0)); + return vqx_dwait.s.time_wait; +} + +static void cptvf_enable_swerr_interrupts(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_ena_w1s vqx_misc_ena; + + vqx_misc_ena.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_ena_w1s(0)); + /* enable swerr interrupts for the requested vf */ + vqx_misc_ena.s.swerr = 1; + writeq(vqx_misc_ena.u, cptvf->reg_base + otx_cpt_vqx_misc_ena_w1s(0)); +} + +static void cptvf_enable_mbox_interrupts(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_ena_w1s vqx_misc_ena; + + vqx_misc_ena.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_ena_w1s(0)); + /* enable mbox interrupt for the requested vf */ + vqx_misc_ena.s.mbox = 1; + writeq(vqx_misc_ena.u, cptvf->reg_base + otx_cpt_vqx_misc_ena_w1s(0)); +} + +static void cptvf_enable_done_interrupts(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_done_ena_w1s vqx_done_ena; + + vqx_done_ena.u = readq(cptvf->reg_base + otx_cpt_vqx_done_ena_w1s(0)); + /* enable done interrupt for the requested vf */ + vqx_done_ena.s.done = 1; + writeq(vqx_done_ena.u, cptvf->reg_base + otx_cpt_vqx_done_ena_w1s(0)); +} + +static void cptvf_clear_dovf_intr(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_int vqx_misc_int; + + vqx_misc_int.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_int(0)); + /* w1c for the vf */ + vqx_misc_int.s.dovf = 1; + writeq(vqx_misc_int.u, cptvf->reg_base + otx_cpt_vqx_misc_int(0)); +} + +static void cptvf_clear_irde_intr(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_int vqx_misc_int; + + vqx_misc_int.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_int(0)); + /* w1c for the vf */ + vqx_misc_int.s.irde = 1; + writeq(vqx_misc_int.u, cptvf->reg_base + otx_cpt_vqx_misc_int(0)); +} + +static void cptvf_clear_nwrp_intr(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_int vqx_misc_int; + + vqx_misc_int.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_int(0)); + /* w1c for the vf */ + vqx_misc_int.s.nwrp = 1; + writeq(vqx_misc_int.u, cptvf->reg_base + otx_cpt_vqx_misc_int(0)); +} + +static void cptvf_clear_mbox_intr(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_int vqx_misc_int; + + vqx_misc_int.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_int(0)); + /* w1c for the vf */ + vqx_misc_int.s.mbox = 1; + writeq(vqx_misc_int.u, cptvf->reg_base + otx_cpt_vqx_misc_int(0)); +} + +static void cptvf_clear_swerr_intr(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_misc_int vqx_misc_int; + + vqx_misc_int.u = readq(cptvf->reg_base + otx_cpt_vqx_misc_int(0)); + /* w1c for the vf */ + vqx_misc_int.s.swerr = 1; + writeq(vqx_misc_int.u, cptvf->reg_base + otx_cpt_vqx_misc_int(0)); +} + +static u64 cptvf_read_vf_misc_intr_status(struct otx_cptvf *cptvf) +{ + return readq(cptvf->reg_base + otx_cpt_vqx_misc_int(0)); +} + +static irqreturn_t cptvf_misc_intr_handler(int __always_unused irq, + void *arg) +{ + struct otx_cptvf *cptvf = arg; + struct pci_dev *pdev = cptvf->pdev; + u64 intr; + + intr = cptvf_read_vf_misc_intr_status(cptvf); + /* check for misc interrupt types */ + if (likely(intr & otx_cpt_vf_intr_mbox_mask)) { + dev_dbg(&pdev->dev, "mailbox interrupt 0x%llx on cpt vf %d ", + intr, cptvf->vfid); + otx_cptvf_handle_mbox_intr(cptvf); + cptvf_clear_mbox_intr(cptvf); + } else if (unlikely(intr & otx_cpt_vf_intr_dovf_mask)) { + cptvf_clear_dovf_intr(cptvf); + /* clear doorbell count */ + otx_cptvf_write_vq_doorbell(cptvf, 0); + dev_err(&pdev->dev, + "doorbell overflow error interrupt 0x%llx on cpt vf %d ", + intr, cptvf->vfid); + } else if (unlikely(intr & otx_cpt_vf_intr_irde_mask)) { + cptvf_clear_irde_intr(cptvf); + dev_err(&pdev->dev, + "instruction ncb read error interrupt 0x%llx on cpt vf %d ", + intr, cptvf->vfid); + } else if (unlikely(intr & otx_cpt_vf_intr_nwrp_mask)) { + cptvf_clear_nwrp_intr(cptvf); + dev_err(&pdev->dev, + "ncb response write error interrupt 0x%llx on cpt vf %d ", + intr, cptvf->vfid); + } else if (unlikely(intr & otx_cpt_vf_intr_serr_mask)) { + cptvf_clear_swerr_intr(cptvf); + dev_err(&pdev->dev, + "software error interrupt 0x%llx on cpt vf %d ", + intr, cptvf->vfid); + } else { + dev_err(&pdev->dev, "unhandled interrupt in otx_cpt vf %d ", + cptvf->vfid); + } + + return irq_handled; +} + +static inline struct otx_cptvf_wqe *get_cptvf_vq_wqe(struct otx_cptvf *cptvf, + int qno) +{ + struct otx_cptvf_wqe_info *nwqe_info; + + if (unlikely(qno >= cptvf->num_queues)) + return null; + nwqe_info = (struct otx_cptvf_wqe_info *)cptvf->wqe_info; + + return &nwqe_info->vq_wqe[qno]; +} + +static inline u32 cptvf_read_vq_done_count(struct otx_cptvf *cptvf) +{ + union otx_cptx_vqx_done vqx_done; + + vqx_done.u = readq(cptvf->reg_base + otx_cpt_vqx_done(0)); + return vqx_done.s.done; +} + +static inline void cptvf_write_vq_done_ack(struct otx_cptvf *cptvf, + u32 ackcnt) +{ + union otx_cptx_vqx_done_ack vqx_dack_cnt; + + vqx_dack_cnt.u = readq(cptvf->reg_base + otx_cpt_vqx_done_ack(0)); + vqx_dack_cnt.s.done_ack = ackcnt; + writeq(vqx_dack_cnt.u, cptvf->reg_base + otx_cpt_vqx_done_ack(0)); +} + +static irqreturn_t cptvf_done_intr_handler(int __always_unused irq, + void *cptvf_dev) +{ + struct otx_cptvf *cptvf = (struct otx_cptvf *)cptvf_dev; + struct pci_dev *pdev = cptvf->pdev; + /* read the number of completions */ + u32 intr = cptvf_read_vq_done_count(cptvf); + + if (intr) { + struct otx_cptvf_wqe *wqe; + + /* + * acknowledge the number of scheduled completions for + * processing + */ + cptvf_write_vq_done_ack(cptvf, intr); + wqe = get_cptvf_vq_wqe(cptvf, 0); + if (unlikely(!wqe)) { + dev_err(&pdev->dev, "no work to schedule for vf (%d)", + cptvf->vfid); + return irq_none; + } + tasklet_hi_schedule(&wqe->twork); + } + + return irq_handled; +} + +static void cptvf_set_irq_affinity(struct otx_cptvf *cptvf, int vec) +{ + struct pci_dev *pdev = cptvf->pdev; + int cpu; + + if (!zalloc_cpumask_var(&cptvf->affinity_mask[vec], + gfp_kernel)) { + dev_err(&pdev->dev, + "allocation failed for affinity_mask for vf %d", + cptvf->vfid); + return; + } + + cpu = cptvf->vfid % num_online_cpus(); + cpumask_set_cpu(cpumask_local_spread(cpu, cptvf->node), + cptvf->affinity_mask[vec]); + irq_set_affinity_hint(pci_irq_vector(pdev, vec), + cptvf->affinity_mask[vec]); +} + +static void cptvf_write_vq_saddr(struct otx_cptvf *cptvf, u64 val) +{ + union otx_cptx_vqx_saddr vqx_saddr; + + vqx_saddr.u = val; + writeq(vqx_saddr.u, cptvf->reg_base + otx_cpt_vqx_saddr(0)); +} + +static void cptvf_device_init(struct otx_cptvf *cptvf) +{ + u64 base_addr = 0; + + /* disable the vq */ + cptvf_write_vq_ctl(cptvf, 0); + /* reset the doorbell */ + otx_cptvf_write_vq_doorbell(cptvf, 0); + /* clear inflight */ + cptvf_write_vq_inprog(cptvf, 0); + /* write vq saddr */ + base_addr = (u64)(cptvf->cqinfo.queue[0].qhead->dma_addr); + cptvf_write_vq_saddr(cptvf, base_addr); + /* configure timerhold / coalescence */ + cptvf_write_vq_done_timewait(cptvf, otx_cpt_timer_hold); + cptvf_write_vq_done_numwait(cptvf, otx_cpt_count_hold); + /* enable the vq */ + cptvf_write_vq_ctl(cptvf, 1); + /* flag the vf ready */ + cptvf->flags |= otx_cpt_flag_device_ready; +} + +static ssize_t vf_type_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + char *msg; + + switch (cptvf->vftype) { + case otx_cpt_ae_types: + msg = "ae"; + break; + + case otx_cpt_se_types: + msg = "se"; + break; + + default: + msg = "invalid"; + } + + return scnprintf(buf, page_size, "%s ", msg); +} + +static ssize_t vf_engine_group_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + + return scnprintf(buf, page_size, "%d ", cptvf->vfgrp); +} + +static ssize_t vf_engine_group_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + int val, ret; + + ret = kstrtoint(buf, 10, &val); + if (ret) + return ret; + + if (val < 0) + return -einval; + + if (val >= otx_cpt_max_engine_groups) { + dev_err(dev, "engine group >= than max available groups %d", + otx_cpt_max_engine_groups); + return -einval; + } + + ret = otx_cptvf_send_vf_to_grp_msg(cptvf, val); + if (ret) + return ret; + + return count; +} + +static ssize_t vf_coalesc_time_wait_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + + return scnprintf(buf, page_size, "%d ", + cptvf_read_vq_done_timewait(cptvf)); +} + +static ssize_t vf_coalesc_num_wait_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + + return scnprintf(buf, page_size, "%d ", + cptvf_read_vq_done_numwait(cptvf)); +} + +static ssize_t vf_coalesc_time_wait_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + long val; + int ret; + + ret = kstrtol(buf, 10, &val); + if (ret != 0) + return ret; + + if (val < otx_cpt_coalesc_min_time_wait || + val > otx_cpt_coalesc_max_time_wait) + return -einval; + + cptvf_write_vq_done_timewait(cptvf, val); + return count; +} + +static ssize_t vf_coalesc_num_wait_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct otx_cptvf *cptvf = dev_get_drvdata(dev); + long val; + int ret; + + ret = kstrtol(buf, 10, &val); + if (ret != 0) + return ret; + + if (val < otx_cpt_coalesc_min_num_wait || + val > otx_cpt_coalesc_max_num_wait) + return -einval; + + cptvf_write_vq_done_numwait(cptvf, val); + return count; +} + +static device_attr_ro(vf_type); +static device_attr_rw(vf_engine_group); +static device_attr_rw(vf_coalesc_time_wait); +static device_attr_rw(vf_coalesc_num_wait); + +static struct attribute *otx_cptvf_attrs[] = { + &dev_attr_vf_type.attr, + &dev_attr_vf_engine_group.attr, + &dev_attr_vf_coalesc_time_wait.attr, + &dev_attr_vf_coalesc_num_wait.attr, + null +}; + +static const struct attribute_group otx_cptvf_sysfs_group = { + .attrs = otx_cptvf_attrs, +}; + +static int otx_cptvf_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct device *dev = &pdev->dev; + struct otx_cptvf *cptvf; + int err; + + cptvf = devm_kzalloc(dev, sizeof(*cptvf), gfp_kernel); + if (!cptvf) + return -enomem; + + pci_set_drvdata(pdev, cptvf); + cptvf->pdev = pdev; + + err = pci_enable_device(pdev); + if (err) { + dev_err(dev, "failed to enable pci device "); + goto clear_drvdata; + } + err = pci_request_regions(pdev, drv_name); + if (err) { + dev_err(dev, "pci request regions failed 0x%x ", err); + goto disable_device; + } + err = pci_set_dma_mask(pdev, dma_bit_mask(48)); + if (err) { + dev_err(dev, "unable to get usable dma configuration "); + goto release_regions; + } + + err = pci_set_consistent_dma_mask(pdev, dma_bit_mask(48)); + if (err) { + dev_err(dev, "unable to get 48-bit dma for consistent allocations "); + goto release_regions; + } + + /* map pf's configuration registers */ + cptvf->reg_base = pci_iomap(pdev, otx_cpt_vf_pci_cfg_bar, 0); + if (!cptvf->reg_base) { + dev_err(dev, "cannot map config register space, aborting "); + err = -enomem; + goto release_regions; + } + + cptvf->node = dev_to_node(&pdev->dev); + err = pci_alloc_irq_vectors(pdev, otx_cpt_vf_msix_vectors, + otx_cpt_vf_msix_vectors, pci_irq_msix); + if (err < 0) { + dev_err(dev, "request for #%d msix vectors failed ", + otx_cpt_vf_msix_vectors); + goto unmap_region; + } + + err = request_irq(pci_irq_vector(pdev, cpt_vf_int_vec_e_misc), + cptvf_misc_intr_handler, 0, "cpt vf misc intr", + cptvf); + if (err) { + dev_err(dev, "failed to request misc irq"); + goto free_vectors; + } + + /* enable mailbox interrupt */ + cptvf_enable_mbox_interrupts(cptvf); + cptvf_enable_swerr_interrupts(cptvf); + + /* check cpt pf status, gets chip id / device id from pf if ready */ + err = otx_cptvf_check_pf_ready(cptvf); + if (err) + goto free_misc_irq; + + /* cpt vf software resources initialization */ + cptvf->cqinfo.qchunksize = otx_cpt_cmd_qchunk_size; + err = cptvf_sw_init(cptvf, otx_cpt_cmd_qlen, otx_cpt_num_qs_per_vf); + if (err) { + dev_err(dev, "cptvf_sw_init() failed"); + goto free_misc_irq; + } + /* convey vq len to pf */ + err = otx_cptvf_send_vq_size_msg(cptvf); + if (err) + goto sw_cleanup; + + /* cpt vf device initialization */ + cptvf_device_init(cptvf); + /* send msg to pf to assign currnet q to required group */ + err = otx_cptvf_send_vf_to_grp_msg(cptvf, cptvf->vfgrp); + if (err) + goto sw_cleanup; + + cptvf->priority = 1; + err = otx_cptvf_send_vf_priority_msg(cptvf); + if (err) + goto sw_cleanup; + + err = request_irq(pci_irq_vector(pdev, cpt_vf_int_vec_e_done), + cptvf_done_intr_handler, 0, "cpt vf done intr", + cptvf); + if (err) { + dev_err(dev, "failed to request done irq "); + goto free_done_irq; + } + + /* enable done interrupt */ + cptvf_enable_done_interrupts(cptvf); + + /* set irq affinity masks */ + cptvf_set_irq_affinity(cptvf, cpt_vf_int_vec_e_misc); + cptvf_set_irq_affinity(cptvf, cpt_vf_int_vec_e_done); + + err = otx_cptvf_send_vf_up(cptvf); + if (err) + goto free_irq_affinity; + + /* initialize algorithms and set ops */ + err = otx_cpt_crypto_init(pdev, this_module, + cptvf->vftype == otx_cpt_se_types ? otx_cpt_se : otx_cpt_ae, + cptvf->vftype, 1, cptvf->num_vfs); + if (err) { + dev_err(dev, "failed to register crypto algs "); + goto free_irq_affinity; + } + + err = sysfs_create_group(&dev->kobj, &otx_cptvf_sysfs_group); + if (err) { + dev_err(dev, "creating sysfs entries failed "); + goto crypto_exit; + } + + return 0; + +crypto_exit: + otx_cpt_crypto_exit(pdev, this_module, cptvf->vftype); +free_irq_affinity: + cptvf_free_irq_affinity(cptvf, cpt_vf_int_vec_e_done); + cptvf_free_irq_affinity(cptvf, cpt_vf_int_vec_e_misc); +free_done_irq: + free_irq(pci_irq_vector(pdev, cpt_vf_int_vec_e_done), cptvf); +sw_cleanup: + cptvf_sw_cleanup(cptvf); +free_misc_irq: + free_irq(pci_irq_vector(pdev, cpt_vf_int_vec_e_misc), cptvf); +free_vectors: + pci_free_irq_vectors(cptvf->pdev); +unmap_region: + pci_iounmap(pdev, cptvf->reg_base); +release_regions: + pci_release_regions(pdev); +disable_device: + pci_disable_device(pdev); +clear_drvdata: + pci_set_drvdata(pdev, null); + + return err; +} + +static void otx_cptvf_remove(struct pci_dev *pdev) +{ + struct otx_cptvf *cptvf = pci_get_drvdata(pdev); + + if (!cptvf) { + dev_err(&pdev->dev, "invalid cpt-vf device "); + return; + } + + /* convey down to pf */ + if (otx_cptvf_send_vf_down(cptvf)) { + dev_err(&pdev->dev, "pf not responding to down msg"); + } else { + sysfs_remove_group(&pdev->dev.kobj, &otx_cptvf_sysfs_group); + otx_cpt_crypto_exit(pdev, this_module, cptvf->vftype); + cptvf_free_irq_affinity(cptvf, cpt_vf_int_vec_e_done); + cptvf_free_irq_affinity(cptvf, cpt_vf_int_vec_e_misc); + free_irq(pci_irq_vector(pdev, cpt_vf_int_vec_e_done), cptvf); + free_irq(pci_irq_vector(pdev, cpt_vf_int_vec_e_misc), cptvf); + cptvf_sw_cleanup(cptvf); + pci_free_irq_vectors(cptvf->pdev); + pci_iounmap(pdev, cptvf->reg_base); + pci_release_regions(pdev); + pci_disable_device(pdev); + pci_set_drvdata(pdev, null); + } +} + +/* supported devices */ +static const struct pci_device_id otx_cptvf_id_table[] = { + {pci_vdevice(cavium, otx_cpt_pci_vf_device_id), 0}, + { 0, } /* end of table */ +}; + +static struct pci_driver otx_cptvf_pci_driver = { + .name = drv_name, + .id_table = otx_cptvf_id_table, + .probe = otx_cptvf_probe, + .remove = otx_cptvf_remove, +}; + +module_pci_driver(otx_cptvf_pci_driver); + +module_author("marvell international ltd."); +module_description("marvell octeontx cpt virtual function driver"); +module_license("gpl v2"); +module_version(drv_version); +module_device_table(pci, otx_cptvf_id_table); diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c b/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_mbox.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include <linux/delay.h> +#include "otx_cptvf.h" + +#define cpt_mbox_msg_timeout 2000 + +static char *get_mbox_opcode_str(int msg_opcode) +{ + char *str = "unknown"; + + switch (msg_opcode) { + case otx_cpt_msg_vf_up: + str = "up"; + break; + + case otx_cpt_msg_vf_down: + str = "down"; + break; + + case otx_cpt_msg_ready: + str = "ready"; + break; + + case otx_cpt_msg_qlen: + str = "qlen"; + break; + + case otx_cpt_msg_qbind_grp: + str = "qbind_grp"; + break; + + case otx_cpt_msg_vq_priority: + str = "vq_priority"; + break; + + case otx_cpt_msg_pf_type: + str = "pf_type"; + break; + + case otx_cpt_msg_ack: + str = "ack"; + break; + + case otx_cpt_msg_nack: + str = "nack"; + break; + } + return str; +} + +static void dump_mbox_msg(struct otx_cpt_mbox *mbox_msg, int vf_id) +{ + char raw_data_str[otx_cpt_max_mbox_data_str_size]; + + hex_dump_to_buffer(mbox_msg, sizeof(struct otx_cpt_mbox), 16, 8, + raw_data_str, otx_cpt_max_mbox_data_str_size, false); + if (vf_id >= 0) + pr_debug("mbox msg %s received from vf%d raw_data %s", + get_mbox_opcode_str(mbox_msg->msg), vf_id, + raw_data_str); + else + pr_debug("mbox msg %s received from pf raw_data %s", + get_mbox_opcode_str(mbox_msg->msg), raw_data_str); +} + +static void cptvf_send_msg_to_pf(struct otx_cptvf *cptvf, + struct otx_cpt_mbox *mbx) +{ + /* writing mbox(1) causes interrupt */ + writeq(mbx->msg, cptvf->reg_base + otx_cpt_vfx_pf_mboxx(0, 0)); + writeq(mbx->data, cptvf->reg_base + otx_cpt_vfx_pf_mboxx(0, 1)); +} + +/* interrupt handler to handle mailbox messages from vfs */ +void otx_cptvf_handle_mbox_intr(struct otx_cptvf *cptvf) +{ + struct otx_cpt_mbox mbx = {}; + + /* + * mbox[0] contains msg + * mbox[1] contains data + */ + mbx.msg = readq(cptvf->reg_base + otx_cpt_vfx_pf_mboxx(0, 0)); + mbx.data = readq(cptvf->reg_base + otx_cpt_vfx_pf_mboxx(0, 1)); + + dump_mbox_msg(&mbx, -1); + + switch (mbx.msg) { + case otx_cpt_msg_vf_up: + cptvf->pf_acked = true; + cptvf->num_vfs = mbx.data; + break; + case otx_cpt_msg_ready: + cptvf->pf_acked = true; + cptvf->vfid = mbx.data; + dev_dbg(&cptvf->pdev->dev, "received vfid %d ", cptvf->vfid); + break; + case otx_cpt_msg_qbind_grp: + cptvf->pf_acked = true; + cptvf->vftype = mbx.data; + dev_dbg(&cptvf->pdev->dev, "vf %d type %s group %d ", + cptvf->vfid, + ((mbx.data == otx_cpt_se_types) ? "se" : "ae"), + cptvf->vfgrp); + break; + case otx_cpt_msg_ack: + cptvf->pf_acked = true; + break; + case otx_cpt_msg_nack: + cptvf->pf_nacked = true; + break; + default: + dev_err(&cptvf->pdev->dev, "invalid msg from pf, msg 0x%llx ", + mbx.msg); + break; + } +} + +static int cptvf_send_msg_to_pf_timeout(struct otx_cptvf *cptvf, + struct otx_cpt_mbox *mbx) +{ + int timeout = cpt_mbox_msg_timeout; + int sleep = 10; + + cptvf->pf_acked = false; + cptvf->pf_nacked = false; + cptvf_send_msg_to_pf(cptvf, mbx); + /* wait for previous message to be acked, timeout 2sec */ + while (!cptvf->pf_acked) { + if (cptvf->pf_nacked) + return -einval; + msleep(sleep); + if (cptvf->pf_acked) + break; + timeout -= sleep; + if (!timeout) { + dev_err(&cptvf->pdev->dev, + "pf didn't ack to mbox msg %llx from vf%u ", + mbx->msg, cptvf->vfid); + return -ebusy; + } + } + return 0; +} + +/* + * checks if vf is able to comminicate with pf + * and also gets the cpt number this vf is associated to. + */ +int otx_cptvf_check_pf_ready(struct otx_cptvf *cptvf) +{ + struct otx_cpt_mbox mbx = {}; + int ret; + + mbx.msg = otx_cpt_msg_ready; + ret = cptvf_send_msg_to_pf_timeout(cptvf, &mbx); + + return ret; +} + +/* + * communicate vqs size to pf to program cpt(0)_pf_q(0-15)_ctl of the vf. + * must be acked. + */ +int otx_cptvf_send_vq_size_msg(struct otx_cptvf *cptvf) +{ + struct otx_cpt_mbox mbx = {}; + int ret; + + mbx.msg = otx_cpt_msg_qlen; + mbx.data = cptvf->qsize; + ret = cptvf_send_msg_to_pf_timeout(cptvf, &mbx); + + return ret; +} + +/* + * communicate vf group required to pf and get the vq binded to that group + */ +int otx_cptvf_send_vf_to_grp_msg(struct otx_cptvf *cptvf, int group) +{ + struct otx_cpt_mbox mbx = {}; + int ret; + + mbx.msg = otx_cpt_msg_qbind_grp; + /* convey group of the vf */ + mbx.data = group; + ret = cptvf_send_msg_to_pf_timeout(cptvf, &mbx); + if (ret) + return ret; + cptvf->vfgrp = group; + + return 0; +} + +/* + * communicate vf group required to pf and get the vq binded to that group + */ +int otx_cptvf_send_vf_priority_msg(struct otx_cptvf *cptvf) +{ + struct otx_cpt_mbox mbx = {}; + int ret; + + mbx.msg = otx_cpt_msg_vq_priority; + /* convey group of the vf */ + mbx.data = cptvf->priority; + ret = cptvf_send_msg_to_pf_timeout(cptvf, &mbx); + + return ret; +} + +/* + * communicate to pf that vf is up and running + */ +int otx_cptvf_send_vf_up(struct otx_cptvf *cptvf) +{ + struct otx_cpt_mbox mbx = {}; + int ret; + + mbx.msg = otx_cpt_msg_vf_up; + ret = cptvf_send_msg_to_pf_timeout(cptvf, &mbx); + + return ret; +} + +/* + * communicate to pf that vf is down and running + */ +int otx_cptvf_send_vf_down(struct otx_cptvf *cptvf) +{ + struct otx_cpt_mbox mbx = {}; + int ret; + + mbx.msg = otx_cpt_msg_vf_down; + ret = cptvf_send_msg_to_pf_timeout(cptvf, &mbx); + + return ret; +} diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c b/drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#include "otx_cptvf.h" +#include "otx_cptvf_algs.h" + +/* completion code size and initial value */ +#define completion_code_size 8 +#define completion_code_init 0 + +/* sg list header size in bytes */ +#define sg_list_hdr_size 8 + +/* default timeout when waiting for free pending entry in us */ +#define cpt_pentry_timeout 1000 +#define cpt_pentry_step 50 + +/* default threshold for stopping and resuming sender requests */ +#define cpt_iq_stop_margin 128 +#define cpt_iq_resume_margin 512 + +#define cpt_dma_align 128 + +void otx_cpt_dump_sg_list(struct pci_dev *pdev, struct otx_cpt_req_info *req) +{ + int i; + + pr_debug("gather list size %d ", req->incnt); + for (i = 0; i < req->incnt; i++) { + pr_debug("buffer %d size %d, vptr 0x%p, dmaptr 0x%p ", i, + req->in[i].size, req->in[i].vptr, + (void *) req->in[i].dma_addr); + pr_debug("buffer hexdump (%d bytes) ", + req->in[i].size); + print_hex_dump_debug("", dump_prefix_none, 16, 1, + req->in[i].vptr, req->in[i].size, false); + } + + pr_debug("scatter list size %d ", req->outcnt); + for (i = 0; i < req->outcnt; i++) { + pr_debug("buffer %d size %d, vptr 0x%p, dmaptr 0x%p ", i, + req->out[i].size, req->out[i].vptr, + (void *) req->out[i].dma_addr); + pr_debug("buffer hexdump (%d bytes) ", req->out[i].size); + print_hex_dump_debug("", dump_prefix_none, 16, 1, + req->out[i].vptr, req->out[i].size, false); + } +} + +static inline struct otx_cpt_pending_entry *get_free_pending_entry( + struct otx_cpt_pending_queue *q, + int qlen) +{ + struct otx_cpt_pending_entry *ent = null; + + ent = &q->head[q->rear]; + if (unlikely(ent->busy)) + return null; + + q->rear++; + if (unlikely(q->rear == qlen)) + q->rear = 0; + + return ent; +} + +static inline u32 modulo_inc(u32 index, u32 length, u32 inc) +{ + if (warn_on(inc > length)) + inc = length; + + index += inc; + if (unlikely(index >= length)) + index -= length; + + return index; +} + +static inline void free_pentry(struct otx_cpt_pending_entry *pentry) +{ + pentry->completion_addr = null; + pentry->info = null; + pentry->callback = null; + pentry->areq = null; + pentry->resume_sender = false; + pentry->busy = false; +} + +static inline int setup_sgio_components(struct pci_dev *pdev, + struct otx_cpt_buf_ptr *list, + int buf_count, u8 *buffer) +{ + struct otx_cpt_sglist_component *sg_ptr = null; + int ret = 0, i, j; + int components; + + if (unlikely(!list)) { + dev_err(&pdev->dev, "input list pointer is null "); + return -efault; + } + + for (i = 0; i < buf_count; i++) { + if (likely(list[i].vptr)) { + list[i].dma_addr = dma_map_single(&pdev->dev, + list[i].vptr, + list[i].size, + dma_bidirectional); + if (unlikely(dma_mapping_error(&pdev->dev, + list[i].dma_addr))) { + dev_err(&pdev->dev, "dma mapping failed "); + ret = -eio; + goto sg_cleanup; + } + } + } + + components = buf_count / 4; + sg_ptr = (struct otx_cpt_sglist_component *)buffer; + for (i = 0; i < components; i++) { + sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size); + sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size); + sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size); + sg_ptr->u.s.len3 = cpu_to_be16(list[i * 4 + 3].size); + sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr); + sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr); + sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr); + sg_ptr->ptr3 = cpu_to_be64(list[i * 4 + 3].dma_addr); + sg_ptr++; + } + components = buf_count % 4; + + switch (components) { + case 3: + sg_ptr->u.s.len2 = cpu_to_be16(list[i * 4 + 2].size); + sg_ptr->ptr2 = cpu_to_be64(list[i * 4 + 2].dma_addr); + /* fall through */ + case 2: + sg_ptr->u.s.len1 = cpu_to_be16(list[i * 4 + 1].size); + sg_ptr->ptr1 = cpu_to_be64(list[i * 4 + 1].dma_addr); + /* fall through */ + case 1: + sg_ptr->u.s.len0 = cpu_to_be16(list[i * 4 + 0].size); + sg_ptr->ptr0 = cpu_to_be64(list[i * 4 + 0].dma_addr); + break; + default: + break; + } + return ret; + +sg_cleanup: + for (j = 0; j < i; j++) { + if (list[j].dma_addr) { + dma_unmap_single(&pdev->dev, list[i].dma_addr, + list[i].size, dma_bidirectional); + } + + list[j].dma_addr = 0; + } + return ret; +} + +static inline int setup_sgio_list(struct pci_dev *pdev, + struct otx_cpt_info_buffer **pinfo, + struct otx_cpt_req_info *req, gfp_t gfp) +{ + u32 dlen, align_dlen, info_len, rlen; + struct otx_cpt_info_buffer *info; + u16 g_sz_bytes, s_sz_bytes; + int align = cpt_dma_align; + u32 total_mem_len; + + if (unlikely(req->incnt > otx_cpt_max_sg_in_cnt || + req->outcnt > otx_cpt_max_sg_out_cnt)) { + dev_err(&pdev->dev, "error too many sg components "); + return -einval; + } + + g_sz_bytes = ((req->incnt + 3) / 4) * + sizeof(struct otx_cpt_sglist_component); + s_sz_bytes = ((req->outcnt + 3) / 4) * + sizeof(struct otx_cpt_sglist_component); + + dlen = g_sz_bytes + s_sz_bytes + sg_list_hdr_size; + align_dlen = align(dlen, align); + info_len = align(sizeof(*info), align); + rlen = align(sizeof(union otx_cpt_res_s), align); + total_mem_len = align_dlen + info_len + rlen + completion_code_size; + + info = kzalloc(total_mem_len, gfp); + if (unlikely(!info)) { + dev_err(&pdev->dev, "memory allocation failed "); + return -enomem; + } + *pinfo = info; + info->dlen = dlen; + info->in_buffer = (u8 *)info + info_len; + + ((u16 *)info->in_buffer)[0] = req->outcnt; + ((u16 *)info->in_buffer)[1] = req->incnt; + ((u16 *)info->in_buffer)[2] = 0; + ((u16 *)info->in_buffer)[3] = 0; + *(u64 *)info->in_buffer = cpu_to_be64p((u64 *)info->in_buffer); + + /* setup gather (input) components */ + if (setup_sgio_components(pdev, req->in, req->incnt, + &info->in_buffer[8])) { + dev_err(&pdev->dev, "failed to setup gather list "); + return -efault; + } + + if (setup_sgio_components(pdev, req->out, req->outcnt, + &info->in_buffer[8 + g_sz_bytes])) { + dev_err(&pdev->dev, "failed to setup scatter list "); + return -efault; + } + + info->dma_len = total_mem_len - info_len; + info->dptr_baddr = dma_map_single(&pdev->dev, (void *)info->in_buffer, + info->dma_len, dma_bidirectional); + if (unlikely(dma_mapping_error(&pdev->dev, info->dptr_baddr))) { + dev_err(&pdev->dev, "dma mapping failed for cpt req "); + return -eio; + } + /* + * get buffer for union otx_cpt_res_s response + * structure and its physical address + */ + info->completion_addr = (u64 *)(info->in_buffer + align_dlen); + info->comp_baddr = info->dptr_baddr + align_dlen; + + /* create and initialize rptr */ + info->out_buffer = (u8 *)info->completion_addr + rlen; + info->rptr_baddr = info->comp_baddr + rlen; + + *((u64 *) info->out_buffer) = ~((u64) completion_code_init); + + return 0; +} + + +static void cpt_fill_inst(union otx_cpt_inst_s *inst, + struct otx_cpt_info_buffer *info, + struct otx_cpt_iq_cmd *cmd) +{ + inst->u[0] = 0x0; + inst->s.doneint = true; + inst->s.res_addr = (u64)info->comp_baddr; + inst->u[2] = 0x0; + inst->s.wq_ptr = 0; + inst->s.ei0 = cmd->cmd.u64; + inst->s.ei1 = cmd->dptr; + inst->s.ei2 = cmd->rptr; + inst->s.ei3 = cmd->cptr.u64; +} + +/* + * on octeontx platform the parameter db_count is used as a count for ringing + * door bell. the valid values for db_count are: + * 0 - 1 cpt instruction will be enqueued however cpt will not be informed + * 1 - 1 cpt instruction will be enqueued and cpt will be informed + */ +static void cpt_send_cmd(union otx_cpt_inst_s *cptinst, struct otx_cptvf *cptvf) +{ + struct otx_cpt_cmd_qinfo *qinfo = &cptvf->cqinfo; + struct otx_cpt_cmd_queue *queue; + struct otx_cpt_cmd_chunk *curr; + u8 *ent; + + queue = &qinfo->queue[0]; + /* + * cpt_send_cmd is currently called only from critical section + * therefore no locking is required for accessing instruction queue + */ + ent = &queue->qhead->head[queue->idx * otx_cpt_inst_size]; + memcpy(ent, (void *) cptinst, otx_cpt_inst_size); + + if (++queue->idx >= queue->qhead->size / 64) { + curr = queue->qhead; + + if (list_is_last(&curr->nextchunk, &queue->chead)) + queue->qhead = queue->base; + else + queue->qhead = list_next_entry(queue->qhead, nextchunk); + queue->idx = 0; + } + /* make sure all memory stores are done before ringing doorbell */ + smp_wmb(); + otx_cptvf_write_vq_doorbell(cptvf, 1); +} + +static int process_request(struct pci_dev *pdev, struct otx_cpt_req_info *req, + struct otx_cpt_pending_queue *pqueue, + struct otx_cptvf *cptvf) +{ + struct otx_cptvf_request *cpt_req = &req->req; + struct otx_cpt_pending_entry *pentry = null; + union otx_cpt_ctrl_info *ctrl = &req->ctrl; + struct otx_cpt_info_buffer *info = null; + union otx_cpt_res_s *result = null; + struct otx_cpt_iq_cmd iq_cmd; + union otx_cpt_inst_s cptinst; + int retry, ret = 0; + u8 resume_sender; + gfp_t gfp; + + gfp = (req->areq->flags & crypto_tfm_req_may_sleep) ? gfp_kernel : + gfp_atomic; + ret = setup_sgio_list(pdev, &info, req, gfp); + if (unlikely(ret)) { + dev_err(&pdev->dev, "setting up sg list failed"); + goto request_cleanup; + } + cpt_req->dlen = info->dlen; + + result = (union otx_cpt_res_s *) info->completion_addr; + result->s.compcode = completion_code_init; + + spin_lock_bh(&pqueue->lock); + pentry = get_free_pending_entry(pqueue, pqueue->qlen); + retry = cpt_pentry_timeout / cpt_pentry_step; + while (unlikely(!pentry) && retry--) { + spin_unlock_bh(&pqueue->lock); + udelay(cpt_pentry_step); + spin_lock_bh(&pqueue->lock); + pentry = get_free_pending_entry(pqueue, pqueue->qlen); + } + + if (unlikely(!pentry)) { + ret = -enospc; + spin_unlock_bh(&pqueue->lock); + goto request_cleanup; + } + + /* + * check if we are close to filling in entire pending queue, + * if so then tell the sender to stop/sleep by returning -ebusy + * we do it only for context which can sleep (gfp_kernel) + */ + if (gfp == gfp_kernel && + pqueue->pending_count > (pqueue->qlen - cpt_iq_stop_margin)) { + pentry->resume_sender = true; + } else + pentry->resume_sender = false; + resume_sender = pentry->resume_sender; + pqueue->pending_count++; + + pentry->completion_addr = info->completion_addr; + pentry->info = info; + pentry->callback = req->callback; + pentry->areq = req->areq; + pentry->busy = true; + info->pentry = pentry; + info->time_in = jiffies; + info->req = req; + + /* fill in the command */ + iq_cmd.cmd.u64 = 0; + iq_cmd.cmd.s.opcode = cpu_to_be16(cpt_req->opcode.flags); + iq_cmd.cmd.s.param1 = cpu_to_be16(cpt_req->param1); + iq_cmd.cmd.s.param2 = cpu_to_be16(cpt_req->param2); + iq_cmd.cmd.s.dlen = cpu_to_be16(cpt_req->dlen); + + /* 64-bit swap for microcode data reads, not needed for addresses*/ + iq_cmd.cmd.u64 = cpu_to_be64(iq_cmd.cmd.u64); + iq_cmd.dptr = info->dptr_baddr; + iq_cmd.rptr = info->rptr_baddr; + iq_cmd.cptr.u64 = 0; + iq_cmd.cptr.s.grp = ctrl->s.grp; + + /* fill in the cpt_inst_s type command for hw interpretation */ + cpt_fill_inst(&cptinst, info, &iq_cmd); + + /* print debug info if enabled */ + otx_cpt_dump_sg_list(pdev, req); + pr_debug("cpt_inst_s hexdump (%d bytes) ", otx_cpt_inst_size); + print_hex_dump_debug("", 0, 16, 1, &cptinst, otx_cpt_inst_size, false); + pr_debug("dptr hexdump (%d bytes) ", cpt_req->dlen); + print_hex_dump_debug("", 0, 16, 1, info->in_buffer, + cpt_req->dlen, false); + + /* send cpt command */ + cpt_send_cmd(&cptinst, cptvf); + + /* + * we allocate and prepare pending queue entry in critical section + * together with submitting cpt instruction to cpt instruction queue + * to make sure that order of cpt requests is the same in both + * pending and instruction queues + */ + spin_unlock_bh(&pqueue->lock); + + ret = resume_sender ? -ebusy : -einprogress; + return ret; + +request_cleanup: + do_request_cleanup(pdev, info); + return ret; +} + +int otx_cpt_do_request(struct pci_dev *pdev, struct otx_cpt_req_info *req, + int cpu_num) +{ + struct otx_cptvf *cptvf = pci_get_drvdata(pdev); + + if (!otx_cpt_device_ready(cptvf)) { + dev_err(&pdev->dev, "cpt device is not ready"); + return -enodev; + } + + if ((cptvf->vftype == otx_cpt_se_types) && (!req->ctrl.s.se_req)) { + dev_err(&pdev->dev, "cptvf-%d of se type got ae request", + cptvf->vfid); + return -einval; + } else if ((cptvf->vftype == otx_cpt_ae_types) && + (req->ctrl.s.se_req)) { + dev_err(&pdev->dev, "cptvf-%d of ae type got se request", + cptvf->vfid); + return -einval; + } + + return process_request(pdev, req, &cptvf->pqinfo.queue[0], cptvf); +} + +static int cpt_process_ccode(struct pci_dev *pdev, + union otx_cpt_res_s *cpt_status, + struct otx_cpt_info_buffer *cpt_info, + struct otx_cpt_req_info *req, u32 *res_code) +{ + u8 ccode = cpt_status->s.compcode; + union otx_cpt_error_code ecode; + + ecode.u = be64_to_cpu(*((u64 *) cpt_info->out_buffer)); + switch (ccode) { + case cpt_comp_e_fault: + dev_err(&pdev->dev, + "request failed with dma fault "); + otx_cpt_dump_sg_list(pdev, req); + break; + + case cpt_comp_e_swerr: + dev_err(&pdev->dev, + "request failed with software error code %d ", + ecode.s.ccode); + otx_cpt_dump_sg_list(pdev, req); + break; + + case cpt_comp_e_hwerr: + dev_err(&pdev->dev, + "request failed with hardware error "); + otx_cpt_dump_sg_list(pdev, req); + break; + + case completion_code_init: + /* check for timeout */ + if (time_after_eq(jiffies, cpt_info->time_in + + otx_cpt_command_timeout * hz)) + dev_warn(&pdev->dev, "request timed out 0x%p", req); + else if (cpt_info->extra_time < otx_cpt_time_in_reset_count) { + cpt_info->time_in = jiffies; + cpt_info->extra_time++; + } + return 1; + + case cpt_comp_e_good: + /* check microcode completion code */ + if (ecode.s.ccode) { + /* + * if requested hmac is truncated and ucode returns + * s/g write length error then we report success + * because ucode writes as many bytes of calculated + * hmac as available in gather buffer and reports + * s/g write length error if number of bytes in gather + * buffer is less than full hmac size. + */ + if (req->is_trunc_hmac && + ecode.s.ccode == err_scatter_gather_write_length) { + *res_code = 0; + break; + } + + dev_err(&pdev->dev, + "request failed with software error code 0x%x ", + ecode.s.ccode); + otx_cpt_dump_sg_list(pdev, req); + break; + } + + /* request has been processed with success */ + *res_code = 0; + break; + + default: + dev_err(&pdev->dev, "request returned invalid status "); + break; + } + + return 0; +} + +static inline void process_pending_queue(struct pci_dev *pdev, + struct otx_cpt_pending_queue *pqueue) +{ + void (*callback)(int status, void *arg1, void *arg2); + struct otx_cpt_pending_entry *resume_pentry = null; + struct otx_cpt_pending_entry *pentry = null; + struct otx_cpt_info_buffer *cpt_info = null; + union otx_cpt_res_s *cpt_status = null; + struct otx_cpt_req_info *req = null; + struct crypto_async_request *areq; + u32 res_code, resume_index; + + while (1) { + spin_lock_bh(&pqueue->lock); + pentry = &pqueue->head[pqueue->front]; + + if (warn_on(!pentry)) { + spin_unlock_bh(&pqueue->lock); + break; + } + + res_code = -einval; + if (unlikely(!pentry->busy)) { + spin_unlock_bh(&pqueue->lock); + break; + } + + if (unlikely(!pentry->callback)) { + dev_err(&pdev->dev, "callback null "); + goto process_pentry; + } + + cpt_info = pentry->info; + if (unlikely(!cpt_info)) { + dev_err(&pdev->dev, "pending entry post arg null "); + goto process_pentry; + } + + req = cpt_info->req; + if (unlikely(!req)) { + dev_err(&pdev->dev, "request null "); + goto process_pentry; + } + + cpt_status = (union otx_cpt_res_s *) pentry->completion_addr; + if (unlikely(!cpt_status)) { + dev_err(&pdev->dev, "completion address null "); + goto process_pentry; + } + + if (cpt_process_ccode(pdev, cpt_status, cpt_info, req, + &res_code)) { + spin_unlock_bh(&pqueue->lock); + return; + } + cpt_info->pdev = pdev; + +process_pentry: + /* + * check if we should inform sending side to resume + * we do it cpt_iq_resume_margin elements in advance before + * pending queue becomes empty + */ + resume_index = modulo_inc(pqueue->front, pqueue->qlen, + cpt_iq_resume_margin); + resume_pentry = &pqueue->head[resume_index]; + if (resume_pentry && + resume_pentry->resume_sender) { + resume_pentry->resume_sender = false; + callback = resume_pentry->callback; + areq = resume_pentry->areq; + + if (callback) { + spin_unlock_bh(&pqueue->lock); + + /* + * einprogress is an indication for sending + * side that it can resume sending requests + */ + callback(-einprogress, areq, cpt_info); + spin_lock_bh(&pqueue->lock); + } + } + + callback = pentry->callback; + areq = pentry->areq; + free_pentry(pentry); + + pqueue->pending_count--; + pqueue->front = modulo_inc(pqueue->front, pqueue->qlen, 1); + spin_unlock_bh(&pqueue->lock); + + /* + * call callback after current pending entry has been + * processed, we don't do it if the callback pointer is + * invalid. + */ + if (callback) + callback(res_code, areq, cpt_info); + } +} + +void otx_cpt_post_process(struct otx_cptvf_wqe *wqe) +{ + process_pending_queue(wqe->cptvf->pdev, &wqe->cptvf->pqinfo.queue[0]); +} diff --git a/drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.h b/drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.h --- /dev/null +++ b/drivers/crypto/marvell/octeontx/otx_cptvf_reqmgr.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx cpt driver + * + * copyright (c) 2019 marvell international ltd. + * + * this program is free software; you can redistribute it and/or modify + * it under the terms of the gnu general public license version 2 as + * published by the free software foundation. + */ + +#ifndef __otx_cptvf_request_manager_h +#define __otx_cptvf_request_manager_h + +#include <linux/types.h> +#include <linux/crypto.h> +#include <linux/pci.h> +#include "otx_cpt_hw_types.h" + +/* + * maximum total number of sg buffers is 100, we divide it equally + * between input and output + */ +#define otx_cpt_max_sg_in_cnt 50 +#define otx_cpt_max_sg_out_cnt 50 + +/* dma mode direct or sg */ +#define otx_cpt_dma_direct_direct 0 +#define otx_cpt_dma_gather_scatter 1 + +/* context source cptr or dptr */ +#define otx_cpt_from_cptr 0 +#define otx_cpt_from_dptr 1 + +/* cpt instruction queue alignment */ +#define otx_cpt_inst_q_alignment 128 +#define otx_cpt_max_req_size 65535 + +/* default command timeout in seconds */ +#define otx_cpt_command_timeout 4 +#define otx_cpt_timer_hold 0x03f +#define otx_cpt_count_hold 32 +#define otx_cpt_time_in_reset_count 5 + +/* minimum and maximum values for interrupt coalescing */ +#define otx_cpt_coalesc_min_time_wait 0x0 +#define otx_cpt_coalesc_max_time_wait ((1<<16)-1) +#define otx_cpt_coalesc_min_num_wait 0x0 +#define otx_cpt_coalesc_max_num_wait ((1<<20)-1) + +union otx_cpt_opcode_info { + u16 flags; + struct { + u8 major; + u8 minor; + } s; +}; + +struct otx_cptvf_request { + u32 param1; + u32 param2; + u16 dlen; + union otx_cpt_opcode_info opcode; +}; + +struct otx_cpt_buf_ptr { + u8 *vptr; + dma_addr_t dma_addr; + u16 size; +}; + +union otx_cpt_ctrl_info { + u32 flags; + struct { +#if defined(__big_endian_bitfield) + u32 reserved0:26; + u32 grp:3; /* group bits */ + u32 dma_mode:2; /* dma mode */ + u32 se_req:1; /* to se core */ +#else + u32 se_req:1; /* to se core */ + u32 dma_mode:2; /* dma mode */ + u32 grp:3; /* group bits */ + u32 reserved0:26; +#endif + } s; +}; + +/* + * cpt_inst_s software command definitions + * words ei (0-3) + */ +union otx_cpt_iq_cmd_word0 { + u64 u64; + struct { + u16 opcode; + u16 param1; + u16 param2; + u16 dlen; + } s; +}; + +union otx_cpt_iq_cmd_word3 { + u64 u64; + struct { +#if defined(__big_endian_bitfield) + u64 grp:3; + u64 cptr:61; +#else + u64 cptr:61; + u64 grp:3; +#endif + } s; +}; + +struct otx_cpt_iq_cmd { + union otx_cpt_iq_cmd_word0 cmd; + u64 dptr; + u64 rptr; + union otx_cpt_iq_cmd_word3 cptr; +}; + +struct otx_cpt_sglist_component { + union { + u64 len; + struct { + u16 len0; + u16 len1; + u16 len2; + u16 len3; + } s; + } u; + u64 ptr0; + u64 ptr1; + u64 ptr2; + u64 ptr3; +}; + +struct otx_cpt_pending_entry { + u64 *completion_addr; /* completion address */ + struct otx_cpt_info_buffer *info; + /* kernel async request callback */ + void (*callback)(int status, void *arg1, void *arg2); + struct crypto_async_request *areq; /* async request callback arg */ + u8 resume_sender; /* notify sender to resume sending requests */ + u8 busy; /* entry status (free/busy) */ +}; + +struct otx_cpt_pending_queue { + struct otx_cpt_pending_entry *head; /* head of the queue */ + u32 front; /* process work from here */ + u32 rear; /* append new work here */ + u32 pending_count; /* pending requests count */ + u32 qlen; /* queue length */ + spinlock_t lock; /* queue lock */ +}; + +struct otx_cpt_req_info { + /* kernel async request callback */ + void (*callback)(int status, void *arg1, void *arg2); + struct crypto_async_request *areq; /* async request callback arg */ + struct otx_cptvf_request req;/* request information (core specific) */ + union otx_cpt_ctrl_info ctrl;/* user control information */ + struct otx_cpt_buf_ptr in[otx_cpt_max_sg_in_cnt]; + struct otx_cpt_buf_ptr out[otx_cpt_max_sg_out_cnt]; + u8 *iv_out; /* iv to send back */ + u16 rlen; /* output length */ + u8 incnt; /* number of input buffers */ + u8 outcnt; /* number of output buffers */ + u8 req_type; /* type of request */ + u8 is_enc; /* is a request an encryption request */ + u8 is_trunc_hmac;/* is truncated hmac used */ +}; + +struct otx_cpt_info_buffer { + struct otx_cpt_pending_entry *pentry; + struct otx_cpt_req_info *req; + struct pci_dev *pdev; + u64 *completion_addr; + u8 *out_buffer; + u8 *in_buffer; + dma_addr_t dptr_baddr; + dma_addr_t rptr_baddr; + dma_addr_t comp_baddr; + unsigned long time_in; + u32 dlen; + u32 dma_len; + u8 extra_time; +}; + +static inline void do_request_cleanup(struct pci_dev *pdev, + struct otx_cpt_info_buffer *info) +{ + struct otx_cpt_req_info *req; + int i; + + if (info->dptr_baddr) + dma_unmap_single(&pdev->dev, info->dptr_baddr, + info->dma_len, dma_bidirectional); + + if (info->req) { + req = info->req; + for (i = 0; i < req->outcnt; i++) { + if (req->out[i].dma_addr) + dma_unmap_single(&pdev->dev, + req->out[i].dma_addr, + req->out[i].size, + dma_bidirectional); + } + + for (i = 0; i < req->incnt; i++) { + if (req->in[i].dma_addr) + dma_unmap_single(&pdev->dev, + req->in[i].dma_addr, + req->in[i].size, + dma_bidirectional); + } + } + kzfree(info); +} + +struct otx_cptvf_wqe; +void otx_cpt_dump_sg_list(struct pci_dev *pdev, struct otx_cpt_req_info *req); +void otx_cpt_post_process(struct otx_cptvf_wqe *wqe); +int otx_cpt_do_request(struct pci_dev *pdev, struct otx_cpt_req_info *req, + int cpu_num); + +#endif /* __otx_cptvf_request_manager_h */
|
Cryptography hardware acceleration
|
10b4f09491bfeb0b298cb2f49df585510ee6189a
|
srujanachalla
|
drivers
|
crypto
|
marvell, octeontx
|
crypto: marvell - enable octeontx cpt options for build
|
add the octeontx cpt options in crypto kconfig and makefile
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
support for marvell octeontx cpt driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['marvell']
|
['kconfig', 'makefile']
| 2
| 17
| 0
|
--- diff --git a/drivers/crypto/marvell/kconfig b/drivers/crypto/marvell/kconfig --- a/drivers/crypto/marvell/kconfig +++ b/drivers/crypto/marvell/kconfig + +config crypto_dev_octeontx_cpt + tristate "support for marvell octeontx cpt driver" + depends on arch_thunder || compile_test + depends on pci_msi && 64bit + depends on crypto_lib_aes + select crypto_skcipher + select crypto_hash + select crypto_aead + select crypto_dev_marvell + help + this driver allows you to utilize the marvell cryptographic + accelerator unit(cpt) found in octeontx series of processors. + + to compile this driver as module, choose m here: + the modules will be called octeontx-cpt and octeontx-cptvf diff --git a/drivers/crypto/marvell/makefile b/drivers/crypto/marvell/makefile --- a/drivers/crypto/marvell/makefile +++ b/drivers/crypto/marvell/makefile +obj-$(config_crypto_dev_octeontx_cpt) += octeontx/
|
Cryptography hardware acceleration
|
6482023b9d3350bf1b756ef36e1ea1a1c871879c
|
srujanachalla
|
drivers
|
crypto
|
marvell
|
crypto: xilinx - add xilinx aes driver
|
this patch adds aes driver support for the xilinx zynqmp soc.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
xilinx - add xilinx aes driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 4
| 472
| 0
|
--- diff --git a/drivers/crypto/kconfig b/drivers/crypto/kconfig --- a/drivers/crypto/kconfig +++ b/drivers/crypto/kconfig +config crypto_dev_zynqmp_aes + tristate "support for xilinx zynqmp aes hw accelerator" + depends on zynqmp_firmware || compile_test + select crypto_aes + select crypto_engine + select crypto_aead + help + xilinx zynqmp has aes-gcm engine used for symmetric key + encryption and decryption. this driver interfaces with aes hw + accelerator. select this if you want to use the zynqmp module + for aes algorithms. + diff --git a/drivers/crypto/makefile b/drivers/crypto/makefile --- a/drivers/crypto/makefile +++ b/drivers/crypto/makefile +obj-$(config_crypto_dev_zynqmp_aes) += xilinx/ diff --git a/drivers/crypto/xilinx/makefile b/drivers/crypto/xilinx/makefile --- /dev/null +++ b/drivers/crypto/xilinx/makefile +# spdx-license-identifier: gpl-2.0-only +obj-$(config_crypto_dev_zynqmp_aes) += zynqmp-aes-gcm.o diff --git a/drivers/crypto/xilinx/zynqmp-aes-gcm.c b/drivers/crypto/xilinx/zynqmp-aes-gcm.c --- /dev/null +++ b/drivers/crypto/xilinx/zynqmp-aes-gcm.c +// spdx-license-identifier: gpl-2.0 +/* + * xilinx zynqmp aes driver. + * copyright (c) 2020 xilinx inc. + */ + +#include <crypto/aes.h> +#include <crypto/engine.h> +#include <crypto/gcm.h> +#include <crypto/internal/aead.h> +#include <crypto/scatterwalk.h> + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> + +#include <linux/firmware/xlnx-zynqmp.h> + +#define zynqmp_dma_bit_mask 32u + +#define zynqmp_aes_key_size aes_keysize_256 +#define zynqmp_aes_auth_size 16u +#define zynqmp_key_src_sel_key_len 1u +#define zynqmp_aes_blk_size 1u +#define zynqmp_aes_min_input_blk_size 4u +#define zynqmp_aes_word_len 4u + +#define zynqmp_aes_gcm_tag_mismatch_err 0x01 +#define zynqmp_aes_wrong_key_src_err 0x13 +#define zynqmp_aes_puf_not_programmed 0xe300 + +enum zynqmp_aead_op { + zynqmp_aes_decrypt = 0, + zynqmp_aes_encrypt +}; + +enum zynqmp_aead_keysrc { + zynqmp_aes_kup_key = 0, + zynqmp_aes_dev_key, + zynqmp_aes_puf_key +}; + +struct zynqmp_aead_drv_ctx { + union { + struct aead_alg aead; + } alg; + struct device *dev; + struct crypto_engine *engine; + const struct zynqmp_eemi_ops *eemi_ops; +}; + +struct zynqmp_aead_hw_req { + u64 src; + u64 iv; + u64 key; + u64 dst; + u64 size; + u64 op; + u64 keysrc; +}; + +struct zynqmp_aead_tfm_ctx { + struct crypto_engine_ctx engine_ctx; + struct device *dev; + u8 key[zynqmp_aes_key_size]; + u8 *iv; + u32 keylen; + u32 authsize; + enum zynqmp_aead_keysrc keysrc; + struct crypto_aead *fbk_cipher; +}; + +struct zynqmp_aead_req_ctx { + enum zynqmp_aead_op op; +}; + +static int zynqmp_aes_aead_cipher(struct aead_request *req) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead); + struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); + struct device *dev = tfm_ctx->dev; + struct aead_alg *alg = crypto_aead_alg(aead); + struct zynqmp_aead_drv_ctx *drv_ctx; + struct zynqmp_aead_hw_req *hwreq; + dma_addr_t dma_addr_data, dma_addr_hw_req; + unsigned int data_size; + unsigned int status; + size_t dma_size; + char *kbuf; + int err; + + drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); + + if (!drv_ctx->eemi_ops->aes) + return -enotsupp; + + if (tfm_ctx->keysrc == zynqmp_aes_kup_key) + dma_size = req->cryptlen + zynqmp_aes_key_size + + gcm_aes_iv_size; + else + dma_size = req->cryptlen + gcm_aes_iv_size; + + kbuf = dma_alloc_coherent(dev, dma_size, &dma_addr_data, gfp_kernel); + if (!kbuf) + return -enomem; + + hwreq = dma_alloc_coherent(dev, sizeof(struct zynqmp_aead_hw_req), + &dma_addr_hw_req, gfp_kernel); + if (!hwreq) { + dma_free_coherent(dev, dma_size, kbuf, dma_addr_data); + return -enomem; + } + + data_size = req->cryptlen; + scatterwalk_map_and_copy(kbuf, req->src, 0, req->cryptlen, 0); + memcpy(kbuf + data_size, req->iv, gcm_aes_iv_size); + + hwreq->src = dma_addr_data; + hwreq->dst = dma_addr_data; + hwreq->iv = hwreq->src + data_size; + hwreq->keysrc = tfm_ctx->keysrc; + hwreq->op = rq_ctx->op; + + if (hwreq->op == zynqmp_aes_encrypt) + hwreq->size = data_size; + else + hwreq->size = data_size - zynqmp_aes_auth_size; + + if (hwreq->keysrc == zynqmp_aes_kup_key) { + memcpy(kbuf + data_size + gcm_aes_iv_size, + tfm_ctx->key, zynqmp_aes_key_size); + + hwreq->key = hwreq->src + data_size + gcm_aes_iv_size; + } else { + hwreq->key = 0; + } + + drv_ctx->eemi_ops->aes(dma_addr_hw_req, &status); + + if (status) { + switch (status) { + case zynqmp_aes_gcm_tag_mismatch_err: + dev_err(dev, "error: gcm tag mismatch "); + break; + case zynqmp_aes_wrong_key_src_err: + dev_err(dev, "error: wrong keysrc, enable secure mode "); + break; + case zynqmp_aes_puf_not_programmed: + dev_err(dev, "error: puf is not registered "); + break; + default: + dev_err(dev, "error: unknown error "); + break; + } + err = -status; + } else { + if (hwreq->op == zynqmp_aes_encrypt) + data_size = data_size + zynqmp_aes_auth_size; + else + data_size = data_size - zynqmp_aes_auth_size; + + sg_copy_from_buffer(req->dst, sg_nents(req->dst), + kbuf, data_size); + err = 0; + } + + if (kbuf) { + memzero_explicit(kbuf, dma_size); + dma_free_coherent(dev, dma_size, kbuf, dma_addr_data); + } + if (hwreq) { + memzero_explicit(hwreq, sizeof(struct zynqmp_aead_hw_req)); + dma_free_coherent(dev, sizeof(struct zynqmp_aead_hw_req), + hwreq, dma_addr_hw_req); + } + return err; +} + +static int zynqmp_fallback_check(struct zynqmp_aead_tfm_ctx *tfm_ctx, + struct aead_request *req) +{ + int need_fallback = 0; + struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); + + if (tfm_ctx->authsize != zynqmp_aes_auth_size) + need_fallback = 1; + + if (tfm_ctx->keysrc == zynqmp_aes_kup_key && + tfm_ctx->keylen != zynqmp_aes_key_size) { + need_fallback = 1; + } + if (req->assoclen != 0 || + req->cryptlen < zynqmp_aes_min_input_blk_size) { + need_fallback = 1; + } + if ((req->cryptlen % zynqmp_aes_word_len) != 0) + need_fallback = 1; + + if (rq_ctx->op == zynqmp_aes_decrypt && + req->cryptlen <= zynqmp_aes_auth_size) { + need_fallback = 1; + } + return need_fallback; +} + +static int zynqmp_handle_aes_req(struct crypto_engine *engine, + void *req) +{ + struct aead_request *areq = + container_of(req, struct aead_request, base); + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct zynqmp_aead_tfm_ctx *tfm_ctx = crypto_aead_ctx(aead); + struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(areq); + struct aead_request *subreq = aead_request_ctx(req); + int need_fallback; + int err; + + need_fallback = zynqmp_fallback_check(tfm_ctx, areq); + + if (need_fallback) { + aead_request_set_tfm(subreq, tfm_ctx->fbk_cipher); + + aead_request_set_callback(subreq, areq->base.flags, + null, null); + aead_request_set_crypt(subreq, areq->src, areq->dst, + areq->cryptlen, areq->iv); + aead_request_set_ad(subreq, areq->assoclen); + if (rq_ctx->op == zynqmp_aes_encrypt) + err = crypto_aead_encrypt(subreq); + else + err = crypto_aead_decrypt(subreq); + } else { + err = zynqmp_aes_aead_cipher(areq); + } + + crypto_finalize_aead_request(engine, areq, err); + return 0; +} + +static int zynqmp_aes_aead_setkey(struct crypto_aead *aead, const u8 *key, + unsigned int keylen) +{ + struct crypto_tfm *tfm = crypto_aead_tfm(aead); + struct zynqmp_aead_tfm_ctx *tfm_ctx = + (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); + unsigned char keysrc; + + if (keylen == zynqmp_key_src_sel_key_len) { + keysrc = *key; + if (keysrc == zynqmp_aes_kup_key || + keysrc == zynqmp_aes_dev_key || + keysrc == zynqmp_aes_puf_key) { + tfm_ctx->keysrc = (enum zynqmp_aead_keysrc)keysrc; + } else { + tfm_ctx->keylen = keylen; + } + } else { + tfm_ctx->keylen = keylen; + if (keylen == zynqmp_aes_key_size) { + tfm_ctx->keysrc = zynqmp_aes_kup_key; + memcpy(tfm_ctx->key, key, keylen); + } + } + + tfm_ctx->fbk_cipher->base.crt_flags &= ~crypto_tfm_req_mask; + tfm_ctx->fbk_cipher->base.crt_flags |= (aead->base.crt_flags & + crypto_tfm_req_mask); + + return crypto_aead_setkey(tfm_ctx->fbk_cipher, key, keylen); +} + +static int zynqmp_aes_aead_setauthsize(struct crypto_aead *aead, + unsigned int authsize) +{ + struct crypto_tfm *tfm = crypto_aead_tfm(aead); + struct zynqmp_aead_tfm_ctx *tfm_ctx = + (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); + + tfm_ctx->authsize = authsize; + return crypto_aead_setauthsize(tfm_ctx->fbk_cipher, authsize); +} + +static int zynqmp_aes_aead_encrypt(struct aead_request *req) +{ + struct zynqmp_aead_drv_ctx *drv_ctx; + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct aead_alg *alg = crypto_aead_alg(aead); + struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); + + rq_ctx->op = zynqmp_aes_encrypt; + drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); + + return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req); +} + +static int zynqmp_aes_aead_decrypt(struct aead_request *req) +{ + struct zynqmp_aead_drv_ctx *drv_ctx; + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct aead_alg *alg = crypto_aead_alg(aead); + struct zynqmp_aead_req_ctx *rq_ctx = aead_request_ctx(req); + + rq_ctx->op = zynqmp_aes_decrypt; + drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); + + return crypto_transfer_aead_request_to_engine(drv_ctx->engine, req); +} + +static int zynqmp_aes_aead_init(struct crypto_aead *aead) +{ + struct crypto_tfm *tfm = crypto_aead_tfm(aead); + struct zynqmp_aead_tfm_ctx *tfm_ctx = + (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); + struct zynqmp_aead_drv_ctx *drv_ctx; + struct aead_alg *alg = crypto_aead_alg(aead); + + drv_ctx = container_of(alg, struct zynqmp_aead_drv_ctx, alg.aead); + tfm_ctx->dev = drv_ctx->dev; + + tfm_ctx->engine_ctx.op.do_one_request = zynqmp_handle_aes_req; + tfm_ctx->engine_ctx.op.prepare_request = null; + tfm_ctx->engine_ctx.op.unprepare_request = null; + + tfm_ctx->fbk_cipher = crypto_alloc_aead(drv_ctx->alg.aead.base.cra_name, + 0, + crypto_alg_need_fallback); + + if (is_err(tfm_ctx->fbk_cipher)) { + pr_err("%s() error: failed to allocate fallback for %s ", + __func__, drv_ctx->alg.aead.base.cra_name); + return ptr_err(tfm_ctx->fbk_cipher); + } + + crypto_aead_set_reqsize(aead, + max(sizeof(struct zynqmp_aead_req_ctx), + sizeof(struct aead_request) + + crypto_aead_reqsize(tfm_ctx->fbk_cipher))); + return 0; +} + +static void zynqmp_aes_aead_exit(struct crypto_aead *aead) +{ + struct crypto_tfm *tfm = crypto_aead_tfm(aead); + struct zynqmp_aead_tfm_ctx *tfm_ctx = + (struct zynqmp_aead_tfm_ctx *)crypto_tfm_ctx(tfm); + + if (tfm_ctx->fbk_cipher) { + crypto_free_aead(tfm_ctx->fbk_cipher); + tfm_ctx->fbk_cipher = null; + } + memzero_explicit(tfm_ctx, sizeof(struct zynqmp_aead_tfm_ctx)); +} + +static struct zynqmp_aead_drv_ctx aes_drv_ctx = { + .alg.aead = { + .setkey = zynqmp_aes_aead_setkey, + .setauthsize = zynqmp_aes_aead_setauthsize, + .encrypt = zynqmp_aes_aead_encrypt, + .decrypt = zynqmp_aes_aead_decrypt, + .init = zynqmp_aes_aead_init, + .exit = zynqmp_aes_aead_exit, + .ivsize = gcm_aes_iv_size, + .maxauthsize = zynqmp_aes_auth_size, + .base = { + .cra_name = "gcm(aes)", + .cra_driver_name = "xilinx-zynqmp-aes-gcm", + .cra_priority = 200, + .cra_flags = crypto_alg_type_aead | + crypto_alg_async | + crypto_alg_kern_driver_only | + crypto_alg_need_fallback, + .cra_blocksize = zynqmp_aes_blk_size, + .cra_ctxsize = sizeof(struct zynqmp_aead_tfm_ctx), + .cra_module = this_module, + } + } +}; + +static int zynqmp_aes_aead_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int err; + + /* zynqmp aes driver supports only one instance */ + if (!aes_drv_ctx.dev) + aes_drv_ctx.dev = dev; + else + return -enodev; + + aes_drv_ctx.eemi_ops = zynqmp_pm_get_eemi_ops(); + if (is_err(aes_drv_ctx.eemi_ops)) { + dev_err(dev, "failed to get zynqmp eemi interface "); + return ptr_err(aes_drv_ctx.eemi_ops); + } + + err = dma_set_mask_and_coherent(dev, dma_bit_mask(zynqmp_dma_bit_mask)); + if (err < 0) { + dev_err(dev, "no usable dma configuration "); + return err; + } + + aes_drv_ctx.engine = crypto_engine_alloc_init(dev, 1); + if (!aes_drv_ctx.engine) { + dev_err(dev, "cannot alloc aes engine "); + err = -enomem; + goto err_engine; + } + + err = crypto_engine_start(aes_drv_ctx.engine); + if (err) { + dev_err(dev, "cannot start aes engine "); + goto err_engine; + } + + err = crypto_register_aead(&aes_drv_ctx.alg.aead); + if (err < 0) { + dev_err(dev, "failed to register aead alg. "); + goto err_aead; + } + return 0; + +err_aead: + crypto_unregister_aead(&aes_drv_ctx.alg.aead); + +err_engine: + if (aes_drv_ctx.engine) + crypto_engine_exit(aes_drv_ctx.engine); + + return err; +} + +static int zynqmp_aes_aead_remove(struct platform_device *pdev) +{ + crypto_engine_exit(aes_drv_ctx.engine); + crypto_unregister_aead(&aes_drv_ctx.alg.aead); + + return 0; +} + +static const struct of_device_id zynqmp_aes_dt_ids[] = { + { .compatible = "xlnx,zynqmp-aes" }, + { /* sentinel */ } +}; +module_device_table(of, zynqmp_aes_dt_ids); + +static struct platform_driver zynqmp_aes_driver = { + .probe = zynqmp_aes_aead_probe, + .remove = zynqmp_aes_aead_remove, + .driver = { + .name = "zynqmp-aes", + .of_match_table = zynqmp_aes_dt_ids, + }, +}; + +module_platform_driver(zynqmp_aes_driver); +module_license("gpl");
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Cryptography hardware acceleration
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4d96f7d48131fefe30d7c1d1e2a23ef37164dbf5
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kalyani akula michal simek michal simek xilinx com
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drivers
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crypto
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xilinx
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pci/err: update error status after reset_link()
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commit bdb5ac85777d ("pci/err: handle fatal error recovery") uses reset_link() to recover from fatal errors. but during fatal error recovery, if the initial value of error status is pci_ers_result_disconnect or pci_ers_result_no_aer_driver then even after successful recovery (using reset_link()) pcie_do_recovery() will report the recovery result as failure. update the status of error after reset_link().
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for error disconnect recover (edr, you can find edr spec
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
|
['c']
| 1
| 2
| 1
|
--- diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c - if (reset_link(dev, service) != pci_ers_result_recovered) + status = reset_link(dev, service); + if (status != pci_ers_result_recovered)
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PCI
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6d2c89441571ea534d6240f7724f518936c44f8d
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kuppuswamy sathyanarayanan
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drivers
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pci
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pcie
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pci/dpc: move dpc data into struct pci_dev
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we only need 25 bits of data for dpc, so i don't think it's worth the complexity of allocating and keeping track of the struct dpc_dev separately from the pci_dev. move that data into the struct pci_dev.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for error disconnect recover (edr, you can find edr spec
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
|
['h', 'c']
| 2
| 36
| 72
|
--- diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c -struct dpc_dev { - struct pcie_device *dev; - u16 cap_pos; - bool rp_extensions; - u8 rp_log_size; -}; - -static struct dpc_dev *to_dpc_dev(struct pci_dev *dev) -{ - struct device *device; - - device = pcie_port_find_device(dev, pcie_port_service_dpc); - if (!device) - return null; - return get_service_data(to_pcie_device(device)); -} - - struct dpc_dev *dpc; - dpc = to_dpc_dev(dev); - if (!dpc) - return; - - pci_read_config_word(dev, dpc->cap_pos + pci_exp_dpc_ctl, cap); + pci_read_config_word(dev, dev->dpc_cap + pci_exp_dpc_ctl, cap); - struct dpc_dev *dpc; - dpc = to_dpc_dev(dev); - if (!dpc) - return; - - pci_write_config_word(dev, dpc->cap_pos + pci_exp_dpc_ctl, *cap); + pci_write_config_word(dev, dev->dpc_cap + pci_exp_dpc_ctl, *cap); -static int dpc_wait_rp_inactive(struct dpc_dev *dpc) +static int dpc_wait_rp_inactive(struct pci_dev *pdev) - struct pci_dev *pdev = dpc->dev->port; - u16 cap = dpc->cap_pos, status; + u16 cap = pdev->dpc_cap, status; - struct dpc_dev *dpc; - dpc = to_dpc_dev(pdev); - cap = dpc->cap_pos; + cap = pdev->dpc_cap; - if (dpc->rp_extensions && dpc_wait_rp_inactive(dpc)) + if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) -static void dpc_process_rp_pio_error(struct dpc_dev *dpc) +static void dpc_process_rp_pio_error(struct pci_dev *pdev) - struct pci_dev *pdev = dpc->dev->port; - u16 cap = dpc->cap_pos, dpc_status, first_error; + u16 cap = pdev->dpc_cap, dpc_status, first_error; - if (dpc->rp_log_size < 4) + if (pdev->dpc_rp_log_size < 4) - if (dpc->rp_log_size < 5) + if (pdev->dpc_rp_log_size < 5) - for (i = 0; i < dpc->rp_log_size - 5; i++) { + for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) { + struct pci_dev *pdev = context; + u16 cap = pdev->dpc_cap, status, source, reason, ext_reason; - struct dpc_dev *dpc = context; - struct pci_dev *pdev = dpc->dev->port; - u16 cap = dpc->cap_pos, status, source, reason, ext_reason; - if (dpc->rp_extensions && reason == 3 && ext_reason == 0) - dpc_process_rp_pio_error(dpc); + if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0) + dpc_process_rp_pio_error(pdev); - struct dpc_dev *dpc = (struct dpc_dev *)context; - struct pci_dev *pdev = dpc->dev->port; - u16 cap = dpc->cap_pos, status; + struct pci_dev *pdev = context; + u16 cap = pdev->dpc_cap, status; - struct dpc_dev *dpc; - dpc = devm_kzalloc(device, sizeof(*dpc), gfp_kernel); - if (!dpc) - return -enomem; - - dpc->cap_pos = pci_find_ext_capability(pdev, pci_ext_cap_id_dpc); - dpc->dev = dev; - set_service_data(dev, dpc); + pdev->dpc_cap = pci_find_ext_capability(pdev, pci_ext_cap_id_dpc); - "pcie-dpc", dpc); + "pcie-dpc", pdev); - pci_read_config_word(pdev, dpc->cap_pos + pci_exp_dpc_cap, &cap); - pci_read_config_word(pdev, dpc->cap_pos + pci_exp_dpc_ctl, &ctl); + pci_read_config_word(pdev, pdev->dpc_cap + pci_exp_dpc_cap, &cap); + pci_read_config_word(pdev, pdev->dpc_cap + pci_exp_dpc_ctl, &ctl); - dpc->rp_extensions = (cap & pci_exp_dpc_cap_rp_ext); - if (dpc->rp_extensions) { - dpc->rp_log_size = (cap & pci_exp_dpc_rp_pio_log_size) >> 8; - if (dpc->rp_log_size < 4 || dpc->rp_log_size > 9) { + pdev->dpc_rp_extensions = (cap & pci_exp_dpc_cap_rp_ext) ? 1 : 0; + if (pdev->dpc_rp_extensions) { + pdev->dpc_rp_log_size = (cap & pci_exp_dpc_rp_pio_log_size) >> 8; + if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { - dpc->rp_log_size); - dpc->rp_log_size = 0; + pdev->dpc_rp_log_size); + pdev->dpc_rp_log_size = 0; - pci_write_config_word(pdev, dpc->cap_pos + pci_exp_dpc_ctl, ctl); + pci_write_config_word(pdev, pdev->dpc_cap + pci_exp_dpc_ctl, ctl); - flag(cap, pci_exp_dpc_cap_sw_trigger), dpc->rp_log_size, + flag(cap, pci_exp_dpc_cap_sw_trigger), pdev->dpc_rp_log_size, - struct dpc_dev *dpc = get_service_data(dev); - pci_read_config_word(pdev, dpc->cap_pos + pci_exp_dpc_ctl, &ctl); + pci_read_config_word(pdev, pdev->dpc_cap + pci_exp_dpc_ctl, &ctl); - pci_write_config_word(pdev, dpc->cap_pos + pci_exp_dpc_ctl, ctl); + pci_write_config_word(pdev, pdev->dpc_cap + pci_exp_dpc_ctl, ctl); diff --git a/include/linux/pci.h b/include/linux/pci.h --- a/include/linux/pci.h +++ b/include/linux/pci.h +#ifdef config_pcie_dpc + u16 dpc_cap; + unsigned int dpc_rp_extensions:1; + u8 dpc_rp_log_size; +#endif
|
PCI
|
be06c1b42eea749547d2f0248dc0a7c1153f67b9
|
bjorn helgaas
|
include
|
linux
|
pcie
|
pci/err: remove service dependency in pcie_do_recovery()
|
previously we passed the pcie service type parameter to pcie_do_recovery(), where reset_link() looked up the underlying pci_port_service_driver and its .reset_link() function pointer. instead of using this roundabout way, we can just pass the driver-specific .reset_link() callback function when calling pcie_do_recovery() function.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c', 'rst']
| 7
| 18
| 96
|
--- diff --git a/documentation/pci/pcieaer-howto.rst b/documentation/pci/pcieaer-howto.rst --- a/documentation/pci/pcieaer-howto.rst +++ b/documentation/pci/pcieaer-howto.rst -in struct pcie_port_service_driver, a new pointer, reset_link, is -added. -:: - - pci_ers_result_t (*reset_link) (struct pci_dev *dev); - -function to reset link. firstly, kernel looks for if the upstream -component has an aer driver. if it has, kernel uses the reset_link -callback of the aer driver. if the upstream component has no aer driver -and the port is downstream port, we will perform a hot reset as the -default by setting the secondary bus reset bit of the bridge control -register associated with the downstream port. as for upstream ports, -they should provide their own aer service drivers with reset_link -function. if error_detected returns pci_ers_result_can_recover and -reset_link returns pci_ers_result_recovered, the error handling goes +function to reset link via callback parameter of pcie_do_recovery() +function. if reset_link is not null, recovery function will use it +to reset the link. if error_detected returns pci_ers_result_can_recover +and reset_link returns pci_ers_result_recovered, the error handling goes diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h - u32 service); + pci_ers_result_t (*reset_link)(struct pci_dev *pdev)); diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c +static pci_ers_result_t aer_root_reset(struct pci_dev *dev); - pcie_do_recovery(dev, pci_channel_io_normal, - pcie_port_service_aer); + pcie_do_recovery(dev, pci_channel_io_normal, aer_root_reset); - pcie_do_recovery(dev, pci_channel_io_frozen, - pcie_port_service_aer); + pcie_do_recovery(dev, pci_channel_io_frozen, aer_root_reset); - pcie_port_service_aer); + aer_root_reset); - pcie_port_service_aer); + aer_root_reset); - .reset_link = aer_root_reset, diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c - pcie_do_recovery(pdev, pci_channel_io_frozen, pcie_port_service_dpc); + pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link); - .reset_link = dpc_reset_link, diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c -/** - * default_reset_link - default reset function - * @dev: pointer to pci_dev data structure - * - * invoked when performing link reset on a downstream port or a - * root port with no aer driver. - */ -static pci_ers_result_t default_reset_link(struct pci_dev *dev) -{ - int rc; - - rc = pci_bus_error_reset(dev); - pci_printk(kern_debug, dev, "downstream link has been reset "); - return rc ? pci_ers_result_disconnect : pci_ers_result_recovered; -} - -static pci_ers_result_t reset_link(struct pci_dev *dev, u32 service) -{ - pci_ers_result_t status; - struct pcie_port_service_driver *driver = null; - - driver = pcie_port_find_service(dev, service); - if (driver && driver->reset_link) { - status = driver->reset_link(dev); - } else if (pcie_downstream_port(dev)) { - status = default_reset_link(dev); - } else { - pci_printk(kern_debug, dev, "no link-reset support at upstream device %s ", - pci_name(dev)); - return pci_ers_result_disconnect; - } - - if (status != pci_ers_result_recovered) { - pci_printk(kern_debug, dev, "link reset at upstream device %s failed ", - pci_name(dev)); - return pci_ers_result_disconnect; - } - - return status; -} - -void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, - u32 service) +void pcie_do_recovery(struct pci_dev *dev, + enum pci_channel_state state, + pci_ers_result_t (*reset_link)(struct pci_dev *pdev)) - status = reset_link(dev, service); - if (status != pci_ers_result_recovered) + status = reset_link(dev); + if (status != pci_ers_result_recovered) { + pci_warn(dev, "link reset failed "); + } diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h - /* link reset capability - aer service driver specific */ - pci_ers_result_t (*reset_link)(struct pci_dev *dev); - -struct pcie_port_service_driver *pcie_port_find_service(struct pci_dev *dev, - u32 service); diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c --- a/drivers/pci/pcie/portdrv_core.c +++ b/drivers/pci/pcie/portdrv_core.c -/** - * pcie_port_find_service - find the service driver - * @dev: pci express port the service is associated with - * @service: service to find - * - * find pci express port service driver associated with given service - */ -struct pcie_port_service_driver *pcie_port_find_service(struct pci_dev *dev, - u32 service) -{ - struct pcie_port_service_driver *drv; - struct portdrv_service_data pdrvs; - - pdrvs.drv = null; - pdrvs.service = service; - device_for_each_child(&dev->dev, &pdrvs, find_service_iter); - - drv = pdrvs.drv; - return drv; -} -
|
PCI
|
b6cf1a42f916af0b056079c37fc5fa7bf8e4b2e2
|
kuppuswamy sathyanarayanan
|
drivers
|
pci
|
pcie
|
pci/err: return status of pcie_do_recovery()
|
as per the dpc enhancements ecn [1], sec 4.5.1, table 4-4, if the os supports error disconnect recover (edr), it must invalidate the software state associated with child devices of the port without attempting to access the child device hardware. in addition, if the os supports dpc, it must attempt to recover the child devices if the port implements the dpc capability. if the os continues operation, the os must inform the firmware of the status of the recovery operation via the _ost method.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 2
| 9
| 6
|
--- diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h -void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state, - pci_ers_result_t (*reset_link)(struct pci_dev *pdev)); +pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, + enum pci_channel_state state, + pci_ers_result_t (*reset_link)(struct pci_dev *pdev)); diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c -void pcie_do_recovery(struct pci_dev *dev, - enum pci_channel_state state, - pci_ers_result_t (*reset_link)(struct pci_dev *pdev)) +pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, + enum pci_channel_state state, + pci_ers_result_t (*reset_link)(struct pci_dev *pdev)) - return; + return status; + + return status;
|
PCI
|
e8e5ff2aeec19ade42f0535f4b554a3f6e1a58f7
|
kuppuswamy sathyanarayanan
|
drivers
|
pci
|
pcie
|
pci/dpc: cache dpc capabilities in pci_init_capabilities()
|
since error disconnect recover needs to use dpc error handling routines even if the os doesn't have control of dpc, move the initalization and caching of dpc capabilities from the dpc driver to pci_init_capabilities().
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 3
| 24
| 12
|
--- diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h +void pci_dpc_init(struct pci_dev *pdev); +static inline void pci_dpc_init(struct pci_dev *pdev) {} diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c +void pci_dpc_init(struct pci_dev *pdev) +{ + u16 cap; + + pdev->dpc_cap = pci_find_ext_capability(pdev, pci_ext_cap_id_dpc); + if (!pdev->dpc_cap) + return; + + pci_read_config_word(pdev, pdev->dpc_cap + pci_exp_dpc_cap, &cap); + if (!(cap & pci_exp_dpc_cap_rp_ext)) + return; + + pdev->dpc_rp_extensions = true; + pdev->dpc_rp_log_size = (cap & pci_exp_dpc_rp_pio_log_size) >> 8; + if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { + pci_err(pdev, "rp pio log size %u is invalid ", + pdev->dpc_rp_log_size); + pdev->dpc_rp_log_size = 0; + } +} + - pdev->dpc_cap = pci_find_ext_capability(pdev, pci_ext_cap_id_dpc); - - pdev->dpc_rp_extensions = (cap & pci_exp_dpc_cap_rp_ext) ? 1 : 0; - if (pdev->dpc_rp_extensions) { - pdev->dpc_rp_log_size = (cap & pci_exp_dpc_rp_pio_log_size) >> 8; - if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) { - pci_err(pdev, "rp pio log size %u is invalid ", - pdev->dpc_rp_log_size); - pdev->dpc_rp_log_size = 0; - } - } - diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c + pci_dpc_init(dev); /* downstream port containment */
|
PCI
|
27005618178ef9e9bf9c42fd91101771c92e9308
|
kuppuswamy sathyanarayanan
|
drivers
|
pci
|
pcie
|
pci/aer: add pci_aer_raw_clear_status() to unconditionally clear error status
|
per the sfi _osc and dpc updates ecn [1] implementation note flowchart, the os seems to be expected to clear aer status even if it doesn't have ownership of the aer capability. unlike the dpc capability, where a dpc ecn [2] specifies a window when the os is allowed to access dpc registers even if it doesn't have ownership, there is no clear model for aer.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 2
| 20
| 4
|
--- diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h +int pci_aer_raw_clear_status(struct pci_dev *dev); +static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -einval; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c -int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) +/** + * pci_aer_raw_clear_status - clear aer error registers. + * @dev: the pci device + * + * clearing aer error status registers unconditionally, regardless of + * whether they're owned by firmware or the os. + * + * returns 0 on success, or negative on failure. + */ +int pci_aer_raw_clear_status(struct pci_dev *dev) - if (pcie_aer_get_firmware_first(dev)) - return -eio; - +int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) +{ + if (pcie_aer_get_firmware_first(dev)) + return -eio; + + return pci_aer_raw_clear_status(dev); +} +
|
PCI
|
20e15e673b05a045fdbe534d40edf948e1b0b1af
|
kuppuswamy sathyanarayanan
|
drivers
|
pci
|
pcie
|
pci/dpc: expose dpc_process_error(), dpc_reset_link() for use by edr
|
if firmware controls dpc, it is generally responsible for managing the dpc capability and events, and the os should not access the dpc capability.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 2
| 11
| 3
|
--- diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h +void dpc_process_error(struct pci_dev *pdev); +pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c -static pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) +pci_ers_result_t dpc_reset_link(struct pci_dev *pdev) -static irqreturn_t dpc_handler(int irq, void *context) +void dpc_process_error(struct pci_dev *pdev) - struct pci_dev *pdev = context; +} + +static irqreturn_t dpc_handler(int irq, void *context) +{ + struct pci_dev *pdev = context; + + dpc_process_error(pdev);
|
PCI
|
aea47413e7ceec6024f5a2b743cb1a4b2176bf3f
|
kuppuswamy sathyanarayanan
|
drivers
|
pci
|
pcie
|
pci/dpc: add error disconnect recover (edr) support
|
error disconnect recover (edr) is a feature that allows acpi firmware to notify ospm that a device has been disconnected due to an error condition (acpi v6.3, sec 5.6.6). ospm advertises its support for edr on pci devices via _osc (see [1], sec 4.5.1, table 4-4). the ospm edr notify handler should invalidate software state associated with disconnected devices and may attempt to recover them. ospm communicates the status of recovery to the firmware via _ost (sec 6.3.5.2).
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['kconfig', 'h', 'c', 'makefile']
| 9
| 281
| 2
|
--- diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c + { osc_pci_edr_support, "edr" }, + { osc_pci_express_dpc_control, "dpc" }, + if (is_enabled(config_pcie_edr)) + support |= osc_pci_edr_support; + /* + * per the downstream port containment related enhancements ecn to + * the pci firmware spec, r3.2, sec 4.5.1, table 4-5, + * osc_pci_express_dpc_control indicates the os supports both dpc + * and edr. + */ + if (is_enabled(config_pcie_dpc) && is_enabled(config_pcie_edr)) + control |= osc_pci_express_dpc_control; + + if (!(root->osc_control_set & osc_pci_express_dpc_control)) + host_bridge->native_dpc = 0; diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c + pci_acpi_add_edr_notifier(pci_dev); + pci_acpi_remove_edr_notifier(pci_dev); diff --git a/drivers/pci/pcie/kconfig b/drivers/pci/pcie/kconfig --- a/drivers/pci/pcie/kconfig +++ b/drivers/pci/pcie/kconfig + +config pcie_edr + bool "pci express error disconnect recover support" + depends on pcie_dpc && acpi + help + this option adds error disconnect recover support as specified + in the downstream port containment related enhancements ecn to + the pci firmware specification r3.2. enable this if you want to + support hybrid dpc model which uses both firmware and os to + implement dpc. diff --git a/drivers/pci/pcie/makefile b/drivers/pci/pcie/makefile --- a/drivers/pci/pcie/makefile +++ b/drivers/pci/pcie/makefile +obj-$(config_pcie_edr) += edr.o diff --git a/drivers/pci/pcie/edr.c b/drivers/pci/pcie/edr.c --- /dev/null +++ b/drivers/pci/pcie/edr.c +// spdx-license-identifier: gpl-2.0 +/* + * pci error disconnect recover support + * author: kuppuswamy sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> + * + * copyright (c) 2020 intel corp. + */ + +#define dev_fmt(fmt) "edr: " fmt + +#include <linux/pci.h> +#include <linux/pci-acpi.h> + +#include "portdrv.h" +#include "../pci.h" + +#define edr_port_dpc_enable_dsm 0x0c +#define edr_port_locate_dsm 0x0d +#define edr_ost_success 0x80 +#define edr_ost_failed 0x81 + +/* + * _dsm wrapper function to enable/disable dpc + * @pdev : pci device structure + * + * returns 0 on success or errno on failure. + */ +static int acpi_enable_dpc(struct pci_dev *pdev) +{ + struct acpi_device *adev = acpi_companion(&pdev->dev); + union acpi_object *obj, argv4, req; + int status = 0; + + /* + * behavior when calling unsupported _dsm functions is undefined, + * so check whether edr_port_dpc_enable_dsm is supported. + */ + if (!acpi_check_dsm(adev->handle, &pci_acpi_dsm_guid, 5, + 1ull << edr_port_dpc_enable_dsm)) + return 0; + + req.type = acpi_type_integer; + req.integer.value = 1; + + argv4.type = acpi_type_package; + argv4.package.count = 1; + argv4.package.elements = &req; + + /* + * per downstream port containment related enhancements ecn to pci + * firmware specification r3.2, sec 4.6.12, edr_port_dpc_enable_dsm is + * optional. return success if it's not implemented. + */ + obj = acpi_evaluate_dsm(adev->handle, &pci_acpi_dsm_guid, 5, + edr_port_dpc_enable_dsm, &argv4); + if (!obj) + return 0; + + if (obj->type != acpi_type_integer) { + pci_err(pdev, fw_bug "enable dpc _dsm returned non integer "); + status = -eio; + } + + if (obj->integer.value != 1) { + pci_err(pdev, "enable dpc _dsm failed to enable dpc "); + status = -eio; + } + + acpi_free(obj); + + return status; +} + +/* + * _dsm wrapper function to locate dpc port + * @pdev : device which received edr event + * + * returns pci_dev or null. caller is responsible for dropping a reference + * on the returned pci_dev with pci_dev_put(). + */ +static struct pci_dev *acpi_dpc_port_get(struct pci_dev *pdev) +{ + struct acpi_device *adev = acpi_companion(&pdev->dev); + union acpi_object *obj; + u16 port; + + /* + * behavior when calling unsupported _dsm functions is undefined, + * so check whether edr_port_dpc_enable_dsm is supported. + */ + if (!acpi_check_dsm(adev->handle, &pci_acpi_dsm_guid, 5, + 1ull << edr_port_locate_dsm)) + return pci_dev_get(pdev); + + obj = acpi_evaluate_dsm(adev->handle, &pci_acpi_dsm_guid, 5, + edr_port_locate_dsm, null); + if (!obj) + return pci_dev_get(pdev); + + if (obj->type != acpi_type_integer) { + acpi_free(obj); + pci_err(pdev, fw_bug "locate port _dsm returned non integer "); + return null; + } + + /* + * firmware returns dpc port bdf details in following format: + * 15:8 = bus + * 7:3 = device + * 2:0 = function + */ + port = obj->integer.value; + + acpi_free(obj); + + return pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), + pci_bus_num(port), port & 0xff); +} + +/* + * _ost wrapper function to let firmware know the status of edr event + * @pdev : device used to send _ost + * @edev : device which experienced edr event + * @status : status of edr event + */ +static int acpi_send_edr_status(struct pci_dev *pdev, struct pci_dev *edev, + u16 status) +{ + struct acpi_device *adev = acpi_companion(&pdev->dev); + u32 ost_status; + + pci_dbg(pdev, "status for %s: %#x ", pci_name(edev), status); + + ost_status = pci_devid(edev->bus->number, edev->devfn) << 16; + ost_status |= status; + + status = acpi_evaluate_ost(adev->handle, acpi_notify_disconnect_recover, + ost_status, null); + if (acpi_failure(status)) + return -einval; + + return 0; +} + +static void edr_handle_event(acpi_handle handle, u32 event, void *data) +{ + struct pci_dev *pdev = data, *edev; + pci_ers_result_t estate = pci_ers_result_disconnect; + u16 status; + + pci_info(pdev, "acpi event %#x received ", event); + + if (event != acpi_notify_disconnect_recover) + return; + + /* locate the port which issued edr event */ + edev = acpi_dpc_port_get(pdev); + if (!edev) { + pci_err(pdev, "firmware failed to locate dpc port "); + return; + } + + pci_dbg(pdev, "reported edr dev: %s ", pci_name(edev)); + + /* if port does not support dpc, just send the ost */ + if (!edev->dpc_cap) { + pci_err(edev, fw_bug "this device doesn't support dpc "); + goto send_ost; + } + + /* check if there is a valid dpc trigger */ + pci_read_config_word(edev, edev->dpc_cap + pci_exp_dpc_status, &status); + if (!(status & pci_exp_dpc_status_trigger)) { + pci_err(edev, "invalid dpc trigger %#010x ", status); + goto send_ost; + } + + dpc_process_error(edev); + pci_aer_raw_clear_status(edev); + + /* + * irrespective of whether the dpc event is triggered by err_fatal + * or err_nonfatal, since the link is already down, use the fatal + * error recovery path for both cases. + */ + estate = pcie_do_recovery(edev, pci_channel_io_frozen, dpc_reset_link); + +send_ost: + + /* + * if recovery is successful, send _ost(0xf, bdf << 16 | 0x80) + * to firmware. if not successful, send _ost(0xf, bdf << 16 | 0x81). + */ + if (estate == pci_ers_result_recovered) { + pci_dbg(edev, "dpc port successfully recovered "); + acpi_send_edr_status(pdev, edev, edr_ost_success); + } else { + pci_dbg(edev, "dpc port recovery failed "); + acpi_send_edr_status(pdev, edev, edr_ost_failed); + } + + pci_dev_put(edev); +} + +void pci_acpi_add_edr_notifier(struct pci_dev *pdev) +{ + struct acpi_device *adev = acpi_companion(&pdev->dev); + acpi_status status; + + if (!adev) { + pci_dbg(pdev, "no valid acpi node, skipping edr init "); + return; + } + + status = acpi_install_notify_handler(adev->handle, acpi_system_notify, + edr_handle_event, pdev); + if (acpi_failure(status)) { + pci_err(pdev, "failed to install notify handler "); + return; + } + + if (acpi_enable_dpc(pdev)) + acpi_remove_notify_handler(adev->handle, acpi_system_notify, + edr_handle_event); + else + pci_dbg(pdev, "notify handler installed "); +} + +void pci_acpi_remove_edr_notifier(struct pci_dev *pdev) +{ + struct acpi_device *adev = acpi_companion(&pdev->dev); + + if (!adev) + return; + + acpi_remove_notify_handler(adev->handle, acpi_system_notify, + edr_handle_event); + pci_dbg(pdev, "notify handler removed "); +} diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c + bridge->native_dpc = 1; diff --git a/include/linux/acpi.h b/include/linux/acpi.h --- a/include/linux/acpi.h +++ b/include/linux/acpi.h +#define osc_pci_edr_support 0x00000080 -#define osc_pci_support_masks 0x0000011f +#define osc_pci_support_masks 0x0000019f -#define osc_pci_control_masks 0x0000003f +#define osc_pci_express_dpc_control 0x00000080 +#define osc_pci_control_masks 0x000000bf diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h --- a/include/linux/pci-acpi.h +++ b/include/linux/pci-acpi.h +#ifdef config_pcie_edr +void pci_acpi_add_edr_notifier(struct pci_dev *pdev); +void pci_acpi_remove_edr_notifier(struct pci_dev *pdev); +#else +static inline void pci_acpi_add_edr_notifier(struct pci_dev *pdev) { } +static inline void pci_acpi_remove_edr_notifier(struct pci_dev *pdev) { } +#endif /* config_pcie_edr */ + diff --git a/include/linux/pci.h b/include/linux/pci.h --- a/include/linux/pci.h +++ b/include/linux/pci.h + unsigned int native_dpc:1; /* os may use pcie dpc */
|
PCI
|
ac1c8e35a3262d04cc81b07fac6480a3539e3b0f
|
kuppuswamy sathyanarayanan
|
drivers
|
acpi
|
pcie
|
pci/aer: rationalize error status register clearing
|
the aer interfaces to clear error status registers were a confusing mess:
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for error disconnect recover (edr, you can find edr spec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c', 'rst']
| 10
| 19
| 22
|
- pci_cleanup_aer_uncorrect_error_status() cleared non-fatal errors - pci_aer_clear_fatal_status() cleared fatal errors from the - pci_cleanup_aer_error_status_regs() cleared the root error status ---------------------------------------- ------------------------------- --- diff --git a/documentation/pci/pcieaer-howto.rst b/documentation/pci/pcieaer-howto.rst --- a/documentation/pci/pcieaer-howto.rst +++ b/documentation/pci/pcieaer-howto.rst - int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev);' + int pci_aer_clear_nonfatal_status(struct pci_dev *dev);' -pci_cleanup_aer_uncorrect_error_status cleanups the uncorrectable +pci_aer_clear_nonfatal_status clears non-fatal errors in the uncorrectable diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c - err = pci_cleanup_aer_uncorrect_error_status(pdev); + err = pci_aer_clear_nonfatal_status(pdev); - "pci_cleanup_aer_uncorrect_error_status failed, error %d ", + "pci_aer_clear_nonfatal_status() failed, error %d ", diff --git a/drivers/ntb/hw/idt/ntb_hw_idt.c b/drivers/ntb/hw/idt/ntb_hw_idt.c --- a/drivers/ntb/hw/idt/ntb_hw_idt.c +++ b/drivers/ntb/hw/idt/ntb_hw_idt.c - else /* cleanup uncorrectable error status before getting to init */ - pci_cleanup_aer_uncorrect_error_status(pdev); + else /* cleanup nonfatal error status before getting to init */ + pci_aer_clear_nonfatal_status(pdev); diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c - pci_cleanup_aer_error_status_regs(dev); + pci_aer_clear_status(dev); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h +int pci_aer_clear_status(struct pci_dev *dev); +static inline int pci_aer_clear_status(struct pci_dev *dev) { return -einval; } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c -int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) +int pci_aer_clear_nonfatal_status(struct pci_dev *dev) -export_symbol_gpl(pci_cleanup_aer_uncorrect_error_status); +export_symbol_gpl(pci_aer_clear_nonfatal_status); -int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) +int pci_aer_clear_status(struct pci_dev *dev) - pci_cleanup_aer_error_status_regs(dev); + pci_aer_clear_status(dev); diff --git a/drivers/pci/pcie/dpc.c b/drivers/pci/pcie/dpc.c --- a/drivers/pci/pcie/dpc.c +++ b/drivers/pci/pcie/dpc.c - pci_cleanup_aer_uncorrect_error_status(pdev); + pci_aer_clear_nonfatal_status(pdev); diff --git a/drivers/pci/pcie/err.c b/drivers/pci/pcie/err.c --- a/drivers/pci/pcie/err.c +++ b/drivers/pci/pcie/err.c - pci_cleanup_aer_uncorrect_error_status(dev); + pci_aer_clear_nonfatal_status(dev); diff --git a/drivers/scsi/lpfc/lpfc_attr.c b/drivers/scsi/lpfc/lpfc_attr.c --- a/drivers/scsi/lpfc/lpfc_attr.c +++ b/drivers/scsi/lpfc/lpfc_attr.c - * pci_cleanup_aer_uncorrect_error_status to clean up the uncorrectable + * pci_aer_clear_nonfatal_status() to clean up the uncorrectable - rc = pci_cleanup_aer_uncorrect_error_status(phba->pcidev); + rc = pci_aer_clear_nonfatal_status(phba->pcidev); diff --git a/include/linux/aer.h b/include/linux/aer.h --- a/include/linux/aer.h +++ b/include/linux/aer.h -int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev); -int pci_cleanup_aer_error_status_regs(struct pci_dev *dev); +int pci_aer_clear_nonfatal_status(struct pci_dev *dev); -static inline int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev) -{ - return -einval; -} -static inline int pci_cleanup_aer_error_status_regs(struct pci_dev *dev) +static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)
|
PCI
|
894020fdd88c1e9a74c60b67c0f19f1c7696ba2f
|
kuppuswamy sathyanarayanan
|
drivers
|
pci
|
ethernet, hw, ice, idt, intel, lpfc, pcie
|
pci/p2pdma: add intel sky lake-e root ports b, c, d to the whitelist
|
add the three remaining intel sky lake-e host root ports to the whitelist of p2pdma.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add intel skylake-e root ports b, c, d to the whitelist
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['p2pdma']
|
['c']
| 1
| 3
| 0
|
--- diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c + {pci_vendor_id_intel, 0x2031, 0}, + {pci_vendor_id_intel, 0x2032, 0}, + {pci_vendor_id_intel, 0x2033, 0},
|
PCI
|
7b94b53db34f78bb5e09f44e8827d45a8a88bf47
|
andrew maier
|
drivers
|
pci
| |
pci: mobiveil: add pcie gen4 rc driver for layerscape socs
|
add a pci host controller driver for layerscape socs integrating the mobiveil gpex ip.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add pcie gen4 rc driver for layerscape socs
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['mobiveil']
|
['h', 'kconfig', 'c', 'makefile']
| 4
| 291
| 2
|
--- diff --git a/drivers/pci/controller/mobiveil/kconfig b/drivers/pci/controller/mobiveil/kconfig --- a/drivers/pci/controller/mobiveil/kconfig +++ b/drivers/pci/controller/mobiveil/kconfig +config pcie_layerscape_gen4 + bool "freescale layerscape pcie gen4 controller" + depends on pci + depends on of && (arm64 || arch_layerscape) + depends on pci_msi_irq_domain + select pcie_mobiveil_host + help + say y here if you want pcie gen4 controller support on + layerscape socs. diff --git a/drivers/pci/controller/mobiveil/makefile b/drivers/pci/controller/mobiveil/makefile --- a/drivers/pci/controller/mobiveil/makefile +++ b/drivers/pci/controller/mobiveil/makefile +obj-$(config_pcie_layerscape_gen4) += pcie-layerscape-gen4.o diff --git a/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c --- /dev/null +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4.c +// spdx-license-identifier: gpl-2.0 +/* + * pcie gen4 host controller driver for nxp layerscape socs + * + * copyright 2019-2020 nxp + * + * author: zhiqiang hou <zhiqiang.hou@nxp.com> + */ + +#include <linux/kernel.h> +#include <linux/interrupt.h> +#include <linux/init.h> +#include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/of_irq.h> +#include <linux/of_address.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/resource.h> +#include <linux/mfd/syscon.h> +#include <linux/regmap.h> + +#include "pcie-mobiveil.h" + +/* lut and pf control registers */ +#define pcie_lut_off 0x80000 +#define pcie_pf_off 0xc0000 +#define pcie_pf_int_stat 0x18 +#define pf_int_stat_pabrst bit(31) + +#define pcie_pf_dbg 0x7fc +#define pf_dbg_ltssm_mask 0x3f +#define pf_dbg_ltssm_l0 0x2d /* l0 state */ +#define pf_dbg_we bit(31) +#define pf_dbg_pabr bit(27) + +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev) + +struct ls_pcie_g4 { + struct mobiveil_pcie pci; + struct delayed_work dwork; + int irq; +}; + +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci.csr_axi_slave_base + pcie_lut_off + off); +} + +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci.csr_axi_slave_base + pcie_lut_off + off); +} + +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off) +{ + return ioread32(pcie->pci.csr_axi_slave_base + pcie_pf_off + off); +} + +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie, + u32 off, u32 val) +{ + iowrite32(val, pcie->pci.csr_axi_slave_base + pcie_pf_off + off); +} + +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci); + u32 state; + + state = ls_pcie_g4_pf_readl(pcie, pcie_pf_dbg); + state = state & pf_dbg_ltssm_mask; + + if (state == pf_dbg_ltssm_l0) + return 1; + + return 0; +} + +static void ls_pcie_g4_disable_interrupt(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = &pcie->pci; + + mobiveil_csr_writel(mv_pci, 0, pab_intp_amba_misc_enb); +} + +static void ls_pcie_g4_enable_interrupt(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = &pcie->pci; + u32 val; + + /* clear the interrupt status */ + mobiveil_csr_writel(mv_pci, 0xffffffff, pab_intp_amba_misc_stat); + + val = pab_intp_intx_mask | pab_intp_msi | pab_intp_reset | + pab_intp_pcie_ue | pab_intp_ie_pmredi | pab_intp_ie_ec; + mobiveil_csr_writel(mv_pci, val, pab_intp_amba_misc_enb); +} + +static int ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie) +{ + struct mobiveil_pcie *mv_pci = &pcie->pci; + struct device *dev = &mv_pci->pdev->dev; + u32 val, act_stat; + int to = 100; + + /* poll for pab_csb_reset to set and pab activity to clear */ + do { + usleep_range(10, 15); + val = ls_pcie_g4_pf_readl(pcie, pcie_pf_int_stat); + act_stat = mobiveil_csr_readl(mv_pci, pab_activity_stat); + } while (((val & pf_int_stat_pabrst) == 0 || act_stat) && to--); + if (to < 0) { + dev_err(dev, "poll pabrst&pabact timeout "); + return -eio; + } + + /* clear pex_reset bit in pex_pf0_dbg register */ + val = ls_pcie_g4_pf_readl(pcie, pcie_pf_dbg); + val |= pf_dbg_we; + ls_pcie_g4_pf_writel(pcie, pcie_pf_dbg, val); + + val = ls_pcie_g4_pf_readl(pcie, pcie_pf_dbg); + val |= pf_dbg_pabr; + ls_pcie_g4_pf_writel(pcie, pcie_pf_dbg, val); + + val = ls_pcie_g4_pf_readl(pcie, pcie_pf_dbg); + val &= ~pf_dbg_we; + ls_pcie_g4_pf_writel(pcie, pcie_pf_dbg, val); + + mobiveil_host_init(mv_pci, true); + + to = 100; + while (!ls_pcie_g4_link_up(mv_pci) && to--) + usleep_range(200, 250); + if (to < 0) { + dev_err(dev, "pcie link training timeout "); + return -eio; + } + + return 0; +} + +static irqreturn_t ls_pcie_g4_isr(int irq, void *dev_id) +{ + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id; + struct mobiveil_pcie *mv_pci = &pcie->pci; + u32 val; + + val = mobiveil_csr_readl(mv_pci, pab_intp_amba_misc_stat); + if (!val) + return irq_none; + + if (val & pab_intp_reset) { + ls_pcie_g4_disable_interrupt(pcie); + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1)); + } + + mobiveil_csr_writel(mv_pci, val, pab_intp_amba_misc_stat); + + return irq_handled; +} + +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci) +{ + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci); + struct platform_device *pdev = mv_pci->pdev; + struct device *dev = &pdev->dev; + int ret; + + pcie->irq = platform_get_irq_byname(pdev, "intr"); + if (pcie->irq < 0) { + dev_err(dev, "can't get 'intr' irq, errno = %d ", pcie->irq); + return pcie->irq; + } + ret = devm_request_irq(dev, pcie->irq, ls_pcie_g4_isr, + irqf_shared, pdev->name, pcie); + if (ret) { + dev_err(dev, "can't register pcie irq, errno = %d ", ret); + return ret; + } + + return 0; +} + +static void ls_pcie_g4_reset(struct work_struct *work) +{ + struct delayed_work *dwork = container_of(work, struct delayed_work, + work); + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork); + struct mobiveil_pcie *mv_pci = &pcie->pci; + u16 ctrl; + + ctrl = mobiveil_csr_readw(mv_pci, pci_bridge_control); + ctrl &= ~pci_bridge_ctl_bus_reset; + mobiveil_csr_writew(mv_pci, ctrl, pci_bridge_control); + + if (!ls_pcie_g4_reinit_hw(pcie)) + return; + + ls_pcie_g4_enable_interrupt(pcie); +} + +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = { + .interrupt_init = ls_pcie_g4_interrupt_init, +}; + +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = { + .link_up = ls_pcie_g4_link_up, +}; + +static int __init ls_pcie_g4_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pci_host_bridge *bridge; + struct mobiveil_pcie *mv_pci; + struct ls_pcie_g4 *pcie; + struct device_node *np = dev->of_node; + int ret; + + if (!of_parse_phandle(np, "msi-parent", 0)) { + dev_err(dev, "failed to find msi-parent "); + return -einval; + } + + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); + if (!bridge) + return -enomem; + + pcie = pci_host_bridge_priv(bridge); + mv_pci = &pcie->pci; + + mv_pci->pdev = pdev; + mv_pci->ops = &ls_pcie_g4_pab_ops; + mv_pci->rp.ops = &ls_pcie_g4_rp_ops; + mv_pci->rp.bridge = bridge; + + platform_set_drvdata(pdev, pcie); + + init_delayed_work(&pcie->dwork, ls_pcie_g4_reset); + + ret = mobiveil_pcie_host_probe(mv_pci); + if (ret) { + dev_err(dev, "fail to probe "); + return ret; + } + + ls_pcie_g4_enable_interrupt(pcie); + + return 0; +} + +static const struct of_device_id ls_pcie_g4_of_match[] = { + { .compatible = "fsl,lx2160a-pcie", }, + { }, +}; + +static struct platform_driver ls_pcie_g4_driver = { + .driver = { + .name = "layerscape-pcie-gen4", + .of_match_table = ls_pcie_g4_of_match, + .suppress_bind_attrs = true, + }, +}; + +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h +#define pab_activity_stat 0x81c + -#define pab_intp_intx_mask 0x01e0 -#define pab_intp_msi_mask 0x8 +#define pab_intp_reset bit(1) +#define pab_intp_msi bit(3) +#define pab_intp_inta bit(5) +#define pab_intp_intb bit(6) +#define pab_intp_intc bit(7) +#define pab_intp_intd bit(8) +#define pab_intp_pcie_ue bit(9) +#define pab_intp_ie_pmredi bit(29) +#define pab_intp_ie_ec bit(30) +#define pab_intp_msi_mask pab_intp_msi +#define pab_intp_intx_mask (pab_intp_inta | pab_intp_intb |\ + pab_intp_intc | pab_intp_intd)
|
PCI
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d29ad70a813b0daa424b70950d432c34a1a95865
|
hou zhiqiang minghuan lian minghuan lian nxp com andrew murray amurray thegoodpenguin co uk
|
drivers
|
pci
|
controller, mobiveil
|
pci: tegra: add support for pcie endpoint mode in tegra194
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add support for the endpoint mode of synopsys designware core based dual mode pcie controllers present in tegra194 soc.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for pcie endpoint mode in tegra194
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['tegra']
|
['kconfig', 'c']
| 3
| 695
| 18
|
--- diff --git a/drivers/pci/controller/dwc/kconfig b/drivers/pci/controller/dwc/kconfig --- a/drivers/pci/controller/dwc/kconfig +++ b/drivers/pci/controller/dwc/kconfig - tristate "nvidia tegra194 (and later) pcie controller" + tristate + +config pcie_tegra194_host + tristate "nvidia tegra194 (and later) pcie controller - host mode" + select pcie_tegra194 + help + enables support for the pcie controller in the nvidia tegra194 soc to + work in host mode. there are two instances of pcie controllers in + tegra194. this controller can work either as ep or rc. in order to + enable host-specific features pcie_tegra194_host must be selected and + in order to enable device-specific features pcie_tegra194_ep must be + selected. this uses the designware core. + +config pcie_tegra194_ep + tristate "nvidia tegra194 (and later) pcie controller - endpoint mode" + depends on arch_tegra_194_soc || compile_test + depends on pci_endpoint + select pcie_dw_ep + select phy_tegra194_p2u + select pcie_tegra194 - say y here if you want support for designware core based pcie host - controller found in nvidia tegra194 soc. + enables support for the pcie controller in the nvidia tegra194 soc to + work in host mode. there are two instances of pcie controllers in + tegra194. this controller can work either as ep or rc. in order to + enable host-specific features pcie_tegra194_host must be selected and + in order to enable device-specific features pcie_tegra194_ep must be + selected. this uses the designware core. diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c +export_symbol_gpl(dw_pcie_ep_linkup); +export_symbol_gpl(dw_pcie_ep_init_notify); +export_symbol_gpl(dw_pcie_ep_init_complete); +export_symbol_gpl(dw_pcie_ep_init); diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c +#include <linux/gpio/consumer.h> +#define appl_intr_en_l0_0_pci_cmd_en_int_en bit(15) +#define appl_intr_status_l0_pci_cmd_en_int bit(15) +#define appl_intr_status_l0_pex_rst_int bit(16) +#define appl_intr_en_l1_0_0_rdlh_link_up_int_en bit(3) +#define appl_intr_en_l1_0_0_hot_reset_done_int_en bit(30) +#define appl_intr_status_l1_0_0_rdlh_link_up_chged bit(3) +#define appl_intr_status_l1_0_0_hot_reset_done bit(30) +#define appl_intr_status_l1_15_cfg_bme_chged bit(1) +#define appl_msi_ctrl_1 0xac + +#define appl_legacy_intx 0xb8 + +#define msix_addr_match_low_off 0x940 +#define msix_addr_match_low_off_en bit(0) +#define msix_addr_match_low_off_mask genmask(31, 2) + +#define msix_addr_match_high_off 0x944 +#define msix_addr_match_high_off_mask genmask(31, 0) + +#define ltr_msg_timeout (100 * 1000) + +#define perst_debounce_time (5 * 1000) + +#define ep_state_disabled 0 +#define ep_state_enabled 1 + + enum dw_pcie_device_mode mode; + + + /* endpoint mode specific */ + struct gpio_desc *pex_rst_gpiod; + struct gpio_desc *pex_refclk_sel_gpiod; + unsigned int pex_rst_irq; + int ep_state; +}; + +struct tegra_pcie_dw_of_data { + enum dw_pcie_device_mode mode; -static irqreturn_t tegra_pcie_rp_irq_handler(struct tegra_pcie_dw *pcie) +static irqreturn_t tegra_pcie_rp_irq_handler(int irq, void *arg) + struct tegra_pcie_dw *pcie = arg; -static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg) +static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie) +{ + u32 val; + + appl_writel(pcie, 0xffffffff, appl_intr_status_l0); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_0_0); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_1); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_2); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_3); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_6); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_7); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_8_0); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_9); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_10); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_11); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_13); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_14); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_15); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_17); + appl_writel(pcie, 0xffffffff, appl_msi_ctrl_2); + + val = appl_readl(pcie, appl_ctrl); + val |= appl_ctrl_ltssm_en; + appl_writel(pcie, val, appl_ctrl); +} + +static irqreturn_t tegra_pcie_ep_irq_thread(int irq, void *arg) + struct dw_pcie *pci = &pcie->pci; + u32 val, speed; + + speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + pci_exp_lnksta) & + pci_exp_lnksta_cls; + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + + /* if ep doesn't advertise l1ss, just return */ + val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); + if (!(val & (pci_l1ss_cap_aspm_l1_1 | pci_l1ss_cap_aspm_l1_2))) + return irq_handled; + + /* check if bme is set to '1' */ + val = dw_pcie_readl_dbi(pci, pci_command); + if (val & pci_command_master) { + ktime_t timeout; + + /* 110us for both snoop and no-snoop */ + val = 110 | (2 << pci_ltr_scale_shift) | ltr_msg_req; + val |= (val << ltr_mst_no_snoop_shift); + appl_writel(pcie, val, appl_ltr_msg_1); + + /* send ltr upstream */ + val = appl_readl(pcie, appl_ltr_msg_2); + val |= appl_ltr_msg_2_ltr_msg_req_state; + appl_writel(pcie, val, appl_ltr_msg_2); + + timeout = ktime_add_us(ktime_get(), ltr_msg_timeout); + for (;;) { + val = appl_readl(pcie, appl_ltr_msg_2); + if (!(val & appl_ltr_msg_2_ltr_msg_req_state)) + break; + if (ktime_after(ktime_get(), timeout)) + break; + usleep_range(1000, 1100); + } + if (val & appl_ltr_msg_2_ltr_msg_req_state) + dev_err(pcie->dev, "failed to send ltr message "); + } - return tegra_pcie_rp_irq_handler(pcie); + return irq_handled; +} + +static irqreturn_t tegra_pcie_ep_hard_irq(int irq, void *arg) +{ + struct tegra_pcie_dw *pcie = arg; + struct dw_pcie_ep *ep = &pcie->pci.ep; + int spurious = 1; + u32 val, tmp; + + val = appl_readl(pcie, appl_intr_status_l0); + if (val & appl_intr_status_l0_link_state_int) { + val = appl_readl(pcie, appl_intr_status_l1_0_0); + appl_writel(pcie, val, appl_intr_status_l1_0_0); + + if (val & appl_intr_status_l1_0_0_hot_reset_done) + pex_ep_event_hot_rst_done(pcie); + + if (val & appl_intr_status_l1_0_0_rdlh_link_up_chged) { + tmp = appl_readl(pcie, appl_link_status); + if (tmp & appl_link_status_rdlh_link_up) { + dev_dbg(pcie->dev, "link is up with host "); + dw_pcie_ep_linkup(ep); + } + } + + spurious = 0; + } + + if (val & appl_intr_status_l0_pci_cmd_en_int) { + val = appl_readl(pcie, appl_intr_status_l1_15); + appl_writel(pcie, val, appl_intr_status_l1_15); + + if (val & appl_intr_status_l1_15_cfg_bme_chged) + return irq_wake_thread; + + spurious = 0; + } + + if (spurious) { + dev_warn(pcie->dev, "random interrupt (status = 0x%08x) ", + val); + appl_writel(pcie, val, appl_intr_status_l0); + } + + return irq_handled; +static int tegra_pcie_dw_start_link(struct dw_pcie *pci) +{ + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); + + enable_irq(pcie->pex_rst_irq); + + return 0; +} + +static void tegra_pcie_dw_stop_link(struct dw_pcie *pci) +{ + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); + + disable_irq(pcie->pex_rst_irq); +} + + .start_link = tegra_pcie_dw_start_link, + .stop_link = tegra_pcie_dw_stop_link, + if (pcie->mode == dw_pcie_rc_type) + return 0; + + /* endpoint mode specific dt entries */ + pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", gpiod_in); + if (is_err(pcie->pex_rst_gpiod)) { + dev_err(pcie->dev, "failed to get perst gpio: %ld ", + ptr_err(pcie->pex_rst_gpiod)); + return ptr_err(pcie->pex_rst_gpiod); + } + + pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, + "nvidia,refclk-select", + gpiod_out_high); + if (is_err(pcie->pex_refclk_sel_gpiod)) { + dev_info(pcie->dev, "failed to get refclk select gpios: %ld ", + ptr_err(pcie->pex_refclk_sel_gpiod)); + pcie->pex_refclk_sel_gpiod = null; + } + +static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie, + bool enable) +{ + struct mrq_uphy_response resp; + struct tegra_bpmp_message msg; + struct mrq_uphy_request req; + + memset(&req, 0, sizeof(req)); + memset(&resp, 0, sizeof(resp)); + + if (enable) { + req.cmd = cmd_uphy_pcie_ep_controller_pll_init; + req.ep_ctrlr_pll_init.ep_controller = pcie->cid; + } else { + req.cmd = cmd_uphy_pcie_ep_controller_pll_off; + req.ep_ctrlr_pll_off.ep_controller = pcie->cid; + } + + memset(&msg, 0, sizeof(msg)); + msg.mrq = mrq_uphy; + msg.tx.data = &req; + msg.tx.size = sizeof(req); + msg.rx.data = &resp; + msg.rx.size = sizeof(resp); + + return tegra_bpmp_transfer(pcie->bpmp, &msg); +} + +static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie) +{ + u32 val; + int ret; + + if (pcie->ep_state == ep_state_disabled) + return; + + /* disable ltssm */ + val = appl_readl(pcie, appl_ctrl); + val &= ~appl_ctrl_ltssm_en; + appl_writel(pcie, val, appl_ctrl); + + ret = readl_poll_timeout(pcie->appl_base + appl_debug, val, + ((val & appl_debug_ltssm_state_mask) >> + appl_debug_ltssm_state_shift) == + ltssm_state_pre_detect, + 1, ltssm_timeout); + if (ret) + dev_err(pcie->dev, "failed to go detect state: %d ", ret); + + reset_control_assert(pcie->core_rst); + + tegra_pcie_disable_phy(pcie); + + reset_control_assert(pcie->core_apb_rst); + + clk_disable_unprepare(pcie->core_clk); + + pm_runtime_put_sync(pcie->dev); + + ret = tegra_pcie_bpmp_set_pll_state(pcie, false); + if (ret) + dev_err(pcie->dev, "failed to turn off uphy: %d ", ret); + + pcie->ep_state = ep_state_disabled; + dev_dbg(pcie->dev, "uninitialization of endpoint is completed "); +} + +static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) +{ + struct dw_pcie *pci = &pcie->pci; + struct dw_pcie_ep *ep = &pci->ep; + struct device *dev = pcie->dev; + u32 val; + int ret; + + if (pcie->ep_state == ep_state_enabled) + return; + + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "failed to get runtime sync for pcie dev: %d ", + ret); + return; + } + + ret = tegra_pcie_bpmp_set_pll_state(pcie, true); + if (ret) { + dev_err(dev, "failed to init uphy for pcie ep: %d ", ret); + goto fail_pll_init; + } + + ret = clk_prepare_enable(pcie->core_clk); + if (ret) { + dev_err(dev, "failed to enable core clock: %d ", ret); + goto fail_core_clk_enable; + } + + ret = reset_control_deassert(pcie->core_apb_rst); + if (ret) { + dev_err(dev, "failed to deassert core apb reset: %d ", ret); + goto fail_core_apb_rst; + } + + ret = tegra_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable phy: %d ", ret); + goto fail_phy; + } + + /* clear any stale interrupt statuses */ + appl_writel(pcie, 0xffffffff, appl_intr_status_l0); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_0_0); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_1); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_2); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_3); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_6); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_7); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_8_0); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_9); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_10); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_11); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_13); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_14); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_15); + appl_writel(pcie, 0xffffffff, appl_intr_status_l1_17); + + /* configure this core for ep mode operation */ + val = appl_readl(pcie, appl_dm_type); + val &= ~appl_dm_type_mask; + val |= appl_dm_type_ep; + appl_writel(pcie, val, appl_dm_type); + + appl_writel(pcie, 0x0, appl_cfg_slcg_override); + + val = appl_readl(pcie, appl_ctrl); + val |= appl_ctrl_sys_pre_det_state; + val |= appl_ctrl_hw_hot_rst_en; + appl_writel(pcie, val, appl_ctrl); + + val = appl_readl(pcie, appl_cfg_misc); + val |= appl_cfg_misc_slv_ep_mode; + val |= (appl_cfg_misc_arcache_val << appl_cfg_misc_arcache_shift); + appl_writel(pcie, val, appl_cfg_misc); + + val = appl_readl(pcie, appl_pinmux); + val |= appl_pinmux_clk_output_in_override_en; + val |= appl_pinmux_clk_output_in_override; + appl_writel(pcie, val, appl_pinmux); + + appl_writel(pcie, pcie->dbi_res->start & appl_cfg_base_addr_mask, + appl_cfg_base_addr); + + appl_writel(pcie, pcie->atu_dma_res->start & + appl_cfg_iatu_dma_base_addr_mask, + appl_cfg_iatu_dma_base_addr); + + val = appl_readl(pcie, appl_intr_en_l0_0); + val |= appl_intr_en_l0_0_sys_intr_en; + val |= appl_intr_en_l0_0_link_state_int_en; + val |= appl_intr_en_l0_0_pci_cmd_en_int_en; + appl_writel(pcie, val, appl_intr_en_l0_0); + + val = appl_readl(pcie, appl_intr_en_l1_0_0); + val |= appl_intr_en_l1_0_0_hot_reset_done_int_en; + val |= appl_intr_en_l1_0_0_rdlh_link_up_int_en; + appl_writel(pcie, val, appl_intr_en_l1_0_0); + + reset_control_deassert(pcie->core_rst); + + if (pcie->update_fc_fixup) { + val = dw_pcie_readl_dbi(pci, cfg_timer_ctrl_max_func_num_off); + val |= 0x1 << cfg_timer_ctrl_ack_nak_shift; + dw_pcie_writel_dbi(pci, cfg_timer_ctrl_max_func_num_off, val); + } + + config_gen3_gen4_eq_presets(pcie); + + init_host_aspm(pcie); + + /* disable aspm-l1ss advertisement if there is no clkreq routing */ + if (!pcie->supports_clkreq) { + disable_aspm_l11(pcie); + disable_aspm_l12(pcie); + } + + val = dw_pcie_readl_dbi(pci, gen3_related_off); + val &= ~gen3_related_off_gen3_zrxdc_noncompl; + dw_pcie_writel_dbi(pci, gen3_related_off, val); + + /* configure n_fts & fts */ + val = dw_pcie_readl_dbi(pci, port_logic_ack_f_aspm_ctrl); + val &= ~(n_fts_mask << n_fts_shift); + val |= n_fts_val << n_fts_shift; + dw_pcie_writel_dbi(pci, port_logic_ack_f_aspm_ctrl, val); + + val = dw_pcie_readl_dbi(pci, port_logic_gen2_ctrl); + val &= ~fts_mask; + val |= fts_val; + dw_pcie_writel_dbi(pci, port_logic_gen2_ctrl, val); + + /* configure max speed from dt */ + if (pcie->max_speed && pcie->max_speed != -einval) { + val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + + pci_exp_lnkcap); + val &= ~pci_exp_lnkcap_sls; + val |= pcie->max_speed; + dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + pci_exp_lnkcap, + val); + } + + pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, + pci_cap_id_exp); + clk_set_rate(pcie->core_clk, gen4_core_clk_freq); + + val = (ep->msi_mem_phys & msix_addr_match_low_off_mask); + val |= msix_addr_match_low_off_en; + dw_pcie_writel_dbi(pci, msix_addr_match_low_off, val); + val = (lower_32_bits(ep->msi_mem_phys) & msix_addr_match_high_off_mask); + dw_pcie_writel_dbi(pci, msix_addr_match_high_off, val); + + ret = dw_pcie_ep_init_complete(ep); + if (ret) { + dev_err(dev, "failed to complete initialization: %d ", ret); + goto fail_init_complete; + } + + dw_pcie_ep_init_notify(ep); + + /* enable ltssm */ + val = appl_readl(pcie, appl_ctrl); + val |= appl_ctrl_ltssm_en; + appl_writel(pcie, val, appl_ctrl); + + pcie->ep_state = ep_state_enabled; + dev_dbg(dev, "initialization of endpoint is completed "); + + return; + +fail_init_complete: + reset_control_assert(pcie->core_rst); + tegra_pcie_disable_phy(pcie); +fail_phy: + reset_control_assert(pcie->core_apb_rst); +fail_core_apb_rst: + clk_disable_unprepare(pcie->core_clk); +fail_core_clk_enable: + tegra_pcie_bpmp_set_pll_state(pcie, false); +fail_pll_init: + pm_runtime_put_sync(dev); +} + +static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg) +{ + struct tegra_pcie_dw *pcie = arg; + + if (gpiod_get_value(pcie->pex_rst_gpiod)) + pex_ep_event_pex_rst_assert(pcie); + else + pex_ep_event_pex_rst_deassert(pcie); + + return irq_handled; +} + +static int tegra_pcie_ep_raise_legacy_irq(struct tegra_pcie_dw *pcie, u16 irq) +{ + /* tegra194 supports only inta */ + if (irq > 1) + return -einval; + + appl_writel(pcie, 1, appl_legacy_intx); + usleep_range(1000, 2000); + appl_writel(pcie, 0, appl_legacy_intx); + return 0; +} + +static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) +{ + if (unlikely(irq > 31)) + return -einval; + + appl_writel(pcie, (1 << irq), appl_msi_ctrl_1); + + return 0; +} + +static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq) +{ + struct dw_pcie_ep *ep = &pcie->pci.ep; + + writel(irq, ep->msi_mem); + + return 0; +} + +static int tegra_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); + + switch (type) { + case pci_epc_irq_legacy: + return tegra_pcie_ep_raise_legacy_irq(pcie, interrupt_num); + + case pci_epc_irq_msi: + return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num); + + case pci_epc_irq_msix: + return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num); + + default: + dev_err(pci->dev, "unknown irq type "); + return -eperm; + } + + return 0; +} + +static const struct pci_epc_features tegra_pcie_epc_features = { + .linkup_notifier = true, + .core_init_notifier = true, + .msi_capable = false, + .msix_capable = false, + .reserved_bar = 1 << bar_2 | 1 << bar_3 | 1 << bar_4 | 1 << bar_5, + .bar_fixed_64bit = 1 << bar_0, + .bar_fixed_size[0] = sz_1m, +}; + +static const struct pci_epc_features* +tegra_pcie_ep_get_features(struct dw_pcie_ep *ep) +{ + return &tegra_pcie_epc_features; +} + +static struct dw_pcie_ep_ops pcie_ep_ops = { + .raise_irq = tegra_pcie_ep_raise_irq, + .get_features = tegra_pcie_ep_get_features, +}; + +static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie, + struct platform_device *pdev) +{ + struct dw_pcie *pci = &pcie->pci; + struct device *dev = pcie->dev; + struct dw_pcie_ep *ep; + struct resource *res; + char *name; + int ret; + + ep = &pci->ep; + ep->ops = &pcie_ep_ops; + + res = platform_get_resource_byname(pdev, ioresource_mem, "addr_space"); + if (!res) + return -einval; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + ep->page_size = sz_64k; + + ret = gpiod_set_debounce(pcie->pex_rst_gpiod, perst_debounce_time); + if (ret < 0) { + dev_err(dev, "failed to set perst gpio debounce time: %d ", + ret); + return ret; + } + + ret = gpiod_to_irq(pcie->pex_rst_gpiod); + if (ret < 0) { + dev_err(dev, "failed to get irq for perst gpio: %d ", ret); + return ret; + } + pcie->pex_rst_irq = (unsigned int)ret; + + name = devm_kasprintf(dev, gfp_kernel, "tegra_pcie_%u_pex_rst_irq", + pcie->cid); + if (!name) { + dev_err(dev, "failed to create perst irq string "); + return -enomem; + } + + irq_set_status_flags(pcie->pex_rst_irq, irq_noautoen); + + pcie->ep_state = ep_state_disabled; + + ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, null, + tegra_pcie_ep_pex_rst_irq, + irqf_trigger_rising | + irqf_trigger_falling | irqf_oneshot, + name, (void *)pcie); + if (ret < 0) { + dev_err(dev, "failed to request irq for perst: %d ", ret); + return ret; + } + + name = devm_kasprintf(dev, gfp_kernel, "tegra_pcie_%u_ep_work", + pcie->cid); + if (!name) { + dev_err(dev, "failed to create pcie ep work thread string "); + return -enomem; + } + + pm_runtime_enable(dev); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize dwc endpoint subsystem: %d ", + ret); + return ret; + } + + return 0; +} + + const struct tegra_pcie_dw_of_data *data; + data = of_device_get_match_data(dev); + + pcie->mode = (enum dw_pcie_device_mode)data->mode; + if (pcie->pex_refclk_sel_gpiod) + gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); + - ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler, - irqf_shared, "tegra-pcie-intr", pcie); - if (ret) { - dev_err(dev, "failed to request irq %d: %d ", pp->irq, ret); - return ret; - } - - ret = tegra_pcie_config_rp(pcie); - if (ret && ret != -enomedium) - goto fail; - else - return 0; + switch (pcie->mode) { + case dw_pcie_rc_type: + ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, + irqf_shared, "tegra-pcie-intr", pcie); + if (ret) { + dev_err(dev, "failed to request irq %d: %d ", pp->irq, + ret); + goto fail; + } + + ret = tegra_pcie_config_rp(pcie); + if (ret && ret != -enomedium) + goto fail; + else + return 0; + break; + + case dw_pcie_ep_type: + ret = devm_request_threaded_irq(dev, pp->irq, + tegra_pcie_ep_hard_irq, + tegra_pcie_ep_irq_thread, + irqf_shared | irqf_oneshot, + "tegra-pcie-ep-intr", pcie); + if (ret) { + dev_err(dev, "failed to request irq %d: %d ", pp->irq, + ret); + goto fail; + } + + ret = tegra_pcie_config_ep(pcie, pdev); + if (ret < 0) + goto fail; + break; + + default: + dev_err(dev, "invalid pcie device type %d ", pcie->mode); + } + if (pcie->pex_refclk_sel_gpiod) + gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); +static const struct tegra_pcie_dw_of_data tegra_pcie_dw_rc_of_data = { + .mode = dw_pcie_rc_type, +}; + +static const struct tegra_pcie_dw_of_data tegra_pcie_dw_ep_of_data = { + .mode = dw_pcie_ep_type, +}; + + .data = &tegra_pcie_dw_rc_of_data, + }, + { + .compatible = "nvidia,tegra194-pcie-ep", + .data = &tegra_pcie_dw_ep_of_data,
|
PCI
|
c57247f940e8ea13a0ec33378304dc3cdc5da4a8
|
vidya sagar thierry reding treding nvidia com
|
drivers
|
pci
|
controller, dwc
|
pci: vmd: add two vmd device ids
|
add new vmd device ids that require the bus restriction mode.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add two vmd device ids
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['vmd']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c + {pci_device(pci_vendor_id_intel, 0x467f), + .driver_data = vmd_feat_has_bus_restrictions,}, + {pci_device(pci_vendor_id_intel, 0x4c3d), + .driver_data = vmd_feat_has_bus_restrictions,},
|
PCI
|
449a01d2659c207b012e6d3bb6edfff8c94a4e55
|
sushma kalakota
|
drivers
|
pci
|
controller
|
genirq/debugfs: add missing sanity checks to interrupt injection
|
interrupts cannot be injected when the interrupt is not activated and when a replay is already in progress.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['c']
| 1
| 9
| 2
|
--- diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c - if (irq_settings_is_level(desc) || desc->istate & irqs_nmi) { - /* can't do level nor nmis, sorry */ + /* + * don't allow injection when the interrupt is: + * - level or nmi type + * - not activated + * - replaying already + */ + if (irq_settings_is_level(desc) || + !irqd_is_activated(&desc->irq_data) || + (desc->istate & (irqs_nmi | irqs_replay))) {
|
PCI
|
a740a423c36932695b01a3e920f697bc55b05fec
|
thomas gleixner marc zyngier maz kernel org
|
kernel
|
irq
| |
genirq: add protection against unsafe usage of generic_handle_irq()
|
in general calling generic_handle_irq() with interrupts disabled from non interrupt context is harmless. for some interrupt controllers like the x86 trainwrecks this is outright dangerous as it might corrupt state if an interrupt affinity change is pending.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['h', 'c']
| 4
| 30
| 2
|
--- diff --git a/include/linux/irq.h b/include/linux/irq.h --- a/include/linux/irq.h +++ b/include/linux/irq.h + * irqd_handle_enforce_irqctx - enforce that handle_irq_*() is only invoked + * from actual interrupt context. + irqd_handle_enforce_irqctx = (1 << 28), +static inline void irqd_set_handle_enforce_irqctx(struct irq_data *d) +{ + __irqd_to_state(d) |= irqd_handle_enforce_irqctx; +} + +static inline bool irqd_is_handle_enforce_irqctx(struct irq_data *d) +{ + return __irqd_to_state(d) & irqd_handle_enforce_irqctx; +} + diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h +static inline bool handle_enforce_irqctx(struct irq_data *data) +{ + return irqd_is_handle_enforce_irqctx(data); +} +static inline bool handle_enforce_irqctx(struct irq_data *data) +{ + return false; +} diff --git a/kernel/irq/irqdesc.c b/kernel/irq/irqdesc.c --- a/kernel/irq/irqdesc.c +++ b/kernel/irq/irqdesc.c + struct irq_data *data; + + data = irq_desc_get_irq_data(desc); + if (warn_on_once(!in_irq() && handle_enforce_irqctx(data))) + return -eperm; + diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c - if (!desc->irq_data.chip->irq_retrigger || - !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) { + if ((!desc->irq_data.chip->irq_retrigger || + !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) && + !handle_enforce_irqctx(&desc->irq_data)) {
|
PCI
|
c16816acd08697b02a53f56f8936497a9f6f6e7a
|
thomas gleixner
|
include
|
linux
| |
x86/apic/vector: force interupt handler invocation to irq context
|
sathyanarayanan reported that the pci-e aer error injection mechanism can result in a null pointer dereference in apic_ack_edge():
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/arch/x86/kernel/apic/vector.c b/arch/x86/kernel/apic/vector.c --- a/arch/x86/kernel/apic/vector.c +++ b/arch/x86/kernel/apic/vector.c + /* + * prevent that any of these interrupts is invoked in + * non interrupt context via e.g. generic_handle_irq() + * as that can corrupt the affinity move state. + */ + irqd_set_handle_enforce_irqctx(irqd);
|
PCI
|
008f1d60fe25810d4554916744b0975d76601b64
|
thomas gleixner
|
arch
|
x86
|
apic, kernel
|
genirq: add return value to check_irq_resend()
|
in preparation for an interrupt injection interface which can be used safely by error injection mechanisms. e.g. pci-e/ aer, add a return value to check_irq_resend() so errors can be propagated to the caller.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['h', 'c']
| 3
| 51
| 37
|
--- diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c - check_irq_resend(desc); - err = 0; + err = check_irq_resend(desc); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h -void check_irq_resend(struct irq_desc *desc); +int check_irq_resend(struct irq_desc *desc); diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c +static int irq_sw_resend(struct irq_desc *desc) +{ + unsigned int irq = irq_desc_get_irq(desc); + + /* + * validate whether this interrupt can be safely injected from + * non interrupt context + */ + if (handle_enforce_irqctx(&desc->irq_data)) + return -einval; + + /* + * if the interrupt is running in the thread context of the parent + * irq we need to be careful, because we cannot trigger it + * directly. + */ + if (irq_settings_is_nested_thread(desc)) { + /* + * if the parent_irq is valid, we retrigger the parent, + * otherwise we do nothing. + */ + if (!desc->parent_irq) + return -einval; + irq = desc->parent_irq; + } + + /* set it pending and activate the softirq: */ + set_bit(irq, irqs_resend); + tasklet_schedule(&resend_tasklet); + return 0; +} + +#else +static int irq_sw_resend(struct irq_desc *desc) +{ + return -einval; +} -void check_irq_resend(struct irq_desc *desc) +int check_irq_resend(struct irq_desc *desc) - * we do not resend level type interrupts. level type - * interrupts are resent by hardware when they are still - * active. clear the pending bit so suspend/resume does not - * get confused. + * we do not resend level type interrupts. level type interrupts + * are resent by hardware when they are still active. clear the + * pending bit so suspend/resume does not get confused. - return; + return -einval; + - return; + return -ebusy; + - if ((!desc->irq_data.chip->irq_retrigger || - !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) && - !handle_enforce_irqctx(&desc->irq_data)) { -#ifdef config_hardirqs_sw_resend - unsigned int irq = irq_desc_get_irq(desc); - - /* - * if the interrupt is running in the thread - * context of the parent irq we need to be - * careful, because we cannot trigger it - * directly. - */ - if (irq_settings_is_nested_thread(desc)) { - /* - * if the parent_irq is valid, we - * retrigger the parent, otherwise we - * do nothing. - */ - if (!desc->parent_irq) - return; - irq = desc->parent_irq; - } - /* set it pending and activate the softirq: */ - set_bit(irq, irqs_resend); - tasklet_schedule(&resend_tasklet); -#endif - } + if (!desc->irq_data.chip->irq_retrigger || + !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) + return irq_sw_resend(desc); + return 0;
|
PCI
|
1f85b1f5e1f5541272abedc19ba7b6c5b564c228
|
thomas gleixner
|
kernel
|
irq
| |
genirq: sanitize state handling in check_irq_resend()
|
the code sets irqs_replay unconditionally whether the resend happens or not. that doesn't have bad side effects right now, but inconsistent state is always a latent source of problems.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['c']
| 1
| 14
| 8
|
--- diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c + int err = 0; + - if (desc->istate & irqs_pending) { - desc->istate &= ~irqs_pending; - desc->istate |= irqs_replay; + if (!(desc->istate & irqs_pending)) + return 0; - if (!desc->irq_data.chip->irq_retrigger || - !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) - return irq_sw_resend(desc); - } - return 0; + desc->istate &= ~irqs_pending; + + if (!desc->irq_data.chip->irq_retrigger || + !desc->irq_data.chip->irq_retrigger(&desc->irq_data)) + err = irq_sw_resend(desc); + + /* if the retrigger was successfull, mark it with the replay bit */ + if (!err) + desc->istate |= irqs_replay; + return err;
|
PCI
|
da90921acc62c71d27729ae211ccfda5370bf75b
|
thomas gleixner marc zyngier maz kernel org
|
kernel
|
irq
| |
genirq: provide interrupt injection mechanism
|
error injection mechanisms need a half ways safe way to inject interrupts as invoking generic_handle_irq() or the actual device interrupt handler directly from e.g. a debugfs write is not guaranteed to be safe.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['h', 'kconfig', 'c']
| 6
| 61
| 37
|
--- diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h --- a/include/linux/interrupt.h +++ b/include/linux/interrupt.h +extern int irq_inject_interrupt(unsigned int irq); + diff --git a/kernel/irq/kconfig b/kernel/irq/kconfig --- a/kernel/irq/kconfig +++ b/kernel/irq/kconfig +# interrupt injection mechanism +config generic_irq_injection + bool + + select generic_irq_injection ---help--- diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c --- a/kernel/irq/chip.c +++ b/kernel/irq/chip.c - check_irq_resend(desc); + check_irq_resend(desc, false); diff --git a/kernel/irq/debugfs.c b/kernel/irq/debugfs.c --- a/kernel/irq/debugfs.c +++ b/kernel/irq/debugfs.c - unsigned long flags; - int err; - - /* try the hw interface first */ - err = irq_set_irqchip_state(irq_desc_get_irq(desc), - irqchip_state_pending, true); - if (!err) - return count; - - /* - * otherwise, try to inject via the resend interface, - * which may or may not succeed. - */ - chip_bus_lock(desc); - raw_spin_lock_irqsave(&desc->lock, flags); - - /* - * don't allow injection when the interrupt is: - * - level or nmi type - * - not activated - * - replaying already - */ - if (irq_settings_is_level(desc) || - !irqd_is_activated(&desc->irq_data) || - (desc->istate & (irqs_nmi | irqs_replay))) { - err = -einval; - } else { - desc->istate |= irqs_pending; - err = check_irq_resend(desc); - } - - raw_spin_unlock_irqrestore(&desc->lock, flags); - chip_bus_sync_unlock(desc); + int err = irq_inject_interrupt(irq_desc_get_irq(desc)); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h -int check_irq_resend(struct irq_desc *desc); +int check_irq_resend(struct irq_desc *desc, bool inject); diff --git a/kernel/irq/resend.c b/kernel/irq/resend.c --- a/kernel/irq/resend.c +++ b/kernel/irq/resend.c -int check_irq_resend(struct irq_desc *desc) +int check_irq_resend(struct irq_desc *desc, bool inject) - if (!(desc->istate & irqs_pending)) + if (!(desc->istate & irqs_pending) && !inject) + +#ifdef config_generic_irq_injection +/** + * irq_inject_interrupt - inject an interrupt for testing/error injection + * @irq: the interrupt number + * + * this function must only be used for debug and testing purposes! + * + * especially on x86 this can cause a premature completion of an interrupt + * affinity change causing the interrupt line to become stale. very + * unlikely, but possible. + * + * the injection can fail for various reasons: + * - interrupt is not activated + * - interrupt is nmi type or currently replaying + * - interrupt is level type + * - interrupt does not support hardware retrigger and software resend is + * either not enabled or not possible for the interrupt. + */ +int irq_inject_interrupt(unsigned int irq) +{ + struct irq_desc *desc; + unsigned long flags; + int err; + + /* try the state injection hardware interface first */ + if (!irq_set_irqchip_state(irq, irqchip_state_pending, true)) + return 0; + + /* that failed, try via the resend mechanism */ + desc = irq_get_desc_buslock(irq, &flags, 0); + if (!desc) + return -einval; + + /* + * only try to inject when the interrupt is: + * - not nmi type + * - activated + */ + if ((desc->istate & irqs_nmi) || !irqd_is_activated(&desc->irq_data)) + err = -einval; + else + err = check_irq_resend(desc, true); + + irq_put_desc_busunlock(desc, flags); + return err; +} +export_symbol_gpl(irq_inject_interrupt); +#endif
|
PCI
|
acd26bcf362708594ea081ef55140e37d0854ed2
|
thomas gleixner
|
include
|
linux
| |
pci/aer: fix the broken interrupt injection
|
the aer error injection mechanism just blindly abuses generic_handle_irq() which is really not meant for consumption by random drivers. the include of linux/irq.h should have been a red flag in the first place. driver code, unless implementing interrupt chips or low level hypervisor functionality has absolutely no business with that.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
sanitize interrupt injection
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['genirq']
|
['kconfig', 'c']
| 2
| 3
| 4
|
--- diff --git a/drivers/pci/pcie/kconfig b/drivers/pci/pcie/kconfig --- a/drivers/pci/pcie/kconfig +++ b/drivers/pci/pcie/kconfig + select generic_irq_injection diff --git a/drivers/pci/pcie/aer_inject.c b/drivers/pci/pcie/aer_inject.c --- a/drivers/pci/pcie/aer_inject.c +++ b/drivers/pci/pcie/aer_inject.c -#include <linux/irq.h> +#include <linux/interrupt.h> - local_irq_disable(); - generic_handle_irq(edev->irq); - local_irq_enable(); + ret = irq_inject_interrupt(edev->irq);
|
PCI
|
9ae0522537852408f0f48af888e44d6876777463
|
thomas gleixner
|
drivers
|
pci
|
pcie
|
tools: pci: add 'd' command line option to support dma
|
add a new command line option 'd' to use dma for data transfers. it should be used with read, write or copy commands.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add 'd' command-line option to support dma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['tools', 'pcitest']
|
['h', 'c']
| 2
| 26
| 4
|
--- diff --git a/include/uapi/linux/pcitest.h b/include/uapi/linux/pcitest.h --- a/include/uapi/linux/pcitest.h +++ b/include/uapi/linux/pcitest.h +#define pcitest_flags_use_dma 0x00000001 + +struct pci_endpoint_test_xfer_param { + unsigned long size; + unsigned char flags; +}; + diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c --- a/tools/pci/pcitest.c +++ b/tools/pci/pcitest.c + bool use_dma; + struct pci_endpoint_test_xfer_param param; - ret = ioctl(fd, pcitest_write, test->size); + param.size = test->size; + if (test->use_dma) + param.flags = pcitest_flags_use_dma; + ret = ioctl(fd, pcitest_write, ¶m); - ret = ioctl(fd, pcitest_read, test->size); + param.size = test->size; + if (test->use_dma) + param.flags = pcitest_flags_use_dma; + ret = ioctl(fd, pcitest_read, ¶m); - ret = ioctl(fd, pcitest_copy, test->size); + param.size = test->size; + if (test->use_dma) + param.flags = pcitest_flags_use_dma; + ret = ioctl(fd, pcitest_copy, ¶m); - while ((c = getopt(argc, argv, "d🅱️m❌i:ilhrwcs:")) != eof) + while ((c = getopt(argc, argv, "d🅱️m❌i:dilhrwcs:")) != eof) + case 'd': + test->use_dma = true; + continue; + " -d use dma "
|
PCI
|
73c5762652c538527f654b8eb9af47ae2c2434af
|
kishon vijay abraham i alan mikhak alan mikhak sifive com
|
include
|
uapi
|
linux
|
tools: pci: add 'e' to clear irq
|
add a new command line option 'e' to invoke "pcitest_clear_irq" ioctl. this can be used to clear the irqs set using the 'i' option.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add 'd' command-line option to support dma
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['tools', 'pcitest']
|
['c']
| 1
| 15
| 1
|
--- diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c --- a/tools/pci/pcitest.c +++ b/tools/pci/pcitest.c + bool clear_irq; + if (test->clear_irq) { + ret = ioctl(fd, pcitest_clear_irq); + fprintf(stdout, "clear irq: "); + if (ret < 0) + fprintf(stdout, "failed "); + else + fprintf(stdout, "%s ", result[ret]); + } + - while ((c = getopt(argc, argv, "d🅱️m❌i:dilhrwcs:")) != eof) + while ((c = getopt(argc, argv, "d🅱️m❌i:deilhrwcs:")) != eof) + case 'e': + test->clear_irq = true; + continue; + " -e clear irq "
|
PCI
|
74d60b28d5bf1a12abe22d8d88240a4c5d1e3315
|
kishon vijay abraham i
|
tools
|
pci
| |
clk: ingenic: add support for tcu of x1000.
|
x1000 has a different tcu, since x1000 ost has been independent of tcu. this patch is add tcu support of x1000, and prepare for later ost driver.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for tcu of x1000
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['ingenic']
|
['c']
| 1
| 8
| 0
|
--- diff --git a/drivers/clk/ingenic/tcu.c b/drivers/clk/ingenic/tcu.c --- a/drivers/clk/ingenic/tcu.c +++ b/drivers/clk/ingenic/tcu.c +static const struct ingenic_soc_info x1000_soc_info = { + .num_channels = 8, + .has_ost = false, /* x1000 has ost, but it not belong tcu */ + .has_tcu_clk = false, +}; + + { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, }, +clk_of_declare_driver(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);
|
Clock
|
dc6a81c3382f74fe94eb0b8c616493598926efff
|
zhou yanjie
|
drivers
|
clk
|
ingenic
|
clk: at91: add at91rm9200 pmc driver
|
add a driver for the pmc clocks of the at91rm9200.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add at91rm9200 pmc driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['at91']
|
['c', 'makefile']
| 2
| 200
| 0
|
--- diff --git a/drivers/clk/at91/makefile b/drivers/clk/at91/makefile --- a/drivers/clk/at91/makefile +++ b/drivers/clk/at91/makefile +obj-$(config_soc_at91rm9200) += at91rm9200.o diff --git a/drivers/clk/at91/at91rm9200.c b/drivers/clk/at91/at91rm9200.c --- /dev/null +++ b/drivers/clk/at91/at91rm9200.c +// spdx-license-identifier: gpl-2.0 +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/at91.h> + +#include "pmc.h" + +struct sck { + char *n; + char *p; + u8 id; +}; + +struct pck { + char *n; + u8 id; +}; + +static const struct clk_master_characteristics rm9200_mck_characteristics = { + .output = { .min = 0, .max = 80000000 }, + .divisors = { 1, 2, 3, 4 }, +}; + +static u8 rm9200_pll_out[] = { 0, 2 }; + +static const struct clk_range rm9200_pll_outputs[] = { + { .min = 80000000, .max = 160000000 }, + { .min = 150000000, .max = 180000000 }, +}; + +static const struct clk_pll_characteristics rm9200_pll_characteristics = { + .input = { .min = 1000000, .max = 32000000 }, + .num_output = array_size(rm9200_pll_outputs), + .output = rm9200_pll_outputs, + .out = rm9200_pll_out, +}; + +static const struct sck at91rm9200_systemck[] = { + { .n = "udpck", .p = "usbck", .id = 2 }, + { .n = "uhpck", .p = "usbck", .id = 4 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "pck2", .p = "prog2", .id = 10 }, + { .n = "pck3", .p = "prog3", .id = 11 }, +}; + +static const struct pck at91rm9200_periphck[] = { + { .n = "pioa_clk", .id = 2 }, + { .n = "piob_clk", .id = 3 }, + { .n = "pioc_clk", .id = 4 }, + { .n = "piod_clk", .id = 5 }, + { .n = "usart0_clk", .id = 6 }, + { .n = "usart1_clk", .id = 7 }, + { .n = "usart2_clk", .id = 8 }, + { .n = "usart3_clk", .id = 9 }, + { .n = "mci0_clk", .id = 10 }, + { .n = "udc_clk", .id = 11 }, + { .n = "twi0_clk", .id = 12 }, + { .n = "spi0_clk", .id = 13 }, + { .n = "ssc0_clk", .id = 14 }, + { .n = "ssc1_clk", .id = 15 }, + { .n = "ssc2_clk", .id = 16 }, + { .n = "tc0_clk", .id = 17 }, + { .n = "tc1_clk", .id = 18 }, + { .n = "tc2_clk", .id = 19 }, + { .n = "tc3_clk", .id = 20 }, + { .n = "tc4_clk", .id = 21 }, + { .n = "tc5_clk", .id = 22 }, + { .n = "ohci_clk", .id = 23 }, + { .n = "macb0_clk", .id = 24 }, +}; + +static void __init at91rm9200_pmc_setup(struct device_node *np) +{ + const char *slowxtal_name, *mainxtal_name; + struct pmc_data *at91rm9200_pmc; + u32 usb_div[] = { 1, 2, 0, 0 }; + const char *parent_names[6]; + struct regmap *regmap; + struct clk_hw *hw; + int i; + bool bypass; + + i = of_property_match_string(np, "clock-names", "slow_xtal"); + if (i < 0) + return; + + slowxtal_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = device_node_to_regmap(np); + if (is_err(regmap)) + return; + + at91rm9200_pmc = pmc_data_allocate(pmc_main + 1, + nck(at91rm9200_systemck), + nck(at91rm9200_periphck), 0); + if (!at91rm9200_pmc) + return; + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, + bypass); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc"); + if (is_err(hw)) + goto err_free; + + at91rm9200_pmc->chws[pmc_main] = hw; + + hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, + &at91rm9200_pll_layout, + &rm9200_pll_characteristics); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + &at91rm9200_pll_layout, + &rm9200_pll_characteristics); + if (is_err(hw)) + goto err_free; + + parent_names[0] = slowxtal_name; + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + parent_names[3] = "pllbck"; + hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, + &at91rm9200_master_layout, + &rm9200_mck_characteristics); + if (is_err(hw)) + goto err_free; + + at91rm9200_pmc->chws[pmc_mck] = hw; + + hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div); + if (is_err(hw)) + goto err_free; + + parent_names[0] = slowxtal_name; + parent_names[1] = "mainck"; + parent_names[2] = "pllack"; + parent_names[3] = "pllbck"; + for (i = 0; i < 4; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, 4, i, + &at91rm9200_programmable_layout); + if (is_err(hw)) + goto err_free; + } + + for (i = 0; i < array_size(at91rm9200_systemck); i++) { + hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n, + at91rm9200_systemck[i].p, + at91rm9200_systemck[i].id); + if (is_err(hw)) + goto err_free; + + at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw; + } + + for (i = 0; i < array_size(at91rm9200_periphck); i++) { + hw = at91_clk_register_peripheral(regmap, + at91rm9200_periphck[i].n, + "masterck", + at91rm9200_periphck[i].id); + if (is_err(hw)) + goto err_free; + + at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91rm9200_pmc); + + return; + +err_free: + pmc_data_free(at91rm9200_pmc); +} +/* + * while the tcb can be used as the clocksource, the system timer is most likely + * to be used instead. however, the pinctrl driver doesn't support probe + * deferring properly. once this is fixed, this can be switched to a platform + * driver. + */ +clk_of_declare_driver(at91rm9200_pmc, "atmel,at91rm9200-pmc", + at91rm9200_pmc_setup);
|
Clock
|
02ff48e4d7f7f253008f3aeadd41c8a2fc640587
|
alexandre belloni
|
drivers
|
clk
|
at91
|
clk: at91: add at91sam9g45 pmc driver
|
add a driver for the pmc clocks of the at91sam9g45 family.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add at91sam9g45 pmc driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['at91']
|
['c', 'makefile']
| 2
| 221
| 0
|
--- diff --git a/drivers/clk/at91/makefile b/drivers/clk/at91/makefile --- a/drivers/clk/at91/makefile +++ b/drivers/clk/at91/makefile +obj-$(config_soc_at91sam9) += at91sam9g45.o diff --git a/drivers/clk/at91/at91sam9g45.c b/drivers/clk/at91/at91sam9g45.c --- /dev/null +++ b/drivers/clk/at91/at91sam9g45.c +// spdx-license-identifier: gpl-2.0 +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/at91.h> + +#include "pmc.h" + +static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 133333333 }, + .divisors = { 1, 2, 4, 3 }, +}; + +static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; + +static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; + +static const struct clk_range plla_outputs[] = { + { .min = 745000000, .max = 800000000 }, + { .min = 695000000, .max = 750000000 }, + { .min = 645000000, .max = 700000000 }, + { .min = 595000000, .max = 650000000 }, + { .min = 545000000, .max = 600000000 }, + { .min = 495000000, .max = 555000000 }, + { .min = 445000000, .max = 500000000 }, + { .min = 400000000, .max = 450000000 }, +}; + +static const struct clk_pll_characteristics plla_characteristics = { + .input = { .min = 2000000, .max = 32000000 }, + .num_output = array_size(plla_outputs), + .output = plla_outputs, + .icpll = plla_icpll, + .out = plla_out, +}; + +static const struct { + char *n; + char *p; + u8 id; +} at91sam9g45_systemck[] = { + { .n = "ddrck", .p = "masterck", .id = 2 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, +}; + +static const struct clk_pcr_layout at91sam9g45_pcr_layout = { + .offset = 0x10c, + .cmd = bit(12), + .pid_mask = genmask(5, 0), + .div_mask = genmask(17, 16), +}; + +struct pck { + char *n; + u8 id; +}; + +static const struct pck at91sam9g45_periphck[] = { + { .n = "pioa_clk", .id = 2, }, + { .n = "piob_clk", .id = 3, }, + { .n = "pioc_clk", .id = 4, }, + { .n = "piode_clk", .id = 5, }, + { .n = "trng_clk", .id = 6, }, + { .n = "usart0_clk", .id = 7, }, + { .n = "usart1_clk", .id = 8, }, + { .n = "usart2_clk", .id = 9, }, + { .n = "usart3_clk", .id = 10, }, + { .n = "mci0_clk", .id = 11, }, + { .n = "twi0_clk", .id = 12, }, + { .n = "twi1_clk", .id = 13, }, + { .n = "spi0_clk", .id = 14, }, + { .n = "spi1_clk", .id = 15, }, + { .n = "ssc0_clk", .id = 16, }, + { .n = "ssc1_clk", .id = 17, }, + { .n = "tcb0_clk", .id = 18, }, + { .n = "pwm_clk", .id = 19, }, + { .n = "adc_clk", .id = 20, }, + { .n = "dma0_clk", .id = 21, }, + { .n = "uhphs_clk", .id = 22, }, + { .n = "lcd_clk", .id = 23, }, + { .n = "ac97_clk", .id = 24, }, + { .n = "macb0_clk", .id = 25, }, + { .n = "isi_clk", .id = 26, }, + { .n = "udphs_clk", .id = 27, }, + { .n = "aestdessha_clk", .id = 28, }, + { .n = "mci1_clk", .id = 29, }, + { .n = "vdec_clk", .id = 30, }, +}; + +static void __init at91sam9g45_pmc_setup(struct device_node *np) +{ + const char *slck_name, *mainxtal_name; + struct pmc_data *at91sam9g45_pmc; + const char *parent_names[6]; + struct regmap *regmap; + struct clk_hw *hw; + int i; + bool bypass; + + i = of_property_match_string(np, "clock-names", "slow_clk"); + if (i < 0) + return; + + slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = syscon_node_to_regmap(np); + if (is_err(regmap)) + return; + + at91sam9g45_pmc = pmc_data_allocate(pmc_main + 1, + nck(at91sam9g45_systemck), + nck(at91sam9g45_periphck), 0); + if (!at91sam9g45_pmc) + return; + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, + bypass); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc"); + if (is_err(hw)) + goto err_free; + + at91sam9g45_pmc->chws[pmc_main] = hw; + + hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, + &at91rm9200_pll_layout, &plla_characteristics); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_utmi(regmap, null, "utmick", "mainck"); + if (is_err(hw)) + goto err_free; + + at91sam9g45_pmc->chws[pmc_utmi] = hw; + + parent_names[0] = slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; + hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, + &at91rm9200_master_layout, + &mck_characteristics); + if (is_err(hw)) + goto err_free; + + at91sam9g45_pmc->chws[pmc_mck] = hw; + + parent_names[0] = "plladivck"; + parent_names[1] = "utmick"; + hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + if (is_err(hw)) + goto err_free; + + parent_names[0] = slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; + parent_names[4] = "masterck"; + for (i = 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, 5, i, + &at91sam9g45_programmable_layout); + if (is_err(hw)) + goto err_free; + } + + for (i = 0; i < array_size(at91sam9g45_systemck); i++) { + hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n, + at91sam9g45_systemck[i].p, + at91sam9g45_systemck[i].id); + if (is_err(hw)) + goto err_free; + + at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw; + } + + for (i = 0; i < array_size(at91sam9g45_periphck); i++) { + hw = at91_clk_register_peripheral(regmap, + at91sam9g45_periphck[i].n, + "masterck", + at91sam9g45_periphck[i].id); + if (is_err(hw)) + goto err_free; + + at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc); + + return; + +err_free: + pmc_data_free(at91sam9g45_pmc); +} +/* + * the tcb is used as the clocksource so its clock is needed early. this means + * this can't be a platform driver. + */ +clk_of_declare_driver(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", + at91sam9g45_pmc_setup);
|
Clock
|
12dc8d3be9d86cccc35dcf32828d3a8e9d48e0d1
|
alexandre belloni
|
drivers
|
clk
|
at91
|
clk: at91: add at91sam9n12 pmc driver
|
add a driver for the pmc clocks of the at91sam9n12 family.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add at91sam9n12 pmc driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['at91']
|
['c', 'makefile']
| 2
| 239
| 0
|
--- diff --git a/drivers/clk/at91/makefile b/drivers/clk/at91/makefile --- a/drivers/clk/at91/makefile +++ b/drivers/clk/at91/makefile +obj-$(config_soc_at91sam9) += at91sam9n12.o at91sam9x5.o diff --git a/drivers/clk/at91/at91sam9n12.c b/drivers/clk/at91/at91sam9n12.c --- /dev/null +++ b/drivers/clk/at91/at91sam9n12.c +// spdx-license-identifier: gpl-2.0 +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/at91.h> + +#include "pmc.h" + +static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 133333333 }, + .divisors = { 1, 2, 4, 3 }, + .have_div3_pres = 1, +}; + +static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 }; + +static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 }; + +static const struct clk_range plla_outputs[] = { + { .min = 745000000, .max = 800000000 }, + { .min = 695000000, .max = 750000000 }, + { .min = 645000000, .max = 700000000 }, + { .min = 595000000, .max = 650000000 }, + { .min = 545000000, .max = 600000000 }, + { .min = 495000000, .max = 555000000 }, + { .min = 445000000, .max = 500000000 }, + { .min = 400000000, .max = 450000000 }, +}; + +static const struct clk_pll_characteristics plla_characteristics = { + .input = { .min = 2000000, .max = 32000000 }, + .num_output = array_size(plla_outputs), + .output = plla_outputs, + .icpll = plla_icpll, + .out = plla_out, +}; + +static u8 pllb_out[] = { 0 }; + +static const struct clk_range pllb_outputs[] = { + { .min = 30000000, .max = 100000000 }, +}; + +static const struct clk_pll_characteristics pllb_characteristics = { + .input = { .min = 2000000, .max = 32000000 }, + .num_output = array_size(pllb_outputs), + .output = pllb_outputs, + .out = pllb_out, +}; + +static const struct { + char *n; + char *p; + u8 id; +} at91sam9n12_systemck[] = { + { .n = "ddrck", .p = "masterck", .id = 2 }, + { .n = "lcdck", .p = "masterck", .id = 3 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, +}; + +static const struct clk_pcr_layout at91sam9n12_pcr_layout = { + .offset = 0x10c, + .cmd = bit(12), + .pid_mask = genmask(5, 0), + .div_mask = genmask(17, 16), +}; + +struct pck { + char *n; + u8 id; +}; + +static const struct pck at91sam9n12_periphck[] = { + { .n = "pioab_clk", .id = 2, }, + { .n = "piocd_clk", .id = 3, }, + { .n = "fuse_clk", .id = 4, }, + { .n = "usart0_clk", .id = 5, }, + { .n = "usart1_clk", .id = 6, }, + { .n = "usart2_clk", .id = 7, }, + { .n = "usart3_clk", .id = 8, }, + { .n = "twi0_clk", .id = 9, }, + { .n = "twi1_clk", .id = 10, }, + { .n = "mci0_clk", .id = 12, }, + { .n = "spi0_clk", .id = 13, }, + { .n = "spi1_clk", .id = 14, }, + { .n = "uart0_clk", .id = 15, }, + { .n = "uart1_clk", .id = 16, }, + { .n = "tcb_clk", .id = 17, }, + { .n = "pwm_clk", .id = 18, }, + { .n = "adc_clk", .id = 19, }, + { .n = "dma0_clk", .id = 20, }, + { .n = "uhphs_clk", .id = 22, }, + { .n = "udphs_clk", .id = 23, }, + { .n = "lcdc_clk", .id = 25, }, + { .n = "sha_clk", .id = 27, }, + { .n = "ssc0_clk", .id = 28, }, + { .n = "aes_clk", .id = 29, }, + { .n = "trng_clk", .id = 30, }, +}; + +static void __init at91sam9n12_pmc_setup(struct device_node *np) +{ + struct clk_range range = clk_range(0, 0); + const char *slck_name, *mainxtal_name; + struct pmc_data *at91sam9n12_pmc; + const char *parent_names[6]; + struct regmap *regmap; + struct clk_hw *hw; + int i; + bool bypass; + + i = of_property_match_string(np, "clock-names", "slow_clk"); + if (i < 0) + return; + + slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = syscon_node_to_regmap(np); + if (is_err(regmap)) + return; + + at91sam9n12_pmc = pmc_data_allocate(pmc_main + 1, + nck(at91sam9n12_systemck), 31, 0); + if (!at91sam9n12_pmc) + return; + + hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (is_err(hw)) + goto err_free; + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, + bypass); + if (is_err(hw)) + goto err_free; + + parent_names[0] = "main_rc_osc"; + parent_names[1] = "main_osc"; + hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); + if (is_err(hw)) + goto err_free; + + at91sam9n12_pmc->chws[pmc_main] = hw; + + hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, + &at91rm9200_pll_layout, &plla_characteristics); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1, + &at91rm9200_pll_layout, &pllb_characteristics); + if (is_err(hw)) + goto err_free; + + parent_names[0] = slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "pllbck"; + hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, + &at91sam9x5_master_layout, + &mck_characteristics); + if (is_err(hw)) + goto err_free; + + at91sam9n12_pmc->chws[pmc_mck] = hw; + + hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck"); + if (is_err(hw)) + goto err_free; + + parent_names[0] = slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "pllbck"; + parent_names[4] = "masterck"; + for (i = 0; i < 2; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, 5, i, + &at91sam9x5_programmable_layout); + if (is_err(hw)) + goto err_free; + } + + for (i = 0; i < array_size(at91sam9n12_systemck); i++) { + hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n, + at91sam9n12_systemck[i].p, + at91sam9n12_systemck[i].id); + if (is_err(hw)) + goto err_free; + + at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw; + } + + for (i = 0; i < array_size(at91sam9n12_periphck); i++) { + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &at91sam9n12_pcr_layout, + at91sam9n12_periphck[i].n, + "masterck", + at91sam9n12_periphck[i].id, + &range); + if (is_err(hw)) + goto err_free; + + at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc); + + return; + +err_free: + pmc_data_free(at91sam9n12_pmc); +} +/* + * the tcb is used as the clocksource so its clock is needed early. this means + * this can't be a platform driver. + */ +clk_of_declare_driver(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", + at91sam9n12_pmc_setup);
|
Clock
|
143e04dab6b4c73c66b1708f6bc3212b9cb71dbb
|
alexandre belloni
|
drivers
|
clk
|
at91
|
clk: at91: add sama5d3 pmc driver
|
add a driver for the pmc clocks of the sama5d3.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add sama5d3 pmc driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['at91']
|
['c', 'makefile']
| 2
| 241
| 0
|
--- diff --git a/drivers/clk/at91/makefile b/drivers/clk/at91/makefile --- a/drivers/clk/at91/makefile +++ b/drivers/clk/at91/makefile +obj-$(config_soc_sama5d3) += sama5d3.o diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c --- /dev/null +++ b/drivers/clk/at91/sama5d3.c +// spdx-license-identifier: gpl-2.0 +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/at91.h> + +#include "pmc.h" + +static const struct clk_master_characteristics mck_characteristics = { + .output = { .min = 0, .max = 166000000 }, + .divisors = { 1, 2, 4, 3 }, +}; + +static u8 plla_out[] = { 0 }; + +static u16 plla_icpll[] = { 0 }; + +static const struct clk_range plla_outputs[] = { + { .min = 400000000, .max = 1000000000 }, +}; + +static const struct clk_pll_characteristics plla_characteristics = { + .input = { .min = 8000000, .max = 50000000 }, + .num_output = array_size(plla_outputs), + .output = plla_outputs, + .icpll = plla_icpll, + .out = plla_out, +}; + +static const struct clk_pcr_layout sama5d3_pcr_layout = { + .offset = 0x10c, + .cmd = bit(12), + .pid_mask = genmask(6, 0), + .div_mask = genmask(17, 16), +}; + +static const struct { + char *n; + char *p; + u8 id; +} sama5d3_systemck[] = { + { .n = "ddrck", .p = "masterck", .id = 2 }, + { .n = "lcdck", .p = "masterck", .id = 3 }, + { .n = "smdck", .p = "smdclk", .id = 4 }, + { .n = "uhpck", .p = "usbck", .id = 6 }, + { .n = "udpck", .p = "usbck", .id = 7 }, + { .n = "pck0", .p = "prog0", .id = 8 }, + { .n = "pck1", .p = "prog1", .id = 9 }, + { .n = "pck2", .p = "prog2", .id = 10 }, +}; + +static const struct { + char *n; + u8 id; + struct clk_range r; +} sama5d3_periphck[] = { + { .n = "dbgu_clk", .id = 2, }, + { .n = "hsmc_clk", .id = 5, }, + { .n = "pioa_clk", .id = 6, }, + { .n = "piob_clk", .id = 7, }, + { .n = "pioc_clk", .id = 8, }, + { .n = "piod_clk", .id = 9, }, + { .n = "pioe_clk", .id = 10, }, + { .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, }, + { .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, }, + { .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, }, + { .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, }, + { .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, }, + { .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, }, + { .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, }, + { .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, }, + { .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, }, + { .n = "mci0_clk", .id = 21, }, + { .n = "mci1_clk", .id = 22, }, + { .n = "mci2_clk", .id = 23, }, + { .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, }, + { .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, }, + { .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, }, + { .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, }, + { .n = "pwm_clk", .id = 28, }, + { .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, }, + { .n = "dma0_clk", .id = 30, }, + { .n = "dma1_clk", .id = 31, }, + { .n = "uhphs_clk", .id = 32, }, + { .n = "udphs_clk", .id = 33, }, + { .n = "macb0_clk", .id = 34, }, + { .n = "macb1_clk", .id = 35, }, + { .n = "lcdc_clk", .id = 36, }, + { .n = "isi_clk", .id = 37, }, + { .n = "ssc0_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, }, + { .n = "ssc1_clk", .id = 39, .r = { .min = 0, .max = 83000000 }, }, + { .n = "can0_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, }, + { .n = "can1_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, }, + { .n = "sha_clk", .id = 42, }, + { .n = "aes_clk", .id = 43, }, + { .n = "tdes_clk", .id = 44, }, + { .n = "trng_clk", .id = 45, }, + { .n = "fuse_clk", .id = 48, }, + { .n = "mpddr_clk", .id = 49, }, +}; + +static void __init sama5d3_pmc_setup(struct device_node *np) +{ + const char *slck_name, *mainxtal_name; + struct pmc_data *sama5d3_pmc; + const char *parent_names[5]; + struct regmap *regmap; + struct clk_hw *hw; + int i; + bool bypass; + + i = of_property_match_string(np, "clock-names", "slow_clk"); + if (i < 0) + return; + + slck_name = of_clk_get_parent_name(np, i); + + i = of_property_match_string(np, "clock-names", "main_xtal"); + if (i < 0) + return; + mainxtal_name = of_clk_get_parent_name(np, i); + + regmap = syscon_node_to_regmap(np); + if (is_err(regmap)) + return; + + sama5d3_pmc = pmc_data_allocate(pmc_main + 1, + nck(sama5d3_systemck), + nck(sama5d3_periphck), 0); + if (!sama5d3_pmc) + return; + + hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000, + 50000000); + if (is_err(hw)) + goto err_free; + + bypass = of_property_read_bool(np, "atmel,osc-bypass"); + + hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, + bypass); + if (is_err(hw)) + goto err_free; + + parent_names[0] = "main_rc_osc"; + parent_names[1] = "main_osc"; + hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0, + &sama5d3_pll_layout, &plla_characteristics); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack"); + if (is_err(hw)) + goto err_free; + + hw = at91_clk_register_utmi(regmap, null, "utmick", "mainck"); + if (is_err(hw)) + goto err_free; + + sama5d3_pmc->chws[pmc_utmi] = hw; + + parent_names[0] = slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; + hw = at91_clk_register_master(regmap, "masterck", 4, parent_names, + &at91sam9x5_master_layout, + &mck_characteristics); + if (is_err(hw)) + goto err_free; + + sama5d3_pmc->chws[pmc_mck] = hw; + + parent_names[0] = "plladivck"; + parent_names[1] = "utmick"; + hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2); + if (is_err(hw)) + goto err_free; + + hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2); + if (is_err(hw)) + goto err_free; + + parent_names[0] = slck_name; + parent_names[1] = "mainck"; + parent_names[2] = "plladivck"; + parent_names[3] = "utmick"; + parent_names[4] = "masterck"; + for (i = 0; i < 3; i++) { + char name[6]; + + snprintf(name, sizeof(name), "prog%d", i); + + hw = at91_clk_register_programmable(regmap, name, + parent_names, 5, i, + &at91sam9x5_programmable_layout); + if (is_err(hw)) + goto err_free; + } + + for (i = 0; i < array_size(sama5d3_systemck); i++) { + hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n, + sama5d3_systemck[i].p, + sama5d3_systemck[i].id); + if (is_err(hw)) + goto err_free; + + sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw; + } + + for (i = 0; i < array_size(sama5d3_periphck); i++) { + hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock, + &sama5d3_pcr_layout, + sama5d3_periphck[i].n, + "masterck", + sama5d3_periphck[i].id, + &sama5d3_periphck[i].r); + if (is_err(hw)) + goto err_free; + + sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw; + } + + of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d3_pmc); + + return; + +err_free: + pmc_data_free(sama5d3_pmc); +} +/* + * the tcb is used as the clocksource so its clock is needed early. this means + * this can't be a platform driver. + */ +clk_of_declare_driver(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
|
Clock
|
0969b242f7b8e5de0a1c28f81d8558fd678c066d
|
alexandre belloni
|
drivers
|
clk
|
at91
|
clk: imx7d: add pxp clock
|
the pxp has a single ccgr clock gate, gating both the ipg_clk_root and the main_axi_clk_root. add a single clock to cover both.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add pxp clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['imx7d']
|
['h', 'c']
| 2
| 3
| 1
|
--- diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c + hws[imx7d_pxp_clk] = imx_clk_hw_gate4("pxp_clk", "main_axi_root_clk", base + 0x44c0, 0); diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h -#define imx7d_clk_end 445 +#define imx7d_pxp_clk 445 +#define imx7d_clk_end 446
|
Clock
|
4ae9afbaaeb9bd939ac2bb8d53828fdebca5ec1b
|
laurent pinchart
|
include
|
dt-bindings
|
clock, imx
|
clk: imx8mm: add clko2 support
|
add clko2 support, which is useful for debugging purposes.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add clko2 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['imx8mm']
|
['h', 'c']
| 2
| 6
| 1
|
--- diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c +static const char *imx8mm_clko2_sels[] = {"osc_24m", "sys_pll2_200m", "sys_pll1_400m", "sys_pll2_166m", + "sys_pll3_out", "audio_pll1_out", "video_pll1_out", "osc_32k", }; + hws[imx8mm_clk_clko2] = imx8m_clk_hw_composite("clko2", imx8mm_clko2_sels, base + 0xba80); diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h -#define imx8mm_clk_end 250 +#define imx8mm_clk_clko2 250 + +#define imx8mm_clk_end 251
|
Clock
|
9c07ae6983d434841bb19bea0a75bd0fd925a75c
|
fabio estevam abel vesa abel vesa nxp com
|
include
|
dt-bindings
|
clock, imx
|
clk: keystone: add new driver to handle syscon based clocks
|
on ti's am654/j721e socs, certain clocks can be gated/ungated by setting a single bit in soc's system control module registers. sometime more than one clock control can be in the same register.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add new driver to handle syscon based clocks
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['keystone']
|
['kconfig', 'c', 'makefile']
| 3
| 181
| 0
|
--- diff --git a/drivers/clk/keystone/kconfig b/drivers/clk/keystone/kconfig --- a/drivers/clk/keystone/kconfig +++ b/drivers/clk/keystone/kconfig + +config ti_syscon_clk + tristate "syscon based clock driver for k2/k3 socs" + depends on arch_keystone || arch_k3 || compile_test + default arch_keystone || arch_k3 + help + this adds clock driver support for syscon based gate + clocks on ti's k2 and k3 socs. diff --git a/drivers/clk/keystone/makefile b/drivers/clk/keystone/makefile --- a/drivers/clk/keystone/makefile +++ b/drivers/clk/keystone/makefile +obj-$(config_ti_syscon_clk) += syscon-clk.o diff --git a/drivers/clk/keystone/syscon-clk.c b/drivers/clk/keystone/syscon-clk.c --- /dev/null +++ b/drivers/clk/keystone/syscon-clk.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2020 texas instruments incorporated - http://www.ti.com/ + */ + +#include <linux/clk-provider.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> + +struct ti_syscon_gate_clk_priv { + struct clk_hw hw; + struct regmap *regmap; + u32 reg; + u32 idx; +}; + +struct ti_syscon_gate_clk_data { + char *name; + u32 offset; + u32 bit_idx; +}; + +static struct +ti_syscon_gate_clk_priv *to_ti_syscon_gate_clk_priv(struct clk_hw *hw) +{ + return container_of(hw, struct ti_syscon_gate_clk_priv, hw); +} + +static int ti_syscon_gate_clk_enable(struct clk_hw *hw) +{ + struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw); + + return regmap_write_bits(priv->regmap, priv->reg, priv->idx, + priv->idx); +} + +static void ti_syscon_gate_clk_disable(struct clk_hw *hw) +{ + struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw); + + regmap_write_bits(priv->regmap, priv->reg, priv->idx, 0); +} + +static int ti_syscon_gate_clk_is_enabled(struct clk_hw *hw) +{ + unsigned int val; + struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw); + + regmap_read(priv->regmap, priv->reg, &val); + + return !!(val & priv->idx); +} + +static const struct clk_ops ti_syscon_gate_clk_ops = { + .enable = ti_syscon_gate_clk_enable, + .disable = ti_syscon_gate_clk_disable, + .is_enabled = ti_syscon_gate_clk_is_enabled, +}; + +static struct clk_hw +*ti_syscon_gate_clk_register(struct device *dev, struct regmap *regmap, + const struct ti_syscon_gate_clk_data *data) +{ + struct ti_syscon_gate_clk_priv *priv; + struct clk_init_data init; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return err_ptr(-enomem); + + init.name = data->name; + init.ops = &ti_syscon_gate_clk_ops; + init.parent_names = null; + init.num_parents = 0; + init.flags = 0; + + priv->regmap = regmap; + priv->reg = data->offset; + priv->idx = bit(data->bit_idx); + priv->hw.init = &init; + + ret = devm_clk_hw_register(dev, &priv->hw); + if (ret) + return err_ptr(ret); + + return &priv->hw; +} + +static int ti_syscon_gate_clk_probe(struct platform_device *pdev) +{ + const struct ti_syscon_gate_clk_data *data, *p; + struct clk_hw_onecell_data *hw_data; + struct device *dev = &pdev->dev; + struct regmap *regmap; + int num_clks, i; + + data = device_get_match_data(dev); + if (!data) + return -einval; + + regmap = syscon_node_to_regmap(dev->of_node); + if (is_err(regmap)) { + if (ptr_err(regmap) == -eprobe_defer) + return -eprobe_defer; + dev_err(dev, "failed to find parent regmap "); + return ptr_err(regmap); + } + + num_clks = 0; + for (p = data; p->name; p++) + num_clks++; + + hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks), + gfp_kernel); + if (!hw_data) + return -enomem; + + hw_data->num = num_clks; + + for (i = 0; i < num_clks; i++) { + hw_data->hws[i] = ti_syscon_gate_clk_register(dev, regmap, + &data[i]); + if (is_err(hw_data->hws[i])) + dev_warn(dev, "failed to register %s ", + data[i].name); + } + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, + hw_data); +} + +#define ti_syscon_clk_gate(_name, _offset, _bit_idx) \ + { \ + .name = _name, \ + .offset = (_offset), \ + .bit_idx = (_bit_idx), \ + } + +static const struct ti_syscon_gate_clk_data am654_clk_data[] = { + ti_syscon_clk_gate("ehrpwm_tbclk0", 0x0, 0), + ti_syscon_clk_gate("ehrpwm_tbclk1", 0x4, 0), + ti_syscon_clk_gate("ehrpwm_tbclk2", 0x8, 0), + ti_syscon_clk_gate("ehrpwm_tbclk3", 0xc, 0), + ti_syscon_clk_gate("ehrpwm_tbclk4", 0x10, 0), + ti_syscon_clk_gate("ehrpwm_tbclk5", 0x14, 0), + { /* sentinel */ }, +}; + +static const struct of_device_id ti_syscon_gate_clk_ids[] = { + { + .compatible = "ti,am654-ehrpwm-tbclk", + .data = &am654_clk_data, + }, + { } +}; +module_device_table(of, ti_syscon_gate_clk_ids); + +static struct platform_driver ti_syscon_gate_clk_driver = { + .probe = ti_syscon_gate_clk_probe, + .driver = { + .name = "ti-syscon-gate-clk", + .of_match_table = ti_syscon_gate_clk_ids, + }, +}; +module_platform_driver(ti_syscon_gate_clk_driver); + +module_author("vignesh raghavendra <vigneshr@ti.com>"); +module_description("syscon backed gate-clock driver"); +module_license("gpl");
|
Clock
|
1aa0817e43c525c3ee035786a17a19077a0bb06a
|
vignesh raghavendra
|
drivers
|
clk
|
keystone
|
clk: meson: g12a: add support for the spicc sclk source clocks
|
this adds the clocks used for the amlogic g12a and compatible socs spicc controller to provide a more complete range of frequencies instead of the spicc internal divider over xtal.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for the spicc sclk source clocks
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['meson', 'g12a']
|
['h', 'c']
| 2
| 134
| 1
|
--- diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c +/* spicc sclk source clock */ + +static const struct clk_parent_data spicc_sclk_parent_data[] = { + { .fw_name = "xtal", }, + { .hw = &g12a_clk81.hw }, + { .hw = &g12a_fclk_div4.hw }, + { .hw = &g12a_fclk_div3.hw }, + { .hw = &g12a_fclk_div5.hw }, + { .hw = &g12a_fclk_div7.hw }, +}; + +static struct clk_regmap g12a_spicc0_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = hhi_spicc_clk_cntl, + .mask = 7, + .shift = 7, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = array_size(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc0_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = hhi_spicc_clk_cntl, + .shift = 0, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_sel.hw + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_regmap g12a_spicc0_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = hhi_spicc_clk_cntl, + .bit_idx = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc0_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc0_sclk_div.hw + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = hhi_spicc_clk_cntl, + .mask = 7, + .shift = 23, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_sel", + .ops = &clk_regmap_mux_ops, + .parent_data = spicc_sclk_parent_data, + .num_parents = array_size(spicc_sclk_parent_data), + }, +}; + +static struct clk_regmap g12a_spicc1_sclk_div = { + .data = &(struct clk_regmap_div_data){ + .offset = hhi_spicc_clk_cntl, + .shift = 16, + .width = 6, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk_div", + .ops = &clk_regmap_divider_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_sel.hw + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + }, +}; + +static struct clk_regmap g12a_spicc1_sclk = { + .data = &(struct clk_regmap_gate_data){ + .offset = hhi_spicc_clk_cntl, + .bit_idx = 22, + }, + .hw.init = &(struct clk_init_data){ + .name = "spicc1_sclk", + .ops = &clk_regmap_gate_ops, + .parent_hws = (const struct clk_hw *[]) { + &g12a_spicc1_sclk_div.hw + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + }, +}; + + [clkid_spicc0_sclk_sel] = &g12a_spicc0_sclk_sel.hw, + [clkid_spicc0_sclk_div] = &g12a_spicc0_sclk_div.hw, + [clkid_spicc0_sclk] = &g12a_spicc0_sclk.hw, + [clkid_spicc1_sclk_sel] = &g12a_spicc1_sclk_sel.hw, + [clkid_spicc1_sclk_div] = &g12a_spicc1_sclk_div.hw, + [clkid_spicc1_sclk] = &g12a_spicc1_sclk.hw, + [clkid_spicc0_sclk_sel] = &g12a_spicc0_sclk_sel.hw, + [clkid_spicc0_sclk_div] = &g12a_spicc0_sclk_div.hw, + [clkid_spicc0_sclk] = &g12a_spicc0_sclk.hw, + [clkid_spicc1_sclk_sel] = &g12a_spicc1_sclk_sel.hw, + [clkid_spicc1_sclk_div] = &g12a_spicc1_sclk_div.hw, + [clkid_spicc1_sclk] = &g12a_spicc1_sclk.hw, + [clkid_spicc0_sclk_sel] = &g12a_spicc0_sclk_sel.hw, + [clkid_spicc0_sclk_div] = &g12a_spicc0_sclk_div.hw, + [clkid_spicc0_sclk] = &g12a_spicc0_sclk.hw, + [clkid_spicc1_sclk_sel] = &g12a_spicc1_sclk_sel.hw, + [clkid_spicc1_sclk_div] = &g12a_spicc1_sclk_div.hw, + [clkid_spicc1_sclk] = &g12a_spicc1_sclk.hw, + &g12a_spicc0_sclk_sel, + &g12a_spicc0_sclk_div, + &g12a_spicc0_sclk, + &g12a_spicc1_sclk_sel, + &g12a_spicc1_sclk_div, + &g12a_spicc1_sclk, diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h --- a/drivers/clk/meson/g12a.h +++ b/drivers/clk/meson/g12a.h +#define clkid_spicc0_sclk_sel 256 +#define clkid_spicc0_sclk_div 257 +#define clkid_spicc1_sclk_sel 259 +#define clkid_spicc1_sclk_div 260 -#define nr_clks 256 +#define nr_clks 262
|
Clock
|
a18c8e0b76979881f3b31e96c398e62ab30a1662
|
neil armstrong
|
drivers
|
clk
|
meson
|
clk: mmp2: add clocks for the thermal sensors
|
the register definitions gotten from olpc open firmware.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add clocks for the thermal sensors
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['mmp2']
|
['c']
| 1
| 16
| 0
|
--- diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c +#define apbc_thermal0 0x90 +#define apbc_thermal1 0x98 +#define apbc_thermal2 0x9c +#define apbc_thermal3 0xa0 + {mmp2_clk_thermal0, "thermal0_clk", "vctcxo", clk_set_rate_parent, apbc_thermal0, 0x7, 0x3, 0x0, mmp_clk_gate_need_delay, &reset_lock}, +}; + +static struct mmp_param_gate_clk mmp3_apbc_gate_clks[] = { + {mmp3_clk_thermal1, "thermal1_clk", "vctcxo", clk_set_rate_parent, apbc_thermal1, 0x7, 0x3, 0x0, mmp_clk_gate_need_delay, &reset_lock}, + {mmp3_clk_thermal2, "thermal2_clk", "vctcxo", clk_set_rate_parent, apbc_thermal2, 0x7, 0x3, 0x0, mmp_clk_gate_need_delay, &reset_lock}, + {mmp3_clk_thermal3, "thermal3_clk", "vctcxo", clk_set_rate_parent, apbc_thermal3, 0x7, 0x3, 0x0, mmp_clk_gate_need_delay, &reset_lock}, + + if (pxa_unit->model == clk_model_mmp3) { + mmp_register_gate_clks(unit, mmp3_apbc_gate_clks, pxa_unit->apbc_base, + array_size(mmp3_apbc_gate_clks)); + }
|
Clock
|
82d59c382c230fb26fe193c9e1b5239d8fcb2d77
|
lubomir rintel
|
drivers
|
clk
|
mmp
|
clk: mmp2: add support for pll clock sources
|
the clk-of-mmp2 driver pretends that the clock outputs from the plls are constant, but in fact they are configurable.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for pll clock sources
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['mmp2']
|
['h', 'c', 'makefile']
| 4
| 195
| 1
|
--- diff --git a/drivers/clk/mmp/makefile b/drivers/clk/mmp/makefile --- a/drivers/clk/mmp/makefile +++ b/drivers/clk/mmp/makefile -obj-$(config_common_clk_mmp2) += clk-of-mmp2.o +obj-$(config_common_clk_mmp2) += clk-of-mmp2.o clk-pll.o diff --git a/drivers/clk/mmp/clk-pll.c b/drivers/clk/mmp/clk-pll.c --- /dev/null +++ b/drivers/clk/mmp/clk-pll.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * mmp pll clock rate calculation + * + * copyright (c) 2020 lubomir rintel <lkundrak@v3.sk> + */ + +#include <linux/clk-provider.h> +#include <linux/slab.h> +#include <linux/io.h> + +#include "clk.h" + +#define to_clk_mmp_pll(hw) container_of(hw, struct mmp_clk_pll, hw) + +struct mmp_clk_pll { + struct clk_hw hw; + unsigned long default_rate; + void __iomem *enable_reg; + u32 enable; + void __iomem *reg; + u8 shift; + + unsigned long input_rate; + void __iomem *postdiv_reg; + u8 postdiv_shift; +}; + +static int mmp_clk_pll_is_enabled(struct clk_hw *hw) +{ + struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); + u32 val; + + val = readl_relaxed(pll->enable_reg); + if ((val & pll->enable) == pll->enable) + return 1; + + /* some plls, if not software controlled, output default clock. */ + if (pll->default_rate > 0) + return 1; + + return 0; +} + +static unsigned long mmp_clk_pll_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct mmp_clk_pll *pll = to_clk_mmp_pll(hw); + u32 fbdiv, refdiv, postdiv; + u64 rate; + u32 val; + + val = readl_relaxed(pll->enable_reg); + if ((val & pll->enable) != pll->enable) + return pll->default_rate; + + if (pll->reg) { + val = readl_relaxed(pll->reg); + fbdiv = (val >> pll->shift) & 0x1ff; + refdiv = (val >> (pll->shift + 9)) & 0x1f; + } else { + fbdiv = 2; + refdiv = 1; + } + + if (pll->postdiv_reg) { + /* mmp3 clock rate calculation */ + static const u8 postdivs[] = {2, 3, 4, 5, 6, 8, 10, 12, 16}; + + val = readl_relaxed(pll->postdiv_reg); + postdiv = (val >> pll->postdiv_shift) & 0x7; + + rate = pll->input_rate; + rate *= 2 * fbdiv; + do_div(rate, refdiv); + do_div(rate, postdivs[postdiv]); + } else { + /* mmp2 clock rate calculation */ + if (refdiv == 3) { + rate = 19200000; + } else if (refdiv == 4) { + rate = 26000000; + } else { + pr_err("bad refdiv: %d (0x%08x) ", refdiv, val); + return 0; + } + + rate *= fbdiv + 2; + do_div(rate, refdiv + 2); + } + + return (unsigned long)rate; +} + +static const struct clk_ops mmp_clk_pll_ops = { + .is_enabled = mmp_clk_pll_is_enabled, + .recalc_rate = mmp_clk_pll_recalc_rate, +}; + +struct clk *mmp_clk_register_pll(char *name, + unsigned long default_rate, + void __iomem *enable_reg, u32 enable, + void __iomem *reg, u8 shift, + unsigned long input_rate, + void __iomem *postdiv_reg, u8 postdiv_shift) +{ + struct mmp_clk_pll *pll; + struct clk *clk; + struct clk_init_data init; + + pll = kzalloc(sizeof(*pll), gfp_kernel); + if (!pll) + return err_ptr(-enomem); + + init.name = name; + init.ops = &mmp_clk_pll_ops; + init.flags = 0; + init.parent_names = null; + init.num_parents = 0; + + pll->default_rate = default_rate; + pll->enable_reg = enable_reg; + pll->enable = enable; + pll->reg = reg; + pll->shift = shift; + + pll->input_rate = input_rate; + pll->postdiv_reg = postdiv_reg; + pll->postdiv_shift = postdiv_shift; + + pll->hw.init = &init; + + clk = clk_register(null, &pll->hw); + + if (is_err(clk)) + kfree(pll); + + return clk; +} diff --git a/drivers/clk/mmp/clk.c b/drivers/clk/mmp/clk.c --- a/drivers/clk/mmp/clk.c +++ b/drivers/clk/mmp/clk.c +void mmp_register_pll_clks(struct mmp_clk_unit *unit, + struct mmp_param_pll_clk *clks, + void __iomem *base, int size) +{ + struct clk *clk; + int i; + + for (i = 0; i < size; i++) { + void __iomem *reg = null; + + if (clks[i].offset) + reg = base + clks[i].offset; + + clk = mmp_clk_register_pll(clks[i].name, + clks[i].default_rate, + base + clks[i].enable_offset, + clks[i].enable, + reg, clks[i].shift, + clks[i].input_rate, + base + clks[i].postdiv_offset, + clks[i].postdiv_shift); + if (is_err(clk)) { + pr_err("%s: failed to register clock %s ", + __func__, clks[i].name); + continue; + } + if (clks[i].id) + unit->clk_table[clks[i].id] = clk; + } +} + diff --git a/drivers/clk/mmp/clk.h b/drivers/clk/mmp/clk.h --- a/drivers/clk/mmp/clk.h +++ b/drivers/clk/mmp/clk.h +struct mmp_param_pll_clk { + unsigned int id; + char *name; + unsigned long default_rate; + unsigned long enable_offset; + u32 enable; + unsigned long offset; + u8 shift; + /* mmp3 specific: */ + unsigned long input_rate; + unsigned long postdiv_offset; + unsigned long postdiv_shift; +}; +void mmp_register_pll_clks(struct mmp_clk_unit *unit, + struct mmp_param_pll_clk *clks, + void __iomem *base, int size); + +extern struct clk *mmp_clk_register_pll(char *name, + unsigned long default_rate, + void __iomem *enable_reg, u32 enable, + void __iomem *reg, u8 shift, + unsigned long input_rate, + void __iomem *postdiv_reg, u8 postdiv_shift); +
|
Clock
|
5d34d0b32d6c13947b0aa890fc4c68f203491169
|
lubomir rintel
|
drivers
|
clk
|
mmp
|
clk: qcom: add modem clock controller driver for sc7180
|
add support for the modem clock controller found on sc7180 based devices. this would allow modem drivers to probe and control their clocks.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add modem clock controller driver for sc7180
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qcom']
|
['kconfig', 'c', 'makefile']
| 3
| 153
| 0
|
--- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config sc_mss_7180 + tristate "sc7180 modem clock controller" + select sc_gcc_7180 + help + support for the modem subsystem clock controller on qualcomm + technologies, inc on sc7180 devices. + say y if you want to use the modem branch clocks of the modem + subsystem clock controller to reset the mss subsystem. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_sc_mss_7180) += mss-sc7180.o diff --git a/drivers/clk/qcom/mss-sc7180.c b/drivers/clk/qcom/mss-sc7180.c --- /dev/null +++ b/drivers/clk/qcom/mss-sc7180.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2020, the linux foundation. all rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/platform_device.h> +#include <linux/module.h> +#include <linux/pm_clock.h> +#include <linux/pm_runtime.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,mss-sc7180.h> + +#include "clk-regmap.h" +#include "clk-branch.h" +#include "common.h" + +static struct clk_branch mss_axi_nav_clk = { + .halt_reg = 0x20bc, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x20bc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mss_axi_nav_clk", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "gcc_mss_nav_axi", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch mss_axi_crypto_clk = { + .halt_reg = 0x20cc, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x20cc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "mss_axi_crypto_clk", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "gcc_mss_mfab_axis", + }, + .num_parents = 1, + .ops = &clk_branch2_ops, + }, + }, +}; + +static const struct regmap_config mss_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .fast_io = true, + .max_register = 0x41aa0cc, +}; + +static struct clk_regmap *mss_sc7180_clocks[] = { + [mss_axi_crypto_clk] = &mss_axi_crypto_clk.clkr, + [mss_axi_nav_clk] = &mss_axi_nav_clk.clkr, +}; + +static const struct qcom_cc_desc mss_sc7180_desc = { + .config = &mss_regmap_config, + .clks = mss_sc7180_clocks, + .num_clks = array_size(mss_sc7180_clocks), +}; + +static int mss_sc7180_probe(struct platform_device *pdev) +{ + int ret; + + pm_runtime_enable(&pdev->dev); + ret = pm_clk_create(&pdev->dev); + if (ret) + goto disable_pm_runtime; + + ret = pm_clk_add(&pdev->dev, "cfg_ahb"); + if (ret < 0) { + dev_err(&pdev->dev, "failed to acquire iface clock "); + goto destroy_pm_clk; + } + + ret = qcom_cc_probe(pdev, &mss_sc7180_desc); + if (ret < 0) + goto destroy_pm_clk; + + return 0; + +destroy_pm_clk: + pm_clk_destroy(&pdev->dev); + +disable_pm_runtime: + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int mss_sc7180_remove(struct platform_device *pdev) +{ + pm_clk_destroy(&pdev->dev); + pm_runtime_disable(&pdev->dev); + + return 0; +} + +static const struct dev_pm_ops mss_sc7180_pm_ops = { + set_runtime_pm_ops(pm_clk_suspend, pm_clk_resume, null) +}; + +static const struct of_device_id mss_sc7180_match_table[] = { + { .compatible = "qcom,sc7180-mss" }, + { } +}; +module_device_table(of, mss_sc7180_match_table); + +static struct platform_driver mss_sc7180_driver = { + .probe = mss_sc7180_probe, + .remove = mss_sc7180_remove, + .driver = { + .name = "sc7180-mss", + .of_match_table = mss_sc7180_match_table, + .pm = &mss_sc7180_pm_ops, + }, +}; + +static int __init mss_sc7180_init(void) +{ + return platform_driver_register(&mss_sc7180_driver); +} +subsys_initcall(mss_sc7180_init); + +static void __exit mss_sc7180_exit(void) +{ + platform_driver_unregister(&mss_sc7180_driver); +} +module_exit(mss_sc7180_exit); + +module_description("qti mss sc7180 driver"); +module_license("gpl v2");
|
Clock
|
8def929c4097d9014c37d6a3649b21d38ad607d7
|
taniya das sibi sankar sibis codeaurora org
|
drivers
|
clk
|
qcom
|
clk: qcom: clk-alpha-pll: add support for controlling lucid plls
|
add programming sequence support for managing the lucid plls.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for controlling lucid plls
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qcom', 'clk-alpha-pll']
|
['h', 'c']
| 2
| 205
| 0
|
--- diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c +#define pll_test_ctl_u1(p) ((p)->offset + (p)->regs[pll_off_test_ctl_u1]) + [clk_alpha_pll_type_lucid] = { + [pll_off_l_val] = 0x04, + [pll_off_cal_l_val] = 0x08, + [pll_off_user_ctl] = 0x0c, + [pll_off_user_ctl_u] = 0x10, + [pll_off_user_ctl_u1] = 0x14, + [pll_off_config_ctl] = 0x18, + [pll_off_config_ctl_u] = 0x1c, + [pll_off_config_ctl_u1] = 0x20, + [pll_off_test_ctl] = 0x24, + [pll_off_test_ctl_u] = 0x28, + [pll_off_test_ctl_u1] = 0x2c, + [pll_off_status] = 0x30, + [pll_off_opmode] = 0x38, + [pll_off_alpha_val] = 0x40, + }, +/* lucid pll specific settings and offsets */ +#define lucid_pll_cal_val 0x44 +#define lucid_pcal_done bit(26) + + +/** + * clk_lucid_pll_configure - configure the lucid pll + * + * @pll: clk alpha pll + * @regmap: register map + * @config: configuration to apply for pll + */ +void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) +{ + if (config->l) + regmap_write(regmap, pll_l_val(pll), config->l); + + regmap_write(regmap, pll_cal_l_val(pll), lucid_pll_cal_val); + + if (config->alpha) + regmap_write(regmap, pll_alpha_val(pll), config->alpha); + + if (config->config_ctl_val) + regmap_write(regmap, pll_config_ctl(pll), + config->config_ctl_val); + + if (config->config_ctl_hi_val) + regmap_write(regmap, pll_config_ctl_u(pll), + config->config_ctl_hi_val); + + if (config->config_ctl_hi1_val) + regmap_write(regmap, pll_config_ctl_u1(pll), + config->config_ctl_hi1_val); + + if (config->user_ctl_val) + regmap_write(regmap, pll_user_ctl(pll), + config->user_ctl_val); + + if (config->user_ctl_hi_val) + regmap_write(regmap, pll_user_ctl_u(pll), + config->user_ctl_hi_val); + + if (config->user_ctl_hi1_val) + regmap_write(regmap, pll_user_ctl_u1(pll), + config->user_ctl_hi1_val); + + if (config->test_ctl_val) + regmap_write(regmap, pll_test_ctl(pll), + config->test_ctl_val); + + if (config->test_ctl_hi_val) + regmap_write(regmap, pll_test_ctl_u(pll), + config->test_ctl_hi_val); + + if (config->test_ctl_hi1_val) + regmap_write(regmap, pll_test_ctl_u1(pll), + config->test_ctl_hi1_val); + + regmap_update_bits(regmap, pll_mode(pll), pll_update_bypass, + pll_update_bypass); + + /* disable pll output */ + regmap_update_bits(regmap, pll_mode(pll), pll_outctrl, 0); + + /* set operation mode to off */ + regmap_write(regmap, pll_opmode(pll), pll_standby); + + /* place the pll in standby mode */ + regmap_update_bits(regmap, pll_mode(pll), pll_reset_n, pll_reset_n); +} +export_symbol_gpl(clk_lucid_pll_configure); + +/* + * the lucid pll requires a power-on self-calibration which happens when the + * pll comes out of reset. calibrate in case it is not completed. + */ +static int alpha_pll_lucid_prepare(struct clk_hw *hw) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + u32 regval; + int ret; + + /* return early if calibration is not needed. */ + regmap_read(pll->clkr.regmap, pll_status(pll), ®val); + if (regval & lucid_pcal_done) + return 0; + + /* on/off to calibrate */ + ret = clk_trion_pll_enable(hw); + if (!ret) + clk_trion_pll_disable(hw); + + return ret; +} + +static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long prate) +{ + struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); + unsigned long rrate; + u32 regval, l, alpha_width = pll_alpha_width(pll); + u64 a; + int ret; + + rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width); + + /* + * due to a limited number of bits for fractional rate programming, the + * rounded up rate could be marginally higher than the requested rate. + */ + if (rrate > (rate + pll_rate_margin) || rrate < rate) { + pr_err("call set rate on the pll with rounded rates! "); + return -einval; + } + + regmap_write(pll->clkr.regmap, pll_l_val(pll), l); + regmap_write(pll->clkr.regmap, pll_alpha_val(pll), a); + + /* latch the pll input */ + ret = regmap_update_bits(pll->clkr.regmap, pll_mode(pll), + pll_update, pll_update); + if (ret) + return ret; + + /* wait for 2 reference cycles before checking the ack bit. */ + udelay(1); + regmap_read(pll->clkr.regmap, pll_mode(pll), ®val); + if (!(regval & alpha_pll_ack_latch)) { + pr_err("lucid pll latch failed. output may be unstable! "); + return -einval; + } + + /* return the latch input to 0 */ + ret = regmap_update_bits(pll->clkr.regmap, pll_mode(pll), + pll_update, 0); + if (ret) + return ret; + + if (clk_hw_is_enabled(hw)) { + ret = wait_for_pll_enable_lock(pll); + if (ret) + return ret; + } + + /* wait for pll output to stabilize */ + udelay(100); + return 0; +} + +const struct clk_ops clk_alpha_pll_lucid_ops = { + .prepare = alpha_pll_lucid_prepare, + .enable = clk_trion_pll_enable, + .disable = clk_trion_pll_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, + .set_rate = alpha_pll_lucid_set_rate, +}; +export_symbol_gpl(clk_alpha_pll_lucid_ops); + +const struct clk_ops clk_alpha_pll_fixed_lucid_ops = { + .enable = clk_trion_pll_enable, + .disable = clk_trion_pll_disable, + .is_enabled = clk_trion_pll_is_enabled, + .recalc_rate = clk_trion_pll_recalc_rate, + .round_rate = clk_alpha_pll_round_rate, +}; +export_symbol_gpl(clk_alpha_pll_fixed_lucid_ops); + +const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = { + .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate, + .round_rate = clk_alpha_pll_postdiv_fabia_round_rate, + .set_rate = clk_alpha_pll_postdiv_fabia_set_rate, +}; +export_symbol_gpl(clk_alpha_pll_postdiv_lucid_ops); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h + clk_alpha_pll_type_lucid, + pll_off_test_ctl_u1, + u32 config_ctl_hi1_val; + u32 user_ctl_hi1_val; + u32 test_ctl_hi1_val; +extern const struct clk_ops clk_alpha_pll_lucid_ops; +extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops; +extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops; + +void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config); +
|
Clock
|
59128c20a6a98ee454e5ad23fe28dc84d23b6234
|
taniya das bryan o donoghue bryan odonoghue linaro org bryan o donoghue bryan odonoghue linaro org
|
drivers
|
clk
|
qcom
|
clk: qcom: gcc: add global clock controller driver for sm8250
|
add the clocks supported in global clock controller, which clock the peripherals like blsps, sdcc, usb, mdss etc. register all the clocks to the clock framework for the clients to be able to request for them.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add global clock controller driver for sm8250
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qcom', 'gcc']
|
['kconfig', 'c', 'makefile']
| 3
| 3,698
| 0
|
--- diff --git a/drivers/clk/qcom/kconfig b/drivers/clk/qcom/kconfig --- a/drivers/clk/qcom/kconfig +++ b/drivers/clk/qcom/kconfig +config sm_gcc_8250 + tristate "sm8250 global clock controller" + help + support for the global clock controller on sm8250 devices. + say y if you want to use peripheral devices such as uart, + spi, i2c, usb, sd/ufs, pcie etc. + diff --git a/drivers/clk/qcom/makefile b/drivers/clk/qcom/makefile --- a/drivers/clk/qcom/makefile +++ b/drivers/clk/qcom/makefile +obj-$(config_sm_gcc_8250) += gcc-sm8250.o diff --git a/drivers/clk/qcom/gcc-sm8250.c b/drivers/clk/qcom/gcc-sm8250.c --- /dev/null +++ b/drivers/clk/qcom/gcc-sm8250.c +// spdx-license-identifier: gpl-2.0-only +/* + * copyright (c) 2020, the linux foundation. all rights reserved. + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of.h> +#include <linux/regmap.h> + +#include <dt-bindings/clock/qcom,gcc-sm8250.h> + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +enum { + p_bi_tcxo, + p_aud_ref_clk, + p_core_bi_pll_test_se, + p_gpll0_out_even, + p_gpll0_out_main, + p_gpll4_out_main, + p_gpll9_out_main, + p_sleep_clk, +}; + +static struct clk_alpha_pll gpll0 = { + .offset = 0x0, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_lucid], + .clkr = { + .enable_reg = 0x52018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct clk_div_table post_div_table_gpll0_out_even[] = { + { 0x1, 2 }, + { } +}; + +static struct clk_alpha_pll_postdiv gpll0_out_even = { + .offset = 0x0, + .post_div_shift = 8, + .post_div_table = post_div_table_gpll0_out_even, + .num_post_div = array_size(post_div_table_gpll0_out_even), + .width = 4, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_lucid], + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll0_out_even", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpll0.clkr.hw, + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_lucid_ops, + }, +}; + +static struct clk_alpha_pll gpll4 = { + .offset = 0x76000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_lucid], + .clkr = { + .enable_reg = 0x52018, + .enable_mask = bit(4), + .hw.init = &(struct clk_init_data){ + .name = "gpll4", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll9 = { + .offset = 0x1c000, + .regs = clk_alpha_pll_regs[clk_alpha_pll_type_lucid], + .clkr = { + .enable_reg = 0x52018, + .enable_mask = bit(9), + .hw.init = &(struct clk_init_data){ + .name = "gpll9", + .parent_data = &(const struct clk_parent_data){ + .fw_name = "bi_tcxo", + }, + .num_parents = 1, + .ops = &clk_alpha_pll_fixed_lucid_ops, + }, + }, +}; + +static const struct parent_map gcc_parent_map_0[] = { + { p_bi_tcxo, 0 }, + { p_gpll0_out_main, 1 }, + { p_gpll0_out_even, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_0[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct clk_parent_data gcc_parent_data_0_ao[] = { + { .fw_name = "bi_tcxo_ao" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_1[] = { + { p_bi_tcxo, 0 }, + { p_gpll0_out_main, 1 }, + { p_sleep_clk, 5 }, + { p_gpll0_out_even, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "sleep_clk" }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_2[] = { + { p_bi_tcxo, 0 }, + { p_sleep_clk, 5 }, +}; + +static const struct clk_parent_data gcc_parent_data_2[] = { + { .fw_name = "bi_tcxo" }, + { .fw_name = "sleep_clk" }, +}; + +static const struct parent_map gcc_parent_map_3[] = { + { p_bi_tcxo, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_3[] = { + { .fw_name = "bi_tcxo" }, +}; + +static const struct parent_map gcc_parent_map_4[] = { + { p_bi_tcxo, 0 }, + { p_gpll0_out_main, 1 }, + { p_gpll9_out_main, 2 }, + { p_gpll4_out_main, 5 }, + { p_gpll0_out_even, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_4[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .hw = &gpll9.clkr.hw }, + { .hw = &gpll4.clkr.hw }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct parent_map gcc_parent_map_5[] = { + { p_bi_tcxo, 0 }, + { p_gpll0_out_main, 1 }, + { p_aud_ref_clk, 2 }, + { p_gpll0_out_even, 6 }, +}; + +static const struct clk_parent_data gcc_parent_data_5[] = { + { .fw_name = "bi_tcxo" }, + { .hw = &gpll0.clkr.hw }, + { .fw_name = "aud_ref_clk" }, + { .hw = &gpll0_out_even.clkr.hw }, +}; + +static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { + .cmd_rcgr = 0x48010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk_src", + .parent_data = gcc_parent_data_0_ao, + .num_parents = 3, + .flags = clk_set_rate_parent, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + f(25000000, p_gpll0_out_even, 12, 0, 0), + f(50000000, p_gpll0_out_even, 6, 0, 0), + f(100000000, p_gpll0_out_main, 6, 0, 0), + f(200000000, p_gpll0_out_main, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_gp1_clk_src = { + .cmd_rcgr = 0x64004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp2_clk_src = { + .cmd_rcgr = 0x65004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_gp3_clk_src = { + .cmd_rcgr = 0x66004, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_1, + .freq_tbl = ftbl_gcc_gp1_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk_src", + .parent_data = gcc_parent_data_1, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_0_aux_clk_src[] = { + f(9600000, p_bi_tcxo, 2, 0, 0), + f(19200000, p_bi_tcxo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_0_aux_clk_src = { + .cmd_rcgr = 0x6b038, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_aux_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_1_aux_clk_src = { + .cmd_rcgr = 0x8d038, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_aux_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_pcie_2_aux_clk_src = { + .cmd_rcgr = 0x6038, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_aux_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pcie_phy_refgen_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + f(100000000, p_gpll0_out_main, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { + .cmd_rcgr = 0x6f014, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_phy_refgen_clk_src", + .parent_data = gcc_parent_data_0_ao, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_pdm2_clk_src[] = { + f(9600000, p_bi_tcxo, 2, 0, 0), + f(19200000, p_bi_tcxo, 1, 0, 0), + f(60000000, p_gpll0_out_main, 10, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_pdm2_clk_src = { + .cmd_rcgr = 0x33010, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_pdm2_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = { + f(7372800, p_gpll0_out_even, 1, 384, 15625), + f(14745600, p_gpll0_out_even, 1, 768, 15625), + f(19200000, p_bi_tcxo, 1, 0, 0), + f(29491200, p_gpll0_out_even, 1, 1536, 15625), + f(32000000, p_gpll0_out_even, 1, 8, 75), + f(48000000, p_gpll0_out_even, 1, 4, 25), + f(50000000, p_gpll0_out_even, 6, 0, 0), + f(64000000, p_gpll0_out_even, 1, 16, 75), + f(75000000, p_gpll0_out_even, 4, 0, 0), + f(80000000, p_gpll0_out_even, 1, 4, 15), + f(96000000, p_gpll0_out_even, 1, 8, 25), + f(100000000, p_gpll0_out_main, 6, 0, 0), + f(102400000, p_gpll0_out_even, 1, 128, 375), + f(112000000, p_gpll0_out_even, 1, 28, 75), + f(117964800, p_gpll0_out_even, 1, 6144, 15625), + f(120000000, p_gpll0_out_even, 2.5, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = { + .name = "gcc_qupv3_wrap0_s0_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = { + .cmd_rcgr = 0x17010, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = { + .name = "gcc_qupv3_wrap0_s1_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = { + .cmd_rcgr = 0x17140, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s1_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s2_clk_src[] = { + f(7372800, p_gpll0_out_even, 1, 384, 15625), + f(14745600, p_gpll0_out_even, 1, 768, 15625), + f(19200000, p_bi_tcxo, 1, 0, 0), + f(29491200, p_gpll0_out_even, 1, 1536, 15625), + f(32000000, p_gpll0_out_even, 1, 8, 75), + f(48000000, p_gpll0_out_even, 1, 4, 25), + f(50000000, p_gpll0_out_even, 6, 0, 0), + f(64000000, p_gpll0_out_even, 1, 16, 75), + f(75000000, p_gpll0_out_even, 4, 0, 0), + f(80000000, p_gpll0_out_even, 1, 4, 15), + f(96000000, p_gpll0_out_even, 1, 8, 25), + f(100000000, p_gpll0_out_main, 6, 0, 0), + { } +}; + +static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = { + .name = "gcc_qupv3_wrap0_s2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = { + .cmd_rcgr = 0x17270, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = { + .name = "gcc_qupv3_wrap0_s3_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = { + .cmd_rcgr = 0x173a0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = { + .name = "gcc_qupv3_wrap0_s4_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = { + .cmd_rcgr = 0x174d0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = { + .name = "gcc_qupv3_wrap0_s5_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = { + .cmd_rcgr = 0x17600, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = { + .name = "gcc_qupv3_wrap0_s6_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = { + .cmd_rcgr = 0x17730, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s6_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = { + .name = "gcc_qupv3_wrap0_s7_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = { + .cmd_rcgr = 0x17860, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap0_s7_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = { + .name = "gcc_qupv3_wrap1_s0_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = { + .cmd_rcgr = 0x18010, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = { + .name = "gcc_qupv3_wrap1_s1_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = { + .cmd_rcgr = 0x18140, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = { + .name = "gcc_qupv3_wrap1_s2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = { + .cmd_rcgr = 0x18270, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = { + .name = "gcc_qupv3_wrap1_s3_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = { + .cmd_rcgr = 0x183a0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = { + .name = "gcc_qupv3_wrap1_s4_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = { + .cmd_rcgr = 0x184d0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = { + .name = "gcc_qupv3_wrap1_s5_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = { + .cmd_rcgr = 0x18600, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap1_s5_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = { + .name = "gcc_qupv3_wrap2_s0_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = { + .cmd_rcgr = 0x1e010, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s0_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap2_s0_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = { + .name = "gcc_qupv3_wrap2_s1_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = { + .cmd_rcgr = 0x1e140, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap2_s1_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = { + .name = "gcc_qupv3_wrap2_s2_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = { + .cmd_rcgr = 0x1e270, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap2_s2_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = { + .name = "gcc_qupv3_wrap2_s3_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = { + .cmd_rcgr = 0x1e3a0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap2_s3_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = { + .name = "gcc_qupv3_wrap2_s4_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = { + .cmd_rcgr = 0x1e4d0, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap2_s4_clk_src_init, +}; + +static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = { + .name = "gcc_qupv3_wrap2_s5_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, +}; + +static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = { + .cmd_rcgr = 0x1e600, + .mnd_width = 16, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_qupv3_wrap0_s2_clk_src, + .clkr.hw.init = &gcc_qupv3_wrap2_s5_clk_src_init, +}; + +static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = { + f(400000, p_bi_tcxo, 12, 1, 4), + f(19200000, p_bi_tcxo, 1, 0, 0), + f(25000000, p_gpll0_out_even, 12, 0, 0), + f(50000000, p_gpll0_out_even, 6, 0, 0), + f(100000000, p_gpll0_out_main, 6, 0, 0), + f(202000000, p_gpll9_out_main, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { + .cmd_rcgr = 0x1400c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_4, + .freq_tbl = ftbl_gcc_sdcc2_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk_src", + .parent_data = gcc_parent_data_4, + .num_parents = 5, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_sdcc4_apps_clk_src[] = { + f(400000, p_bi_tcxo, 12, 1, 4), + f(19200000, p_bi_tcxo, 1, 0, 0), + f(25000000, p_gpll0_out_even, 12, 0, 0), + f(50000000, p_gpll0_out_even, 6, 0, 0), + f(100000000, p_gpll0_out_main, 6, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { + .cmd_rcgr = 0x1600c, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_sdcc4_apps_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_apps_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_tsif_ref_clk_src[] = { + f(105495, p_bi_tcxo, 2, 1, 91), + { } +}; + +static struct clk_rcg2 gcc_tsif_ref_clk_src = { + .cmd_rcgr = 0x36010, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_5, + .freq_tbl = ftbl_gcc_tsif_ref_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ref_clk_src", + .parent_data = gcc_parent_data_5, + .num_parents = 4, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_card_axi_clk_src[] = { + f(25000000, p_gpll0_out_even, 12, 0, 0), + f(50000000, p_gpll0_out_even, 6, 0, 0), + f(100000000, p_gpll0_out_main, 6, 0, 0), + f(200000000, p_gpll0_out_main, 3, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_card_axi_clk_src = { + .cmd_rcgr = 0x75024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_axi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_card_ice_core_clk_src[] = { + f(37500000, p_gpll0_out_even, 8, 0, 0), + f(75000000, p_gpll0_out_even, 4, 0, 0), + f(150000000, p_gpll0_out_main, 4, 0, 0), + f(300000000, p_gpll0_out_main, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = { + .cmd_rcgr = 0x7506c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_card_phy_aux_clk_src[] = { + f(19200000, p_bi_tcxo, 1, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = { + .cmd_rcgr = 0x750a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_phy_aux_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = 1, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_card_unipro_core_clk_src[] = { + f(37500000, p_gpll0_out_even, 8, 0, 0), + f(75000000, p_gpll0_out_main, 8, 0, 0), + f(150000000, p_gpll0_out_main, 4, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = { + .cmd_rcgr = 0x75084, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_unipro_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_unipro_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = { + f(25000000, p_gpll0_out_even, 12, 0, 0), + f(37500000, p_gpll0_out_even, 8, 0, 0), + f(75000000, p_gpll0_out_even, 4, 0, 0), + f(150000000, p_gpll0_out_main, 4, 0, 0), + f(300000000, p_gpll0_out_main, 2, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = { + .cmd_rcgr = 0x77024, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = { + .cmd_rcgr = 0x7706c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = { + .cmd_rcgr = 0x770a0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_3, + .freq_tbl = ftbl_gcc_pcie_0_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk_src", + .parent_data = gcc_parent_data_3, + .num_parents = 1, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = { + .cmd_rcgr = 0x77084, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_ice_core_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = { + f(33333333, p_gpll0_out_even, 9, 0, 0), + f(66666667, p_gpll0_out_even, 4.5, 0, 0), + f(133333333, p_gpll0_out_main, 4.5, 0, 0), + f(200000000, p_gpll0_out_main, 3, 0, 0), + f(240000000, p_gpll0_out_main, 2.5, 0, 0), + { } +}; + +static struct clk_rcg2 gcc_usb30_prim_master_clk_src = { + .cmd_rcgr = 0xf020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = { + .cmd_rcgr = 0xf038, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_sec_master_clk_src = { + .cmd_rcgr = 0x10020, + .mnd_width = 8, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_usb30_prim_master_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_master_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = { + .cmd_rcgr = 0x10038, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_0, + .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_mock_utmi_clk_src", + .parent_data = gcc_parent_data_0, + .num_parents = 3, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = { + .cmd_rcgr = 0xf064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = { + .cmd_rcgr = 0x10064, + .mnd_width = 0, + .hid_width = 5, + .parent_map = gcc_parent_map_2, + .freq_tbl = ftbl_gcc_ufs_card_phy_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_phy_aux_clk_src", + .parent_data = gcc_parent_data_2, + .num_parents = 2, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div gcc_cpuss_ahb_postdiv_clk_src = { + .reg = 0x48028, + .shift = 0, + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gcc_cpuss_ahb_postdiv_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_cpuss_ahb_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_prim_mock_utmi_postdiv_clk_src = { + .reg = 0xf050, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gcc_usb30_prim_mock_utmi_postdiv_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_prim_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div gcc_usb30_sec_mock_utmi_postdiv_clk_src = { + .reg = 0x10050, + .shift = 0, + .width = 2, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gcc_usb30_sec_mock_utmi_postdiv_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_sec_mock_utmi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch gcc_aggre_noc_pcie_tbu_clk = { + .halt_reg = 0x9000c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x9000c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre_noc_pcie_tbu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_card_axi_clk = { + .halt_reg = 0x750cc, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x750cc, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x750cc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre_ufs_card_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_ufs_phy_axi_clk = { + .halt_reg = 0x770cc, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x770cc, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x770cc, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre_ufs_phy_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_prim_axi_clk = { + .halt_reg = 0xf080, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xf080, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre_usb3_prim_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_aggre_usb3_sec_axi_clk = { + .halt_reg = 0x10080, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x10080, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_aggre_usb3_sec_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_boot_rom_ahb_clk = { + .halt_reg = 0x38004, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x38004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_boot_rom_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk = { + .halt_reg = 0xb02c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xb02c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_sf_axi_clk = { + .halt_reg = 0xb030, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xb030, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_sf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_xo_clk = { + .halt_reg = 0xb040, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xb040, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_camera_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_prim_axi_clk = { + .halt_reg = 0xf07c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xf07c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_prim_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cfg_noc_usb3_sec_axi_clk = { + .halt_reg = 0x1007c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x1007c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cfg_noc_usb3_sec_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_ahb_clk = { + .halt_reg = 0x48000, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_ahb_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_cpuss_ahb_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_is_critical | clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_cpuss_rbcpr_clk = { + .halt_reg = 0x48004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x48004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_cpuss_rbcpr_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_gpu_axi_clk = { + .halt_reg = 0x71154, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x71154, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ddrss_gpu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ddrss_pcie_sf_tbu_clk = { + .halt_reg = 0x8d058, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x8d058, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ddrss_pcie_sf_tbu_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_hf_axi_clk = { + .halt_reg = 0xb034, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xb034, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_hf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_sf_axi_clk = { + .halt_reg = 0xb038, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xb038, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_sf_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_disp_xo_clk = { + .halt_reg = 0xb044, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xb044, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_disp_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp1_clk = { + .halt_reg = 0x64000, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x64000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp1_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_gp1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp2_clk = { + .halt_reg = 0x65000, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x65000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp2_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_gp2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gp3_clk = { + .halt_reg = 0x66000, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x66000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gp3_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_gp3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_iref_en = { + .halt_reg = 0x8c014, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x8c014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_iref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_memnoc_gfx_clk = { + .halt_reg = 0x7100c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x7100c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_memnoc_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_snoc_dvm_gfx_clk = { + .halt_reg = 0x71018, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x71018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_snoc_dvm_gfx_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_axi_clk = { + .halt_reg = 0x4d008, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x4d008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_axi_clk = { + .halt_reg = 0x73008, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x73008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_bwmon_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_bwmon_cfg_ahb_clk = { + .halt_reg = 0x73004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x73004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_bwmon_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_cfg_ahb_clk = { + .halt_reg = 0x4d004, + .halt_check = branch_halt, + .hwcg_reg = 0x4d004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x4d004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_dma_clk = { + .halt_reg = 0x4d00c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x4d00c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_dma_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_clk_src = { + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(18), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_gpll0_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpll0.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src = { + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(19), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_gpll0_div_clk_src", + .parent_data = &(const struct clk_parent_data){ + .hw = &gpll0_out_even.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie0_phy_refgen_clk = { + .halt_reg = 0x6f02c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x6f02c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie0_phy_refgen_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie1_phy_refgen_clk = { + .halt_reg = 0x6f030, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x6f030, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie1_phy_refgen_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie2_phy_refgen_clk = { + .halt_reg = 0x6f034, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x6f034, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie2_phy_refgen_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_phy_refgen_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_aux_clk = { + .halt_reg = 0x6b028, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { + .halt_reg = 0x6b024, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x6b024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_mstr_axi_clk = { + .halt_reg = 0x6b01c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_pipe_clk = { + .halt_reg = 0x6b02c, + .halt_check = branch_halt_skip, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_axi_clk = { + .halt_reg = 0x6b014, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x6b014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { + .halt_reg = 0x6b010, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_0_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_aux_clk = { + .halt_reg = 0x8d028, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(29), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_1_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { + .halt_reg = 0x8d024, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x8d024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(28), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_mstr_axi_clk = { + .halt_reg = 0x8d01c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_pipe_clk = { + .halt_reg = 0x8d02c, + .halt_check = branch_halt_skip, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(30), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_axi_clk = { + .halt_reg = 0x8d014, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x8d014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_1_slv_q2a_axi_clk = { + .halt_reg = 0x8d010, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_1_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_aux_clk = { + .halt_reg = 0x6028, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_2_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { + .halt_reg = 0x6024, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x6024, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_cfg_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_mstr_axi_clk = { + .halt_reg = 0x601c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(12), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_mstr_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_pipe_clk = { + .halt_reg = 0x602c, + .halt_check = branch_halt_skip, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_axi_clk = { + .halt_reg = 0x6014, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x6014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(11), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_slv_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_2_slv_q2a_axi_clk = { + .halt_reg = 0x6010, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_2_slv_q2a_axi_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_mdm_clkref_en = { + .halt_reg = 0x8c00c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x8c00c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_mdm_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_phy_aux_clk = { + .halt_reg = 0x6f004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x6f004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_phy_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pcie_0_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_wifi_clkref_en = { + .halt_reg = 0x8c004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x8c004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_wifi_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pcie_wigig_clkref_en = { + .halt_reg = 0x8c008, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x8c008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pcie_wigig_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm2_clk = { + .halt_reg = 0x3300c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x3300c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm2_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_pdm2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_ahb_clk = { + .halt_reg = 0x33004, + .halt_check = branch_halt, + .hwcg_reg = 0x33004, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x33004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_pdm_xo4_clk = { + .halt_reg = 0x33008, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x33008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_pdm_xo4_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_prng_ahb_clk = { + .halt_reg = 0x34004, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52000, + .enable_mask = bit(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_prng_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_nrt_ahb_clk = { + .halt_reg = 0xb018, + .halt_check = branch_halt_voted, + .hwcg_reg = 0xb018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_nrt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_camera_rt_ahb_clk = { + .halt_reg = 0xb01c, + .halt_check = branch_halt_voted, + .hwcg_reg = 0xb01c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb01c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_camera_rt_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_disp_ahb_clk = { + .halt_reg = 0xb020, + .halt_check = branch_halt_voted, + .hwcg_reg = 0xb020, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_disp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_cvp_ahb_clk = { + .halt_reg = 0xb010, + .halt_check = branch_halt_voted, + .hwcg_reg = 0xb010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_video_cvp_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qmip_video_vcodec_ahb_clk = { + .halt_reg = 0xb014, + .halt_check = branch_halt_voted, + .hwcg_reg = 0xb014, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0xb014, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qmip_video_vcodec_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_2x_clk = { + .halt_reg = 0x23008, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(9), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_core_clk = { + .halt_reg = 0x23000, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s0_clk = { + .halt_reg = 0x1700c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(10), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s1_clk = { + .halt_reg = 0x1713c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(11), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s1_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s2_clk = { + .halt_reg = 0x1726c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(12), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s2_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s3_clk = { + .halt_reg = 0x1739c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(13), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s3_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s4_clk = { + .halt_reg = 0x174cc, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(14), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s4_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s5_clk = { + .halt_reg = 0x175fc, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s5_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s6_clk = { + .halt_reg = 0x1772c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s6_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s6_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap0_s7_clk = { + .halt_reg = 0x1785c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(17), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap0_s7_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap0_s7_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_2x_clk = { + .halt_reg = 0x23140, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(18), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_core_clk = { + .halt_reg = 0x23138, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(19), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s0_clk = { + .halt_reg = 0x1800c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(22), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap1_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s1_clk = { + .halt_reg = 0x1813c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(23), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s1_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap1_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s2_clk = { + .halt_reg = 0x1826c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(24), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s2_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap1_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s3_clk = { + .halt_reg = 0x1839c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(25), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s3_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap1_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s4_clk = { + .halt_reg = 0x184cc, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(26), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s4_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap1_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap1_s5_clk = { + .halt_reg = 0x185fc, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(27), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap1_s5_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap1_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_2x_clk = { + .halt_reg = 0x23278, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(3), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_core_2x_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_core_clk = { + .halt_reg = 0x23270, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_core_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s0_clk = { + .halt_reg = 0x1e00c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(4), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s0_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap2_s0_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s1_clk = { + .halt_reg = 0x1e13c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(5), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s1_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap2_s1_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s2_clk = { + .halt_reg = 0x1e26c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(6), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s2_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap2_s2_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s3_clk = { + .halt_reg = 0x1e39c, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s3_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap2_s3_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s4_clk = { + .halt_reg = 0x1e4cc, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(8), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s4_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap2_s4_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap2_s5_clk = { + .halt_reg = 0x1e5fc, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(9), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap2_s5_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_qupv3_wrap2_s5_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_m_ahb_clk = { + .halt_reg = 0x17004, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(6), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_0_s_ahb_clk = { + .halt_reg = 0x17008, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x17008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(7), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_0_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_m_ahb_clk = { + .halt_reg = 0x18004, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(20), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_1_s_ahb_clk = { + .halt_reg = 0x18008, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x18008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52008, + .enable_mask = bit(21), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_1_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_m_ahb_clk = { + .halt_reg = 0x1e004, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(2), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_2_m_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_qupv3_wrap_2_s_ahb_clk = { + .halt_reg = 0x1e008, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x1e008, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x52010, + .enable_mask = bit(1), + .hw.init = &(struct clk_init_data){ + .name = "gcc_qupv3_wrap_2_s_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_ahb_clk = { + .halt_reg = 0x14008, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x14008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc2_apps_clk = { + .halt_reg = 0x14004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x14004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc2_apps_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_sdcc2_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_ahb_clk = { + .halt_reg = 0x16008, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x16008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_sdcc4_apps_clk = { + .halt_reg = 0x16004, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x16004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_sdcc4_apps_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_sdcc4_apps_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tsif_ahb_clk = { + .halt_reg = 0x36004, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x36004, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tsif_inactivity_timers_clk = { + .halt_reg = 0x3600c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x3600c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_inactivity_timers_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_tsif_ref_clk = { + .halt_reg = 0x36008, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x36008, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_tsif_ref_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_tsif_ref_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_1x_clkref_en = { + .halt_reg = 0x8c000, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x8c000, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_1x_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_ahb_clk = { + .halt_reg = 0x75018, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x75018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x75018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_axi_clk = { + .halt_reg = 0x75010, + .halt_check = branch_halt, + .hwcg_reg = 0x75010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x75010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_card_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_ice_core_clk = { + .halt_reg = 0x75064, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x75064, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x75064, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_ice_core_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_card_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_phy_aux_clk = { + .halt_reg = 0x7509c, + .halt_check = branch_halt, + .hwcg_reg = 0x7509c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7509c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_phy_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_card_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { + .halt_reg = 0x75020, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x75020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { + .halt_reg = 0x750b8, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x750b8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { + .halt_reg = 0x7501c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x7501c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_unipro_core_clk = { + .halt_reg = 0x7505c, + .halt_check = branch_halt, + .hwcg_reg = 0x7505c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7505c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_card_unipro_core_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_card_unipro_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ahb_clk = { + .halt_reg = 0x77018, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x77018, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x77018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ahb_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_axi_clk = { + .halt_reg = 0x77010, + .halt_check = branch_halt, + .hwcg_reg = 0x77010, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x77010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_axi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_phy_axi_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_ice_core_clk = { + .halt_reg = 0x77064, + .halt_check = branch_halt_voted, + .hwcg_reg = 0x77064, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x77064, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_ice_core_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_phy_ice_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_phy_aux_clk = { + .halt_reg = 0x7709c, + .halt_check = branch_halt, + .hwcg_reg = 0x7709c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7709c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_phy_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_phy_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { + .halt_reg = 0x77020, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x77020, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { + .halt_reg = 0x770b8, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x770b8, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_rx_symbol_1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { + .halt_reg = 0x7701c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x7701c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_tx_symbol_0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_unipro_core_clk = { + .halt_reg = 0x7705c, + .halt_check = branch_halt, + .hwcg_reg = 0x7705c, + .hwcg_bit = 1, + .clkr = { + .enable_reg = 0x7705c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_ufs_phy_unipro_core_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_ufs_phy_unipro_core_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_master_clk = { + .halt_reg = 0xf010, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xf010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_master_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_prim_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_mock_utmi_clk = { + .halt_reg = 0xf01c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xf01c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_mock_utmi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_prim_sleep_clk = { + .halt_reg = 0xf018, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xf018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_prim_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_master_clk = { + .halt_reg = 0x10010, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0x10010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_master_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb30_sec_master_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_mock_utmi_clk = { + .halt_reg = 0x1001c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x1001c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_mock_utmi_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = + &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb30_sec_sleep_clk = { + .halt_reg = 0x10018, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x10018, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb30_sec_sleep_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_aux_clk = { + .halt_reg = 0xf054, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xf054, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { + .halt_reg = 0xf058, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xf058, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_com_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb3_prim_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_reg = 0xf05c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0xf05c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_prim_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_clkref_en = { + .halt_reg = 0x8c010, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x8c010, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_clkref_en", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_aux_clk = { + .halt_reg = 0x10054, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x10054, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_phy_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { + .halt_reg = 0x10058, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0x10058, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_phy_com_aux_clk", + .parent_data = &(const struct clk_parent_data){ + .hw = &gcc_usb3_sec_phy_aux_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = clk_set_rate_parent, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { + .halt_reg = 0x1005c, + .halt_check = branch_halt_delay, + .clkr = { + .enable_reg = 0x1005c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_usb3_sec_phy_pipe_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi0_clk = { + .halt_reg = 0xb024, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xb024, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_axi0_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_axi1_clk = { + .halt_reg = 0xb028, + .halt_check = branch_halt_voted, + .clkr = { + .enable_reg = 0xb028, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_axi1_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_video_xo_clk = { + .halt_reg = 0xb03c, + .halt_check = branch_halt, + .clkr = { + .enable_reg = 0xb03c, + .enable_mask = bit(0), + .hw.init = &(struct clk_init_data){ + .name = "gcc_video_xo_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct gdsc pcie_0_gdsc = { + .gdscr = 0x6b004, + .pd = { + .name = "pcie_0_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc pcie_1_gdsc = { + .gdscr = 0x8d004, + .pd = { + .name = "pcie_1_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc pcie_2_gdsc = { + .gdscr = 0x6004, + .pd = { + .name = "pcie_2_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc ufs_card_gdsc = { + .gdscr = 0x75004, + .pd = { + .name = "ufs_card_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc ufs_phy_gdsc = { + .gdscr = 0x77004, + .pd = { + .name = "ufs_phy_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc usb30_prim_gdsc = { + .gdscr = 0xf004, + .pd = { + .name = "usb30_prim_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc usb30_sec_gdsc = { + .gdscr = 0x10004, + .pd = { + .name = "usb30_sec_gdsc", + }, + .pwrsts = pwrsts_off_on, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc = { + .gdscr = 0x7d050, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc", + }, + .pwrsts = pwrsts_off_on, + .flags = votable, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc = { + .gdscr = 0x7d058, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc", + }, + .pwrsts = pwrsts_off_on, + .flags = votable, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc = { + .gdscr = 0x7d054, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc", + }, + .pwrsts = pwrsts_off_on, + .flags = votable, +}; + +static struct gdsc hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc = { + .gdscr = 0x7d06c, + .pd = { + .name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc", + }, + .pwrsts = pwrsts_off_on, + .flags = votable, +}; + +static struct clk_regmap *gcc_sm8250_clocks[] = { + [gcc_aggre_noc_pcie_tbu_clk] = &gcc_aggre_noc_pcie_tbu_clk.clkr, + [gcc_aggre_ufs_card_axi_clk] = &gcc_aggre_ufs_card_axi_clk.clkr, + [gcc_aggre_ufs_phy_axi_clk] = &gcc_aggre_ufs_phy_axi_clk.clkr, + [gcc_aggre_usb3_prim_axi_clk] = &gcc_aggre_usb3_prim_axi_clk.clkr, + [gcc_aggre_usb3_sec_axi_clk] = &gcc_aggre_usb3_sec_axi_clk.clkr, + [gcc_boot_rom_ahb_clk] = &gcc_boot_rom_ahb_clk.clkr, + [gcc_camera_hf_axi_clk] = &gcc_camera_hf_axi_clk.clkr, + [gcc_camera_sf_axi_clk] = &gcc_camera_sf_axi_clk.clkr, + [gcc_camera_xo_clk] = &gcc_camera_xo_clk.clkr, + [gcc_cfg_noc_usb3_prim_axi_clk] = &gcc_cfg_noc_usb3_prim_axi_clk.clkr, + [gcc_cfg_noc_usb3_sec_axi_clk] = &gcc_cfg_noc_usb3_sec_axi_clk.clkr, + [gcc_cpuss_ahb_clk] = &gcc_cpuss_ahb_clk.clkr, + [gcc_cpuss_ahb_clk_src] = &gcc_cpuss_ahb_clk_src.clkr, + [gcc_cpuss_ahb_postdiv_clk_src] = &gcc_cpuss_ahb_postdiv_clk_src.clkr, + [gcc_cpuss_rbcpr_clk] = &gcc_cpuss_rbcpr_clk.clkr, + [gcc_ddrss_gpu_axi_clk] = &gcc_ddrss_gpu_axi_clk.clkr, + [gcc_ddrss_pcie_sf_tbu_clk] = &gcc_ddrss_pcie_sf_tbu_clk.clkr, + [gcc_disp_hf_axi_clk] = &gcc_disp_hf_axi_clk.clkr, + [gcc_disp_sf_axi_clk] = &gcc_disp_sf_axi_clk.clkr, + [gcc_disp_xo_clk] = &gcc_disp_xo_clk.clkr, + [gcc_gp1_clk] = &gcc_gp1_clk.clkr, + [gcc_gp1_clk_src] = &gcc_gp1_clk_src.clkr, + [gcc_gp2_clk] = &gcc_gp2_clk.clkr, + [gcc_gp2_clk_src] = &gcc_gp2_clk_src.clkr, + [gcc_gp3_clk] = &gcc_gp3_clk.clkr, + [gcc_gp3_clk_src] = &gcc_gp3_clk_src.clkr, + [gcc_gpu_gpll0_clk_src] = &gcc_gpu_gpll0_clk_src.clkr, + [gcc_gpu_gpll0_div_clk_src] = &gcc_gpu_gpll0_div_clk_src.clkr, + [gcc_gpu_iref_en] = &gcc_gpu_iref_en.clkr, + [gcc_gpu_memnoc_gfx_clk] = &gcc_gpu_memnoc_gfx_clk.clkr, + [gcc_gpu_snoc_dvm_gfx_clk] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, + [gcc_npu_axi_clk] = &gcc_npu_axi_clk.clkr, + [gcc_npu_bwmon_axi_clk] = &gcc_npu_bwmon_axi_clk.clkr, + [gcc_npu_bwmon_cfg_ahb_clk] = &gcc_npu_bwmon_cfg_ahb_clk.clkr, + [gcc_npu_cfg_ahb_clk] = &gcc_npu_cfg_ahb_clk.clkr, + [gcc_npu_dma_clk] = &gcc_npu_dma_clk.clkr, + [gcc_npu_gpll0_clk_src] = &gcc_npu_gpll0_clk_src.clkr, + [gcc_npu_gpll0_div_clk_src] = &gcc_npu_gpll0_div_clk_src.clkr, + [gcc_pcie0_phy_refgen_clk] = &gcc_pcie0_phy_refgen_clk.clkr, + [gcc_pcie1_phy_refgen_clk] = &gcc_pcie1_phy_refgen_clk.clkr, + [gcc_pcie2_phy_refgen_clk] = &gcc_pcie2_phy_refgen_clk.clkr, + [gcc_pcie_0_aux_clk] = &gcc_pcie_0_aux_clk.clkr, + [gcc_pcie_0_aux_clk_src] = &gcc_pcie_0_aux_clk_src.clkr, + [gcc_pcie_0_cfg_ahb_clk] = &gcc_pcie_0_cfg_ahb_clk.clkr, + [gcc_pcie_0_mstr_axi_clk] = &gcc_pcie_0_mstr_axi_clk.clkr, + [gcc_pcie_0_pipe_clk] = &gcc_pcie_0_pipe_clk.clkr, + [gcc_pcie_0_slv_axi_clk] = &gcc_pcie_0_slv_axi_clk.clkr, + [gcc_pcie_0_slv_q2a_axi_clk] = &gcc_pcie_0_slv_q2a_axi_clk.clkr, + [gcc_pcie_1_aux_clk] = &gcc_pcie_1_aux_clk.clkr, + [gcc_pcie_1_aux_clk_src] = &gcc_pcie_1_aux_clk_src.clkr, + [gcc_pcie_1_cfg_ahb_clk] = &gcc_pcie_1_cfg_ahb_clk.clkr, + [gcc_pcie_1_mstr_axi_clk] = &gcc_pcie_1_mstr_axi_clk.clkr, + [gcc_pcie_1_pipe_clk] = &gcc_pcie_1_pipe_clk.clkr, + [gcc_pcie_1_slv_axi_clk] = &gcc_pcie_1_slv_axi_clk.clkr, + [gcc_pcie_1_slv_q2a_axi_clk] = &gcc_pcie_1_slv_q2a_axi_clk.clkr, + [gcc_pcie_2_aux_clk] = &gcc_pcie_2_aux_clk.clkr, + [gcc_pcie_2_aux_clk_src] = &gcc_pcie_2_aux_clk_src.clkr, + [gcc_pcie_2_cfg_ahb_clk] = &gcc_pcie_2_cfg_ahb_clk.clkr, + [gcc_pcie_2_mstr_axi_clk] = &gcc_pcie_2_mstr_axi_clk.clkr, + [gcc_pcie_2_pipe_clk] = &gcc_pcie_2_pipe_clk.clkr, + [gcc_pcie_2_slv_axi_clk] = &gcc_pcie_2_slv_axi_clk.clkr, + [gcc_pcie_2_slv_q2a_axi_clk] = &gcc_pcie_2_slv_q2a_axi_clk.clkr, + [gcc_pcie_mdm_clkref_en] = &gcc_pcie_mdm_clkref_en.clkr, + [gcc_pcie_phy_aux_clk] = &gcc_pcie_phy_aux_clk.clkr, + [gcc_pcie_phy_refgen_clk_src] = &gcc_pcie_phy_refgen_clk_src.clkr, + [gcc_pcie_wifi_clkref_en] = &gcc_pcie_wifi_clkref_en.clkr, + [gcc_pcie_wigig_clkref_en] = &gcc_pcie_wigig_clkref_en.clkr, + [gcc_pdm2_clk] = &gcc_pdm2_clk.clkr, + [gcc_pdm2_clk_src] = &gcc_pdm2_clk_src.clkr, + [gcc_pdm_ahb_clk] = &gcc_pdm_ahb_clk.clkr, + [gcc_pdm_xo4_clk] = &gcc_pdm_xo4_clk.clkr, + [gcc_prng_ahb_clk] = &gcc_prng_ahb_clk.clkr, + [gcc_qmip_camera_nrt_ahb_clk] = &gcc_qmip_camera_nrt_ahb_clk.clkr, + [gcc_qmip_camera_rt_ahb_clk] = &gcc_qmip_camera_rt_ahb_clk.clkr, + [gcc_qmip_disp_ahb_clk] = &gcc_qmip_disp_ahb_clk.clkr, + [gcc_qmip_video_cvp_ahb_clk] = &gcc_qmip_video_cvp_ahb_clk.clkr, + [gcc_qmip_video_vcodec_ahb_clk] = &gcc_qmip_video_vcodec_ahb_clk.clkr, + [gcc_qupv3_wrap0_core_2x_clk] = &gcc_qupv3_wrap0_core_2x_clk.clkr, + [gcc_qupv3_wrap0_core_clk] = &gcc_qupv3_wrap0_core_clk.clkr, + [gcc_qupv3_wrap0_s0_clk] = &gcc_qupv3_wrap0_s0_clk.clkr, + [gcc_qupv3_wrap0_s0_clk_src] = &gcc_qupv3_wrap0_s0_clk_src.clkr, + [gcc_qupv3_wrap0_s1_clk] = &gcc_qupv3_wrap0_s1_clk.clkr, + [gcc_qupv3_wrap0_s1_clk_src] = &gcc_qupv3_wrap0_s1_clk_src.clkr, + [gcc_qupv3_wrap0_s2_clk] = &gcc_qupv3_wrap0_s2_clk.clkr, + [gcc_qupv3_wrap0_s2_clk_src] = &gcc_qupv3_wrap0_s2_clk_src.clkr, + [gcc_qupv3_wrap0_s3_clk] = &gcc_qupv3_wrap0_s3_clk.clkr, + [gcc_qupv3_wrap0_s3_clk_src] = &gcc_qupv3_wrap0_s3_clk_src.clkr, + [gcc_qupv3_wrap0_s4_clk] = &gcc_qupv3_wrap0_s4_clk.clkr, + [gcc_qupv3_wrap0_s4_clk_src] = &gcc_qupv3_wrap0_s4_clk_src.clkr, + [gcc_qupv3_wrap0_s5_clk] = &gcc_qupv3_wrap0_s5_clk.clkr, + [gcc_qupv3_wrap0_s5_clk_src] = &gcc_qupv3_wrap0_s5_clk_src.clkr, + [gcc_qupv3_wrap0_s6_clk] = &gcc_qupv3_wrap0_s6_clk.clkr, + [gcc_qupv3_wrap0_s6_clk_src] = &gcc_qupv3_wrap0_s6_clk_src.clkr, + [gcc_qupv3_wrap0_s7_clk] = &gcc_qupv3_wrap0_s7_clk.clkr, + [gcc_qupv3_wrap0_s7_clk_src] = &gcc_qupv3_wrap0_s7_clk_src.clkr, + [gcc_qupv3_wrap1_core_2x_clk] = &gcc_qupv3_wrap1_core_2x_clk.clkr, + [gcc_qupv3_wrap1_core_clk] = &gcc_qupv3_wrap1_core_clk.clkr, + [gcc_qupv3_wrap1_s0_clk] = &gcc_qupv3_wrap1_s0_clk.clkr, + [gcc_qupv3_wrap1_s0_clk_src] = &gcc_qupv3_wrap1_s0_clk_src.clkr, + [gcc_qupv3_wrap1_s1_clk] = &gcc_qupv3_wrap1_s1_clk.clkr, + [gcc_qupv3_wrap1_s1_clk_src] = &gcc_qupv3_wrap1_s1_clk_src.clkr, + [gcc_qupv3_wrap1_s2_clk] = &gcc_qupv3_wrap1_s2_clk.clkr, + [gcc_qupv3_wrap1_s2_clk_src] = &gcc_qupv3_wrap1_s2_clk_src.clkr, + [gcc_qupv3_wrap1_s3_clk] = &gcc_qupv3_wrap1_s3_clk.clkr, + [gcc_qupv3_wrap1_s3_clk_src] = &gcc_qupv3_wrap1_s3_clk_src.clkr, + [gcc_qupv3_wrap1_s4_clk] = &gcc_qupv3_wrap1_s4_clk.clkr, + [gcc_qupv3_wrap1_s4_clk_src] = &gcc_qupv3_wrap1_s4_clk_src.clkr, + [gcc_qupv3_wrap1_s5_clk] = &gcc_qupv3_wrap1_s5_clk.clkr, + [gcc_qupv3_wrap1_s5_clk_src] = &gcc_qupv3_wrap1_s5_clk_src.clkr, + [gcc_qupv3_wrap2_core_2x_clk] = &gcc_qupv3_wrap2_core_2x_clk.clkr, + [gcc_qupv3_wrap2_core_clk] = &gcc_qupv3_wrap2_core_clk.clkr, + [gcc_qupv3_wrap2_s0_clk] = &gcc_qupv3_wrap2_s0_clk.clkr, + [gcc_qupv3_wrap2_s0_clk_src] = &gcc_qupv3_wrap2_s0_clk_src.clkr, + [gcc_qupv3_wrap2_s1_clk] = &gcc_qupv3_wrap2_s1_clk.clkr, + [gcc_qupv3_wrap2_s1_clk_src] = &gcc_qupv3_wrap2_s1_clk_src.clkr, + [gcc_qupv3_wrap2_s2_clk] = &gcc_qupv3_wrap2_s2_clk.clkr, + [gcc_qupv3_wrap2_s2_clk_src] = &gcc_qupv3_wrap2_s2_clk_src.clkr, + [gcc_qupv3_wrap2_s3_clk] = &gcc_qupv3_wrap2_s3_clk.clkr, + [gcc_qupv3_wrap2_s3_clk_src] = &gcc_qupv3_wrap2_s3_clk_src.clkr, + [gcc_qupv3_wrap2_s4_clk] = &gcc_qupv3_wrap2_s4_clk.clkr, + [gcc_qupv3_wrap2_s4_clk_src] = &gcc_qupv3_wrap2_s4_clk_src.clkr, + [gcc_qupv3_wrap2_s5_clk] = &gcc_qupv3_wrap2_s5_clk.clkr, + [gcc_qupv3_wrap2_s5_clk_src] = &gcc_qupv3_wrap2_s5_clk_src.clkr, + [gcc_qupv3_wrap_0_m_ahb_clk] = &gcc_qupv3_wrap_0_m_ahb_clk.clkr, + [gcc_qupv3_wrap_0_s_ahb_clk] = &gcc_qupv3_wrap_0_s_ahb_clk.clkr, + [gcc_qupv3_wrap_1_m_ahb_clk] = &gcc_qupv3_wrap_1_m_ahb_clk.clkr, + [gcc_qupv3_wrap_1_s_ahb_clk] = &gcc_qupv3_wrap_1_s_ahb_clk.clkr, + [gcc_qupv3_wrap_2_m_ahb_clk] = &gcc_qupv3_wrap_2_m_ahb_clk.clkr, + [gcc_qupv3_wrap_2_s_ahb_clk] = &gcc_qupv3_wrap_2_s_ahb_clk.clkr, + [gcc_sdcc2_ahb_clk] = &gcc_sdcc2_ahb_clk.clkr, + [gcc_sdcc2_apps_clk] = &gcc_sdcc2_apps_clk.clkr, + [gcc_sdcc2_apps_clk_src] = &gcc_sdcc2_apps_clk_src.clkr, + [gcc_sdcc4_ahb_clk] = &gcc_sdcc4_ahb_clk.clkr, + [gcc_sdcc4_apps_clk] = &gcc_sdcc4_apps_clk.clkr, + [gcc_sdcc4_apps_clk_src] = &gcc_sdcc4_apps_clk_src.clkr, + [gcc_tsif_ahb_clk] = &gcc_tsif_ahb_clk.clkr, + [gcc_tsif_inactivity_timers_clk] = &gcc_tsif_inactivity_timers_clk.clkr, + [gcc_tsif_ref_clk] = &gcc_tsif_ref_clk.clkr, + [gcc_tsif_ref_clk_src] = &gcc_tsif_ref_clk_src.clkr, + [gcc_ufs_1x_clkref_en] = &gcc_ufs_1x_clkref_en.clkr, + [gcc_ufs_card_ahb_clk] = &gcc_ufs_card_ahb_clk.clkr, + [gcc_ufs_card_axi_clk] = &gcc_ufs_card_axi_clk.clkr, + [gcc_ufs_card_axi_clk_src] = &gcc_ufs_card_axi_clk_src.clkr, + [gcc_ufs_card_ice_core_clk] = &gcc_ufs_card_ice_core_clk.clkr, + [gcc_ufs_card_ice_core_clk_src] = &gcc_ufs_card_ice_core_clk_src.clkr, + [gcc_ufs_card_phy_aux_clk] = &gcc_ufs_card_phy_aux_clk.clkr, + [gcc_ufs_card_phy_aux_clk_src] = &gcc_ufs_card_phy_aux_clk_src.clkr, + [gcc_ufs_card_rx_symbol_0_clk] = &gcc_ufs_card_rx_symbol_0_clk.clkr, + [gcc_ufs_card_rx_symbol_1_clk] = &gcc_ufs_card_rx_symbol_1_clk.clkr, + [gcc_ufs_card_tx_symbol_0_clk] = &gcc_ufs_card_tx_symbol_0_clk.clkr, + [gcc_ufs_card_unipro_core_clk] = &gcc_ufs_card_unipro_core_clk.clkr, + [gcc_ufs_card_unipro_core_clk_src] = + &gcc_ufs_card_unipro_core_clk_src.clkr, + [gcc_ufs_phy_ahb_clk] = &gcc_ufs_phy_ahb_clk.clkr, + [gcc_ufs_phy_axi_clk] = &gcc_ufs_phy_axi_clk.clkr, + [gcc_ufs_phy_axi_clk_src] = &gcc_ufs_phy_axi_clk_src.clkr, + [gcc_ufs_phy_ice_core_clk] = &gcc_ufs_phy_ice_core_clk.clkr, + [gcc_ufs_phy_ice_core_clk_src] = &gcc_ufs_phy_ice_core_clk_src.clkr, + [gcc_ufs_phy_phy_aux_clk] = &gcc_ufs_phy_phy_aux_clk.clkr, + [gcc_ufs_phy_phy_aux_clk_src] = &gcc_ufs_phy_phy_aux_clk_src.clkr, + [gcc_ufs_phy_rx_symbol_0_clk] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [gcc_ufs_phy_rx_symbol_1_clk] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [gcc_ufs_phy_tx_symbol_0_clk] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, + [gcc_ufs_phy_unipro_core_clk] = &gcc_ufs_phy_unipro_core_clk.clkr, + [gcc_ufs_phy_unipro_core_clk_src] = + &gcc_ufs_phy_unipro_core_clk_src.clkr, + [gcc_usb30_prim_master_clk] = &gcc_usb30_prim_master_clk.clkr, + [gcc_usb30_prim_master_clk_src] = &gcc_usb30_prim_master_clk_src.clkr, + [gcc_usb30_prim_mock_utmi_clk] = &gcc_usb30_prim_mock_utmi_clk.clkr, + [gcc_usb30_prim_mock_utmi_clk_src] = + &gcc_usb30_prim_mock_utmi_clk_src.clkr, + [gcc_usb30_prim_mock_utmi_postdiv_clk_src] = + &gcc_usb30_prim_mock_utmi_postdiv_clk_src.clkr, + [gcc_usb30_prim_sleep_clk] = &gcc_usb30_prim_sleep_clk.clkr, + [gcc_usb30_sec_master_clk] = &gcc_usb30_sec_master_clk.clkr, + [gcc_usb30_sec_master_clk_src] = &gcc_usb30_sec_master_clk_src.clkr, + [gcc_usb30_sec_mock_utmi_clk] = &gcc_usb30_sec_mock_utmi_clk.clkr, + [gcc_usb30_sec_mock_utmi_clk_src] = + &gcc_usb30_sec_mock_utmi_clk_src.clkr, + [gcc_usb30_sec_mock_utmi_postdiv_clk_src] = + &gcc_usb30_sec_mock_utmi_postdiv_clk_src.clkr, + [gcc_usb30_sec_sleep_clk] = &gcc_usb30_sec_sleep_clk.clkr, + [gcc_usb3_prim_phy_aux_clk] = &gcc_usb3_prim_phy_aux_clk.clkr, + [gcc_usb3_prim_phy_aux_clk_src] = &gcc_usb3_prim_phy_aux_clk_src.clkr, + [gcc_usb3_prim_phy_com_aux_clk] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [gcc_usb3_prim_phy_pipe_clk] = &gcc_usb3_prim_phy_pipe_clk.clkr, + [gcc_usb3_sec_clkref_en] = &gcc_usb3_sec_clkref_en.clkr, + [gcc_usb3_sec_phy_aux_clk] = &gcc_usb3_sec_phy_aux_clk.clkr, + [gcc_usb3_sec_phy_aux_clk_src] = &gcc_usb3_sec_phy_aux_clk_src.clkr, + [gcc_usb3_sec_phy_com_aux_clk] = &gcc_usb3_sec_phy_com_aux_clk.clkr, + [gcc_usb3_sec_phy_pipe_clk] = &gcc_usb3_sec_phy_pipe_clk.clkr, + [gcc_video_axi0_clk] = &gcc_video_axi0_clk.clkr, + [gcc_video_axi1_clk] = &gcc_video_axi1_clk.clkr, + [gcc_video_xo_clk] = &gcc_video_xo_clk.clkr, + [gpll0] = &gpll0.clkr, + [gpll0_out_even] = &gpll0_out_even.clkr, + [gpll4] = &gpll4.clkr, + [gpll9] = &gpll9.clkr, +}; + +static struct gdsc *gcc_sm8250_gdscs[] = { + [pcie_0_gdsc] = &pcie_0_gdsc, + [pcie_1_gdsc] = &pcie_1_gdsc, + [pcie_2_gdsc] = &pcie_2_gdsc, + [ufs_card_gdsc] = &ufs_card_gdsc, + [ufs_phy_gdsc] = &ufs_phy_gdsc, + [usb30_prim_gdsc] = &usb30_prim_gdsc, + [usb30_sec_gdsc] = &usb30_sec_gdsc, + [hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc] = + &hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc, + [hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc] = + &hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc, + [hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc] = + &hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc, + [hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc] = + &hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc, +}; + +static const struct qcom_reset_map gcc_sm8250_resets[] = { + [gcc_gpu_bcr] = { 0x71000 }, + [gcc_mmss_bcr] = { 0xb000 }, + [gcc_npu_bwmon_bcr] = { 0x73000 }, + [gcc_npu_bcr] = { 0x4d000 }, + [gcc_pcie_0_bcr] = { 0x6b000 }, + [gcc_pcie_0_link_down_bcr] = { 0x6c014 }, + [gcc_pcie_0_nocsr_com_phy_bcr] = { 0x6c020 }, + [gcc_pcie_0_phy_bcr] = { 0x6c01c }, + [gcc_pcie_0_phy_nocsr_com_phy_bcr] = { 0x6c028 }, + [gcc_pcie_1_bcr] = { 0x8d000 }, + [gcc_pcie_1_link_down_bcr] = { 0x8e014 }, + [gcc_pcie_1_nocsr_com_phy_bcr] = { 0x8e020 }, + [gcc_pcie_1_phy_bcr] = { 0x8e01c }, + [gcc_pcie_1_phy_nocsr_com_phy_bcr] = { 0x8e000 }, + [gcc_pcie_2_bcr] = { 0x6000 }, + [gcc_pcie_2_link_down_bcr] = { 0x1f014 }, + [gcc_pcie_2_nocsr_com_phy_bcr] = { 0x1f020 }, + [gcc_pcie_2_phy_bcr] = { 0x1f01c }, + [gcc_pcie_2_phy_nocsr_com_phy_bcr] = { 0x1f028 }, + [gcc_pcie_phy_bcr] = { 0x6f000 }, + [gcc_pcie_phy_cfg_ahb_bcr] = { 0x6f00c }, + [gcc_pcie_phy_com_bcr] = { 0x6f010 }, + [gcc_pdm_bcr] = { 0x33000 }, + [gcc_prng_bcr] = { 0x34000 }, + [gcc_qupv3_wrapper_0_bcr] = { 0x17000 }, + [gcc_qupv3_wrapper_1_bcr] = { 0x18000 }, + [gcc_qupv3_wrapper_2_bcr] = { 0x1e000 }, + [gcc_qusb2phy_prim_bcr] = { 0x12000 }, + [gcc_qusb2phy_sec_bcr] = { 0x12004 }, + [gcc_sdcc2_bcr] = { 0x14000 }, + [gcc_sdcc4_bcr] = { 0x16000 }, + [gcc_tsif_bcr] = { 0x36000 }, + [gcc_ufs_card_bcr] = { 0x75000 }, + [gcc_ufs_phy_bcr] = { 0x77000 }, + [gcc_usb30_prim_bcr] = { 0xf000 }, + [gcc_usb30_sec_bcr] = { 0x10000 }, + [gcc_usb3_dp_phy_prim_bcr] = { 0x50008 }, + [gcc_usb3_dp_phy_sec_bcr] = { 0x50014 }, + [gcc_usb3_phy_prim_bcr] = { 0x50000 }, + [gcc_usb3_phy_sec_bcr] = { 0x5000c }, + [gcc_usb3phy_phy_prim_bcr] = { 0x50004 }, + [gcc_usb3phy_phy_sec_bcr] = { 0x50010 }, + [gcc_usb_phy_cfg_ahb2phy_bcr] = { 0x6a000 }, + [gcc_video_axi0_clk_ares] = { 0xb024, 2 }, + [gcc_video_axi1_clk_ares] = { 0xb028, 2 }, +}; + +static const struct clk_rcg_dfs_data gcc_dfs_clocks[] = { + define_rcg_dfs(gcc_qupv3_wrap0_s0_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s1_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s2_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s3_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s4_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s5_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s6_clk_src), + define_rcg_dfs(gcc_qupv3_wrap0_s7_clk_src), + define_rcg_dfs(gcc_qupv3_wrap1_s0_clk_src), + define_rcg_dfs(gcc_qupv3_wrap1_s1_clk_src), + define_rcg_dfs(gcc_qupv3_wrap1_s2_clk_src), + define_rcg_dfs(gcc_qupv3_wrap1_s3_clk_src), + define_rcg_dfs(gcc_qupv3_wrap1_s4_clk_src), + define_rcg_dfs(gcc_qupv3_wrap1_s5_clk_src), + define_rcg_dfs(gcc_qupv3_wrap2_s0_clk_src), + define_rcg_dfs(gcc_qupv3_wrap2_s1_clk_src), + define_rcg_dfs(gcc_qupv3_wrap2_s2_clk_src), + define_rcg_dfs(gcc_qupv3_wrap2_s3_clk_src), + define_rcg_dfs(gcc_qupv3_wrap2_s4_clk_src), + define_rcg_dfs(gcc_qupv3_wrap2_s5_clk_src), +}; + +static const struct regmap_config gcc_sm8250_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x9c100, + .fast_io = true, +}; + +static const struct qcom_cc_desc gcc_sm8250_desc = { + .config = &gcc_sm8250_regmap_config, + .clks = gcc_sm8250_clocks, + .num_clks = array_size(gcc_sm8250_clocks), + .resets = gcc_sm8250_resets, + .num_resets = array_size(gcc_sm8250_resets), + .gdscs = gcc_sm8250_gdscs, + .num_gdscs = array_size(gcc_sm8250_gdscs), +}; + +static const struct of_device_id gcc_sm8250_match_table[] = { + { .compatible = "qcom,gcc-sm8250" }, + { } +}; +module_device_table(of, gcc_sm8250_match_table); + +static int gcc_sm8250_probe(struct platform_device *pdev) +{ + struct regmap *regmap; + int ret; + + regmap = qcom_cc_map(pdev, &gcc_sm8250_desc); + if (is_err(regmap)) + return ptr_err(regmap); + + /* + * disable the gpll0 active input to npu and gpu + * via misc registers. + */ + regmap_update_bits(regmap, 0x4d110, 0x3, 0x3); + regmap_update_bits(regmap, 0x71028, 0x3, 0x3); + + /* + * keep the clocks always-on + * gcc_video_ahb_clk, gcc_camera_ahb_clk, gcc_disp_ahb_clk, + * gcc_cpuss_dvm_bus_clk, gcc_gpu_cfg_ahb_clk, + * gcc_sys_noc_cpuss_ahb_clk + */ + regmap_update_bits(regmap, 0x0b004, bit(0), bit(0)); + regmap_update_bits(regmap, 0x0b008, bit(0), bit(0)); + regmap_update_bits(regmap, 0x0b00c, bit(0), bit(0)); + regmap_update_bits(regmap, 0x4818c, bit(0), bit(0)); + regmap_update_bits(regmap, 0x71004, bit(0), bit(0)); + regmap_update_bits(regmap, 0x52000, bit(0), bit(0)); + + ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks, + array_size(gcc_dfs_clocks)); + if (ret) + return ret; + + return qcom_cc_really_probe(pdev, &gcc_sm8250_desc, regmap); +} + +static struct platform_driver gcc_sm8250_driver = { + .probe = gcc_sm8250_probe, + .driver = { + .name = "gcc-sm8250", + .of_match_table = gcc_sm8250_match_table, + }, +}; + +static int __init gcc_sm8250_init(void) +{ + return platform_driver_register(&gcc_sm8250_driver); +} +subsys_initcall(gcc_sm8250_init); + +static void __exit gcc_sm8250_exit(void) +{ + platform_driver_unregister(&gcc_sm8250_driver); +} +module_exit(gcc_sm8250_exit); + +module_description("qti gcc sm8250 driver"); +module_license("gpl v2");
|
Clock
|
3e5770921a8846ed1071257398eb7cd369399412
|
taniya das bryan o donoghue bryan odonoghue linaro org bryan o donoghue bryan odonoghue linaro org
|
drivers
|
clk
|
qcom
|
clk: qcom: gpucc: add support for gx gdsc for sc7180
|
most of the time the cpu should not be touching the gx domain on the gpu except for a very special use case when the cpu needs to force the gx headswitch off. add the gx domain for that use case. as part of this add a dummy enable function for the gx gdsc to simulate success so that the pm_runtime reference counting is correct. this matches what was done in sdm845 in commit 85a3d920d30a ("clk: qcom: add a dummy enable function for gx gdsc").
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for gx gdsc for sc7180
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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['qcom', 'gpucc']
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['c']
| 1
| 37
| 0
|
--- diff --git a/drivers/clk/qcom/gpucc-sc7180.c b/drivers/clk/qcom/gpucc-sc7180.c --- a/drivers/clk/qcom/gpucc-sc7180.c +++ b/drivers/clk/qcom/gpucc-sc7180.c +/* + * on sc7180 the gpu gx domain is *almost* entirely controlled by the gmu + * running in the cx domain so the cpu doesn't need to know anything about the + * gx domain except.... + * + * hardware constraints dictate that the gx be powered down before the cx. if + * the gmu crashes it could leave the gx on. in order to successfully bring back + * the device the cpu needs to disable the gx headswitch. there being no sane + * way to reach in and touch that register from deep inside the gpu driver we + * need to set up the infrastructure to be able to ensure that the gpu can + * ensure that the gx is off during this super special case. we do this by + * defining a gx gdsc with a dummy enable function and a "default" disable + * function. + * + * this allows us to attach with genpd_dev_pm_attach_by_name() in the gpu + * driver. during power up, nothing will happen from the cpu (and the gmu will + * power up normally but during power down this will ensure that the gx domain + * is *really* off - this gives us a semi standard way of doing what we need. + */ +static int gx_gdsc_enable(struct generic_pm_domain *domain) +{ + /* do nothing but give genpd the impression that we were successful */ + return 0; +} + +static struct gdsc gx_gdsc = { + .gdscr = 0x100c, + .clamp_io_ctrl = 0x1508, + .pd = { + .name = "gx_gdsc", + .power_on = gx_gdsc_enable, + }, + .pwrsts = pwrsts_off_on, + .flags = clamp_io, +}; + + [gx_gdsc] = &gx_gdsc,
|
Clock
|
1a6151128c847c473da1c7e7022ef78d3e2d6689
|
taniya das douglas anderson dianders chromium org
|
drivers
|
clk
|
qcom
|
clk: qcom: rpmh: add support for rpmh clocks on sm8250
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add support for rpmh clocks on sm8250.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add support for rpmh clocks on sm8250
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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['qcom', 'rpmh']
|
['c']
| 1
| 24
| 1
|
--- diff --git a/drivers/clk/qcom/clk-rpmh.c b/drivers/clk/qcom/clk-rpmh.c --- a/drivers/clk/qcom/clk-rpmh.c +++ b/drivers/clk/qcom/clk-rpmh.c - * copyright (c) 2018-2019, the linux foundation. all rights reserved. + * copyright (c) 2018-2020, the linux foundation. all rights reserved. +define_clk_rpmh_vrm(sm8250, ln_bb_clk1, ln_bb_clk1_ao, "lnbclka1", 2); + +static struct clk_hw *sm8250_rpmh_clocks[] = { + [rpmh_cxo_clk] = &sdm845_bi_tcxo.hw, + [rpmh_cxo_clk_a] = &sdm845_bi_tcxo_ao.hw, + [rpmh_ln_bb_clk1] = &sm8250_ln_bb_clk1.hw, + [rpmh_ln_bb_clk1_a] = &sm8250_ln_bb_clk1_ao.hw, + [rpmh_ln_bb_clk2] = &sdm845_ln_bb_clk2.hw, + [rpmh_ln_bb_clk2_a] = &sdm845_ln_bb_clk2_ao.hw, + [rpmh_ln_bb_clk3] = &sdm845_ln_bb_clk3.hw, + [rpmh_ln_bb_clk3_a] = &sdm845_ln_bb_clk3_ao.hw, + [rpmh_rf_clk1] = &sdm845_rf_clk1.hw, + [rpmh_rf_clk1_a] = &sdm845_rf_clk1_ao.hw, + [rpmh_rf_clk3] = &sdm845_rf_clk3.hw, + [rpmh_rf_clk3_a] = &sdm845_rf_clk3_ao.hw, +}; + +static const struct clk_rpmh_desc clk_rpmh_sm8250 = { + .clks = sm8250_rpmh_clocks, + .num_clks = array_size(sm8250_rpmh_clocks), +}; + + { .compatible = "qcom,sm8250-rpmh-clk", .data = &clk_rpmh_sm8250},
|
Clock
|
29093b1a5833c24c692abb1370de547d2a60e6be
|
taniya das vinod koul vkoul kernel org bjorn andersson bjorn andersson linaro org
|
drivers
|
clk
|
qcom
|
clk, clk-si5341: support multiple input ports
|
the si5341 and si5340 have multiple input clock options. so far, the driver only supported the xtal input, this adds support for the three external clock inputs as well.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
support multiple input ports
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['si5341']
|
['c']
| 1
| 196
| 16
|
--- diff --git a/drivers/clk/clk-si5341.c b/drivers/clk/clk-si5341.c --- a/drivers/clk/clk-si5341.c +++ b/drivers/clk/clk-si5341.c +#define si5341_num_inputs 4 + - struct clk *pxtal; - const char *pxtal_name; + struct clk *input_clk[si5341_num_inputs]; + const char *input_clk_name[si5341_num_inputs]; +#define si5341_in_sel 0x0021 +#define si5341_xaxb_cfg 0x090e +#define si5341_in_en 0x0949 +#define si5341_inx_to_pfd_en 0x094a + +/* input selection */ +#define si5341_in_sel_mask 0x06 +#define si5341_in_sel_shift 1 +#define si5341_in_sel_regctrl 0x01 +#define si5341_inx_to_pfd_shift 4 + +/* xtal config bits */ +#define si5341_xaxb_cfg_extclk_en bit(0) +#define si5341_xaxb_cfg_pdnb bit(1) +#define si5341_px_upd 0x0230 +static const char * const si5341_input_clock_names[] = { + "in0", "in1", "in2", "xtal" +}; + +static int si5341_clk_get_selected_input(struct clk_si5341 *data) +{ + int err; + u32 val; + + err = regmap_read(data->regmap, si5341_in_sel, &val); + if (err < 0) + return err; + + return (val & si5341_in_sel_mask) >> si5341_in_sel_shift; +} + +static u8 si5341_clk_get_parent(struct clk_hw *hw) +{ + struct clk_si5341 *data = to_clk_si5341(hw); + int res = si5341_clk_get_selected_input(data); + + if (res < 0) + return 0; /* apparently we cannot report errors */ + + return res; +} + +static int si5341_clk_reparent(struct clk_si5341 *data, u8 index) +{ + int err; + u8 val; + + val = (index << si5341_in_sel_shift) & si5341_in_sel_mask; + /* enable register-based input selection */ + val |= si5341_in_sel_regctrl; + + err = regmap_update_bits(data->regmap, + si5341_in_sel, si5341_in_sel_regctrl | si5341_in_sel_mask, val); + if (err < 0) + return err; + + if (index < 3) { + /* enable input buffer for selected input */ + err = regmap_update_bits(data->regmap, + si5341_in_en, 0x07, bit(index)); + if (err < 0) + return err; + + /* enables the input to phase detector */ + err = regmap_update_bits(data->regmap, si5341_inx_to_pfd_en, + 0x7 << si5341_inx_to_pfd_shift, + bit(index + si5341_inx_to_pfd_shift)); + if (err < 0) + return err; + + /* power down xtal oscillator and buffer */ + err = regmap_update_bits(data->regmap, si5341_xaxb_cfg, + si5341_xaxb_cfg_pdnb, 0); + if (err < 0) + return err; + + /* + * set the p divider to "1". there's no explanation in the + * datasheet of these registers, but the clockbuilder software + * programs a "1" when the input is being used. + */ + err = regmap_write(data->regmap, si5341_in_pdiv(index), 1); + if (err < 0) + return err; + + err = regmap_write(data->regmap, si5341_in_pset(index), 1); + if (err < 0) + return err; + + /* set update pdiv bit */ + err = regmap_write(data->regmap, si5341_px_upd, bit(index)); + if (err < 0) + return err; + } else { + /* disable all input buffers */ + err = regmap_update_bits(data->regmap, si5341_in_en, 0x07, 0); + if (err < 0) + return err; + + /* disable input to phase detector */ + err = regmap_update_bits(data->regmap, si5341_inx_to_pfd_en, + 0x7 << si5341_inx_to_pfd_shift, 0); + if (err < 0) + return err; + + /* power up xtal oscillator and buffer */ + err = regmap_update_bits(data->regmap, si5341_xaxb_cfg, + si5341_xaxb_cfg_pdnb, si5341_xaxb_cfg_pdnb); + if (err < 0) + return err; + } + + return 0; +} + +static int si5341_clk_set_parent(struct clk_hw *hw, u8 index) +{ + struct clk_si5341 *data = to_clk_si5341(hw); + + return si5341_clk_reparent(data, index); +} + + .set_parent = si5341_clk_set_parent, + .get_parent = si5341_clk_get_parent, - /* update bits for synth config */ + /* update bits for p divider and synth config */ + regmap_reg_range(si5341_px_upd, si5341_px_upd), + int sel; - m_den = clk_get_rate(data->pxtal) / 10; + sel = si5341_clk_get_selected_input(data); + if (sel < 0) + return sel; + + m_den = clk_get_rate(data->input_clk[sel]) / 10; +static int si5341_clk_select_active_input(struct clk_si5341 *data) +{ + int res; + int err; + int i; + + res = si5341_clk_get_selected_input(data); + if (res < 0) + return res; + + /* if the current register setting is invalid, pick the first input */ + if (!data->input_clk[res]) { + dev_dbg(&data->i2c_client->dev, + "input %d not connected, rerouting ", res); + res = -enodev; + for (i = 0; i < si5341_num_inputs; ++i) { + if (data->input_clk[i]) { + res = i; + break; + } + } + if (res < 0) { + dev_err(&data->i2c_client->dev, + "no clock input available "); + return res; + } + } + + /* make sure the selected clock is also enabled and routed */ + err = si5341_clk_reparent(data, res); + if (err < 0) + return err; + + err = clk_prepare_enable(data->input_clk[res]); + if (err < 0) + return err; + + return res; +} + + struct clk *input; - data->pxtal = devm_clk_get(&client->dev, "xtal"); - if (is_err(data->pxtal)) { - if (ptr_err(data->pxtal) == -eprobe_defer) - return -eprobe_defer; - - dev_err(&client->dev, "missing xtal clock input "); + for (i = 0; i < si5341_num_inputs; ++i) { + input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); + if (is_err(input)) { + if (ptr_err(input) == -eprobe_defer) + return -eprobe_defer; + data->input_clk_name[i] = si5341_input_clock_names[i]; + } else { + data->input_clk[i] = input; + data->input_clk_name[i] = __clk_get_name(input); + } - /* "activate" the xtal (usually a fixed clock) */ - clk_prepare_enable(data->pxtal); - + } + + /* input must be up and running at this point */ + err = si5341_clk_select_active_input(data); + if (err < 0) + return err; + if (initialization_required) { - data->pxtal_name = __clk_get_name(data->pxtal); - init.parent_names = &data->pxtal_name; - init.num_parents = 1; /* for now, only xtal input supported */ + init.parent_names = data->input_clk_name; + init.num_parents = si5341_num_inputs;
|
Clock
|
692751879ea876dec81357e6f1f8ca0ced131ceb
|
mike looijmans
|
drivers
|
clk
| |
clk: sprd: add clocks support for sc9863a
|
add the list of clocks for the unisoc sc9863a, along with clock initialization.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add clocks support for sc9863a
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['sprd']
|
['kconfig', 'c', 'makefile']
| 3
| 1,781
| 0
|
--- diff --git a/drivers/clk/sprd/kconfig b/drivers/clk/sprd/kconfig --- a/drivers/clk/sprd/kconfig +++ b/drivers/clk/sprd/kconfig + +config sprd_sc9863a_clk + tristate "support for the spreadtrum sc9863a clocks" + depends on (arm64 && arch_sprd) || compile_test + default arm64 && arch_sprd + help + support for the global clock controller on sc9863a devices. + say y if you want to use peripheral devices on sc9863a soc. diff --git a/drivers/clk/sprd/makefile b/drivers/clk/sprd/makefile --- a/drivers/clk/sprd/makefile +++ b/drivers/clk/sprd/makefile +obj-$(config_sprd_sc9863a_clk) += sc9863a-clk.o diff --git a/drivers/clk/sprd/sc9863a-clk.c b/drivers/clk/sprd/sc9863a-clk.c --- /dev/null +++ b/drivers/clk/sprd/sc9863a-clk.c +// spdx-license-identifier: gpl-2.0-only +/* + * unisoc sc9863a clock driver + * + * copyright (c) 2019 unisoc, inc. + * author: chunyan zhang <chunyan.zhang@unisoc.com> + */ + +#include <linux/clk-provider.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include <dt-bindings/clock/sprd,sc9863a-clk.h> + +#include "common.h" +#include "composite.h" +#include "div.h" +#include "gate.h" +#include "mux.h" +#include "pll.h" + +/* mpll*_gate clocks control cpu cores, they were enabled by default */ +sprd_pll_sc_gate_clk_fw_name(mpll0_gate, "mpll0-gate", "ext-26m", 0x94, + 0x1000, bit(0), clk_ignore_unused, 0, 240); +sprd_pll_sc_gate_clk_fw_name(dpll0_gate, "dpll0-gate", "ext-26m", 0x98, + 0x1000, bit(0), 0, 0, 240); +sprd_pll_sc_gate_clk_fw_name(lpll_gate, "lpll-gate", "ext-26m", 0x9c, + 0x1000, bit(0), 0, 0, 240); +sprd_pll_sc_gate_clk_fw_name(gpll_gate, "gpll-gate", "ext-26m", 0xa8, + 0x1000, bit(0), 0, 0, 240); +sprd_pll_sc_gate_clk_fw_name(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc, + 0x1000, bit(0), 0, 0, 240); +sprd_pll_sc_gate_clk_fw_name(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0, + 0x1000, bit(0), clk_ignore_unused, 0, 240); +sprd_pll_sc_gate_clk_fw_name(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4, + 0x1000, bit(0), clk_ignore_unused, 0, 240); +sprd_pll_sc_gate_clk_fw_name(isppll_gate, "isppll-gate", "ext-26m", 0x1e8, + 0x1000, bit(0), 0, 0, 240); + +static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = { + /* address base is 0x402b0000 */ + &mpll0_gate.common, + &dpll0_gate.common, + &lpll_gate.common, + &gpll_gate.common, + &dpll1_gate.common, + &mpll1_gate.common, + &mpll2_gate.common, + &isppll_gate.common, +}; + +static struct clk_hw_onecell_data sc9863a_pmu_gate_hws = { + .hws = { + [clk_mpll0_gate] = &mpll0_gate.common.hw, + [clk_dpll0_gate] = &dpll0_gate.common.hw, + [clk_lpll_gate] = &lpll_gate.common.hw, + [clk_gpll_gate] = &gpll_gate.common.hw, + [clk_dpll1_gate] = &dpll1_gate.common.hw, + [clk_mpll1_gate] = &mpll1_gate.common.hw, + [clk_mpll2_gate] = &mpll2_gate.common.hw, + [clk_isppll_gate] = &isppll_gate.common.hw, + }, + .num = clk_pmu_apb_num, +}; + +static const struct sprd_clk_desc sc9863a_pmu_gate_desc = { + .clk_clks = sc9863a_pmu_gate_clks, + .num_clk_clks = array_size(sc9863a_pmu_gate_clks), + .hw_clks = &sc9863a_pmu_gate_hws, +}; + +static const u64 itable[5] = {4, 1000000000, 1200000000, + 1400000000, 1600000000}; + +static const struct clk_bit_field f_twpll[pll_fact_max] = { + { .shift = 95, .width = 1 }, /* lock_done */ + { .shift = 0, .width = 1 }, /* div_s */ + { .shift = 1, .width = 1 }, /* mod_en */ + { .shift = 2, .width = 1 }, /* sdm_en */ + { .shift = 0, .width = 0 }, /* refin */ + { .shift = 3, .width = 3 }, /* ibias */ + { .shift = 8, .width = 11 }, /* n */ + { .shift = 55, .width = 7 }, /* nint */ + { .shift = 32, .width = 23}, /* kint */ + { .shift = 0, .width = 0 }, /* prediv */ + { .shift = 0, .width = 0 }, /* postdiv */ +}; +static sprd_pll_fw_name(twpll, "twpll", "ext-26m", 0x4, 3, itable, + f_twpll, 240, 1000, 1000, 0, 0); +static clk_fixed_factor_hw(twpll_768m, "twpll-768m", &twpll.common.hw, 2, 1, 0); +static clk_fixed_factor_hw(twpll_384m, "twpll-384m", &twpll.common.hw, 4, 1, 0); +static clk_fixed_factor_hw(twpll_192m, "twpll-192m", &twpll.common.hw, 8, 1, 0); +static clk_fixed_factor_hw(twpll_96m, "twpll-96m", &twpll.common.hw, 16, 1, 0); +static clk_fixed_factor_hw(twpll_48m, "twpll-48m", &twpll.common.hw, 32, 1, 0); +static clk_fixed_factor_hw(twpll_24m, "twpll-24m", &twpll.common.hw, 64, 1, 0); +static clk_fixed_factor_hw(twpll_12m, "twpll-12m", &twpll.common.hw, 128, 1, 0); +static clk_fixed_factor_hw(twpll_512m, "twpll-512m", &twpll.common.hw, 3, 1, 0); +static clk_fixed_factor_hw(twpll_256m, "twpll-256m", &twpll.common.hw, 6, 1, 0); +static clk_fixed_factor_hw(twpll_128m, "twpll-128m", &twpll.common.hw, 12, 1, 0); +static clk_fixed_factor_hw(twpll_64m, "twpll-64m", &twpll.common.hw, 24, 1, 0); +static clk_fixed_factor_hw(twpll_307m2, "twpll-307m2", &twpll.common.hw, 5, 1, 0); +static clk_fixed_factor_hw(twpll_219m4, "twpll-219m4", &twpll.common.hw, 7, 1, 0); +static clk_fixed_factor_hw(twpll_170m6, "twpll-170m6", &twpll.common.hw, 9, 1, 0); +static clk_fixed_factor_hw(twpll_153m6, "twpll-153m6", &twpll.common.hw, 10, 1, 0); +static clk_fixed_factor_hw(twpll_76m8, "twpll-76m8", &twpll.common.hw, 20, 1, 0); +static clk_fixed_factor_hw(twpll_51m2, "twpll-51m2", &twpll.common.hw, 30, 1, 0); +static clk_fixed_factor_hw(twpll_38m4, "twpll-38m4", &twpll.common.hw, 40, 1, 0); +static clk_fixed_factor_hw(twpll_19m2, "twpll-19m2", &twpll.common.hw, 80, 1, 0); + +static const struct clk_bit_field f_lpll[pll_fact_max] = { + { .shift = 95, .width = 1 }, /* lock_done */ + { .shift = 0, .width = 1 }, /* div_s */ + { .shift = 1, .width = 1 }, /* mod_en */ + { .shift = 2, .width = 1 }, /* sdm_en */ + { .shift = 0, .width = 0 }, /* refin */ + { .shift = 6, .width = 2 }, /* ibias */ + { .shift = 8, .width = 11 }, /* n */ + { .shift = 55, .width = 7 }, /* nint */ + { .shift = 32, .width = 23}, /* kint */ + { .shift = 0, .width = 0 }, /* prediv */ + { .shift = 0, .width = 0 }, /* postdiv */ +}; +static sprd_pll_hw(lpll, "lpll", &lpll_gate.common.hw, 0x20, 3, itable, + f_lpll, 240, 1000, 1000, 0, 0); +static clk_fixed_factor_hw(lpll_409m6, "lpll-409m6", &lpll.common.hw, 3, 1, 0); +static clk_fixed_factor_hw(lpll_245m76, "lpll-245m76", &lpll.common.hw, 5, 1, 0); + +static const struct clk_bit_field f_gpll[pll_fact_max] = { + { .shift = 95, .width = 1 }, /* lock_done */ + { .shift = 0, .width = 1 }, /* div_s */ + { .shift = 1, .width = 1 }, /* mod_en */ + { .shift = 2, .width = 1 }, /* sdm_en */ + { .shift = 0, .width = 0 }, /* refin */ + { .shift = 6, .width = 2 }, /* ibias */ + { .shift = 8, .width = 11 }, /* n */ + { .shift = 55, .width = 7 }, /* nint */ + { .shift = 32, .width = 23}, /* kint */ + { .shift = 0, .width = 0 }, /* prediv */ + { .shift = 80, .width = 1 }, /* postdiv */ +}; +static sprd_pll_hw(gpll, "gpll", &gpll_gate.common.hw, 0x38, 3, itable, + f_gpll, 240, 1000, 1000, 1, 400000000); + +static sprd_pll_hw(isppll, "isppll", &isppll_gate.common.hw, 0x50, 3, itable, + f_gpll, 240, 1000, 1000, 0, 0); +static clk_fixed_factor_hw(isppll_468m, "isppll-468m", &isppll.common.hw, 2, 1, 0); + +static struct sprd_clk_common *sc9863a_pll_clks[] = { + /* address base is 0x40353000 */ + &twpll.common, + &lpll.common, + &gpll.common, + &isppll.common, +}; + +static struct clk_hw_onecell_data sc9863a_pll_hws = { + .hws = { + [clk_twpll] = &twpll.common.hw, + [clk_twpll_768m] = &twpll_768m.hw, + [clk_twpll_384m] = &twpll_384m.hw, + [clk_twpll_192m] = &twpll_192m.hw, + [clk_twpll_96m] = &twpll_96m.hw, + [clk_twpll_48m] = &twpll_48m.hw, + [clk_twpll_24m] = &twpll_24m.hw, + [clk_twpll_12m] = &twpll_12m.hw, + [clk_twpll_512m] = &twpll_512m.hw, + [clk_twpll_256m] = &twpll_256m.hw, + [clk_twpll_128m] = &twpll_128m.hw, + [clk_twpll_64m] = &twpll_64m.hw, + [clk_twpll_307m2] = &twpll_307m2.hw, + [clk_twpll_219m4] = &twpll_219m4.hw, + [clk_twpll_170m6] = &twpll_170m6.hw, + [clk_twpll_153m6] = &twpll_153m6.hw, + [clk_twpll_76m8] = &twpll_76m8.hw, + [clk_twpll_51m2] = &twpll_51m2.hw, + [clk_twpll_38m4] = &twpll_38m4.hw, + [clk_twpll_19m2] = &twpll_19m2.hw, + [clk_lpll] = &lpll.common.hw, + [clk_lpll_409m6] = &lpll_409m6.hw, + [clk_lpll_245m76] = &lpll_245m76.hw, + [clk_gpll] = &gpll.common.hw, + [clk_isppll] = &isppll.common.hw, + [clk_isppll_468m] = &isppll_468m.hw, + + }, + .num = clk_anlg_phy_g1_num, +}; + +static const struct sprd_clk_desc sc9863a_pll_desc = { + .clk_clks = sc9863a_pll_clks, + .num_clk_clks = array_size(sc9863a_pll_clks), + .hw_clks = &sc9863a_pll_hws, +}; + +static const u64 itable_mpll[6] = {5, 1000000000, 1200000000, 1400000000, + 1600000000, 1800000000}; +static sprd_pll_hw(mpll0, "mpll0", &mpll0_gate.common.hw, 0x0, 3, itable_mpll, + f_gpll, 240, 1000, 1000, 1, 1000000000); +static sprd_pll_hw(mpll1, "mpll1", &mpll1_gate.common.hw, 0x18, 3, itable_mpll, + f_gpll, 240, 1000, 1000, 1, 1000000000); +static sprd_pll_hw(mpll2, "mpll2", &mpll2_gate.common.hw, 0x30, 3, itable_mpll, + f_gpll, 240, 1000, 1000, 1, 1000000000); +static clk_fixed_factor_hw(mpll2_675m, "mpll2-675m", &mpll2.common.hw, 2, 1, 0); + +static struct sprd_clk_common *sc9863a_mpll_clks[] = { + /* address base is 0x40359000 */ + &mpll0.common, + &mpll1.common, + &mpll2.common, +}; + +static struct clk_hw_onecell_data sc9863a_mpll_hws = { + .hws = { + [clk_mpll0] = &mpll0.common.hw, + [clk_mpll1] = &mpll1.common.hw, + [clk_mpll2] = &mpll2.common.hw, + [clk_mpll2_675m] = &mpll2_675m.hw, + + }, + .num = clk_anlg_phy_g4_num, +}; + +static const struct sprd_clk_desc sc9863a_mpll_desc = { + .clk_clks = sc9863a_mpll_clks, + .num_clk_clks = array_size(sc9863a_mpll_clks), + .hw_clks = &sc9863a_mpll_hws, +}; + +static sprd_sc_gate_clk_fw_name(audio_gate, "audio-gate", "ext-26m", + 0x4, 0x1000, bit(8), 0, 0); + +static sprd_pll_fw_name(rpll, "rpll", "ext-26m", 0x10, + 3, itable, f_lpll, 240, 1000, 1000, 0, 0); + +static clk_fixed_factor_hw(rpll_390m, "rpll-390m", &rpll.common.hw, 2, 1, 0); +static clk_fixed_factor_hw(rpll_260m, "rpll-260m", &rpll.common.hw, 3, 1, 0); +static clk_fixed_factor_hw(rpll_195m, "rpll-195m", &rpll.common.hw, 4, 1, 0); +static clk_fixed_factor_hw(rpll_26m, "rpll-26m", &rpll.common.hw, 30, 1, 0); + +static struct sprd_clk_common *sc9863a_rpll_clks[] = { + /* address base is 0x4035c000 */ + &audio_gate.common, + &rpll.common, +}; + +static struct clk_hw_onecell_data sc9863a_rpll_hws = { + .hws = { + [clk_audio_gate] = &audio_gate.common.hw, + [clk_rpll] = &rpll.common.hw, + [clk_rpll_390m] = &rpll_390m.hw, + [clk_rpll_260m] = &rpll_260m.hw, + [clk_rpll_195m] = &rpll_195m.hw, + [clk_rpll_26m] = &rpll_26m.hw, + }, + .num = clk_anlg_phy_g5_num, +}; + +static const struct sprd_clk_desc sc9863a_rpll_desc = { + .clk_clks = sc9863a_rpll_clks, + .num_clk_clks = array_size(sc9863a_rpll_clks), + .hw_clks = &sc9863a_rpll_hws, +}; + +static const u64 itable_dpll[5] = {4, 1211000000, 1320000000, 1570000000, + 1866000000}; +static sprd_pll_hw(dpll0, "dpll0", &dpll0_gate.common.hw, 0x0, 3, itable_dpll, + f_lpll, 240, 1000, 1000, 0, 0); +static sprd_pll_hw(dpll1, "dpll1", &dpll1_gate.common.hw, 0x18, 3, itable_dpll, + f_lpll, 240, 1000, 1000, 0, 0); + +static clk_fixed_factor_hw(dpll0_933m, "dpll0-933m", &dpll0.common.hw, 2, 1, 0); +static clk_fixed_factor_hw(dpll0_622m3, "dpll0-622m3", &dpll0.common.hw, 3, 1, 0); +static clk_fixed_factor_hw(dpll1_400m, "dpll1-400m", &dpll0.common.hw, 4, 1, 0); +static clk_fixed_factor_hw(dpll1_266m7, "dpll1-266m7", &dpll0.common.hw, 6, 1, 0); +static clk_fixed_factor_hw(dpll1_123m1, "dpll1-123m1", &dpll0.common.hw, 13, 1, 0); +static clk_fixed_factor_hw(dpll1_50m, "dpll1-50m", &dpll0.common.hw, 32, 1, 0); + +static struct sprd_clk_common *sc9863a_dpll_clks[] = { + /* address base is 0x40363000 */ + &dpll0.common, + &dpll1.common, +}; + +static struct clk_hw_onecell_data sc9863a_dpll_hws = { + .hws = { + [clk_dpll0] = &dpll0.common.hw, + [clk_dpll1] = &dpll1.common.hw, + [clk_dpll0_933m] = &dpll0_933m.hw, + [clk_dpll0_622m3] = &dpll0_622m3.hw, + [clk_dpll0_400m] = &dpll1_400m.hw, + [clk_dpll0_266m7] = &dpll1_266m7.hw, + [clk_dpll0_123m1] = &dpll1_123m1.hw, + [clk_dpll0_50m] = &dpll1_50m.hw, + + }, + .num = clk_anlg_phy_g7_num, +}; + +static const struct sprd_clk_desc sc9863a_dpll_desc = { + .clk_clks = sc9863a_dpll_clks, + .num_clk_clks = array_size(sc9863a_dpll_clks), + .hw_clks = &sc9863a_dpll_hws, +}; + +static clk_fixed_factor_fw_name(clk_6m5, "clk-6m5", "ext-26m", 4, 1, 0); +static clk_fixed_factor_fw_name(clk_4m3, "clk-4m3", "ext-26m", 6, 1, 0); +static clk_fixed_factor_fw_name(clk_2m, "clk-2m", "ext-26m", 13, 1, 0); +static clk_fixed_factor_fw_name(clk_250k, "clk-250k", "ext-26m", 104, 1, 0); +static clk_fixed_factor_fw_name(rco_25m, "rco-25m", "rco-100m", 4, 1, 0); +static clk_fixed_factor_fw_name(rco_4m, "rco-4m", "rco-100m", 25, 1, 0); +static clk_fixed_factor_fw_name(rco_2m, "rco-2m", "rco-100m", 50, 1, 0); + +#define sc9863a_mux_flag \ + (clk_get_rate_nocache | clk_set_rate_no_reparent) + +static clk_fixed_factor_fw_name(clk_13m, "clk-13m", "ext-26m", 2, 1, 0); +static const struct clk_parent_data emc_clk_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_384m.hw }, + { .hw = &twpll_512m.hw }, + { .hw = &twpll_768m.hw }, + { .hw = &twpll.common.hw }, +}; +static sprd_mux_clk_data(emc_clk, "emc-clk", emc_clk_parents, 0x220, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data aon_apb_parents[] = { + { .hw = &rco_4m.hw }, + { .hw = &rco_25m.hw }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_96m.hw }, + { .fw_name = "rco-100m" }, + { .hw = &twpll_128m.hw }, +}; +static sprd_comp_clk_data(aon_apb, "aon-apb", aon_apb_parents, 0x224, + 0, 3, 8, 2, 0); + +static const struct clk_parent_data adi_parents[] = { + { .hw = &rco_4m.hw }, + { .hw = &rco_25m.hw }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_38m4.hw }, + { .hw = &twpll_51m2.hw }, +}; +static sprd_mux_clk_data(adi_clk, "adi-clk", adi_parents, 0x228, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data aux_parents[] = { + { .fw_name = "ext-32k" }, + { .hw = &rpll_26m.hw }, + { .fw_name = "ext-26m" }, +}; +static sprd_comp_clk_data(aux0_clk, "aux0-clk", aux_parents, 0x22c, + 0, 5, 8, 4, 0); +static sprd_comp_clk_data(aux1_clk, "aux1-clk", aux_parents, 0x230, + 0, 5, 8, 4, 0); +static sprd_comp_clk_data(aux2_clk, "aux2-clk", aux_parents, 0x234, + 0, 5, 8, 4, 0); +static sprd_comp_clk_data(probe_clk, "probe-clk", aux_parents, 0x238, + 0, 5, 8, 4, 0); + +static const struct clk_parent_data pwm_parents[] = { + { .fw_name = "ext-32k" }, + { .hw = &rpll_26m.hw }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_48m.hw }, +}; +static sprd_mux_clk_data(pwm0_clk, "pwm0-clk", pwm_parents, 0x23c, + 0, 2, sc9863a_mux_flag); +static sprd_mux_clk_data(pwm1_clk, "pwm1-clk", pwm_parents, 0x240, + 0, 2, sc9863a_mux_flag); +static sprd_mux_clk_data(pwm2_clk, "pwm2-clk", pwm_parents, 0x244, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data aon_thm_parents[] = { + { .fw_name = "ext-32k" }, + { .hw = &clk_250k.hw }, +}; +static sprd_mux_clk_data(aon_thm_clk, "aon-thm-clk", aon_thm_parents, 0x25c, + 0, 1, sc9863a_mux_flag); + +static const struct clk_parent_data audif_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_38m4.hw }, + { .hw = &twpll_51m2.hw }, +}; +static sprd_mux_clk_data(audif_clk, "audif-clk", audif_parents, 0x264, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data cpu_dap_parents[] = { + { .hw = &rco_4m.hw }, + { .hw = &rco_25m.hw }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_76m8.hw }, + { .fw_name = "rco-100m" }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, +}; +static sprd_mux_clk_data(cpu_dap_clk, "cpu-dap-clk", cpu_dap_parents, 0x26c, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data cpu_ts_parents[] = { + { .fw_name = "ext-32k" }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, +}; +static sprd_mux_clk_data(cpu_ts_clk, "cpu-ts-clk", cpu_ts_parents, 0x274, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data djtag_tck_parents[] = { + { .hw = &rco_4m.hw }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(djtag_tck_clk, "djtag-tck-clk", djtag_tck_parents, 0x28c, + 0, 1, sc9863a_mux_flag); + +static const struct clk_parent_data emc_ref_parents[] = { + { .hw = &clk_6m5.hw }, + { .hw = &clk_13m.hw }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(emc_ref_clk, "emc-ref-clk", emc_ref_parents, 0x29c, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data cssys_parents[] = { + { .hw = &rco_4m.hw }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_96m.hw }, + { .fw_name = "rco-100m" }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &twpll_512m.hw }, + { .hw = &mpll2_675m.hw }, +}; +static sprd_comp_clk_data(cssys_clk, "cssys-clk", cssys_parents, 0x2a0, + 0, 4, 8, 2, 0); + +static const struct clk_parent_data aon_pmu_parents[] = { + { .fw_name = "ext-32k" }, + { .hw = &rco_4m.hw }, + { .fw_name = "ext-4m" }, +}; +static sprd_mux_clk_data(aon_pmu_clk, "aon-pmu-clk", aon_pmu_parents, 0x2a8, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data pmu_26m_parents[] = { + { .hw = &rco_4m.hw }, + { .hw = &rco_25m.hw }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(pmu_26m_clk, "26m-pmu-clk", pmu_26m_parents, 0x2ac, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data aon_tmr_parents[] = { + { .hw = &rco_4m.hw }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(aon_tmr_clk, "aon-tmr-clk", aon_tmr_parents, 0x2b0, + 0, 1, sc9863a_mux_flag); + +static const struct clk_parent_data power_cpu_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &rco_25m.hw }, + { .fw_name = "rco-100m" }, + { .hw = &twpll_128m.hw }, +}; +static sprd_mux_clk_data(power_cpu_clk, "power-cpu-clk", power_cpu_parents, 0x2c4, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data ap_axi_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_76m8.hw }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_256m.hw }, +}; +static sprd_mux_clk_data(ap_axi, "ap-axi", ap_axi_parents, 0x2c8, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data sdio_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &rpll_390m.hw }, + { .hw = &dpll1_400m.hw }, + { .hw = &lpll_409m6.hw }, +}; +static sprd_mux_clk_data(sdio0_2x, "sdio0-2x", sdio_parents, 0x2cc, + 0, 3, sc9863a_mux_flag); +static sprd_mux_clk_data(sdio1_2x, "sdio1-2x", sdio_parents, 0x2d4, + 0, 3, sc9863a_mux_flag); +static sprd_mux_clk_data(sdio2_2x, "sdio2-2x", sdio_parents, 0x2dc, + 0, 3, sc9863a_mux_flag); +static sprd_mux_clk_data(emmc_2x, "emmc-2x", sdio_parents, 0x2e4, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data dpu_parents[] = { + { .hw = &twpll_153m6.hw }, + { .hw = &twpll_192m.hw }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_384m.hw }, +}; +static sprd_mux_clk_data(dpu_clk, "dpu", dpu_parents, 0x2f4, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data dpu_dpi_parents[] = { + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, + { .hw = &twpll_192m.hw }, +}; +static sprd_comp_clk_data(dpu_dpi, "dpu-dpi", dpu_dpi_parents, 0x2f8, + 0, 2, 8, 4, 0); + +static const struct clk_parent_data otg_ref_parents[] = { + { .hw = &twpll_12m.hw }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(otg_ref_clk, "otg-ref-clk", otg_ref_parents, 0x308, + 0, 1, sc9863a_mux_flag); + +static const struct clk_parent_data sdphy_apb_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_48m.hw }, +}; +static sprd_mux_clk_data(sdphy_apb_clk, "sdphy-apb-clk", sdphy_apb_parents, 0x330, + 0, 1, sc9863a_mux_flag); + +static const struct clk_parent_data alg_io_apb_parents[] = { + { .hw = &rco_4m.hw }, + { .fw_name = "ext-26m" }, + { .hw = &twpll_48m.hw }, + { .hw = &twpll_96m.hw }, +}; +static sprd_mux_clk_data(alg_io_apb_clk, "alg-io-apb-clk", alg_io_apb_parents, 0x33c, + 0, 1, sc9863a_mux_flag); + +static const struct clk_parent_data gpu_parents[] = { + { .hw = &twpll_153m6.hw }, + { .hw = &twpll_192m.hw }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &twpll_512m.hw }, + { .hw = &gpll.common.hw }, +}; +static sprd_comp_clk_data(gpu_core, "gpu-core", gpu_parents, 0x344, + 0, 3, 8, 2, 0); +static sprd_comp_clk_data(gpu_soc, "gpu-soc", gpu_parents, 0x348, + 0, 3, 8, 2, 0); + +static const struct clk_parent_data mm_emc_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_384m.hw }, + { .hw = &isppll_468m.hw }, + { .hw = &twpll_512m.hw }, +}; +static sprd_mux_clk_data(mm_emc, "mm-emc", mm_emc_parents, 0x350, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data mm_ahb_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_96m.hw }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, +}; +static sprd_mux_clk_data(mm_ahb, "mm-ahb", mm_ahb_parents, 0x354, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data bpc_clk_parents[] = { + { .hw = &twpll_192m.hw }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &isppll_468m.hw }, + { .hw = &dpll0_622m3.hw }, +}; +static sprd_mux_clk_data(bpc_clk, "bpc-clk", bpc_clk_parents, 0x358, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data dcam_if_parents[] = { + { .hw = &twpll_192m.hw }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, +}; +static sprd_mux_clk_data(dcam_if_clk, "dcam-if-clk", dcam_if_parents, 0x35c, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data isp_parents[] = { + { .hw = &twpll_128m.hw }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &isppll_468m.hw }, +}; +static sprd_mux_clk_data(isp_clk, "isp-clk", isp_parents, 0x360, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data jpg_parents[] = { + { .hw = &twpll_76m8.hw }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_307m2.hw }, +}; +static sprd_mux_clk_data(jpg_clk, "jpg-clk", jpg_parents, 0x364, + 0, 2, sc9863a_mux_flag); +static sprd_mux_clk_data(cpp_clk, "cpp-clk", jpg_parents, 0x368, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data sensor_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_48m.hw }, + { .hw = &twpll_76m8.hw }, + { .hw = &twpll_96m.hw }, +}; +static sprd_comp_clk_data(sensor0_clk, "sensor0-clk", sensor_parents, 0x36c, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(sensor1_clk, "sensor1-clk", sensor_parents, 0x370, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(sensor2_clk, "sensor2-clk", sensor_parents, 0x374, + 0, 2, 8, 3, 0); + +static const struct clk_parent_data mm_vemc_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &isppll_468m.hw }, +}; +static sprd_mux_clk_data(mm_vemc, "mm-vemc", mm_vemc_parents, 0x378, + 0, 2, sc9863a_mux_flag); + +static sprd_mux_clk_data(mm_vahb, "mm-vahb", mm_ahb_parents, 0x37c, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data vsp_parents[] = { + { .hw = &twpll_76m8.hw }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_307m2.hw }, + { .hw = &twpll_384m.hw }, +}; +static sprd_mux_clk_data(clk_vsp, "vsp-clk", vsp_parents, 0x380, + 0, 3, sc9863a_mux_flag); + +static const struct clk_parent_data core_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_512m.hw }, + { .hw = &twpll_768m.hw }, + { .hw = &lpll.common.hw }, + { .hw = &dpll0.common.hw }, + { .hw = &mpll2.common.hw }, + { .hw = &mpll0.common.hw }, + { .hw = &mpll1.common.hw }, +}; +static sprd_comp_clk_data(core0_clk, "core0-clk", core_parents, 0xa20, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core1_clk, "core1-clk", core_parents, 0xa24, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core2_clk, "core2-clk", core_parents, 0xa28, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core3_clk, "core3-clk", core_parents, 0xa2c, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core4_clk, "core4-clk", core_parents, 0xa30, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core5_clk, "core5-clk", core_parents, 0xa34, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core6_clk, "core6-clk", core_parents, 0xa38, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(core7_clk, "core7-clk", core_parents, 0xa3c, + 0, 3, 8, 3, 0); +static sprd_comp_clk_data(scu_clk, "scu-clk", core_parents, 0xa40, + 0, 3, 8, 3, 0); + +static sprd_div_clk_hw(ace_clk, "ace-clk", &scu_clk.common.hw, 0xa44, + 8, 3, 0); +static sprd_div_clk_hw(axi_periph_clk, "axi-periph-clk", &scu_clk.common.hw, 0xa48, + 8, 3, 0); +static sprd_div_clk_hw(axi_acp_clk, "axi-acp-clk", &scu_clk.common.hw, 0xa4c, + 8, 3, 0); + +static const struct clk_parent_data atb_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_384m.hw }, + { .hw = &twpll_512m.hw }, + { .hw = &mpll2.common.hw }, +}; +static sprd_comp_clk_data(atb_clk, "atb-clk", atb_parents, 0xa50, + 0, 2, 8, 3, 0); +static sprd_div_clk_hw(debug_apb_clk, "debug-apb-clk", &atb_clk.common.hw, 0xa54, + 8, 3, 0); + +static const struct clk_parent_data gic_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_153m6.hw }, + { .hw = &twpll_384m.hw }, + { .hw = &twpll_512m.hw }, +}; +static sprd_comp_clk_data(gic_clk, "gic-clk", gic_parents, 0xa58, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(periph_clk, "periph-clk", gic_parents, 0xa5c, + 0, 2, 8, 3, 0); + +static struct sprd_clk_common *sc9863a_aon_clks[] = { + /* address base is 0x402d0000 */ + &emc_clk.common, + &aon_apb.common, + &adi_clk.common, + &aux0_clk.common, + &aux1_clk.common, + &aux2_clk.common, + &probe_clk.common, + &pwm0_clk.common, + &pwm1_clk.common, + &pwm2_clk.common, + &aon_thm_clk.common, + &audif_clk.common, + &cpu_dap_clk.common, + &cpu_ts_clk.common, + &djtag_tck_clk.common, + &emc_ref_clk.common, + &cssys_clk.common, + &aon_pmu_clk.common, + &pmu_26m_clk.common, + &aon_tmr_clk.common, + &power_cpu_clk.common, + &ap_axi.common, + &sdio0_2x.common, + &sdio1_2x.common, + &sdio2_2x.common, + &emmc_2x.common, + &dpu_clk.common, + &dpu_dpi.common, + &otg_ref_clk.common, + &sdphy_apb_clk.common, + &alg_io_apb_clk.common, + &gpu_core.common, + &gpu_soc.common, + &mm_emc.common, + &mm_ahb.common, + &bpc_clk.common, + &dcam_if_clk.common, + &isp_clk.common, + &jpg_clk.common, + &cpp_clk.common, + &sensor0_clk.common, + &sensor1_clk.common, + &sensor2_clk.common, + &mm_vemc.common, + &mm_vahb.common, + &clk_vsp.common, + &core0_clk.common, + &core1_clk.common, + &core2_clk.common, + &core3_clk.common, + &core4_clk.common, + &core5_clk.common, + &core6_clk.common, + &core7_clk.common, + &scu_clk.common, + &ace_clk.common, + &axi_periph_clk.common, + &axi_acp_clk.common, + &atb_clk.common, + &debug_apb_clk.common, + &gic_clk.common, + &periph_clk.common, +}; + +static struct clk_hw_onecell_data sc9863a_aon_clk_hws = { + .hws = { + [clk_13m] = &clk_13m.hw, + [clk_6m5] = &clk_6m5.hw, + [clk_4m3] = &clk_4m3.hw, + [clk_2m] = &clk_2m.hw, + [clk_250k] = &clk_250k.hw, + [clk_rco_25m] = &rco_25m.hw, + [clk_rco_4m] = &rco_4m.hw, + [clk_rco_2m] = &rco_2m.hw, + [clk_emc] = &emc_clk.common.hw, + [clk_aon_apb] = &aon_apb.common.hw, + [clk_adi] = &adi_clk.common.hw, + [clk_aux0] = &aux0_clk.common.hw, + [clk_aux1] = &aux1_clk.common.hw, + [clk_aux2] = &aux2_clk.common.hw, + [clk_probe] = &probe_clk.common.hw, + [clk_pwm0] = &pwm0_clk.common.hw, + [clk_pwm1] = &pwm1_clk.common.hw, + [clk_pwm2] = &pwm2_clk.common.hw, + [clk_aon_thm] = &aon_thm_clk.common.hw, + [clk_audif] = &audif_clk.common.hw, + [clk_cpu_dap] = &cpu_dap_clk.common.hw, + [clk_cpu_ts] = &cpu_ts_clk.common.hw, + [clk_djtag_tck] = &djtag_tck_clk.common.hw, + [clk_emc_ref] = &emc_ref_clk.common.hw, + [clk_cssys] = &cssys_clk.common.hw, + [clk_aon_pmu] = &aon_pmu_clk.common.hw, + [clk_pmu_26m] = &pmu_26m_clk.common.hw, + [clk_aon_tmr] = &aon_tmr_clk.common.hw, + [clk_power_cpu] = &power_cpu_clk.common.hw, + [clk_ap_axi] = &ap_axi.common.hw, + [clk_sdio0_2x] = &sdio0_2x.common.hw, + [clk_sdio1_2x] = &sdio1_2x.common.hw, + [clk_sdio2_2x] = &sdio2_2x.common.hw, + [clk_emmc_2x] = &emmc_2x.common.hw, + [clk_dpu] = &dpu_clk.common.hw, + [clk_dpu_dpi] = &dpu_dpi.common.hw, + [clk_otg_ref] = &otg_ref_clk.common.hw, + [clk_sdphy_apb] = &sdphy_apb_clk.common.hw, + [clk_alg_io_apb] = &alg_io_apb_clk.common.hw, + [clk_gpu_core] = &gpu_core.common.hw, + [clk_gpu_soc] = &gpu_soc.common.hw, + [clk_mm_emc] = &mm_emc.common.hw, + [clk_mm_ahb] = &mm_ahb.common.hw, + [clk_bpc] = &bpc_clk.common.hw, + [clk_dcam_if] = &dcam_if_clk.common.hw, + [clk_isp] = &isp_clk.common.hw, + [clk_jpg] = &jpg_clk.common.hw, + [clk_cpp] = &cpp_clk.common.hw, + [clk_sensor0] = &sensor0_clk.common.hw, + [clk_sensor1] = &sensor1_clk.common.hw, + [clk_sensor2] = &sensor2_clk.common.hw, + [clk_mm_vemc] = &mm_vemc.common.hw, + [clk_mm_vahb] = &mm_vahb.common.hw, + [clk_vsp] = &clk_vsp.common.hw, + [clk_core0] = &core0_clk.common.hw, + [clk_core1] = &core1_clk.common.hw, + [clk_core2] = &core2_clk.common.hw, + [clk_core3] = &core3_clk.common.hw, + [clk_core4] = &core4_clk.common.hw, + [clk_core5] = &core5_clk.common.hw, + [clk_core6] = &core6_clk.common.hw, + [clk_core7] = &core7_clk.common.hw, + [clk_scu] = &scu_clk.common.hw, + [clk_ace] = &ace_clk.common.hw, + [clk_axi_periph] = &axi_periph_clk.common.hw, + [clk_axi_acp] = &axi_acp_clk.common.hw, + [clk_atb] = &atb_clk.common.hw, + [clk_debug_apb] = &debug_apb_clk.common.hw, + [clk_gic] = &gic_clk.common.hw, + [clk_periph] = &periph_clk.common.hw, + }, + .num = clk_aon_clk_num, +}; + +static const struct sprd_clk_desc sc9863a_aon_clk_desc = { + .clk_clks = sc9863a_aon_clks, + .num_clk_clks = array_size(sc9863a_aon_clks), + .hw_clks = &sc9863a_aon_clk_hws, +}; + +static const struct clk_parent_data ap_apb_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_64m.hw }, + { .hw = &twpll_96m.hw }, + { .hw = &twpll_128m.hw }, +}; +static sprd_mux_clk_data(ap_apb, "ap-apb", ap_apb_parents, 0x20, + 0, 2, sc9863a_mux_flag); + +static const struct clk_parent_data ap_ce_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_256m.hw }, +}; +static sprd_comp_clk_data(ap_ce, "ap-ce", ap_ce_parents, 0x24, + 0, 1, 8, 3, 0); + +static const struct clk_parent_data nandc_ecc_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_256m.hw }, + { .hw = &twpll_307m2.hw }, +}; +static sprd_comp_clk_data(nandc_ecc, "nandc-ecc", nandc_ecc_parents, 0x28, + 0, 2, 8, 3, 0); + +static const struct clk_parent_data nandc_26m_parents[] = { + { .fw_name = "ext-32k" }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(nandc_26m, "nandc-26m", nandc_26m_parents, 0x2c, + 0, 1, sc9863a_mux_flag); +static sprd_mux_clk_data(emmc_32k, "emmc-32k", nandc_26m_parents, 0x30, + 0, 1, sc9863a_mux_flag); +static sprd_mux_clk_data(sdio0_32k, "sdio0-32k", nandc_26m_parents, 0x34, + 0, 1, sc9863a_mux_flag); +static sprd_mux_clk_data(sdio1_32k, "sdio1-32k", nandc_26m_parents, 0x38, + 0, 1, sc9863a_mux_flag); +static sprd_mux_clk_data(sdio2_32k, "sdio2-32k", nandc_26m_parents, 0x3c, + 0, 1, sc9863a_mux_flag); + +static sprd_gate_clk_hw(otg_utmi, "otg-utmi", &aon_apb.common.hw, 0x40, + bit(16), 0, 0); + +static const struct clk_parent_data ap_uart_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_48m.hw }, + { .hw = &twpll_51m2.hw }, + { .hw = &twpll_96m.hw }, +}; +static sprd_comp_clk_data(ap_uart0, "ap-uart0", ap_uart_parents, 0x44, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_uart1, "ap-uart1", ap_uart_parents, 0x48, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_uart2, "ap-uart2", ap_uart_parents, 0x4c, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_uart3, "ap-uart3", ap_uart_parents, 0x50, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_uart4, "ap-uart4", ap_uart_parents, 0x54, + 0, 2, 8, 3, 0); + +static const struct clk_parent_data i2c_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_48m.hw }, + { .hw = &twpll_51m2.hw }, + { .hw = &twpll_153m6.hw }, +}; +static sprd_comp_clk_data(ap_i2c0, "ap-i2c0", i2c_parents, 0x58, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_i2c1, "ap-i2c1", i2c_parents, 0x5c, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_i2c2, "ap-i2c2", i2c_parents, 0x60, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_i2c3, "ap-i2c3", i2c_parents, 0x64, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_i2c4, "ap-i2c4", i2c_parents, 0x68, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_i2c5, "ap-i2c5", i2c_parents, 0x6c, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_i2c6, "ap-i2c6", i2c_parents, 0x70, + 0, 2, 8, 3, 0); + +static const struct clk_parent_data spi_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, + { .hw = &twpll_192m.hw }, +}; +static sprd_comp_clk_data(ap_spi0, "ap-spi0", spi_parents, 0x74, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_spi1, "ap-spi1", spi_parents, 0x78, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_spi2, "ap-spi2", spi_parents, 0x7c, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_spi3, "ap-spi3", spi_parents, 0x80, + 0, 2, 8, 3, 0); + +static const struct clk_parent_data iis_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_128m.hw }, + { .hw = &twpll_153m6.hw }, +}; +static sprd_comp_clk_data(ap_iis0, "ap-iis0", iis_parents, 0x84, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_iis1, "ap-iis1", iis_parents, 0x88, + 0, 2, 8, 3, 0); +static sprd_comp_clk_data(ap_iis2, "ap-iis2", iis_parents, 0x8c, + 0, 2, 8, 3, 0); + +static const struct clk_parent_data sim0_parents[] = { + { .fw_name = "ext-26m" }, + { .hw = &twpll_51m2.hw }, + { .hw = &twpll_64m.hw }, + { .hw = &twpll_96m.hw }, + { .hw = &twpll_128m.hw }, +}; +static sprd_comp_clk_data(sim0, "sim0", sim0_parents, 0x90, + 0, 3, 8, 3, 0); + +static const struct clk_parent_data sim0_32k_parents[] = { + { .fw_name = "ext-32k" }, + { .fw_name = "ext-26m" }, +}; +static sprd_mux_clk_data(sim0_32k, "sim0-32k", sim0_32k_parents, 0x94, + 0, 1, sc9863a_mux_flag); + +static struct sprd_clk_common *sc9863a_ap_clks[] = { + /* address base is 0x21500000 */ + &ap_apb.common, + &ap_ce.common, + &nandc_ecc.common, + &nandc_26m.common, + &emmc_32k.common, + &sdio0_32k.common, + &sdio1_32k.common, + &sdio2_32k.common, + &otg_utmi.common, + &ap_uart0.common, + &ap_uart1.common, + &ap_uart2.common, + &ap_uart3.common, + &ap_uart4.common, + &ap_i2c0.common, + &ap_i2c1.common, + &ap_i2c2.common, + &ap_i2c3.common, + &ap_i2c4.common, + &ap_i2c5.common, + &ap_i2c6.common, + &ap_spi0.common, + &ap_spi1.common, + &ap_spi2.common, + &ap_spi3.common, + &ap_iis0.common, + &ap_iis1.common, + &ap_iis2.common, + &sim0.common, + &sim0_32k.common, +}; + +static struct clk_hw_onecell_data sc9863a_ap_clk_hws = { + .hws = { + [clk_ap_apb] = &ap_apb.common.hw, + [clk_ap_ce] = &ap_ce.common.hw, + [clk_nandc_ecc] = &nandc_ecc.common.hw, + [clk_nandc_26m] = &nandc_26m.common.hw, + [clk_emmc_32k] = &emmc_32k.common.hw, + [clk_sdio0_32k] = &sdio0_32k.common.hw, + [clk_sdio1_32k] = &sdio1_32k.common.hw, + [clk_sdio2_32k] = &sdio2_32k.common.hw, + [clk_otg_utmi] = &otg_utmi.common.hw, + [clk_ap_uart0] = &ap_uart0.common.hw, + [clk_ap_uart1] = &ap_uart1.common.hw, + [clk_ap_uart2] = &ap_uart2.common.hw, + [clk_ap_uart3] = &ap_uart3.common.hw, + [clk_ap_uart4] = &ap_uart4.common.hw, + [clk_ap_i2c0] = &ap_i2c0.common.hw, + [clk_ap_i2c1] = &ap_i2c1.common.hw, + [clk_ap_i2c2] = &ap_i2c2.common.hw, + [clk_ap_i2c3] = &ap_i2c3.common.hw, + [clk_ap_i2c4] = &ap_i2c4.common.hw, + [clk_ap_i2c5] = &ap_i2c5.common.hw, + [clk_ap_i2c6] = &ap_i2c6.common.hw, + [clk_ap_spi0] = &ap_spi0.common.hw, + [clk_ap_spi1] = &ap_spi1.common.hw, + [clk_ap_spi2] = &ap_spi2.common.hw, + [clk_ap_spi3] = &ap_spi3.common.hw, + [clk_ap_iis0] = &ap_iis0.common.hw, + [clk_ap_iis1] = &ap_iis1.common.hw, + [clk_ap_iis2] = &ap_iis2.common.hw, + [clk_sim0] = &sim0.common.hw, + [clk_sim0_32k] = &sim0_32k.common.hw, + }, + .num = clk_ap_clk_num, +}; + +static const struct sprd_clk_desc sc9863a_ap_clk_desc = { + .clk_clks = sc9863a_ap_clks, + .num_clk_clks = array_size(sc9863a_ap_clks), + .hw_clks = &sc9863a_ap_clk_hws, +}; + +static sprd_sc_gate_clk_hw(otg_eb, "otg-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(4), 0, 0); +static sprd_sc_gate_clk_hw(dma_eb, "dma-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(5), 0, 0); +static sprd_sc_gate_clk_hw(ce_eb, "ce-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(6), 0, 0); +static sprd_sc_gate_clk_hw(nandc_eb, "nandc-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(7), 0, 0); +static sprd_sc_gate_clk_hw(sdio0_eb, "sdio0-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(8), 0, 0); +static sprd_sc_gate_clk_hw(sdio1_eb, "sdio1-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(9), 0, 0); +static sprd_sc_gate_clk_hw(sdio2_eb, "sdio2-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(10), 0, 0); +static sprd_sc_gate_clk_hw(emmc_eb, "emmc-eb", &ap_axi.common.hw, 0x0, 0x1000, + bit(11), 0, 0); +static sprd_sc_gate_clk_hw(emmc_32k_eb, "emmc-32k-eb", &ap_axi.common.hw, 0x0, + 0x1000, bit(27), 0, 0); +static sprd_sc_gate_clk_hw(sdio0_32k_eb, "sdio0-32k-eb", &ap_axi.common.hw, 0x0, + 0x1000, bit(28), 0, 0); +static sprd_sc_gate_clk_hw(sdio1_32k_eb, "sdio1-32k-eb", &ap_axi.common.hw, 0x0, + 0x1000, bit(29), 0, 0); +static sprd_sc_gate_clk_hw(sdio2_32k_eb, "sdio2-32k-eb", &ap_axi.common.hw, 0x0, + 0x1000, bit(30), 0, 0); +static sprd_sc_gate_clk_hw(nandc_26m_eb, "nandc-26m-eb", &ap_axi.common.hw, 0x0, + 0x1000, bit(31), 0, 0); +static sprd_sc_gate_clk_hw(dma_eb2, "dma-eb2", &ap_axi.common.hw, 0x18, + 0x1000, bit(0), 0, 0); +static sprd_sc_gate_clk_hw(ce_eb2, "ce-eb2", &ap_axi.common.hw, 0x18, + 0x1000, bit(1), 0, 0); + +static struct sprd_clk_common *sc9863a_apahb_gate_clks[] = { + /* address base is 0x20e00000 */ + &otg_eb.common, + &dma_eb.common, + &ce_eb.common, + &nandc_eb.common, + &sdio0_eb.common, + &sdio1_eb.common, + &sdio2_eb.common, + &emmc_eb.common, + &emmc_32k_eb.common, + &sdio0_32k_eb.common, + &sdio1_32k_eb.common, + &sdio2_32k_eb.common, + &nandc_26m_eb.common, + &dma_eb2.common, + &ce_eb2.common, +}; + +static struct clk_hw_onecell_data sc9863a_apahb_gate_hws = { + .hws = { + [clk_otg_eb] = &otg_eb.common.hw, + [clk_dma_eb] = &dma_eb.common.hw, + [clk_ce_eb] = &ce_eb.common.hw, + [clk_nandc_eb] = &nandc_eb.common.hw, + [clk_sdio0_eb] = &sdio0_eb.common.hw, + [clk_sdio1_eb] = &sdio1_eb.common.hw, + [clk_sdio2_eb] = &sdio2_eb.common.hw, + [clk_emmc_eb] = &emmc_eb.common.hw, + [clk_emmc_32k_eb] = &emmc_32k_eb.common.hw, + [clk_sdio0_32k_eb] = &sdio0_32k_eb.common.hw, + [clk_sdio1_32k_eb] = &sdio1_32k_eb.common.hw, + [clk_sdio2_32k_eb] = &sdio2_32k_eb.common.hw, + [clk_nandc_26m_eb] = &nandc_26m_eb.common.hw, + [clk_dma_eb2] = &dma_eb2.common.hw, + [clk_ce_eb2] = &ce_eb2.common.hw, + }, + .num = clk_ap_ahb_gate_num, +}; + +static const struct sprd_clk_desc sc9863a_apahb_gate_desc = { + .clk_clks = sc9863a_apahb_gate_clks, + .num_clk_clks = array_size(sc9863a_apahb_gate_clks), + .hw_clks = &sc9863a_apahb_gate_hws, +}; + +/* aon gate clocks */ +static sprd_sc_gate_clk_hw(gpio_eb, "gpio-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(3), 0, 0); +static sprd_sc_gate_clk_hw(pwm0_eb, "pwm0-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(4), 0, 0); +static sprd_sc_gate_clk_hw(pwm1_eb, "pwm1-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(5), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(pwm2_eb, "pwm2-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(6), 0, 0); +static sprd_sc_gate_clk_hw(pwm3_eb, "pwm3-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(7), 0, 0); +static sprd_sc_gate_clk_hw(kpd_eb, "kpd-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(8), 0, 0); +static sprd_sc_gate_clk_hw(aon_syst_eb, "aon-syst-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(9), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_syst_eb, "ap-syst-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(10), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(aon_tmr_eb, "aon-tmr-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(11), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(efuse_eb, "efuse-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(13), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(eic_eb, "eic-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(14), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(intc_eb, "intc-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(15), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(adi_eb, "adi-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(16), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(audif_eb, "audif-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(17), 0, 0); +static sprd_sc_gate_clk_hw(aud_eb, "aud-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(18), 0, 0); +static sprd_sc_gate_clk_hw(vbc_eb, "vbc-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(19), 0, 0); +static sprd_sc_gate_clk_hw(pin_eb, "pin-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(20), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_wdg_eb, "ap-wdg-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(24), 0, 0); +static sprd_sc_gate_clk_hw(mm_eb, "mm-eb", &aon_apb.common.hw, 0x0, + 0x1000, bit(25), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(aon_apb_ckg_eb, "aon-apb-ckg-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(26), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ca53_ts0_eb, "ca53-ts0-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(28), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ca53_ts1_eb, "ca53-ts1-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(29), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ca53_dap_eb, "ca53-dap-eb", &aon_apb.common.hw, + 0x0, 0x1000, bit(30), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(pmu_eb, "pmu-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(0), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(thm_eb, "thm-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(1), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(aux0_eb, "aux0-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(2), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(aux1_eb, "aux1-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(3), 0, 0); +static sprd_sc_gate_clk_hw(aux2_eb, "aux2-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(4), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(probe_eb, "probe-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(5), 0, 0); +static sprd_sc_gate_clk_hw(emc_ref_eb, "emc-ref-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(7), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ca53_wdg_eb, "ca53-wdg-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(8), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_tmr1_eb, "ap-tmr1-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(9), 0, 0); +static sprd_sc_gate_clk_hw(ap_tmr2_eb, "ap-tmr2-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(10), 0, 0); +static sprd_sc_gate_clk_hw(disp_emc_eb, "disp-emc-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(11), 0, 0); +static sprd_sc_gate_clk_hw(zip_emc_eb, "zip-emc-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(12), 0, 0); +static sprd_sc_gate_clk_hw(gsp_emc_eb, "gsp-emc-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(13), 0, 0); +static sprd_sc_gate_clk_hw(mm_vsp_eb, "mm-vsp-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(14), 0, 0); +static sprd_sc_gate_clk_hw(mdar_eb, "mdar-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(17), 0, 0); +static sprd_sc_gate_clk_hw(rtc4m0_cal_eb, "rtc4m0-cal-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(18), 0, 0); +static sprd_sc_gate_clk_hw(rtc4m1_cal_eb, "rtc4m1-cal-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(19), 0, 0); +static sprd_sc_gate_clk_hw(djtag_eb, "djtag-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(20), 0, 0); +static sprd_sc_gate_clk_hw(mbox_eb, "mbox-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(21), 0, 0); +static sprd_sc_gate_clk_hw(aon_dma_eb, "aon-dma-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(22), 0, 0); +static sprd_sc_gate_clk_hw(aon_apb_def_eb, "aon-apb-def-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(25), 0, 0); +static sprd_sc_gate_clk_hw(ca5_ts0_eb, "ca5-ts0-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(26), 0, 0); +static sprd_sc_gate_clk_hw(dbg_eb, "dbg-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(28), 0, 0); +static sprd_sc_gate_clk_hw(dbg_emc_eb, "dbg-emc-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(29), 0, 0); +static sprd_sc_gate_clk_hw(cross_trig_eb, "cross-trig-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(30), 0, 0); +static sprd_sc_gate_clk_hw(serdes_dphy_eb, "serdes-dphy-eb", &aon_apb.common.hw, + 0x4, 0x1000, bit(31), 0, 0); +static sprd_sc_gate_clk_hw(arch_rtc_eb, "arch-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(0), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(kpd_rtc_eb, "kpd-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(1), 0, 0); +static sprd_sc_gate_clk_hw(aon_syst_rtc_eb, "aon-syst-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(2), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_syst_rtc_eb, "ap-syst-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(3), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(aon_tmr_rtc_eb, "aon-tmr-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(4), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_tmr0_rtc_eb, "ap-tmr0-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(5), 0, 0); +static sprd_sc_gate_clk_hw(eic_rtc_eb, "eic-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(6), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(eic_rtcdv5_eb, "eic-rtcdv5-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(7), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_wdg_rtc_eb, "ap-wdg-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(8), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ca53_wdg_rtc_eb, "ca53-wdg-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(9), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(thm_rtc_eb, "thm-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(10), 0, 0); +static sprd_sc_gate_clk_hw(athma_rtc_eb, "athma-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(11), 0, 0); +static sprd_sc_gate_clk_hw(gthma_rtc_eb, "gthma-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(12), 0, 0); +static sprd_sc_gate_clk_hw(athma_rtc_a_eb, "athma-rtc-a-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(13), 0, 0); +static sprd_sc_gate_clk_hw(gthma_rtc_a_eb, "gthma-rtc-a-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(14), 0, 0); +static sprd_sc_gate_clk_hw(ap_tmr1_rtc_eb, "ap-tmr1-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(15), 0, 0); +static sprd_sc_gate_clk_hw(ap_tmr2_rtc_eb, "ap-tmr2-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(16), 0, 0); +static sprd_sc_gate_clk_hw(dxco_lc_rtc_eb, "dxco-lc-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(17), 0, 0); +static sprd_sc_gate_clk_hw(bb_cal_rtc_eb, "bb-cal-rtc-eb", &aon_apb.common.hw, + 0x10, 0x1000, bit(18), 0, 0); +static sprd_sc_gate_clk_hw(gpu_eb, "gpu-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(0), 0, 0); +static sprd_sc_gate_clk_hw(disp_eb, "disp-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(2), 0, 0); +static sprd_sc_gate_clk_hw(mm_emc_eb, "mm-emc-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(3), 0, 0); +static sprd_sc_gate_clk_hw(power_cpu_eb, "power-cpu-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(10), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(hw_i2c_eb, "hw-i2c-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(11), 0, 0); +static sprd_sc_gate_clk_hw(mm_vsp_emc_eb, "mm-vsp-emc-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(14), 0, 0); +static sprd_sc_gate_clk_hw(vsp_eb, "vsp-eb", &aon_apb.common.hw, 0x50, + 0x1000, bit(16), 0, 0); +static sprd_sc_gate_clk_hw(cssys_eb, "cssys-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(4), 0, 0); +static sprd_sc_gate_clk_hw(dmc_eb, "dmc-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(5), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(rosc_eb, "rosc-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(7), 0, 0); +static sprd_sc_gate_clk_hw(s_d_cfg_eb, "s-d-cfg-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(8), 0, 0); +static sprd_sc_gate_clk_hw(s_d_ref_eb, "s-d-ref-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(9), 0, 0); +static sprd_sc_gate_clk_hw(b_dma_eb, "b-dma-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(10), 0, 0); +static sprd_sc_gate_clk_hw(anlg_eb, "anlg-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(11), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(anlg_apb_eb, "anlg-apb-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(13), 0, 0); +static sprd_sc_gate_clk_hw(bsmtmr_eb, "bsmtmr-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(14), 0, 0); +static sprd_sc_gate_clk_hw(ap_axi_eb, "ap-axi-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(15), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_intc0_eb, "ap-intc0-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(16), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_intc1_eb, "ap-intc1-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(17), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_intc2_eb, "ap-intc2-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(18), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_intc3_eb, "ap-intc3-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(19), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_intc4_eb, "ap-intc4-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(20), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(ap_intc5_eb, "ap-intc5-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(21), clk_ignore_unused, 0); +static sprd_sc_gate_clk_hw(scc_eb, "scc-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(22), 0, 0); +static sprd_sc_gate_clk_hw(dphy_cfg_eb, "dphy-cfg-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(23), 0, 0); +static sprd_sc_gate_clk_hw(dphy_ref_eb, "dphy-ref-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(24), 0, 0); +static sprd_sc_gate_clk_hw(cphy_cfg_eb, "cphy-cfg-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(25), 0, 0); +static sprd_sc_gate_clk_hw(otg_ref_eb, "otg-ref-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(26), 0, 0); +static sprd_sc_gate_clk_hw(serdes_eb, "serdes-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(27), 0, 0); +static sprd_sc_gate_clk_hw(aon_ap_emc_eb, "aon-ap-emc-eb", &aon_apb.common.hw, 0xb0, + 0x1000, bit(28), 0, 0); +static struct sprd_clk_common *sc9863a_aonapb_gate_clks[] = { + /* address base is 0x402e0000 */ + &gpio_eb.common, + &pwm0_eb.common, + &pwm1_eb.common, + &pwm2_eb.common, + &pwm3_eb.common, + &kpd_eb.common, + &aon_syst_eb.common, + &ap_syst_eb.common, + &aon_tmr_eb.common, + &efuse_eb.common, + &eic_eb.common, + &intc_eb.common, + &adi_eb.common, + &audif_eb.common, + &aud_eb.common, + &vbc_eb.common, + &pin_eb.common, + &ap_wdg_eb.common, + &mm_eb.common, + &aon_apb_ckg_eb.common, + &ca53_ts0_eb.common, + &ca53_ts1_eb.common, + &ca53_dap_eb.common, + &pmu_eb.common, + &thm_eb.common, + &aux0_eb.common, + &aux1_eb.common, + &aux2_eb.common, + &probe_eb.common, + &emc_ref_eb.common, + &ca53_wdg_eb.common, + &ap_tmr1_eb.common, + &ap_tmr2_eb.common, + &disp_emc_eb.common, + &zip_emc_eb.common, + &gsp_emc_eb.common, + &mm_vsp_eb.common, + &mdar_eb.common, + &rtc4m0_cal_eb.common, + &rtc4m1_cal_eb.common, + &djtag_eb.common, + &mbox_eb.common, + &aon_dma_eb.common, + &aon_apb_def_eb.common, + &ca5_ts0_eb.common, + &dbg_eb.common, + &dbg_emc_eb.common, + &cross_trig_eb.common, + &serdes_dphy_eb.common, + &arch_rtc_eb.common, + &kpd_rtc_eb.common, + &aon_syst_rtc_eb.common, + &ap_syst_rtc_eb.common, + &aon_tmr_rtc_eb.common, + &ap_tmr0_rtc_eb.common, + &eic_rtc_eb.common, + &eic_rtcdv5_eb.common, + &ap_wdg_rtc_eb.common, + &ca53_wdg_rtc_eb.common, + &thm_rtc_eb.common, + &athma_rtc_eb.common, + >hma_rtc_eb.common, + &athma_rtc_a_eb.common, + >hma_rtc_a_eb.common, + &ap_tmr1_rtc_eb.common, + &ap_tmr2_rtc_eb.common, + &dxco_lc_rtc_eb.common, + &bb_cal_rtc_eb.common, + &gpu_eb.common, + &disp_eb.common, + &mm_emc_eb.common, + &power_cpu_eb.common, + &hw_i2c_eb.common, + &mm_vsp_emc_eb.common, + &vsp_eb.common, + &cssys_eb.common, + &dmc_eb.common, + &rosc_eb.common, + &s_d_cfg_eb.common, + &s_d_ref_eb.common, + &b_dma_eb.common, + &anlg_eb.common, + &anlg_apb_eb.common, + &bsmtmr_eb.common, + &ap_axi_eb.common, + &ap_intc0_eb.common, + &ap_intc1_eb.common, + &ap_intc2_eb.common, + &ap_intc3_eb.common, + &ap_intc4_eb.common, + &ap_intc5_eb.common, + &scc_eb.common, + &dphy_cfg_eb.common, + &dphy_ref_eb.common, + &cphy_cfg_eb.common, + &otg_ref_eb.common, + &serdes_eb.common, + &aon_ap_emc_eb.common, +}; + +static struct clk_hw_onecell_data sc9863a_aonapb_gate_hws = { + .hws = { + [clk_gpio_eb] = &gpio_eb.common.hw, + [clk_pwm0_eb] = &pwm0_eb.common.hw, + [clk_pwm1_eb] = &pwm1_eb.common.hw, + [clk_pwm2_eb] = &pwm2_eb.common.hw, + [clk_pwm3_eb] = &pwm3_eb.common.hw, + [clk_kpd_eb] = &kpd_eb.common.hw, + [clk_aon_syst_eb] = &aon_syst_eb.common.hw, + [clk_ap_syst_eb] = &ap_syst_eb.common.hw, + [clk_aon_tmr_eb] = &aon_tmr_eb.common.hw, + [clk_efuse_eb] = &efuse_eb.common.hw, + [clk_eic_eb] = &eic_eb.common.hw, + [clk_intc_eb] = &intc_eb.common.hw, + [clk_adi_eb] = &adi_eb.common.hw, + [clk_audif_eb] = &audif_eb.common.hw, + [clk_aud_eb] = &aud_eb.common.hw, + [clk_vbc_eb] = &vbc_eb.common.hw, + [clk_pin_eb] = &pin_eb.common.hw, + [clk_ap_wdg_eb] = &ap_wdg_eb.common.hw, + [clk_mm_eb] = &mm_eb.common.hw, + [clk_aon_apb_ckg_eb] = &aon_apb_ckg_eb.common.hw, + [clk_ca53_ts0_eb] = &ca53_ts0_eb.common.hw, + [clk_ca53_ts1_eb] = &ca53_ts1_eb.common.hw, + [clk_cs53_dap_eb] = &ca53_dap_eb.common.hw, + [clk_pmu_eb] = &pmu_eb.common.hw, + [clk_thm_eb] = &thm_eb.common.hw, + [clk_aux0_eb] = &aux0_eb.common.hw, + [clk_aux1_eb] = &aux1_eb.common.hw, + [clk_aux2_eb] = &aux2_eb.common.hw, + [clk_probe_eb] = &probe_eb.common.hw, + [clk_emc_ref_eb] = &emc_ref_eb.common.hw, + [clk_ca53_wdg_eb] = &ca53_wdg_eb.common.hw, + [clk_ap_tmr1_eb] = &ap_tmr1_eb.common.hw, + [clk_ap_tmr2_eb] = &ap_tmr2_eb.common.hw, + [clk_disp_emc_eb] = &disp_emc_eb.common.hw, + [clk_zip_emc_eb] = &zip_emc_eb.common.hw, + [clk_gsp_emc_eb] = &gsp_emc_eb.common.hw, + [clk_mm_vsp_eb] = &mm_vsp_eb.common.hw, + [clk_mdar_eb] = &mdar_eb.common.hw, + [clk_rtc4m0_cal_eb] = &rtc4m0_cal_eb.common.hw, + [clk_rtc4m1_cal_eb] = &rtc4m1_cal_eb.common.hw, + [clk_djtag_eb] = &djtag_eb.common.hw, + [clk_mbox_eb] = &mbox_eb.common.hw, + [clk_aon_dma_eb] = &aon_dma_eb.common.hw, + [clk_aon_apb_def_eb] = &aon_apb_def_eb.common.hw, + [clk_ca5_ts0_eb] = &ca5_ts0_eb.common.hw, + [clk_dbg_eb] = &dbg_eb.common.hw, + [clk_dbg_emc_eb] = &dbg_emc_eb.common.hw, + [clk_cross_trig_eb] = &cross_trig_eb.common.hw, + [clk_serdes_dphy_eb] = &serdes_dphy_eb.common.hw, + [clk_arch_rtc_eb] = &arch_rtc_eb.common.hw, + [clk_kpd_rtc_eb] = &kpd_rtc_eb.common.hw, + [clk_aon_syst_rtc_eb] = &aon_syst_rtc_eb.common.hw, + [clk_ap_syst_rtc_eb] = &ap_syst_rtc_eb.common.hw, + [clk_aon_tmr_rtc_eb] = &aon_tmr_rtc_eb.common.hw, + [clk_ap_tmr0_rtc_eb] = &ap_tmr0_rtc_eb.common.hw, + [clk_eic_rtc_eb] = &eic_rtc_eb.common.hw, + [clk_eic_rtcdv5_eb] = &eic_rtcdv5_eb.common.hw, + [clk_ap_wdg_rtc_eb] = &ap_wdg_rtc_eb.common.hw, + [clk_ca53_wdg_rtc_eb] = &ca53_wdg_rtc_eb.common.hw, + [clk_thm_rtc_eb] = &thm_rtc_eb.common.hw, + [clk_athma_rtc_eb] = &athma_rtc_eb.common.hw, + [clk_gthma_rtc_eb] = >hma_rtc_eb.common.hw, + [clk_athma_rtc_a_eb] = &athma_rtc_a_eb.common.hw, + [clk_gthma_rtc_a_eb] = >hma_rtc_a_eb.common.hw, + [clk_ap_tmr1_rtc_eb] = &ap_tmr1_rtc_eb.common.hw, + [clk_ap_tmr2_rtc_eb] = &ap_tmr2_rtc_eb.common.hw, + [clk_dxco_lc_rtc_eb] = &dxco_lc_rtc_eb.common.hw, + [clk_bb_cal_rtc_eb] = &bb_cal_rtc_eb.common.hw, + [clk_gnu_eb] = &gpu_eb.common.hw, + [clk_disp_eb] = &disp_eb.common.hw, + [clk_mm_emc_eb] = &mm_emc_eb.common.hw, + [clk_power_cpu_eb] = &power_cpu_eb.common.hw, + [clk_hw_i2c_eb] = &hw_i2c_eb.common.hw, + [clk_mm_vsp_emc_eb] = &mm_vsp_emc_eb.common.hw, + [clk_vsp_eb] = &vsp_eb.common.hw, + [clk_cssys_eb] = &cssys_eb.common.hw, + [clk_dmc_eb] = &dmc_eb.common.hw, + [clk_rosc_eb] = &rosc_eb.common.hw, + [clk_s_d_cfg_eb] = &s_d_cfg_eb.common.hw, + [clk_s_d_ref_eb] = &s_d_ref_eb.common.hw, + [clk_b_dma_eb] = &b_dma_eb.common.hw, + [clk_anlg_eb] = &anlg_eb.common.hw, + [clk_anlg_apb_eb] = &anlg_apb_eb.common.hw, + [clk_bsmtmr_eb] = &bsmtmr_eb.common.hw, + [clk_ap_axi_eb] = &ap_axi_eb.common.hw, + [clk_ap_intc0_eb] = &ap_intc0_eb.common.hw, + [clk_ap_intc1_eb] = &ap_intc1_eb.common.hw, + [clk_ap_intc2_eb] = &ap_intc2_eb.common.hw, + [clk_ap_intc3_eb] = &ap_intc3_eb.common.hw, + [clk_ap_intc4_eb] = &ap_intc4_eb.common.hw, + [clk_ap_intc5_eb] = &ap_intc5_eb.common.hw, + [clk_scc_eb] = &scc_eb.common.hw, + [clk_dphy_cfg_eb] = &dphy_cfg_eb.common.hw, + [clk_dphy_ref_eb] = &dphy_ref_eb.common.hw, + [clk_cphy_cfg_eb] = &cphy_cfg_eb.common.hw, + [clk_otg_ref_eb] = &otg_ref_eb.common.hw, + [clk_serdes_eb] = &serdes_eb.common.hw, + [clk_aon_ap_emc_eb] = &aon_ap_emc_eb.common.hw, + }, + .num = clk_aon_apb_gate_num, +}; + +static const struct sprd_clk_desc sc9863a_aonapb_gate_desc = { + .clk_clks = sc9863a_aonapb_gate_clks, + .num_clk_clks = array_size(sc9863a_aonapb_gate_clks), + .hw_clks = &sc9863a_aonapb_gate_hws, +}; + +/* mm gate clocks */ +static sprd_sc_gate_clk_hw(mahb_ckg_eb, "mahb-ckg-eb", &mm_ahb.common.hw, 0x0, 0x1000, + bit(0), 0, 0); +static sprd_sc_gate_clk_hw(mdcam_eb, "mdcam-eb", &mm_ahb.common.hw, 0x0, 0x1000, + bit(1), 0, 0); +static sprd_sc_gate_clk_hw(misp_eb, "misp-eb", &mm_ahb.common.hw, 0x0, 0x1000, + bit(2), 0, 0); +static sprd_sc_gate_clk_hw(mahbcsi_eb, "mahbcsi-eb", &mm_ahb.common.hw, 0x0, 0x1000, + bit(3), 0, 0); +static sprd_sc_gate_clk_hw(mcsi_s_eb, "mcsi-s-eb", &mm_ahb.common.hw, 0x0, 0x1000, + bit(4), 0, 0); +static sprd_sc_gate_clk_hw(mcsi_t_eb, "mcsi-t-eb", &mm_ahb.common.hw, 0x0, 0x1000, + bit(5), 0, 0); +static sprd_gate_clk_hw(dcam_axi_eb, "dcam-axi-eb", &mm_ahb.common.hw, 0x8, + bit(0), 0, 0); +static sprd_gate_clk_hw(isp_axi_eb, "isp-axi-eb", &mm_ahb.common.hw, 0x8, + bit(1), 0, 0); +static sprd_gate_clk_hw(mcsi_eb, "mcsi-eb", &mm_ahb.common.hw, 0x8, + bit(2), 0, 0); +static sprd_gate_clk_hw(mcsi_s_ckg_eb, "mcsi-s-ckg-eb", &mm_ahb.common.hw, 0x8, + bit(3), 0, 0); +static sprd_gate_clk_hw(mcsi_t_ckg_eb, "mcsi-t-ckg-eb", &mm_ahb.common.hw, 0x8, + bit(4), 0, 0); +static sprd_gate_clk_hw(sensor0_eb, "sensor0-eb", &mm_ahb.common.hw, 0x8, + bit(5), 0, 0); +static sprd_gate_clk_hw(sensor1_eb, "sensor1-eb", &mm_ahb.common.hw, 0x8, + bit(6), 0, 0); +static sprd_gate_clk_hw(sensor2_eb, "sensor2-eb", &mm_ahb.common.hw, 0x8, + bit(7), 0, 0); +static sprd_gate_clk_hw(mcphy_cfg_eb, "mcphy-cfg-eb", &mm_ahb.common.hw, 0x8, + bit(8), 0, 0); + +static struct sprd_clk_common *sc9863a_mm_gate_clks[] = { + /* address base is 0x60800000 */ + &mahb_ckg_eb.common, + &mdcam_eb.common, + &misp_eb.common, + &mahbcsi_eb.common, + &mcsi_s_eb.common, + &mcsi_t_eb.common, + &dcam_axi_eb.common, + &isp_axi_eb.common, + &mcsi_eb.common, + &mcsi_s_ckg_eb.common, + &mcsi_t_ckg_eb.common, + &sensor0_eb.common, + &sensor1_eb.common, + &sensor2_eb.common, + &mcphy_cfg_eb.common, +}; + +static struct clk_hw_onecell_data sc9863a_mm_gate_hws = { + .hws = { + [clk_mahb_ckg_eb] = &mahb_ckg_eb.common.hw, + [clk_mdcam_eb] = &mdcam_eb.common.hw, + [clk_misp_eb] = &misp_eb.common.hw, + [clk_mahbcsi_eb] = &mahbcsi_eb.common.hw, + [clk_mcsi_s_eb] = &mcsi_s_eb.common.hw, + [clk_mcsi_t_eb] = &mcsi_t_eb.common.hw, + [clk_dcam_axi_eb] = &dcam_axi_eb.common.hw, + [clk_isp_axi_eb] = &isp_axi_eb.common.hw, + [clk_mcsi_eb] = &mcsi_eb.common.hw, + [clk_mcsi_s_ckg_eb] = &mcsi_s_ckg_eb.common.hw, + [clk_mcsi_t_ckg_eb] = &mcsi_t_ckg_eb.common.hw, + [clk_sensor0_eb] = &sensor0_eb.common.hw, + [clk_sensor1_eb] = &sensor1_eb.common.hw, + [clk_sensor2_eb] = &sensor2_eb.common.hw, + [clk_mcphy_cfg_eb] = &mcphy_cfg_eb.common.hw, + }, + .num = clk_mm_gate_num, +}; + +static const struct sprd_clk_desc sc9863a_mm_gate_desc = { + .clk_clks = sc9863a_mm_gate_clks, + .num_clk_clks = array_size(sc9863a_mm_gate_clks), + .hw_clks = &sc9863a_mm_gate_hws, +}; + +static sprd_sc_gate_clk_fw_name(sim0_eb, "sim0-eb", "ext-26m", 0x0, + 0x1000, bit(0), 0, 0); +static sprd_sc_gate_clk_fw_name(iis0_eb, "iis0-eb", "ext-26m", 0x0, + 0x1000, bit(1), 0, 0); +static sprd_sc_gate_clk_fw_name(iis1_eb, "iis1-eb", "ext-26m", 0x0, + 0x1000, bit(2), 0, 0); +static sprd_sc_gate_clk_fw_name(iis2_eb, "iis2-eb", "ext-26m", 0x0, + 0x1000, bit(3), 0, 0); +static sprd_sc_gate_clk_fw_name(spi0_eb, "spi0-eb", "ext-26m", 0x0, + 0x1000, bit(5), 0, 0); +static sprd_sc_gate_clk_fw_name(spi1_eb, "spi1-eb", "ext-26m", 0x0, + 0x1000, bit(6), 0, 0); +static sprd_sc_gate_clk_fw_name(spi2_eb, "spi2-eb", "ext-26m", 0x0, + 0x1000, bit(7), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c0_eb, "i2c0-eb", "ext-26m", 0x0, + 0x1000, bit(8), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c1_eb, "i2c1-eb", "ext-26m", 0x0, + 0x1000, bit(9), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c2_eb, "i2c2-eb", "ext-26m", 0x0, + 0x1000, bit(10), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c3_eb, "i2c3-eb", "ext-26m", 0x0, + 0x1000, bit(11), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c4_eb, "i2c4-eb", "ext-26m", 0x0, + 0x1000, bit(12), 0, 0); +static sprd_sc_gate_clk_fw_name(uart0_eb, "uart0-eb", "ext-26m", 0x0, + 0x1000, bit(13), 0, 0); +static sprd_sc_gate_clk_fw_name(uart1_eb, "uart1-eb", "ext-26m", 0x0, + 0x1000, bit(14), 0, 0); +static sprd_sc_gate_clk_fw_name(uart2_eb, "uart2-eb", "ext-26m", 0x0, + 0x1000, bit(15), 0, 0); +static sprd_sc_gate_clk_fw_name(uart3_eb, "uart3-eb", "ext-26m", 0x0, + 0x1000, bit(16), 0, 0); +static sprd_sc_gate_clk_fw_name(uart4_eb, "uart4-eb", "ext-26m", 0x0, + 0x1000, bit(17), 0, 0); +static sprd_sc_gate_clk_fw_name(sim0_32k_eb, "sim0_32k-eb", "ext-26m", 0x0, + 0x1000, bit(18), 0, 0); +static sprd_sc_gate_clk_fw_name(spi3_eb, "spi3-eb", "ext-26m", 0x0, + 0x1000, bit(19), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c5_eb, "i2c5-eb", "ext-26m", 0x0, + 0x1000, bit(20), 0, 0); +static sprd_sc_gate_clk_fw_name(i2c6_eb, "i2c6-eb", "ext-26m", 0x0, + 0x1000, bit(21), 0, 0); + +static struct sprd_clk_common *sc9863a_apapb_gate[] = { + /* address base is 0x71300000 */ + &sim0_eb.common, + &iis0_eb.common, + &iis1_eb.common, + &iis2_eb.common, + &spi0_eb.common, + &spi1_eb.common, + &spi2_eb.common, + &i2c0_eb.common, + &i2c1_eb.common, + &i2c2_eb.common, + &i2c3_eb.common, + &i2c4_eb.common, + &uart0_eb.common, + &uart1_eb.common, + &uart2_eb.common, + &uart3_eb.common, + &uart4_eb.common, + &sim0_32k_eb.common, + &spi3_eb.common, + &i2c5_eb.common, + &i2c6_eb.common, +}; + +static struct clk_hw_onecell_data sc9863a_apapb_gate_hws = { + .hws = { + [clk_sim0_eb] = &sim0_eb.common.hw, + [clk_iis0_eb] = &iis0_eb.common.hw, + [clk_iis1_eb] = &iis1_eb.common.hw, + [clk_iis2_eb] = &iis2_eb.common.hw, + [clk_spi0_eb] = &spi0_eb.common.hw, + [clk_spi1_eb] = &spi1_eb.common.hw, + [clk_spi2_eb] = &spi2_eb.common.hw, + [clk_i2c0_eb] = &i2c0_eb.common.hw, + [clk_i2c1_eb] = &i2c1_eb.common.hw, + [clk_i2c2_eb] = &i2c2_eb.common.hw, + [clk_i2c3_eb] = &i2c3_eb.common.hw, + [clk_i2c4_eb] = &i2c4_eb.common.hw, + [clk_uart0_eb] = &uart0_eb.common.hw, + [clk_uart1_eb] = &uart1_eb.common.hw, + [clk_uart2_eb] = &uart2_eb.common.hw, + [clk_uart3_eb] = &uart3_eb.common.hw, + [clk_uart4_eb] = &uart4_eb.common.hw, + [clk_sim0_32k_eb] = &sim0_32k_eb.common.hw, + [clk_spi3_eb] = &spi3_eb.common.hw, + [clk_i2c5_eb] = &i2c5_eb.common.hw, + [clk_i2c6_eb] = &i2c6_eb.common.hw, + }, + .num = clk_ap_apb_gate_num, +}; + +static const struct sprd_clk_desc sc9863a_apapb_gate_desc = { + .clk_clks = sc9863a_apapb_gate, + .num_clk_clks = array_size(sc9863a_apapb_gate), + .hw_clks = &sc9863a_apapb_gate_hws, +}; + +static const struct of_device_id sprd_sc9863a_clk_ids[] = { + { .compatible = "sprd,sc9863a-ap-clk", /* 0x21500000 */ + .data = &sc9863a_ap_clk_desc }, + { .compatible = "sprd,sc9863a-pmu-gate", /* 0x402b0000 */ + .data = &sc9863a_pmu_gate_desc }, + { .compatible = "sprd,sc9863a-pll", /* 0x40353000 */ + .data = &sc9863a_pll_desc }, + { .compatible = "sprd,sc9863a-mpll", /* 0x40359000 */ + .data = &sc9863a_mpll_desc }, + { .compatible = "sprd,sc9863a-rpll", /* 0x4035c000 */ + .data = &sc9863a_rpll_desc }, + { .compatible = "sprd,sc9863a-dpll", /* 0x40363000 */ + .data = &sc9863a_dpll_desc }, + { .compatible = "sprd,sc9863a-aon-clk", /* 0x402d0000 */ + .data = &sc9863a_aon_clk_desc }, + { .compatible = "sprd,sc9863a-apahb-gate", /* 0x20e00000 */ + .data = &sc9863a_apahb_gate_desc }, + { .compatible = "sprd,sc9863a-aonapb-gate", /* 0x402e0000 */ + .data = &sc9863a_aonapb_gate_desc }, + { .compatible = "sprd,sc9863a-mm-gate", /* 0x60800000 */ + .data = &sc9863a_mm_gate_desc }, + { .compatible = "sprd,sc9863a-apapb-gate", /* 0x71300000 */ + .data = &sc9863a_apapb_gate_desc }, + { } +}; +module_device_table(of, sprd_sc9863a_clk_ids); + +static int sc9863a_clk_probe(struct platform_device *pdev) +{ + const struct sprd_clk_desc *desc; + int ret; + + desc = device_get_match_data(&pdev->dev); + if (!desc) + return -enodev; + + ret = sprd_clk_regmap_init(pdev, desc); + if (ret) + return ret; + + return sprd_clk_probe(&pdev->dev, desc->hw_clks); +} + +static struct platform_driver sc9863a_clk_driver = { + .probe = sc9863a_clk_probe, + .driver = { + .name = "sc9863a-clk", + .of_match_table = sprd_sc9863a_clk_ids, + }, +}; +module_platform_driver(sc9863a_clk_driver); + +module_description("spreadtrum sc9863a clock driver"); +module_license("gpl v2");
|
Clock
|
0e4b8a2349f3aa9b54c217b338ee65d8b2b6b739
|
chunyan zhang
|
drivers
|
clk
|
sprd
|
clocksource: add driver for the ingenic jz47xx ost
|
ost is the os timer, a 64-bit timer/counter with buffered reading.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add driver for the ingenic jz47xx ost
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['clocksource']
|
['kconfig', 'c', 'makefile']
| 3
| 198
| 0
|
--- diff --git a/drivers/clocksource/kconfig b/drivers/clocksource/kconfig --- a/drivers/clocksource/kconfig +++ b/drivers/clocksource/kconfig +config ingenic_ost + bool "clocksource for ingenic os timer" + depends on mips || compile_test + depends on common_clk + select mfd_syscon + help + support for the operating system timer of the ingenic jz socs. + diff --git a/drivers/clocksource/makefile b/drivers/clocksource/makefile --- a/drivers/clocksource/makefile +++ b/drivers/clocksource/makefile +obj-$(config_ingenic_ost) += ingenic-ost.o diff --git a/drivers/clocksource/ingenic-ost.c b/drivers/clocksource/ingenic-ost.c --- /dev/null +++ b/drivers/clocksource/ingenic-ost.c +// spdx-license-identifier: gpl-2.0 +/* + * jz47xx socs tcu operating system timer driver + * + * copyright (c) 2016 maarten ter huurne <maarten@treewalker.org> + * copyright (c) 2020 paul cercueil <paul@crapouillou.net> + */ + +#include <linux/clk.h> +#include <linux/clocksource.h> +#include <linux/mfd/ingenic-tcu.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/pm.h> +#include <linux/regmap.h> +#include <linux/sched_clock.h> + +#define tcu_ost_tcsr_mask 0xffc0 +#define tcu_ost_tcsr_cnt_md bit(15) + +#define tcu_ost_channel 15 + +/* + * the tcu_reg_ost_cnt{l,r} from <linux/mfd/ingenic-tcu.h> are only for the + * regmap; these are for use with the __iomem pointer. + */ +#define ost_reg_cntl 0x4 +#define ost_reg_cnth 0x8 + +struct ingenic_ost_soc_info { + bool is64bit; +}; + +struct ingenic_ost { + void __iomem *regs; + struct clk *clk; + + struct clocksource cs; +}; + +static struct ingenic_ost *ingenic_ost; + +static u64 notrace ingenic_ost_read_cntl(void) +{ + /* read using __iomem pointer instead of regmap to avoid locking */ + return readl(ingenic_ost->regs + ost_reg_cntl); +} + +static u64 notrace ingenic_ost_read_cnth(void) +{ + /* read using __iomem pointer instead of regmap to avoid locking */ + return readl(ingenic_ost->regs + ost_reg_cnth); +} + +static u64 notrace ingenic_ost_clocksource_readl(struct clocksource *cs) +{ + return ingenic_ost_read_cntl(); +} + +static u64 notrace ingenic_ost_clocksource_readh(struct clocksource *cs) +{ + return ingenic_ost_read_cnth(); +} + +static int __init ingenic_ost_probe(struct platform_device *pdev) +{ + const struct ingenic_ost_soc_info *soc_info; + struct device *dev = &pdev->dev; + struct ingenic_ost *ost; + struct clocksource *cs; + struct regmap *map; + unsigned long rate; + int err; + + soc_info = device_get_match_data(dev); + if (!soc_info) + return -einval; + + ost = devm_kzalloc(dev, sizeof(*ost), gfp_kernel); + if (!ost) + return -enomem; + + ingenic_ost = ost; + + ost->regs = devm_platform_ioremap_resource(pdev, 0); + if (is_err(ost->regs)) + return ptr_err(ost->regs); + + map = device_node_to_regmap(dev->parent->of_node); + if (!map) { + dev_err(dev, "regmap not found"); + return -einval; + } + + ost->clk = devm_clk_get(dev, "ost"); + if (is_err(ost->clk)) + return ptr_err(ost->clk); + + err = clk_prepare_enable(ost->clk); + if (err) + return err; + + /* clear counter high/low registers */ + if (soc_info->is64bit) + regmap_write(map, tcu_reg_ost_cntl, 0); + regmap_write(map, tcu_reg_ost_cnth, 0); + + /* don't reset counter at compare value. */ + regmap_update_bits(map, tcu_reg_ost_tcsr, + tcu_ost_tcsr_mask, tcu_ost_tcsr_cnt_md); + + rate = clk_get_rate(ost->clk); + + /* enable ost tcu channel */ + regmap_write(map, tcu_reg_tesr, bit(tcu_ost_channel)); + + cs = &ost->cs; + cs->name = "ingenic-ost"; + cs->rating = 320; + cs->flags = clock_source_is_continuous; + cs->mask = clocksource_mask(32); + + if (soc_info->is64bit) + cs->read = ingenic_ost_clocksource_readl; + else + cs->read = ingenic_ost_clocksource_readh; + + err = clocksource_register_hz(cs, rate); + if (err) { + dev_err(dev, "clocksource registration failed"); + clk_disable_unprepare(ost->clk); + return err; + } + + if (soc_info->is64bit) + sched_clock_register(ingenic_ost_read_cntl, 32, rate); + else + sched_clock_register(ingenic_ost_read_cnth, 32, rate); + + return 0; +} + +static int __maybe_unused ingenic_ost_suspend(struct device *dev) +{ + struct ingenic_ost *ost = dev_get_drvdata(dev); + + clk_disable(ost->clk); + + return 0; +} + +static int __maybe_unused ingenic_ost_resume(struct device *dev) +{ + struct ingenic_ost *ost = dev_get_drvdata(dev); + + return clk_enable(ost->clk); +} + +static const struct dev_pm_ops __maybe_unused ingenic_ost_pm_ops = { + /* _noirq: we want the ost clock to be gated last / ungated first */ + .suspend_noirq = ingenic_ost_suspend, + .resume_noirq = ingenic_ost_resume, +}; + +static const struct ingenic_ost_soc_info jz4725b_ost_soc_info = { + .is64bit = false, +}; + +static const struct ingenic_ost_soc_info jz4770_ost_soc_info = { + .is64bit = true, +}; + +static const struct of_device_id ingenic_ost_of_match[] = { + { .compatible = "ingenic,jz4725b-ost", .data = &jz4725b_ost_soc_info, }, + { .compatible = "ingenic,jz4770-ost", .data = &jz4770_ost_soc_info, }, + { } +}; + +static struct platform_driver ingenic_ost_driver = { + .driver = { + .name = "ingenic-ost", +#ifdef config_pm_suspend + .pm = &ingenic_ost_pm_ops, +#endif + .of_match_table = ingenic_ost_of_match, + }, +}; +builtin_platform_driver_probe(ingenic_ost_driver, ingenic_ost_probe);
|
Clock
|
ca7b72b5a5f248b72c88441a93bdcee22f42b9b3
|
maarten ter huurne
|
drivers
|
clocksource
| |
clocksource/drivers/ingenic: add support for tcu of x1000
|
x1000 has a different tcu containing ost, since x1000, ost has been independent of tcu. this patch is prepare for later ost driver.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for tcu of x1000
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['clocksource', 'ingenic']
|
['c']
| 1
| 2
| 1
|
--- diff --git a/drivers/clocksource/ingenic-timer.c b/drivers/clocksource/ingenic-timer.c --- a/drivers/clocksource/ingenic-timer.c +++ b/drivers/clocksource/ingenic-timer.c + { .compatible = "ingenic,x1000-tcu", .data = &jz4740_soc_info, }, - +timer_of_declare(x1000_tcu_intc, "ingenic,x1000-tcu", ingenic_tcu_init);
|
Clock
|
a7cd39552194954bcdecfd9ff775466a61bda5bb
|
zhou yanjie
|
drivers
|
clocksource
| |
phy: amlogic: add amlogic a1 usb2 phy driver
|
this adds support for the usb2 phy found in the amlogic a1 soc family.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add amlogic a1 usb2 phy driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['amlogic']
|
['c']
| 1
| 59
| 26
|
--- diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c --- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c +++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c +enum meson_soc_id { + meson_soc_g12a = 0, + meson_soc_a1, +}; + + int soc_id; + unsigned int value; - regmap_write(priv->regmap, phy_ctrl_r18, - field_prep(phy_ctrl_r18_mpll_lkw_sel, 1) | - field_prep(phy_ctrl_r18_mpll_lk_w, 9) | - field_prep(phy_ctrl_r18_mpll_lk_s, 0x27) | - field_prep(phy_ctrl_r18_mpll_pfd_gain, 1) | - field_prep(phy_ctrl_r18_mpll_rou, 7) | - field_prep(phy_ctrl_r18_mpll_data_sel, 3) | - field_prep(phy_ctrl_r18_mpll_bias_adj, 1) | - field_prep(phy_ctrl_r18_mpll_bb_mode, 0) | - field_prep(phy_ctrl_r18_mpll_alpha, 3) | - field_prep(phy_ctrl_r18_mpll_adj_ldo, 1) | - phy_ctrl_r18_mpll_acg_range); + value = field_prep(phy_ctrl_r18_mpll_lkw_sel, 1) | + field_prep(phy_ctrl_r18_mpll_lk_w, 9) | + field_prep(phy_ctrl_r18_mpll_lk_s, 0x27) | + field_prep(phy_ctrl_r18_mpll_pfd_gain, 1) | + field_prep(phy_ctrl_r18_mpll_rou, 7) | + field_prep(phy_ctrl_r18_mpll_data_sel, 3) | + field_prep(phy_ctrl_r18_mpll_bias_adj, 1) | + field_prep(phy_ctrl_r18_mpll_bb_mode, 0) | + field_prep(phy_ctrl_r18_mpll_alpha, 3) | + field_prep(phy_ctrl_r18_mpll_adj_ldo, 1) | + phy_ctrl_r18_mpll_acg_range; + + if (priv->soc_id == meson_soc_a1) + value |= phy_ctrl_r18_mpll_dco_clk_sel; + + regmap_write(priv->regmap, phy_ctrl_r18, value); - regmap_write(priv->regmap, phy_ctrl_r4, - field_prep(phy_ctrl_r4_calib_code_7_0, 0xf) | - field_prep(phy_ctrl_r4_calib_code_15_8, 0xf) | - field_prep(phy_ctrl_r4_calib_code_23_16, 0xf) | - phy_ctrl_r4_test_bypass_mode_en | - field_prep(phy_ctrl_r4_i_c2l_bias_trim_1_0, 0) | - field_prep(phy_ctrl_r4_i_c2l_bias_trim_3_2, 0)); + if (priv->soc_id == meson_soc_g12a) + regmap_write(priv->regmap, phy_ctrl_r4, + field_prep(phy_ctrl_r4_calib_code_7_0, 0xf) | + field_prep(phy_ctrl_r4_calib_code_15_8, 0xf) | + field_prep(phy_ctrl_r4_calib_code_23_16, 0xf) | + phy_ctrl_r4_test_bypass_mode_en | + field_prep(phy_ctrl_r4_i_c2l_bias_trim_1_0, 0) | + field_prep(phy_ctrl_r4_i_c2l_bias_trim_3_2, 0)); + else if (priv->soc_id == meson_soc_a1) { + regmap_write(priv->regmap, phy_ctrl_r21, + phy_ctrl_r21_usb2_cal_ack_en | + phy_ctrl_r21_usb2_tx_strg_pd | + field_prep(phy_ctrl_r21_usb2_otg_aca_trim_1_0, 2)); + + /* analog settings */ + regmap_write(priv->regmap, phy_ctrl_r13, + field_prep(phy_ctrl_r13_min_count_for_sync_det, 7)); + } - /* analog settings */ - regmap_write(priv->regmap, phy_ctrl_r14, 0); - regmap_write(priv->regmap, phy_ctrl_r13, - phy_ctrl_r13_update_pma_signals | - field_prep(phy_ctrl_r13_min_count_for_sync_det, 7)); + if (priv->soc_id == meson_soc_g12a) { + /* analog settings */ + regmap_write(priv->regmap, phy_ctrl_r14, 0); + regmap_write(priv->regmap, phy_ctrl_r13, + phy_ctrl_r13_update_pma_signals | + field_prep(phy_ctrl_r13_min_count_for_sync_det, 7)); + } + priv->soc_id = (enum meson_soc_id)of_device_get_match_data(&pdev->dev); + - { .compatible = "amlogic,g12a-usb2-phy", }, - { }, + { + .compatible = "amlogic,g12a-usb2-phy", + .data = (void *)meson_soc_g12a, + }, + { + .compatible = "amlogic,a1-usb2-phy", + .data = (void *)meson_soc_a1, + }, + { /* sentinel */ }
|
PHY ("physical layer" framework)
|
23bcbb41645c2a3cfb8d78fa0820eb7b0f5e6e97
|
hanjie lin
|
drivers
|
phy
|
amlogic
|
phy: amlogic: add amlogic axg mipi/pcie analog phy driver
|
this adds support for the mipi analog phy which is also used for pcie found in the amlogic axg soc family.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add amlogic axg mipi/pcie analog phy driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['amlogic']
|
['kconfig', 'c', 'makefile']
| 3
| 205
| 5
|
--- diff --git a/drivers/phy/amlogic/kconfig b/drivers/phy/amlogic/kconfig --- a/drivers/phy/amlogic/kconfig +++ b/drivers/phy/amlogic/kconfig + +config phy_meson_axg_mipi_pcie_analog + tristate "meson axg mipi + pcie analog phy driver" + default arch_meson + depends on of && (arch_meson || compile_test) + select generic_phy + select regmap_mmio + help + enable this to support the meson mipi + pcie analog phy + found in meson axg socs. + if unsure, say n. diff --git a/drivers/phy/amlogic/makefile b/drivers/phy/amlogic/makefile --- a/drivers/phy/amlogic/makefile +++ b/drivers/phy/amlogic/makefile -obj-$(config_phy_meson8b_usb2) += phy-meson8b-usb2.o -obj-$(config_phy_meson_gxl_usb2) += phy-meson-gxl-usb2.o -obj-$(config_phy_meson_g12a_usb2) += phy-meson-g12a-usb2.o -obj-$(config_phy_meson_gxl_usb3) += phy-meson-gxl-usb3.o -obj-$(config_phy_meson_g12a_usb3_pcie) += phy-meson-g12a-usb3-pcie.o +obj-$(config_phy_meson8b_usb2) += phy-meson8b-usb2.o +obj-$(config_phy_meson_gxl_usb2) += phy-meson-gxl-usb2.o +obj-$(config_phy_meson_g12a_usb2) += phy-meson-g12a-usb2.o +obj-$(config_phy_meson_gxl_usb3) += phy-meson-gxl-usb3.o +obj-$(config_phy_meson_g12a_usb3_pcie) += phy-meson-g12a-usb3-pcie.o +obj-$(config_phy_meson_axg_mipi_pcie_analog) += phy-meson-axg-mipi-pcie-analog.o diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c --- /dev/null +++ b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c +// spdx-license-identifier: gpl-2.0 +/* + * amlogic axg mipi + pcie analog phy driver + * + * copyright (c) 2019 remi pommarel <repk@triplefau.lt> + */ +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/platform_device.h> +#include <dt-bindings/phy/phy.h> + +#define hhi_mipi_cntl0 0x00 +#define hhi_mipi_cntl0_common_block genmask(31, 28) +#define hhi_mipi_cntl0_enable bit(29) +#define hhi_mipi_cntl0_bandgap bit(26) +#define hhi_mipi_cntl0_decode_to_rterm genmask(15, 12) +#define hhi_mipi_cntl0_output_en bit(3) + +#define hhi_mipi_cntl1 0x01 +#define hhi_mipi_cntl1_ch0_cml_pdr_en bit(12) +#define hhi_mipi_cntl1_lp_ability genmask(5, 4) +#define hhi_mipi_cntl1_lp_resister bit(3) +#define hhi_mipi_cntl1_input_setting bit(2) +#define hhi_mipi_cntl1_input_sel bit(1) +#define hhi_mipi_cntl1_prbs7_en bit(0) + +#define hhi_mipi_cntl2 0x02 +#define hhi_mipi_cntl2_ch_pu genmask(31, 25) +#define hhi_mipi_cntl2_ch_ctl genmask(24, 19) +#define hhi_mipi_cntl2_ch0_digdr_en bit(18) +#define hhi_mipi_cntl2_ch_digdr_en bit(17) +#define hhi_mipi_cntl2_lpulps_en bit(16) +#define hhi_mipi_cntl2_ch_en(n) bit(15 - (n)) +#define hhi_mipi_cntl2_ch0_lp_ctl genmask(10, 1) + +struct phy_axg_mipi_pcie_analog_priv { + struct phy *phy; + unsigned int mode; + struct regmap *regmap; +}; + +static const struct regmap_config phy_axg_mipi_pcie_analog_regmap_conf = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = hhi_mipi_cntl2, +}; + +static int phy_axg_mipi_pcie_analog_power_on(struct phy *phy) +{ + struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy); + + /* mipi not supported yet */ + if (priv->mode != phy_type_pcie) + return -einval; + + regmap_update_bits(priv->regmap, hhi_mipi_cntl0, + hhi_mipi_cntl0_bandgap, hhi_mipi_cntl0_bandgap); + + regmap_update_bits(priv->regmap, hhi_mipi_cntl0, + hhi_mipi_cntl0_enable, hhi_mipi_cntl0_enable); + return 0; +} + +static int phy_axg_mipi_pcie_analog_power_off(struct phy *phy) +{ + struct phy_axg_mipi_pcie_analog_priv *priv = phy_get_drvdata(phy); + + /* mipi not supported yet */ + if (priv->mode != phy_type_pcie) + return -einval; + + regmap_update_bits(priv->regmap, hhi_mipi_cntl0, + hhi_mipi_cntl0_bandgap, 0); + regmap_update_bits(priv->regmap, hhi_mipi_cntl0, + hhi_mipi_cntl0_enable, 0); + return 0; +} + +static int phy_axg_mipi_pcie_analog_init(struct phy *phy) +{ + return 0; +} + +static int phy_axg_mipi_pcie_analog_exit(struct phy *phy) +{ + return 0; +} + +static const struct phy_ops phy_axg_mipi_pcie_analog_ops = { + .init = phy_axg_mipi_pcie_analog_init, + .exit = phy_axg_mipi_pcie_analog_exit, + .power_on = phy_axg_mipi_pcie_analog_power_on, + .power_off = phy_axg_mipi_pcie_analog_power_off, + .owner = this_module, +}; + +static struct phy *phy_axg_mipi_pcie_analog_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct phy_axg_mipi_pcie_analog_priv *priv = dev_get_drvdata(dev); + unsigned int mode; + + if (args->args_count != 1) { + dev_err(dev, "invalid number of arguments "); + return err_ptr(-einval); + } + + mode = args->args[0]; + + /* mipi mode is not supported yet */ + if (mode != phy_type_pcie) { + dev_err(dev, "invalid phy mode select argument "); + return err_ptr(-einval); + } + + priv->mode = mode; + return priv->phy; +} + +static int phy_axg_mipi_pcie_analog_probe(struct platform_device *pdev) +{ + struct phy_provider *phy; + struct device *dev = &pdev->dev; + struct phy_axg_mipi_pcie_analog_priv *priv; + struct device_node *np = dev->of_node; + struct regmap *map; + struct resource *res; + void __iomem *base; + int ret; + + priv = devm_kmalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + res = platform_get_resource(pdev, ioresource_mem, 0); + base = devm_ioremap_resource(dev, res); + if (is_err(base)) { + dev_err(dev, "failed to get regmap base "); + return ptr_err(base); + } + + map = devm_regmap_init_mmio(dev, base, + &phy_axg_mipi_pcie_analog_regmap_conf); + if (is_err(map)) { + dev_err(dev, "failed to get hhi regmap "); + return ptr_err(map); + } + priv->regmap = map; + + priv->phy = devm_phy_create(dev, np, &phy_axg_mipi_pcie_analog_ops); + if (is_err(priv->phy)) { + ret = ptr_err(priv->phy); + if (ret != -eprobe_defer) + dev_err(dev, "failed to create phy "); + return ret; + } + + phy_set_drvdata(priv->phy, priv); + dev_set_drvdata(dev, priv); + + phy = devm_of_phy_provider_register(dev, + phy_axg_mipi_pcie_analog_xlate); + + return ptr_err_or_zero(phy); +} + +static const struct of_device_id phy_axg_mipi_pcie_analog_of_match[] = { + { + .compatible = "amlogic,axg-mipi-pcie-analog-phy", + }, + { }, +}; +module_device_table(of, phy_axg_mipi_pcie_analog_of_match); + +static struct platform_driver phy_axg_mipi_pcie_analog_driver = { + .probe = phy_axg_mipi_pcie_analog_probe, + .driver = { + .name = "phy-axg-mipi-pcie-analog", + .of_match_table = phy_axg_mipi_pcie_analog_of_match, + }, +}; +module_platform_driver(phy_axg_mipi_pcie_analog_driver); + +module_author("remi pommarel <repk@triplefau.lt>"); +module_description("amlogic axg mipi + pcie analog phy driver"); +module_license("gpl v2");
|
PHY ("physical layer" framework)
|
af3f5722d10cc345cbcfd2e1190334baa237a4ee
|
remi pommarel
|
drivers
|
phy
|
amlogic
|
phy: amlogic: add amlogic axg pcie phy driver
|
this adds support for the pci phy found in the amlogic axg soc family. this will allow to mutualize code in pci-meson.c between axg and g12a soc.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add amlogic axg pcie phy driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['amlogic']
|
['kconfig', 'c', 'makefile']
| 3
| 204
| 0
|
--- diff --git a/drivers/phy/amlogic/kconfig b/drivers/phy/amlogic/kconfig --- a/drivers/phy/amlogic/kconfig +++ b/drivers/phy/amlogic/kconfig +config phy_meson_axg_pcie + tristate "meson axg pcie phy driver" + default arch_meson + depends on of && (arch_meson || compile_test) + select generic_phy + select regmap_mmio + help + enable this to support the meson mipi + pcie phy found + in meson axg socs. + if unsure, say n. + diff --git a/drivers/phy/amlogic/makefile b/drivers/phy/amlogic/makefile --- a/drivers/phy/amlogic/makefile +++ b/drivers/phy/amlogic/makefile +obj-$(config_phy_meson_axg_pcie) += phy-meson-axg-pcie.o diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c b/drivers/phy/amlogic/phy-meson-axg-pcie.c --- /dev/null +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c +// spdx-license-identifier: gpl-2.0 +/* + * amlogic axg pcie phy driver + * + * copyright (c) 2020 remi pommarel <repk@triplefau.lt> + */ +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <linux/platform_device.h> +#include <linux/bitfield.h> +#include <dt-bindings/phy/phy.h> + +#define meson_pcie_reg0 0x00 +#define meson_pcie_common_clk bit(4) +#define meson_pcie_port_sel genmask(3, 2) +#define meson_pcie_clk bit(1) +#define meson_pcie_powerdown bit(0) + +#define meson_pcie_two_x1 field_prep(meson_pcie_port_sel, 0x3) +#define meson_pcie_common_ref_clk field_prep(meson_pcie_common_clk, 0x1) +#define meson_pcie_phy_init (meson_pcie_two_x1 | \ + meson_pcie_common_ref_clk) +#define meson_pcie_reset_delay 500 + +struct phy_axg_pcie_priv { + struct phy *phy; + struct phy *analog; + struct regmap *regmap; + struct reset_control *reset; +}; + +static const struct regmap_config phy_axg_pcie_regmap_conf = { + .reg_bits = 8, + .val_bits = 32, + .reg_stride = 4, + .max_register = meson_pcie_reg0, +}; + +static int phy_axg_pcie_power_on(struct phy *phy) +{ + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = phy_power_on(priv->analog); + if (ret != 0) + return ret; + + regmap_update_bits(priv->regmap, meson_pcie_reg0, + meson_pcie_powerdown, 0); + return 0; +} + +static int phy_axg_pcie_power_off(struct phy *phy) +{ + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = phy_power_off(priv->analog); + if (ret != 0) + return ret; + + regmap_update_bits(priv->regmap, meson_pcie_reg0, + meson_pcie_powerdown, 1); + return 0; +} + +static int phy_axg_pcie_init(struct phy *phy) +{ + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = phy_init(priv->analog); + if (ret != 0) + return ret; + + regmap_write(priv->regmap, meson_pcie_reg0, meson_pcie_phy_init); + return reset_control_reset(priv->reset); +} + +static int phy_axg_pcie_exit(struct phy *phy) +{ + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = phy_exit(priv->analog); + if (ret != 0) + return ret; + + return reset_control_reset(priv->reset); +} + +static int phy_axg_pcie_reset(struct phy *phy) +{ + struct phy_axg_pcie_priv *priv = phy_get_drvdata(phy); + int ret = 0; + + ret = phy_reset(priv->analog); + if (ret != 0) + goto out; + + ret = reset_control_assert(priv->reset); + if (ret != 0) + goto out; + udelay(meson_pcie_reset_delay); + + ret = reset_control_deassert(priv->reset); + if (ret != 0) + goto out; + udelay(meson_pcie_reset_delay); + +out: + return ret; +} + +static const struct phy_ops phy_axg_pcie_ops = { + .init = phy_axg_pcie_init, + .exit = phy_axg_pcie_exit, + .power_on = phy_axg_pcie_power_on, + .power_off = phy_axg_pcie_power_off, + .reset = phy_axg_pcie_reset, + .owner = this_module, +}; + +static int phy_axg_pcie_probe(struct platform_device *pdev) +{ + struct phy_provider *pphy; + struct device *dev = &pdev->dev; + struct phy_axg_pcie_priv *priv; + struct device_node *np = dev->of_node; + struct resource *res; + void __iomem *base; + int ret; + + priv = devm_kmalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + priv->phy = devm_phy_create(dev, np, &phy_axg_pcie_ops); + if (is_err(priv->phy)) { + ret = ptr_err(priv->phy); + if (ret != -eprobe_defer) + dev_err(dev, "failed to create phy "); + return ret; + } + + res = platform_get_resource(pdev, ioresource_mem, 0); + base = devm_ioremap_resource(dev, res); + if (is_err(base)) + return ptr_err(base); + + priv->regmap = devm_regmap_init_mmio(dev, base, + &phy_axg_pcie_regmap_conf); + if (is_err(priv->regmap)) + return ptr_err(priv->regmap); + + priv->reset = devm_reset_control_array_get(dev, false, false); + if (is_err(priv->reset)) + return ptr_err(priv->reset); + + priv->analog = devm_phy_get(dev, "analog"); + if (is_err(priv->analog)) + return ptr_err(priv->analog); + + phy_set_drvdata(priv->phy, priv); + dev_set_drvdata(dev, priv); + pphy = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return ptr_err_or_zero(pphy); +} + +static const struct of_device_id phy_axg_pcie_of_match[] = { + { + .compatible = "amlogic,axg-pcie-phy", + }, + { }, +}; +module_device_table(of, phy_axg_pcie_of_match); + +static struct platform_driver phy_axg_pcie_driver = { + .probe = phy_axg_pcie_probe, + .driver = { + .name = "phy-axg-pcie", + .of_match_table = phy_axg_pcie_of_match, + }, +}; +module_platform_driver(phy_axg_pcie_driver); + +module_author("remi pommarel <repk@triplefau.lt>"); +module_description("amlogic axg pcie phy driver"); +module_license("gpl v2");
|
PHY ("physical layer" framework)
|
e2463559ff1d5a76e708a26ec91e4950e702b25c
|
remi pommarel
|
drivers
|
phy
|
amlogic
|
phy: qcom-qmp: add msm8996 ufs qmp support
|
the support for the 14nm msm8996 ufs phy is currently handled by the ufs-specific 14nm qmp driver, due to the earlier need for additional operations beyond the standard phy api.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add msm8996 ufs qmp support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qcom-qmp']
|
['txt', 'c']
| 2
| 111
| 0
|
--- diff --git a/documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/documentation/devicetree/bindings/phy/qcom-qmp-phy.txt --- a/documentation/devicetree/bindings/phy/qcom-qmp-phy.txt +++ b/documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - compatible: compatible list, contains: + "qcom,msm8996-qmp-ufs-phy" for 14nm ufs phy on msm8996, + for "qcom,msm8996-qmp-ufs-phy" must contain: + "ref". + for "qcom,msm8996-qmp-ufs-phy": must contain: + "ufsphy". diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c +static const unsigned int msm8996_ufsphy_regs_layout[] = { + [qphy_start_ctrl] = 0x00, + [qphy_pcs_ready_status] = 0x168, +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { + qmp_phy_init_cfg(qphy_power_down_control, 0x01), + qmp_phy_init_cfg(qserdes_com_cmn_config, 0x0e), + qmp_phy_init_cfg(qserdes_com_sysclk_en_sel, 0xd7), + qmp_phy_init_cfg(qserdes_com_clk_select, 0x30), + qmp_phy_init_cfg(qserdes_com_sys_clk_ctrl, 0x06), + qmp_phy_init_cfg(qserdes_com_bias_en_clkbuflr_en, 0x08), + qmp_phy_init_cfg(qserdes_com_bg_timer, 0x0a), + qmp_phy_init_cfg(qserdes_com_hsclk_sel, 0x05), + qmp_phy_init_cfg(qserdes_com_coreclk_div, 0x0a), + qmp_phy_init_cfg(qserdes_com_coreclk_div_mode1, 0x0a), + qmp_phy_init_cfg(qserdes_com_lock_cmp_en, 0x01), + qmp_phy_init_cfg(qserdes_com_vco_tune_ctrl, 0x10), + qmp_phy_init_cfg(qserdes_com_resetsm_cntrl, 0x20), + qmp_phy_init_cfg(qserdes_com_core_clk_en, 0x00), + qmp_phy_init_cfg(qserdes_com_lock_cmp_cfg, 0x00), + qmp_phy_init_cfg(qserdes_com_vco_tune_timer1, 0xff), + qmp_phy_init_cfg(qserdes_com_vco_tune_timer2, 0x3f), + qmp_phy_init_cfg(qserdes_com_vco_tune_map, 0x54), + qmp_phy_init_cfg(qserdes_com_svs_mode_clk_sel, 0x05), + qmp_phy_init_cfg(qserdes_com_dec_start_mode0, 0x82), + qmp_phy_init_cfg(qserdes_com_div_frac_start1_mode0, 0x00), + qmp_phy_init_cfg(qserdes_com_div_frac_start2_mode0, 0x00), + qmp_phy_init_cfg(qserdes_com_div_frac_start3_mode0, 0x00), + qmp_phy_init_cfg(qserdes_com_cp_ctrl_mode0, 0x0b), + qmp_phy_init_cfg(qserdes_com_pll_rctrl_mode0, 0x16), + qmp_phy_init_cfg(qserdes_com_pll_cctrl_mode0, 0x28), + qmp_phy_init_cfg(qserdes_com_integloop_gain0_mode0, 0x80), + qmp_phy_init_cfg(qserdes_com_integloop_gain1_mode0, 0x00), + qmp_phy_init_cfg(qserdes_com_vco_tune1_mode0, 0x28), + qmp_phy_init_cfg(qserdes_com_vco_tune2_mode0, 0x02), + qmp_phy_init_cfg(qserdes_com_lock_cmp1_mode0, 0xff), + qmp_phy_init_cfg(qserdes_com_lock_cmp2_mode0, 0x0c), + qmp_phy_init_cfg(qserdes_com_lock_cmp3_mode0, 0x00), + qmp_phy_init_cfg(qserdes_com_dec_start_mode1, 0x98), + qmp_phy_init_cfg(qserdes_com_div_frac_start1_mode1, 0x00), + qmp_phy_init_cfg(qserdes_com_div_frac_start2_mode1, 0x00), + qmp_phy_init_cfg(qserdes_com_div_frac_start3_mode1, 0x00), + qmp_phy_init_cfg(qserdes_com_cp_ctrl_mode1, 0x0b), + qmp_phy_init_cfg(qserdes_com_pll_rctrl_mode1, 0x16), + qmp_phy_init_cfg(qserdes_com_pll_cctrl_mode1, 0x28), + qmp_phy_init_cfg(qserdes_com_integloop_gain0_mode1, 0x80), + qmp_phy_init_cfg(qserdes_com_integloop_gain1_mode1, 0x00), + qmp_phy_init_cfg(qserdes_com_vco_tune1_mode1, 0xd6), + qmp_phy_init_cfg(qserdes_com_vco_tune2_mode1, 0x00), + qmp_phy_init_cfg(qserdes_com_lock_cmp1_mode1, 0x32), + qmp_phy_init_cfg(qserdes_com_lock_cmp2_mode1, 0x0f), + qmp_phy_init_cfg(qserdes_com_lock_cmp3_mode1, 0x00), +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { + qmp_phy_init_cfg(qserdes_tx_highz_transceiveren_bias_drvr_en, 0x45), + qmp_phy_init_cfg(qserdes_tx_lane_mode, 0x02), +}; + +static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { + qmp_phy_init_cfg(qserdes_rx_sigdet_lvl, 0x24), + qmp_phy_init_cfg(qserdes_rx_sigdet_cntrl, 0x02), + qmp_phy_init_cfg(qserdes_rx_rx_interface_mode, 0x00), + qmp_phy_init_cfg(qserdes_rx_sigdet_deglitch_cntrl, 0x18), + qmp_phy_init_cfg(qserdes_rx_ucdr_fastlock_fo_gain, 0x0b), + qmp_phy_init_cfg(qserdes_rx_rx_term_bw, 0x5b), + qmp_phy_init_cfg(qserdes_rx_rx_eq_gain1_lsb, 0xff), + qmp_phy_init_cfg(qserdes_rx_rx_eq_gain1_msb, 0x3f), + qmp_phy_init_cfg(qserdes_rx_rx_eq_gain2_lsb, 0xff), + qmp_phy_init_cfg(qserdes_rx_rx_eq_gain2_msb, 0x0f), + qmp_phy_init_cfg(qserdes_rx_rx_equ_adaptor_cntrl2, 0x0e), +}; + +static const char * const msm8996_ufs_phy_clk_l[] = { + "ref", +}; + +static const struct qmp_phy_cfg msm8996_ufs_cfg = { + .type = phy_type_ufs, + .nlanes = 1, + + .serdes_tbl = msm8996_ufs_serdes_tbl, + .serdes_tbl_num = array_size(msm8996_ufs_serdes_tbl), + .tx_tbl = msm8996_ufs_tx_tbl, + .tx_tbl_num = array_size(msm8996_ufs_tx_tbl), + .rx_tbl = msm8996_ufs_rx_tbl, + .rx_tbl_num = array_size(msm8996_ufs_rx_tbl), + + .clk_list = msm8996_ufs_phy_clk_l, + .num_clks = array_size(msm8996_ufs_phy_clk_l), + + .vreg_list = qmp_phy_vreg_l, + .num_vregs = array_size(qmp_phy_vreg_l), + + .regs = msm8996_ufsphy_regs_layout, + + .start_ctrl = serdes_start, + .pwrdn_ctrl = sw_pwrdn, + + .no_pcs_sw_reset = true, +}; + + }, { + .compatible = "qcom,msm8996-qmp-ufs-phy", + .data = &msm8996_ufs_cfg,
|
PHY ("physical layer" framework)
|
0347f0dcbd2f0ed3335e1e1bb908534c3e05d7f2
|
bjorn andersson
|
drivers
|
phy
|
bindings, phy, qualcomm
|
phy: qcom-qusb2: add generic qusb2 v2 phy support
|
add generic qusb2 v2 phy table so the respective phys can use the same table.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add generic qusb2 v2 phy support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qcom-qusb2']
|
['c']
| 1
| 9
| 9
|
--- diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c - * copyright (c) 2017, the linux foundation. all rights reserved. + * copyright (c) 2017, 2019, the linux foundation. all rights reserved. -static const unsigned int sdm845_regs_layout[] = { +static const unsigned int qusb2_v2_regs_layout[] = { -static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = { +static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { -static const struct qusb2_phy_cfg sdm845_phy_cfg = { - .tbl = sdm845_init_tbl, - .tbl_num = array_size(sdm845_init_tbl), - .regs = sdm845_regs_layout, +static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { + .tbl = qusb2_v2_init_tbl, + .tbl_num = array_size(qusb2_v2_init_tbl), + .regs = qusb2_v2_regs_layout, - .compatible = "qcom,sdm845-qusb2-phy", - .data = &sdm845_phy_cfg, + .compatible = "qcom,qusb2-v2-phy", + .data = &qusb2_v2_phy_cfg,
|
PHY ("physical layer" framework)
|
8fe75cd4cddfc8f8cd039ec4f2ee3fcb9fc8af09
|
sandeep maheswaram matthias kaehlcke mka chromium org stephen boyd swboyd chromium org
|
drivers
|
phy
|
qualcomm
|
phy: qcom: qmp: add sdm845 pcie qmp phy support
|
qcom_qmp_phy_init() is extended to support the additional register writes needed in pcs misc and the appropriate sequences and resources are defined for the gen2 pcie qmp phy found in sdm845.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add sdm845 pcie qmp phy support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qcom', 'qmp']
|
['c']
| 1
| 156
| 0
|
--- diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c +static const unsigned int sdm845_qmp_pciephy_regs_layout[] = { + [qphy_sw_reset] = 0x00, + [qphy_start_ctrl] = 0x08, + [qphy_pcs_status] = 0x174, +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = { + qmp_phy_init_cfg(qserdes_v3_com_bias_en_clkbuflr_en, 0x14), + qmp_phy_init_cfg(qserdes_v3_com_clk_select, 0x30), + qmp_phy_init_cfg(qserdes_v3_com_pll_ivco, 0x007), + qmp_phy_init_cfg(qserdes_v3_com_cmn_config, 0x06), + qmp_phy_init_cfg(qserdes_v3_com_lock_cmp_en, 0x01), + qmp_phy_init_cfg(qserdes_v3_com_resetsm_cntrl, 0x20), + qmp_phy_init_cfg(qserdes_v3_com_vco_tune_map, 0x00), + qmp_phy_init_cfg(qserdes_v3_com_vco_tune2_mode0, 0x01), + qmp_phy_init_cfg(qserdes_v3_com_vco_tune1_mode0, 0xc9), + qmp_phy_init_cfg(qserdes_v3_com_vco_tune_timer1, 0xff), + qmp_phy_init_cfg(qserdes_v3_com_vco_tune_timer2, 0x3f), + qmp_phy_init_cfg(qserdes_v3_com_svs_mode_clk_sel, 0x01), + qmp_phy_init_cfg(qserdes_v3_com_core_clk_en, 0x00), + qmp_phy_init_cfg(qserdes_v3_com_coreclk_div_mode0, 0x0a), + qmp_phy_init_cfg(qserdes_v3_com_clk_ep_div, 0x19), + qmp_phy_init_cfg(qserdes_v3_com_clk_enable1, 0x90), + qmp_phy_init_cfg(qserdes_v3_com_dec_start_mode0, 0x82), + qmp_phy_init_cfg(qserdes_v3_com_div_frac_start3_mode0, 0x02), + qmp_phy_init_cfg(qserdes_v3_com_div_frac_start2_mode0, 0xea), + qmp_phy_init_cfg(qserdes_v3_com_div_frac_start1_mode0, 0xab), + qmp_phy_init_cfg(qserdes_v3_com_lock_cmp3_mode0, 0x00), + qmp_phy_init_cfg(qserdes_v3_com_lock_cmp2_mode0, 0x0d), + qmp_phy_init_cfg(qserdes_v3_com_lock_cmp1_mode0, 0x04), + qmp_phy_init_cfg(qserdes_v3_com_hsclk_sel, 0x00), + qmp_phy_init_cfg(qserdes_v3_com_cp_ctrl_mode0, 0x06), + qmp_phy_init_cfg(qserdes_v3_com_pll_rctrl_mode0, 0x16), + qmp_phy_init_cfg(qserdes_v3_com_pll_cctrl_mode0, 0x36), + qmp_phy_init_cfg(qserdes_v3_com_cmn_mode, 0x01), + qmp_phy_init_cfg(qserdes_v3_com_clk_select, 0x33), + qmp_phy_init_cfg(qserdes_v3_com_sys_clk_ctrl, 0x02), + qmp_phy_init_cfg(qserdes_v3_com_sysclk_buf_enable, 0x06), + qmp_phy_init_cfg(qserdes_v3_com_sysclk_en_sel, 0x04), + qmp_phy_init_cfg(qserdes_v3_com_integloop_gain1_mode0, 0x00), + qmp_phy_init_cfg(qserdes_v3_com_integloop_gain0_mode0, 0x3f), + qmp_phy_init_cfg(qserdes_v3_com_bg_timer, 0x09), + qmp_phy_init_cfg(qserdes_v3_com_ssc_en_center, 0x01), + qmp_phy_init_cfg(qserdes_v3_com_ssc_per1, 0x40), + qmp_phy_init_cfg(qserdes_v3_com_ssc_per2, 0x01), + qmp_phy_init_cfg(qserdes_v3_com_ssc_adj_per1, 0x02), + qmp_phy_init_cfg(qserdes_v3_com_ssc_adj_per2, 0x00), + qmp_phy_init_cfg(qserdes_v3_com_ssc_step_size1, 0x7e), + qmp_phy_init_cfg(qserdes_v3_com_ssc_step_size2, 0x15), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = { + qmp_phy_init_cfg(qserdes_v3_tx_res_code_lane_offset_tx, 0x02), + qmp_phy_init_cfg(qserdes_v3_tx_rcv_detect_lvl_2, 0x12), + qmp_phy_init_cfg(qserdes_v3_tx_highz_drvr_en, 0x10), + qmp_phy_init_cfg(qserdes_v3_tx_lane_mode_1, 0x06), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = { + qmp_phy_init_cfg(qserdes_v3_rx_sigdet_cntrl, 0x03), + qmp_phy_init_cfg(qserdes_v3_rx_sigdet_enables, 0x10), + qmp_phy_init_cfg(qserdes_v3_rx_sigdet_deglitch_cntrl, 0x14), + qmp_phy_init_cfg(qserdes_v3_rx_rx_equ_adaptor_cntrl2, 0x0e), + qmp_phy_init_cfg(qserdes_v3_rx_rx_equ_adaptor_cntrl3, 0x04), + qmp_phy_init_cfg(qserdes_v3_rx_rx_equ_adaptor_cntrl4, 0x1a), + qmp_phy_init_cfg(qserdes_v3_rx_ucdr_so_saturation_and_enable, 0x4b), + qmp_phy_init_cfg(qserdes_v3_rx_ucdr_so_gain, 0x04), + qmp_phy_init_cfg(qserdes_v3_rx_ucdr_so_gain_half, 0x04), + qmp_phy_init_cfg(qserdes_v3_rx_rx_eq_offset_adaptor_cntrl1, 0x71), + qmp_phy_init_cfg(qserdes_v3_rx_rx_mode_00, 0x59), + qmp_phy_init_cfg(qserdes_v3_rx_rx_mode_01, 0x59), + qmp_phy_init_cfg(qserdes_v3_rx_rx_offset_adaptor_cntrl2, 0x80), + qmp_phy_init_cfg(qserdes_v3_rx_rx_interface_mode, 0x40), + qmp_phy_init_cfg(qserdes_v3_rx_ucdr_pi_controls, 0x71), + qmp_phy_init_cfg(qserdes_v3_rx_ucdr_fastlock_count_low, 0x40), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = { + qmp_phy_init_cfg(qphy_v3_pcs_endpoint_refclk_drive, 0x04), + + qmp_phy_init_cfg(qphy_v3_pcs_fll_cntrl2, 0x83), + qmp_phy_init_cfg(qphy_v3_pcs_fll_cnt_val_l, 0x09), + qmp_phy_init_cfg(qphy_v3_pcs_fll_cnt_val_h_tol, 0xa2), + qmp_phy_init_cfg(qphy_v3_pcs_fll_man_code, 0x40), + qmp_phy_init_cfg(qphy_v3_pcs_fll_cntrl1, 0x02), + + qmp_phy_init_cfg(qphy_v3_pcs_osc_dtct_actions, 0x00), + qmp_phy_init_cfg(qphy_v3_pcs_pwrup_reset_dly_time_auxclk, 0x01), + qmp_phy_init_cfg(qphy_v3_pcs_l1ss_wakeup_dly_time_auxclk_msb, 0x00), + qmp_phy_init_cfg(qphy_v3_pcs_l1ss_wakeup_dly_time_auxclk_lsb, 0x20), + qmp_phy_init_cfg(qphy_v3_pcs_lp_wakeup_dly_time_auxclk_msb, 0x00), + qmp_phy_init_cfg(qphy_v3_pcs_lp_wakeup_dly_time_auxclk, 0x01), + qmp_phy_init_cfg(qphy_v3_pcs_pll_lock_chk_dly_time, 0x73), + + qmp_phy_init_cfg(qphy_v3_pcs_rx_sigdet_lvl, 0xbb), + qmp_phy_init_cfg(qphy_v3_pcs_sigdet_cntrl, 0x03), + qmp_phy_init_cfg(qphy_v3_pcs_refgen_req_config1, 0x0d), + + qmp_phy_init_cfg(qphy_v3_pcs_power_state_config4, 0x00), +}; + +static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = { + qmp_phy_init_cfg(qphy_v3_pcs_misc_osc_dtct_config2, 0x52), + qmp_phy_init_cfg(qphy_v3_pcs_misc_osc_dtct_mode2_config2, 0x10), + qmp_phy_init_cfg(qphy_v3_pcs_misc_osc_dtct_mode2_config4, 0x1a), + qmp_phy_init_cfg(qphy_v3_pcs_misc_osc_dtct_mode2_config5, 0x06), + qmp_phy_init_cfg(qphy_v3_pcs_misc_pcie_int_aux_clk_config1, 0x00), +}; + + const struct qmp_phy_init_tbl *pcs_misc_tbl; + int pcs_misc_tbl_num; +static const char * const sdm845_pciephy_clk_l[] = { + "aux", "cfg_ahb", "ref", "refgen", +}; + +static const char * const sdm845_pciephy_reset_l[] = { + "phy", +}; + +static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { + .type = phy_type_pcie, + .nlanes = 1, + + .serdes_tbl = sdm845_qmp_pcie_serdes_tbl, + .serdes_tbl_num = array_size(sdm845_qmp_pcie_serdes_tbl), + .tx_tbl = sdm845_qmp_pcie_tx_tbl, + .tx_tbl_num = array_size(sdm845_qmp_pcie_tx_tbl), + .rx_tbl = sdm845_qmp_pcie_rx_tbl, + .rx_tbl_num = array_size(sdm845_qmp_pcie_rx_tbl), + .pcs_tbl = sdm845_qmp_pcie_pcs_tbl, + .pcs_tbl_num = array_size(sdm845_qmp_pcie_pcs_tbl), + .pcs_misc_tbl = sdm845_qmp_pcie_pcs_misc_tbl, + .pcs_misc_tbl_num = array_size(sdm845_qmp_pcie_pcs_misc_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = array_size(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = array_size(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = array_size(qmp_phy_vreg_l), + .regs = sdm845_qmp_pciephy_regs_layout, + + .start_ctrl = pcs_start | serdes_start, + .pwrdn_ctrl = sw_pwrdn | refclk_drv_dsbl, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + + void __iomem *pcs_misc = qphy->pcs_misc; + qcom_qmp_phy_configure(pcs_misc, cfg->regs, cfg->pcs_misc_tbl, + cfg->pcs_misc_tbl_num); + + }, { + .compatible = "qcom,sdm845-qmp-pcie-phy", + .data = &sdm845_qmp_pciephy_cfg,
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PHY ("physical layer" framework)
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421c9a0e97314fc9fc9f94aa47af9ecbd6cb65b6
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bjorn andersson vinod koul vkoul kernel org vinod koul vkoul kernel org
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drivers
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phy
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qualcomm
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phy: qcom: qmp: add sdm845 qhp pcie phy
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add the gen3 qhp pcie phy found in sdm845.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add sdm845 qhp pcie phy
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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['qcom', 'qmp']
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['h', 'c']
| 2
| 271
| 0
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--- diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c --- a/drivers/phy/qualcomm/phy-qcom-qmp.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp.c +static const unsigned int sdm845_qhp_pciephy_regs_layout[] = { + [qphy_sw_reset] = 0x00, + [qphy_start_ctrl] = 0x08, + [qphy_pcs_status] = 0x2ac, +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = { + qmp_phy_init_cfg(pcie_gen3_qhp_com_sysclk_en_sel, 0x27), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_en_center, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_per1, 0x31), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_per2, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_step_size1, 0xde), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_step_size2, 0x07), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_step_size1_mode1, 0x4c), + qmp_phy_init_cfg(pcie_gen3_qhp_com_ssc_step_size2_mode1, 0x06), + qmp_phy_init_cfg(pcie_gen3_qhp_com_bias_en_ckbuflr_en, 0x18), + qmp_phy_init_cfg(pcie_gen3_qhp_com_clk_enable1, 0xb0), + qmp_phy_init_cfg(pcie_gen3_qhp_com_lock_cmp1_mode0, 0x8c), + qmp_phy_init_cfg(pcie_gen3_qhp_com_lock_cmp2_mode0, 0x20), + qmp_phy_init_cfg(pcie_gen3_qhp_com_lock_cmp1_mode1, 0x14), + qmp_phy_init_cfg(pcie_gen3_qhp_com_lock_cmp2_mode1, 0x34), + qmp_phy_init_cfg(pcie_gen3_qhp_com_cp_ctrl_mode0, 0x06), + qmp_phy_init_cfg(pcie_gen3_qhp_com_cp_ctrl_mode1, 0x06), + qmp_phy_init_cfg(pcie_gen3_qhp_com_pll_rctrl_mode0, 0x16), + qmp_phy_init_cfg(pcie_gen3_qhp_com_pll_rctrl_mode1, 0x16), + qmp_phy_init_cfg(pcie_gen3_qhp_com_pll_cctrl_mode0, 0x36), + qmp_phy_init_cfg(pcie_gen3_qhp_com_pll_cctrl_mode1, 0x36), + qmp_phy_init_cfg(pcie_gen3_qhp_com_restrim_ctrl2, 0x05), + qmp_phy_init_cfg(pcie_gen3_qhp_com_lock_cmp_en, 0x42), + qmp_phy_init_cfg(pcie_gen3_qhp_com_dec_start_mode0, 0x82), + qmp_phy_init_cfg(pcie_gen3_qhp_com_dec_start_mode1, 0x68), + qmp_phy_init_cfg(pcie_gen3_qhp_com_div_frac_start1_mode0, 0x55), + qmp_phy_init_cfg(pcie_gen3_qhp_com_div_frac_start2_mode0, 0x55), + qmp_phy_init_cfg(pcie_gen3_qhp_com_div_frac_start3_mode0, 0x03), + qmp_phy_init_cfg(pcie_gen3_qhp_com_div_frac_start1_mode1, 0xab), + qmp_phy_init_cfg(pcie_gen3_qhp_com_div_frac_start2_mode1, 0xaa), + qmp_phy_init_cfg(pcie_gen3_qhp_com_div_frac_start3_mode1, 0x02), + qmp_phy_init_cfg(pcie_gen3_qhp_com_integloop_gain0_mode0, 0x3f), + qmp_phy_init_cfg(pcie_gen3_qhp_com_integloop_gain0_mode1, 0x3f), + qmp_phy_init_cfg(pcie_gen3_qhp_com_vco_tune_map, 0x10), + qmp_phy_init_cfg(pcie_gen3_qhp_com_clk_select, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_com_hsclk_sel1, 0x30), + qmp_phy_init_cfg(pcie_gen3_qhp_com_coreclk_div, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_com_core_clk_en, 0x73), + qmp_phy_init_cfg(pcie_gen3_qhp_com_cmn_config, 0x0c), + qmp_phy_init_cfg(pcie_gen3_qhp_com_svs_mode_clk_sel, 0x15), + qmp_phy_init_cfg(pcie_gen3_qhp_com_coreclk_div_mode1, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_com_cmn_mode, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_com_vregclk_div1, 0x22), + qmp_phy_init_cfg(pcie_gen3_qhp_com_vregclk_div2, 0x00), + qmp_phy_init_cfg(pcie_gen3_qhp_com_bgv_trim, 0x20), + qmp_phy_init_cfg(pcie_gen3_qhp_com_bg_ctrl, 0x07), +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = { + qmp_phy_init_cfg(pcie_gen3_qhp_l0_drvr_ctrl0, 0x00), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_drvr_tap_en, 0x0d), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_tx_band_mode, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_lane_mode, 0x1a), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_parallel_rate, 0x2f), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_cml_ctrl_mode0, 0x09), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_cml_ctrl_mode1, 0x09), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_cml_ctrl_mode2, 0x1b), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_preamp_ctrl_mode1, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_preamp_ctrl_mode2, 0x07), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_mixer_ctrl_mode0, 0x31), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_mixer_ctrl_mode1, 0x31), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_mixer_ctrl_mode2, 0x03), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ctle_thresh_dfe, 0x02), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_cga_thresh_dfe, 0x00), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rxengine_en0, 0x12), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ctle_train_time, 0x25), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ctle_dfe_ovrlp_time, 0x00), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_dfe_refresh_time, 0x05), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_dfe_enable_time, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_vga_gain, 0x26), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_dfe_gain, 0x12), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_eq_gain, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_offset_gain, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_pre_gain, 0x09), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_eq_intval, 0x15), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_edac_initval, 0x28), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rxeq_initb0, 0x7f), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rxeq_initb1, 0x07), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rcvrdone_thresh1, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rxeq_ctrl, 0x70), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_fo_gain_mode0, 0x8b), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_fo_gain_mode1, 0x08), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_fo_gain_mode2, 0x0a), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_so_gain_mode0, 0x03), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_so_gain_mode1, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_so_gain_mode2, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ucdr_so_config, 0x0c), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_band, 0x02), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_rcvr_path1_mode0, 0x5c), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_rcvr_path1_mode1, 0x3e), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_rcvr_path1_mode2, 0x3f), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_sigdet_enables, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_sigdet_cntrl, 0xa0), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_sigdet_deglitch_cntrl, 0x08), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_dcc_gain, 0x01), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_en_signal, 0xc3), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_psm_rx_en_cal, 0x00), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_misc_cntrl0, 0xbc), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_ts0_timer, 0x7f), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_dll_highdatarate, 0x15), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_drvr_ctrl1, 0x0c), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_drvr_ctrl2, 0x0f), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rx_resetcode_offset, 0x04), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_vga_initval, 0x20), + qmp_phy_init_cfg(pcie_gen3_qhp_l0_rsm_start, 0x01), +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_rx_tbl[] = { +}; + +static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = { + qmp_phy_init_cfg(pcie_gen3_qhp_phy_power_state_config, 0x3f), + qmp_phy_init_cfg(pcie_gen3_qhp_phy_pcs_tx_rx_config, 0x50), + qmp_phy_init_cfg(pcie_gen3_qhp_phy_txmgn_main_v0_m3p5db, 0x19), + qmp_phy_init_cfg(pcie_gen3_qhp_phy_txmgn_post_v0_m3p5db, 0x07), + qmp_phy_init_cfg(pcie_gen3_qhp_phy_txmgn_main_v0_m6db, 0x17), + qmp_phy_init_cfg(pcie_gen3_qhp_phy_txmgn_post_v0_m6db, 0x09), + qmp_phy_init_cfg(pcie_gen3_qhp_phy_power_state_config5, 0x9f), +}; + +static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = { + .type = phy_type_pcie, + .nlanes = 1, + + .serdes_tbl = sdm845_qhp_pcie_serdes_tbl, + .serdes_tbl_num = array_size(sdm845_qhp_pcie_serdes_tbl), + .tx_tbl = sdm845_qhp_pcie_tx_tbl, + .tx_tbl_num = array_size(sdm845_qhp_pcie_tx_tbl), + .rx_tbl = sdm845_qhp_pcie_rx_tbl, + .rx_tbl_num = array_size(sdm845_qhp_pcie_rx_tbl), + .pcs_tbl = sdm845_qhp_pcie_pcs_tbl, + .pcs_tbl_num = array_size(sdm845_qhp_pcie_pcs_tbl), + .clk_list = sdm845_pciephy_clk_l, + .num_clks = array_size(sdm845_pciephy_clk_l), + .reset_list = sdm845_pciephy_reset_l, + .num_resets = array_size(sdm845_pciephy_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = array_size(qmp_phy_vreg_l), + .regs = sdm845_qhp_pciephy_regs_layout, + + .start_ctrl = pcs_start | serdes_start, + .pwrdn_ctrl = sw_pwrdn | refclk_drv_dsbl, + + .has_pwrdn_delay = true, + .pwrdn_delay_min = 995, /* us */ + .pwrdn_delay_max = 1005, /* us */ +}; + + }, { + .compatible = "qcom,sdm845-qhp-pcie-phy", + .data = &sdm845_qhp_pciephy_cfg, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h +/* pcie gen3 com registers */ +#define pcie_gen3_qhp_com_ssc_en_center 0x14 +#define pcie_gen3_qhp_com_ssc_per1 0x20 +#define pcie_gen3_qhp_com_ssc_per2 0x24 +#define pcie_gen3_qhp_com_ssc_step_size1 0x28 +#define pcie_gen3_qhp_com_ssc_step_size2 0x2c +#define pcie_gen3_qhp_com_ssc_step_size1_mode1 0x34 +#define pcie_gen3_qhp_com_ssc_step_size2_mode1 0x38 +#define pcie_gen3_qhp_com_bias_en_ckbuflr_en 0x54 +#define pcie_gen3_qhp_com_clk_enable1 0x58 +#define pcie_gen3_qhp_com_lock_cmp1_mode0 0x6c +#define pcie_gen3_qhp_com_lock_cmp2_mode0 0x70 +#define pcie_gen3_qhp_com_lock_cmp1_mode1 0x78 +#define pcie_gen3_qhp_com_lock_cmp2_mode1 0x7c +#define pcie_gen3_qhp_com_bgv_trim 0x98 +#define pcie_gen3_qhp_com_cp_ctrl_mode0 0xb4 +#define pcie_gen3_qhp_com_cp_ctrl_mode1 0xb8 +#define pcie_gen3_qhp_com_pll_rctrl_mode0 0xc0 +#define pcie_gen3_qhp_com_pll_rctrl_mode1 0xc4 +#define pcie_gen3_qhp_com_pll_cctrl_mode0 0xcc +#define pcie_gen3_qhp_com_pll_cctrl_mode1 0xd0 +#define pcie_gen3_qhp_com_sysclk_en_sel 0xdc +#define pcie_gen3_qhp_com_restrim_ctrl2 0xf0 +#define pcie_gen3_qhp_com_lock_cmp_en 0xf8 +#define pcie_gen3_qhp_com_dec_start_mode0 0x100 +#define pcie_gen3_qhp_com_dec_start_mode1 0x108 +#define pcie_gen3_qhp_com_div_frac_start1_mode0 0x11c +#define pcie_gen3_qhp_com_div_frac_start2_mode0 0x120 +#define pcie_gen3_qhp_com_div_frac_start3_mode0 0x124 +#define pcie_gen3_qhp_com_div_frac_start1_mode1 0x128 +#define pcie_gen3_qhp_com_div_frac_start2_mode1 0x12c +#define pcie_gen3_qhp_com_div_frac_start3_mode1 0x130 +#define pcie_gen3_qhp_com_integloop_gain0_mode0 0x150 +#define pcie_gen3_qhp_com_integloop_gain0_mode1 0x158 +#define pcie_gen3_qhp_com_vco_tune_map 0x178 +#define pcie_gen3_qhp_com_bg_ctrl 0x1c8 +#define pcie_gen3_qhp_com_clk_select 0x1cc +#define pcie_gen3_qhp_com_hsclk_sel1 0x1d0 +#define pcie_gen3_qhp_com_coreclk_div 0x1e0 +#define pcie_gen3_qhp_com_core_clk_en 0x1e8 +#define pcie_gen3_qhp_com_cmn_config 0x1f0 +#define pcie_gen3_qhp_com_svs_mode_clk_sel 0x1fc +#define pcie_gen3_qhp_com_coreclk_div_mode1 0x21c +#define pcie_gen3_qhp_com_cmn_mode 0x224 +#define pcie_gen3_qhp_com_vregclk_div1 0x228 +#define pcie_gen3_qhp_com_vregclk_div2 0x22c + +/* pcie gen3 qhp lane registers */ +#define pcie_gen3_qhp_l0_drvr_ctrl0 0xc +#define pcie_gen3_qhp_l0_drvr_ctrl1 0x10 +#define pcie_gen3_qhp_l0_drvr_ctrl2 0x14 +#define pcie_gen3_qhp_l0_drvr_tap_en 0x18 +#define pcie_gen3_qhp_l0_tx_band_mode 0x60 +#define pcie_gen3_qhp_l0_lane_mode 0x64 +#define pcie_gen3_qhp_l0_parallel_rate 0x7c +#define pcie_gen3_qhp_l0_cml_ctrl_mode0 0xc0 +#define pcie_gen3_qhp_l0_cml_ctrl_mode1 0xc4 +#define pcie_gen3_qhp_l0_cml_ctrl_mode2 0xc8 +#define pcie_gen3_qhp_l0_preamp_ctrl_mode1 0xd0 +#define pcie_gen3_qhp_l0_preamp_ctrl_mode2 0xd4 +#define pcie_gen3_qhp_l0_mixer_ctrl_mode0 0xd8 +#define pcie_gen3_qhp_l0_mixer_ctrl_mode1 0xdc +#define pcie_gen3_qhp_l0_mixer_ctrl_mode2 0xe0 +#define pcie_gen3_qhp_l0_ctle_thresh_dfe 0xfc +#define pcie_gen3_qhp_l0_cga_thresh_dfe 0x100 +#define pcie_gen3_qhp_l0_rxengine_en0 0x108 +#define pcie_gen3_qhp_l0_ctle_train_time 0x114 +#define pcie_gen3_qhp_l0_ctle_dfe_ovrlp_time 0x118 +#define pcie_gen3_qhp_l0_dfe_refresh_time 0x11c +#define pcie_gen3_qhp_l0_dfe_enable_time 0x120 +#define pcie_gen3_qhp_l0_vga_gain 0x124 +#define pcie_gen3_qhp_l0_dfe_gain 0x128 +#define pcie_gen3_qhp_l0_eq_gain 0x130 +#define pcie_gen3_qhp_l0_offset_gain 0x134 +#define pcie_gen3_qhp_l0_pre_gain 0x138 +#define pcie_gen3_qhp_l0_vga_initval 0x13c +#define pcie_gen3_qhp_l0_eq_intval 0x154 +#define pcie_gen3_qhp_l0_edac_initval 0x160 +#define pcie_gen3_qhp_l0_rxeq_initb0 0x168 +#define pcie_gen3_qhp_l0_rxeq_initb1 0x16c +#define pcie_gen3_qhp_l0_rcvrdone_thresh1 0x178 +#define pcie_gen3_qhp_l0_rxeq_ctrl 0x180 +#define pcie_gen3_qhp_l0_ucdr_fo_gain_mode0 0x184 +#define pcie_gen3_qhp_l0_ucdr_fo_gain_mode1 0x188 +#define pcie_gen3_qhp_l0_ucdr_fo_gain_mode2 0x18c +#define pcie_gen3_qhp_l0_ucdr_so_gain_mode0 0x190 +#define pcie_gen3_qhp_l0_ucdr_so_gain_mode1 0x194 +#define pcie_gen3_qhp_l0_ucdr_so_gain_mode2 0x198 +#define pcie_gen3_qhp_l0_ucdr_so_config 0x19c +#define pcie_gen3_qhp_l0_rx_band 0x1a4 +#define pcie_gen3_qhp_l0_rx_rcvr_path1_mode0 0x1c0 +#define pcie_gen3_qhp_l0_rx_rcvr_path1_mode1 0x1c4 +#define pcie_gen3_qhp_l0_rx_rcvr_path1_mode2 0x1c8 +#define pcie_gen3_qhp_l0_sigdet_enables 0x230 +#define pcie_gen3_qhp_l0_sigdet_cntrl 0x234 +#define pcie_gen3_qhp_l0_sigdet_deglitch_cntrl 0x238 +#define pcie_gen3_qhp_l0_dcc_gain 0x2a4 +#define pcie_gen3_qhp_l0_rsm_start 0x2a8 +#define pcie_gen3_qhp_l0_rx_en_signal 0x2ac +#define pcie_gen3_qhp_l0_psm_rx_en_cal 0x2b0 +#define pcie_gen3_qhp_l0_rx_misc_cntrl0 0x2b8 +#define pcie_gen3_qhp_l0_ts0_timer 0x2c0 +#define pcie_gen3_qhp_l0_dll_highdatarate 0x2c4 +#define pcie_gen3_qhp_l0_rx_resetcode_offset 0x2cc + +/* pcie gen3 pcs registers */ +#define pcie_gen3_qhp_phy_txmgn_main_v0_m3p5db 0x2c +#define pcie_gen3_qhp_phy_txmgn_post_v0_m3p5db 0x40 +#define pcie_gen3_qhp_phy_txmgn_main_v0_m6db 0x54 +#define pcie_gen3_qhp_phy_txmgn_post_v0_m6db 0x68 +#define pcie_gen3_qhp_phy_power_state_config 0x15c +#define pcie_gen3_qhp_phy_power_state_config5 0x16c +#define pcie_gen3_qhp_phy_pcs_tx_rx_config 0x174 +
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PHY ("physical layer" framework)
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909a5c78de9126f090eeb44c66accece12b3e689
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bjorn andersson vinod koul vkoul kernel org julien massot jmassot softbankrobotics com vinod koul vkoul kernel org
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drivers
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phy
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qualcomm
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phy: qualcomm: add synopsys 28nm hi-speed usb phy driver
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adds qualcomm 28nm hi-speed usb phy driver support. this phy is usually paired with synopsys dwc3 usb controllers on qualcomm socs.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add synopsys 28nm hi-speed usb phy driver
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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['qualcomm']
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['kconfig', 'c', 'makefile']
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| 427
| 0
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--- diff --git a/drivers/phy/qualcomm/kconfig b/drivers/phy/qualcomm/kconfig --- a/drivers/phy/qualcomm/kconfig +++ b/drivers/phy/qualcomm/kconfig + +config phy_qcom_usb_hs_28nm + tristate "qualcomm 28nm high-speed phy" + depends on arch_qcom || compile_test + depends on extcon || !extcon # if extcon=m, this cannot be built-in + select generic_phy + help + enable this to support the qualcomm synopsys designware core 28nm + high-speed phy driver. this driver supports the hi-speed phy which + is usually paired with either the chipidea or synopsys dwc3 usb + ips on msm socs. diff --git a/drivers/phy/qualcomm/makefile b/drivers/phy/qualcomm/makefile --- a/drivers/phy/qualcomm/makefile +++ b/drivers/phy/qualcomm/makefile +obj-$(config_phy_qcom_usb_hs_28nm) += phy-qcom-usb-hs-28nm.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2009-2018, linux foundation. all rights reserved. + * copyright (c) 2018-2020, linaro limited + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_graph.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/reset.h> +#include <linux/slab.h> + +/* phy register and bit definitions */ +#define phy_ctrl_common0 0x078 +#define siddq bit(2) +#define phy_irq_cmd 0x0d0 +#define phy_intr_mask0 0x0d4 +#define phy_intr_clear0 0x0dc +#define dpdm_mask 0x1e +#define dp_1_0 bit(4) +#define dp_0_1 bit(3) +#define dm_1_0 bit(2) +#define dm_0_1 bit(1) + +enum hsphy_voltage { + vol_none, + vol_min, + vol_max, + vol_num, +}; + +enum hsphy_vreg { + vdd, + vdda_1p8, + vdda_3p3, + vreg_num, +}; + +struct hsphy_init_seq { + int offset; + int val; + int delay; +}; + +struct hsphy_data { + const struct hsphy_init_seq *init_seq; + unsigned int init_seq_num; +}; + +struct hsphy_priv { + void __iomem *base; + struct clk_bulk_data *clks; + int num_clks; + struct reset_control *phy_reset; + struct reset_control *por_reset; + struct regulator_bulk_data vregs[vreg_num]; + const struct hsphy_data *data; + enum phy_mode mode; +}; + +static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + priv->mode = phy_mode_invalid; + + if (mode > 0) + priv->mode = mode; + + return 0; +} + +static void qcom_snps_hsphy_enable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + /* clear any existing interrupts before enabling the interrupts */ + val = readb(priv->base + phy_intr_clear0); + val |= dpdm_mask; + writeb(val, priv->base + phy_intr_clear0); + + writeb(0x0, priv->base + phy_irq_cmd); + usleep_range(200, 220); + writeb(0x1, priv->base + phy_irq_cmd); + + /* make sure the interrupts are cleared */ + usleep_range(200, 220); + + val = readb(priv->base + phy_intr_mask0); + switch (priv->mode) { + case phy_mode_usb_host_hs: + case phy_mode_usb_host_fs: + case phy_mode_usb_device_hs: + case phy_mode_usb_device_fs: + val |= dp_1_0 | dm_0_1; + break; + case phy_mode_usb_host_ls: + case phy_mode_usb_device_ls: + val |= dp_0_1 | dm_1_0; + break; + default: + /* no device connected */ + val |= dp_0_1 | dm_0_1; + break; + } + writeb(val, priv->base + phy_intr_mask0); +} + +static void qcom_snps_hsphy_disable_hv_interrupts(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + phy_intr_mask0); + val &= ~dpdm_mask; + writeb(val, priv->base + phy_intr_mask0); + + /* clear any pending interrupts */ + val = readb(priv->base + phy_intr_clear0); + val |= dpdm_mask; + writeb(val, priv->base + phy_intr_clear0); + + writeb(0x0, priv->base + phy_irq_cmd); + usleep_range(200, 220); + + writeb(0x1, priv->base + phy_irq_cmd); + usleep_range(200, 220); +} + +static void qcom_snps_hsphy_enter_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + phy_ctrl_common0); + val |= siddq; + writeb(val, priv->base + phy_ctrl_common0); +} + +static void qcom_snps_hsphy_exit_retention(struct hsphy_priv *priv) +{ + u32 val; + + val = readb(priv->base + phy_ctrl_common0); + val &= ~siddq; + writeb(val, priv->base + phy_ctrl_common0); +} + +static int qcom_snps_hsphy_power_on(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(vreg_num, priv->vregs); + if (ret) + return ret; + ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + goto err_disable_regulator; + qcom_snps_hsphy_disable_hv_interrupts(priv); + qcom_snps_hsphy_exit_retention(priv); + + return 0; + +err_disable_regulator: + regulator_bulk_disable(vreg_num, priv->vregs); + + return ret; +} + +static int qcom_snps_hsphy_power_off(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + + qcom_snps_hsphy_enter_retention(priv); + qcom_snps_hsphy_enable_hv_interrupts(priv); + clk_bulk_disable_unprepare(priv->num_clks, priv->clks); + regulator_bulk_disable(vreg_num, priv->vregs); + + return 0; +} + +static int qcom_snps_hsphy_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(10, 15); + + ret = reset_control_deassert(priv->phy_reset); + if (ret) + return ret; + + usleep_range(80, 100); + + return 0; +} + +static void qcom_snps_hsphy_init_sequence(struct hsphy_priv *priv) +{ + const struct hsphy_data *data = priv->data; + const struct hsphy_init_seq *seq; + int i; + + /* device match data is optional. */ + if (!data) + return; + + seq = data->init_seq; + + for (i = 0; i < data->init_seq_num; i++, seq++) { + writeb(seq->val, priv->base + seq->offset); + if (seq->delay) + usleep_range(seq->delay, seq->delay + 10); + } +} + +static int qcom_snps_hsphy_por_reset(struct hsphy_priv *priv) +{ + int ret; + + ret = reset_control_assert(priv->por_reset); + if (ret) + return ret; + + /* + * the femto phy is por reset in the following scenarios. + * + * 1. after overriding the parameter registers. + * 2. low power mode exit from phy retention. + * + * ensure that siddq is cleared before bringing the phy + * out of reset. + */ + qcom_snps_hsphy_exit_retention(priv); + + /* + * as per databook, 10 usec delay is required between + * phy por assert and de-assert. + */ + usleep_range(10, 20); + ret = reset_control_deassert(priv->por_reset); + if (ret) + return ret; + + /* + * as per databook, it takes 75 usec for phy to stabilize + * after the reset. + */ + usleep_range(80, 100); + + return 0; +} + +static int qcom_snps_hsphy_init(struct phy *phy) +{ + struct hsphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = qcom_snps_hsphy_reset(priv); + if (ret) + return ret; + + qcom_snps_hsphy_init_sequence(priv); + + ret = qcom_snps_hsphy_por_reset(priv); + if (ret) + return ret; + + return 0; +} + +static const struct phy_ops qcom_snps_hsphy_ops = { + .init = qcom_snps_hsphy_init, + .power_on = qcom_snps_hsphy_power_on, + .power_off = qcom_snps_hsphy_power_off, + .set_mode = qcom_snps_hsphy_set_mode, + .owner = this_module, +}; + +static const char * const qcom_snps_hsphy_clks[] = { + "ref", + "ahb", + "sleep", +}; + +static int qcom_snps_hsphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct hsphy_priv *priv; + struct phy *phy; + int ret; + int i; + + priv = devm_kzalloc(dev, sizeof(*priv), gfp_kernel); + if (!priv) + return -enomem; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(priv->base)) + return ptr_err(priv->base); + + priv->num_clks = array_size(qcom_snps_hsphy_clks); + priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks), + gfp_kernel); + if (!priv->clks) + return -enomem; + + for (i = 0; i < priv->num_clks; i++) + priv->clks[i].id = qcom_snps_hsphy_clks[i]; + + ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks); + if (ret) + return ret; + + priv->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); + if (is_err(priv->phy_reset)) + return ptr_err(priv->phy_reset); + + priv->por_reset = devm_reset_control_get_exclusive(dev, "por"); + if (is_err(priv->por_reset)) + return ptr_err(priv->por_reset); + + priv->vregs[vdd].supply = "vdd"; + priv->vregs[vdda_1p8].supply = "vdda1p8"; + priv->vregs[vdda_3p3].supply = "vdda3p3"; + + ret = devm_regulator_bulk_get(dev, vreg_num, priv->vregs); + if (ret) + return ret; + + /* get device match data */ + priv->data = device_get_match_data(dev); + + phy = devm_phy_create(dev, dev->of_node, &qcom_snps_hsphy_ops); + if (is_err(phy)) + return ptr_err(phy); + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + if (is_err(provider)) + return ptr_err(provider); + + ret = regulator_set_load(priv->vregs[vdda_1p8].consumer, 19000); + if (ret < 0) + return ret; + + ret = regulator_set_load(priv->vregs[vdda_3p3].consumer, 16000); + if (ret < 0) + goto unset_1p8_load; + + return 0; + +unset_1p8_load: + regulator_set_load(priv->vregs[vdda_1p8].consumer, 0); + + return ret; +} + +/* + * the macro is used to define an initialization sequence. each tuple + * is meant to program 'value' into phy register at 'offset' with 'delay' + * in us followed. + */ +#define hsphy_init_cfg(o, v, d) { .offset = o, .val = v, .delay = d, } + +static const struct hsphy_init_seq init_seq_femtophy[] = { + hsphy_init_cfg(0xc0, 0x01, 0), + hsphy_init_cfg(0xe8, 0x0d, 0), + hsphy_init_cfg(0x74, 0x12, 0), + hsphy_init_cfg(0x98, 0x63, 0), + hsphy_init_cfg(0x9c, 0x03, 0), + hsphy_init_cfg(0xa0, 0x1d, 0), + hsphy_init_cfg(0xa4, 0x03, 0), + hsphy_init_cfg(0x8c, 0x23, 0), + hsphy_init_cfg(0x78, 0x08, 0), + hsphy_init_cfg(0x7c, 0xdc, 0), + hsphy_init_cfg(0x90, 0xe0, 20), + hsphy_init_cfg(0x74, 0x10, 0), + hsphy_init_cfg(0x90, 0x60, 0), +}; + +static const struct hsphy_data hsphy_data_femtophy = { + .init_seq = init_seq_femtophy, + .init_seq_num = array_size(init_seq_femtophy), +}; + +static const struct of_device_id qcom_snps_hsphy_match[] = { + { .compatible = "qcom,usb-hs-28nm-femtophy", .data = &hsphy_data_femtophy, }, + { }, +}; +module_device_table(of, qcom_snps_hsphy_match); + +static struct platform_driver qcom_snps_hsphy_driver = { + .probe = qcom_snps_hsphy_probe, + .driver = { + .name = "qcom,usb-hs-28nm-phy", + .of_match_table = qcom_snps_hsphy_match, + }, +}; +module_platform_driver(qcom_snps_hsphy_driver); + +module_description("qualcomm 28nm hi-speed usb phy driver"); +module_license("gpl v2");
|
PHY ("physical layer" framework)
|
67b27dbeac4dc86d8f09789861bc8eda6f3538c4
|
shawn guo
|
drivers
|
phy
|
qualcomm
|
phy: qualcomm: usb: add superspeed phy driver
|
controls qualcomm's ss phy 1.0.0 implemented on various socs on both the 20nm and 28nm process nodes.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add superspeed phy driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['qualcomm', 'usb']
|
['kconfig', 'c', 'makefile']
| 3
| 256
| 0
|
--- diff --git a/drivers/phy/qualcomm/kconfig b/drivers/phy/qualcomm/kconfig --- a/drivers/phy/qualcomm/kconfig +++ b/drivers/phy/qualcomm/kconfig + +config phy_qcom_usb_ss + tristate "qualcomm usb super-speed phy driver" + depends on arch_qcom || compile_test + depends on extcon || !extcon # if extcon=m, this cannot be built-in + select generic_phy + help + enable this to support the super-speed usb transceiver on various + qualcomm chipsets. diff --git a/drivers/phy/qualcomm/makefile b/drivers/phy/qualcomm/makefile --- a/drivers/phy/qualcomm/makefile +++ b/drivers/phy/qualcomm/makefile +obj-$(config_phy_qcom_usb_ss) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2012-2014,2017 the linux foundation. all rights reserved. + * copyright (c) 2018-2020, linaro limited + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/reset.h> +#include <linux/slab.h> + +#define phy_ctrl0 0x6c +#define phy_ctrl1 0x70 +#define phy_ctrl2 0x74 +#define phy_ctrl4 0x7c + +/* phy_ctrl bits */ +#define ref_phy_en bit(0) +#define lane0_pwr_on bit(2) +#define swi_pcs_clk_sel bit(4) +#define tst_pwr_down bit(4) +#define phy_reset bit(7) + +#define num_bulk_clks 3 +#define num_bulk_regs 2 + +struct ssphy_priv { + void __iomem *base; + struct device *dev; + struct reset_control *reset_com; + struct reset_control *reset_phy; + struct regulator_bulk_data regs[num_bulk_regs]; + struct clk_bulk_data clks[num_bulk_clks]; + enum phy_mode mode; +}; + +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static int qcom_ssphy_do_reset(struct ssphy_priv *priv) +{ + int ret; + + if (!priv->reset_com) { + qcom_ssphy_updatel(priv->base + phy_ctrl1, phy_reset, + phy_reset); + usleep_range(10, 20); + qcom_ssphy_updatel(priv->base + phy_ctrl1, phy_reset, 0); + } else { + ret = reset_control_assert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "failed to assert reset com "); + return ret; + } + + ret = reset_control_assert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "failed to assert reset phy "); + return ret; + } + + usleep_range(10, 20); + + ret = reset_control_deassert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "failed to deassert reset com "); + return ret; + } + + ret = reset_control_deassert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "failed to deassert reset phy "); + return ret; + } + } + + return 0; +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(num_bulk_regs, priv->regs); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(num_bulk_clks, priv->clks); + if (ret) + goto err_disable_regulator; + + ret = qcom_ssphy_do_reset(priv); + if (ret) + goto err_disable_clock; + + writeb(swi_pcs_clk_sel, priv->base + phy_ctrl0); + qcom_ssphy_updatel(priv->base + phy_ctrl4, lane0_pwr_on, lane0_pwr_on); + qcom_ssphy_updatel(priv->base + phy_ctrl2, ref_phy_en, ref_phy_en); + qcom_ssphy_updatel(priv->base + phy_ctrl4, tst_pwr_down, 0); + + return 0; +err_disable_clock: + clk_bulk_disable_unprepare(num_bulk_clks, priv->clks); +err_disable_regulator: + regulator_bulk_disable(num_bulk_regs, priv->regs); + + return ret; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_updatel(priv->base + phy_ctrl4, lane0_pwr_on, 0); + qcom_ssphy_updatel(priv->base + phy_ctrl2, ref_phy_en, 0); + qcom_ssphy_updatel(priv->base + phy_ctrl4, tst_pwr_down, tst_pwr_down); + + clk_bulk_disable_unprepare(num_bulk_clks, priv->clks); + regulator_bulk_disable(num_bulk_regs, priv->regs); + + return 0; +} + +static int qcom_ssphy_init_clock(struct ssphy_priv *priv) +{ + priv->clks[0].id = "ref"; + priv->clks[1].id = "ahb"; + priv->clks[2].id = "pipe"; + + return devm_clk_bulk_get(priv->dev, num_bulk_clks, priv->clks); +} + +static int qcom_ssphy_init_regulator(struct ssphy_priv *priv) +{ + int ret; + + priv->regs[0].supply = "vdd"; + priv->regs[1].supply = "vdda1p8"; + ret = devm_regulator_bulk_get(priv->dev, num_bulk_regs, priv->regs); + if (ret) { + if (ret != -eprobe_defer) + dev_err(priv->dev, "failed to get regulators "); + return ret; + } + + return ret; +} + +static int qcom_ssphy_init_reset(struct ssphy_priv *priv) +{ + priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com"); + if (is_err(priv->reset_com)) { + dev_err(priv->dev, "failed to get reset control com "); + return ptr_err(priv->reset_com); + } + + if (priv->reset_com) { + /* if reset_com is present, reset_phy is no longer optional */ + priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy"); + if (is_err(priv->reset_phy)) { + dev_err(priv->dev, "failed to get reset control phy "); + return ptr_err(priv->reset_phy); + } + } + + return 0; +} + +static const struct phy_ops qcom_ssphy_ops = { + .power_off = qcom_ssphy_power_off, + .power_on = qcom_ssphy_power_on, + .owner = this_module, +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct phy *phy; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), gfp_kernel); + if (!priv) + return -enomem; + + priv->dev = dev; + priv->mode = phy_mode_invalid; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(priv->base)) + return ptr_err(priv->base); + + ret = qcom_ssphy_init_clock(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_reset(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_regulator(priv); + if (ret) + return ret; + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (is_err(phy)) { + dev_err(dev, "failed to create the ss phy "); + return ptr_err(phy); + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return ptr_err_or_zero(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,usb-ss-28nm-phy", }, + { }, +}; +module_device_table(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom-usb-ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +module_description("qualcomm superspeed usb phy driver"); +module_license("gpl v2");
|
PHY ("physical layer" framework)
|
6076967a500c4c6dad19d10d71863db1590a35ed
|
jorge ramirez ortiz
|
drivers
|
phy
|
qualcomm
|
phy: tegra: xusb: add tegra194 support
|
add support for the xusb pad controller found on tegra194 socs. it is mostly similar to the same ip found on tegra186, but the number of pads exposed differs, as do the programming sequences. because most of the tegra194 xusb padctl registers definition and programming sequence are the same as tegra186, tegra194 xusb padctl can share the same driver, xusb-tegra186.c, with tegra186 xusb padctl.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add tegra194 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['tegra', 'xusb']
|
['h', 'c', 'makefile']
| 4
| 96
| 0
|
--- diff --git a/drivers/phy/tegra/makefile b/drivers/phy/tegra/makefile --- a/drivers/phy/tegra/makefile +++ b/drivers/phy/tegra/makefile +phy-tegra-xusb-$(config_arch_tegra_194_soc) += xusb-tegra186.o diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c --- a/drivers/phy/tegra/xusb-tegra186.c +++ b/drivers/phy/tegra/xusb-tegra186.c +#define xusb_padctl_ss_port_cfg 0x2c +#define portx_speed_support_shift(x) ((x) * 4) +#define portx_speed_support_mask (0x3) +#define port_speed_support_gen1 (0x0) + if (padctl->soc->supports_gen2 && port->disable_gen2) { + value = padctl_readl(padctl, xusb_padctl_ss_port_cfg); + value &= ~(portx_speed_support_mask << + portx_speed_support_shift(index)); + value |= (port_speed_support_gen1 << + portx_speed_support_shift(index)); + padctl_writel(padctl, value, xusb_padctl_ss_port_cfg); + } + +#if is_enabled(config_arch_tegra_194_soc) +static const char * const tegra194_xusb_padctl_supply_names[] = { + "avdd-usb", + "vclamp-usb", +}; + +static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = { + tegra186_lane("usb2-0", 0, 0, 0, usb2), + tegra186_lane("usb2-1", 0, 0, 0, usb2), + tegra186_lane("usb2-2", 0, 0, 0, usb2), + tegra186_lane("usb2-3", 0, 0, 0, usb2), +}; + +static const struct tegra_xusb_pad_soc tegra194_usb2_pad = { + .name = "usb2", + .num_lanes = array_size(tegra194_usb2_lanes), + .lanes = tegra194_usb2_lanes, + .ops = &tegra186_usb2_pad_ops, +}; + +static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = { + tegra186_lane("usb3-0", 0, 0, 0, usb3), + tegra186_lane("usb3-1", 0, 0, 0, usb3), + tegra186_lane("usb3-2", 0, 0, 0, usb3), + tegra186_lane("usb3-3", 0, 0, 0, usb3), +}; + +static const struct tegra_xusb_pad_soc tegra194_usb3_pad = { + .name = "usb3", + .num_lanes = array_size(tegra194_usb3_lanes), + .lanes = tegra194_usb3_lanes, + .ops = &tegra186_usb3_pad_ops, +}; + +static const struct tegra_xusb_pad_soc * const tegra194_pads[] = { + &tegra194_usb2_pad, + &tegra194_usb3_pad, +}; + +const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = { + .num_pads = array_size(tegra194_pads), + .pads = tegra194_pads, + .ports = { + .usb2 = { + .ops = &tegra186_usb2_port_ops, + .count = 4, + }, + .usb3 = { + .ops = &tegra186_usb3_port_ops, + .count = 4, + }, + }, + .ops = &tegra186_xusb_padctl_ops, + .supply_names = tegra194_xusb_padctl_supply_names, + .num_supplies = array_size(tegra194_xusb_padctl_supply_names), + .supports_gen2 = true, +}; +export_symbol_gpl(tegra194_xusb_padctl_soc); +#endif + diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c --- a/drivers/phy/tegra/xusb.c +++ b/drivers/phy/tegra/xusb.c +#endif +#if defined(config_arch_tegra_194_soc) + { + .compatible = "nvidia,tegra194-xusb-padctl", + .data = &tegra194_xusb_padctl_soc, + }, + enum usb_device_speed maximum_speed; + if (device_property_present(&port->dev, "maximum-speed")) { + maximum_speed = usb_get_maximum_speed(&port->dev); + if (maximum_speed == usb_speed_super) + usb3->disable_gen2 = true; + else if (maximum_speed == usb_speed_super_plus) + usb3->disable_gen2 = false; + else + return -einval; + } + diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h --- a/drivers/phy/tegra/xusb.h +++ b/drivers/phy/tegra/xusb.h + bool disable_gen2; + bool supports_gen2; +#if defined(config_arch_tegra_194_soc) +extern const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc; +#endif
|
PHY ("physical layer" framework)
|
1ef535c6ba8ebcad1ced47a9d382b162c34fba3a
|
jc kuo
|
drivers
|
phy
|
tegra
|
phy: ti: gmii-sel: add support for am654x/j721e soc
|
ti am654x/j721e socs have the same phy interface selection mechanism for cpswx subsystem as ti socs (am3/4/5/dra7), but registers and bit-fields placement is different.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for am654x/j721e soc
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['ti', 'gmii-sel']
|
['c']
| 1
| 19
| 0
|
--- diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c --- a/drivers/phy/ti/phy-gmii-sel.c +++ b/drivers/phy/ti/phy-gmii-sel.c +static const +struct reg_field phy_gmii_sel_fields_am654[][phy_gmii_sel_last] = { + { + [phy_gmii_sel_port_mode] = reg_field(0x4040, 0, 1), + [phy_gmii_sel_rgmii_id_mode] = reg_field((~0), 0, 0), + [phy_gmii_sel_rmii_io_clk_en] = reg_field((~0), 0, 0), + }, +}; + +static const +struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = { + .num_ports = 1, + .regfields = phy_gmii_sel_fields_am654, +}; + + { + .compatible = "ti,am654-phy-gmii-sel", + .data = &phy_gmii_sel_soc_am654, + },
|
PHY ("physical layer" framework)
|
d9aa91dfb2da59c1f22887013a1cec32a6f9fcec
|
grygorii strashko
|
drivers
|
phy
|
ti
|
phy: uniphier-pcie: add legacy soc support for pro5
|
add legacy soc support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. this supports pro5.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add legacy soc support for pro5
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['uniphier-pcie']
|
['c']
| 1
| 72
| 11
|
--- diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c --- a/drivers/phy/socionext/phy-uniphier-pcie.c +++ b/drivers/phy/socionext/phy-uniphier-pcie.c +#define pcl_phy_clkctrl 0x0000 +#define port_sel_mask genmask(11, 9) +#define port_sel_1 field_prep(port_sel_mask, 1) + - struct clk *clk; - struct reset_control *rst; + struct clk *clk, *clk_gio; + struct reset_control *rst, *rst_gio; + bool is_legacy; + u32 val; - ret = reset_control_deassert(priv->rst); + ret = clk_prepare_enable(priv->clk_gio); + ret = reset_control_deassert(priv->rst); + if (ret) + goto out_clk_gio_disable; + + ret = reset_control_deassert(priv->rst_gio); + if (ret) + goto out_rst_assert; + + /* support only 1 port */ + val = readl(priv->base + pcl_phy_clkctrl); + val &= ~port_sel_mask; + val |= port_sel_1; + writel(val, priv->base + pcl_phy_clkctrl); + + /* legacy controller doesn't have phy_reset and parameters */ + if (priv->data->is_legacy) + return 0; + +out_rst_assert: + reset_control_assert(priv->rst); +out_clk_gio_disable: + clk_disable_unprepare(priv->clk_gio); - uniphier_pciephy_assert(priv); + if (!priv->data->is_legacy) + uniphier_pciephy_assert(priv); + reset_control_assert(priv->rst_gio); + clk_disable_unprepare(priv->clk_gio); - priv->clk = devm_clk_get(dev, null); - if (is_err(priv->clk)) - return ptr_err(priv->clk); - - priv->rst = devm_reset_control_get_shared(dev, null); - if (is_err(priv->rst)) - return ptr_err(priv->rst); + if (priv->data->is_legacy) { + priv->clk_gio = devm_clk_get(dev, "gio"); + if (is_err(priv->clk_gio)) + return ptr_err(priv->clk_gio); + + priv->rst_gio = + devm_reset_control_get_shared(dev, "gio"); + if (is_err(priv->rst_gio)) + return ptr_err(priv->rst_gio); + + priv->clk = devm_clk_get(dev, "link"); + if (is_err(priv->clk)) + return ptr_err(priv->clk); + + priv->rst = devm_reset_control_get_shared(dev, "link"); + if (is_err(priv->rst)) + return ptr_err(priv->rst); + } else { + priv->clk = devm_clk_get(dev, null); + if (is_err(priv->clk)) + return ptr_err(priv->clk); + + priv->rst = devm_reset_control_get_shared(dev, null); + if (is_err(priv->rst)) + return ptr_err(priv->rst); + } +static const struct uniphier_pciephy_soc_data uniphier_pro5_data = { + .has_syscon = false, + .is_legacy = true, +}; + + .is_legacy = false, + .is_legacy = false, + { + .compatible = "socionext,uniphier-pro5-pcie-phy", + .data = &uniphier_pro5_data, + },
|
PHY ("physical layer" framework)
|
04de8fa202e6d5fbb07aecbb45daaeec8594664e
|
kunihiko hayashi
|
drivers
|
phy
|
socionext
|
phy: uniphier-usb3hs: add legacy soc support for pro5
|
add legacy soc support that needs to manage gio clock and reset. this supports pro5.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add legacy soc support for pro5
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['uniphier-usb3hs']
|
['c']
| 1
| 53
| 15
|
--- diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c --- a/drivers/phy/socionext/phy-uniphier-usb3hs.c +++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c - struct clk *clk, *clk_parent, *clk_ext; - struct reset_control *rst, *rst_parent; + struct clk *clk, *clk_parent, *clk_ext, *clk_parent_gio; + struct reset_control *rst, *rst_parent, *rst_parent_gio; + bool is_legacy; - ret = reset_control_deassert(priv->rst_parent); + ret = clk_prepare_enable(priv->clk_parent_gio); - if (!priv->data->config0 && !priv->data->config1) + ret = reset_control_deassert(priv->rst_parent); + if (ret) + goto out_clk_gio_disable; + + ret = reset_control_deassert(priv->rst_parent_gio); + if (ret) + goto out_rst_assert; + + if ((priv->data->is_legacy) + || (!priv->data->config0 && !priv->data->config1)) +out_clk_gio_disable: + clk_disable_unprepare(priv->clk_parent_gio); + reset_control_assert(priv->rst_parent_gio); + clk_disable_unprepare(priv->clk_parent_gio); - priv->clk = devm_clk_get(dev, "phy"); - if (is_err(priv->clk)) - return ptr_err(priv->clk); + if (!priv->data->is_legacy) { + priv->clk = devm_clk_get(dev, "phy"); + if (is_err(priv->clk)) + return ptr_err(priv->clk); + + priv->clk_ext = devm_clk_get_optional(dev, "phy-ext"); + if (is_err(priv->clk_ext)) + return ptr_err(priv->clk_ext); + + priv->rst = devm_reset_control_get_shared(dev, "phy"); + if (is_err(priv->rst)) + return ptr_err(priv->rst); + + } else { + priv->clk_parent_gio = devm_clk_get(dev, "gio"); + if (is_err(priv->clk_parent_gio)) + return ptr_err(priv->clk_parent_gio); + + priv->rst_parent_gio = + devm_reset_control_get_shared(dev, "gio"); + if (is_err(priv->rst_parent_gio)) + return ptr_err(priv->rst_parent_gio); + } - priv->clk_ext = devm_clk_get_optional(dev, "phy-ext"); - if (is_err(priv->clk_ext)) - return ptr_err(priv->clk_ext); - - priv->rst = devm_reset_control_get_shared(dev, "phy"); - if (is_err(priv->rst)) - return ptr_err(priv->rst); - +static const struct uniphier_u3hsphy_soc_data uniphier_pro5_data = { + .is_legacy = true, + .nparams = 0, +}; + + .is_legacy = false, + .is_legacy = false, + .is_legacy = false, + { + .compatible = "socionext,uniphier-pro5-usb3-hsphy", + .data = &uniphier_pro5_data, + },
|
PHY ("physical layer" framework)
|
e68c2a8a2f45cbe4a237b874f87ec14ae2dfa84c
|
kunihiko hayashi
|
drivers
|
phy
|
socionext
|
phy: uniphier-usb3ss: add pro5 support
|
pro5 soc has same scheme of usb3 ss-phy as pro4, so the data for pro5 is equivalent to pro4.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add pro5 support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['uniphier-usb3ss']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/phy/socionext/phy-uniphier-usb3ss.c b/drivers/phy/socionext/phy-uniphier-usb3ss.c --- a/drivers/phy/socionext/phy-uniphier-usb3ss.c +++ b/drivers/phy/socionext/phy-uniphier-usb3ss.c + { + .compatible = "socionext,uniphier-pro5-usb3-ssphy", + .data = &uniphier_pro4_data, + },
|
PHY ("physical layer" framework)
|
9376fa634afc207a3ce99e0957e04948c34d6510
|
kunihiko hayashi
|
drivers
|
phy
|
socionext
|
edac: add edac driver for dmc520
|
the driver supports error detection and correction on devices with an arm dmc-520 memory controller.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add edac driver for dmc520
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['kconfig', 'maintainers', 'c', 'makefile']
| 4
| 670
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +edac-dmc520 +m: lei wang <lewan@microsoft.com> +l: linux-edac@vger.kernel.org +s: supported +f: drivers/edac/dmc520_edac.c + diff --git a/drivers/edac/kconfig b/drivers/edac/kconfig --- a/drivers/edac/kconfig +++ b/drivers/edac/kconfig +config edac_dmc520 + tristate "arm dmc-520 ecc" + depends on arm64 + help + support for error detection and correction on the + socs with arm dmc-520 dram controller. + diff --git a/drivers/edac/makefile b/drivers/edac/makefile --- a/drivers/edac/makefile +++ b/drivers/edac/makefile +obj-$(config_edac_dmc520) += dmc520_edac.o diff --git a/drivers/edac/dmc520_edac.c b/drivers/edac/dmc520_edac.c --- /dev/null +++ b/drivers/edac/dmc520_edac.c +// spdx-license-identifier: gpl-2.0 + +/* + * edac driver for dmc-520 memory controller. + * + * the driver supports 10 interrupt lines, + * though only dram_ecc_errc and dram_ecc_errd are currently handled. + * + * authors: rui zhao <ruizhao@microsoft.com> + * lei wang <lewan@microsoft.com> + * shiping ji <shji@microsoft.com> + */ + +#include <linux/bitfield.h> +#include <linux/edac.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include "edac_mc.h" + +/* dmc-520 registers */ +#define reg_offset_feature_config 0x130 +#define reg_offset_ecc_errc_count_31_00 0x158 +#define reg_offset_ecc_errc_count_63_32 0x15c +#define reg_offset_ecc_errd_count_31_00 0x160 +#define reg_offset_ecc_errd_count_63_32 0x164 +#define reg_offset_interrupt_control 0x500 +#define reg_offset_interrupt_clr 0x508 +#define reg_offset_interrupt_status 0x510 +#define reg_offset_dram_ecc_errc_int_info_31_00 0x528 +#define reg_offset_dram_ecc_errc_int_info_63_32 0x52c +#define reg_offset_dram_ecc_errd_int_info_31_00 0x530 +#define reg_offset_dram_ecc_errd_int_info_63_32 0x534 +#define reg_offset_address_control_now 0x1010 +#define reg_offset_memory_type_now 0x1128 +#define reg_offset_scrub_control0_now 0x1170 +#define reg_offset_format_control 0x18 + +/* dmc-520 types, masks and bitfields */ +#define ram_ecc_int_ce_bit bit(0) +#define ram_ecc_int_ue_bit bit(1) +#define dram_ecc_int_ce_bit bit(2) +#define dram_ecc_int_ue_bit bit(3) +#define failed_access_int_bit bit(4) +#define failed_prog_int_bit bit(5) +#define link_err_int_bit bit(6) +#define temperature_event_int_bit bit(7) +#define arch_fsm_int_bit bit(8) +#define phy_request_int_bit bit(9) +#define memory_width_mask genmask(1, 0) +#define scrub_trigger0_next_mask genmask(1, 0) +#define reg_field_dram_ecc_enabled genmask(1, 0) +#define reg_field_memory_type genmask(2, 0) +#define reg_field_device_width genmask(9, 8) +#define reg_field_address_control_col genmask(2, 0) +#define reg_field_address_control_row genmask(10, 8) +#define reg_field_address_control_bank genmask(18, 16) +#define reg_field_address_control_rank genmask(25, 24) +#define reg_field_err_info_low_valid bit(0) +#define reg_field_err_info_low_col genmask(10, 1) +#define reg_field_err_info_low_row genmask(28, 11) +#define reg_field_err_info_low_rank genmask(31, 29) +#define reg_field_err_info_high_bank genmask(3, 0) +#define reg_field_err_info_high_valid bit(31) + +#define dram_address_control_min_col_bits 8 +#define dram_address_control_min_row_bits 11 + +#define dmc520_scrub_trigger_err_detect 2 +#define dmc520_scrub_trigger_idle 3 + +/* driver settings */ +/* + * the max-length message would be: "rank:7 bank:15 row:262143 col:1023". + * max length is 34. using a 40-size buffer is enough. + */ +#define dmc520_msg_buf_size 40 +#define edac_mod_name "dmc520-edac" +#define edac_ctl_name "dmc520" + +/* the data bus width for the attached memory chips. */ +enum dmc520_mem_width { + mem_width_x32 = 2, + mem_width_x64 = 3 +}; + +/* memory type */ +enum dmc520_mem_type { + mem_type_ddr3 = 1, + mem_type_ddr4 = 2 +}; + +/* memory device width */ +enum dmc520_dev_width { + dev_width_x4 = 0, + dev_width_x8 = 1, + dev_width_x16 = 2 +}; + +struct ecc_error_info { + u32 col; + u32 row; + u32 bank; + u32 rank; +}; + +/* the interrupt config */ +struct dmc520_irq_config { + char *name; + int mask; +}; + +/* the interrupt mappings */ +static struct dmc520_irq_config dmc520_irq_configs[] = { + { + .name = "ram_ecc_errc", + .mask = ram_ecc_int_ce_bit + }, + { + .name = "ram_ecc_errd", + .mask = ram_ecc_int_ue_bit + }, + { + .name = "dram_ecc_errc", + .mask = dram_ecc_int_ce_bit + }, + { + .name = "dram_ecc_errd", + .mask = dram_ecc_int_ue_bit + }, + { + .name = "failed_access", + .mask = failed_access_int_bit + }, + { + .name = "failed_prog", + .mask = failed_prog_int_bit + }, + { + .name = "link_err", + .mask = link_err_int_bit + }, + { + .name = "temperature_event", + .mask = temperature_event_int_bit + }, + { + .name = "arch_fsm", + .mask = arch_fsm_int_bit + }, + { + .name = "phy_request", + .mask = phy_request_int_bit + } +}; + +#define number_of_irqs array_size(dmc520_irq_configs) + +/* + * the edac driver private data. + * error_lock is to protect concurrent writes to the mci->error_desc through + * edac_mc_handle_error(). + */ +struct dmc520_edac { + void __iomem *reg_base; + spinlock_t error_lock; + u32 mem_width_in_bytes; + int irqs[number_of_irqs]; + int masks[number_of_irqs]; +}; + +static int dmc520_mc_idx; + +static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset) +{ + return readl(pvt->reg_base + offset); +} + +static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset) +{ + writel(val, pvt->reg_base + offset); +} + +static u32 dmc520_calc_dram_ecc_error(u32 value) +{ + u32 total = 0; + + /* each rank's error counter takes one byte. */ + while (value > 0) { + total += (value & 0xff); + value >>= 8; + } + return total; +} + +static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt, + bool is_ce) +{ + u32 reg_offset_low, reg_offset_high; + u32 err_low, err_high; + u32 err_count; + + reg_offset_low = is_ce ? reg_offset_ecc_errc_count_31_00 : + reg_offset_ecc_errd_count_31_00; + reg_offset_high = is_ce ? reg_offset_ecc_errc_count_63_32 : + reg_offset_ecc_errd_count_63_32; + + err_low = dmc520_read_reg(pvt, reg_offset_low); + err_high = dmc520_read_reg(pvt, reg_offset_high); + /* reset error counters */ + dmc520_write_reg(pvt, 0, reg_offset_low); + dmc520_write_reg(pvt, 0, reg_offset_high); + + err_count = dmc520_calc_dram_ecc_error(err_low) + + dmc520_calc_dram_ecc_error(err_high); + + return err_count; +} + +static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt, + bool is_ce, + struct ecc_error_info *info) +{ + u32 reg_offset_low, reg_offset_high; + u32 reg_val_low, reg_val_high; + bool valid; + + reg_offset_low = is_ce ? reg_offset_dram_ecc_errc_int_info_31_00 : + reg_offset_dram_ecc_errd_int_info_31_00; + reg_offset_high = is_ce ? reg_offset_dram_ecc_errc_int_info_63_32 : + reg_offset_dram_ecc_errd_int_info_63_32; + + reg_val_low = dmc520_read_reg(pvt, reg_offset_low); + reg_val_high = dmc520_read_reg(pvt, reg_offset_high); + + valid = (field_get(reg_field_err_info_low_valid, reg_val_low) != 0) && + (field_get(reg_field_err_info_high_valid, reg_val_high) != 0); + + if (valid) { + info->col = field_get(reg_field_err_info_low_col, reg_val_low); + info->row = field_get(reg_field_err_info_low_row, reg_val_low); + info->rank = field_get(reg_field_err_info_low_rank, reg_val_low); + info->bank = field_get(reg_field_err_info_high_bank, reg_val_high); + } else { + memset(info, 0, sizeof(*info)); + } +} + +static bool dmc520_is_ecc_enabled(void __iomem *reg_base) +{ + u32 reg_val = readl(reg_base + reg_offset_feature_config); + + return field_get(reg_field_dram_ecc_enabled, reg_val); +} + +static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt) +{ + enum scrub_type type = scrub_none; + u32 reg_val, scrub_cfg; + + reg_val = dmc520_read_reg(pvt, reg_offset_scrub_control0_now); + scrub_cfg = field_get(scrub_trigger0_next_mask, reg_val); + + if (scrub_cfg == dmc520_scrub_trigger_err_detect || + scrub_cfg == dmc520_scrub_trigger_idle) + type = scrub_hw_prog; + + return type; +} + +/* get the memory data bus width, in number of bytes. */ +static u32 dmc520_get_memory_width(struct dmc520_edac *pvt) +{ + enum dmc520_mem_width mem_width_field; + u32 mem_width_in_bytes = 0; + u32 reg_val; + + reg_val = dmc520_read_reg(pvt, reg_offset_format_control); + mem_width_field = field_get(memory_width_mask, reg_val); + + if (mem_width_field == mem_width_x32) + mem_width_in_bytes = 4; + else if (mem_width_field == mem_width_x64) + mem_width_in_bytes = 8; + return mem_width_in_bytes; +} + +static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt) +{ + enum mem_type mt = mem_unknown; + enum dmc520_mem_type type; + u32 reg_val; + + reg_val = dmc520_read_reg(pvt, reg_offset_memory_type_now); + type = field_get(reg_field_memory_type, reg_val); + + switch (type) { + case mem_type_ddr3: + mt = mem_ddr3; + break; + + case mem_type_ddr4: + mt = mem_ddr4; + break; + } + + return mt; +} + +static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt) +{ + enum dmc520_dev_width device_width; + enum dev_type dt = dev_unknown; + u32 reg_val; + + reg_val = dmc520_read_reg(pvt, reg_offset_memory_type_now); + device_width = field_get(reg_field_device_width, reg_val); + + switch (device_width) { + case dev_width_x4: + dt = dev_x4; + break; + + case dev_width_x8: + dt = dev_x8; + break; + + case dev_width_x16: + dt = dev_x16; + break; + } + + return dt; +} + +static u32 dmc520_get_rank_count(void __iomem *reg_base) +{ + u32 reg_val, rank_bits; + + reg_val = readl(reg_base + reg_offset_address_control_now); + rank_bits = field_get(reg_field_address_control_rank, reg_val); + + return bit(rank_bits); +} + +static u64 dmc520_get_rank_size(struct dmc520_edac *pvt) +{ + u32 reg_val, col_bits, row_bits, bank_bits; + + reg_val = dmc520_read_reg(pvt, reg_offset_address_control_now); + + col_bits = field_get(reg_field_address_control_col, reg_val) + + dram_address_control_min_col_bits; + row_bits = field_get(reg_field_address_control_row, reg_val) + + dram_address_control_min_row_bits; + bank_bits = field_get(reg_field_address_control_bank, reg_val); + + return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits); +} + +static void dmc520_handle_dram_ecc_errors(struct mem_ctl_info *mci, + bool is_ce) +{ + struct dmc520_edac *pvt = mci->pvt_info; + char message[dmc520_msg_buf_size]; + struct ecc_error_info info; + u32 cnt; + + dmc520_get_dram_ecc_error_info(pvt, is_ce, &info); + + cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce); + if (!cnt) + return; + + snprintf(message, array_size(message), + "rank:%d bank:%d row:%d col:%d", + info.rank, info.bank, + info.row, info.col); + + spin_lock(&pvt->error_lock); + edac_mc_handle_error((is_ce ? hw_event_err_corrected : + hw_event_err_uncorrected), + mci, cnt, 0, 0, 0, info.rank, -1, -1, + message, ""); + spin_unlock(&pvt->error_lock); +} + +static irqreturn_t dmc520_edac_dram_ecc_isr(int irq, struct mem_ctl_info *mci, + bool is_ce) +{ + struct dmc520_edac *pvt = mci->pvt_info; + u32 i_mask; + + i_mask = is_ce ? dram_ecc_int_ce_bit : dram_ecc_int_ue_bit; + + dmc520_handle_dram_ecc_errors(mci, is_ce); + + dmc520_write_reg(pvt, i_mask, reg_offset_interrupt_clr); + + return irq_handled; +} + +static irqreturn_t dmc520_edac_dram_all_isr(int irq, struct mem_ctl_info *mci, + u32 irq_mask) +{ + struct dmc520_edac *pvt = mci->pvt_info; + irqreturn_t irq_ret = irq_none; + u32 status; + + status = dmc520_read_reg(pvt, reg_offset_interrupt_status); + + if ((irq_mask & dram_ecc_int_ce_bit) && + (status & dram_ecc_int_ce_bit)) + irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, true); + + if ((irq_mask & dram_ecc_int_ue_bit) && + (status & dram_ecc_int_ue_bit)) + irq_ret = dmc520_edac_dram_ecc_isr(irq, mci, false); + + return irq_ret; +} + +static irqreturn_t dmc520_isr(int irq, void *data) +{ + struct mem_ctl_info *mci = data; + struct dmc520_edac *pvt = mci->pvt_info; + u32 mask = 0; + int idx; + + for (idx = 0; idx < number_of_irqs; idx++) { + if (pvt->irqs[idx] == irq) { + mask = pvt->masks[idx]; + break; + } + } + return dmc520_edac_dram_all_isr(irq, mci, mask); +} + +static void dmc520_init_csrow(struct mem_ctl_info *mci) +{ + struct dmc520_edac *pvt = mci->pvt_info; + struct csrow_info *csi; + struct dimm_info *dimm; + u32 pages_per_rank; + enum dev_type dt; + enum mem_type mt; + int row, ch; + u64 rs; + + dt = dmc520_get_dtype(pvt); + mt = dmc520_get_mtype(pvt); + rs = dmc520_get_rank_size(pvt); + pages_per_rank = rs >> page_shift; + + for (row = 0; row < mci->nr_csrows; row++) { + csi = mci->csrows[row]; + + for (ch = 0; ch < csi->nr_channels; ch++) { + dimm = csi->channels[ch]->dimm; + dimm->grain = pvt->mem_width_in_bytes; + dimm->dtype = dt; + dimm->mtype = mt; + dimm->edac_mode = edac_flag_secded; + dimm->nr_pages = pages_per_rank / csi->nr_channels; + } + } +} + +static int dmc520_edac_probe(struct platform_device *pdev) +{ + bool registered[number_of_irqs] = { false }; + int irqs[number_of_irqs] = { -enxio }; + int masks[number_of_irqs] = { 0 }; + struct edac_mc_layer layers[1]; + struct dmc520_edac *pvt = null; + struct mem_ctl_info *mci; + void __iomem *reg_base; + u32 irq_mask_all = 0; + struct resource *res; + struct device *dev; + int ret, idx, irq; + u32 reg_val; + + /* parse the device node */ + dev = &pdev->dev; + + for (idx = 0; idx < number_of_irqs; idx++) { + irq = platform_get_irq_byname(pdev, dmc520_irq_configs[idx].name); + irqs[idx] = irq; + masks[idx] = dmc520_irq_configs[idx].mask; + if (irq >= 0) { + irq_mask_all |= dmc520_irq_configs[idx].mask; + edac_dbg(0, "discovered %s, irq: %d. ", dmc520_irq_configs[idx].name, irq); + } + } + + if (!irq_mask_all) { + edac_printk(kern_err, edac_mod_name, + "at least one valid interrupt line is expected. "); + return -einval; + } + + /* initialize dmc520 edac */ + res = platform_get_resource(pdev, ioresource_mem, 0); + reg_base = devm_ioremap_resource(dev, res); + if (is_err(reg_base)) + return ptr_err(reg_base); + + if (!dmc520_is_ecc_enabled(reg_base)) + return -enxio; + + layers[0].type = edac_mc_layer_chip_select; + layers[0].size = dmc520_get_rank_count(reg_base); + layers[0].is_virt_csrow = true; + + mci = edac_mc_alloc(dmc520_mc_idx++, array_size(layers), layers, sizeof(*pvt)); + if (!mci) { + edac_printk(kern_err, edac_mod_name, + "failed to allocate memory for mc instance "); + ret = -enomem; + goto err; + } + + pvt = mci->pvt_info; + + pvt->reg_base = reg_base; + spin_lock_init(&pvt->error_lock); + memcpy(pvt->irqs, irqs, sizeof(irqs)); + memcpy(pvt->masks, masks, sizeof(masks)); + + platform_set_drvdata(pdev, mci); + + mci->pdev = dev; + mci->mtype_cap = mem_flag_ddr3 | mem_flag_ddr4; + mci->edac_ctl_cap = edac_flag_none | edac_flag_secded; + mci->edac_cap = edac_flag_secded; + mci->scrub_cap = scrub_flag_hw_src; + mci->scrub_mode = dmc520_get_scrub_type(pvt); + mci->ctl_name = edac_ctl_name; + mci->dev_name = dev_name(mci->pdev); + mci->mod_name = edac_mod_name; + + edac_op_state = edac_opstate_int; + + pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt); + + dmc520_init_csrow(mci); + + /* clear interrupts, not affecting other unrelated interrupts */ + reg_val = dmc520_read_reg(pvt, reg_offset_interrupt_control); + dmc520_write_reg(pvt, reg_val & (~irq_mask_all), + reg_offset_interrupt_control); + dmc520_write_reg(pvt, irq_mask_all, reg_offset_interrupt_clr); + + for (idx = 0; idx < number_of_irqs; idx++) { + irq = irqs[idx]; + if (irq >= 0) { + ret = devm_request_irq(&pdev->dev, irq, + dmc520_isr, irqf_shared, + dev_name(&pdev->dev), mci); + if (ret < 0) { + edac_printk(kern_err, edac_mc, + "failed to request irq %d ", irq); + goto err; + } + registered[idx] = true; + } + } + + /* reset dram ce/ue counters */ + if (irq_mask_all & dram_ecc_int_ce_bit) + dmc520_get_dram_ecc_error_count(pvt, true); + + if (irq_mask_all & dram_ecc_int_ue_bit) + dmc520_get_dram_ecc_error_count(pvt, false); + + ret = edac_mc_add_mc(mci); + if (ret) { + edac_printk(kern_err, edac_mod_name, + "failed to register with edac core "); + goto err; + } + + /* enable interrupts, not affecting other unrelated interrupts */ + dmc520_write_reg(pvt, reg_val | irq_mask_all, + reg_offset_interrupt_control); + + return 0; + +err: + for (idx = 0; idx < number_of_irqs; idx++) { + if (registered[idx]) + devm_free_irq(&pdev->dev, pvt->irqs[idx], mci); + } + if (mci) + edac_mc_free(mci); + + return ret; +} + +static int dmc520_edac_remove(struct platform_device *pdev) +{ + u32 reg_val, idx, irq_mask_all = 0; + struct mem_ctl_info *mci; + struct dmc520_edac *pvt; + + mci = platform_get_drvdata(pdev); + pvt = mci->pvt_info; + + /* disable interrupts */ + reg_val = dmc520_read_reg(pvt, reg_offset_interrupt_control); + dmc520_write_reg(pvt, reg_val & (~irq_mask_all), + reg_offset_interrupt_control); + + /* free irq's */ + for (idx = 0; idx < number_of_irqs; idx++) { + if (pvt->irqs[idx] >= 0) { + irq_mask_all |= pvt->masks[idx]; + devm_free_irq(&pdev->dev, pvt->irqs[idx], mci); + } + } + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + + return 0; +} + +static const struct of_device_id dmc520_edac_driver_id[] = { + { .compatible = "arm,dmc-520", }, + { /* end of table */ } +}; + +module_device_table(of, dmc520_edac_driver_id); + +static struct platform_driver dmc520_edac_driver = { + .driver = { + .name = "dmc520", + .of_match_table = dmc520_edac_driver_id, + }, + + .probe = dmc520_edac_probe, + .remove = dmc520_edac_remove +}; + +module_platform_driver(dmc520_edac_driver); + +module_author("rui zhao <ruizhao@microsoft.com>"); +module_author("lei wang <lewan@microsoft.com>"); +module_author("shiping ji <shji@microsoft.com>"); +module_description("dmc-520 ecc driver"); +module_license("gpl v2");
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EDAC (Error Detection And Correction)
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1088750d78392cf79c113082ffbf955384737e9c
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lei wang james morse james morse arm com
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drivers
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edac
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docs: add documentation for mhi bus
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mhi (modem host interface) is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems. this commit adds the documentation for the bus and the implementation in linux kernel.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
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['rst']
| 4
| 297
| 0
|
--- diff --git a/documentation/index.rst b/documentation/index.rst --- a/documentation/index.rst +++ b/documentation/index.rst + mhi/index ----------------------------------- diff --git a/documentation/mhi/index.rst b/documentation/mhi/index.rst --- /dev/null +++ b/documentation/mhi/index.rst +.. spdx-license-identifier: gpl-2.0 + +=== +mhi +=== + +.. toctree:: + :maxdepth: 1 + + mhi + topology + +.. only:: subproject and html + + indices + ======= + + * :ref:'genindex' diff --git a/documentation/mhi/mhi.rst b/documentation/mhi/mhi.rst --- /dev/null +++ b/documentation/mhi/mhi.rst +.. spdx-license-identifier: gpl-2.0 + +========================== +mhi (modem host interface) +========================== + +this document provides information about the mhi protocol. + +overview +======== + +mhi is a protocol developed by qualcomm innovation center, inc. it is used +by the host processors to control and communicate with modem devices over high +speed peripheral buses or shared memory. even though mhi can be easily adapted +to any peripheral buses, it is primarily used with pcie based devices. mhi +provides logical channels over the physical buses and allows transporting the +modem protocols, such as ip data packets, modem control messages, and +diagnostics over at least one of those logical channels. also, the mhi +protocol provides data acknowledgment feature and manages the power state of the +modems via one or more logical channels. + +mhi internals +============= + +mmio +---- + +mmio (memory mapped io) consists of a set of registers in the device hardware, +which are mapped to the host memory space by the peripheral buses like pcie. +following are the major components of mmio register space: + +mhi control registers: access to mhi configurations registers + +mhi bhi registers: bhi (boot host interface) registers are used by the host +for downloading the firmware to the device before mhi initialization. + +channel doorbell array: channel doorbell (db) registers used by the host to +notify the device when there is new work to do. + +event doorbell array: associated with event context array, the event doorbell +(db) registers are used by the host to notify the device when new events are +available. + +debug registers: a set of registers and counters used by the device to expose +debugging information like performance, functional, and stability to the host. + +data structures +--------------- + +all data structures used by mhi are in the host system memory. using the +physical interface, the device accesses those data structures. mhi data +structures and data buffers in the host system memory regions are mapped for +the device. + +channel context array: all channel configurations are organized in channel +context data array. + +transfer rings: used by the host to schedule work items for a channel. the +transfer rings are organized as a circular queue of transfer descriptors (td). + +event context array: all event configurations are organized in the event context +data array. + +event rings: used by the device to send completion and state transition messages +to the host + +command context array: all command configurations are organized in command +context data array. + +command rings: used by the host to send mhi commands to the device. the command +rings are organized as a circular queue of command descriptors (cd). + +channels +-------- + +mhi channels are logical, unidirectional data pipes between a host and a device. +the concept of channels in mhi is similar to endpoints in usb. mhi supports up +to 256 channels. however, specific device implementations may support less than +the maximum number of channels allowed. + +two unidirectional channels with their associated transfer rings form a +bidirectional data pipe, which can be used by the upper-layer protocols to +transport application data packets (such as ip packets, modem control messages, +diagnostics messages, and so on). each channel is associated with a single +transfer ring. + +transfer rings +-------------- + +transfers between the host and device are organized by channels and defined by +transfer descriptors (td). tds are managed through transfer rings, which are +defined for each channel between the device and host and reside in the host +memory. tds consist of one or more ring elements (or transfer blocks):: + + [read pointer (rp)] ----------->[ring element] } td + [write pointer (wp)]- [ring element] + - [ring element] + --------->[ring element] + [ring element] + +below is the basic usage of transfer rings: + +* host allocates memory for transfer ring. +* host sets the base pointer, read pointer, and write pointer in corresponding + channel context. +* ring is considered empty when rp == wp. +* ring is considered full when wp + 1 == rp. +* rp indicates the next element to be serviced by the device. +* when the host has a new buffer to send, it updates the ring element with + buffer information, increments the wp to the next element and rings the + associated channel db. + +event rings +----------- + +events from the device to host are organized in event rings and defined by event +descriptors (ed). event rings are used by the device to report events such as +data transfer completion status, command completion status, and state changes +to the host. event rings are the array of eds that resides in the host +memory. eds consist of one or more ring elements (or transfer blocks):: + + [read pointer (rp)] ----------->[ring element] } ed + [write pointer (wp)]- [ring element] + - [ring element] + --------->[ring element] + [ring element] + +below is the basic usage of event rings: + +* host allocates memory for event ring. +* host sets the base pointer, read pointer, and write pointer in corresponding + channel context. +* both host and device has a local copy of rp, wp. +* ring is considered empty (no events to service) when wp + 1 == rp. +* ring is considered full of events when rp == wp. +* when there is a new event the device needs to send, the device updates ed + pointed by rp, increments the rp to the next element and triggers the + interrupt. + +ring element +------------ + +a ring element is a data structure used to transfer a single block +of data between the host and the device. transfer ring element types contain a +single buffer pointer, the size of the buffer, and additional control +information. other ring element types may only contain control and status +information. for single buffer operations, a ring descriptor is composed of a +single element. for large multi-buffer operations (such as scatter and gather), +elements can be chained to form a longer descriptor. + +mhi operations +============== + +mhi states +---------- + +mhi_state_reset +~~~~~~~~~~~~~~~ +mhi is in reset state after power-up or hardware reset. the host is not allowed +to access device mmio register space. + +mhi_state_ready +~~~~~~~~~~~~~~~ +mhi is ready for initialization. the host can start mhi initialization by +programming mmio registers. + +mhi_state_m0 +~~~~~~~~~~~~ +mhi is running and operational in the device. the host can start channels by +issuing channel start command. + +mhi_state_m1 +~~~~~~~~~~~~ +mhi operation is suspended by the device. this state is entered when the +device detects inactivity at the physical interface within a preset time. + +mhi_state_m2 +~~~~~~~~~~~~ +mhi is in low power state. mhi operation is suspended and the device may +enter lower power mode. + +mhi_state_m3 +~~~~~~~~~~~~ +mhi operation stopped by the host. this state is entered when the host suspends +mhi operation. + +mhi initialization +------------------ + +after system boots, the device is enumerated over the physical interface. +in the case of pcie, the device is enumerated and assigned bar-0 for +the device's mmio register space. to initialize the mhi in a device, +the host performs the following operations: + +* allocates the mhi context for event, channel and command arrays. +* initializes the context array, and prepares interrupts. +* waits until the device enters ready state. +* programs mhi mmio registers and sets device into mhi_m0 state. +* waits for the device to enter m0 state. + +mhi data transfer +----------------- + +mhi data transfer is initiated by the host to transfer data to the device. +following are the sequence of operations performed by the host to transfer +data to device: + +* host prepares td with buffer information. +* host increments the wp of the corresponding channel transfer ring. +* host rings the channel db register. +* device wakes up to process the td. +* device generates a completion event for the processed td by updating ed. +* device increments the rp of the corresponding event ring. +* device triggers irq to wake up the host. +* host wakes up and checks the event ring for completion event. +* host updates the wp of the corresponding event ring to indicate that the + data transfer has been completed successfully. + diff --git a/documentation/mhi/topology.rst b/documentation/mhi/topology.rst --- /dev/null +++ b/documentation/mhi/topology.rst +.. spdx-license-identifier: gpl-2.0 + +============ +mhi topology +============ + +this document provides information about the mhi topology modeling and +representation in the kernel. + +mhi controller +-------------- + +mhi controller driver manages the interaction with the mhi client devices +such as the external modems and wifi chipsets. it is also the mhi bus master +which is in charge of managing the physical link between the host and device. +it is however not involved in the actual data transfer as the data transfer +is taken care by the physical bus such as pcie. each controller driver exposes +channels and events based on the client device type. + +below are the roles of the mhi controller driver: + +* turns on the physical bus and establishes the link to the device +* configures irqs, iommu, and iomem +* allocates struct mhi_controller and registers with the mhi bus framework + with channel and event configurations using mhi_register_controller. +* initiates power on and shutdown sequence +* initiates suspend and resume power management operations of the device. + +mhi device +---------- + +mhi device is the logical device which binds to a maximum of two mhi channels +for bi-directional communication. once mhi is in powered on state, the mhi +core will create mhi devices based on the channel configuration exposed +by the controller. there can be a single mhi device for each channel or for a +couple of channels. + +each supported device is enumerated in:: + + /sys/bus/mhi/devices/ + +mhi driver +---------- + +mhi driver is the client driver which binds to one or more mhi devices. the mhi +driver sends and receives the upper-layer protocol packets like ip packets, +modem control messages, and diagnostics messages over mhi. the mhi core will +bind the mhi devices to the mhi driver. + +each supported driver is enumerated in:: + + /sys/bus/mhi/drivers/ + +below are the roles of the mhi driver: + +* registers the driver with the mhi bus framework using mhi_driver_register. +* prepares the device for transfer by calling mhi_prepare_for_transfer. +* initiates data transfer by calling mhi_queue_transfer. +* once the data transfer is finished, calls mhi_unprepare_from_transfer to + end data transfer.
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Modem Host Interface (MHI) Bus
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9435dc3b5e62557eea57cea922020ab3a41aaf7b
|
manivannan sadhasivam
|
documentation
| ||
bus: mhi: core: add support for registering mhi controllers
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this commit adds support for registering mhi controller drivers with the mhi stack. mhi controller drivers manages the interaction with the mhi client devices such as the external modems and wifi chipsets. they are also the mhi bus master in charge of managing the physical link between the host and client device.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
|
['h', 'kconfig', 'c', 'makefile']
| 9
| 988
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--- diff --git a/drivers/bus/kconfig b/drivers/bus/kconfig --- a/drivers/bus/kconfig +++ b/drivers/bus/kconfig +source "drivers/bus/mhi/kconfig" diff --git a/drivers/bus/makefile b/drivers/bus/makefile --- a/drivers/bus/makefile +++ b/drivers/bus/makefile + +# mhi +obj-$(config_mhi_bus) += mhi/ diff --git a/drivers/bus/mhi/kconfig b/drivers/bus/mhi/kconfig --- /dev/null +++ b/drivers/bus/mhi/kconfig +# spdx-license-identifier: gpl-2.0 +# +# mhi bus +# +# copyright (c) 2018-2020, the linux foundation. all rights reserved. +# + +config mhi_bus + tristate "modem host interface (mhi) bus" + help + bus driver for mhi protocol. modem host interface (mhi) is a + communication protocol used by the host processors to control + and communicate with modem devices over a high speed peripheral + bus or shared memory. diff --git a/drivers/bus/mhi/makefile b/drivers/bus/mhi/makefile --- /dev/null +++ b/drivers/bus/mhi/makefile +# core layer +obj-y += core/ diff --git a/drivers/bus/mhi/core/makefile b/drivers/bus/mhi/core/makefile --- /dev/null +++ b/drivers/bus/mhi/core/makefile +obj-$(config_mhi_bus) := mhi.o + +mhi-y := init.o diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- /dev/null +++ b/drivers/bus/mhi/core/init.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018-2020, the linux foundation. all rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/dma-direction.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/mhi.h> +#include <linux/mod_devicetable.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/vmalloc.h> +#include <linux/wait.h> +#include "internal.h" + +static int parse_ev_cfg(struct mhi_controller *mhi_cntrl, + struct mhi_controller_config *config) +{ + struct mhi_event *mhi_event; + struct mhi_event_config *event_cfg; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int i, num; + + num = config->num_events; + mhi_cntrl->total_ev_rings = num; + mhi_cntrl->mhi_event = kcalloc(num, sizeof(*mhi_cntrl->mhi_event), + gfp_kernel); + if (!mhi_cntrl->mhi_event) + return -enomem; + + /* populate event ring */ + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < num; i++) { + event_cfg = &config->event_cfg[i]; + + mhi_event->er_index = i; + mhi_event->ring.elements = event_cfg->num_elements; + mhi_event->intmod = event_cfg->irq_moderation_ms; + mhi_event->irq = event_cfg->irq; + + if (event_cfg->channel != u32_max) { + /* this event ring has a dedicated channel */ + mhi_event->chan = event_cfg->channel; + if (mhi_event->chan >= mhi_cntrl->max_chan) { + dev_err(dev, + "event ring channel not available "); + goto error_ev_cfg; + } + + mhi_event->mhi_chan = + &mhi_cntrl->mhi_chan[mhi_event->chan]; + } + + /* priority is fixed to 1 for now */ + mhi_event->priority = 1; + + mhi_event->db_cfg.brstmode = event_cfg->mode; + if (mhi_invalid_brstmode(mhi_event->db_cfg.brstmode)) + goto error_ev_cfg; + + mhi_event->data_type = event_cfg->data_type; + + mhi_event->hw_ring = event_cfg->hardware_event; + if (mhi_event->hw_ring) + mhi_cntrl->hw_ev_rings++; + else + mhi_cntrl->sw_ev_rings++; + + mhi_event->cl_manage = event_cfg->client_managed; + mhi_event->offload_ev = event_cfg->offload_channel; + mhi_event++; + } + + /* we need irq for each event ring + additional one for bhi */ + mhi_cntrl->nr_irqs_req = mhi_cntrl->total_ev_rings + 1; + + return 0; + +error_ev_cfg: + + kfree(mhi_cntrl->mhi_event); + return -einval; +} + +static int parse_ch_cfg(struct mhi_controller *mhi_cntrl, + struct mhi_controller_config *config) +{ + struct mhi_channel_config *ch_cfg; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int i; + u32 chan; + + mhi_cntrl->max_chan = config->max_channels; + + /* + * the allocation of mhi channels can exceed 32kb in some scenarios, + * so to avoid any memory possible allocation failures, vzalloc is + * used here + */ + mhi_cntrl->mhi_chan = vzalloc(mhi_cntrl->max_chan * + sizeof(*mhi_cntrl->mhi_chan)); + if (!mhi_cntrl->mhi_chan) + return -enomem; + + init_list_head(&mhi_cntrl->lpm_chans); + + /* populate channel configurations */ + for (i = 0; i < config->num_channels; i++) { + struct mhi_chan *mhi_chan; + + ch_cfg = &config->ch_cfg[i]; + + chan = ch_cfg->num; + if (chan >= mhi_cntrl->max_chan) { + dev_err(dev, "channel %d not available ", chan); + goto error_chan_cfg; + } + + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + mhi_chan->name = ch_cfg->name; + mhi_chan->chan = chan; + + mhi_chan->tre_ring.elements = ch_cfg->num_elements; + if (!mhi_chan->tre_ring.elements) + goto error_chan_cfg; + + /* + * for some channels, local ring length should be bigger than + * the transfer ring length due to internal logical channels + * in device. so host can queue much more buffers than transfer + * ring length. example, rsc channels should have a larger local + * channel length than transfer ring length. + */ + mhi_chan->buf_ring.elements = ch_cfg->local_elements; + if (!mhi_chan->buf_ring.elements) + mhi_chan->buf_ring.elements = mhi_chan->tre_ring.elements; + mhi_chan->er_index = ch_cfg->event_ring; + mhi_chan->dir = ch_cfg->dir; + + /* + * for most channels, chtype is identical to channel directions. + * so, if it is not defined then assign channel direction to + * chtype + */ + mhi_chan->type = ch_cfg->type; + if (!mhi_chan->type) + mhi_chan->type = (enum mhi_ch_type)mhi_chan->dir; + + mhi_chan->ee_mask = ch_cfg->ee_mask; + mhi_chan->db_cfg.pollcfg = ch_cfg->pollcfg; + mhi_chan->lpm_notify = ch_cfg->lpm_notify; + mhi_chan->offload_ch = ch_cfg->offload_channel; + mhi_chan->db_cfg.reset_req = ch_cfg->doorbell_mode_switch; + mhi_chan->pre_alloc = ch_cfg->auto_queue; + mhi_chan->auto_start = ch_cfg->auto_start; + + /* + * if mhi host allocates buffers, then the channel direction + * should be dma_from_device + */ + if (mhi_chan->pre_alloc && mhi_chan->dir != dma_from_device) { + dev_err(dev, "invalid channel configuration "); + goto error_chan_cfg; + } + + /* + * bi-directional and direction less channel must be an + * offload channel + */ + if ((mhi_chan->dir == dma_bidirectional || + mhi_chan->dir == dma_none) && !mhi_chan->offload_ch) { + dev_err(dev, "invalid channel configuration "); + goto error_chan_cfg; + } + + if (!mhi_chan->offload_ch) { + mhi_chan->db_cfg.brstmode = ch_cfg->doorbell; + if (mhi_invalid_brstmode(mhi_chan->db_cfg.brstmode)) { + dev_err(dev, "invalid door bell mode "); + goto error_chan_cfg; + } + } + + mhi_chan->configured = true; + + if (mhi_chan->lpm_notify) + list_add_tail(&mhi_chan->node, &mhi_cntrl->lpm_chans); + } + + return 0; + +error_chan_cfg: + vfree(mhi_cntrl->mhi_chan); + + return -einval; +} + +static int parse_config(struct mhi_controller *mhi_cntrl, + struct mhi_controller_config *config) +{ + int ret; + + /* parse mhi channel configuration */ + ret = parse_ch_cfg(mhi_cntrl, config); + if (ret) + return ret; + + /* parse mhi event configuration */ + ret = parse_ev_cfg(mhi_cntrl, config); + if (ret) + goto error_ev_cfg; + + mhi_cntrl->timeout_ms = config->timeout_ms; + if (!mhi_cntrl->timeout_ms) + mhi_cntrl->timeout_ms = mhi_timeout_ms; + + mhi_cntrl->bounce_buf = config->use_bounce_buf; + mhi_cntrl->buffer_len = config->buf_len; + if (!mhi_cntrl->buffer_len) + mhi_cntrl->buffer_len = mhi_max_mtu; + + return 0; + +error_ev_cfg: + vfree(mhi_cntrl->mhi_chan); + + return ret; +} + +int mhi_register_controller(struct mhi_controller *mhi_cntrl, + struct mhi_controller_config *config) +{ + int ret; + int i; + struct mhi_event *mhi_event; + struct mhi_chan *mhi_chan; + struct mhi_cmd *mhi_cmd; + struct mhi_device *mhi_dev; + + if (!mhi_cntrl) + return -einval; + + if (!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put) + return -einval; + + if (!mhi_cntrl->status_cb || !mhi_cntrl->link_status) + return -einval; + + ret = parse_config(mhi_cntrl, config); + if (ret) + return -einval; + + mhi_cntrl->mhi_cmd = kcalloc(nr_of_cmd_rings, + sizeof(*mhi_cntrl->mhi_cmd), gfp_kernel); + if (!mhi_cntrl->mhi_cmd) { + ret = -enomem; + goto error_alloc_cmd; + } + + init_list_head(&mhi_cntrl->transition_list); + spin_lock_init(&mhi_cntrl->transition_lock); + spin_lock_init(&mhi_cntrl->wlock); + init_waitqueue_head(&mhi_cntrl->state_event); + + mhi_cmd = mhi_cntrl->mhi_cmd; + for (i = 0; i < nr_of_cmd_rings; i++, mhi_cmd++) + spin_lock_init(&mhi_cmd->lock); + + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + /* skip for offload events */ + if (mhi_event->offload_ev) + continue; + + mhi_event->mhi_cntrl = mhi_cntrl; + spin_lock_init(&mhi_event->lock); + } + + mhi_chan = mhi_cntrl->mhi_chan; + for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { + mutex_init(&mhi_chan->mutex); + init_completion(&mhi_chan->completion); + rwlock_init(&mhi_chan->lock); + } + + /* register controller with mhi bus */ + mhi_dev = mhi_alloc_device(mhi_cntrl); + if (is_err(mhi_dev)) { + dev_err(mhi_cntrl->cntrl_dev, "failed to allocate mhi device "); + ret = ptr_err(mhi_dev); + goto error_alloc_dev; + } + + mhi_dev->dev_type = mhi_device_controller; + mhi_dev->mhi_cntrl = mhi_cntrl; + dev_set_name(&mhi_dev->dev, "%s", dev_name(mhi_cntrl->cntrl_dev)); + + /* init wakeup source */ + device_init_wakeup(&mhi_dev->dev, true); + + ret = device_add(&mhi_dev->dev); + if (ret) + goto error_add_dev; + + mhi_cntrl->mhi_dev = mhi_dev; + + return 0; + +error_add_dev: + put_device(&mhi_dev->dev); + +error_alloc_dev: + kfree(mhi_cntrl->mhi_cmd); + +error_alloc_cmd: + vfree(mhi_cntrl->mhi_chan); + kfree(mhi_cntrl->mhi_event); + + return ret; +} +export_symbol_gpl(mhi_register_controller); + +void mhi_unregister_controller(struct mhi_controller *mhi_cntrl) +{ + struct mhi_device *mhi_dev = mhi_cntrl->mhi_dev; + struct mhi_chan *mhi_chan = mhi_cntrl->mhi_chan; + unsigned int i; + + kfree(mhi_cntrl->mhi_cmd); + kfree(mhi_cntrl->mhi_event); + + /* drop the references to mhi devices created for channels */ + for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { + if (!mhi_chan->mhi_dev) + continue; + + put_device(&mhi_chan->mhi_dev->dev); + } + vfree(mhi_cntrl->mhi_chan); + + device_del(&mhi_dev->dev); + put_device(&mhi_dev->dev); +} +export_symbol_gpl(mhi_unregister_controller); + +static void mhi_release_device(struct device *dev) +{ + struct mhi_device *mhi_dev = to_mhi_device(dev); + + kfree(mhi_dev); +} + +struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl) +{ + struct mhi_device *mhi_dev; + struct device *dev; + + mhi_dev = kzalloc(sizeof(*mhi_dev), gfp_kernel); + if (!mhi_dev) + return err_ptr(-enomem); + + dev = &mhi_dev->dev; + device_initialize(dev); + dev->bus = &mhi_bus_type; + dev->release = mhi_release_device; + dev->parent = mhi_cntrl->cntrl_dev; + mhi_dev->mhi_cntrl = mhi_cntrl; + mhi_dev->dev_wake = 0; + + return mhi_dev; +} + +static int mhi_match(struct device *dev, struct device_driver *drv) +{ + return 0; +}; + +struct bus_type mhi_bus_type = { + .name = "mhi", + .dev_name = "mhi", + .match = mhi_match, +}; + +static int __init mhi_init(void) +{ + return bus_register(&mhi_bus_type); +} + +static void __exit mhi_exit(void) +{ + bus_unregister(&mhi_bus_type); +} + +postcore_initcall(mhi_init); +module_exit(mhi_exit); + +module_license("gpl v2"); +module_description("mhi host interface"); diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- /dev/null +++ b/drivers/bus/mhi/core/internal.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2018-2020, the linux foundation. all rights reserved. + * + */ + +#ifndef _mhi_int_h +#define _mhi_int_h + +#include <linux/mhi.h> + +extern struct bus_type mhi_bus_type; + +/* mhi transfer completion events */ +enum mhi_ev_ccs { + mhi_ev_cc_invalid = 0x0, + mhi_ev_cc_success = 0x1, + mhi_ev_cc_eot = 0x2, /* end of transfer event */ + mhi_ev_cc_overflow = 0x3, + mhi_ev_cc_eob = 0x4, /* end of block event */ + mhi_ev_cc_oob = 0x5, /* out of block event */ + mhi_ev_cc_db_mode = 0x6, + mhi_ev_cc_undefined_err = 0x10, + mhi_ev_cc_bad_tre = 0x11, +}; + +enum mhi_ch_state { + mhi_ch_state_disabled = 0x0, + mhi_ch_state_enabled = 0x1, + mhi_ch_state_running = 0x2, + mhi_ch_state_suspended = 0x3, + mhi_ch_state_stop = 0x4, + mhi_ch_state_error = 0x5, +}; + +#define mhi_invalid_brstmode(mode) (mode != mhi_db_brst_disable && \ + mode != mhi_db_brst_enable) + +#define nr_of_cmd_rings 1 +#define cmd_el_per_ring 128 +#define primary_cmd_ring 0 +#define mhi_max_mtu 0xffff + +enum mhi_er_type { + mhi_er_type_invalid = 0x0, + mhi_er_type_valid = 0x1, +}; + +struct db_cfg { + bool reset_req; + bool db_mode; + u32 pollcfg; + enum mhi_db_brst_mode brstmode; + dma_addr_t db_val; + void (*process_db)(struct mhi_controller *mhi_cntrl, + struct db_cfg *db_cfg, void __iomem *io_addr, + dma_addr_t db_val); +}; + +struct mhi_ring { + dma_addr_t dma_handle; + dma_addr_t iommu_base; + u64 *ctxt_wp; /* point to ctxt wp */ + void *pre_aligned; + void *base; + void *rp; + void *wp; + size_t el_size; + size_t len; + size_t elements; + size_t alloc_size; + void __iomem *db_addr; +}; + +struct mhi_cmd { + struct mhi_ring ring; + spinlock_t lock; +}; + +struct mhi_buf_info { + void *v_addr; + void *bb_addr; + void *wp; + void *cb_buf; + dma_addr_t p_addr; + size_t len; + enum dma_data_direction dir; +}; + +struct mhi_event { + struct mhi_controller *mhi_cntrl; + struct mhi_chan *mhi_chan; /* dedicated to channel */ + u32 er_index; + u32 intmod; + u32 irq; + int chan; /* this event ring is dedicated to a channel (optional) */ + u32 priority; + enum mhi_er_data_type data_type; + struct mhi_ring ring; + struct db_cfg db_cfg; + struct tasklet_struct task; + spinlock_t lock; + int (*process_event)(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, + u32 event_quota); + bool hw_ring; + bool cl_manage; + bool offload_ev; /* managed by a device driver */ +}; + +struct mhi_chan { + const char *name; + /* + * important: when consuming, increment tre_ring first and when + * releasing, decrement buf_ring first. if tre_ring has space, buf_ring + * is guranteed to have space so we do not need to check both rings. + */ + struct mhi_ring buf_ring; + struct mhi_ring tre_ring; + u32 chan; + u32 er_index; + u32 intmod; + enum mhi_ch_type type; + enum dma_data_direction dir; + struct db_cfg db_cfg; + enum mhi_ch_ee_mask ee_mask; + enum mhi_ch_state ch_state; + enum mhi_ev_ccs ccs; + struct mhi_device *mhi_dev; + void (*xfer_cb)(struct mhi_device *mhi_dev, struct mhi_result *result); + struct mutex mutex; + struct completion completion; + rwlock_t lock; + struct list_head node; + bool lpm_notify; + bool configured; + bool offload_ch; + bool pre_alloc; + bool auto_start; + bool wake_capable; +}; + +/* default mhi timeout */ +#define mhi_timeout_ms (1000) + +struct mhi_device *mhi_alloc_device(struct mhi_controller *mhi_cntrl); + +int mhi_destroy_device(struct device *dev, void *data); +void mhi_create_devices(struct mhi_controller *mhi_cntrl); + +#endif /* _mhi_int_h */ diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- /dev/null +++ b/include/linux/mhi.h +/* spdx-license-identifier: gpl-2.0 */ +/* + * copyright (c) 2018-2020, the linux foundation. all rights reserved. + * + */ +#ifndef _mhi_h_ +#define _mhi_h_ + +#include <linux/device.h> +#include <linux/dma-direction.h> +#include <linux/mutex.h> +#include <linux/rwlock_types.h> +#include <linux/slab.h> +#include <linux/spinlock_types.h> +#include <linux/wait.h> +#include <linux/workqueue.h> + +struct mhi_chan; +struct mhi_event; +struct mhi_ctxt; +struct mhi_cmd; +struct mhi_buf_info; + +/** + * enum mhi_callback - mhi callback + * @mhi_cb_idle: mhi entered idle state + * @mhi_cb_pending_data: new data available for client to process + * @mhi_cb_lpm_enter: mhi host entered low power mode + * @mhi_cb_lpm_exit: mhi host about to exit low power mode + * @mhi_cb_ee_rddm: mhi device entered rddm exec env + * @mhi_cb_ee_mission_mode: mhi device entered mission mode exec env + * @mhi_cb_sys_error: mhi device entered error state (may recover) + * @mhi_cb_fatal_error: mhi device entered fatal error state + */ +enum mhi_callback { + mhi_cb_idle, + mhi_cb_pending_data, + mhi_cb_lpm_enter, + mhi_cb_lpm_exit, + mhi_cb_ee_rddm, + mhi_cb_ee_mission_mode, + mhi_cb_sys_error, + mhi_cb_fatal_error, +}; + +/** + * enum mhi_flags - transfer flags + * @mhi_eob: end of buffer for bulk transfer + * @mhi_eot: end of transfer + * @mhi_chain: linked transfer + */ +enum mhi_flags { + mhi_eob, + mhi_eot, + mhi_chain, +}; + +/** + * enum mhi_device_type - device types + * @mhi_device_xfer: handles data transfer + * @mhi_device_controller: control device + */ +enum mhi_device_type { + mhi_device_xfer, + mhi_device_controller, +}; + +/** + * enum mhi_ch_type - channel types + * @mhi_ch_type_invalid: invalid channel type + * @mhi_ch_type_outbound: outbound channel to the device + * @mhi_ch_type_inbound: inbound channel from the device + * @mhi_ch_type_inbound_coalesced: coalesced channel for the device to combine + * multiple packets and send them as a single + * large packet to reduce cpu consumption + */ +enum mhi_ch_type { + mhi_ch_type_invalid = 0, + mhi_ch_type_outbound = dma_to_device, + mhi_ch_type_inbound = dma_from_device, + mhi_ch_type_inbound_coalesced = 3, +}; + +/** + * enum mhi_ee_type - execution environment types + * @mhi_ee_pbl: primary bootloader + * @mhi_ee_sbl: secondary bootloader + * @mhi_ee_amss: modem, aka the primary runtime ee + * @mhi_ee_rddm: ram dump download mode + * @mhi_ee_wfw: wlan firmware mode + * @mhi_ee_pthru: passthrough + * @mhi_ee_edl: embedded downloader + */ +enum mhi_ee_type { + mhi_ee_pbl, + mhi_ee_sbl, + mhi_ee_amss, + mhi_ee_rddm, + mhi_ee_wfw, + mhi_ee_pthru, + mhi_ee_edl, + mhi_ee_max_supported = mhi_ee_edl, + mhi_ee_disable_transition, /* local ee, not related to mhi spec */ + mhi_ee_not_supported, + mhi_ee_max, +}; + +/** + * enum mhi_ch_ee_mask - execution environment mask for channel + * @mhi_ch_ee_pbl: allow channel to be used in pbl ee + * @mhi_ch_ee_sbl: allow channel to be used in sbl ee + * @mhi_ch_ee_amss: allow channel to be used in amss ee + * @mhi_ch_ee_rddm: allow channel to be used in rddm ee + * @mhi_ch_ee_pthru: allow channel to be used in pthru ee + * @mhi_ch_ee_wfw: allow channel to be used in wfw ee + * @mhi_ch_ee_edl: allow channel to be used in edl ee + */ +enum mhi_ch_ee_mask { + mhi_ch_ee_pbl = bit(mhi_ee_pbl), + mhi_ch_ee_sbl = bit(mhi_ee_sbl), + mhi_ch_ee_amss = bit(mhi_ee_amss), + mhi_ch_ee_rddm = bit(mhi_ee_rddm), + mhi_ch_ee_pthru = bit(mhi_ee_pthru), + mhi_ch_ee_wfw = bit(mhi_ee_wfw), + mhi_ch_ee_edl = bit(mhi_ee_edl), +}; + +/** + * enum mhi_er_data_type - event ring data types + * @mhi_er_data: only client data over this ring + * @mhi_er_ctrl: mhi control data and client data + */ +enum mhi_er_data_type { + mhi_er_data, + mhi_er_ctrl, +}; + +/** + * enum mhi_db_brst_mode - doorbell mode + * @mhi_db_brst_disable: burst mode disable + * @mhi_db_brst_enable: burst mode enable + */ +enum mhi_db_brst_mode { + mhi_db_brst_disable = 0x2, + mhi_db_brst_enable = 0x3, +}; + +/** + * struct mhi_channel_config - channel configuration structure for controller + * @name: the name of this channel + * @num: the number assigned to this channel + * @num_elements: the number of elements that can be queued to this channel + * @local_elements: the local ring length of the channel + * @event_ring: the event rung index that services this channel + * @dir: direction that data may flow on this channel + * @type: channel type + * @ee_mask: execution environment mask for this channel + * @pollcfg: polling configuration for burst mode. 0 is default. milliseconds + for ul channels, multiple of 8 ring elements for dl channels + * @doorbell: doorbell mode + * @lpm_notify: the channel master requires low power mode notifications + * @offload_channel: the client manages the channel completely + * @doorbell_mode_switch: channel switches to doorbell mode on m0 transition + * @auto_queue: framework will automatically queue buffers for dl traffic + * @auto_start: automatically start (open) this channel + */ +struct mhi_channel_config { + char *name; + u32 num; + u32 num_elements; + u32 local_elements; + u32 event_ring; + enum dma_data_direction dir; + enum mhi_ch_type type; + u32 ee_mask; + u32 pollcfg; + enum mhi_db_brst_mode doorbell; + bool lpm_notify; + bool offload_channel; + bool doorbell_mode_switch; + bool auto_queue; + bool auto_start; +}; + +/** + * struct mhi_event_config - event ring configuration structure for controller + * @num_elements: the number of elements that can be queued to this ring + * @irq_moderation_ms: delay irq for additional events to be aggregated + * @irq: irq associated with this ring + * @channel: dedicated channel number. u32_max indicates a non-dedicated ring + * @priority: priority of this ring. use 1 for now + * @mode: doorbell mode + * @data_type: type of data this ring will process + * @hardware_event: this ring is associated with hardware channels + * @client_managed: this ring is client managed + * @offload_channel: this ring is associated with an offloaded channel + */ +struct mhi_event_config { + u32 num_elements; + u32 irq_moderation_ms; + u32 irq; + u32 channel; + u32 priority; + enum mhi_db_brst_mode mode; + enum mhi_er_data_type data_type; + bool hardware_event; + bool client_managed; + bool offload_channel; +}; + +/** + * struct mhi_controller_config - root mhi controller configuration + * @max_channels: maximum number of channels supported + * @timeout_ms: timeout value for operations. 0 means use default + * @buf_len: size of automatically allocated buffers. 0 means use default + * @num_channels: number of channels defined in @ch_cfg + * @ch_cfg: array of defined channels + * @num_events: number of event rings defined in @event_cfg + * @event_cfg: array of defined event rings + * @use_bounce_buf: use a bounce buffer pool due to limited ddr access + * @m2_no_db: host is not allowed to ring db in m2 state + */ +struct mhi_controller_config { + u32 max_channels; + u32 timeout_ms; + u32 buf_len; + u32 num_channels; + struct mhi_channel_config *ch_cfg; + u32 num_events; + struct mhi_event_config *event_cfg; + bool use_bounce_buf; + bool m2_no_db; +}; + +/** + * struct mhi_controller - master mhi controller structure + * @cntrl_dev: pointer to the struct device of physical bus acting as the mhi + * controller (required) + * @mhi_dev: mhi device instance for the controller + * @regs: base address of mhi mmio register space (required) + * @iova_start: iommu starting address for data (required) + * @iova_stop: iommu stop address for data (required) + * @fw_image: firmware image name for normal booting (required) + * @edl_image: firmware image name for emergency download mode (optional) + * @sbl_size: sbl image size downloaded through bhie (optional) + * @seg_len: bhie vector size (optional) + * @mhi_chan: points to the channel configuration table + * @lpm_chans: list of channels that require lpm notifications + * @irq: base irq # to request (required) + * @max_chan: maximum number of channels the controller supports + * @total_ev_rings: total # of event rings allocated + * @hw_ev_rings: number of hardware event rings + * @sw_ev_rings: number of software event rings + * @nr_irqs_req: number of irqs required to operate (optional) + * @nr_irqs: number of irq allocated by bus master (required) + * @mhi_event: mhi event ring configurations table + * @mhi_cmd: mhi command ring configurations table + * @mhi_ctxt: mhi device context, shared memory between host and device + * @pm_mutex: mutex for suspend/resume operation + * @pm_lock: lock for protecting mhi power management state + * @timeout_ms: timeout in ms for state transitions + * @pm_state: mhi power management state + * @db_access: db access states + * @ee: mhi device execution environment + * @dev_wake: device wakeup count + * @pending_pkts: pending packets for the controller + * @transition_list: list of mhi state transitions + * @transition_lock: lock for protecting mhi state transition list + * @wlock: lock for protecting device wakeup + * @st_worker: state transition worker + * @fw_worker: firmware download worker + * @syserr_worker: system error worker + * @state_event: state change event + * @status_cb: cb function to notify power states of the device (required) + * @link_status: cb function to query link status of the device (required) + * @wake_get: cb function to assert device wake (optional) + * @wake_put: cb function to de-assert device wake (optional) + * @wake_toggle: cb function to assert and de-assert device wake (optional) + * @runtime_get: cb function to controller runtime resume (required) + * @runtimet_put: cb function to decrement pm usage (required) + * @buffer_len: bounce buffer length + * @bounce_buf: use of bounce buffer + * @fbc_download: mhi host needs to do complete image transfer (optional) + * @pre_init: mhi host needs to do pre-initialization before power up + * @wake_set: device wakeup set flag + * + * fields marked as (required) need to be populated by the controller driver + * before calling mhi_register_controller(). for the fields marked as (optional) + * they can be populated depending on the usecase. + */ +struct mhi_controller { + struct device *cntrl_dev; + struct mhi_device *mhi_dev; + void __iomem *regs; + dma_addr_t iova_start; + dma_addr_t iova_stop; + const char *fw_image; + const char *edl_image; + size_t sbl_size; + size_t seg_len; + struct mhi_chan *mhi_chan; + struct list_head lpm_chans; + int *irq; + u32 max_chan; + u32 total_ev_rings; + u32 hw_ev_rings; + u32 sw_ev_rings; + u32 nr_irqs_req; + u32 nr_irqs; + + struct mhi_event *mhi_event; + struct mhi_cmd *mhi_cmd; + struct mhi_ctxt *mhi_ctxt; + + struct mutex pm_mutex; + rwlock_t pm_lock; + u32 timeout_ms; + u32 pm_state; + u32 db_access; + enum mhi_ee_type ee; + atomic_t dev_wake; + atomic_t pending_pkts; + struct list_head transition_list; + spinlock_t transition_lock; + spinlock_t wlock; + struct work_struct st_worker; + struct work_struct fw_worker; + struct work_struct syserr_worker; + wait_queue_head_t state_event; + + void (*status_cb)(struct mhi_controller *mhi_cntrl, + enum mhi_callback cb); + int (*link_status)(struct mhi_controller *mhi_cntrl); + void (*wake_get)(struct mhi_controller *mhi_cntrl, bool override); + void (*wake_put)(struct mhi_controller *mhi_cntrl, bool override); + void (*wake_toggle)(struct mhi_controller *mhi_cntrl); + int (*runtime_get)(struct mhi_controller *mhi_cntrl); + void (*runtime_put)(struct mhi_controller *mhi_cntrl); + + size_t buffer_len; + bool bounce_buf; + bool fbc_download; + bool pre_init; + bool wake_set; +}; + +/** + * struct mhi_device - structure representing a mhi device which binds + * to channels + * @id: pointer to mhi device id struct + * @chan_name: name of the channel to which the device binds + * @mhi_cntrl: controller the device belongs to + * @ul_chan: ul channel for the device + * @dl_chan: dl channel for the device + * @dev: driver model device node for the mhi device + * @dev_type: mhi device type + * @dev_wake: device wakeup counter + */ +struct mhi_device { + const struct mhi_device_id *id; + const char *chan_name; + struct mhi_controller *mhi_cntrl; + struct mhi_chan *ul_chan; + struct mhi_chan *dl_chan; + struct device dev; + enum mhi_device_type dev_type; + u32 dev_wake; +}; + +/** + * struct mhi_result - completed buffer information + * @buf_addr: address of data buffer + * @bytes_xferd: # of bytes transferred + * @dir: channel direction + * @transaction_status: status of last transaction + */ +struct mhi_result { + void *buf_addr; + size_t bytes_xferd; + enum dma_data_direction dir; + int transaction_status; +}; + +#define to_mhi_device(dev) container_of(dev, struct mhi_device, dev) + +/** + * mhi_register_controller - register mhi controller + * @mhi_cntrl: mhi controller to register + * @config: configuration to use for the controller + */ +int mhi_register_controller(struct mhi_controller *mhi_cntrl, + struct mhi_controller_config *config); + +/** + * mhi_unregister_controller - unregister mhi controller + * @mhi_cntrl: mhi controller to unregister + */ +void mhi_unregister_controller(struct mhi_controller *mhi_cntrl); + +#endif /* _mhi_h_ */ diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h +#define mhi_name_size 32 + +/** + * struct mhi_device_id - mhi device identification + * @chan: mhi channel name + * @driver_data: driver data; + */ +struct mhi_device_id { + const char chan[mhi_name_size]; + kernel_ulong_t driver_data; +}; +
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Modem Host Interface (MHI) Bus
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0cbf260820fa780a336e4a08cce1f81cd66a7ac1
|
manivannan sadhasivam
|
drivers
|
bus
|
core, mhi
|
bus: mhi: core: add support for registering mhi client drivers
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this commit adds support for registering mhi client drivers with the mhi stack. mhi client drivers binds to one or more mhi devices inorder to sends and receive the upper-layer protocol packets like ip packets, modem control messages, and diagnostics messages over mhi bus.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
|
['h', 'c']
| 2
| 188
| 0
|
--- diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c +static int mhi_driver_probe(struct device *dev) +{ + struct mhi_device *mhi_dev = to_mhi_device(dev); + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct device_driver *drv = dev->driver; + struct mhi_driver *mhi_drv = to_mhi_driver(drv); + struct mhi_event *mhi_event; + struct mhi_chan *ul_chan = mhi_dev->ul_chan; + struct mhi_chan *dl_chan = mhi_dev->dl_chan; + + if (ul_chan) { + /* + * if channel supports lpm notifications then status_cb should + * be provided + */ + if (ul_chan->lpm_notify && !mhi_drv->status_cb) + return -einval; + + /* for non-offload channels then xfer_cb should be provided */ + if (!ul_chan->offload_ch && !mhi_drv->ul_xfer_cb) + return -einval; + + ul_chan->xfer_cb = mhi_drv->ul_xfer_cb; + } + + if (dl_chan) { + /* + * if channel supports lpm notifications then status_cb should + * be provided + */ + if (dl_chan->lpm_notify && !mhi_drv->status_cb) + return -einval; + + /* for non-offload channels then xfer_cb should be provided */ + if (!dl_chan->offload_ch && !mhi_drv->dl_xfer_cb) + return -einval; + + mhi_event = &mhi_cntrl->mhi_event[dl_chan->er_index]; + + /* + * if the channel event ring is managed by client, then + * status_cb must be provided so that the framework can + * notify pending data + */ + if (mhi_event->cl_manage && !mhi_drv->status_cb) + return -einval; + + dl_chan->xfer_cb = mhi_drv->dl_xfer_cb; + } + + /* call the user provided probe function */ + return mhi_drv->probe(mhi_dev, mhi_dev->id); +} + +static int mhi_driver_remove(struct device *dev) +{ + struct mhi_device *mhi_dev = to_mhi_device(dev); + struct mhi_driver *mhi_drv = to_mhi_driver(dev->driver); + struct mhi_chan *mhi_chan; + enum mhi_ch_state ch_state[] = { + mhi_ch_state_disabled, + mhi_ch_state_disabled + }; + int dir; + + /* skip if it is a controller device */ + if (mhi_dev->dev_type == mhi_device_controller) + return 0; + + /* reset both channels */ + for (dir = 0; dir < 2; dir++) { + mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; + + if (!mhi_chan) + continue; + + /* wake all threads waiting for completion */ + write_lock_irq(&mhi_chan->lock); + mhi_chan->ccs = mhi_ev_cc_invalid; + complete_all(&mhi_chan->completion); + write_unlock_irq(&mhi_chan->lock); + + /* set the channel state to disabled */ + mutex_lock(&mhi_chan->mutex); + write_lock_irq(&mhi_chan->lock); + ch_state[dir] = mhi_chan->ch_state; + mhi_chan->ch_state = mhi_ch_state_suspended; + write_unlock_irq(&mhi_chan->lock); + + mutex_unlock(&mhi_chan->mutex); + } + + mhi_drv->remove(mhi_dev); + + /* de-init channel if it was enabled */ + for (dir = 0; dir < 2; dir++) { + mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; + + if (!mhi_chan) + continue; + + mutex_lock(&mhi_chan->mutex); + + mhi_chan->ch_state = mhi_ch_state_disabled; + + mutex_unlock(&mhi_chan->mutex); + } + + return 0; +} + +int mhi_driver_register(struct mhi_driver *mhi_drv) +{ + struct device_driver *driver = &mhi_drv->driver; + + if (!mhi_drv->probe || !mhi_drv->remove) + return -einval; + + driver->bus = &mhi_bus_type; + driver->probe = mhi_driver_probe; + driver->remove = mhi_driver_remove; + + return driver_register(driver); +} +export_symbol_gpl(mhi_driver_register); + +void mhi_driver_unregister(struct mhi_driver *mhi_drv) +{ + driver_unregister(&mhi_drv->driver); +} +export_symbol_gpl(mhi_driver_unregister); + + struct mhi_device *mhi_dev = to_mhi_device(dev); + struct mhi_driver *mhi_drv = to_mhi_driver(drv); + const struct mhi_device_id *id; + + /* + * if the device is a controller type then there is no client driver + * associated with it + */ + if (mhi_dev->dev_type == mhi_device_controller) + return 0; + + for (id = mhi_drv->id_table; id->chan[0]; id++) + if (!strcmp(mhi_dev->chan_name, id->chan)) { + mhi_dev->id = id; + return 1; + } + diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h + * @ul_chan_id: mhi channel id for ul transfer + * @dl_chan_id: mhi channel id for dl transfer + int ul_chan_id; + int dl_chan_id; +/** + * struct mhi_driver - structure representing a mhi client driver + * @probe: cb function for client driver probe function + * @remove: cb function for client driver remove function + * @ul_xfer_cb: cb function for ul data transfer + * @dl_xfer_cb: cb function for dl data transfer + * @status_cb: cb functions for asynchronous status + * @driver: device driver model driver + */ +struct mhi_driver { + const struct mhi_device_id *id_table; + int (*probe)(struct mhi_device *mhi_dev, + const struct mhi_device_id *id); + void (*remove)(struct mhi_device *mhi_dev); + void (*ul_xfer_cb)(struct mhi_device *mhi_dev, + struct mhi_result *result); + void (*dl_xfer_cb)(struct mhi_device *mhi_dev, + struct mhi_result *result); + void (*status_cb)(struct mhi_device *mhi_dev, enum mhi_callback mhi_cb); + struct device_driver driver; +}; + +#define to_mhi_driver(drv) container_of(drv, struct mhi_driver, driver) +/** + * mhi_driver_register - register driver with mhi framework + * @mhi_drv: driver associated with the device + */ +int mhi_driver_register(struct mhi_driver *mhi_drv); + +/** + * mhi_driver_unregister - unregister a driver for mhi_devices + * @mhi_drv: driver associated with the device + */ +void mhi_driver_unregister(struct mhi_driver *mhi_drv); +
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Modem Host Interface (MHI) Bus
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e755cadb0171ce78b29b89fe8bdd0179121a7827
|
manivannan sadhasivam
|
include
|
linux
|
core, mhi
|
bus: mhi: core: add support for creating and destroying mhi devices
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this commit adds support for creating and destroying mhi devices. the mhi devices binds to the mhi channels and are used to transfer data between mhi host and client device.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c', 'makefile']
| 3
| 126
| 1
|
--- diff --git a/drivers/bus/mhi/core/makefile b/drivers/bus/mhi/core/makefile --- a/drivers/bus/mhi/core/makefile +++ b/drivers/bus/mhi/core/makefile -mhi-y := init.o +mhi-y := init.o main.o diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c --- /dev/null +++ b/drivers/bus/mhi/core/main.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018-2020, the linux foundation. all rights reserved. + * + */ + +#include <linux/device.h> +#include <linux/dma-direction.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/mhi.h> +#include <linux/module.h> +#include <linux/skbuff.h> +#include <linux/slab.h> +#include "internal.h" + +int mhi_destroy_device(struct device *dev, void *data) +{ + struct mhi_device *mhi_dev; + struct mhi_controller *mhi_cntrl; + + if (dev->bus != &mhi_bus_type) + return 0; + + mhi_dev = to_mhi_device(dev); + mhi_cntrl = mhi_dev->mhi_cntrl; + + /* only destroy virtual devices thats attached to bus */ + if (mhi_dev->dev_type == mhi_device_controller) + return 0; + + dev_dbg(&mhi_cntrl->mhi_dev->dev, "destroy device for chan:%s ", + mhi_dev->chan_name); + + /* notify the client and remove the device from mhi bus */ + device_del(dev); + put_device(dev); + + return 0; +} + +static void mhi_notify(struct mhi_device *mhi_dev, enum mhi_callback cb_reason) +{ + struct mhi_driver *mhi_drv; + + if (!mhi_dev->dev.driver) + return; + + mhi_drv = to_mhi_driver(mhi_dev->dev.driver); + + if (mhi_drv->status_cb) + mhi_drv->status_cb(mhi_dev, cb_reason); +} + +/* bind mhi channels to mhi devices */ +void mhi_create_devices(struct mhi_controller *mhi_cntrl) +{ + struct mhi_chan *mhi_chan; + struct mhi_device *mhi_dev; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int i, ret; + + mhi_chan = mhi_cntrl->mhi_chan; + for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { + if (!mhi_chan->configured || mhi_chan->mhi_dev || + !(mhi_chan->ee_mask & bit(mhi_cntrl->ee))) + continue; + mhi_dev = mhi_alloc_device(mhi_cntrl); + if (!mhi_dev) + return; + + mhi_dev->dev_type = mhi_device_xfer; + switch (mhi_chan->dir) { + case dma_to_device: + mhi_dev->ul_chan = mhi_chan; + mhi_dev->ul_chan_id = mhi_chan->chan; + break; + case dma_from_device: + /* we use dl_chan as offload channels */ + mhi_dev->dl_chan = mhi_chan; + mhi_dev->dl_chan_id = mhi_chan->chan; + break; + default: + dev_err(dev, "direction not supported "); + put_device(&mhi_dev->dev); + return; + } + + get_device(&mhi_dev->dev); + mhi_chan->mhi_dev = mhi_dev; + + /* check next channel if it matches */ + if ((i + 1) < mhi_cntrl->max_chan && mhi_chan[1].configured) { + if (!strcmp(mhi_chan[1].name, mhi_chan->name)) { + i++; + mhi_chan++; + if (mhi_chan->dir == dma_to_device) { + mhi_dev->ul_chan = mhi_chan; + mhi_dev->ul_chan_id = mhi_chan->chan; + } else { + mhi_dev->dl_chan = mhi_chan; + mhi_dev->dl_chan_id = mhi_chan->chan; + } + get_device(&mhi_dev->dev); + mhi_chan->mhi_dev = mhi_dev; + } + } + + /* channel name is same for both ul and dl */ + mhi_dev->chan_name = mhi_chan->name; + dev_set_name(&mhi_dev->dev, "%04x_%s", mhi_chan->chan, + mhi_dev->chan_name); + + /* init wakeup source if available */ + if (mhi_dev->dl_chan && mhi_dev->dl_chan->wake_capable) + device_init_wakeup(&mhi_dev->dev, true); + + ret = device_add(&mhi_dev->dev); + if (ret) + put_device(&mhi_dev->dev); + } +} diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h + * @wake-capable: channel capable of waking up the system + bool wake_capable;
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Modem Host Interface (MHI) Bus
|
da1c4f85692476ab038e3279209f07b8f4b7641e
|
manivannan sadhasivam
|
include
|
linux
|
core, mhi
|
bus: mhi: core: add support for ringing channel/event ring doorbells
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this commit adds support for ringing channel and event ring doorbells by mhi host. the mhi host can use the channel and event ring doorbells for notifying the client device about processing transfer and event rings which it has queued using mmio registers.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
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['h', 'c']
| 4
| 545
| 0
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--- diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c +int mhi_init_mmio(struct mhi_controller *mhi_cntrl) +{ + u32 val; + int i, ret; + struct mhi_chan *mhi_chan; + struct mhi_event *mhi_event; + void __iomem *base = mhi_cntrl->regs; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + struct { + u32 offset; + u32 mask; + u32 shift; + u32 val; + } reg_info[] = { + { + ccabap_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr), + }, + { + ccabap_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->mhi_ctxt->chan_ctxt_addr), + }, + { + ecabap_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr), + }, + { + ecabap_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->mhi_ctxt->er_ctxt_addr), + }, + { + crcbap_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr), + }, + { + crcbap_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->mhi_ctxt->cmd_ctxt_addr), + }, + { + mhicfg, mhicfg_ner_mask, mhicfg_ner_shift, + mhi_cntrl->total_ev_rings, + }, + { + mhicfg, mhicfg_nhwer_mask, mhicfg_nhwer_shift, + mhi_cntrl->hw_ev_rings, + }, + { + mhictrlbase_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->iova_start), + }, + { + mhictrlbase_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->iova_start), + }, + { + mhidatabase_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->iova_start), + }, + { + mhidatabase_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->iova_start), + }, + { + mhictrllimit_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->iova_stop), + }, + { + mhictrllimit_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->iova_stop), + }, + { + mhidatalimit_higher, u32_max, 0, + upper_32_bits(mhi_cntrl->iova_stop), + }, + { + mhidatalimit_lower, u32_max, 0, + lower_32_bits(mhi_cntrl->iova_stop), + }, + { 0, 0, 0 } + }; + + dev_dbg(dev, "initializing mhi registers "); + + /* read channel db offset */ + ret = mhi_read_reg_field(mhi_cntrl, base, chdboff, chdboff_chdboff_mask, + chdboff_chdboff_shift, &val); + if (ret) { + dev_err(dev, "unable to read chdboff register "); + return -eio; + } + + /* setup wake db */ + mhi_cntrl->wake_db = base + val + (8 * mhi_dev_wake_db); + mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0); + mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0); + mhi_cntrl->wake_set = false; + + /* setup channel db address for each channel in tre_ring */ + mhi_chan = mhi_cntrl->mhi_chan; + for (i = 0; i < mhi_cntrl->max_chan; i++, val += 8, mhi_chan++) + mhi_chan->tre_ring.db_addr = base + val; + + /* read event ring db offset */ + ret = mhi_read_reg_field(mhi_cntrl, base, erdboff, erdboff_erdboff_mask, + erdboff_erdboff_shift, &val); + if (ret) { + dev_err(dev, "unable to read erdboff register "); + return -eio; + } + + /* setup event db address for each ev_ring */ + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, val += 8, mhi_event++) { + if (mhi_event->offload_ev) + continue; + + mhi_event->ring.db_addr = base + val; + } + + /* setup db register for primary cmd rings */ + mhi_cntrl->mhi_cmd[primary_cmd_ring].ring.db_addr = base + crdb_lower; + + /* write to mmio registers */ + for (i = 0; reg_info[i].offset; i++) + mhi_write_reg_field(mhi_cntrl, base, reg_info[i].offset, + reg_info[i].mask, reg_info[i].shift, + reg_info[i].val); + + return 0; +} + + if (mhi_event->db_cfg.brstmode == mhi_db_brst_enable) + mhi_event->db_cfg.process_db = mhi_db_brstmode; + else + mhi_event->db_cfg.process_db = mhi_db_brstmode_disable; + + if (mhi_chan->db_cfg.brstmode == mhi_db_brst_enable) + mhi_chan->db_cfg.process_db = mhi_db_brstmode; + else + mhi_chan->db_cfg.process_db = mhi_db_brstmode_disable; + diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h +/* mhi mmio register mapping */ +#define pci_invalid_read(val) (val == u32_max) + +#define mhireglen (0x0) +#define mhireglen_mhireglen_mask (0xffffffff) +#define mhireglen_mhireglen_shift (0) + +#define mhiver (0x8) +#define mhiver_mhiver_mask (0xffffffff) +#define mhiver_mhiver_shift (0) + +#define mhicfg (0x10) +#define mhicfg_nhwer_mask (0xff000000) +#define mhicfg_nhwer_shift (24) +#define mhicfg_ner_mask (0xff0000) +#define mhicfg_ner_shift (16) +#define mhicfg_nhwch_mask (0xff00) +#define mhicfg_nhwch_shift (8) +#define mhicfg_nch_mask (0xff) +#define mhicfg_nch_shift (0) + +#define chdboff (0x18) +#define chdboff_chdboff_mask (0xffffffff) +#define chdboff_chdboff_shift (0) + +#define erdboff (0x20) +#define erdboff_erdboff_mask (0xffffffff) +#define erdboff_erdboff_shift (0) + +#define bhioff (0x28) +#define bhioff_bhioff_mask (0xffffffff) +#define bhioff_bhioff_shift (0) + +#define bhieoff (0x2c) +#define bhieoff_bhieoff_mask (0xffffffff) +#define bhieoff_bhieoff_shift (0) + +#define debugoff (0x30) +#define debugoff_debugoff_mask (0xffffffff) +#define debugoff_debugoff_shift (0) + +#define mhictrl (0x38) +#define mhictrl_mhistate_mask (0x0000ff00) +#define mhictrl_mhistate_shift (8) +#define mhictrl_reset_mask (0x2) +#define mhictrl_reset_shift (1) + +#define mhistatus (0x48) +#define mhistatus_mhistate_mask (0x0000ff00) +#define mhistatus_mhistate_shift (8) +#define mhistatus_syserr_mask (0x4) +#define mhistatus_syserr_shift (2) +#define mhistatus_ready_mask (0x1) +#define mhistatus_ready_shift (0) + +#define ccabap_lower (0x58) +#define ccabap_lower_ccabap_lower_mask (0xffffffff) +#define ccabap_lower_ccabap_lower_shift (0) + +#define ccabap_higher (0x5c) +#define ccabap_higher_ccabap_higher_mask (0xffffffff) +#define ccabap_higher_ccabap_higher_shift (0) + +#define ecabap_lower (0x60) +#define ecabap_lower_ecabap_lower_mask (0xffffffff) +#define ecabap_lower_ecabap_lower_shift (0) + +#define ecabap_higher (0x64) +#define ecabap_higher_ecabap_higher_mask (0xffffffff) +#define ecabap_higher_ecabap_higher_shift (0) + +#define crcbap_lower (0x68) +#define crcbap_lower_crcbap_lower_mask (0xffffffff) +#define crcbap_lower_crcbap_lower_shift (0) + +#define crcbap_higher (0x6c) +#define crcbap_higher_crcbap_higher_mask (0xffffffff) +#define crcbap_higher_crcbap_higher_shift (0) + +#define crdb_lower (0x70) +#define crdb_lower_crdb_lower_mask (0xffffffff) +#define crdb_lower_crdb_lower_shift (0) + +#define crdb_higher (0x74) +#define crdb_higher_crdb_higher_mask (0xffffffff) +#define crdb_higher_crdb_higher_shift (0) + +#define mhictrlbase_lower (0x80) +#define mhictrlbase_lower_mhictrlbase_lower_mask (0xffffffff) +#define mhictrlbase_lower_mhictrlbase_lower_shift (0) + +#define mhictrlbase_higher (0x84) +#define mhictrlbase_higher_mhictrlbase_higher_mask (0xffffffff) +#define mhictrlbase_higher_mhictrlbase_higher_shift (0) + +#define mhictrllimit_lower (0x88) +#define mhictrllimit_lower_mhictrllimit_lower_mask (0xffffffff) +#define mhictrllimit_lower_mhictrllimit_lower_shift (0) + +#define mhictrllimit_higher (0x8c) +#define mhictrllimit_higher_mhictrllimit_higher_mask (0xffffffff) +#define mhictrllimit_higher_mhictrllimit_higher_shift (0) + +#define mhidatabase_lower (0x98) +#define mhidatabase_lower_mhidatabase_lower_mask (0xffffffff) +#define mhidatabase_lower_mhidatabase_lower_shift (0) + +#define mhidatabase_higher (0x9c) +#define mhidatabase_higher_mhidatabase_higher_mask (0xffffffff) +#define mhidatabase_higher_mhidatabase_higher_shift (0) + +#define mhidatalimit_lower (0xa0) +#define mhidatalimit_lower_mhidatalimit_lower_mask (0xffffffff) +#define mhidatalimit_lower_mhidatalimit_lower_shift (0) + +#define mhidatalimit_higher (0xa4) +#define mhidatalimit_higher_mhidatalimit_higher_mask (0xffffffff) +#define mhidatalimit_higher_mhidatalimit_higher_shift (0) + +/* host request register */ +#define mhi_soc_reset_req_offset (0xb0) +#define mhi_soc_reset_req bit(0) + +/* mhi bhi offfsets */ +#define bhi_bhiversion_minor (0x00) +#define bhi_bhiversion_major (0x04) +#define bhi_imgaddr_low (0x08) +#define bhi_imgaddr_high (0x0c) +#define bhi_imgsize (0x10) +#define bhi_rsvd1 (0x14) +#define bhi_imgtxdb (0x18) +#define bhi_txdb_seqnum_bmsk (0x3fffffff) +#define bhi_txdb_seqnum_shft (0) +#define bhi_rsvd2 (0x1c) +#define bhi_intvec (0x20) +#define bhi_rsvd3 (0x24) +#define bhi_execenv (0x28) +#define bhi_status (0x2c) +#define bhi_errcode (0x30) +#define bhi_errdbg1 (0x34) +#define bhi_errdbg2 (0x38) +#define bhi_errdbg3 (0x3c) +#define bhi_serialnu (0x40) +#define bhi_sblantirollver (0x44) +#define bhi_numseg (0x48) +#define bhi_msmhwid(n) (0x4c + (0x4 * n)) +#define bhi_oempkhash(n) (0x64 + (0x4 * n)) +#define bhi_rsvd5 (0xc4) +#define bhi_status_mask (0xc0000000) +#define bhi_status_shift (30) +#define bhi_status_error (3) +#define bhi_status_success (2) +#define bhi_status_reset (0) + +/* mhi bhie offsets */ +#define bhie_msmsocid_offs (0x0000) +#define bhie_txvecaddr_low_offs (0x002c) +#define bhie_txvecaddr_high_offs (0x0030) +#define bhie_txvecsize_offs (0x0034) +#define bhie_txvecdb_offs (0x003c) +#define bhie_txvecdb_seqnum_bmsk (0x3fffffff) +#define bhie_txvecdb_seqnum_shft (0) +#define bhie_txvecstatus_offs (0x0044) +#define bhie_txvecstatus_seqnum_bmsk (0x3fffffff) +#define bhie_txvecstatus_seqnum_shft (0) +#define bhie_txvecstatus_status_bmsk (0xc0000000) +#define bhie_txvecstatus_status_shft (30) +#define bhie_txvecstatus_status_reset (0x00) +#define bhie_txvecstatus_status_xfer_compl (0x02) +#define bhie_txvecstatus_status_error (0x03) +#define bhie_rxvecaddr_low_offs (0x0060) +#define bhie_rxvecaddr_high_offs (0x0064) +#define bhie_rxvecsize_offs (0x0068) +#define bhie_rxvecdb_offs (0x0070) +#define bhie_rxvecdb_seqnum_bmsk (0x3fffffff) +#define bhie_rxvecdb_seqnum_shft (0) +#define bhie_rxvecstatus_offs (0x0078) +#define bhie_rxvecstatus_seqnum_bmsk (0x3fffffff) +#define bhie_rxvecstatus_seqnum_shft (0) +#define bhie_rxvecstatus_status_bmsk (0xc0000000) +#define bhie_rxvecstatus_status_shft (30) +#define bhie_rxvecstatus_status_reset (0x00) +#define bhie_rxvecstatus_status_xfer_compl (0x02) +#define bhie_rxvecstatus_status_error (0x03) + +#define ev_ctx_reserved_mask genmask(7, 0) +#define ev_ctx_intmodc_mask genmask(15, 8) +#define ev_ctx_intmodc_shift 8 +#define ev_ctx_intmodt_mask genmask(31, 16) +#define ev_ctx_intmodt_shift 16 +struct mhi_event_ctxt { + __u32 intmod; + __u32 ertype; + __u32 msivec; + + __u64 rbase __packed __aligned(4); + __u64 rlen __packed __aligned(4); + __u64 rp __packed __aligned(4); + __u64 wp __packed __aligned(4); +}; + +#define chan_ctx_chstate_mask genmask(7, 0) +#define chan_ctx_chstate_shift 0 +#define chan_ctx_brstmode_mask genmask(9, 8) +#define chan_ctx_brstmode_shift 8 +#define chan_ctx_pollcfg_mask genmask(15, 10) +#define chan_ctx_pollcfg_shift 10 +#define chan_ctx_reserved_mask genmask(31, 16) +struct mhi_chan_ctxt { + __u32 chcfg; + __u32 chtype; + __u32 erindex; + + __u64 rbase __packed __aligned(4); + __u64 rlen __packed __aligned(4); + __u64 rp __packed __aligned(4); + __u64 wp __packed __aligned(4); +}; + +struct mhi_cmd_ctxt { + __u32 reserved0; + __u32 reserved1; + __u32 reserved2; + + __u64 rbase __packed __aligned(4); + __u64 rlen __packed __aligned(4); + __u64 rp __packed __aligned(4); + __u64 wp __packed __aligned(4); +}; + +struct mhi_ctxt { + struct mhi_event_ctxt *er_ctxt; + struct mhi_chan_ctxt *chan_ctxt; + struct mhi_cmd_ctxt *cmd_ctxt; + dma_addr_t er_ctxt_addr; + dma_addr_t chan_ctxt_addr; + dma_addr_t cmd_ctxt_addr; +}; + +struct mhi_tre { + u64 ptr; + u32 dword[2]; +}; + +struct bhi_vec_entry { + u64 dma_addr; + u64 size; +}; + +enum mhi_cmd_type { + mhi_cmd_nop = 1, + mhi_cmd_reset_chan = 16, + mhi_cmd_stop_chan = 17, + mhi_cmd_start_chan = 18, +}; + +#define mhi_dev_wake_db 127 +/* register access methods */ +void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, struct db_cfg *db_cfg, + void __iomem *db_addr, dma_addr_t db_val); +void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, + struct db_cfg *db_mode, void __iomem *db_addr, + dma_addr_t db_val); +int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, u32 *out); +int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, u32 mask, + u32 shift, u32 *out); +void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, + u32 offset, u32 val); +void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, + u32 offset, u32 mask, u32 shift, u32 val); +void mhi_ring_er_db(struct mhi_event *mhi_event); +void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, + dma_addr_t db_val); +void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd); +void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan); + +/* initialization methods */ +int mhi_init_mmio(struct mhi_controller *mhi_cntrl); + diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c +int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, u32 *out) +{ + u32 tmp = readl(base + offset); + + /* if there is any unexpected value, query the link status */ + if (pci_invalid_read(tmp) && + mhi_cntrl->link_status(mhi_cntrl)) + return -eio; + + *out = tmp; + + return 0; +} + +int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl, + void __iomem *base, u32 offset, + u32 mask, u32 shift, u32 *out) +{ + u32 tmp; + int ret; + + ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); + if (ret) + return ret; + + *out = (tmp & mask) >> shift; + + return 0; +} + +void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base, + u32 offset, u32 val) +{ + writel(val, base + offset); +} + +void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base, + u32 offset, u32 mask, u32 shift, u32 val) +{ + int ret; + u32 tmp; + + ret = mhi_read_reg(mhi_cntrl, base, offset, &tmp); + if (ret) + return; + + tmp &= ~mask; + tmp |= (val << shift); + mhi_write_reg(mhi_cntrl, base, offset, tmp); +} + +void mhi_write_db(struct mhi_controller *mhi_cntrl, void __iomem *db_addr, + dma_addr_t db_val) +{ + mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(db_val)); + mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(db_val)); +} + +void mhi_db_brstmode(struct mhi_controller *mhi_cntrl, + struct db_cfg *db_cfg, + void __iomem *db_addr, + dma_addr_t db_val) +{ + if (db_cfg->db_mode) { + db_cfg->db_val = db_val; + mhi_write_db(mhi_cntrl, db_addr, db_val); + db_cfg->db_mode = 0; + } +} + +void mhi_db_brstmode_disable(struct mhi_controller *mhi_cntrl, + struct db_cfg *db_cfg, + void __iomem *db_addr, + dma_addr_t db_val) +{ + db_cfg->db_val = db_val; + mhi_write_db(mhi_cntrl, db_addr, db_val); +} + +void mhi_ring_er_db(struct mhi_event *mhi_event) +{ + struct mhi_ring *ring = &mhi_event->ring; + + mhi_event->db_cfg.process_db(mhi_event->mhi_cntrl, &mhi_event->db_cfg, + ring->db_addr, *ring->ctxt_wp); +} + +void mhi_ring_cmd_db(struct mhi_controller *mhi_cntrl, struct mhi_cmd *mhi_cmd) +{ + dma_addr_t db; + struct mhi_ring *ring = &mhi_cmd->ring; + + db = ring->iommu_base + (ring->wp - ring->base); + *ring->ctxt_wp = db; + mhi_write_db(mhi_cntrl, ring->db_addr, db); +} + +void mhi_ring_chan_db(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan) +{ + struct mhi_ring *ring = &mhi_chan->tre_ring; + dma_addr_t db; + + db = ring->iommu_base + (ring->wp - ring->base); + *ring->ctxt_wp = db; + mhi_chan->db_cfg.process_db(mhi_cntrl, &mhi_chan->db_cfg, + ring->db_addr, db); +} + +enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl) +{ + u32 exec; + int ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->bhi, bhi_execenv, &exec); + + return (ret) ? mhi_ee_max : exec; +} + diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h + * @bhi: points to base of mhi bhi register space + * @wake_db: mhi wake doorbell register address + void __iomem *bhi; + void __iomem *wake_db;
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Modem Host Interface (MHI) Bus
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6cd330ae76ffd5c8f6294c423cabde7eeef1b40c
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manivannan sadhasivam
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include
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linux
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core, mhi
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bus: mhi: core: add support for pm state transitions
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this commit adds support for transitioning the mhi states as a part of the power management operations. helpers functions are provided for the state transitions, which will be consumed by the actual power management routines.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
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['h', 'c', 'makefile']
| 6
| 980
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--- diff --git a/drivers/bus/mhi/core/makefile b/drivers/bus/mhi/core/makefile --- a/drivers/bus/mhi/core/makefile +++ b/drivers/bus/mhi/core/makefile -mhi-y := init.o main.o +mhi-y := init.o main.o pm.o diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c +const char * const mhi_ee_str[mhi_ee_max] = { + [mhi_ee_pbl] = "pbl", + [mhi_ee_sbl] = "sbl", + [mhi_ee_amss] = "amss", + [mhi_ee_rddm] = "rddm", + [mhi_ee_wfw] = "wfw", + [mhi_ee_pthru] = "pass thru", + [mhi_ee_edl] = "edl", + [mhi_ee_disable_transition] = "disable", + [mhi_ee_not_supported] = "not supported", +}; + +const char * const dev_state_tran_str[dev_st_transition_max] = { + [dev_st_transition_pbl] = "pbl", + [dev_st_transition_ready] = "ready", + [dev_st_transition_sbl] = "sbl", + [dev_st_transition_mission_mode] = "mission_mode", +}; + +const char * const mhi_state_str[mhi_state_max] = { + [mhi_state_reset] = "reset", + [mhi_state_ready] = "ready", + [mhi_state_m0] = "m0", + [mhi_state_m1] = "m1", + [mhi_state_m2] = "m2", + [mhi_state_m3] = "m3", + [mhi_state_m3_fast] = "m3_fast", + [mhi_state_bhi] = "bhi", + [mhi_state_sys_err] = "sys_err", +}; + +static const char * const mhi_pm_state_str[] = { + [mhi_pm_state_disable] = "disable", + [mhi_pm_state_por] = "por", + [mhi_pm_state_m0] = "m0", + [mhi_pm_state_m2] = "m2", + [mhi_pm_state_m3_enter] = "m?->m3", + [mhi_pm_state_m3] = "m3", + [mhi_pm_state_m3_exit] = "m3->m0", + [mhi_pm_state_fw_dl_err] = "fw dl error", + [mhi_pm_state_sys_err_detect] = "sys_err detect", + [mhi_pm_state_sys_err_process] = "sys_err process", + [mhi_pm_state_shutdown_process] = "shutdown process", + [mhi_pm_state_ld_err_fatal_detect] = "ld or error fatal detect", +}; + +const char *to_mhi_pm_state_str(enum mhi_pm_state state) +{ + int index = find_last_bit((unsigned long *)&state, 32); + + if (index >= array_size(mhi_pm_state_str)) + return "invalid state"; + + return mhi_pm_state_str[index]; +} + + /* by default, host is allowed to ring db in both m0 and m2 states */ + mhi_cntrl->db_access = mhi_pm_m0 | mhi_pm_m2; + if (config->m2_no_db) + mhi_cntrl->db_access &= ~mhi_pm_m2; + + mutex_init(&mhi_cntrl->pm_mutex); + rwlock_init(&mhi_cntrl->pm_lock); + init_work(&mhi_cntrl->st_worker, mhi_pm_st_worker); + init_work(&mhi_cntrl->syserr_worker, mhi_pm_sys_err_worker); diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h +/* no operation command */ +#define mhi_tre_cmd_noop_ptr (0) +#define mhi_tre_cmd_noop_dword0 (0) +#define mhi_tre_cmd_noop_dword1 (mhi_cmd_nop << 16) + +/* channel reset command */ +#define mhi_tre_cmd_reset_ptr (0) +#define mhi_tre_cmd_reset_dword0 (0) +#define mhi_tre_cmd_reset_dword1(chid) ((chid << 24) | \ + (mhi_cmd_reset_chan << 16)) + +/* channel stop command */ +#define mhi_tre_cmd_stop_ptr (0) +#define mhi_tre_cmd_stop_dword0 (0) +#define mhi_tre_cmd_stop_dword1(chid) ((chid << 24) | \ + (mhi_cmd_stop_chan << 16)) + +/* channel start command */ +#define mhi_tre_cmd_start_ptr (0) +#define mhi_tre_cmd_start_dword0 (0) +#define mhi_tre_cmd_start_dword1(chid) ((chid << 24) | \ + (mhi_cmd_start_chan << 16)) + +#define mhi_tre_get_cmd_chid(tre) (((tre)->dword[1] >> 24) & 0xff) +#define mhi_tre_get_cmd_type(tre) (((tre)->dword[1] >> 16) & 0xff) + +/* event descriptor macros */ +#define mhi_tre_ev_ptr(ptr) (ptr) +#define mhi_tre_ev_dword0(code, len) ((code << 24) | len) +#define mhi_tre_ev_dword1(chid, type) ((chid << 24) | (type << 16)) +#define mhi_tre_get_ev_ptr(tre) ((tre)->ptr) +#define mhi_tre_get_ev_code(tre) (((tre)->dword[0] >> 24) & 0xff) +#define mhi_tre_get_ev_len(tre) ((tre)->dword[0] & 0xffff) +#define mhi_tre_get_ev_chid(tre) (((tre)->dword[1] >> 24) & 0xff) +#define mhi_tre_get_ev_type(tre) (((tre)->dword[1] >> 16) & 0xff) +#define mhi_tre_get_ev_state(tre) (((tre)->dword[0] >> 24) & 0xff) +#define mhi_tre_get_ev_execenv(tre) (((tre)->dword[0] >> 24) & 0xff) +#define mhi_tre_get_ev_seq(tre) ((tre)->dword[0]) +#define mhi_tre_get_ev_time(tre) ((tre)->ptr) +#define mhi_tre_get_ev_cookie(tre) lower_32_bits((tre)->ptr) +#define mhi_tre_get_ev_veid(tre) (((tre)->dword[0] >> 16) & 0xff) +#define mhi_tre_get_ev_linkspeed(tre) (((tre)->dword[1] >> 24) & 0xff) +#define mhi_tre_get_ev_linkwidth(tre) ((tre)->dword[0] & 0xff) + +/* transfer descriptor macros */ +#define mhi_tre_data_ptr(ptr) (ptr) +#define mhi_tre_data_dword0(len) (len & mhi_max_mtu) +#define mhi_tre_data_dword1(bei, ieot, ieob, chain) ((2 << 16) | (bei << 10) \ + | (ieot << 9) | (ieob << 8) | chain) + +/* rsc transfer descriptor macros */ +#define mhi_rsctre_data_ptr(ptr, len) (((u64)len << 48) | ptr) +#define mhi_rsctre_data_dword0(cookie) (cookie) +#define mhi_rsctre_data_dword1 (mhi_pkt_type_coalescing << 16) + +enum mhi_pkt_type { + mhi_pkt_type_invalid = 0x0, + mhi_pkt_type_noop_cmd = 0x1, + mhi_pkt_type_transfer = 0x2, + mhi_pkt_type_coalescing = 0x8, + mhi_pkt_type_reset_chan_cmd = 0x10, + mhi_pkt_type_stop_chan_cmd = 0x11, + mhi_pkt_type_start_chan_cmd = 0x12, + mhi_pkt_type_state_change_event = 0x20, + mhi_pkt_type_cmd_completion_event = 0x21, + mhi_pkt_type_tx_event = 0x22, + mhi_pkt_type_rsc_tx_event = 0x28, + mhi_pkt_type_ee_event = 0x40, + mhi_pkt_type_tsync_event = 0x48, + mhi_pkt_type_bw_req_event = 0x50, + mhi_pkt_type_stale_event, /* internal event */ +}; + +extern const char * const mhi_ee_str[mhi_ee_max]; +#define to_mhi_exec_str(ee) (((ee) >= mhi_ee_max) ? \ + "invalid_ee" : mhi_ee_str[ee]) + +#define mhi_in_pbl(ee) (ee == mhi_ee_pbl || ee == mhi_ee_pthru || \ + ee == mhi_ee_edl) + +#define mhi_in_mission_mode(ee) (ee == mhi_ee_amss || ee == mhi_ee_wfw) + +enum dev_st_transition { + dev_st_transition_pbl, + dev_st_transition_ready, + dev_st_transition_sbl, + dev_st_transition_mission_mode, + dev_st_transition_max, +}; + +extern const char * const dev_state_tran_str[dev_st_transition_max]; +#define to_dev_state_trans_str(state) (((state) >= dev_st_transition_max) ? \ + "invalid_state" : dev_state_tran_str[state]) + +extern const char * const mhi_state_str[mhi_state_max]; +#define to_mhi_state_str(state) ((state >= mhi_state_max || \ + !mhi_state_str[state]) ? \ + "invalid_state" : mhi_state_str[state]) + +/* internal power states */ +enum mhi_pm_state { + mhi_pm_state_disable, + mhi_pm_state_por, + mhi_pm_state_m0, + mhi_pm_state_m2, + mhi_pm_state_m3_enter, + mhi_pm_state_m3, + mhi_pm_state_m3_exit, + mhi_pm_state_fw_dl_err, + mhi_pm_state_sys_err_detect, + mhi_pm_state_sys_err_process, + mhi_pm_state_shutdown_process, + mhi_pm_state_ld_err_fatal_detect, + mhi_pm_state_max +}; + +#define mhi_pm_disable bit(0) +#define mhi_pm_por bit(1) +#define mhi_pm_m0 bit(2) +#define mhi_pm_m2 bit(3) +#define mhi_pm_m3_enter bit(4) +#define mhi_pm_m3 bit(5) +#define mhi_pm_m3_exit bit(6) +/* firmware download failure state */ +#define mhi_pm_fw_dl_err bit(7) +#define mhi_pm_sys_err_detect bit(8) +#define mhi_pm_sys_err_process bit(9) +#define mhi_pm_shutdown_process bit(10) +/* link not accessible */ +#define mhi_pm_ld_err_fatal_detect bit(11) + +#define mhi_reg_access_valid(pm_state) ((pm_state & (mhi_pm_por | mhi_pm_m0 | \ + mhi_pm_m2 | mhi_pm_m3_enter | mhi_pm_m3_exit | \ + mhi_pm_sys_err_detect | mhi_pm_sys_err_process | \ + mhi_pm_shutdown_process | mhi_pm_fw_dl_err))) +#define mhi_pm_in_error_state(pm_state) (pm_state >= mhi_pm_fw_dl_err) +#define mhi_pm_in_fatal_state(pm_state) (pm_state == mhi_pm_ld_err_fatal_detect) +#define mhi_db_access_valid(mhi_cntrl) (mhi_cntrl->pm_state & \ + mhi_cntrl->db_access) +#define mhi_wake_db_clear_valid(pm_state) (pm_state & (mhi_pm_m0 | \ + mhi_pm_m2 | mhi_pm_m3_exit)) +#define mhi_wake_db_set_valid(pm_state) (pm_state & mhi_pm_m2) +#define mhi_wake_db_force_set_valid(pm_state) mhi_wake_db_clear_valid(pm_state) +#define mhi_event_access_invalid(pm_state) (pm_state == mhi_pm_disable || \ + mhi_pm_in_error_state(pm_state)) +#define mhi_pm_in_suspend_state(pm_state) (pm_state & \ + (mhi_pm_m3_enter | mhi_pm_m3)) + +struct mhi_pm_transitions { + enum mhi_pm_state from_state; + u32 to_states; +}; + +struct state_transition { + struct list_head node; + enum dev_st_transition state; +}; + +/* power management apis */ +enum mhi_pm_state __must_check mhi_tryset_pm_state( + struct mhi_controller *mhi_cntrl, + enum mhi_pm_state state); +const char *to_mhi_pm_state_str(enum mhi_pm_state state); +enum mhi_ee_type mhi_get_exec_env(struct mhi_controller *mhi_cntrl); +int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, + enum dev_st_transition state); +void mhi_pm_st_worker(struct work_struct *work); +void mhi_pm_sys_err_worker(struct work_struct *work); +int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl); +void mhi_ctrl_ev_task(unsigned long data); +int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl); +void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl); +int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl); +int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl); + diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c +enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl) +{ + u32 state; + int ret = mhi_read_reg_field(mhi_cntrl, mhi_cntrl->regs, mhistatus, + mhistatus_mhistate_mask, + mhistatus_mhistate_shift, &state); + return ret ? mhi_state_max : state; +} + diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c --- /dev/null +++ b/drivers/bus/mhi/core/pm.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018-2020, the linux foundation. all rights reserved. + * + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/dma-direction.h> +#include <linux/dma-mapping.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/mhi.h> +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/wait.h> +#include "internal.h" + +/* + * not all mhi state transitions are synchronous. transitions like linkdown, + * sys_err, and shutdown can happen anytime asynchronously. this function will + * transition to a new state only if we're allowed to. + * + * priority increases as we go down. for instance, from any state in l0, the + * transition can be made to states in l1, l2 and l3. a notable exception to + * this rule is state disable. from disable state we can only transition to + * por state. also, while in l2 state, user cannot jump back to previous + * l1 or l0 states. + * + * valid transitions: + * l0: disable <--> por + * por <--> por + * por -> m0 -> m2 --> m0 + * por -> fw_dl_err + * fw_dl_err <--> fw_dl_err + * m0 <--> m0 + * m0 -> fw_dl_err + * m0 -> m3_enter -> m3 -> m3_exit --> m0 + * l1: sys_err_detect -> sys_err_process --> por + * l2: shutdown_process -> disable + * l3: ld_err_fatal_detect <--> ld_err_fatal_detect + * ld_err_fatal_detect -> shutdown_process + */ +static struct mhi_pm_transitions const dev_state_transitions[] = { + /* l0 states */ + { + mhi_pm_disable, + mhi_pm_por + }, + { + mhi_pm_por, + mhi_pm_por | mhi_pm_disable | mhi_pm_m0 | + mhi_pm_sys_err_detect | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect | mhi_pm_fw_dl_err + }, + { + mhi_pm_m0, + mhi_pm_m0 | mhi_pm_m2 | mhi_pm_m3_enter | + mhi_pm_sys_err_detect | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect | mhi_pm_fw_dl_err + }, + { + mhi_pm_m2, + mhi_pm_m0 | mhi_pm_sys_err_detect | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect + }, + { + mhi_pm_m3_enter, + mhi_pm_m3 | mhi_pm_sys_err_detect | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect + }, + { + mhi_pm_m3, + mhi_pm_m3_exit | mhi_pm_sys_err_detect | + mhi_pm_shutdown_process | mhi_pm_ld_err_fatal_detect + }, + { + mhi_pm_m3_exit, + mhi_pm_m0 | mhi_pm_sys_err_detect | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect + }, + { + mhi_pm_fw_dl_err, + mhi_pm_fw_dl_err | mhi_pm_sys_err_detect | + mhi_pm_shutdown_process | mhi_pm_ld_err_fatal_detect + }, + /* l1 states */ + { + mhi_pm_sys_err_detect, + mhi_pm_sys_err_process | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect + }, + { + mhi_pm_sys_err_process, + mhi_pm_por | mhi_pm_shutdown_process | + mhi_pm_ld_err_fatal_detect + }, + /* l2 states */ + { + mhi_pm_shutdown_process, + mhi_pm_disable | mhi_pm_ld_err_fatal_detect + }, + /* l3 states */ + { + mhi_pm_ld_err_fatal_detect, + mhi_pm_ld_err_fatal_detect | mhi_pm_shutdown_process + }, +}; + +enum mhi_pm_state __must_check mhi_tryset_pm_state(struct mhi_controller *mhi_cntrl, + enum mhi_pm_state state) +{ + unsigned long cur_state = mhi_cntrl->pm_state; + int index = find_last_bit(&cur_state, 32); + + if (unlikely(index >= array_size(dev_state_transitions))) + return cur_state; + + if (unlikely(dev_state_transitions[index].from_state != cur_state)) + return cur_state; + + if (unlikely(!(dev_state_transitions[index].to_states & state))) + return cur_state; + + mhi_cntrl->pm_state = state; + return mhi_cntrl->pm_state; +} + +void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, enum mhi_state state) +{ + if (state == mhi_state_reset) { + mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, mhictrl, + mhictrl_reset_mask, mhictrl_reset_shift, 1); + } else { + mhi_write_reg_field(mhi_cntrl, mhi_cntrl->regs, mhictrl, + mhictrl_mhistate_mask, + mhictrl_mhistate_shift, state); + } +} + +/* handle device ready state transition */ +int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl) +{ + void __iomem *base = mhi_cntrl->regs; + struct mhi_event *mhi_event; + enum mhi_pm_state cur_state; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + u32 reset = 1, ready = 0; + int ret, i; + + /* wait for reset to be cleared and ready bit to be set by the device */ + wait_event_timeout(mhi_cntrl->state_event, + mhi_pm_in_fatal_state(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, base, mhictrl, + mhictrl_reset_mask, + mhictrl_reset_shift, &reset) || + mhi_read_reg_field(mhi_cntrl, base, mhistatus, + mhistatus_ready_mask, + mhistatus_ready_shift, &ready) || + (!reset && ready), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + /* check if device entered error state */ + if (mhi_pm_in_fatal_state(mhi_cntrl->pm_state)) { + dev_err(dev, "device link is not accessible "); + return -eio; + } + + /* timeout if device did not transition to ready state */ + if (reset || !ready) { + dev_err(dev, "device ready timeout "); + return -etimedout; + } + + dev_dbg(dev, "device in ready state "); + write_lock_irq(&mhi_cntrl->pm_lock); + cur_state = mhi_tryset_pm_state(mhi_cntrl, mhi_pm_por); + mhi_cntrl->dev_state = mhi_state_ready; + write_unlock_irq(&mhi_cntrl->pm_lock); + + if (cur_state != mhi_pm_por) { + dev_err(dev, "error moving to state %s from %s ", + to_mhi_pm_state_str(mhi_pm_por), + to_mhi_pm_state_str(cur_state)); + return -eio; + } + + read_lock_bh(&mhi_cntrl->pm_lock); + if (!mhi_reg_access_valid(mhi_cntrl->pm_state)) { + dev_err(dev, "device registers not accessible "); + goto error_mmio; + } + + /* configure mmio registers */ + ret = mhi_init_mmio(mhi_cntrl); + if (ret) { + dev_err(dev, "error configuring mmio registers "); + goto error_mmio; + } + + /* add elements to all sw event rings */ + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + struct mhi_ring *ring = &mhi_event->ring; + + /* skip if this is an offload or hw event */ + if (mhi_event->offload_ev || mhi_event->hw_ring) + continue; + + ring->wp = ring->base + ring->len - ring->el_size; + *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size; + /* update all cores */ + smp_wmb(); + + /* ring the event ring db */ + spin_lock_irq(&mhi_event->lock); + mhi_ring_er_db(mhi_event); + spin_unlock_irq(&mhi_event->lock); + } + + /* set mhi to m0 state */ + mhi_set_mhi_state(mhi_cntrl, mhi_state_m0); + read_unlock_bh(&mhi_cntrl->pm_lock); + + return 0; + +error_mmio: + read_unlock_bh(&mhi_cntrl->pm_lock); + + return -eio; +} + +int mhi_pm_m0_transition(struct mhi_controller *mhi_cntrl) +{ + enum mhi_pm_state cur_state; + struct mhi_chan *mhi_chan; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int i; + + write_lock_irq(&mhi_cntrl->pm_lock); + mhi_cntrl->dev_state = mhi_state_m0; + cur_state = mhi_tryset_pm_state(mhi_cntrl, mhi_pm_m0); + write_unlock_irq(&mhi_cntrl->pm_lock); + if (unlikely(cur_state != mhi_pm_m0)) { + dev_err(dev, "unable to transition to m0 state "); + return -eio; + } + + /* wake up the device */ + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, true); + + /* ring all event rings and cmd ring only if we're in mission mode */ + if (mhi_in_mission_mode(mhi_cntrl->ee)) { + struct mhi_event *mhi_event = mhi_cntrl->mhi_event; + struct mhi_cmd *mhi_cmd = + &mhi_cntrl->mhi_cmd[primary_cmd_ring]; + + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->offload_ev) + continue; + + spin_lock_irq(&mhi_event->lock); + mhi_ring_er_db(mhi_event); + spin_unlock_irq(&mhi_event->lock); + } + + /* only ring primary cmd ring if ring is not empty */ + spin_lock_irq(&mhi_cmd->lock); + if (mhi_cmd->ring.rp != mhi_cmd->ring.wp) + mhi_ring_cmd_db(mhi_cntrl, mhi_cmd); + spin_unlock_irq(&mhi_cmd->lock); + } + + /* ring channel db registers */ + mhi_chan = mhi_cntrl->mhi_chan; + for (i = 0; i < mhi_cntrl->max_chan; i++, mhi_chan++) { + struct mhi_ring *tre_ring = &mhi_chan->tre_ring; + + write_lock_irq(&mhi_chan->lock); + if (mhi_chan->db_cfg.reset_req) + mhi_chan->db_cfg.db_mode = true; + + /* only ring db if ring is not empty */ + if (tre_ring->base && tre_ring->wp != tre_ring->rp) + mhi_ring_chan_db(mhi_cntrl, mhi_chan); + write_unlock_irq(&mhi_chan->lock); + } + + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + wake_up_all(&mhi_cntrl->state_event); + + return 0; +} + +/* + * after receiving the mhi state change event from the device indicating the + * transition to m1 state, the host can transition the device to m2 state + * for keeping it in low power state. + */ +void mhi_pm_m1_transition(struct mhi_controller *mhi_cntrl) +{ + enum mhi_pm_state state; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + write_lock_irq(&mhi_cntrl->pm_lock); + state = mhi_tryset_pm_state(mhi_cntrl, mhi_pm_m2); + if (state == mhi_pm_m2) { + mhi_set_mhi_state(mhi_cntrl, mhi_state_m2); + mhi_cntrl->dev_state = mhi_state_m2; + + write_unlock_irq(&mhi_cntrl->pm_lock); + wake_up_all(&mhi_cntrl->state_event); + + /* if there are any pending resources, exit m2 immediately */ + if (unlikely(atomic_read(&mhi_cntrl->pending_pkts) || + atomic_read(&mhi_cntrl->dev_wake))) { + dev_dbg(dev, + "exiting m2, pending_pkts: %d dev_wake: %d ", + atomic_read(&mhi_cntrl->pending_pkts), + atomic_read(&mhi_cntrl->dev_wake)); + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, true); + mhi_cntrl->wake_put(mhi_cntrl, true); + read_unlock_bh(&mhi_cntrl->pm_lock); + } else { + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_idle); + } + } else { + write_unlock_irq(&mhi_cntrl->pm_lock); + } +} + +/* mhi m3 completion handler */ +int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl) +{ + enum mhi_pm_state state; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + write_lock_irq(&mhi_cntrl->pm_lock); + mhi_cntrl->dev_state = mhi_state_m3; + state = mhi_tryset_pm_state(mhi_cntrl, mhi_pm_m3); + write_unlock_irq(&mhi_cntrl->pm_lock); + if (state != mhi_pm_m3) { + dev_err(dev, "unable to transition to m3 state "); + return -eio; + } + + wake_up_all(&mhi_cntrl->state_event); + + return 0; +} + +/* handle device mission mode transition */ +static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl) +{ + struct mhi_event *mhi_event; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int i, ret; + + dev_dbg(dev, "processing mission mode transition "); + + write_lock_irq(&mhi_cntrl->pm_lock); + if (mhi_reg_access_valid(mhi_cntrl->pm_state)) + mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + write_unlock_irq(&mhi_cntrl->pm_lock); + + if (!mhi_in_mission_mode(mhi_cntrl->ee)) + return -eio; + + wake_up_all(&mhi_cntrl->state_event); + + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_ee_mission_mode); + + /* force mhi to be in m0 state before continuing */ + ret = __mhi_device_get_sync(mhi_cntrl); + if (ret) + return ret; + + read_lock_bh(&mhi_cntrl->pm_lock); + + if (mhi_pm_in_error_state(mhi_cntrl->pm_state)) { + ret = -eio; + goto error_mission_mode; + } + + /* add elements to all hw event rings */ + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + struct mhi_ring *ring = &mhi_event->ring; + + if (mhi_event->offload_ev || !mhi_event->hw_ring) + continue; + + ring->wp = ring->base + ring->len - ring->el_size; + *ring->ctxt_wp = ring->iommu_base + ring->len - ring->el_size; + /* update to all cores */ + smp_wmb(); + + spin_lock_irq(&mhi_event->lock); + if (mhi_db_access_valid(mhi_cntrl)) + mhi_ring_er_db(mhi_event); + spin_unlock_irq(&mhi_event->lock); + } + + read_unlock_bh(&mhi_cntrl->pm_lock); + + /* + * the mhi devices are only created when the client device switches its + * execution environment (ee) to either sbl or amss states + */ + mhi_create_devices(mhi_cntrl); + + read_lock_bh(&mhi_cntrl->pm_lock); + +error_mission_mode: + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + + return ret; +} + +/* handle sys_err and shutdown transitions */ +static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, + enum mhi_pm_state transition_state) +{ + enum mhi_pm_state cur_state, prev_state; + struct mhi_event *mhi_event; + struct mhi_cmd_ctxt *cmd_ctxt; + struct mhi_cmd *mhi_cmd; + struct mhi_event_ctxt *er_ctxt; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int ret, i; + + dev_dbg(dev, "transitioning from pm state: %s to: %s ", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + to_mhi_pm_state_str(transition_state)); + + /* we must notify mhi control driver so it can clean up first */ + if (transition_state == mhi_pm_sys_err_process) { + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_sys_error); + } + + mutex_lock(&mhi_cntrl->pm_mutex); + write_lock_irq(&mhi_cntrl->pm_lock); + prev_state = mhi_cntrl->pm_state; + cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state); + if (cur_state == transition_state) { + mhi_cntrl->ee = mhi_ee_disable_transition; + mhi_cntrl->dev_state = mhi_state_reset; + } + write_unlock_irq(&mhi_cntrl->pm_lock); + + /* wake up threads waiting for state transition */ + wake_up_all(&mhi_cntrl->state_event); + + if (cur_state != transition_state) { + dev_err(dev, "failed to transition to state: %s from: %s ", + to_mhi_pm_state_str(transition_state), + to_mhi_pm_state_str(cur_state)); + mutex_unlock(&mhi_cntrl->pm_mutex); + return; + } + + /* trigger mhi reset so that the device will not access host memory */ + if (mhi_reg_access_valid(prev_state)) { + u32 in_reset = -1; + unsigned long timeout = msecs_to_jiffies(mhi_cntrl->timeout_ms); + + dev_dbg(dev, "triggering mhi reset in device "); + mhi_set_mhi_state(mhi_cntrl, mhi_state_reset); + + /* wait for the reset bit to be cleared by the device */ + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_read_reg_field(mhi_cntrl, + mhi_cntrl->regs, + mhictrl, + mhictrl_reset_mask, + mhictrl_reset_shift, + &in_reset) || + !in_reset, timeout); + if ((!ret || in_reset) && cur_state == mhi_pm_sys_err_process) { + dev_err(dev, "device failed to exit mhi reset state "); + mutex_unlock(&mhi_cntrl->pm_mutex); + return; + } + + /* + * device will clear bhi_intvec as a part of reset processing, + * hence re-program it + */ + mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, bhi_intvec, 0); + } + + dev_dbg(dev, + "waiting for all pending event ring processing to complete "); + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->offload_ev) + continue; + tasklet_kill(&mhi_event->task); + } + + /* release lock and wait for all pending threads to complete */ + mutex_unlock(&mhi_cntrl->pm_mutex); + dev_dbg(dev, "waiting for all pending threads to complete "); + wake_up_all(&mhi_cntrl->state_event); + flush_work(&mhi_cntrl->st_worker); + flush_work(&mhi_cntrl->fw_worker); + + dev_dbg(dev, "reset all active channels and remove mhi devices "); + device_for_each_child(mhi_cntrl->cntrl_dev, null, mhi_destroy_device); + + mutex_lock(&mhi_cntrl->pm_mutex); + + warn_on(atomic_read(&mhi_cntrl->dev_wake)); + warn_on(atomic_read(&mhi_cntrl->pending_pkts)); + + /* reset the ev rings and cmd rings */ + dev_dbg(dev, "resetting ev ctxt and cmd ctxt "); + mhi_cmd = mhi_cntrl->mhi_cmd; + cmd_ctxt = mhi_cntrl->mhi_ctxt->cmd_ctxt; + for (i = 0; i < nr_of_cmd_rings; i++, mhi_cmd++, cmd_ctxt++) { + struct mhi_ring *ring = &mhi_cmd->ring; + + ring->rp = ring->base; + ring->wp = ring->base; + cmd_ctxt->rp = cmd_ctxt->rbase; + cmd_ctxt->wp = cmd_ctxt->rbase; + } + + mhi_event = mhi_cntrl->mhi_event; + er_ctxt = mhi_cntrl->mhi_ctxt->er_ctxt; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, + mhi_event++) { + struct mhi_ring *ring = &mhi_event->ring; + + /* skip offload events */ + if (mhi_event->offload_ev) + continue; + + ring->rp = ring->base; + ring->wp = ring->base; + er_ctxt->rp = er_ctxt->rbase; + er_ctxt->wp = er_ctxt->rbase; + } + + if (cur_state == mhi_pm_sys_err_process) { + mhi_ready_state_transition(mhi_cntrl); + } else { + /* move to disable state */ + write_lock_irq(&mhi_cntrl->pm_lock); + cur_state = mhi_tryset_pm_state(mhi_cntrl, mhi_pm_disable); + write_unlock_irq(&mhi_cntrl->pm_lock); + if (unlikely(cur_state != mhi_pm_disable)) + dev_err(dev, "error moving from pm state: %s to: %s ", + to_mhi_pm_state_str(cur_state), + to_mhi_pm_state_str(mhi_pm_disable)); + } + + dev_dbg(dev, "exiting with pm state: %s, mhi state: %s ", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + to_mhi_state_str(mhi_cntrl->dev_state)); + + mutex_unlock(&mhi_cntrl->pm_mutex); +} + +/* queue a new work item and schedule work */ +int mhi_queue_state_transition(struct mhi_controller *mhi_cntrl, + enum dev_st_transition state) +{ + struct state_transition *item = kmalloc(sizeof(*item), gfp_atomic); + unsigned long flags; + + if (!item) + return -enomem; + + item->state = state; + spin_lock_irqsave(&mhi_cntrl->transition_lock, flags); + list_add_tail(&item->node, &mhi_cntrl->transition_list); + spin_unlock_irqrestore(&mhi_cntrl->transition_lock, flags); + + schedule_work(&mhi_cntrl->st_worker); + + return 0; +} + +/* sys_err worker */ +void mhi_pm_sys_err_worker(struct work_struct *work) +{ + struct mhi_controller *mhi_cntrl = container_of(work, + struct mhi_controller, + syserr_worker); + + mhi_pm_disable_transition(mhi_cntrl, mhi_pm_sys_err_process); +} + +/* device state transition worker */ +void mhi_pm_st_worker(struct work_struct *work) +{ + struct state_transition *itr, *tmp; + list_head(head); + struct mhi_controller *mhi_cntrl = container_of(work, + struct mhi_controller, + st_worker); + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + spin_lock_irq(&mhi_cntrl->transition_lock); + list_splice_tail_init(&mhi_cntrl->transition_list, &head); + spin_unlock_irq(&mhi_cntrl->transition_lock); + + list_for_each_entry_safe(itr, tmp, &head, node) { + list_del(&itr->node); + dev_dbg(dev, "handling state transition: %s ", + to_dev_state_trans_str(itr->state)); + + switch (itr->state) { + case dev_st_transition_pbl: + write_lock_irq(&mhi_cntrl->pm_lock); + if (mhi_reg_access_valid(mhi_cntrl->pm_state)) + mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + write_unlock_irq(&mhi_cntrl->pm_lock); + if (mhi_in_pbl(mhi_cntrl->ee)) + wake_up_all(&mhi_cntrl->state_event); + break; + case dev_st_transition_sbl: + write_lock_irq(&mhi_cntrl->pm_lock); + mhi_cntrl->ee = mhi_ee_sbl; + write_unlock_irq(&mhi_cntrl->pm_lock); + /* + * the mhi devices are only created when the client + * device switches its execution environment (ee) to + * either sbl or amss states + */ + mhi_create_devices(mhi_cntrl); + break; + case dev_st_transition_mission_mode: + mhi_pm_mission_mode_transition(mhi_cntrl); + break; + case dev_st_transition_ready: + mhi_ready_state_transition(mhi_cntrl); + break; + default: + break; + } + kfree(itr); + } +} + +int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl) +{ + int ret; + + /* wake up the device */ + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, true); + if (mhi_pm_in_suspend_state(mhi_cntrl->pm_state)) { + pm_wakeup_event(&mhi_cntrl->mhi_dev->dev, 0); + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + } + read_unlock_bh(&mhi_cntrl->pm_lock); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->pm_state == mhi_pm_m0 || + mhi_pm_in_error_state(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || mhi_pm_in_error_state(mhi_cntrl->pm_state)) { + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); + return -eio; + } + + return 0; +} diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h +/** + * enum mhi_state - mhi states + * @mhi_state_reset: reset state + * @mhi_state_ready: ready state + * @mhi_state_m0: m0 state + * @mhi_state_m1: m1 state + * @mhi_state_m2: m2 state + * @mhi_state_m3: m3 state + * @mhi_state_m3_fast: m3 fast state + * @mhi_state_bhi: bhi state + * @mhi_state_sys_err: system error state + */ +enum mhi_state { + mhi_state_reset = 0x0, + mhi_state_ready = 0x1, + mhi_state_m0 = 0x2, + mhi_state_m1 = 0x3, + mhi_state_m2 = 0x4, + mhi_state_m3 = 0x5, + mhi_state_m3_fast = 0x6, + mhi_state_bhi = 0x7, + mhi_state_sys_err = 0xff, + mhi_state_max, +}; + + * @dev_state: mhi device state + + enum mhi_state dev_state; +/** + * struct mhi_buf - mhi buffer description + * @buf: virtual address of the buffer + * @name: buffer label. for offload channel, configurations name must be: + * eca - event context array data + * cca - channel context array data + * @dma_addr: iommu address of the buffer + * @len: # of bytes + */ +struct mhi_buf { + void *buf; + const char *name; + dma_addr_t dma_addr; + size_t len; +}; + +/** + * mhi_set_mhi_state - set mhi device state + * @mhi_cntrl: mhi controller + * @state: state to set + */ +void mhi_set_mhi_state(struct mhi_controller *mhi_cntrl, + enum mhi_state state); +
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Modem Host Interface (MHI) Bus
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a6e2e3522f29141b95c1ef8580c665a3582b3e66
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manivannan sadhasivam
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include
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linux
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core, mhi
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bus: mhi: core: add support for basic pm operations
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this commit adds support for basic mhi pm operations such as mhi_async_power_up, mhi_sync_power_up, and mhi_power_down. these routines places the mhi bus into respective power domain states and calls the state_transition apis when necessary. the mhi controller driver is expected to call these pm routines for mhi powerup and powerdown.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
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['h', 'c', 'makefile']
| 7
| 801
| 1
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--- diff --git a/drivers/bus/mhi/core/makefile b/drivers/bus/mhi/core/makefile --- a/drivers/bus/mhi/core/makefile +++ b/drivers/bus/mhi/core/makefile -mhi-y := init.o main.o pm.o +mhi-y := init.o main.o pm.o boot.o diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c --- /dev/null +++ b/drivers/bus/mhi/core/boot.c +// spdx-license-identifier: gpl-2.0 +/* + * copyright (c) 2018-2020, the linux foundation. all rights reserved. + * + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/dma-direction.h> +#include <linux/dma-mapping.h> +#include <linux/firmware.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/mhi.h> +#include <linux/module.h> +#include <linux/random.h> +#include <linux/slab.h> +#include <linux/wait.h> +#include "internal.h" + +void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, + struct image_info *image_info) +{ + int i; + struct mhi_buf *mhi_buf = image_info->mhi_buf; + + for (i = 0; i < image_info->entries; i++, mhi_buf++) + mhi_free_coherent(mhi_cntrl, mhi_buf->len, mhi_buf->buf, + mhi_buf->dma_addr); + + kfree(image_info->mhi_buf); + kfree(image_info); +} + +int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, + struct image_info **image_info, + size_t alloc_size) +{ + size_t seg_size = mhi_cntrl->seg_len; + int segments = div_round_up(alloc_size, seg_size) + 1; + int i; + struct image_info *img_info; + struct mhi_buf *mhi_buf; + + img_info = kzalloc(sizeof(*img_info), gfp_kernel); + if (!img_info) + return -enomem; + + /* allocate memory for entries */ + img_info->mhi_buf = kcalloc(segments, sizeof(*img_info->mhi_buf), + gfp_kernel); + if (!img_info->mhi_buf) + goto error_alloc_mhi_buf; + + /* allocate and populate vector table */ + mhi_buf = img_info->mhi_buf; + for (i = 0; i < segments; i++, mhi_buf++) { + size_t vec_size = seg_size; + + /* vector table is the last entry */ + if (i == segments - 1) + vec_size = sizeof(struct bhi_vec_entry) * i; + + mhi_buf->len = vec_size; + mhi_buf->buf = mhi_alloc_coherent(mhi_cntrl, vec_size, + &mhi_buf->dma_addr, + gfp_kernel); + if (!mhi_buf->buf) + goto error_alloc_segment; + } + + img_info->bhi_vec = img_info->mhi_buf[segments - 1].buf; + img_info->entries = segments; + *image_info = img_info; + + return 0; + +error_alloc_segment: + for (--i, --mhi_buf; i >= 0; i--, mhi_buf--) + mhi_free_coherent(mhi_cntrl, mhi_buf->len, mhi_buf->buf, + mhi_buf->dma_addr); + +error_alloc_mhi_buf: + kfree(img_info); + + return -enomem; +} diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c +/* mhi protocol requires the transfer ring to be aligned with ring length */ +static int mhi_alloc_aligned_ring(struct mhi_controller *mhi_cntrl, + struct mhi_ring *ring, + u64 len) +{ + ring->alloc_size = len + (len - 1); + ring->pre_aligned = mhi_alloc_coherent(mhi_cntrl, ring->alloc_size, + &ring->dma_handle, gfp_kernel); + if (!ring->pre_aligned) + return -enomem; + + ring->iommu_base = (ring->dma_handle + (len - 1)) & ~(len - 1); + ring->base = ring->pre_aligned + (ring->iommu_base - ring->dma_handle); + + return 0; +} + +void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl) +{ + int i; + struct mhi_event *mhi_event = mhi_cntrl->mhi_event; + + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->offload_ev) + continue; + + free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); + } + + free_irq(mhi_cntrl->irq[0], mhi_cntrl); +} + +int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl) +{ + struct mhi_event *mhi_event = mhi_cntrl->mhi_event; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int i, ret; + + /* setup bhi_intvec irq */ + ret = request_threaded_irq(mhi_cntrl->irq[0], mhi_intvec_handler, + mhi_intvec_threaded_handler, + irqf_shared | irqf_no_suspend, + "bhi", mhi_cntrl); + if (ret) + return ret; + + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->offload_ev) + continue; + + ret = request_irq(mhi_cntrl->irq[mhi_event->irq], + mhi_irq_handler, + irqf_shared | irqf_no_suspend, + "mhi", mhi_event); + if (ret) { + dev_err(dev, "error requesting irq:%d for ev:%d ", + mhi_cntrl->irq[mhi_event->irq], i); + goto error_request; + } + } + + return 0; + +error_request: + for (--i, --mhi_event; i >= 0; i--, mhi_event--) { + if (mhi_event->offload_ev) + continue; + + free_irq(mhi_cntrl->irq[mhi_event->irq], mhi_event); + } + free_irq(mhi_cntrl->irq[0], mhi_cntrl); + + return ret; +} + +void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl) +{ + int i; + struct mhi_ctxt *mhi_ctxt = mhi_cntrl->mhi_ctxt; + struct mhi_cmd *mhi_cmd; + struct mhi_event *mhi_event; + struct mhi_ring *ring; + + mhi_cmd = mhi_cntrl->mhi_cmd; + for (i = 0; i < nr_of_cmd_rings; i++, mhi_cmd++) { + ring = &mhi_cmd->ring; + mhi_free_coherent(mhi_cntrl, ring->alloc_size, + ring->pre_aligned, ring->dma_handle); + ring->base = null; + ring->iommu_base = 0; + } + + mhi_free_coherent(mhi_cntrl, + sizeof(*mhi_ctxt->cmd_ctxt) * nr_of_cmd_rings, + mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr); + + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, mhi_event++) { + if (mhi_event->offload_ev) + continue; + + ring = &mhi_event->ring; + mhi_free_coherent(mhi_cntrl, ring->alloc_size, + ring->pre_aligned, ring->dma_handle); + ring->base = null; + ring->iommu_base = 0; + } + + mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->er_ctxt) * + mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt, + mhi_ctxt->er_ctxt_addr); + + mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->chan_ctxt) * + mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt, + mhi_ctxt->chan_ctxt_addr); + + kfree(mhi_ctxt); + mhi_cntrl->mhi_ctxt = null; +} + +int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl) +{ + struct mhi_ctxt *mhi_ctxt; + struct mhi_chan_ctxt *chan_ctxt; + struct mhi_event_ctxt *er_ctxt; + struct mhi_cmd_ctxt *cmd_ctxt; + struct mhi_chan *mhi_chan; + struct mhi_event *mhi_event; + struct mhi_cmd *mhi_cmd; + u32 tmp; + int ret = -enomem, i; + + atomic_set(&mhi_cntrl->dev_wake, 0); + atomic_set(&mhi_cntrl->pending_pkts, 0); + + mhi_ctxt = kzalloc(sizeof(*mhi_ctxt), gfp_kernel); + if (!mhi_ctxt) + return -enomem; + + /* setup channel ctxt */ + mhi_ctxt->chan_ctxt = mhi_alloc_coherent(mhi_cntrl, + sizeof(*mhi_ctxt->chan_ctxt) * + mhi_cntrl->max_chan, + &mhi_ctxt->chan_ctxt_addr, + gfp_kernel); + if (!mhi_ctxt->chan_ctxt) + goto error_alloc_chan_ctxt; + + mhi_chan = mhi_cntrl->mhi_chan; + chan_ctxt = mhi_ctxt->chan_ctxt; + for (i = 0; i < mhi_cntrl->max_chan; i++, chan_ctxt++, mhi_chan++) { + /* skip if it is an offload channel */ + if (mhi_chan->offload_ch) + continue; + + tmp = chan_ctxt->chcfg; + tmp &= ~chan_ctx_chstate_mask; + tmp |= (mhi_ch_state_disabled << chan_ctx_chstate_shift); + tmp &= ~chan_ctx_brstmode_mask; + tmp |= (mhi_chan->db_cfg.brstmode << chan_ctx_brstmode_shift); + tmp &= ~chan_ctx_pollcfg_mask; + tmp |= (mhi_chan->db_cfg.pollcfg << chan_ctx_pollcfg_shift); + chan_ctxt->chcfg = tmp; + + chan_ctxt->chtype = mhi_chan->type; + chan_ctxt->erindex = mhi_chan->er_index; + + mhi_chan->ch_state = mhi_ch_state_disabled; + mhi_chan->tre_ring.db_addr = (void __iomem *)&chan_ctxt->wp; + } + + /* setup event context */ + mhi_ctxt->er_ctxt = mhi_alloc_coherent(mhi_cntrl, + sizeof(*mhi_ctxt->er_ctxt) * + mhi_cntrl->total_ev_rings, + &mhi_ctxt->er_ctxt_addr, + gfp_kernel); + if (!mhi_ctxt->er_ctxt) + goto error_alloc_er_ctxt; + + er_ctxt = mhi_ctxt->er_ctxt; + mhi_event = mhi_cntrl->mhi_event; + for (i = 0; i < mhi_cntrl->total_ev_rings; i++, er_ctxt++, + mhi_event++) { + struct mhi_ring *ring = &mhi_event->ring; + + /* skip if it is an offload event */ + if (mhi_event->offload_ev) + continue; + + tmp = er_ctxt->intmod; + tmp &= ~ev_ctx_intmodc_mask; + tmp &= ~ev_ctx_intmodt_mask; + tmp |= (mhi_event->intmod << ev_ctx_intmodt_shift); + er_ctxt->intmod = tmp; + + er_ctxt->ertype = mhi_er_type_valid; + er_ctxt->msivec = mhi_event->irq; + mhi_event->db_cfg.db_mode = true; + + ring->el_size = sizeof(struct mhi_tre); + ring->len = ring->el_size * ring->elements; + ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len); + if (ret) + goto error_alloc_er; + + /* + * if the read pointer equals to the write pointer, then the + * ring is empty + */ + ring->rp = ring->wp = ring->base; + er_ctxt->rbase = ring->iommu_base; + er_ctxt->rp = er_ctxt->wp = er_ctxt->rbase; + er_ctxt->rlen = ring->len; + ring->ctxt_wp = &er_ctxt->wp; + } + + /* setup cmd context */ + mhi_ctxt->cmd_ctxt = mhi_alloc_coherent(mhi_cntrl, + sizeof(*mhi_ctxt->cmd_ctxt) * + nr_of_cmd_rings, + &mhi_ctxt->cmd_ctxt_addr, + gfp_kernel); + if (!mhi_ctxt->cmd_ctxt) + goto error_alloc_er; + + mhi_cmd = mhi_cntrl->mhi_cmd; + cmd_ctxt = mhi_ctxt->cmd_ctxt; + for (i = 0; i < nr_of_cmd_rings; i++, mhi_cmd++, cmd_ctxt++) { + struct mhi_ring *ring = &mhi_cmd->ring; + + ring->el_size = sizeof(struct mhi_tre); + ring->elements = cmd_el_per_ring; + ring->len = ring->el_size * ring->elements; + ret = mhi_alloc_aligned_ring(mhi_cntrl, ring, ring->len); + if (ret) + goto error_alloc_cmd; + + ring->rp = ring->wp = ring->base; + cmd_ctxt->rbase = ring->iommu_base; + cmd_ctxt->rp = cmd_ctxt->wp = cmd_ctxt->rbase; + cmd_ctxt->rlen = ring->len; + ring->ctxt_wp = &cmd_ctxt->wp; + } + + mhi_cntrl->mhi_ctxt = mhi_ctxt; + + return 0; + +error_alloc_cmd: + for (--i, --mhi_cmd; i >= 0; i--, mhi_cmd--) { + struct mhi_ring *ring = &mhi_cmd->ring; + + mhi_free_coherent(mhi_cntrl, ring->alloc_size, + ring->pre_aligned, ring->dma_handle); + } + mhi_free_coherent(mhi_cntrl, + sizeof(*mhi_ctxt->cmd_ctxt) * nr_of_cmd_rings, + mhi_ctxt->cmd_ctxt, mhi_ctxt->cmd_ctxt_addr); + i = mhi_cntrl->total_ev_rings; + mhi_event = mhi_cntrl->mhi_event + i; + +error_alloc_er: + for (--i, --mhi_event; i >= 0; i--, mhi_event--) { + struct mhi_ring *ring = &mhi_event->ring; + + if (mhi_event->offload_ev) + continue; + + mhi_free_coherent(mhi_cntrl, ring->alloc_size, + ring->pre_aligned, ring->dma_handle); + } + mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->er_ctxt) * + mhi_cntrl->total_ev_rings, mhi_ctxt->er_ctxt, + mhi_ctxt->er_ctxt_addr); + +error_alloc_er_ctxt: + mhi_free_coherent(mhi_cntrl, sizeof(*mhi_ctxt->chan_ctxt) * + mhi_cntrl->max_chan, mhi_ctxt->chan_ctxt, + mhi_ctxt->chan_ctxt_addr); + +error_alloc_chan_ctxt: + kfree(mhi_ctxt); + + return ret; +} + +int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl) +{ + int ret; + + mutex_lock(&mhi_cntrl->pm_mutex); + + ret = mhi_init_dev_ctxt(mhi_cntrl); + if (ret) + goto error_dev_ctxt; + + mhi_cntrl->pre_init = true; + + mutex_unlock(&mhi_cntrl->pm_mutex); + + return 0; + +error_dev_ctxt: + mutex_unlock(&mhi_cntrl->pm_mutex); + + return ret; +} +export_symbol_gpl(mhi_prepare_for_power_up); + +void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl) +{ + if (mhi_cntrl->fbc_image) { + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); + mhi_cntrl->fbc_image = null; + } + + mhi_deinit_dev_ctxt(mhi_cntrl); + mhi_cntrl->pre_init = false; +} +export_symbol_gpl(mhi_unprepare_after_power_down); + diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h +int mhi_alloc_bhie_table(struct mhi_controller *mhi_cntrl, + struct image_info **image_info, size_t alloc_size); +void mhi_free_bhie_table(struct mhi_controller *mhi_cntrl, + struct image_info *image_info); + +int mhi_init_dev_ctxt(struct mhi_controller *mhi_cntrl); +void mhi_deinit_dev_ctxt(struct mhi_controller *mhi_cntrl); +int mhi_init_irq_setup(struct mhi_controller *mhi_cntrl); +void mhi_deinit_free_irq(struct mhi_controller *mhi_cntrl); + +/* memory allocation methods */ +static inline void *mhi_alloc_coherent(struct mhi_controller *mhi_cntrl, + size_t size, + dma_addr_t *dma_handle, + gfp_t gfp) +{ + void *buf = dma_alloc_coherent(mhi_cntrl->cntrl_dev, size, dma_handle, + gfp); + + return buf; +} + +static inline void mhi_free_coherent(struct mhi_controller *mhi_cntrl, + size_t size, + void *vaddr, + dma_addr_t dma_handle) +{ + dma_free_coherent(mhi_cntrl->cntrl_dev, size, vaddr, dma_handle); +} + +/* isr handlers */ +irqreturn_t mhi_irq_handler(int irq_number, void *dev); +irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev); +irqreturn_t mhi_intvec_handler(int irq_number, void *dev); diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c +static void *mhi_to_virtual(struct mhi_ring *ring, dma_addr_t addr) +{ + return (addr - ring->iommu_base) + ring->base; +} + + +irqreturn_t mhi_irq_handler(int irq_number, void *dev) +{ + struct mhi_event *mhi_event = dev; + struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; + struct mhi_event_ctxt *er_ctxt = + &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; + struct mhi_ring *ev_ring = &mhi_event->ring; + void *dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + + /* only proceed if event ring has pending events */ + if (ev_ring->rp == dev_rp) + return irq_handled; + + /* for client managed event ring, notify pending data */ + if (mhi_event->cl_manage) { + struct mhi_chan *mhi_chan = mhi_event->mhi_chan; + struct mhi_device *mhi_dev = mhi_chan->mhi_dev; + + if (mhi_dev) + mhi_notify(mhi_dev, mhi_cb_pending_data); + } else { + tasklet_schedule(&mhi_event->task); + } + + return irq_handled; +} + +irqreturn_t mhi_intvec_threaded_handler(int irq_number, void *dev) +{ + struct mhi_controller *mhi_cntrl = dev; + enum mhi_state state = mhi_state_max; + enum mhi_pm_state pm_state = 0; + enum mhi_ee_type ee = 0; + + write_lock_irq(&mhi_cntrl->pm_lock); + if (mhi_reg_access_valid(mhi_cntrl->pm_state)) { + state = mhi_get_mhi_state(mhi_cntrl); + ee = mhi_cntrl->ee; + mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl); + } + + if (state == mhi_state_sys_err) { + dev_dbg(&mhi_cntrl->mhi_dev->dev, "system error detected "); + pm_state = mhi_tryset_pm_state(mhi_cntrl, + mhi_pm_sys_err_detect); + } + write_unlock_irq(&mhi_cntrl->pm_lock); + + /* if device in rddm don't bother processing sys error */ + if (mhi_cntrl->ee == mhi_ee_rddm) { + if (mhi_cntrl->ee != ee) { + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_ee_rddm); + wake_up_all(&mhi_cntrl->state_event); + } + goto exit_intvec; + } + + if (pm_state == mhi_pm_sys_err_detect) { + wake_up_all(&mhi_cntrl->state_event); + + /* for fatal errors, we let controller decide next step */ + if (mhi_in_pbl(ee)) + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_fatal_error); + else + schedule_work(&mhi_cntrl->syserr_worker); + } + +exit_intvec: + + return irq_handled; +} + +irqreturn_t mhi_intvec_handler(int irq_number, void *dev) +{ + struct mhi_controller *mhi_cntrl = dev; + + /* wake up events waiting for state change */ + wake_up_all(&mhi_cntrl->state_event); + + return irq_wake_thread; +} diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c +/* nop for backward compatibility, host allowed to ring db in m2 state */ +static void mhi_toggle_dev_wake_nop(struct mhi_controller *mhi_cntrl) +{ +} + +static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl) +{ + mhi_cntrl->wake_get(mhi_cntrl, false); + mhi_cntrl->wake_put(mhi_cntrl, true); +} + + +/* assert device wake db */ +static void mhi_assert_dev_wake(struct mhi_controller *mhi_cntrl, bool force) +{ + unsigned long flags; + + /* + * if force flag is set, then increment the wake count value and + * ring wake db + */ + if (unlikely(force)) { + spin_lock_irqsave(&mhi_cntrl->wlock, flags); + atomic_inc(&mhi_cntrl->dev_wake); + if (mhi_wake_db_force_set_valid(mhi_cntrl->pm_state) && + !mhi_cntrl->wake_set) { + mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1); + mhi_cntrl->wake_set = true; + } + spin_unlock_irqrestore(&mhi_cntrl->wlock, flags); + } else { + /* + * if resources are already requested, then just increment + * the wake count value and return + */ + if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, 1, 0))) + return; + + spin_lock_irqsave(&mhi_cntrl->wlock, flags); + if ((atomic_inc_return(&mhi_cntrl->dev_wake) == 1) && + mhi_wake_db_set_valid(mhi_cntrl->pm_state) && + !mhi_cntrl->wake_set) { + mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 1); + mhi_cntrl->wake_set = true; + } + spin_unlock_irqrestore(&mhi_cntrl->wlock, flags); + } +} + +/* de-assert device wake db */ +static void mhi_deassert_dev_wake(struct mhi_controller *mhi_cntrl, + bool override) +{ + unsigned long flags; + + /* + * only continue if there is a single resource, else just decrement + * and return + */ + if (likely(atomic_add_unless(&mhi_cntrl->dev_wake, -1, 1))) + return; + + spin_lock_irqsave(&mhi_cntrl->wlock, flags); + if ((atomic_dec_return(&mhi_cntrl->dev_wake) == 0) && + mhi_wake_db_clear_valid(mhi_cntrl->pm_state) && !override && + mhi_cntrl->wake_set) { + mhi_write_db(mhi_cntrl, mhi_cntrl->wake_db, 0); + mhi_cntrl->wake_set = false; + } + spin_unlock_irqrestore(&mhi_cntrl->wlock, flags); +} + +int mhi_async_power_up(struct mhi_controller *mhi_cntrl) +{ + enum mhi_ee_type current_ee; + enum dev_st_transition next_state; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + u32 val; + int ret; + + dev_info(dev, "requested to power on "); + + if (mhi_cntrl->nr_irqs < mhi_cntrl->total_ev_rings) + return -einval; + + /* supply default wake routines if not provided by controller driver */ + if (!mhi_cntrl->wake_get || !mhi_cntrl->wake_put || + !mhi_cntrl->wake_toggle) { + mhi_cntrl->wake_get = mhi_assert_dev_wake; + mhi_cntrl->wake_put = mhi_deassert_dev_wake; + mhi_cntrl->wake_toggle = (mhi_cntrl->db_access & mhi_pm_m2) ? + mhi_toggle_dev_wake_nop : mhi_toggle_dev_wake; + } + + mutex_lock(&mhi_cntrl->pm_mutex); + mhi_cntrl->pm_state = mhi_pm_disable; + + if (!mhi_cntrl->pre_init) { + /* setup device context */ + ret = mhi_init_dev_ctxt(mhi_cntrl); + if (ret) + goto error_dev_ctxt; + } + + ret = mhi_init_irq_setup(mhi_cntrl); + if (ret) + goto error_setup_irq; + + /* setup bhi offset & intvec */ + write_lock_irq(&mhi_cntrl->pm_lock); + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, bhioff, &val); + if (ret) { + write_unlock_irq(&mhi_cntrl->pm_lock); + goto error_bhi_offset; + } + + mhi_cntrl->bhi = mhi_cntrl->regs + val; + + /* setup bhie offset */ + if (mhi_cntrl->fbc_download) { + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, bhieoff, &val); + if (ret) { + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_err(dev, "error reading bhie offset "); + goto error_bhi_offset; + } + + mhi_cntrl->bhie = mhi_cntrl->regs + val; + } + + mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, bhi_intvec, 0); + mhi_cntrl->pm_state = mhi_pm_por; + mhi_cntrl->ee = mhi_ee_max; + current_ee = mhi_get_exec_env(mhi_cntrl); + write_unlock_irq(&mhi_cntrl->pm_lock); + + /* confirm that the device is in valid exec env */ + if (!mhi_in_pbl(current_ee) && current_ee != mhi_ee_amss) { + dev_err(dev, "not a valid ee for power on "); + ret = -eio; + goto error_bhi_offset; + } + + /* transition to next state */ + next_state = mhi_in_pbl(current_ee) ? + dev_st_transition_pbl : dev_st_transition_ready; + + if (next_state == dev_st_transition_pbl) + schedule_work(&mhi_cntrl->fw_worker); + + mhi_queue_state_transition(mhi_cntrl, next_state); + + mutex_unlock(&mhi_cntrl->pm_mutex); + + dev_info(dev, "power on setup success "); + + return 0; + +error_bhi_offset: + mhi_deinit_free_irq(mhi_cntrl); + +error_setup_irq: + if (!mhi_cntrl->pre_init) + mhi_deinit_dev_ctxt(mhi_cntrl); + +error_dev_ctxt: + mutex_unlock(&mhi_cntrl->pm_mutex); + + return ret; +} +export_symbol_gpl(mhi_async_power_up); + +void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful) +{ + enum mhi_pm_state cur_state; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + /* if it's not a graceful shutdown, force mhi to linkdown state */ + if (!graceful) { + mutex_lock(&mhi_cntrl->pm_mutex); + write_lock_irq(&mhi_cntrl->pm_lock); + cur_state = mhi_tryset_pm_state(mhi_cntrl, + mhi_pm_ld_err_fatal_detect); + write_unlock_irq(&mhi_cntrl->pm_lock); + mutex_unlock(&mhi_cntrl->pm_mutex); + if (cur_state != mhi_pm_ld_err_fatal_detect) + dev_dbg(dev, "failed to move to state: %s from: %s ", + to_mhi_pm_state_str(mhi_pm_ld_err_fatal_detect), + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + } + mhi_pm_disable_transition(mhi_cntrl, mhi_pm_shutdown_process); + mhi_deinit_free_irq(mhi_cntrl); + + if (!mhi_cntrl->pre_init) { + /* free all allocated resources */ + if (mhi_cntrl->fbc_image) { + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); + mhi_cntrl->fbc_image = null; + } + mhi_deinit_dev_ctxt(mhi_cntrl); + } +} +export_symbol_gpl(mhi_power_down); + +int mhi_sync_power_up(struct mhi_controller *mhi_cntrl) +{ + int ret = mhi_async_power_up(mhi_cntrl); + + if (ret) + return ret; + + wait_event_timeout(mhi_cntrl->state_event, + mhi_in_mission_mode(mhi_cntrl->ee) || + mhi_pm_in_error_state(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + return (mhi_in_mission_mode(mhi_cntrl->ee)) ? 0 : -eio; +} +export_symbol(mhi_sync_power_up); diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h +/** + * struct image_info - firmware and rddm table table + * @mhi_buf - buffer for firmware and rddm table + * @entries - # of entries in table + */ +struct image_info { + struct mhi_buf *mhi_buf; + struct bhi_vec_entry *bhi_vec; + u32 entries; +}; + + * @bhie: points to base of mhi bhie register space + * @fbc_image: points to firmware image buffer + void __iomem *bhie; + struct image_info *fbc_image; +/** + * mhi_prepare_for_power_up - do pre-initialization before power up. + * this is optional, call this before power up if + * the controller does not want bus framework to + * automatically free any allocated memory during + * shutdown process. + * @mhi_cntrl: mhi controller + */ +int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl); + +/** + * mhi_async_power_up - start mhi power up sequence + * @mhi_cntrl: mhi controller + */ +int mhi_async_power_up(struct mhi_controller *mhi_cntrl); + +/** + * mhi_sync_power_up - start mhi power up sequence and wait till the device + * device enters valid ee state + * @mhi_cntrl: mhi controller + */ +int mhi_sync_power_up(struct mhi_controller *mhi_cntrl); + +/** + * mhi_power_down - start mhi power down sequence + * @mhi_cntrl: mhi controller + * @graceful: link is still accessible, so do a graceful shutdown process + */ +void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful); + +/** + * mhi_unprepare_after_power_down - free any allocated memory after power down + * @mhi_cntrl: mhi controller + */ +void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl); +
|
Modem Host Interface (MHI) Bus
|
3000f85b8f47b2c860add5cce4c201c83bde6468
|
manivannan sadhasivam
|
include
|
linux
|
core, mhi
|
bus: mhi: core: add support for downloading firmware over bhie
|
mhi supports downloading the device firmware over bhi/bhie (boot host interface) protocol. hence, this commit adds necessary helpers, which will be called during device power up stage.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 3
| 270
| 0
|
--- diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c --- a/drivers/bus/mhi/core/boot.c +++ b/drivers/bus/mhi/core/boot.c +static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, + const struct mhi_buf *mhi_buf) +{ + void __iomem *base = mhi_cntrl->bhie; + rwlock_t *pm_lock = &mhi_cntrl->pm_lock; + u32 tx_status, sequence_id; + + read_lock_bh(pm_lock); + if (!mhi_reg_access_valid(mhi_cntrl->pm_state)) { + read_unlock_bh(pm_lock); + return -eio; + } + + mhi_write_reg(mhi_cntrl, base, bhie_txvecaddr_high_offs, + upper_32_bits(mhi_buf->dma_addr)); + + mhi_write_reg(mhi_cntrl, base, bhie_txvecaddr_low_offs, + lower_32_bits(mhi_buf->dma_addr)); + + mhi_write_reg(mhi_cntrl, base, bhie_txvecsize_offs, mhi_buf->len); + + sequence_id = prandom_u32() & bhie_txvecstatus_seqnum_bmsk; + mhi_write_reg_field(mhi_cntrl, base, bhie_txvecdb_offs, + bhie_txvecdb_seqnum_bmsk, bhie_txvecdb_seqnum_shft, + sequence_id); + read_unlock_bh(pm_lock); + + /* wait for the image download to complete */ + wait_event_timeout(mhi_cntrl->state_event, + mhi_pm_in_error_state(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, base, + bhie_txvecstatus_offs, + bhie_txvecstatus_status_bmsk, + bhie_txvecstatus_status_shft, + &tx_status) || tx_status, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (mhi_pm_in_error_state(mhi_cntrl->pm_state)) + return -eio; + + return (tx_status == bhie_txvecstatus_status_xfer_compl) ? 0 : -eio; +} + +static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, + dma_addr_t dma_addr, + size_t size) +{ + u32 tx_status, val, session_id; + int i, ret; + void __iomem *base = mhi_cntrl->bhi; + rwlock_t *pm_lock = &mhi_cntrl->pm_lock; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + struct { + char *name; + u32 offset; + } error_reg[] = { + { "error_code", bhi_errcode }, + { "error_dbg1", bhi_errdbg1 }, + { "error_dbg2", bhi_errdbg2 }, + { "error_dbg3", bhi_errdbg3 }, + { null }, + }; + + read_lock_bh(pm_lock); + if (!mhi_reg_access_valid(mhi_cntrl->pm_state)) { + read_unlock_bh(pm_lock); + goto invalid_pm_state; + } + + dev_dbg(dev, "starting sbl download via bhi "); + mhi_write_reg(mhi_cntrl, base, bhi_status, 0); + mhi_write_reg(mhi_cntrl, base, bhi_imgaddr_high, + upper_32_bits(dma_addr)); + mhi_write_reg(mhi_cntrl, base, bhi_imgaddr_low, + lower_32_bits(dma_addr)); + mhi_write_reg(mhi_cntrl, base, bhi_imgsize, size); + session_id = prandom_u32() & bhi_txdb_seqnum_bmsk; + mhi_write_reg(mhi_cntrl, base, bhi_imgtxdb, session_id); + read_unlock_bh(pm_lock); + + /* wait for the image download to complete */ + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_pm_in_error_state(mhi_cntrl->pm_state) || + mhi_read_reg_field(mhi_cntrl, base, bhi_status, + bhi_status_mask, bhi_status_shift, + &tx_status) || tx_status, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (mhi_pm_in_error_state(mhi_cntrl->pm_state)) + goto invalid_pm_state; + + if (tx_status == bhi_status_error) { + dev_err(dev, "image transfer failed "); + read_lock_bh(pm_lock); + if (mhi_reg_access_valid(mhi_cntrl->pm_state)) { + for (i = 0; error_reg[i].name; i++) { + ret = mhi_read_reg(mhi_cntrl, base, + error_reg[i].offset, &val); + if (ret) + break; + dev_err(dev, "reg: %s value: 0x%x ", + error_reg[i].name, val); + } + } + read_unlock_bh(pm_lock); + goto invalid_pm_state; + } + + return (!ret) ? -etimedout : 0; + +invalid_pm_state: + + return -eio; +} + + +static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl, + const struct firmware *firmware, + struct image_info *img_info) +{ + size_t remainder = firmware->size; + size_t to_cpy; + const u8 *buf = firmware->data; + int i = 0; + struct mhi_buf *mhi_buf = img_info->mhi_buf; + struct bhi_vec_entry *bhi_vec = img_info->bhi_vec; + + while (remainder) { + to_cpy = min(remainder, mhi_buf->len); + memcpy(mhi_buf->buf, buf, to_cpy); + bhi_vec->dma_addr = mhi_buf->dma_addr; + bhi_vec->size = to_cpy; + + buf += to_cpy; + remainder -= to_cpy; + i++; + bhi_vec++; + mhi_buf++; + } +} + +void mhi_fw_load_worker(struct work_struct *work) +{ + struct mhi_controller *mhi_cntrl; + const struct firmware *firmware = null; + struct image_info *image_info; + struct device *dev; + const char *fw_name; + void *buf; + dma_addr_t dma_addr; + size_t size; + int ret; + + mhi_cntrl = container_of(work, struct mhi_controller, fw_worker); + dev = &mhi_cntrl->mhi_dev->dev; + + dev_dbg(dev, "waiting for device to enter pbl from: %s ", + to_mhi_exec_str(mhi_cntrl->ee)); + + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_in_pbl(mhi_cntrl->ee) || + mhi_pm_in_error_state(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || mhi_pm_in_error_state(mhi_cntrl->pm_state)) { + dev_err(dev, "device mhi is not in valid state "); + return; + } + + /* if device is in pass through, do reset to ready state transition */ + if (mhi_cntrl->ee == mhi_ee_pthru) + goto fw_load_ee_pthru; + + fw_name = (mhi_cntrl->ee == mhi_ee_edl) ? + mhi_cntrl->edl_image : mhi_cntrl->fw_image; + + if (!fw_name || (mhi_cntrl->fbc_download && (!mhi_cntrl->sbl_size || + !mhi_cntrl->seg_len))) { + dev_err(dev, + "no firmware image defined or !sbl_size || !seg_len "); + return; + } + + ret = request_firmware(&firmware, fw_name, dev); + if (ret) { + dev_err(dev, "error loading firmware: %d ", ret); + return; + } + + size = (mhi_cntrl->fbc_download) ? mhi_cntrl->sbl_size : firmware->size; + + /* sbl size provided is maximum size, not necessarily the image size */ + if (size > firmware->size) + size = firmware->size; + + buf = mhi_alloc_coherent(mhi_cntrl, size, &dma_addr, gfp_kernel); + if (!buf) { + release_firmware(firmware); + return; + } + + /* download sbl image */ + memcpy(buf, firmware->data, size); + ret = mhi_fw_load_sbl(mhi_cntrl, dma_addr, size); + mhi_free_coherent(mhi_cntrl, size, buf, dma_addr); + + if (!mhi_cntrl->fbc_download || ret || mhi_cntrl->ee == mhi_ee_edl) + release_firmware(firmware); + + /* error or in edl mode, we're done */ + if (ret || mhi_cntrl->ee == mhi_ee_edl) + return; + + write_lock_irq(&mhi_cntrl->pm_lock); + mhi_cntrl->dev_state = mhi_state_reset; + write_unlock_irq(&mhi_cntrl->pm_lock); + + /* + * if we're doing fbc, populate vector tables while + * device transitioning into mhi ready state + */ + if (mhi_cntrl->fbc_download) { + ret = mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->fbc_image, + firmware->size); + if (ret) + goto error_alloc_fw_table; + + /* load the firmware into bhie vec table */ + mhi_firmware_copy(mhi_cntrl, firmware, mhi_cntrl->fbc_image); + } + +fw_load_ee_pthru: + /* transitioning into mhi reset->ready state */ + ret = mhi_ready_state_transition(mhi_cntrl); + + if (!mhi_cntrl->fbc_download) + return; + + if (ret) + goto error_read; + + /* wait for the sbl event */ + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->ee == mhi_ee_sbl || + mhi_pm_in_error_state(mhi_cntrl->pm_state), + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + if (!ret || mhi_pm_in_error_state(mhi_cntrl->pm_state)) { + dev_err(dev, "mhi did not enter sbl "); + goto error_read; + } + + /* start full firmware image download */ + image_info = mhi_cntrl->fbc_image; + ret = mhi_fw_load_amss(mhi_cntrl, + /* vector table is the last entry */ + &image_info->mhi_buf[image_info->entries - 1]); + + release_firmware(firmware); + + return; + +error_read: + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image); + mhi_cntrl->fbc_image = null; + +error_alloc_fw_table: + release_firmware(firmware); +} diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c + init_work(&mhi_cntrl->fw_worker, mhi_fw_load_worker); diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h +void mhi_fw_load_worker(struct work_struct *work);
|
Modem Host Interface (MHI) Bus
|
cd457afb16670501f00354eb0e705a7d8a50d79d
|
manivannan sadhasivam
|
drivers
|
bus
|
core, mhi
|
bus: mhi: core: add support for downloading rddm image during panic
|
mhi protocol supports downloading rddm (ram dump) image from the device through bhie. this is useful to debugging as the rddm image can capture the firmware state.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 5
| 249
| 0
|
--- diff --git a/drivers/bus/mhi/core/boot.c b/drivers/bus/mhi/core/boot.c --- a/drivers/bus/mhi/core/boot.c +++ b/drivers/bus/mhi/core/boot.c +/* setup rddm vector table for rddm transfer and program rxvec */ +void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, + struct image_info *img_info) +{ + struct mhi_buf *mhi_buf = img_info->mhi_buf; + struct bhi_vec_entry *bhi_vec = img_info->bhi_vec; + void __iomem *base = mhi_cntrl->bhie; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + u32 sequence_id; + unsigned int i; + + for (i = 0; i < img_info->entries - 1; i++, mhi_buf++, bhi_vec++) { + bhi_vec->dma_addr = mhi_buf->dma_addr; + bhi_vec->size = mhi_buf->len; + } + + dev_dbg(dev, "bhie programming for rddm "); + + mhi_write_reg(mhi_cntrl, base, bhie_rxvecaddr_high_offs, + upper_32_bits(mhi_buf->dma_addr)); + + mhi_write_reg(mhi_cntrl, base, bhie_rxvecaddr_low_offs, + lower_32_bits(mhi_buf->dma_addr)); + + mhi_write_reg(mhi_cntrl, base, bhie_rxvecsize_offs, mhi_buf->len); + sequence_id = prandom_u32() & bhie_rxvecstatus_seqnum_bmsk; + + if (unlikely(!sequence_id)) + sequence_id = 1; + + mhi_write_reg_field(mhi_cntrl, base, bhie_rxvecdb_offs, + bhie_rxvecdb_seqnum_bmsk, bhie_rxvecdb_seqnum_shft, + sequence_id); + + dev_dbg(dev, "address: %p and len: 0x%lx sequence: %u ", + &mhi_buf->dma_addr, mhi_buf->len, sequence_id); +} + +/* collect rddm buffer during kernel panic */ +static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) +{ + int ret; + u32 rx_status; + enum mhi_ee_type ee; + const u32 delayus = 2000; + u32 retry = (mhi_cntrl->timeout_ms * 1000) / delayus; + const u32 rddm_timeout_us = 200000; + int rddm_retry = rddm_timeout_us / delayus; + void __iomem *base = mhi_cntrl->bhie; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + dev_dbg(dev, "entered with pm_state:%s dev_state:%s ee:%s ", + to_mhi_pm_state_str(mhi_cntrl->pm_state), + to_mhi_state_str(mhi_cntrl->dev_state), + to_mhi_exec_str(mhi_cntrl->ee)); + + /* + * this should only be executing during a kernel panic, we expect all + * other cores to shutdown while we're collecting rddm buffer. after + * returning from this function, we expect the device to reset. + * + * normaly, we read/write pm_state only after grabbing the + * pm_lock, since we're in a panic, skipping it. also there is no + * gurantee that this state change would take effect since + * we're setting it w/o grabbing pm_lock + */ + mhi_cntrl->pm_state = mhi_pm_ld_err_fatal_detect; + /* update should take the effect immediately */ + smp_wmb(); + + /* + * make sure device is not already in rddm. in case the device asserts + * and a kernel panic follows, device will already be in rddm. + * do not trigger sys err again and proceed with waiting for + * image download completion. + */ + ee = mhi_get_exec_env(mhi_cntrl); + if (ee != mhi_ee_rddm) { + dev_dbg(dev, "trigger device into rddm mode using sys err "); + mhi_set_mhi_state(mhi_cntrl, mhi_state_sys_err); + + dev_dbg(dev, "waiting for device to enter rddm "); + while (rddm_retry--) { + ee = mhi_get_exec_env(mhi_cntrl); + if (ee == mhi_ee_rddm) + break; + + udelay(delayus); + } + + if (rddm_retry <= 0) { + /* hardware reset so force device to enter rddm */ + dev_dbg(dev, + "did not enter rddm, do a host req reset "); + mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, + mhi_soc_reset_req_offset, + mhi_soc_reset_req); + udelay(delayus); + } + + ee = mhi_get_exec_env(mhi_cntrl); + } + + dev_dbg(dev, "waiting for image download completion, current ee: %s ", + to_mhi_exec_str(ee)); + + while (retry--) { + ret = mhi_read_reg_field(mhi_cntrl, base, bhie_rxvecstatus_offs, + bhie_rxvecstatus_status_bmsk, + bhie_rxvecstatus_status_shft, + &rx_status); + if (ret) + return -eio; + + if (rx_status == bhie_rxvecstatus_status_xfer_compl) + return 0; + + udelay(delayus); + } + + ee = mhi_get_exec_env(mhi_cntrl); + ret = mhi_read_reg(mhi_cntrl, base, bhie_rxvecstatus_offs, &rx_status); + + dev_err(dev, "did not complete rddm transfer "); + dev_err(dev, "current ee: %s ", to_mhi_exec_str(ee)); + dev_err(dev, "rxvec_status: 0x%x ", rx_status); + + return -eio; +} + +/* download rddm image from device */ +int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic) +{ + void __iomem *base = mhi_cntrl->bhie; + u32 rx_status; + + if (in_panic) + return __mhi_download_rddm_in_panic(mhi_cntrl); + + /* wait for the image download to complete */ + wait_event_timeout(mhi_cntrl->state_event, + mhi_read_reg_field(mhi_cntrl, base, + bhie_rxvecstatus_offs, + bhie_rxvecstatus_status_bmsk, + bhie_rxvecstatus_status_shft, + &rx_status) || rx_status, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + + return (rx_status == bhie_rxvecstatus_status_xfer_compl) ? 0 : -eio; +} +export_symbol_gpl(mhi_download_rddm_img); + diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c + struct device *dev = &mhi_cntrl->mhi_dev->dev; + u32 bhie_off; + /* + * allocate rddm table if specified, this table is for debugging purpose + */ + if (mhi_cntrl->rddm_size) { + mhi_alloc_bhie_table(mhi_cntrl, &mhi_cntrl->rddm_image, + mhi_cntrl->rddm_size); + + /* + * this controller supports rddm, so we need to manually clear + * bhie rx registers since por values are undefined. + */ + ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs, bhieoff, + &bhie_off); + if (ret) { + dev_err(dev, "error getting bhie offset "); + goto bhie_error; + } + + memset_io(mhi_cntrl->regs + bhie_off + bhie_rxvecaddr_low_offs, + 0, bhie_rxvecstatus_offs - bhie_rxvecaddr_low_offs + + 4); + + if (mhi_cntrl->rddm_image) + mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image); + } + +bhie_error: + if (mhi_cntrl->rddm_image) { + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); + mhi_cntrl->rddm_image = null; + } + + if (mhi_cntrl->rddm_image) { + mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->rddm_image); + mhi_cntrl->rddm_image = null; + } + diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h +void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, + struct image_info *img_info); diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c + /* + * if controller supports rddm, we do not process + * sys error state, instead we will jump directly + * to rddm state + */ + if (mhi_cntrl->rddm_image) { + dev_dbg(dev, + "controller supports rddm, so skip sys_err "); + return; + } + +int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl) +{ + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int ret; + + /* check if device is already in rddm */ + if (mhi_cntrl->ee == mhi_ee_rddm) + return 0; + + dev_dbg(dev, "triggering sys_err to force rddm state "); + mhi_set_mhi_state(mhi_cntrl, mhi_state_sys_err); + + /* wait for rddm event */ + ret = wait_event_timeout(mhi_cntrl->state_event, + mhi_cntrl->ee == mhi_ee_rddm, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + ret = ret ? 0 : -eio; + + return ret; +} +export_symbol_gpl(mhi_force_rddm_mode); diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h + * @rddm_size: ram dump size that host should allocate for debugging purpose + * @rddm_image: points to ram dump buffer + size_t rddm_size; + struct image_info *rddm_image; +/** + * mhi_download_rddm_img - download ramdump image from device for + * debugging purpose. + * @mhi_cntrl: mhi controller + * @in_panic: download rddm image during kernel panic + */ +int mhi_download_rddm_img(struct mhi_controller *mhi_cntrl, bool in_panic); + +/** + * mhi_force_rddm_mode - force device into rddm mode + * @mhi_cntrl: mhi controller + */ +int mhi_force_rddm_mode(struct mhi_controller *mhi_cntrl); + +/** + * mhi_get_mhi_state - get mhi state of the device + * @mhi_cntrl: mhi controller + */ +enum mhi_state mhi_get_mhi_state(struct mhi_controller *mhi_cntrl); +
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Modem Host Interface (MHI) Bus
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6fdfdd27328ceef39f4b8daec3510874ad68e753
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manivannan sadhasivam
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include
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linux
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core, mhi
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bus: mhi: core: add support for processing events from client device
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this commit adds support for processing the mhi data and control events from the client device. the client device can report various events such as ee events, state change events by interrupting the host through irq and adding events to the event rings allocated by the host during initialization.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
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[]
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['h', 'c']
| 4
| 510
| 0
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--- diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c + switch (mhi_event->data_type) { + case mhi_er_data: + mhi_event->process_event = mhi_process_data_event_ring; + break; + case mhi_er_ctrl: + mhi_event->process_event = mhi_process_ctrl_ev_ring; + break; + default: + dev_err(dev, "event ring type not supported "); + goto error_ev_cfg; + } + + if (mhi_event->data_type == mhi_er_ctrl) + tasklet_init(&mhi_event->task, mhi_ctrl_ev_task, + (ulong)mhi_event); + else + tasklet_init(&mhi_event->task, mhi_ev_task, + (ulong)mhi_event); diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h + bool used; /* indicates whether the buffer is used or not */ + bool pre_mapped; /* already pre-mapped by client */ +/* event processing methods */ +void mhi_ctrl_ev_task(unsigned long data); +void mhi_ev_task(unsigned long data); +int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, u32 event_quota); +int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, u32 event_quota); + diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c +static void mhi_del_ring_element(struct mhi_controller *mhi_cntrl, + struct mhi_ring *ring) +{ + ring->rp += ring->el_size; + if (ring->rp >= (ring->base + ring->len)) + ring->rp = ring->base; + /* smp update */ + smp_wmb(); +} + + +static void mhi_recycle_ev_ring_element(struct mhi_controller *mhi_cntrl, + struct mhi_ring *ring) +{ + dma_addr_t ctxt_wp; + + /* update the wp */ + ring->wp += ring->el_size; + ctxt_wp = *ring->ctxt_wp + ring->el_size; + + if (ring->wp >= (ring->base + ring->len)) { + ring->wp = ring->base; + ctxt_wp = ring->iommu_base; + } + + *ring->ctxt_wp = ctxt_wp; + + /* update the rp */ + ring->rp += ring->el_size; + if (ring->rp >= (ring->base + ring->len)) + ring->rp = ring->base; + + /* update to all cores */ + smp_wmb(); +} + +static int parse_xfer_event(struct mhi_controller *mhi_cntrl, + struct mhi_tre *event, + struct mhi_chan *mhi_chan) +{ + struct mhi_ring *buf_ring, *tre_ring; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + struct mhi_result result; + unsigned long flags = 0; + u32 ev_code; + + ev_code = mhi_tre_get_ev_code(event); + buf_ring = &mhi_chan->buf_ring; + tre_ring = &mhi_chan->tre_ring; + + result.transaction_status = (ev_code == mhi_ev_cc_overflow) ? + -eoverflow : 0; + + /* + * if it's a db event then we need to grab the lock + * with preemption disabled and as a write because we + * have to update db register and there are chances that + * another thread could be doing the same. + */ + if (ev_code >= mhi_ev_cc_oob) + write_lock_irqsave(&mhi_chan->lock, flags); + else + read_lock_bh(&mhi_chan->lock); + + if (mhi_chan->ch_state != mhi_ch_state_enabled) + goto end_process_tx_event; + + switch (ev_code) { + case mhi_ev_cc_overflow: + case mhi_ev_cc_eob: + case mhi_ev_cc_eot: + { + dma_addr_t ptr = mhi_tre_get_ev_ptr(event); + struct mhi_tre *local_rp, *ev_tre; + void *dev_rp; + struct mhi_buf_info *buf_info; + u16 xfer_len; + + /* get the trb this event points to */ + ev_tre = mhi_to_virtual(tre_ring, ptr); + + /* device rp after servicing the tres */ + dev_rp = ev_tre + 1; + if (dev_rp >= (tre_ring->base + tre_ring->len)) + dev_rp = tre_ring->base; + + result.dir = mhi_chan->dir; + + /* local rp */ + local_rp = tre_ring->rp; + while (local_rp != dev_rp) { + buf_info = buf_ring->rp; + /* if it's the last tre, get length from the event */ + if (local_rp == ev_tre) + xfer_len = mhi_tre_get_ev_len(event); + else + xfer_len = buf_info->len; + + result.buf_addr = buf_info->cb_buf; + result.bytes_xferd = xfer_len; + mhi_del_ring_element(mhi_cntrl, buf_ring); + mhi_del_ring_element(mhi_cntrl, tre_ring); + local_rp = tre_ring->rp; + + /* notify client */ + mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + + if (mhi_chan->dir == dma_to_device) + atomic_dec(&mhi_cntrl->pending_pkts); + } + break; + } /* cc_eot */ + case mhi_ev_cc_oob: + case mhi_ev_cc_db_mode: + { + unsigned long flags; + + mhi_chan->db_cfg.db_mode = 1; + read_lock_irqsave(&mhi_cntrl->pm_lock, flags); + if (tre_ring->wp != tre_ring->rp && + mhi_db_access_valid(mhi_cntrl)) { + mhi_ring_chan_db(mhi_cntrl, mhi_chan); + } + read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); + break; + } + case mhi_ev_cc_bad_tre: + default: + dev_err(dev, "unknown event 0x%x ", ev_code); + break; + } /* switch(mhi_ev_read_code(ev_trb_code,event)) */ + +end_process_tx_event: + if (ev_code >= mhi_ev_cc_oob) + write_unlock_irqrestore(&mhi_chan->lock, flags); + else + read_unlock_bh(&mhi_chan->lock); + + return 0; +} + +static int parse_rsc_event(struct mhi_controller *mhi_cntrl, + struct mhi_tre *event, + struct mhi_chan *mhi_chan) +{ + struct mhi_ring *buf_ring, *tre_ring; + struct mhi_buf_info *buf_info; + struct mhi_result result; + int ev_code; + u32 cookie; /* offset to local descriptor */ + u16 xfer_len; + + buf_ring = &mhi_chan->buf_ring; + tre_ring = &mhi_chan->tre_ring; + + ev_code = mhi_tre_get_ev_code(event); + cookie = mhi_tre_get_ev_cookie(event); + xfer_len = mhi_tre_get_ev_len(event); + + /* received out of bound cookie */ + warn_on(cookie >= buf_ring->len); + + buf_info = buf_ring->base + cookie; + + result.transaction_status = (ev_code == mhi_ev_cc_overflow) ? + -eoverflow : 0; + result.bytes_xferd = xfer_len; + result.buf_addr = buf_info->cb_buf; + result.dir = mhi_chan->dir; + + read_lock_bh(&mhi_chan->lock); + + if (mhi_chan->ch_state != mhi_ch_state_enabled) + goto end_process_rsc_event; + + warn_on(!buf_info->used); + + /* notify the client */ + mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + + /* + * note: we're arbitrarily incrementing rp even though, completion + * packet we processed might not be the same one, reason we can do this + * is because device guaranteed to cache descriptors in order it + * receive, so even though completion event is different we can re-use + * all descriptors in between. + * example: + * transfer ring has descriptors: a, b, c, d + * last descriptor host queue is d (wp) and first descriptor + * host queue is a (rp). + * the completion event we just serviced is descriptor c. + * then we can safely queue descriptors to replace a, b, and c + * even though host did not receive any completions. + */ + mhi_del_ring_element(mhi_cntrl, tre_ring); + buf_info->used = false; + +end_process_rsc_event: + read_unlock_bh(&mhi_chan->lock); + + return 0; +} + +static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl, + struct mhi_tre *tre) +{ + dma_addr_t ptr = mhi_tre_get_ev_ptr(tre); + struct mhi_cmd *cmd_ring = &mhi_cntrl->mhi_cmd[primary_cmd_ring]; + struct mhi_ring *mhi_ring = &cmd_ring->ring; + struct mhi_tre *cmd_pkt; + struct mhi_chan *mhi_chan; + u32 chan; + + cmd_pkt = mhi_to_virtual(mhi_ring, ptr); + + chan = mhi_tre_get_cmd_chid(cmd_pkt); + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + write_lock_bh(&mhi_chan->lock); + mhi_chan->ccs = mhi_tre_get_ev_code(tre); + complete(&mhi_chan->completion); + write_unlock_bh(&mhi_chan->lock); + + mhi_del_ring_element(mhi_cntrl, mhi_ring); +} + +int mhi_process_ctrl_ev_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, + u32 event_quota) +{ + struct mhi_tre *dev_rp, *local_rp; + struct mhi_ring *ev_ring = &mhi_event->ring; + struct mhi_event_ctxt *er_ctxt = + &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; + struct mhi_chan *mhi_chan; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + u32 chan; + int count = 0; + + /* + * this is a quick check to avoid unnecessary event processing + * in case mhi is already in error state, but it's still possible + * to transition to error state while processing events + */ + if (unlikely(mhi_event_access_invalid(mhi_cntrl->pm_state))) + return -eio; + + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + local_rp = ev_ring->rp; + + while (dev_rp != local_rp) { + enum mhi_pkt_type type = mhi_tre_get_ev_type(local_rp); + + switch (type) { + case mhi_pkt_type_bw_req_event: + { + struct mhi_link_info *link_info; + + link_info = &mhi_cntrl->mhi_link_info; + write_lock_irq(&mhi_cntrl->pm_lock); + link_info->target_link_speed = + mhi_tre_get_ev_linkspeed(local_rp); + link_info->target_link_width = + mhi_tre_get_ev_linkwidth(local_rp); + write_unlock_irq(&mhi_cntrl->pm_lock); + dev_dbg(dev, "received bw_req event "); + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_bw_req); + break; + } + case mhi_pkt_type_state_change_event: + { + enum mhi_state new_state; + + new_state = mhi_tre_get_ev_state(local_rp); + + dev_dbg(dev, "state change event to state: %s ", + to_mhi_state_str(new_state)); + + switch (new_state) { + case mhi_state_m0: + mhi_pm_m0_transition(mhi_cntrl); + break; + case mhi_state_m1: + mhi_pm_m1_transition(mhi_cntrl); + break; + case mhi_state_m3: + mhi_pm_m3_transition(mhi_cntrl); + break; + case mhi_state_sys_err: + { + enum mhi_pm_state new_state; + + dev_dbg(dev, "system error detected "); + write_lock_irq(&mhi_cntrl->pm_lock); + new_state = mhi_tryset_pm_state(mhi_cntrl, + mhi_pm_sys_err_detect); + write_unlock_irq(&mhi_cntrl->pm_lock); + if (new_state == mhi_pm_sys_err_detect) + schedule_work(&mhi_cntrl->syserr_worker); + break; + } + default: + dev_err(dev, "invalid state: %s ", + to_mhi_state_str(new_state)); + } + + break; + } + case mhi_pkt_type_cmd_completion_event: + mhi_process_cmd_completion(mhi_cntrl, local_rp); + break; + case mhi_pkt_type_ee_event: + { + enum dev_st_transition st = dev_st_transition_max; + enum mhi_ee_type event = mhi_tre_get_ev_execenv(local_rp); + + dev_dbg(dev, "received ee event: %s ", + to_mhi_exec_str(event)); + switch (event) { + case mhi_ee_sbl: + st = dev_st_transition_sbl; + break; + case mhi_ee_wfw: + case mhi_ee_amss: + st = dev_st_transition_mission_mode; + break; + case mhi_ee_rddm: + mhi_cntrl->status_cb(mhi_cntrl, mhi_cb_ee_rddm); + write_lock_irq(&mhi_cntrl->pm_lock); + mhi_cntrl->ee = event; + write_unlock_irq(&mhi_cntrl->pm_lock); + wake_up_all(&mhi_cntrl->state_event); + break; + default: + dev_err(dev, + "unhandled ee event: 0x%x ", type); + } + if (st != dev_st_transition_max) + mhi_queue_state_transition(mhi_cntrl, st); + + break; + } + case mhi_pkt_type_tx_event: + chan = mhi_tre_get_ev_chid(local_rp); + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + break; + default: + dev_err(dev, "unhandled event type: %d ", type); + break; + } + + mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); + local_rp = ev_ring->rp; + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + count++; + } + + read_lock_bh(&mhi_cntrl->pm_lock); + if (likely(mhi_db_access_valid(mhi_cntrl))) + mhi_ring_er_db(mhi_event); + read_unlock_bh(&mhi_cntrl->pm_lock); + + return count; +} + +int mhi_process_data_event_ring(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, + u32 event_quota) +{ + struct mhi_tre *dev_rp, *local_rp; + struct mhi_ring *ev_ring = &mhi_event->ring; + struct mhi_event_ctxt *er_ctxt = + &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_event->er_index]; + int count = 0; + u32 chan; + struct mhi_chan *mhi_chan; + + if (unlikely(mhi_event_access_invalid(mhi_cntrl->pm_state))) + return -eio; + + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + local_rp = ev_ring->rp; + + while (dev_rp != local_rp && event_quota > 0) { + enum mhi_pkt_type type = mhi_tre_get_ev_type(local_rp); + + chan = mhi_tre_get_ev_chid(local_rp); + mhi_chan = &mhi_cntrl->mhi_chan[chan]; + + if (likely(type == mhi_pkt_type_tx_event)) { + parse_xfer_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } else if (type == mhi_pkt_type_rsc_tx_event) { + parse_rsc_event(mhi_cntrl, local_rp, mhi_chan); + event_quota--; + } + + mhi_recycle_ev_ring_element(mhi_cntrl, ev_ring); + local_rp = ev_ring->rp; + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + count++; + } + read_lock_bh(&mhi_cntrl->pm_lock); + if (likely(mhi_db_access_valid(mhi_cntrl))) + mhi_ring_er_db(mhi_event); + read_unlock_bh(&mhi_cntrl->pm_lock); + + return count; +} + +void mhi_ev_task(unsigned long data) +{ + struct mhi_event *mhi_event = (struct mhi_event *)data; + struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; + + /* process all pending events */ + spin_lock_bh(&mhi_event->lock); + mhi_event->process_event(mhi_cntrl, mhi_event, u32_max); + spin_unlock_bh(&mhi_event->lock); +} + +void mhi_ctrl_ev_task(unsigned long data) +{ + struct mhi_event *mhi_event = (struct mhi_event *)data; + struct mhi_controller *mhi_cntrl = mhi_event->mhi_cntrl; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + enum mhi_state state; + enum mhi_pm_state pm_state = 0; + int ret; + + /* + * we can check pm state w/o a lock here because there is no way + * pm state can change from reg access valid to no access while this + * thread being executed. + */ + if (!mhi_reg_access_valid(mhi_cntrl->pm_state)) { + /* + * we may have a pending event but not allowed to + * process it since we are probably in a suspended state, + * so trigger a resume. + */ + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + + return; + } + + /* process ctrl events events */ + ret = mhi_event->process_event(mhi_cntrl, mhi_event, u32_max); + + /* + * we received an irq but no events to process, maybe device went to + * sys_err state? check the state to confirm. + */ + if (!ret) { + write_lock_irq(&mhi_cntrl->pm_lock); + state = mhi_get_mhi_state(mhi_cntrl); + if (state == mhi_state_sys_err) { + dev_dbg(dev, "system error detected "); + pm_state = mhi_tryset_pm_state(mhi_cntrl, + mhi_pm_sys_err_detect); + } + write_unlock_irq(&mhi_cntrl->pm_lock); + if (pm_state == mhi_pm_sys_err_detect) + schedule_work(&mhi_cntrl->syserr_worker); + } +} diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h + * @mhi_cb_bw_req: received a bandwidth switch request from device + mhi_cb_bw_req, +/** + * struct mhi_link_info - bw requirement + * target_link_speed - link speed as defined by tls bits in linkcontrol reg + * target_link_width - link width as defined by nlw bits in linkstatus reg + */ +struct mhi_link_info { + unsigned int target_link_speed; + unsigned int target_link_width; +}; + + * @mhi_link_info: device bandwidth info + struct mhi_link_info mhi_link_info;
|
Modem Host Interface (MHI) Bus
|
1d3173a3bae7039b765a0956e3e4bf846dbaacb8
|
manivannan sadhasivam
|
include
|
linux
|
core, mhi
|
bus: mhi: core: add support for data transfer
|
add support for transferring data between external modem and host processor using mhi protocol.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 5
| 979
| 8
|
--- diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c +void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan) +{ + struct mhi_ring *buf_ring; + struct mhi_ring *tre_ring; + struct mhi_chan_ctxt *chan_ctxt; + + buf_ring = &mhi_chan->buf_ring; + tre_ring = &mhi_chan->tre_ring; + chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan]; + + mhi_free_coherent(mhi_cntrl, tre_ring->alloc_size, + tre_ring->pre_aligned, tre_ring->dma_handle); + vfree(buf_ring->base); + + buf_ring->base = tre_ring->base = null; + chan_ctxt->rbase = 0; +} + +int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan) +{ + struct mhi_ring *buf_ring; + struct mhi_ring *tre_ring; + struct mhi_chan_ctxt *chan_ctxt; + u32 tmp; + int ret; + + buf_ring = &mhi_chan->buf_ring; + tre_ring = &mhi_chan->tre_ring; + tre_ring->el_size = sizeof(struct mhi_tre); + tre_ring->len = tre_ring->el_size * tre_ring->elements; + chan_ctxt = &mhi_cntrl->mhi_ctxt->chan_ctxt[mhi_chan->chan]; + ret = mhi_alloc_aligned_ring(mhi_cntrl, tre_ring, tre_ring->len); + if (ret) + return -enomem; + + buf_ring->el_size = sizeof(struct mhi_buf_info); + buf_ring->len = buf_ring->el_size * buf_ring->elements; + buf_ring->base = vzalloc(buf_ring->len); + + if (!buf_ring->base) { + mhi_free_coherent(mhi_cntrl, tre_ring->alloc_size, + tre_ring->pre_aligned, tre_ring->dma_handle); + return -enomem; + } + + tmp = chan_ctxt->chcfg; + tmp &= ~chan_ctx_chstate_mask; + tmp |= (mhi_ch_state_enabled << chan_ctx_chstate_shift); + chan_ctxt->chcfg = tmp; + + chan_ctxt->rbase = tre_ring->iommu_base; + chan_ctxt->rp = chan_ctxt->wp = chan_ctxt->rbase; + chan_ctxt->rlen = tre_ring->len; + tre_ring->ctxt_wp = &chan_ctxt->wp; + + tre_ring->rp = tre_ring->wp = tre_ring->base; + buf_ring->rp = buf_ring->wp = buf_ring->base; + mhi_chan->db_cfg.db_mode = 1; + + /* update to all cores */ + smp_wmb(); + + return 0; +} + + if (mhi_cntrl->bounce_buf) { + mhi_cntrl->map_single = mhi_map_single_use_bb; + mhi_cntrl->unmap_single = mhi_unmap_single_use_bb; + } else { + mhi_cntrl->map_single = mhi_map_single_no_bb; + mhi_cntrl->unmap_single = mhi_unmap_single_no_bb; + } + + int ret; + + /* bring device out of lpm */ + ret = mhi_device_get_sync(mhi_dev); + if (ret) + return ret; + + ret = -einval; - return -einval; + goto exit_probe; - return -einval; + goto exit_probe; + if (ul_chan->auto_start) { + ret = mhi_prepare_channel(mhi_cntrl, ul_chan); + if (ret) + goto exit_probe; + } - return -einval; + goto exit_probe; - return -einval; + goto exit_probe; - return -einval; + goto exit_probe; - return mhi_drv->probe(mhi_dev, mhi_dev->id); + ret = mhi_drv->probe(mhi_dev, mhi_dev->id); + if (ret) + goto exit_probe; + + if (dl_chan && dl_chan->auto_start) + mhi_prepare_channel(mhi_cntrl, dl_chan); + + mhi_device_put(mhi_dev); + + return ret; + +exit_probe: + mhi_unprepare_from_transfer(mhi_dev); + + mhi_device_put(mhi_dev); + + return ret; + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + /* reset the non-offload channel */ + if (!mhi_chan->offload_ch) + mhi_reset_chan(mhi_cntrl, mhi_chan); + + if (ch_state[dir] == mhi_ch_state_enabled && + !mhi_chan->offload_ch) + mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); + + read_lock_bh(&mhi_cntrl->pm_lock); + while (mhi_dev->dev_wake) + mhi_device_put(mhi_dev); + read_unlock_bh(&mhi_cntrl->pm_lock); + diff --git a/drivers/bus/mhi/core/internal.h b/drivers/bus/mhi/core/internal.h --- a/drivers/bus/mhi/core/internal.h +++ b/drivers/bus/mhi/core/internal.h +int mhi_send_cmd(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, + enum mhi_cmd_type cmd); +int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan); +int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan); +void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan); +void mhi_reset_chan(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan); +int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, + void *buf, void *cb, size_t buf_len, enum mhi_flags flags); + +int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info); +int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info); +void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info); +void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info); + diff --git a/drivers/bus/mhi/core/main.c b/drivers/bus/mhi/core/main.c --- a/drivers/bus/mhi/core/main.c +++ b/drivers/bus/mhi/core/main.c +int mhi_map_single_no_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info) +{ + buf_info->p_addr = dma_map_single(mhi_cntrl->cntrl_dev, + buf_info->v_addr, buf_info->len, + buf_info->dir); + if (dma_mapping_error(mhi_cntrl->cntrl_dev, buf_info->p_addr)) + return -enomem; + + return 0; +} + +int mhi_map_single_use_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info) +{ + void *buf = mhi_alloc_coherent(mhi_cntrl, buf_info->len, + &buf_info->p_addr, gfp_atomic); + + if (!buf) + return -enomem; + + if (buf_info->dir == dma_to_device) + memcpy(buf, buf_info->v_addr, buf_info->len); + + buf_info->bb_addr = buf; + + return 0; +} + +void mhi_unmap_single_no_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info) +{ + dma_unmap_single(mhi_cntrl->cntrl_dev, buf_info->p_addr, buf_info->len, + buf_info->dir); +} + +void mhi_unmap_single_use_bb(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf_info) +{ + if (buf_info->dir == dma_from_device) + memcpy(buf_info->v_addr, buf_info->bb_addr, buf_info->len); + + mhi_free_coherent(mhi_cntrl, buf_info->len, buf_info->bb_addr, + buf_info->p_addr); +} + +static int get_nr_avail_ring_elements(struct mhi_controller *mhi_cntrl, + struct mhi_ring *ring) +{ + int nr_el; + + if (ring->wp < ring->rp) { + nr_el = ((ring->rp - ring->wp) / ring->el_size) - 1; + } else { + nr_el = (ring->rp - ring->base) / ring->el_size; + nr_el += ((ring->base + ring->len - ring->wp) / + ring->el_size) - 1; + } + + return nr_el; +} + +static void mhi_add_ring_element(struct mhi_controller *mhi_cntrl, + struct mhi_ring *ring) +{ + ring->wp += ring->el_size; + if (ring->wp >= (ring->base + ring->len)) + ring->wp = ring->base; + /* smp update */ + smp_wmb(); +} + - /* device rp after servicing the tres */ - /* local rp */ + /* unmap if it's not pre-mapped by client */ + if (likely(!buf_info->pre_mapped)) + mhi_cntrl->unmap_single(mhi_cntrl, buf_info); + + + /* + * recycle the buffer if buffer is pre-allocated, + * if there is an error, not much we can do apart + * from dropping the packet + */ + if (mhi_chan->pre_alloc) { + if (mhi_queue_buf(mhi_chan->mhi_dev, + mhi_chan->dir, + buf_info->cb_buf, + buf_info->len, mhi_eot)) { + dev_err(dev, + "error recycling buffer for chan:%d ", + mhi_chan->chan); + kfree(buf_info->cb_buf); + } + } + +static bool mhi_is_ring_full(struct mhi_controller *mhi_cntrl, + struct mhi_ring *ring) +{ + void *tmp = ring->wp + ring->el_size; + + if (tmp >= (ring->base + ring->len)) + tmp = ring->base; + + return (tmp == ring->rp); +} + +int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, + struct sk_buff *skb, size_t len, enum mhi_flags mflags) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct mhi_chan *mhi_chan = (dir == dma_to_device) ? mhi_dev->ul_chan : + mhi_dev->dl_chan; + struct mhi_ring *tre_ring = &mhi_chan->tre_ring; + struct mhi_ring *buf_ring = &mhi_chan->buf_ring; + struct mhi_buf_info *buf_info; + struct mhi_tre *mhi_tre; + int ret; + + /* if mhi host pre-allocates buffers then client drivers cannot queue */ + if (mhi_chan->pre_alloc) + return -einval; + + if (mhi_is_ring_full(mhi_cntrl, tre_ring)) + return -enomem; + + read_lock_bh(&mhi_cntrl->pm_lock); + if (unlikely(mhi_pm_in_error_state(mhi_cntrl->pm_state))) { + read_unlock_bh(&mhi_cntrl->pm_lock); + return -eio; + } + + /* we're in m3 or transitioning to m3 */ + if (mhi_pm_in_suspend_state(mhi_cntrl->pm_state)) { + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + } + + /* toggle wake to exit out of m2 */ + mhi_cntrl->wake_toggle(mhi_cntrl); + + /* generate the tre */ + buf_info = buf_ring->wp; + + buf_info->v_addr = skb->data; + buf_info->cb_buf = skb; + buf_info->wp = tre_ring->wp; + buf_info->dir = mhi_chan->dir; + buf_info->len = len; + ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); + if (ret) + goto map_error; + + mhi_tre = tre_ring->wp; + + mhi_tre->ptr = mhi_tre_data_ptr(buf_info->p_addr); + mhi_tre->dword[0] = mhi_tre_data_dword0(buf_info->len); + mhi_tre->dword[1] = mhi_tre_data_dword1(1, 1, 0, 0); + + /* increment wp */ + mhi_add_ring_element(mhi_cntrl, tre_ring); + mhi_add_ring_element(mhi_cntrl, buf_ring); + + if (mhi_chan->dir == dma_to_device) + atomic_inc(&mhi_cntrl->pending_pkts); + + if (likely(mhi_db_access_valid(mhi_cntrl))) { + read_lock_bh(&mhi_chan->lock); + mhi_ring_chan_db(mhi_cntrl, mhi_chan); + read_unlock_bh(&mhi_chan->lock); + } + + read_unlock_bh(&mhi_cntrl->pm_lock); + + return 0; + +map_error: + read_unlock_bh(&mhi_cntrl->pm_lock); + + return ret; +} +export_symbol_gpl(mhi_queue_skb); + +int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, + struct mhi_buf *mhi_buf, size_t len, enum mhi_flags mflags) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct mhi_chan *mhi_chan = (dir == dma_to_device) ? mhi_dev->ul_chan : + mhi_dev->dl_chan; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + struct mhi_ring *tre_ring = &mhi_chan->tre_ring; + struct mhi_ring *buf_ring = &mhi_chan->buf_ring; + struct mhi_buf_info *buf_info; + struct mhi_tre *mhi_tre; + + /* if mhi host pre-allocates buffers then client drivers cannot queue */ + if (mhi_chan->pre_alloc) + return -einval; + + if (mhi_is_ring_full(mhi_cntrl, tre_ring)) + return -enomem; + + read_lock_bh(&mhi_cntrl->pm_lock); + if (unlikely(mhi_pm_in_error_state(mhi_cntrl->pm_state))) { + dev_err(dev, "mhi is not in activate state, pm state: %s ", + to_mhi_pm_state_str(mhi_cntrl->pm_state)); + read_unlock_bh(&mhi_cntrl->pm_lock); + + return -eio; + } + + /* we're in m3 or transitioning to m3 */ + if (mhi_pm_in_suspend_state(mhi_cntrl->pm_state)) { + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + } + + /* toggle wake to exit out of m2 */ + mhi_cntrl->wake_toggle(mhi_cntrl); + + /* generate the tre */ + buf_info = buf_ring->wp; + warn_on(buf_info->used); + buf_info->p_addr = mhi_buf->dma_addr; + buf_info->pre_mapped = true; + buf_info->cb_buf = mhi_buf; + buf_info->wp = tre_ring->wp; + buf_info->dir = mhi_chan->dir; + buf_info->len = len; + + mhi_tre = tre_ring->wp; + + mhi_tre->ptr = mhi_tre_data_ptr(buf_info->p_addr); + mhi_tre->dword[0] = mhi_tre_data_dword0(buf_info->len); + mhi_tre->dword[1] = mhi_tre_data_dword1(1, 1, 0, 0); + + /* increment wp */ + mhi_add_ring_element(mhi_cntrl, tre_ring); + mhi_add_ring_element(mhi_cntrl, buf_ring); + + if (mhi_chan->dir == dma_to_device) + atomic_inc(&mhi_cntrl->pending_pkts); + + if (likely(mhi_db_access_valid(mhi_cntrl))) { + read_lock_bh(&mhi_chan->lock); + mhi_ring_chan_db(mhi_cntrl, mhi_chan); + read_unlock_bh(&mhi_chan->lock); + } + + read_unlock_bh(&mhi_cntrl->pm_lock); + + return 0; +} +export_symbol_gpl(mhi_queue_dma); + +int mhi_gen_tre(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan, + void *buf, void *cb, size_t buf_len, enum mhi_flags flags) +{ + struct mhi_ring *buf_ring, *tre_ring; + struct mhi_tre *mhi_tre; + struct mhi_buf_info *buf_info; + int eot, eob, chain, bei; + int ret; + + buf_ring = &mhi_chan->buf_ring; + tre_ring = &mhi_chan->tre_ring; + + buf_info = buf_ring->wp; + buf_info->v_addr = buf; + buf_info->cb_buf = cb; + buf_info->wp = tre_ring->wp; + buf_info->dir = mhi_chan->dir; + buf_info->len = buf_len; + + ret = mhi_cntrl->map_single(mhi_cntrl, buf_info); + if (ret) + return ret; + + eob = !!(flags & mhi_eob); + eot = !!(flags & mhi_eot); + chain = !!(flags & mhi_chain); + bei = !!(mhi_chan->intmod); + + mhi_tre = tre_ring->wp; + mhi_tre->ptr = mhi_tre_data_ptr(buf_info->p_addr); + mhi_tre->dword[0] = mhi_tre_data_dword0(buf_len); + mhi_tre->dword[1] = mhi_tre_data_dword1(bei, eot, eob, chain); + + /* increment wp */ + mhi_add_ring_element(mhi_cntrl, tre_ring); + mhi_add_ring_element(mhi_cntrl, buf_ring); + + return 0; +} + +int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, + void *buf, size_t len, enum mhi_flags mflags) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct mhi_chan *mhi_chan = (dir == dma_to_device) ? mhi_dev->ul_chan : + mhi_dev->dl_chan; + struct mhi_ring *tre_ring; + unsigned long flags; + int ret; + + /* + * this check here only as a guard, it's always + * possible mhi can enter error while executing rest of function, + * which is not fatal so we do not need to hold pm_lock + */ + if (unlikely(mhi_pm_in_error_state(mhi_cntrl->pm_state))) + return -eio; + + tre_ring = &mhi_chan->tre_ring; + if (mhi_is_ring_full(mhi_cntrl, tre_ring)) + return -enomem; + + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf, buf, len, mflags); + if (unlikely(ret)) + return ret; + + read_lock_irqsave(&mhi_cntrl->pm_lock, flags); + + /* we're in m3 or transitioning to m3 */ + if (mhi_pm_in_suspend_state(mhi_cntrl->pm_state)) { + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + } + + /* toggle wake to exit out of m2 */ + mhi_cntrl->wake_toggle(mhi_cntrl); + + if (mhi_chan->dir == dma_to_device) + atomic_inc(&mhi_cntrl->pending_pkts); + + if (likely(mhi_db_access_valid(mhi_cntrl))) { + unsigned long flags; + + read_lock_irqsave(&mhi_chan->lock, flags); + mhi_ring_chan_db(mhi_cntrl, mhi_chan); + read_unlock_irqrestore(&mhi_chan->lock, flags); + } + + read_unlock_irqrestore(&mhi_cntrl->pm_lock, flags); + + return 0; +} +export_symbol_gpl(mhi_queue_buf); + +int mhi_send_cmd(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan, + enum mhi_cmd_type cmd) +{ + struct mhi_tre *cmd_tre = null; + struct mhi_cmd *mhi_cmd = &mhi_cntrl->mhi_cmd[primary_cmd_ring]; + struct mhi_ring *ring = &mhi_cmd->ring; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + int chan = 0; + + if (mhi_chan) + chan = mhi_chan->chan; + + spin_lock_bh(&mhi_cmd->lock); + if (!get_nr_avail_ring_elements(mhi_cntrl, ring)) { + spin_unlock_bh(&mhi_cmd->lock); + return -enomem; + } + + /* prepare the cmd tre */ + cmd_tre = ring->wp; + switch (cmd) { + case mhi_cmd_reset_chan: + cmd_tre->ptr = mhi_tre_cmd_reset_ptr; + cmd_tre->dword[0] = mhi_tre_cmd_reset_dword0; + cmd_tre->dword[1] = mhi_tre_cmd_reset_dword1(chan); + break; + case mhi_cmd_start_chan: + cmd_tre->ptr = mhi_tre_cmd_start_ptr; + cmd_tre->dword[0] = mhi_tre_cmd_start_dword0; + cmd_tre->dword[1] = mhi_tre_cmd_start_dword1(chan); + break; + default: + dev_err(dev, "command not supported "); + break; + } + + /* queue to hardware */ + mhi_add_ring_element(mhi_cntrl, ring); + read_lock_bh(&mhi_cntrl->pm_lock); + if (likely(mhi_db_access_valid(mhi_cntrl))) + mhi_ring_cmd_db(mhi_cntrl, mhi_cmd); + read_unlock_bh(&mhi_cntrl->pm_lock); + spin_unlock_bh(&mhi_cmd->lock); + + return 0; +} + +static void __mhi_unprepare_channel(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan) +{ + int ret; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + dev_dbg(dev, "entered: unprepare channel:%d ", mhi_chan->chan); + + /* no more processing events for this channel */ + mutex_lock(&mhi_chan->mutex); + write_lock_irq(&mhi_chan->lock); + if (mhi_chan->ch_state != mhi_ch_state_enabled) { + write_unlock_irq(&mhi_chan->lock); + mutex_unlock(&mhi_chan->mutex); + return; + } + + mhi_chan->ch_state = mhi_ch_state_disabled; + write_unlock_irq(&mhi_chan->lock); + + reinit_completion(&mhi_chan->completion); + read_lock_bh(&mhi_cntrl->pm_lock); + if (mhi_pm_in_error_state(mhi_cntrl->pm_state)) { + read_unlock_bh(&mhi_cntrl->pm_lock); + goto error_invalid_state; + } + + mhi_cntrl->wake_toggle(mhi_cntrl); + read_unlock_bh(&mhi_cntrl->pm_lock); + + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + ret = mhi_send_cmd(mhi_cntrl, mhi_chan, mhi_cmd_reset_chan); + if (ret) + goto error_invalid_state; + + /* even if it fails we will still reset */ + ret = wait_for_completion_timeout(&mhi_chan->completion, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (!ret || mhi_chan->ccs != mhi_ev_cc_success) + dev_err(dev, + "failed to receive cmd completion, still resetting "); + +error_invalid_state: + if (!mhi_chan->offload_ch) { + mhi_reset_chan(mhi_cntrl, mhi_chan); + mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); + } + dev_dbg(dev, "chan:%d successfully resetted ", mhi_chan->chan); + mutex_unlock(&mhi_chan->mutex); +} + +int mhi_prepare_channel(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan) +{ + int ret = 0; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + + dev_dbg(dev, "preparing channel: %d ", mhi_chan->chan); + + if (!(bit(mhi_cntrl->ee) & mhi_chan->ee_mask)) { + dev_err(dev, + "current ee: %s required ee mask: 0x%x for chan: %s ", + to_mhi_exec_str(mhi_cntrl->ee), mhi_chan->ee_mask, + mhi_chan->name); + return -enotconn; + } + + mutex_lock(&mhi_chan->mutex); + + /* if channel is not in disable state, do not allow it to start */ + if (mhi_chan->ch_state != mhi_ch_state_disabled) { + ret = -eio; + dev_dbg(dev, "channel: %d is not in disabled state ", + mhi_chan->chan); + goto error_init_chan; + } + + /* check of client manages channel context for offload channels */ + if (!mhi_chan->offload_ch) { + ret = mhi_init_chan_ctxt(mhi_cntrl, mhi_chan); + if (ret) + goto error_init_chan; + } + + reinit_completion(&mhi_chan->completion); + read_lock_bh(&mhi_cntrl->pm_lock); + if (mhi_pm_in_error_state(mhi_cntrl->pm_state)) { + read_unlock_bh(&mhi_cntrl->pm_lock); + ret = -eio; + goto error_pm_state; + } + + mhi_cntrl->wake_toggle(mhi_cntrl); + read_unlock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + + ret = mhi_send_cmd(mhi_cntrl, mhi_chan, mhi_cmd_start_chan); + if (ret) + goto error_pm_state; + + ret = wait_for_completion_timeout(&mhi_chan->completion, + msecs_to_jiffies(mhi_cntrl->timeout_ms)); + if (!ret || mhi_chan->ccs != mhi_ev_cc_success) { + ret = -eio; + goto error_pm_state; + } + + write_lock_irq(&mhi_chan->lock); + mhi_chan->ch_state = mhi_ch_state_enabled; + write_unlock_irq(&mhi_chan->lock); + + /* pre-allocate buffer for xfer ring */ + if (mhi_chan->pre_alloc) { + int nr_el = get_nr_avail_ring_elements(mhi_cntrl, + &mhi_chan->tre_ring); + size_t len = mhi_cntrl->buffer_len; + + while (nr_el--) { + void *buf; + + buf = kmalloc(len, gfp_kernel); + if (!buf) { + ret = -enomem; + goto error_pre_alloc; + } + + /* prepare transfer descriptors */ + ret = mhi_gen_tre(mhi_cntrl, mhi_chan, buf, buf, + len, mhi_eot); + if (ret) { + kfree(buf); + goto error_pre_alloc; + } + } + + read_lock_bh(&mhi_cntrl->pm_lock); + if (mhi_db_access_valid(mhi_cntrl)) { + read_lock_irq(&mhi_chan->lock); + mhi_ring_chan_db(mhi_cntrl, mhi_chan); + read_unlock_irq(&mhi_chan->lock); + } + read_unlock_bh(&mhi_cntrl->pm_lock); + } + + mutex_unlock(&mhi_chan->mutex); + + dev_dbg(dev, "chan: %d successfully moved to start state ", + mhi_chan->chan); + + return 0; + +error_pm_state: + if (!mhi_chan->offload_ch) + mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan); + +error_init_chan: + mutex_unlock(&mhi_chan->mutex); + + return ret; + +error_pre_alloc: + mutex_unlock(&mhi_chan->mutex); + __mhi_unprepare_channel(mhi_cntrl, mhi_chan); + + return ret; +} + +static void mhi_mark_stale_events(struct mhi_controller *mhi_cntrl, + struct mhi_event *mhi_event, + struct mhi_event_ctxt *er_ctxt, + int chan) + +{ + struct mhi_tre *dev_rp, *local_rp; + struct mhi_ring *ev_ring; + struct device *dev = &mhi_cntrl->mhi_dev->dev; + unsigned long flags; + + dev_dbg(dev, "marking all events for chan: %d as stale ", chan); + + ev_ring = &mhi_event->ring; + + /* mark all stale events related to channel as stale event */ + spin_lock_irqsave(&mhi_event->lock, flags); + dev_rp = mhi_to_virtual(ev_ring, er_ctxt->rp); + + local_rp = ev_ring->rp; + while (dev_rp != local_rp) { + if (mhi_tre_get_ev_type(local_rp) == mhi_pkt_type_tx_event && + chan == mhi_tre_get_ev_chid(local_rp)) + local_rp->dword[1] = mhi_tre_ev_dword1(chan, + mhi_pkt_type_stale_event); + local_rp++; + if (local_rp == (ev_ring->base + ev_ring->len)) + local_rp = ev_ring->base; + } + + dev_dbg(dev, "finished marking events as stale events "); + spin_unlock_irqrestore(&mhi_event->lock, flags); +} + +static void mhi_reset_data_chan(struct mhi_controller *mhi_cntrl, + struct mhi_chan *mhi_chan) +{ + struct mhi_ring *buf_ring, *tre_ring; + struct mhi_result result; + + /* reset any pending buffers */ + buf_ring = &mhi_chan->buf_ring; + tre_ring = &mhi_chan->tre_ring; + result.transaction_status = -enotconn; + result.bytes_xferd = 0; + while (tre_ring->rp != tre_ring->wp) { + struct mhi_buf_info *buf_info = buf_ring->rp; + + if (mhi_chan->dir == dma_to_device) + atomic_dec(&mhi_cntrl->pending_pkts); + + if (!buf_info->pre_mapped) + mhi_cntrl->unmap_single(mhi_cntrl, buf_info); + + mhi_del_ring_element(mhi_cntrl, buf_ring); + mhi_del_ring_element(mhi_cntrl, tre_ring); + + if (mhi_chan->pre_alloc) { + kfree(buf_info->cb_buf); + } else { + result.buf_addr = buf_info->cb_buf; + mhi_chan->xfer_cb(mhi_chan->mhi_dev, &result); + } + } +} + +void mhi_reset_chan(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan) +{ + struct mhi_event *mhi_event; + struct mhi_event_ctxt *er_ctxt; + int chan = mhi_chan->chan; + + /* nothing to reset, client doesn't queue buffers */ + if (mhi_chan->offload_ch) + return; + + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; + er_ctxt = &mhi_cntrl->mhi_ctxt->er_ctxt[mhi_chan->er_index]; + + mhi_mark_stale_events(mhi_cntrl, mhi_event, er_ctxt, chan); + + mhi_reset_data_chan(mhi_cntrl, mhi_chan); + + read_unlock_bh(&mhi_cntrl->pm_lock); +} + +/* move channel to start state */ +int mhi_prepare_for_transfer(struct mhi_device *mhi_dev) +{ + int ret, dir; + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct mhi_chan *mhi_chan; + + for (dir = 0; dir < 2; dir++) { + mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; + if (!mhi_chan) + continue; + + ret = mhi_prepare_channel(mhi_cntrl, mhi_chan); + if (ret) + goto error_open_chan; + } + + return 0; + +error_open_chan: + for (--dir; dir >= 0; dir--) { + mhi_chan = dir ? mhi_dev->dl_chan : mhi_dev->ul_chan; + if (!mhi_chan) + continue; + + __mhi_unprepare_channel(mhi_cntrl, mhi_chan); + } + + return ret; +} +export_symbol_gpl(mhi_prepare_for_transfer); + +void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct mhi_chan *mhi_chan; + int dir; + + for (dir = 0; dir < 2; dir++) { + mhi_chan = dir ? mhi_dev->ul_chan : mhi_dev->dl_chan; + if (!mhi_chan) + continue; + + __mhi_unprepare_channel(mhi_cntrl, mhi_chan); + } +} +export_symbol_gpl(mhi_unprepare_from_transfer); + +int mhi_poll(struct mhi_device *mhi_dev, u32 budget) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + struct mhi_chan *mhi_chan = mhi_dev->dl_chan; + struct mhi_event *mhi_event = &mhi_cntrl->mhi_event[mhi_chan->er_index]; + int ret; + + spin_lock_bh(&mhi_event->lock); + ret = mhi_event->process_event(mhi_cntrl, mhi_event, budget); + spin_unlock_bh(&mhi_event->lock); + + return ret; +} +export_symbol_gpl(mhi_poll); diff --git a/drivers/bus/mhi/core/pm.c b/drivers/bus/mhi/core/pm.c --- a/drivers/bus/mhi/core/pm.c +++ b/drivers/bus/mhi/core/pm.c + +void mhi_device_get(struct mhi_device *mhi_dev) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + + mhi_dev->dev_wake++; + read_lock_bh(&mhi_cntrl->pm_lock); + mhi_cntrl->wake_get(mhi_cntrl, true); + read_unlock_bh(&mhi_cntrl->pm_lock); +} +export_symbol_gpl(mhi_device_get); + +int mhi_device_get_sync(struct mhi_device *mhi_dev) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + int ret; + + ret = __mhi_device_get_sync(mhi_cntrl); + if (!ret) + mhi_dev->dev_wake++; + + return ret; +} +export_symbol_gpl(mhi_device_get_sync); + +void mhi_device_put(struct mhi_device *mhi_dev) +{ + struct mhi_controller *mhi_cntrl = mhi_dev->mhi_cntrl; + + mhi_dev->dev_wake--; + read_lock_bh(&mhi_cntrl->pm_lock); + if (mhi_pm_in_suspend_state(mhi_cntrl->pm_state)) { + mhi_cntrl->runtime_get(mhi_cntrl); + mhi_cntrl->runtime_put(mhi_cntrl); + } + + mhi_cntrl->wake_put(mhi_cntrl, false); + read_unlock_bh(&mhi_cntrl->pm_lock); +} +export_symbol_gpl(mhi_device_put); diff --git a/include/linux/mhi.h b/include/linux/mhi.h --- a/include/linux/mhi.h +++ b/include/linux/mhi.h +#include <linux/skbuff.h> + * @map_single: cb function to create tre buffer + * @unmap_single: cb function to destroy tre buffer + int (*map_single)(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf); + void (*unmap_single)(struct mhi_controller *mhi_cntrl, + struct mhi_buf_info *buf); +/** + * mhi_device_get - disable device low power mode + * @mhi_dev: device associated with the channel + */ +void mhi_device_get(struct mhi_device *mhi_dev); + +/** + * mhi_device_get_sync - disable device low power mode. synchronously + * take the controller out of suspended state + * @mhi_dev: device associated with the channel + */ +int mhi_device_get_sync(struct mhi_device *mhi_dev); + +/** + * mhi_device_put - re-enable device low power mode + * @mhi_dev: device associated with the channel + */ +void mhi_device_put(struct mhi_device *mhi_dev); + +/** + * mhi_prepare_for_transfer - setup channel for data transfer + * @mhi_dev: device associated with the channels + */ +int mhi_prepare_for_transfer(struct mhi_device *mhi_dev); + +/** + * mhi_unprepare_from_transfer - unprepare the channels + * @mhi_dev: device associated with the channels + */ +void mhi_unprepare_from_transfer(struct mhi_device *mhi_dev); + +/** + * mhi_poll - poll for any available data in dl direction + * @mhi_dev: device associated with the channels + * @budget: # of events to process + */ +int mhi_poll(struct mhi_device *mhi_dev, u32 budget); + +/** + * mhi_queue_dma - send or receive dma mapped buffers from client device + * over mhi channel + * @mhi_dev: device associated with the channels + * @dir: dma direction for the channel + * @mhi_buf: buffer for holding the dma mapped data + * @len: buffer length + * @mflags: mhi transfer flags used for the transfer + */ +int mhi_queue_dma(struct mhi_device *mhi_dev, enum dma_data_direction dir, + struct mhi_buf *mhi_buf, size_t len, enum mhi_flags mflags); + +/** + * mhi_queue_buf - send or receive raw buffers from client device over mhi + * channel + * @mhi_dev: device associated with the channels + * @dir: dma direction for the channel + * @buf: buffer for holding the data + * @len: buffer length + * @mflags: mhi transfer flags used for the transfer + */ +int mhi_queue_buf(struct mhi_device *mhi_dev, enum dma_data_direction dir, + void *buf, size_t len, enum mhi_flags mflags); + +/** + * mhi_queue_skb - send or receive skbs from client device over mhi channel + * @mhi_dev: device associated with the channels + * @dir: dma direction for the channel + * @skb: buffer for holding skbs + * @len: buffer length + * @mflags: mhi transfer flags used for the transfer + */ +int mhi_queue_skb(struct mhi_device *mhi_dev, enum dma_data_direction dir, + struct sk_buff *skb, size_t len, enum mhi_flags mflags); +
|
Modem Host Interface (MHI) Bus
|
189ff97cca53e3fe2d8b38d64105040ce17fc62d
|
manivannan sadhasivam
|
include
|
linux
|
core, mhi
|
bus: mhi: core: add uevent support for module autoloading
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add uevent support to mhi bus so that the client drivers can be autoloaded by udev when the mhi devices gets created. the client drivers are expected to provide module_device_table with the mhi id_table struct so that the alias can be exported.
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this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
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add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['h', 'c']
| 4
| 23
| 0
|
--- diff --git a/drivers/bus/mhi/core/init.c b/drivers/bus/mhi/core/init.c --- a/drivers/bus/mhi/core/init.c +++ b/drivers/bus/mhi/core/init.c +static int mhi_uevent(struct device *dev, struct kobj_uevent_env *env) +{ + struct mhi_device *mhi_dev = to_mhi_device(dev); + + return add_uevent_var(env, "modalias=" mhi_device_modalias_fmt, + mhi_dev->chan_name); +} + + .uevent = mhi_uevent, diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h +#define mhi_device_modalias_fmt "mhi:%s" diff --git a/scripts/mod/devicetable-offsets.c b/scripts/mod/devicetable-offsets.c --- a/scripts/mod/devicetable-offsets.c +++ b/scripts/mod/devicetable-offsets.c + devid(mhi_device_id); + devid_field(mhi_device_id, chan); + diff --git a/scripts/mod/file2alias.c b/scripts/mod/file2alias.c --- a/scripts/mod/file2alias.c +++ b/scripts/mod/file2alias.c +/* looks like: mhi:s */ +static int do_mhi_entry(const char *filename, void *symval, char *alias) +{ + def_field_addr(symval, mhi_device_id, chan); + sprintf(alias, mhi_device_modalias_fmt, *chan); + + return 1; +} + + {"mhi", size_mhi_device_id, do_mhi_entry},
|
Modem Host Interface (MHI) Bus
|
e6b0de469c5babfe29a86be289408ba2070ea44a
|
manivannan sadhasivam jeffrey hugo jhugo codeaurora org jeffrey hugo jhugo codeaurora org
|
scripts
|
mod
|
core, mhi
|
maintainers: add entry for mhi bus
|
add maintainers entry for mhi bus.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add the mhi (modem host interface) bus interface to linux kernel. mhi is a communication protocol used by the host processors to control and communicate with modems over a high speed peripheral bus or shared memory. the mhi protocol has been designed and developed by qualcomm innovation center, inc., for use in their modems
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
[]
|
['maintainers']
| 1
| 10
| 0
|
--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +mhi bus +m: manivannan sadhasivam <manivannan.sadhasivam@linaro.org> +m: hemant kumar <hemantk@codeaurora.org> +l: linux-arm-msm@vger.kernel.org +s: maintained +t: git git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi.git +f: documentation/mhi/ +f: drivers/bus/mhi/ +f: include/linux/mhi.h +
|
Modem Host Interface (MHI) Bus
|
8f522bae2394d8f61a9e29d8d5d97553402b7c53
|
manivannan sadhasivam
| |||
bus: ti-sysc: add support for pruss sysc type
|
the pru-icss present on am33xx/am43xx/am57xx has a very unique syscfg register. the register follows the omap4-style sysc_type3 for master standby and slave idle, but also has two additional unique fields - standby_init and sub_mwait. the standby_init is a control bit that is used to initiate a standby sequence (when set) and trigger a mstandby request to the soc's prcm module. this same bit is also used to enable the ocp master ports (when cleared) to allow the pru cores to access any peripherals or memory beyond the pru subsystem. the sub_mwait is a ready status field for the external access.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
add support for pruss sysc type
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['bus', 'ti-sysc']
|
['h', 'c']
| 2
| 29
| 0
|
--- diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c + /* pruss on am3, am4 and am5 */ + sysc_quirk("pruss", 0, 0x26000, 0x26004, -enodev, 0x47000000, 0xff000000, + sysc_module_quirk_pruss), +/* pruss needs to set mstandby_init inorder to idle properly */ +static void sysc_module_disable_quirk_pruss(struct sysc *ddata) +{ + u32 reg; + + reg = sysc_read(ddata, ddata->offsets[sysc_sysconfig]); + reg |= sysc_pruss_standby_init; + sysc_write(ddata, ddata->offsets[sysc_sysconfig], reg); +} + + + if (ddata->cfg.quirks & sysc_module_quirk_pruss) + ddata->module_disable_quirk = sysc_module_disable_quirk_pruss; +/* + * pruss found on some am33xx, am437x and am57xx socs + */ +static const struct sysc_capabilities sysc_pruss = { + .type = ti_sysc_pruss, + .sysc_mask = sysc_pruss_standby_init | sysc_pruss_sub_mwait, + .regbits = &sysc_regbits_omap4_simple, + .mod_quirks = sysc_module_quirk_pruss, +}; + + { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, }, diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h --- a/include/linux/platform_data/ti-sysc.h +++ b/include/linux/platform_data/ti-sysc.h + ti_sysc_pruss, +#define sysc_module_quirk_pruss bit(24)
|
Various
|
b2745d92bb015cc4454d4195c4ce6e2852db397e
|
suman anna
|
drivers
|
bus
|
platform_data
|
counter: 104-quad-8: support differential encoder cable status
|
the acces 104-quad-8 series provides status information about the connection state of the differential encoder cable inputs. this patch implements support to expose such information from these devices.
|
this release adds: support for the notion of thermal pressure, which lets the task scheduler to take better scheduling decisions in the face of cpu frequency changes; support for frequency invariant scheduler accounting on x86 cpus, which makes x86 perform better with the schedutil governor; a new and better exfat file system implementation; support for a x86 feature that allows to detect atomic operations that span cache lines; arm pointer authentication support for kernel code, which helps to prevent security issues; support for spawning processes with clone3() into cgroups; write protection support in userfaultfd(), which is equivalent to (but faster than) using mprotect(2) and a sigsegv signal handler; and a bpf-based linux security module which allows for more dynamic security auditing. as always, there are many other new drivers and improvements.
|
support differential encoder cable status
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'cryptography', 'virtualization', 'security', 'networking', 'architectures arm x86 risc-v s390 powerpc c-sky mips arc']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'input devices: tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'clock', 'phy ("physical layer" framework)', 'edac (error detection and correction)', 'modem host interface (mhi) bus', 'various']
|
['counter', '104-quad-8']
|
['sysfs-bus-counter-104-quad-8', 'c']
| 2
| 93
| 0
|
--- diff --git a/documentation/abi/testing/sysfs-bus-counter-104-quad-8 b/documentation/abi/testing/sysfs-bus-counter-104-quad-8 --- a/documentation/abi/testing/sysfs-bus-counter-104-quad-8 +++ b/documentation/abi/testing/sysfs-bus-counter-104-quad-8 +what: /sys/bus/counter/devices/counterx/signaly/cable_fault +kernelversion: 5.7 +contact: linux-iio@vger.kernel.org +description: + read-only attribute that indicates whether a differential + encoder cable fault (not connected or loose wires) is detected + for the respective channel of signal y. valid attribute values + are boolean. detection must first be enabled via the + corresponding cable_fault_enable attribute. + +what: /sys/bus/counter/devices/counterx/signaly/cable_fault_enable +kernelversion: 5.7 +contact: linux-iio@vger.kernel.org +description: + whether detection of differential encoder cable faults for the + respective channel of signal y is enabled. valid attribute + values are boolean. + diff --git a/drivers/counter/104-quad-8.c b/drivers/counter/104-quad-8.c --- a/drivers/counter/104-quad-8.c +++ b/drivers/counter/104-quad-8.c + * @fck_prescaler: array of filter clock prescaler configurations + * @cable_fault_enable: differential encoder cable status enable configurations + unsigned int cable_fault_enable; +#define quad8_diff_encoder_cable_status 0x17 +static ssize_t quad8_signal_cable_fault_read(struct counter_device *counter, + struct counter_signal *signal, + void *private, char *buf) +{ + const struct quad8_iio *const priv = counter->priv; + const size_t channel_id = signal->id / 2; + const bool disabled = !(priv->cable_fault_enable & bit(channel_id)); + unsigned int status; + unsigned int fault; + + if (disabled) + return -einval; + + /* logic 0 = cable fault */ + status = inb(priv->base + quad8_diff_encoder_cable_status); + + /* mask respective channel and invert logic */ + fault = !(status & bit(channel_id)); + + return sprintf(buf, "%u ", fault); +} + +static ssize_t quad8_signal_cable_fault_enable_read( + struct counter_device *counter, struct counter_signal *signal, + void *private, char *buf) +{ + const struct quad8_iio *const priv = counter->priv; + const size_t channel_id = signal->id / 2; + const unsigned int enb = !!(priv->cable_fault_enable & bit(channel_id)); + + return sprintf(buf, "%u ", enb); +} + +static ssize_t quad8_signal_cable_fault_enable_write( + struct counter_device *counter, struct counter_signal *signal, + void *private, const char *buf, size_t len) +{ + struct quad8_iio *const priv = counter->priv; + const size_t channel_id = signal->id / 2; + bool enable; + int ret; + unsigned int cable_fault_enable; + + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + if (enable) + priv->cable_fault_enable |= bit(channel_id); + else + priv->cable_fault_enable &= ~bit(channel_id); + + /* enable is active low in differential encoder cable status register */ + cable_fault_enable = ~priv->cable_fault_enable; + + outb(cable_fault_enable, priv->base + quad8_diff_encoder_cable_status); + + return len; +} + + { + .name = "cable_fault", + .read = quad8_signal_cable_fault_read + }, + { + .name = "cable_fault_enable", + .read = quad8_signal_cable_fault_enable_read, + .write = quad8_signal_cable_fault_enable_write + }, + /* disable differential encoder cable status for all channels */ + outb(0xff, base[id] + quad8_diff_encoder_cable_status);
|
Various
|
954ab5cc5f3e0bc764df81a13f065936a85e2084
|
william breathitt gray
|
documentation
|
abi
|
testing
|
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