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net: mvpp2: add ppv23 rx fifo flow control
|
new fifo flow control feature was added in ppv23. ppv2 fifo polled by hw and trigger pause frame if fifo fill level is below threshold. fifo hw flow control enabled with cm3 rxq&bm flow control with ethtool. current fifo thresholds is: 9kb for port with maximum speed 10gb/s port 4kb for port with maximum speed 5gb/s port 2kb for port with maximum speed 1gb/s port
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tx flow control support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mvpp2 ']
|
['h', 'c']
| 2
| 68
| 0
|
--- diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +/* rx fifo threshold in 1kb granularity */ +#define mvpp23_port0_fifo_trsh (9 * 1024) +#define mvpp23_port1_fifo_trsh (4 * 1024) +#define mvpp23_port2_fifo_trsh (2 * 1024) + +/* rx flow control registers */ +#define mvpp2_rx_fc_reg(port) (0x150 + 4 * (port)) +#define mvpp2_rx_fc_en bit(24) +#define mvpp2_rx_fc_trsh_offs 16 +#define mvpp2_rx_fc_trsh_mask (0xff << mvpp2_rx_fc_trsh_offs) +#define mvpp2_rx_fc_trsh_unit 256 + +void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en); + + diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c + if (port->priv->hw_version == mvpp23) + mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause); +/* configure rx fifo flow control thresholds */ +static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv) +{ + int port, val; + + /* port 0: maximum speed -10gb/s port + * required by spec rx fifo threshold 9kb + * port 1: maximum speed -5gb/s port + * required by spec rx fifo threshold 4kb + * port 2: maximum speed -1gb/s port + * required by spec rx fifo threshold 2kb + */ + + /* without loopback port */ + for (port = 0; port < (mvpp2_max_ports - 1); port++) { + if (port == 0) { + val = (mvpp23_port0_fifo_trsh / mvpp2_rx_fc_trsh_unit) + << mvpp2_rx_fc_trsh_offs; + val &= mvpp2_rx_fc_trsh_mask; + mvpp2_write(priv, mvpp2_rx_fc_reg(port), val); + } else if (port == 1) { + val = (mvpp23_port1_fifo_trsh / mvpp2_rx_fc_trsh_unit) + << mvpp2_rx_fc_trsh_offs; + val &= mvpp2_rx_fc_trsh_mask; + mvpp2_write(priv, mvpp2_rx_fc_reg(port), val); + } else { + val = (mvpp23_port2_fifo_trsh / mvpp2_rx_fc_trsh_unit) + << mvpp2_rx_fc_trsh_offs; + val &= mvpp2_rx_fc_trsh_mask; + mvpp2_write(priv, mvpp2_rx_fc_reg(port), val); + } + } +} + +/* configure rx fifo flow control thresholds */ +void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en) +{ + int val; + + val = mvpp2_read(priv, mvpp2_rx_fc_reg(port)); + + if (en) + val |= mvpp2_rx_fc_en; + else + val &= ~mvpp2_rx_fc_en; + + mvpp2_write(priv, mvpp2_rx_fc_reg(port), val); +} + + if (priv->hw_version == mvpp23) + mvpp23_rx_fifo_fc_set_tresh(priv);
|
Networking
|
aca0e23584c90fb3b3aee3e413fd872dee1d55fb
|
stefan chulski marcin wojtas mw semihalf com
|
drivers
|
net
|
ethernet, marvell, mvpp2
|
net: mvpp2: set 802.3x gop flow control mode
|
this patch fix gmac tx flow control autoneg. flow control autoneg wrongly were disabled with enabled tx flow control.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tx flow control support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mvpp2 ']
|
['c']
| 1
| 1
| 1
|
--- diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c - ctrl2 &= ~(mvpp2_gmac_inband_an_mask | mvpp2_gmac_pcs_enable_mask); + ctrl2 &= ~(mvpp2_gmac_inband_an_mask | mvpp2_gmac_pcs_enable_mask | mvpp2_gmac_flow_ctrl_mask);
|
Networking
|
262412d55acd58e39b71a277c25ceeeb851cf0f6
|
stefan chulski marcin wojtas mw semihalf com
|
drivers
|
net
|
ethernet, marvell, mvpp2
|
net: mvpp2: add tx fc firmware check
|
patch check that tx fc firmware is running in cm3. if not, global tx fc would be disabled.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tx flow control support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mvpp2 ']
|
['h', 'c']
| 2
| 33
| 7
|
--- diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h +#define mss_fc_max_timeout 5000 diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +static int mvpp2_enable_global_fc(struct mvpp2 *priv) +{ + int val, timeout = 0; + + /* enable global flow control. in this stage global + * flow control enabled, but still disabled per port. + */ + val = mvpp2_cm3_read(priv, mss_fc_com_reg); + val |= flow_control_enable_bit; + mvpp2_cm3_write(priv, mss_fc_com_reg, val); + + /* check if firmware running and disable fc if not*/ + val |= flow_control_update_command_bit; + mvpp2_cm3_write(priv, mss_fc_com_reg, val); + + while (timeout < mss_fc_max_timeout) { + val = mvpp2_cm3_read(priv, mss_fc_com_reg); + + if (!(val & flow_control_update_command_bit)) + return 0; + usleep_range(10, 20); + timeout++; + } + + priv->global_tx_fc = false; + return -eopnotsupp; +} + - int err, val; + int err; - /* enable global flow control. in this stage global - * flow control enabled, but still disabled per port. - */ - val = mvpp2_cm3_read(priv, mss_fc_com_reg); - val |= flow_control_enable_bit; - mvpp2_cm3_write(priv, mss_fc_com_reg, val); + err = mvpp2_enable_global_fc(priv); + if (err) + dev_warn(&pdev->dev, "minimum of cm3 firmware 18.09 and chip revision b0 required for flow control ");
|
Networking
|
9ca5e767ec34336389f3dc68f3cbd7bd91c53d2e
|
stefan chulski marcin wojtas mw semihalf com
|
drivers
|
net
|
ethernet, marvell, mvpp2
|
net: mvpp2: add tx flow control support for jumbo frames
|
with mtu less than 1500b on all ports, the driver uses per cpu pool mode. if one of the ports set to jumbo frame mtu size, all ports move to shared pools mode. here, buffer manager tx flow control reconfigured on all ports.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add tx flow control support for jumbo frames
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mvpp2 ']
|
['c']
| 1
| 26
| 0
|
--- diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c +/* disable/enable flow control for bm pool on all ports */ +static void mvpp2_bm_pool_update_priv_fc(struct mvpp2 *priv, bool en) +{ + struct mvpp2_port *port; + int i; + + for (i = 0; i < priv->port_count; i++) { + port = priv->port_list[i]; + if (port->priv->percpu_pools) { + for (i = 0; i < port->nrxqs; i++) + mvpp2_bm_pool_update_fc(port, &port->priv->bm_pools[i], + port->tx_fc & en); + } else { + mvpp2_bm_pool_update_fc(port, port->pool_long, port->tx_fc & en); + mvpp2_bm_pool_update_fc(port, port->pool_short, port->tx_fc & en); + } + } +} + + bool change_percpu = (percpu != priv->percpu_pools); + if (change_percpu) + mvpp2_bm_pool_update_priv_fc(priv, false); + + if (change_percpu) + mvpp2_bm_pool_update_priv_fc(priv, true); +
|
Networking
|
3a616b92a9d17448d96a33bf58e69f01457fd43a
|
stefan chulski
|
drivers
|
net
|
ethernet, marvell, mvpp2
|
netdevsim: fib: add debugfs to debug route offload failure
|
add "fail_route_offload" flag to disallow offloading routes. it is needed to test "offload failed" notifications.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add debugfs to debug route offload failure
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['netdevsim', 'fib']
|
['c']
| 1
| 112
| 2
|
--- diff --git a/drivers/net/netdevsim/fib.c b/drivers/net/netdevsim/fib.c --- a/drivers/net/netdevsim/fib.c +++ b/drivers/net/netdevsim/fib.c +#include <linux/debugfs.h> + struct dentry *ddir; + bool fail_route_offload; +static void +nsim_fib4_rt_offload_failed_flag_set(struct net *net, + struct fib_entry_notifier_info *fen_info) +{ + u32 *p_dst = (u32 *)&fen_info->dst; + struct fib_rt_info fri; + + fri.fi = fen_info->fi; + fri.tb_id = fen_info->tb_id; + fri.dst = cpu_to_be32(*p_dst); + fri.dst_len = fen_info->dst_len; + fri.tos = fen_info->tos; + fri.type = fen_info->type; + fri.offload = false; + fri.trap = false; + fri.offload_failed = true; + fib_alias_hw_flags_set(net, &fri); +} + + if (data->fail_route_offload) { + /* for testing purposes, user set debugfs fail_route_offload + * value to true. simulate hardware programming latency and then + * fail. + */ + msleep(1); + return -einval; + } + + if (err) { + struct net *net = devlink_net(data->devlink); + + nsim_fib4_rt_offload_failed_flag_set(net, fen_info); + } + if (data->fail_route_offload) { + /* for testing purposes, user set debugfs fail_route_offload + * value to true. simulate hardware programming latency and then + * fail. + */ + msleep(1); + return -einval; + } + +#if is_enabled(config_ipv6) +static void nsim_fib6_rt_offload_failed_flag_set(struct nsim_fib_data *data, + struct fib6_info **rt_arr, + unsigned int nrt6) + +{ + struct net *net = devlink_net(data->devlink); + int i; + + for (i = 0; i < nrt6; i++) + fib6_info_hw_flags_set(net, rt_arr[i], false, false, true); +} +#else +static void nsim_fib6_rt_offload_failed_flag_set(struct nsim_fib_data *data, + struct fib6_info **rt_arr, + unsigned int nrt6) +{ +} +#endif + + if (data->fail_route_offload) { + /* for testing purposes, user set debugfs fail_route_offload + * value to true. simulate hardware programming latency and then + * fail. + */ + msleep(1); + return -einval; + } + - int err = 0; + int err; + if (err) + goto err_rt_offload_failed_flag_set; + if (err) + goto err_rt_offload_failed_flag_set; + return 0; + +err_rt_offload_failed_flag_set: + nsim_fib6_rt_offload_failed_flag_set(data, fib6_event->rt_arr, + fib6_event->nrt6); +static int +nsim_fib_debugfs_init(struct nsim_fib_data *data, struct nsim_dev *nsim_dev) +{ + data->ddir = debugfs_create_dir("fib", nsim_dev->ddir); + if (is_err(data->ddir)) + return ptr_err(data->ddir); + + data->fail_route_offload = false; + debugfs_create_bool("fail_route_offload", 0600, data->ddir, + &data->fail_route_offload); + return 0; +} + +static void nsim_fib_debugfs_exit(struct nsim_fib_data *data) +{ + debugfs_remove_recursive(data->ddir); +} + + struct nsim_dev *nsim_dev; - err = rhashtable_init(&data->nexthop_ht, &nsim_nexthop_ht_params); + nsim_dev = devlink_priv(devlink); + err = nsim_fib_debugfs_init(data, nsim_dev); + err = rhashtable_init(&data->nexthop_ht, &nsim_nexthop_ht_params); + if (err) + goto err_debugfs_exit; + +err_debugfs_exit: + nsim_fib_debugfs_exit(data); + nsim_fib_debugfs_exit(data);
|
Networking
|
134c7532424067b3006024c1acc44bd195245622
|
amit cohen
|
drivers
|
net
|
netdevsim
|
nfc: add a virtual nci device driver
|
nci virtual device simulates a nci device to the user. it can be used to validate the nci module and applications. this driver supports communication between the virtual nci device and nci module.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add a virtual nci device driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['nfc']
|
['kconfig', 'c', 'makefile']
| 3
| 227
| 0
|
--- diff --git a/drivers/nfc/kconfig b/drivers/nfc/kconfig --- a/drivers/nfc/kconfig +++ b/drivers/nfc/kconfig +config nfc_virtual_nci + tristate "nci device simulator driver" + depends on nfc_nci + help + nci virtual device simulates a nci device to the user. + it can be used to validate the nci module and applications. + this driver supports communication between the virtual nci device and + module. + + if unsure, say n. + diff --git a/drivers/nfc/makefile b/drivers/nfc/makefile --- a/drivers/nfc/makefile +++ b/drivers/nfc/makefile +obj-$(config_nfc_virtual_nci) += virtual_ncidev.o diff --git a/drivers/nfc/virtual_ncidev.c b/drivers/nfc/virtual_ncidev.c --- /dev/null +++ b/drivers/nfc/virtual_ncidev.c +// spdx-license-identifier: gpl-2.0-or-later +/* + * virtual nci device simulation driver + * + * copyright (c) 2020 samsung electrnoics + * bongsu jeon <bongsu.jeon@samsung.com> + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/miscdevice.h> +#include <linux/mutex.h> +#include <net/nfc/nci_core.h> + +enum virtual_ncidev_mode { + virtual_ncidev_enabled, + virtual_ncidev_disabled, + virtual_ncidev_disabling, +}; + +#define ioctl_get_ncidev_idx 0 +#define virtual_nfc_protocols (nfc_proto_jewel_mask | \ + nfc_proto_mifare_mask | \ + nfc_proto_felica_mask | \ + nfc_proto_iso14443_mask | \ + nfc_proto_iso14443_b_mask | \ + nfc_proto_iso15693_mask) + +static enum virtual_ncidev_mode state; +static struct miscdevice miscdev; +static struct sk_buff *send_buff; +static struct nci_dev *ndev; +static define_mutex(nci_mutex); + +static int virtual_nci_open(struct nci_dev *ndev) +{ + return 0; +} + +static int virtual_nci_close(struct nci_dev *ndev) +{ + mutex_lock(&nci_mutex); + kfree_skb(send_buff); + send_buff = null; + mutex_unlock(&nci_mutex); + + return 0; +} + +static int virtual_nci_send(struct nci_dev *ndev, struct sk_buff *skb) +{ + mutex_lock(&nci_mutex); + if (state != virtual_ncidev_enabled) { + mutex_unlock(&nci_mutex); + return 0; + } + + if (send_buff) { + mutex_unlock(&nci_mutex); + return -1; + } + send_buff = skb_copy(skb, gfp_kernel); + mutex_unlock(&nci_mutex); + + return 0; +} + +static struct nci_ops virtual_nci_ops = { + .open = virtual_nci_open, + .close = virtual_nci_close, + .send = virtual_nci_send +}; + +static ssize_t virtual_ncidev_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) +{ + size_t actual_len; + + mutex_lock(&nci_mutex); + if (!send_buff) { + mutex_unlock(&nci_mutex); + return 0; + } + + actual_len = min_t(size_t, count, send_buff->len); + + if (copy_to_user(buf, send_buff->data, actual_len)) { + mutex_unlock(&nci_mutex); + return -efault; + } + + skb_pull(send_buff, actual_len); + if (send_buff->len == 0) { + consume_skb(send_buff); + send_buff = null; + } + mutex_unlock(&nci_mutex); + + return actual_len; +} + +static ssize_t virtual_ncidev_write(struct file *file, + const char __user *buf, + size_t count, loff_t *ppos) +{ + struct sk_buff *skb; + + skb = alloc_skb(count, gfp_kernel); + if (!skb) + return -enomem; + + if (copy_from_user(skb_put(skb, count), buf, count)) { + kfree_skb(skb); + return -efault; + } + + nci_recv_frame(ndev, skb); + return count; +} + +static int virtual_ncidev_open(struct inode *inode, struct file *file) +{ + int ret = 0; + + mutex_lock(&nci_mutex); + if (state != virtual_ncidev_disabled) { + mutex_unlock(&nci_mutex); + return -ebusy; + } + + ndev = nci_allocate_device(&virtual_nci_ops, virtual_nfc_protocols, + 0, 0); + if (!ndev) { + mutex_unlock(&nci_mutex); + return -enomem; + } + + ret = nci_register_device(ndev); + if (ret < 0) { + nci_free_device(ndev); + mutex_unlock(&nci_mutex); + return ret; + } + state = virtual_ncidev_enabled; + mutex_unlock(&nci_mutex); + + return 0; +} + +static int virtual_ncidev_close(struct inode *inode, struct file *file) +{ + mutex_lock(&nci_mutex); + + if (state == virtual_ncidev_enabled) { + state = virtual_ncidev_disabling; + mutex_unlock(&nci_mutex); + + nci_unregister_device(ndev); + nci_free_device(ndev); + + mutex_lock(&nci_mutex); + } + + state = virtual_ncidev_disabled; + mutex_unlock(&nci_mutex); + + return 0; +} + +static long virtual_ncidev_ioctl(struct file *flip, unsigned int cmd, + unsigned long arg) +{ + struct nfc_dev *nfc_dev = ndev->nfc_dev; + void __user *p = (void __user *)arg; + + if (cmd != ioctl_get_ncidev_idx) + return -enotty; + + if (copy_to_user(p, &nfc_dev->idx, sizeof(nfc_dev->idx))) + return -efault; + + return 0; +} + +static const struct file_operations virtual_ncidev_fops = { + .owner = this_module, + .read = virtual_ncidev_read, + .write = virtual_ncidev_write, + .open = virtual_ncidev_open, + .release = virtual_ncidev_close, + .unlocked_ioctl = virtual_ncidev_ioctl +}; + +static int __init virtual_ncidev_init(void) +{ + state = virtual_ncidev_disabled; + miscdev.minor = misc_dynamic_minor; + miscdev.name = "virtual_nci"; + miscdev.fops = &virtual_ncidev_fops; + miscdev.mode = s_iallugo; + + return misc_register(&miscdev); +} + +static void __exit virtual_ncidev_exit(void) +{ + misc_deregister(&miscdev); +} + +module_init(virtual_ncidev_init); +module_exit(virtual_ncidev_exit); + +module_license("gpl"); +module_description("virtual nci device simulation driver"); +module_author("bongsu jeon <bongsu.jeon@samsung.com>");
|
Networking
|
e624e6c3e777fb3dfed036b9da4d433aee3608a5
|
bongsu jeon
|
drivers
|
nfc
| |
octeontx2-af: cn10k: add mbox support for cn10k platform
|
firmware allocates memory regions for pfs and vfs in dram. the pfs memory region is used for af-pf and pf-vf mailbox. this mbox facilitates communication between af-pf and pf-vf.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 6
| 191
| 36
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.c b/drivers/net/ethernet/marvell/octeontx2/af/mbox.c --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.c - void *hw_mbase = mbox->hwbase + (devid * mbox_size); + void *hw_mbase = mdev->hwbase; -int otx2_mbox_init(struct otx2_mbox *mbox, void *hwbase, struct pci_dev *pdev, - void *reg_base, int direction, int ndevs) +static int otx2_mbox_setup(struct otx2_mbox *mbox, struct pci_dev *pdev, + void *reg_base, int direction, int ndevs) - struct otx2_mbox_dev *mdev; - int devid; - - mbox->hwbase = hwbase; - + + return 0; +} + +int otx2_mbox_init(struct otx2_mbox *mbox, void *hwbase, struct pci_dev *pdev, + void *reg_base, int direction, int ndevs) +{ + struct otx2_mbox_dev *mdev; + int devid, err; + + err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs); + if (err) + return err; + + mbox->hwbase = hwbase; + + mdev->hwbase = mdev->mbase; +/* initialize mailbox with the set of mailbox region addresses + * in the array hwbase. + */ +int otx2_mbox_regions_init(struct otx2_mbox *mbox, void **hwbase, + struct pci_dev *pdev, void *reg_base, + int direction, int ndevs) +{ + struct otx2_mbox_dev *mdev; + int devid, err; + + err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs); + if (err) + return err; + + mbox->hwbase = hwbase[0]; + + for (devid = 0; devid < ndevs; devid++) { + mdev = &mbox->dev[devid]; + mdev->mbase = hwbase[devid]; + mdev->hwbase = hwbase[devid]; + spin_lock_init(&mdev->mbox_lock); + /* init header to reset value */ + otx2_mbox_reset(mbox, devid); + } + + return 0; +} +export_symbol(otx2_mbox_regions_init); + - void *hw_mbase = mbox->hwbase + (devid * mbox_size); + void *hw_mbase = mdev->hwbase; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h + void *hwbase; +int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase, + struct pci_dev *pdev, void __force *reg_base, + int direction, int ndevs); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c --- a/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/ptp.c +#define pci_subsys_devid_cn10k_a_ptp 0xb900 +#define pci_subsys_devid_cnf10k_a_ptp 0xba00 +#define pci_subsys_devid_cnf10k_b_ptp 0xbc00 + { pci_device_sub(pci_vendor_id_cavium, pci_devid_octeontx2_ptp, + pci_vendor_id_cavium, + pci_subsys_devid_cn10k_a_ptp) }, + { pci_device_sub(pci_vendor_id_cavium, pci_devid_octeontx2_ptp, + pci_vendor_id_cavium, + pci_subsys_devid_cnf10k_a_ptp) }, + { pci_device_sub(pci_vendor_id_cavium, pci_devid_octeontx2_ptp, + pci_vendor_id_cavium, + pci_subsys_devid_cnf10k_b_ptp) }, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c + + if (!is_rvu_otx2(rvu)) + hw->cap.per_pf_mbox_regs = true; +static int rvu_get_mbox_regions(struct rvu *rvu, void **mbox_addr, + int num, int type) +{ + struct rvu_hwinfo *hw = rvu->hw; + int region; + u64 bar4; + + /* for cn10k platform vf mailbox regions of a pf follows after the + * pf <-> af mailbox region. whereas for octeontx2 it is read from + * rvu_pf_vf_bar4_addr register. + */ + if (type == type_afvf) { + for (region = 0; region < num; region++) { + if (hw->cap.per_pf_mbox_regs) { + bar4 = rvu_read64(rvu, blkaddr_rvum, + rvu_af_pfx_bar4_addr(0)) + + mbox_size; + bar4 += region * mbox_size; + } else { + bar4 = rvupf_read64(rvu, rvu_pf_vf_bar4_addr); + bar4 += region * mbox_size; + } + mbox_addr[region] = (void *)ioremap_wc(bar4, mbox_size); + if (!mbox_addr[region]) + goto error; + } + return 0; + } + + /* for cn10k platform af <-> pf mailbox region of a pf is read from per + * pf registers. whereas for octeontx2 it is read from + * rvu_af_pf_bar4_addr register. + */ + for (region = 0; region < num; region++) { + if (hw->cap.per_pf_mbox_regs) { + bar4 = rvu_read64(rvu, blkaddr_rvum, + rvu_af_pfx_bar4_addr(region)); + } else { + bar4 = rvu_read64(rvu, blkaddr_rvum, + rvu_af_pf_bar4_addr); + bar4 += region * mbox_size; + } + mbox_addr[region] = (void *)ioremap_wc(bar4, mbox_size); + if (!mbox_addr[region]) + goto error; + } + return 0; + +error: + while (region--) + iounmap((void __iomem *)mbox_addr[region]); + return -enomem; +} + - void __iomem *hwbase = null, *reg_base; - int err, i, dir, dir_up; + int err = -einval, i, dir, dir_up; + void __iomem *reg_base; + void **mbox_regions; - u64 bar4_addr; + + mbox_regions = kcalloc(num, sizeof(void *), gfp_kernel); + if (!mbox_regions) + return -enomem; - bar4_addr = rvu_read64(rvu, blkaddr_rvum, rvu_af_pf_bar4_addr); + err = rvu_get_mbox_regions(rvu, mbox_regions, num, type_afpf); + if (err) + goto free_regions; - bar4_addr = rvupf_read64(rvu, rvu_pf_vf_bar4_addr); + err = rvu_get_mbox_regions(rvu, mbox_regions, num, type_afvf); + if (err) + goto free_regions; - return -einval; + return err; - if (!mw->mbox_wq) - return -enomem; + if (!mw->mbox_wq) { + err = -enomem; + goto unmap_regions; + } - /* mailbox is a reserved memory (in ram) region shared between - * rvu devices, shouldn't be mapped as device memory to allow - * unaligned accesses. - */ - hwbase = ioremap_wc(bar4_addr, mbox_size * num); - if (!hwbase) { - dev_err(rvu->dev, "unable to map mailbox region "); - err = -enomem; - goto exit; - } - - err = otx2_mbox_init(&mw->mbox, hwbase, rvu->pdev, reg_base, dir, num); + err = otx2_mbox_regions_init(&mw->mbox, mbox_regions, rvu->pdev, + reg_base, dir, num); - err = otx2_mbox_init(&mw->mbox_up, hwbase, rvu->pdev, - reg_base, dir_up, num); + err = otx2_mbox_regions_init(&mw->mbox_up, mbox_regions, rvu->pdev, + reg_base, dir_up, num); - + kfree(mbox_regions); + - if (hwbase) - iounmap((void __iomem *)hwbase); +unmap_regions: + while (num--) + iounmap((void __iomem *)mbox_regions[num]); +free_regions: + kfree(mbox_regions); + struct otx2_mbox *mbox = &mw->mbox; + struct otx2_mbox_dev *mdev; + int devid; + - if (mw->mbox.hwbase) - iounmap((void __iomem *)mw->mbox.hwbase); + for (devid = 0; devid < mbox->ndevs; devid++) { + mdev = &mbox->dev[devid]; + if (mdev->hwbase) + iounmap((void __iomem *)mdev->hwbase); + } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +#define pci_subsys_devid_cn10k_a 0xb900 + bool per_pf_mbox_regs; /* pf mbox specified in per pf registers ? */ +/* revid for pcie devices. + * bits 0..1: minor pass, bit 3..2: major pass + * bits 7..4: midr id + */ +#define pci_revision_id_96xx 0x00 +#define pci_revision_id_95xx 0x10 +#define pci_revision_id_loki 0x20 +#define pci_revision_id_98xx 0x30 +#define pci_revision_id_95xxmm 0x40 + +static inline bool is_rvu_otx2(struct rvu *rvu) +{ + struct pci_dev *pdev = rvu->pdev; + + u8 midr = pdev->revision & 0xf0; + + return (midr == pci_revision_id_96xx || midr == pci_revision_id_95xx || + midr == pci_revision_id_loki || midr == pci_revision_id_98xx || + midr == pci_revision_id_95xxmm); +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +#define rvu_af_pfx_bar4_addr(a) (0x5000 | (a) << 4) +#define rvu_af_pfx_bar4_cfg (0x5200 | (a) << 4) +#define rvu_af_pfx_vf_bar4_addr (0x5400 | (a) << 4) +#define rvu_af_pfx_vf_bar4_cfg (0x5600 | (a) << 4) +#define rvu_af_pfx_lmtline_addr (0x5800 | (a) << 4) +#define rvu_pf_vf_mbox_addr (0xc40) +#define rvu_pf_lmtline_addr (0xc48)
|
Networking
|
98c5611163603d3d8012b1bf64ab48fd932cf734
|
subbaraya sundeep
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-pf: cn10k: add mbox support for cn10k
|
firmware allocates memory regions for pfs and vfs in dram. the pfs memory region is used for af-pf and pf-vf mailbox. this mbox facilitate communication between af-pf and pf-vf.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c', 'makefile']
| 6
| 73
| 27
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/makefile b/drivers/net/ethernet/marvell/octeontx2/nic/makefile --- a/drivers/net/ethernet/marvell/octeontx2/nic/makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/makefile -obj-$(config_octeontx2_pf) += octeontx2_nicpf.o -obj-$(config_octeontx2_vf) += octeontx2_nicvf.o +obj-$(config_octeontx2_pf) += rvu_nicpf.o +obj-$(config_octeontx2_vf) += rvu_nicvf.o -octeontx2_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \ +rvu_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \ -octeontx2_nicvf-y := otx2_vf.o +rvu_nicvf-y := otx2_vf.o diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h - u8 hw_tso; +#define hw_tso bit_ull(0) +#define cn10k_mbox bit_ull(1) + unsigned long cap_flag; +/* revid for pcie devices. + * bits 0..1: minor pass, bit 3..2: major pass + * bits 7..4: midr id + */ +#define pci_revision_id_96xx 0x00 +#define pci_revision_id_95xx 0x10 +#define pci_revision_id_loki 0x20 +#define pci_revision_id_98xx 0x30 +#define pci_revision_id_95xxmm 0x40 + +static inline bool is_dev_otx2(struct pci_dev *pdev) +{ + u8 midr = pdev->revision & 0xf0; + + return (midr == pci_revision_id_96xx || midr == pci_revision_id_95xx || + midr == pci_revision_id_loki || midr == pci_revision_id_98xx || + midr == pci_revision_id_95xxmm); +} + - hw->hw_tso = true; + __set_bit(hw_tso, &hw->cap_flag); - hw->hw_tso = false; + __clear_bit(hw_tso, &hw->cap_flag); + if (!is_dev_otx2(pfvf->pdev)) + __set_bit(cn10k_mbox, &hw->cap_flag); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c -#define drv_name "octeontx2-nicpf" -#define drv_string "marvell octeontx2 nic physical function driver" +#define drv_name "rvu_nicpf" +#define drv_string "marvell rvu nic physical function driver" - base = readq((void __iomem *)((u64)pf->reg_base + rvu_pf_vf_bar4_addr)); - hwbase = ioremap_wc(base, mbox_size * pf->total_vfs); + /* on cn10k platform, pf <-> vf mailbox region follows after + * pf <-> af mailbox region. + */ + if (test_bit(cn10k_mbox, &pf->hw.cap_flag)) + base = pci_resource_start(pf->pdev, pci_mbox_bar_num) + + mbox_size; + else + base = readq((void __iomem *)((u64)pf->reg_base + + rvu_pf_vf_bar4_addr)); + hwbase = ioremap_wc(base, mbox_size * pf->total_vfs); - pci_resource_len(pf->pdev, pci_mbox_bar_num)); + mbox_size); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h +#define rvu_pf_vf_mbox_addr (0xc40) +#define rvu_pf_lmtline_addr (0xc48) +#define rvu_vf_mbox_region (0xc0000) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c - if (!pfvf->hw.hw_tso) - return false; + if (!test_bit(hw_tso, &pfvf->hw.cap_flag)) + return false; + diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c -#define drv_name "octeontx2-nicvf" -#define drv_string "marvell octeontx2 nic virtual function driver" +#define drv_name "rvu_nicvf" +#define drv_string "marvell rvu nic virtual function driver" - if (mbox->mbox.hwbase) + if (mbox->mbox.hwbase && !test_bit(cn10k_mbox, &vf->hw.cap_flag)) - /* mailbox is a reserved memory (in ram) region shared between - * admin function (i.e pf0) and this vf, shouldn't be mapped as - * device memory to allow unaligned accesses. - */ - hwbase = ioremap_wc(pci_resource_start(vf->pdev, pci_mbox_bar_num), - pci_resource_len(vf->pdev, pci_mbox_bar_num)); - if (!hwbase) { - dev_err(vf->dev, "unable to map vfaf mailbox region "); - err = -enomem; - goto exit; + if (test_bit(cn10k_mbox, &vf->hw.cap_flag)) { + /* for cn10k platform, vf mailbox region is in its bar2 + * register space + */ + hwbase = vf->reg_base + rvu_vf_mbox_region; + } else { + /* mailbox is a reserved memory (in ram) region shared between + * admin function (i.e pf0) and this vf, shouldn't be mapped as + * device memory to allow unaligned accesses. + */ + hwbase = ioremap_wc(pci_resource_start(vf->pdev, + pci_mbox_bar_num), + pci_resource_len(vf->pdev, + pci_mbox_bar_num)); + if (!hwbase) { + dev_err(vf->dev, "unable to map vfaf mailbox region "); + err = -enomem; + goto exit; + } + if (hwbase && !test_bit(cn10k_mbox, &vf->hw.cap_flag)) + iounmap(hwbase);
|
Networking
|
facede8209ef0dee84557c036e8502a99bb20a91
|
subbaraya sundeep
|
drivers
|
net
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ethernet, marvell, nic, octeontx2
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octeontx2-af: cn10k: update nix/npa context structure
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nix hardware context structure got changed to accommodate new features like bandwidth steering, l3/l4 outer/inner checksum enable/disable etc., on cn10k platform. this patch defines new mbox message nix_cn10k_aq_inst for new nix context initialization.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add marvell cn10k support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['octeontx2-af ']
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['h', 'c']
| 3
| 223
| 424
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--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +m(nix_cn10k_aq_enq, 0x8019, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \ + nix_cn10k_aq_enq_rsp) +/* cn10k nix aq enqueue msg */ +struct nix_cn10k_aq_enq_req { + struct mbox_msghdr hdr; + u32 qidx; + u8 ctype; + u8 op; + union { + struct nix_cn10k_rq_ctx_s rq; + struct nix_cn10k_sq_ctx_s sq; + struct nix_cq_ctx_s cq; + struct nix_rsse_s rss; + struct nix_rx_mce_s mce; + }; + union { + struct nix_cn10k_rq_ctx_s rq_mask; + struct nix_cn10k_sq_ctx_s sq_mask; + struct nix_cq_ctx_s cq_mask; + struct nix_rsse_s rss_mask; + struct nix_rx_mce_s mce_mask; + }; +}; + +struct nix_cn10k_aq_enq_rsp { + struct mbox_msghdr hdr; + union { + struct nix_cn10k_rq_ctx_s rq; + struct nix_cn10k_sq_ctx_s sq; + struct nix_cq_ctx_s cq; + struct nix_rsse_s rss; + struct nix_rx_mce_s mce; + }; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +/* cn10k mbox handler */ +int rvu_mbox_handler_nix_cn10k_aq_enq(struct rvu *rvu, + struct nix_cn10k_aq_enq_req *req, + struct nix_cn10k_aq_enq_rsp *rsp) +{ + return rvu_nix_aq_enq_inst(rvu, (struct nix_aq_enq_req *)req, + (struct nix_aq_enq_rsp *)rsp); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h -#if defined(__big_endian_bitfield) - u64 doneint : 1; /* w0 */ - u64 reserved_44_62 : 19; - u64 cindex : 20; - u64 reserved_17_23 : 7; - u64 lf : 9; - u64 ctype : 4; - u64 op : 4; -#else - u64 op : 4; + u64 op : 4; /* w0 */ -#endif -#if defined(__big_endian_bitfield) - u64 reserved_17_63 : 47; /* w0 */ - u64 doneint : 1; - u64 compcode : 8; - u64 ctype : 4; - u64 op : 4; -#else - u64 op : 4; + u64 op : 4; /* w0 */ -#endif -#if defined(__big_endian_bitfield) /* w1 */ - u64 avg_level : 8; - u64 reserved_118_119 : 2; - u64 shift : 6; - u64 aura_drop : 8; - u64 reserved_98_103 : 6; - u64 bp_ena : 2; - u64 aura_drop_ena : 1; - u64 pool_drop_ena : 1; - u64 reserved_93 : 1; - u64 avg_con : 9; - u64 pool_way_mask : 16; - u64 pool_caching : 1; - u64 reserved_65 : 2; - u64 ena : 1; -#else - u64 ena : 1; + u64 ena : 1; /* w1 */ -#endif -#if defined(__big_endian_bitfield) /* w2 */ - u64 reserved_189_191 : 3; - u64 nix1_bpid : 9; - u64 reserved_177_179 : 3; - u64 nix0_bpid : 9; - u64 reserved_164_167 : 4; - u64 count : 36; -#else - u64 count : 36; + u64 count : 36; /* w2 */ -#endif -#if defined(__big_endian_bitfield) /* w3 */ - u64 reserved_252_255 : 4; - u64 fc_hyst_bits : 4; - u64 fc_stype : 2; - u64 fc_up_crossing : 1; - u64 fc_ena : 1; - u64 reserved_240_243 : 4; - u64 bp : 8; - u64 reserved_228_231 : 4; - u64 limit : 36; -#else - u64 limit : 36; + u64 limit : 36; /* w3 */ - u64 reserved_240_243 : 4; + u64 reserved_241_243 : 3; + u64 fc_be : 1; -#endif -#if defined(__big_endian_bitfield) /* w5 */ - u64 reserved_379_383 : 5; - u64 err_qint_idx : 7; - u64 reserved_371 : 1; - u64 thresh_qint_idx : 7; - u64 reserved_363 : 1; - u64 thresh_up : 1; - u64 thresh_int_ena : 1; - u64 thresh_int : 1; - u64 err_int_ena : 8; - u64 err_int : 8; - u64 update_time : 16; - u64 pool_drop : 8; -#else - u64 pool_drop : 8; + u64 pool_drop : 8; /* w5 */ -#endif -#if defined(__big_endian_bitfield) /* w6 */ - u64 reserved_420_447 : 28; - u64 thresh : 36; -#else - u64 thresh : 36; - u64 reserved_420_447 : 28; -#endif + u64 thresh : 36; /* w6*/ + u64 rsvd_423_420 : 4; + u64 fc_msh_dst : 11; + u64 reserved_435_447 : 13; -#if defined(__big_endian_bitfield) /* w1 */ - u64 reserved_115_127 : 13; - u64 buf_size : 11; - u64 reserved_100_103 : 4; - u64 buf_offset : 12; - u64 stack_way_mask : 16; - u64 reserved_70_71 : 3; - u64 stack_caching : 1; - u64 reserved_66_67 : 2; - u64 nat_align : 1; - u64 ena : 1; -#else -#endif -#if defined(__big_endian_bitfield) /* w2 */ - u64 stack_pages : 32; - u64 stack_max_pages : 32; -#else -#endif -#if defined(__big_endian_bitfield) /* w3 */ - u64 reserved_240_255 : 16; - u64 op_pc : 48; -#else -#endif -#if defined(__big_endian_bitfield) /* w4 */ - u64 reserved_316_319 : 4; - u64 update_time : 16; - u64 reserved_297_299 : 3; - u64 fc_up_crossing : 1; - u64 fc_hyst_bits : 4; - u64 fc_stype : 2; - u64 fc_ena : 1; - u64 avg_con : 9; - u64 avg_level : 8; - u64 reserved_270_271 : 2; - u64 shift : 6; - u64 reserved_260_263 : 4; - u64 stack_offset : 4; -#else - u64 reserved_297_299 : 3; + u64 fc_be : 1; + u64 reserved_298_299 : 2; -#endif -#if defined(__big_endian_bitfield) /* w8 */ - u64 reserved_571_575 : 5; - u64 err_qint_idx : 7; - u64 reserved_563 : 1; - u64 thresh_qint_idx : 7; - u64 reserved_555 : 1; - u64 thresh_up : 1; - u64 thresh_int_ena : 1; - u64 thresh_int : 1; - u64 err_int_ena : 8; - u64 err_int : 8; - u64 reserved_512_535 : 24; -#else -#endif -#if defined(__big_endian_bitfield) /* w9 */ - u64 reserved_612_639 : 28; -#else - u64 thresh : 36; - u64 reserved_612_639 : 28; -#endif + u64 rsvd_615_612 : 4; + u64 fc_msh_dst : 11; + u64 reserved_627_639 : 13; + nix_aq_ctype_band_prof = 0x6, -#if defined(__big_endian_bitfield) - u64 doneint : 1; /* w0 */ - u64 reserved_44_62 : 19; - u64 cindex : 20; - u64 reserved_15_23 : 9; - u64 lf : 7; - u64 ctype : 4; - u64 op : 4; -#else - u64 lf : 7; - u64 reserved_15_23 : 9; + u64 lf : 9; + u64 reserved_17_23 : 7; -#endif -#if defined(__big_endian_bitfield) - u64 reserved_17_63 : 47; /* w0 */ - u64 doneint : 1; - u64 compcode : 8; - u64 ctype : 4; - u64 op : 4; -#else -#endif -#if defined(__big_endian_bitfield) /* w1 */ - u64 wrptr : 20; - u64 avg_con : 9; - u64 cint_idx : 7; - u64 cq_err : 1; - u64 qint_idx : 7; - u64 rsvd_81_83 : 3; - u64 bpid : 9; - u64 rsvd_69_71 : 3; - u64 bp_ena : 1; - u64 rsvd_64_67 : 4; -#else -#endif -#if defined(__big_endian_bitfield) /* w2 */ - u64 update_time : 16; - u64 avg_level : 8; - u64 head : 20; - u64 tail : 20; -#else -#endif -#if defined(__big_endian_bitfield) /* w3 */ - u64 cq_err_int_ena : 8; - u64 cq_err_int : 8; - u64 qsize : 4; - u64 rsvd_233_235 : 3; - u64 caching : 1; - u64 substream : 20; - u64 rsvd_210_211 : 2; - u64 ena : 1; - u64 drop_ena : 1; - u64 drop : 8; - u64 bp : 8; -#else -#endif +}; + +/* cn10k nix receive queue context structure */ +struct nix_cn10k_rq_ctx_s { + u64 ena : 1; + u64 sso_ena : 1; + u64 ipsech_ena : 1; + u64 ena_wqwd : 1; + u64 cq : 20; + u64 rsvd_36_24 : 13; + u64 lenerr_dis : 1; + u64 csum_il4_dis : 1; + u64 csum_ol4_dis : 1; + u64 len_il4_dis : 1; + u64 len_il3_dis : 1; + u64 len_ol4_dis : 1; + u64 len_ol3_dis : 1; + u64 wqe_aura : 20; + u64 spb_aura : 20; + u64 lpb_aura : 20; + u64 sso_grp : 10; + u64 sso_tt : 2; + u64 pb_caching : 2; + u64 wqe_caching : 1; + u64 xqe_drop_ena : 1; + u64 spb_drop_ena : 1; + u64 lpb_drop_ena : 1; + u64 pb_stashing : 1; + u64 ipsecd_drop_ena : 1; + u64 chi_ena : 1; + u64 rsvd_127_125 : 3; + u64 band_prof_id : 10; /* w2 */ + u64 rsvd_138 : 1; + u64 policer_ena : 1; + u64 spb_sizem1 : 6; + u64 wqe_skip : 2; + u64 rsvd_150_148 : 3; + u64 spb_ena : 1; + u64 lpb_sizem1 : 12; + u64 first_skip : 7; + u64 rsvd_171 : 1; + u64 later_skip : 6; + u64 xqe_imm_size : 6; + u64 rsvd_189_184 : 6; + u64 xqe_imm_copy : 1; + u64 xqe_hdr_split : 1; + u64 xqe_drop : 8; /* w3 */ + u64 xqe_pass : 8; + u64 wqe_pool_drop : 8; + u64 wqe_pool_pass : 8; + u64 spb_aura_drop : 8; + u64 spb_aura_pass : 8; + u64 spb_pool_drop : 8; + u64 spb_pool_pass : 8; + u64 lpb_aura_drop : 8; /* w4 */ + u64 lpb_aura_pass : 8; + u64 lpb_pool_drop : 8; + u64 lpb_pool_pass : 8; + u64 rsvd_291_288 : 4; + u64 rq_int : 8; + u64 rq_int_ena : 8; + u64 qint_idx : 7; + u64 rsvd_319_315 : 5; + u64 ltag : 24; /* w5 */ + u64 good_utag : 8; + u64 bad_utag : 8; + u64 flow_tagw : 6; + u64 ipsec_vwqe : 1; + u64 vwqe_ena : 1; + u64 vwqe_wait : 8; + u64 max_vsize_exp : 4; + u64 vwqe_skip : 2; + u64 rsvd_383_382 : 2; + u64 octs : 48; /* w6 */ + u64 rsvd_447_432 : 16; + u64 pkts : 48; /* w7 */ + u64 rsvd_511_496 : 16; + u64 drop_octs : 48; /* w8 */ + u64 rsvd_575_560 : 16; + u64 drop_pkts : 48; /* w9 */ + u64 rsvd_639_624 : 16; + u64 re_pkts : 48; /* w10 */ + u64 rsvd_703_688 : 16; + u64 rsvd_767_704; /* w11 */ + u64 rsvd_831_768; /* w12 */ + u64 rsvd_895_832; /* w13 */ + u64 rsvd_959_896; /* w14 */ + u64 rsvd_1023_960; /* w15 */ +}; + +/* cn10k nix send queue context structure */ +struct nix_cn10k_sq_ctx_s { + u64 ena : 1; + u64 qint_idx : 6; + u64 substream : 20; + u64 sdp_mcast : 1; + u64 cq : 20; + u64 sqe_way_mask : 16; + u64 smq : 10; /* w1 */ + u64 cq_ena : 1; + u64 xoff : 1; + u64 sso_ena : 1; + u64 smq_rr_weight : 14; + u64 default_chan : 12; + u64 sqb_count : 16; + u64 rsvd_120_119 : 2; + u64 smq_rr_count_lb : 7; + u64 smq_rr_count_ub : 25; /* w2 */ + u64 sqb_aura : 20; + u64 sq_int : 8; + u64 sq_int_ena : 8; + u64 sqe_stype : 2; + u64 rsvd_191 : 1; + u64 max_sqe_size : 2; /* w3 */ + u64 cq_limit : 8; + u64 lmt_dis : 1; + u64 mnq_dis : 1; + u64 smq_next_sq : 20; + u64 smq_lso_segnum : 8; + u64 tail_offset : 6; + u64 smenq_offset : 6; + u64 head_offset : 6; + u64 smenq_next_sqb_vld : 1; + u64 smq_pend : 1; + u64 smq_next_sq_vld : 1; + u64 rsvd_255_253 : 3; + u64 next_sqb : 64; /* w4 */ + u64 tail_sqb : 64; /* w5 */ + u64 smenq_sqb : 64; /* w6 */ + u64 smenq_next_sqb : 64; /* w7 */ + u64 head_sqb : 64; /* w8 */ + u64 rsvd_583_576 : 8; /* w9 */ + u64 vfi_lso_total : 18; + u64 vfi_lso_sizem1 : 3; + u64 vfi_lso_sb : 8; + u64 vfi_lso_mps : 14; + u64 vfi_lso_vlan0_ins_ena : 1; + u64 vfi_lso_vlan1_ins_ena : 1; + u64 vfi_lso_vld : 1; + u64 rsvd_639_630 : 10; + u64 scm_lso_rem : 18; /* w10 */ + u64 rsvd_703_658 : 46; + u64 octs : 48; /* w11 */ + u64 rsvd_767_752 : 16; + u64 pkts : 48; /* w12 */ + u64 rsvd_831_816 : 16; + u64 rsvd_895_832 : 64; /* w13 */ + u64 dropped_octs : 48; + u64 rsvd_959_944 : 16; + u64 dropped_pkts : 48; + u64 rsvd_1023_1008 : 16; -#if defined(__big_endian_bitfield) /* w0 */ - u64 wqe_aura : 20; - u64 substream : 20; - u64 cq : 20; - u64 ena_wqwd : 1; - u64 ipsech_ena : 1; - u64 sso_ena : 1; - u64 ena : 1; -#else -#endif -#if defined(__big_endian_bitfield) /* w1 */ - u64 rsvd_127_122 : 6; - u64 lpb_drop_ena : 1; - u64 spb_drop_ena : 1; - u64 xqe_drop_ena : 1; - u64 wqe_caching : 1; - u64 pb_caching : 2; - u64 sso_tt : 2; - u64 sso_grp : 10; - u64 lpb_aura : 20; - u64 spb_aura : 20; -#else -#endif -#if defined(__big_endian_bitfield) /* w2 */ - u64 xqe_hdr_split : 1; - u64 xqe_imm_copy : 1; - u64 rsvd_189_184 : 6; - u64 xqe_imm_size : 6; - u64 later_skip : 6; - u64 rsvd_171 : 1; - u64 first_skip : 7; - u64 lpb_sizem1 : 12; - u64 spb_ena : 1; - u64 rsvd_150_148 : 3; - u64 wqe_skip : 2; - u64 spb_sizem1 : 6; - u64 rsvd_139_128 : 12; -#else - u64 rsvd_139_128 : 12; + u64 rsvd_139_128 : 12; /* w2 */ -#endif -#if defined(__big_endian_bitfield) /* w3 */ - u64 spb_pool_pass : 8; - u64 spb_pool_drop : 8; - u64 spb_aura_pass : 8; - u64 spb_aura_drop : 8; - u64 wqe_pool_pass : 8; - u64 wqe_pool_drop : 8; - u64 xqe_pass : 8; - u64 xqe_drop : 8; -#else - u64 xqe_drop : 8; + u64 xqe_drop : 8; /* w3*/ -#endif -#if defined(__big_endian_bitfield) /* w4 */ - u64 rsvd_319_315 : 5; - u64 qint_idx : 7; - u64 rq_int_ena : 8; - u64 rq_int : 8; - u64 rsvd_291_288 : 4; - u64 lpb_pool_pass : 8; - u64 lpb_pool_drop : 8; - u64 lpb_aura_pass : 8; - u64 lpb_aura_drop : 8; -#else - u64 lpb_aura_drop : 8; + u64 lpb_aura_drop : 8; /* w4 */ -#endif -#if defined(__big_endian_bitfield) /* w5 */ - u64 rsvd_383_366 : 18; - u64 flow_tagw : 6; - u64 bad_utag : 8; - u64 good_utag : 8; - u64 ltag : 24; -#else - u64 ltag : 24; + u64 ltag : 24; /* w5 */ -#endif -#if defined(__big_endian_bitfield) /* w6 */ - u64 rsvd_447_432 : 16; - u64 octs : 48; -#else - u64 octs : 48; + u64 octs : 48; /* w6 */ -#endif -#if defined(__big_endian_bitfield) /* w7 */ - u64 rsvd_511_496 : 16; - u64 pkts : 48; -#else - u64 pkts : 48; + u64 pkts : 48; /* w7 */ -#endif -#if defined(__big_endian_bitfield) /* w8 */ + u64 drop_octs : 48; /* w8 */ - u64 drop_octs : 48; -#else - u64 drop_octs : 48; - u64 rsvd_575_560 : 16; -#endif -#if defined(__big_endian_bitfield) /* w9 */ - u64 rsvd_639_624 : 16; - u64 drop_pkts : 48; -#else - u64 drop_pkts : 48; + u64 drop_pkts : 48; /* w9 */ -#endif -#if defined(__big_endian_bitfield) /* w10 */ + u64 re_pkts : 48; /* w10 */ - u64 re_pkts : 48; -#else - u64 re_pkts : 48; - u64 rsvd_703_688 : 16; -#endif -#if defined(__big_endian_bitfield) /* w0 */ - u64 sqe_way_mask : 16; - u64 cq : 20; - u64 sdp_mcast : 1; - u64 substream : 20; - u64 qint_idx : 6; - u64 ena : 1; -#else -#endif -#if defined(__big_endian_bitfield) /* w1 */ - u64 sqb_count : 16; - u64 default_chan : 12; - u64 smq_rr_quantum : 24; - u64 sso_ena : 1; - u64 xoff : 1; - u64 cq_ena : 1; - u64 smq : 9; -#else -#endif -#if defined(__big_endian_bitfield) /* w2 */ - u64 rsvd_191 : 1; - u64 sqe_stype : 2; - u64 sq_int_ena : 8; - u64 sq_int : 8; - u64 sqb_aura : 20; - u64 smq_rr_count : 25; -#else -#endif -#if defined(__big_endian_bitfield) /* w3 */ - u64 rsvd_255_253 : 3; - u64 smq_next_sq_vld : 1; - u64 smq_pend : 1; - u64 smenq_next_sqb_vld : 1; - u64 head_offset : 6; - u64 smenq_offset : 6; - u64 tail_offset : 6; - u64 smq_lso_segnum : 8; - u64 smq_next_sq : 20; - u64 mnq_dis : 1; - u64 lmt_dis : 1; - u64 cq_limit : 8; - u64 max_sqe_size : 2; -#else -#endif -#if defined(__big_endian_bitfield) /* w9 */ - u64 rsvd_639_630 : 10; - u64 vfi_lso_vld : 1; - u64 vfi_lso_vlan1_ins_ena : 1; - u64 vfi_lso_vlan0_ins_ena : 1; - u64 vfi_lso_mps : 14; - u64 vfi_lso_sb : 8; - u64 vfi_lso_sizem1 : 3; - u64 vfi_lso_total : 18; - u64 rsvd_583_576 : 8; -#else -#endif -#if defined(__big_endian_bitfield) /* w10 */ - u64 rsvd_703_658 : 46; - u64 scm_lso_rem : 18; -#else -#endif -#if defined(__big_endian_bitfield) /* w11 */ - u64 rsvd_767_752 : 16; - u64 octs : 48; -#else -#endif -#if defined(__big_endian_bitfield) /* w12 */ - u64 rsvd_831_816 : 16; - u64 pkts : 48; -#else -#endif -#if defined(__big_endian_bitfield) /* w14 */ - u64 rsvd_959_944 : 16; - u64 dropped_octs : 48; -#else -#endif -#if defined(__big_endian_bitfield) /* w15 */ - u64 rsvd_1023_1008 : 16; - u64 dropped_pkts : 48; -#else -#endif -#if defined(__big_endian_bitfield) - uint32_t reserved_20_31 : 12; - uint32_t rq : 20; -#else -#endif -#if defined(__big_endian_bitfield) /* w0 */ - uint64_t next : 16; - uint64_t pf_func : 16; - uint64_t rsvd_31_24 : 8; - uint64_t index : 20; - uint64_t eol : 1; - uint64_t rsvd_2 : 1; - uint64_t op : 2; -#else -#endif -#if defined(__big_endian_bitfield) - u64 rsvd_19_63 : 45; - u64 alg : 3; - u64 rsvd_14_15 : 2; - u64 sizem1 : 2; - u64 rsvd_10_11 : 2; - u64 layer : 2; - u64 offset : 8; -#else -#endif -#if defined(__big_endian_bitfield) - u64 reserved_35_63 :29; - u64 ltype_match :4; - u64 ltype_mask :4; - u64 sel_chan :1; - u64 ena :1; - u64 reserved_24_24 :1; - u64 lid :3; - u64 bytesm1 :5; - u64 hdr_offset :8; - u64 fn_mask :1; - u64 ln_mask :1; - u64 key_offset :6; -#else -#endif
|
Networking
|
30077d210c839928bdef70c590cab368b0a96b8a
|
geetha sowjanya
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: cn10k: update nix and npa context in debugfs
|
on cn10k platform npa and nix context structure bit fields had changed to support new features like bandwidth steering etc. this patch dumps approprate context for cn10k platform.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['c']
| 1
| 175
| 2
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c + struct rvu *rvu = m->private; + + if (!is_rvu_otx2(rvu)) + seq_printf(m, "w3: fc_be %d ", aura->fc_be); + if (!is_rvu_otx2(rvu)) + seq_printf(m, "w6: fc_msh_dst %d ", aura->fc_msh_dst); + struct rvu *rvu = m->private; + if (!is_rvu_otx2(rvu)) + seq_printf(m, "w4: fc_be %d ", pool->fc_be); - seq_printf(m, "w8: thresh_qint_idx %d w8: err_qint_idx %d ", + seq_printf(m, "w8: thresh_qint_idx %d w8: err_qint_idx %d ", + if (!is_rvu_otx2(rvu)) + seq_printf(m, "w8: fc_msh_dst %d ", pool->fc_msh_dst); +static void print_nix_cn10k_sq_ctx(struct seq_file *m, + struct nix_cn10k_sq_ctx_s *sq_ctx) +{ + seq_printf(m, "w0: ena %d w0: qint_idx %d ", + sq_ctx->ena, sq_ctx->qint_idx); + seq_printf(m, "w0: substream 0x%03x w0: sdp_mcast %d ", + sq_ctx->substream, sq_ctx->sdp_mcast); + seq_printf(m, "w0: cq %d w0: sqe_way_mask %d ", + sq_ctx->cq, sq_ctx->sqe_way_mask); + + seq_printf(m, "w1: smq %d w1: cq_ena %d w1: xoff %d ", + sq_ctx->smq, sq_ctx->cq_ena, sq_ctx->xoff); + seq_printf(m, "w1: sso_ena %d w1: smq_rr_weight %d ", + sq_ctx->sso_ena, sq_ctx->smq_rr_weight); + seq_printf(m, "w1: default_chan %d w1: sqb_count %d ", + sq_ctx->default_chan, sq_ctx->sqb_count); + + seq_printf(m, "w2: smq_rr_count_lb %d ", sq_ctx->smq_rr_count_lb); + seq_printf(m, "w2: smq_rr_count_ub %d ", sq_ctx->smq_rr_count_ub); + seq_printf(m, "w2: sqb_aura %d w2: sq_int %d ", + sq_ctx->sqb_aura, sq_ctx->sq_int); + seq_printf(m, "w2: sq_int_ena %d w2: sqe_stype %d ", + sq_ctx->sq_int_ena, sq_ctx->sqe_stype); + + seq_printf(m, "w3: max_sqe_size %d w3: cq_limit %d ", + sq_ctx->max_sqe_size, sq_ctx->cq_limit); + seq_printf(m, "w3: lmt_dis %d w3: mnq_dis %d ", + sq_ctx->mnq_dis, sq_ctx->lmt_dis); + seq_printf(m, "w3: smq_next_sq %d w3: smq_lso_segnum %d ", + sq_ctx->smq_next_sq, sq_ctx->smq_lso_segnum); + seq_printf(m, "w3: tail_offset %d w3: smenq_offset %d ", + sq_ctx->tail_offset, sq_ctx->smenq_offset); + seq_printf(m, "w3: head_offset %d w3: smenq_next_sqb_vld %d ", + sq_ctx->head_offset, sq_ctx->smenq_next_sqb_vld); + + seq_printf(m, "w4: next_sqb %llx ", sq_ctx->next_sqb); + seq_printf(m, "w5: tail_sqb %llx ", sq_ctx->tail_sqb); + seq_printf(m, "w6: smenq_sqb %llx ", sq_ctx->smenq_sqb); + seq_printf(m, "w7: smenq_next_sqb %llx ", + sq_ctx->smenq_next_sqb); + + seq_printf(m, "w8: head_sqb %llx ", sq_ctx->head_sqb); + + seq_printf(m, "w9: vfi_lso_total %d ", sq_ctx->vfi_lso_total); + seq_printf(m, "w9: vfi_lso_sizem1 %d w9: vfi_lso_sb %d ", + sq_ctx->vfi_lso_sizem1, sq_ctx->vfi_lso_sb); + seq_printf(m, "w9: vfi_lso_mps %d w9: vfi_lso_vlan0_ins_ena %d ", + sq_ctx->vfi_lso_mps, sq_ctx->vfi_lso_vlan0_ins_ena); + seq_printf(m, "w9: vfi_lso_vlan1_ins_ena %d w9: vfi_lso_vld %d ", + sq_ctx->vfi_lso_vld, sq_ctx->vfi_lso_vlan1_ins_ena); + + seq_printf(m, "w10: scm_lso_rem %llu ", + (u64)sq_ctx->scm_lso_rem); + seq_printf(m, "w11: octs %llu ", (u64)sq_ctx->octs); + seq_printf(m, "w12: pkts %llu ", (u64)sq_ctx->pkts); + seq_printf(m, "w14: dropped_octs %llu ", + (u64)sq_ctx->dropped_octs); + seq_printf(m, "w15: dropped_pkts %llu ", + (u64)sq_ctx->dropped_pkts); +} + + struct nix_hw *nix_hw = m->private; + struct rvu *rvu = nix_hw->rvu; + if (!is_rvu_otx2(rvu)) { + print_nix_cn10k_sq_ctx(m, (struct nix_cn10k_sq_ctx_s *)sq_ctx); + return; + } +static void print_nix_cn10k_rq_ctx(struct seq_file *m, + struct nix_cn10k_rq_ctx_s *rq_ctx) +{ + seq_printf(m, "w0: ena %d w0: sso_ena %d ", + rq_ctx->ena, rq_ctx->sso_ena); + seq_printf(m, "w0: ipsech_ena %d w0: ena_wqwd %d ", + rq_ctx->ipsech_ena, rq_ctx->ena_wqwd); + seq_printf(m, "w0: cq %d w0: lenerr_dis %d ", + rq_ctx->cq, rq_ctx->lenerr_dis); + seq_printf(m, "w0: csum_il4_dis %d w0: csum_ol4_dis %d ", + rq_ctx->csum_il4_dis, rq_ctx->csum_ol4_dis); + seq_printf(m, "w0: len_il4_dis %d w0: len_il3_dis %d ", + rq_ctx->len_il4_dis, rq_ctx->len_il3_dis); + seq_printf(m, "w0: len_ol4_dis %d w0: len_ol3_dis %d ", + rq_ctx->len_ol4_dis, rq_ctx->len_ol3_dis); + seq_printf(m, "w0: wqe_aura %d ", rq_ctx->wqe_aura); + + seq_printf(m, "w1: spb_aura %d w1: lpb_aura %d ", + rq_ctx->spb_aura, rq_ctx->lpb_aura); + seq_printf(m, "w1: spb_aura %d ", rq_ctx->spb_aura); + seq_printf(m, "w1: sso_grp %d w1: sso_tt %d ", + rq_ctx->sso_grp, rq_ctx->sso_tt); + seq_printf(m, "w1: pb_caching %d w1: wqe_caching %d ", + rq_ctx->pb_caching, rq_ctx->wqe_caching); + seq_printf(m, "w1: xqe_drop_ena %d w1: spb_drop_ena %d ", + rq_ctx->xqe_drop_ena, rq_ctx->spb_drop_ena); + seq_printf(m, "w1: lpb_drop_ena %d w1: pb_stashing %d ", + rq_ctx->lpb_drop_ena, rq_ctx->pb_stashing); + seq_printf(m, "w1: ipsecd_drop_ena %d w1: chi_ena %d ", + rq_ctx->ipsecd_drop_ena, rq_ctx->chi_ena); + + seq_printf(m, "w2: band_prof_id %d ", rq_ctx->band_prof_id); + seq_printf(m, "w2: policer_ena %d ", rq_ctx->policer_ena); + seq_printf(m, "w2: spb_sizem1 %d ", rq_ctx->spb_sizem1); + seq_printf(m, "w2: wqe_skip %d w2: sqb_ena %d ", + rq_ctx->wqe_skip, rq_ctx->spb_ena); + seq_printf(m, "w2: lpb_size1 %d w2: first_skip %d ", + rq_ctx->lpb_sizem1, rq_ctx->first_skip); + seq_printf(m, "w2: later_skip %d w2: xqe_imm_size %d ", + rq_ctx->later_skip, rq_ctx->xqe_imm_size); + seq_printf(m, "w2: xqe_imm_copy %d w2: xqe_hdr_split %d ", + rq_ctx->xqe_imm_copy, rq_ctx->xqe_hdr_split); + + seq_printf(m, "w3: xqe_drop %d w3: xqe_pass %d ", + rq_ctx->xqe_drop, rq_ctx->xqe_pass); + seq_printf(m, "w3: wqe_pool_drop %d w3: wqe_pool_pass %d ", + rq_ctx->wqe_pool_drop, rq_ctx->wqe_pool_pass); + seq_printf(m, "w3: spb_pool_drop %d w3: spb_pool_pass %d ", + rq_ctx->spb_pool_drop, rq_ctx->spb_pool_pass); + seq_printf(m, "w3: spb_aura_drop %d w3: spb_aura_pass %d ", + rq_ctx->spb_aura_pass, rq_ctx->spb_aura_drop); + + seq_printf(m, "w4: lpb_aura_drop %d w3: lpb_aura_pass %d ", + rq_ctx->lpb_aura_pass, rq_ctx->lpb_aura_drop); + seq_printf(m, "w4: lpb_pool_drop %d w3: lpb_pool_pass %d ", + rq_ctx->lpb_pool_drop, rq_ctx->lpb_pool_pass); + seq_printf(m, "w4: rq_int %d w4: rq_int_ena %d ", + rq_ctx->rq_int, rq_ctx->rq_int_ena); + seq_printf(m, "w4: qint_idx %d ", rq_ctx->qint_idx); + + seq_printf(m, "w5: ltag %d w5: good_utag %d ", + rq_ctx->ltag, rq_ctx->good_utag); + seq_printf(m, "w5: bad_utag %d w5: flow_tagw %d ", + rq_ctx->bad_utag, rq_ctx->flow_tagw); + seq_printf(m, "w5: ipsec_vwqe %d w5: vwqe_ena %d ", + rq_ctx->ipsec_vwqe, rq_ctx->vwqe_ena); + seq_printf(m, "w5: vwqe_wait %d w5: max_vsize_exp %d ", + rq_ctx->vwqe_wait, rq_ctx->max_vsize_exp); + seq_printf(m, "w5: vwqe_skip %d ", rq_ctx->vwqe_skip); + + seq_printf(m, "w6: octs %llu ", (u64)rq_ctx->octs); + seq_printf(m, "w7: pkts %llu ", (u64)rq_ctx->pkts); + seq_printf(m, "w8: drop_octs %llu ", (u64)rq_ctx->drop_octs); + seq_printf(m, "w9: drop_pkts %llu ", (u64)rq_ctx->drop_pkts); + seq_printf(m, "w10: re_pkts %llu ", (u64)rq_ctx->re_pkts); +} + + struct nix_hw *nix_hw = m->private; + struct rvu *rvu = nix_hw->rvu; + + if (!is_rvu_otx2(rvu)) { + print_nix_cn10k_rq_ctx(m, (struct nix_cn10k_rq_ctx_s *)rq_ctx); + return; + } + if (!cgx_get_cgxcnt_max()) + return; + +static const char *rvu_get_dbg_dir_name(struct rvu *rvu) +{ + if (!is_rvu_otx2(rvu)) + return "cn10k"; + else + return "octeontx2"; +} + - rvu->rvu_dbg.root = debugfs_create_dir(debugfs_dir_name, null); + rvu->rvu_dbg.root = debugfs_create_dir(rvu_get_dbg_dir_name(rvu), null);
|
Networking
|
3feac505fb316ebe86928453db8aa78e296927b7
|
geetha sowjanya
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-pf: cn10k: initialise nix context
|
on cn10k platform nix rq and sq context structure got changed. this patch uses new mbox message "nix_cn10k_aq_enq" for nix context initialization on cn10k platform.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 2
| 80
| 31
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +static int cn10k_sq_aq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) +{ + struct nix_cn10k_aq_enq_req *aq; + + /* get memory to put this msg */ + aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); + if (!aq) + return -enomem; + + aq->sq.cq = pfvf->hw.rx_queues + qidx; + aq->sq.max_sqe_size = nix_maxsqesz_w16; /* 128 byte */ + aq->sq.cq_ena = 1; + aq->sq.ena = 1; + /* only one smq is allocated, map all sq's to that smq */ + aq->sq.smq = pfvf->hw.txschq_list[nix_txsch_lvl_smq][0]; + /* fixme: set based on nix_af_dwrr_rpm_mtu*/ + aq->sq.smq_rr_weight = otx2_max_mtu; + aq->sq.default_chan = pfvf->hw.tx_chan_base; + aq->sq.sqe_stype = nix_stype_stf; /* cache sqb */ + aq->sq.sqb_aura = sqb_aura; + aq->sq.sq_int_ena = nix_sqint_bits; + aq->sq.qint_idx = 0; + /* due pipelining impact minimum 2000 unused sq cqe's + * need to maintain to avoid cq overflow. + */ + aq->sq.cq_limit = ((send_cq_skid * 256) / (pfvf->qset.sqe_cnt)); + + /* fill aq info */ + aq->qidx = qidx; + aq->ctype = nix_aq_ctype_sq; + aq->op = nix_aq_instop_init; + + return otx2_sync_mbox_msg(&pfvf->mbox); +} + +static int otx2_sq_aq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) +{ + struct nix_aq_enq_req *aq; + + /* get memory to put this msg */ + aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); + if (!aq) + return -enomem; + + aq->sq.cq = pfvf->hw.rx_queues + qidx; + aq->sq.max_sqe_size = nix_maxsqesz_w16; /* 128 byte */ + aq->sq.cq_ena = 1; + aq->sq.ena = 1; + /* only one smq is allocated, map all sq's to that smq */ + aq->sq.smq = pfvf->hw.txschq_list[nix_txsch_lvl_smq][0]; + aq->sq.smq_rr_quantum = dflt_rr_qtm; + aq->sq.default_chan = pfvf->hw.tx_chan_base; + aq->sq.sqe_stype = nix_stype_stf; /* cache sqb */ + aq->sq.sqb_aura = sqb_aura; + aq->sq.sq_int_ena = nix_sqint_bits; + aq->sq.qint_idx = 0; + /* due pipelining impact minimum 2000 unused sq cqe's + * need to maintain to avoid cq overflow. + */ + aq->sq.cq_limit = ((send_cq_skid * 256) / (pfvf->qset.sqe_cnt)); + + /* fill aq info */ + aq->qidx = qidx; + aq->ctype = nix_aq_ctype_sq; + aq->op = nix_aq_instop_init; + + return otx2_sync_mbox_msg(&pfvf->mbox); +} + - struct nix_aq_enq_req *aq; - /* get memory to put this msg */ - aq = otx2_mbox_alloc_msg_nix_aq_enq(&pfvf->mbox); - if (!aq) - return -enomem; - - aq->sq.cq = pfvf->hw.rx_queues + qidx; - aq->sq.max_sqe_size = nix_maxsqesz_w16; /* 128 byte */ - aq->sq.cq_ena = 1; - aq->sq.ena = 1; - /* only one smq is allocated, map all sq's to that smq */ - aq->sq.smq = pfvf->hw.txschq_list[nix_txsch_lvl_smq][0]; - aq->sq.smq_rr_quantum = dflt_rr_qtm; - aq->sq.default_chan = pfvf->hw.tx_chan_base; - aq->sq.sqe_stype = nix_stype_stf; /* cache sqb */ - aq->sq.sqb_aura = sqb_aura; - aq->sq.sq_int_ena = nix_sqint_bits; - aq->sq.qint_idx = 0; - /* due pipelining impact minimum 2000 unused sq cqe's - * need to maintain to avoid cq overflow. - */ - aq->sq.cq_limit = ((send_cq_skid * 256) / (sq->sqe_cnt)); - - /* fill aq info */ - aq->qidx = qidx; - aq->ctype = nix_aq_ctype_sq; - aq->op = nix_aq_instop_init; + if (is_dev_otx2(pfvf->pdev)) + return otx2_sq_aq_init(pfvf, qidx, sqb_aura); + else + return cn10k_sq_aq_init(pfvf, qidx, sqb_aura); - return otx2_sync_mbox_msg(&pfvf->mbox); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_struct.h - u64 rsvd_383_341 : 43; + u64 rsvd_359_341 : 19; + u64 color : 2; + u64 rsvd_383_362 : 22; - u64 rsvd_127_114 : 14; + u64 init_color : 2; + u64 rsvd_127_116 : 12; - u64 rsvd_52_16 : 37; + u64 rsvd_51_16 : 36; + u64 per_lso_seg : 1;
|
Networking
|
d21a857562ad562b6b34fe30ab631088cee9cc68
|
geetha sowjanya
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-pf: cn10k: map lmtst region
|
on cn10k platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. whereas pervious silicon's only support single buffer free at a time. to support the same firmware allocates a dram region for each pf/vf for storing lmtlines. these lmtlines are used for npa batch free and for flushing sqe to the hardware. pf/vf lmtst region is accessed via bar4. pfs lmtst region is followed by its vfs mbox memory. the size of region varies from 2kb to 256kb based on number of lmtlines configured.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 3
| 100
| 4
|
- mapping pf/vf lmtst region. - reserves 0-71 (rx + tx + xdp) lmtst lines for npa batch - reserves 72-512 lmtst lines for nix sqe flush. --- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +#define cn10k_lmtst bit_ull(2) + +#define lmt_line_size 128 +#define nix_lmtid_base 72 /* rx + tx + xdp */ + void __iomem *lmt_base; + u64 *npa_lmt_base; + u64 *nix_lmt_base; + /* lmtst lines info */ + u16 tot_lmt_lines; + u16 nix_lmt_lines; + u32 nix_lmt_size; - if (!is_dev_otx2(pfvf->pdev)) + if (!is_dev_otx2(pfvf->pdev)) { + __set_bit(cn10k_lmtst, &hw->cap_flag); + } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +static int cn10k_lmtst_init(struct otx2_nic *pf) +{ + int size, num_lines; + u64 base; + + if (!test_bit(cn10k_lmtst, &pf->hw.cap_flag)) + return 0; + + base = pci_resource_start(pf->pdev, pci_mbox_bar_num) + + (mbox_size * (pf->total_vfs + 1)); + + size = pci_resource_len(pf->pdev, pci_mbox_bar_num) - + (mbox_size * (pf->total_vfs + 1)); + + pf->hw.lmt_base = ioremap(base, size); + + if (!pf->hw.lmt_base) { + dev_err(pf->dev, "unable to map pf lmtst region "); + return -enomem; + } + + /* fixme: get the num of lmtst lines from lmt table */ + pf->tot_lmt_lines = size / lmt_line_size; + num_lines = (pf->tot_lmt_lines - nix_lmtid_base) / + pf->hw.tx_queues; + /* number of lmt lines per sq queues */ + pf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; + + pf->nix_lmt_size = pf->nix_lmt_lines * lmt_line_size; + + return 0; +} + + if (test_bit(cn10k_lmtst, &pf->hw.cap_flag)) { + /* reserve lmt lines for npa aura batch free */ + pf->hw.npa_lmt_base = (__force u64 *)pf->hw.lmt_base; + /* reserve lmt lines for nix tx */ + pf->hw.nix_lmt_base = (__force u64 *)((u64)pf->hw.npa_lmt_base + + (nix_lmtid_base * lmt_line_size)); + } + + otx2_setup_dev_hw_settings(pf); + - otx2_setup_dev_hw_settings(pf); + err = cn10k_lmtst_init(pf); + if (err) + goto err_detach_rsrc; + if (hw->lmt_base) + iounmap(hw->lmt_base); + if (pf->hw.lmt_base) + iounmap(pf->hw.lmt_base); + diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +static int cn10k_lmtst_init(struct otx2_nic *vf) +{ + int size, num_lines; + + if (!test_bit(cn10k_lmtst, &vf->hw.cap_flag)) + return 0; + + size = pci_resource_len(vf->pdev, pci_mbox_bar_num); + vf->hw.lmt_base = ioremap_wc(pci_resource_start(vf->pdev, + pci_mbox_bar_num), + size); + if (!vf->hw.lmt_base) { + dev_err(vf->dev, "unable to map vf lmtst region "); + return -enomem; + } + + vf->tot_lmt_lines = size / lmt_line_size; + /* lmtst lines per sq */ + num_lines = (vf->tot_lmt_lines - nix_lmtid_base) / + vf->hw.tx_queues; + vf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; + vf->nix_lmt_size = vf->nix_lmt_lines * lmt_line_size; + return 0; +} + + otx2_setup_dev_hw_settings(vf); - otx2_setup_dev_hw_settings(vf); + err = cn10k_lmtst_init(vf); + if (err) + goto err_detach_rsrc; + if (hw->lmt_base) + iounmap(hw->lmt_base); - + + if (vf->hw.lmt_base) + iounmap(vf->hw.lmt_base); +
|
Networking
|
6e8ad4387da5760f0737ec21452624f653272ed9
|
geetha sowjanya
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-pf: cn10k: use lmtst lines for npa/nix operations
|
this patch adds support to use new lmtst lines for npa batch free and burst sqe flush. adds new dev_hw_ops structure to hold platform specific functions and create new files cn10k.c and cn10k.h.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c', 'makefile']
| 11
| 336
| 135
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/makefile b/drivers/net/ethernet/marvell/octeontx2/nic/makefile --- a/drivers/net/ethernet/marvell/octeontx2/nic/makefile +++ b/drivers/net/ethernet/marvell/octeontx2/nic/makefile - otx2_ptp.o otx2_flows.o + otx2_ptp.o otx2_flows.o cn10k.o diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx2 rvu physcial function ethernet driver + * + * copyright (c) 2020 marvell. + */ + +#include "cn10k.h" +#include "otx2_reg.h" +#include "otx2_struct.h" + +static struct dev_hw_ops otx2_hw_ops = { + .sq_aq_init = otx2_sq_aq_init, + .sqe_flush = otx2_sqe_flush, + .aura_freeptr = otx2_aura_freeptr, + .refill_pool_ptrs = otx2_refill_pool_ptrs, +}; + +static struct dev_hw_ops cn10k_hw_ops = { + .sq_aq_init = cn10k_sq_aq_init, + .sqe_flush = cn10k_sqe_flush, + .aura_freeptr = cn10k_aura_freeptr, + .refill_pool_ptrs = cn10k_refill_pool_ptrs, +}; + +int cn10k_pf_lmtst_init(struct otx2_nic *pf) +{ + int size, num_lines; + u64 base; + + if (!test_bit(cn10k_lmtst, &pf->hw.cap_flag)) { + pf->hw_ops = &otx2_hw_ops; + return 0; + } + + pf->hw_ops = &cn10k_hw_ops; + base = pci_resource_start(pf->pdev, pci_mbox_bar_num) + + (mbox_size * (pf->total_vfs + 1)); + + size = pci_resource_len(pf->pdev, pci_mbox_bar_num) - + (mbox_size * (pf->total_vfs + 1)); + + pf->hw.lmt_base = ioremap(base, size); + + if (!pf->hw.lmt_base) { + dev_err(pf->dev, "unable to map pf lmtst region "); + return -enomem; + } + + /* fixme: get the num of lmtst lines from lmt table */ + pf->tot_lmt_lines = size / lmt_line_size; + num_lines = (pf->tot_lmt_lines - nix_lmtid_base) / + pf->hw.tx_queues; + /* number of lmt lines per sq queues */ + pf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; + + pf->nix_lmt_size = pf->nix_lmt_lines * lmt_line_size; + return 0; +} + +int cn10k_vf_lmtst_init(struct otx2_nic *vf) +{ + int size, num_lines; + + if (!test_bit(cn10k_lmtst, &vf->hw.cap_flag)) { + vf->hw_ops = &otx2_hw_ops; + return 0; + } + + vf->hw_ops = &cn10k_hw_ops; + size = pci_resource_len(vf->pdev, pci_mbox_bar_num); + vf->hw.lmt_base = ioremap_wc(pci_resource_start(vf->pdev, + pci_mbox_bar_num), + size); + if (!vf->hw.lmt_base) { + dev_err(vf->dev, "unable to map vf lmtst region "); + return -enomem; + } + + vf->tot_lmt_lines = size / lmt_line_size; + /* lmtst lines per sq */ + num_lines = (vf->tot_lmt_lines - nix_lmtid_base) / + vf->hw.tx_queues; + vf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; + vf->nix_lmt_size = vf->nix_lmt_lines * lmt_line_size; + return 0; +} +export_symbol(cn10k_vf_lmtst_init); + +int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) +{ + struct nix_cn10k_aq_enq_req *aq; + struct otx2_nic *pfvf = dev; + struct otx2_snd_queue *sq; + + sq = &pfvf->qset.sq[qidx]; + sq->lmt_addr = (__force u64 *)((u64)pfvf->hw.nix_lmt_base + + (qidx * pfvf->nix_lmt_size)); + + /* get memory to put this msg */ + aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); + if (!aq) + return -enomem; + + aq->sq.cq = pfvf->hw.rx_queues + qidx; + aq->sq.max_sqe_size = nix_maxsqesz_w16; /* 128 byte */ + aq->sq.cq_ena = 1; + aq->sq.ena = 1; + /* only one smq is allocated, map all sq's to that smq */ + aq->sq.smq = pfvf->hw.txschq_list[nix_txsch_lvl_smq][0]; + /* fixme: set based on nix_af_dwrr_rpm_mtu*/ + aq->sq.smq_rr_weight = otx2_max_mtu; + aq->sq.default_chan = pfvf->hw.tx_chan_base; + aq->sq.sqe_stype = nix_stype_stf; /* cache sqb */ + aq->sq.sqb_aura = sqb_aura; + aq->sq.sq_int_ena = nix_sqint_bits; + aq->sq.qint_idx = 0; + /* due pipelining impact minimum 2000 unused sq cqe's + * need to maintain to avoid cq overflow. + */ + aq->sq.cq_limit = ((send_cq_skid * 256) / (pfvf->qset.sqe_cnt)); + + /* fill aq info */ + aq->qidx = qidx; + aq->ctype = nix_aq_ctype_sq; + aq->op = nix_aq_instop_init; + + return otx2_sync_mbox_msg(&pfvf->mbox); +} + +#define npa_max_burst 16 +void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) +{ + struct otx2_nic *pfvf = dev; + u64 ptrs[npa_max_burst]; + int num_ptrs = 1; + dma_addr_t bufptr; + + /* refill pool with new buffers */ + while (cq->pool_ptrs) { + if (otx2_alloc_buffer(pfvf, cq, &bufptr)) { + if (num_ptrs--) + __cn10k_aura_freeptr(pfvf, cq->cq_idx, ptrs, + num_ptrs, + cq->rbpool->lmt_addr); + break; + } + cq->pool_ptrs--; + ptrs[num_ptrs] = (u64)bufptr + otx2_head_room; + num_ptrs++; + if (num_ptrs == npa_max_burst || cq->pool_ptrs == 0) { + __cn10k_aura_freeptr(pfvf, cq->cq_idx, ptrs, + num_ptrs, + cq->rbpool->lmt_addr); + num_ptrs = 1; + } + } +} + +void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx) +{ + struct otx2_nic *pfvf = dev; + int lmt_id = nix_lmtid_base + (qidx * pfvf->nix_lmt_lines); + u64 val = 0, tar_addr = 0; + + /* fixme: val[0:10] lmt_id. + * [12:15] no of lmtst - 1 in the burst. + * [19:63] data size of each lmtst in the burst except first. + */ + val = (lmt_id & 0x7ff); + /* target address for lmtst flush tells hw how many 128bit + * words are present. + * tar_addr[6:4] size of first lmtst - 1 in units of 128b. + */ + tar_addr |= sq->io_addr | (((size / 16) - 1) & 0x7) << 4; + dma_wmb(); + memcpy(sq->lmt_addr, sq->sqe_base, size); + cn10k_lmt_flush(val, tar_addr); + + sq->head++; + sq->head &= (sq->sqe_cnt - 1); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h +/* spdx-license-identifier: gpl-2.0 + * marvell octeontx2 rvu ethernet driver + * + * copyright (c) 2020 marvell. + */ + +#ifndef cn10k_h +#define cn10k_h + +#include "otx2_common.h" + +void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); +void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx); +int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); +int cn10k_pf_lmtst_init(struct otx2_nic *pf); +int cn10k_vf_lmtst_init(struct otx2_nic *vf); +#endif /* cn10k_h */ diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +#include "cn10k.h" +int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, + dma_addr_t *dma) +{ + if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, dma))) { + struct refill_work *work; + struct delayed_work *dwork; + + work = &pfvf->refill_wrk[cq->cq_idx]; + dwork = &work->pool_refill_work; + /* schedule a task if no other task is running */ + if (!cq->refill_task_sched) { + cq->refill_task_sched = true; + schedule_delayed_work(dwork, + msecs_to_jiffies(100)); + } + return -enomem; + } + return 0; +} + -/* send skid of 2000 packets required for cq size of 4k cqes. */ -#define send_cq_skid 2000 - -static int cn10k_sq_aq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) -{ - struct nix_cn10k_aq_enq_req *aq; - - /* get memory to put this msg */ - aq = otx2_mbox_alloc_msg_nix_cn10k_aq_enq(&pfvf->mbox); - if (!aq) - return -enomem; - - aq->sq.cq = pfvf->hw.rx_queues + qidx; - aq->sq.max_sqe_size = nix_maxsqesz_w16; /* 128 byte */ - aq->sq.cq_ena = 1; - aq->sq.ena = 1; - /* only one smq is allocated, map all sq's to that smq */ - aq->sq.smq = pfvf->hw.txschq_list[nix_txsch_lvl_smq][0]; - /* fixme: set based on nix_af_dwrr_rpm_mtu*/ - aq->sq.smq_rr_weight = otx2_max_mtu; - aq->sq.default_chan = pfvf->hw.tx_chan_base; - aq->sq.sqe_stype = nix_stype_stf; /* cache sqb */ - aq->sq.sqb_aura = sqb_aura; - aq->sq.sq_int_ena = nix_sqint_bits; - aq->sq.qint_idx = 0; - /* due pipelining impact minimum 2000 unused sq cqe's - * need to maintain to avoid cq overflow. - */ - aq->sq.cq_limit = ((send_cq_skid * 256) / (pfvf->qset.sqe_cnt)); - - /* fill aq info */ - aq->qidx = qidx; - aq->ctype = nix_aq_ctype_sq; - aq->op = nix_aq_instop_init; - - return otx2_sync_mbox_msg(&pfvf->mbox); -} - -static int otx2_sq_aq_init(struct otx2_nic *pfvf, u16 qidx, u16 sqb_aura) +int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura) + struct otx2_nic *pfvf = dev; + struct otx2_snd_queue *sq; + sq = &pfvf->qset.sq[qidx]; + sq->lmt_addr = (__force u64 *)(pfvf->reg_base + lmt_lf_lmtlinex(qidx)); - sq->lmt_addr = (__force u64 *)(pfvf->reg_base + lmt_lf_lmtlinex(qidx)); - if (is_dev_otx2(pfvf->pdev)) - return otx2_sq_aq_init(pfvf, qidx, sqb_aura); - else - return cn10k_sq_aq_init(pfvf, qidx, sqb_aura); + return pfvf->hw_ops->sq_aq_init(pfvf, qidx, sqb_aura); - otx2_aura_freeptr(pfvf, qidx, bufptr + otx2_head_room); + pfvf->hw_ops->aura_freeptr(pfvf, qidx, bufptr + otx2_head_room); + /* set lmtst addr for npa batch free */ + if (test_bit(cn10k_lmtst, &pfvf->hw.cap_flag)) + pool->lmt_addr = (__force u64 *)((u64)pfvf->hw.npa_lmt_base + + (pool_id * lmt_line_size)); + - otx2_aura_freeptr(pfvf, pool_id, bufptr); + pfvf->hw_ops->aura_freeptr(pfvf, pool_id, bufptr); - otx2_aura_freeptr(pfvf, pool_id, - bufptr + otx2_head_room); + pfvf->hw_ops->aura_freeptr(pfvf, pool_id, + bufptr + otx2_head_room); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +/* send skid of 2000 packets required for cq size of 4k cqes. */ +#define send_cq_skid 2000 + +struct dev_hw_ops { + int (*sq_aq_init)(void *dev, u16 qidx, u16 sqb_aura); + void (*sqe_flush)(void *dev, struct otx2_snd_queue *sq, + int size, int qidx); + void (*refill_pool_ptrs)(void *dev, struct otx2_cq_queue *cq); + void (*aura_freeptr)(void *dev, int aura, u64 buf); +}; + + struct dev_hw_ops *hw_ops; -#define otx2_write128(lo, hi, addr) +#define otx2_write128(lo, hi, addr) writeq((hi) | (lo), addr) +static inline void __cn10k_aura_freeptr(struct otx2_nic *pfvf, u64 aura, + u64 *ptrs, u64 num_ptrs, + u64 *lmt_addr) +{ + u64 size = 0, count_eot = 0; + u64 tar_addr, val = 0; + + tar_addr = (__force u64)otx2_get_regaddr(pfvf, npa_lf_aura_batch_free0); + /* lmtid is same as aura id */ + val = (aura & 0x7ff) | bit_ull(63); + /* set if [127:64] of last 128bit word has a valid pointer */ + count_eot = (num_ptrs % 2) ? 0ull : 1ull; + /* set aura id to free pointer */ + ptrs[0] = (count_eot << 32) | (aura & 0xfffff); + /* target address for lmtst flush tells hw how many 128bit + * words are valid from npa_lf_aura_batch_free0. + * + * tar_addr[6:4] is lmtst size-1 in units of 128b. + */ + if (num_ptrs > 2) { + size = (sizeof(u64) * num_ptrs) / 16; + if (!count_eot) + size++; + tar_addr |= ((size - 1) & 0x7) << 4; + } + memcpy(lmt_addr, ptrs, sizeof(u64) * num_ptrs); + /* perform lmtst flush */ + cn10k_lmt_flush(val, tar_addr); +} + +static inline void cn10k_aura_freeptr(void *dev, int aura, u64 buf) +{ + struct otx2_nic *pfvf = dev; + struct otx2_pool *pool; + u64 ptrs[2]; + + pool = &pfvf->qset.pool[aura]; + ptrs[1] = buf; + __cn10k_aura_freeptr(pfvf, aura, ptrs, 2, pool->lmt_addr); +} + -static inline void otx2_aura_freeptr(struct otx2_nic *pfvf, - int aura, u64 buf) +static inline void otx2_aura_freeptr(void *dev, int aura, u64 buf) - otx2_write128(buf, (u64)aura | bit_ull(63), - otx2_get_regaddr(pfvf, npa_lf_aura_op_free0)); + struct otx2_nic *pfvf = dev; + void __iomem *addr = otx2_get_regaddr(pfvf, npa_lf_aura_op_free0); + + otx2_write128(buf, (u64)aura | bit_ull(63), addr); +int otx2_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); +int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura); +int otx2_alloc_buffer(struct otx2_nic *pfvf, struct otx2_cq_queue *cq, + dma_addr_t *dma); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +#include "cn10k.h" -static int cn10k_lmtst_init(struct otx2_nic *pf) -{ - int size, num_lines; - u64 base; - - if (!test_bit(cn10k_lmtst, &pf->hw.cap_flag)) - return 0; - - base = pci_resource_start(pf->pdev, pci_mbox_bar_num) + - (mbox_size * (pf->total_vfs + 1)); - - size = pci_resource_len(pf->pdev, pci_mbox_bar_num) - - (mbox_size * (pf->total_vfs + 1)); - - pf->hw.lmt_base = ioremap(base, size); - - if (!pf->hw.lmt_base) { - dev_err(pf->dev, "unable to map pf lmtst region "); - return -enomem; - } - - /* fixme: get the num of lmtst lines from lmt table */ - pf->tot_lmt_lines = size / lmt_line_size; - num_lines = (pf->tot_lmt_lines - nix_lmtid_base) / - pf->hw.tx_queues; - /* number of lmt lines per sq queues */ - pf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; - - pf->nix_lmt_size = pf->nix_lmt_lines * lmt_line_size; - - return 0; -} - - err = cn10k_lmtst_init(pf); + err = cn10k_pf_lmtst_init(pf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_reg.h +#define npa_lf_aura_batch_free0 (npa_lfbase | 0x400) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +#include "cn10k.h" - otx2_aura_freeptr(pfvf, qidx, *seg_addr & ~0x07ull); + pfvf->hw_ops->aura_freeptr(pfvf, qidx, + *seg_addr & ~0x07ull); - dma_addr_t bufptr; - + pfvf->hw_ops->refill_pool_ptrs(pfvf, cq); + + return processed_cqe; +} + +void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq) +{ + struct otx2_nic *pfvf = dev; + dma_addr_t bufptr; + - if (unlikely(__otx2_alloc_rbuf(pfvf, cq->rbpool, &bufptr))) { - struct refill_work *work; - struct delayed_work *dwork; - - work = &pfvf->refill_wrk[cq->cq_idx]; - dwork = &work->pool_refill_work; - /* schedule a task if no other task is running */ - if (!cq->refill_task_sched) { - cq->refill_task_sched = true; - schedule_delayed_work(dwork, - msecs_to_jiffies(100)); - } + if (otx2_alloc_buffer(pfvf, cq, &bufptr)) - } - - return processed_cqe; -static void otx2_sqe_flush(struct otx2_snd_queue *sq, int size) +void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, + int size, int qidx) - otx2_sqe_flush(sq, offset); + pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); - otx2_sqe_flush(sq, offset); + pfvf->hw_ops->sqe_flush(pfvf, sq, offset, qidx); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h + u64 *lmt_addr; +void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, + int size, int qidx); +void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq, + int size, int qidx); +void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); +void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +#include "cn10k.h" -static int cn10k_lmtst_init(struct otx2_nic *vf) -{ - int size, num_lines; - - if (!test_bit(cn10k_lmtst, &vf->hw.cap_flag)) - return 0; - - size = pci_resource_len(vf->pdev, pci_mbox_bar_num); - vf->hw.lmt_base = ioremap_wc(pci_resource_start(vf->pdev, - pci_mbox_bar_num), - size); - if (!vf->hw.lmt_base) { - dev_err(vf->dev, "unable to map vf lmtst region "); - return -enomem; - } - - vf->tot_lmt_lines = size / lmt_line_size; - /* lmtst lines per sq */ - num_lines = (vf->tot_lmt_lines - nix_lmtid_base) / - vf->hw.tx_queues; - vf->nix_lmt_lines = num_lines > 32 ? 32 : num_lines; - vf->nix_lmt_size = vf->nix_lmt_lines * lmt_line_size; - return 0; -} - - err = cn10k_lmtst_init(vf); + err = cn10k_vf_lmtst_init(vf); diff --git a/include/linux/soc/marvell/octeontx2/asm.h b/include/linux/soc/marvell/octeontx2/asm.h --- a/include/linux/soc/marvell/octeontx2/asm.h +++ b/include/linux/soc/marvell/octeontx2/asm.h +#define cn10k_lmt_flush(val, addr) \ +({ \ + __asm__ volatile(".cpu generic+lse " \ + "steor %x[rf],[%[rs]]" \ + : [rf]"+r"(val) \ + : [rs]"r"(addr)); \ +}) +#define cn10k_lmt_flush(val, addr) ({ addr = val; })
|
Networking
|
4c236d5dc8b86222dc155cd68e7934624264150f
|
geetha sowjanya
|
include
|
linux
|
ethernet, marvell, nic, octeontx2, soc
|
octeontx2-af: cn10k: add rpm mac support
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octeontx2's next gen platform the cn10k has rpm mac which has a different serdes when compared to cgx mac. though the underlying hw is different, the csr interface has been designed largely inline with cgx mac, with few exceptions though. so we are using the same cgx driver for rpm mac as well and will have a different set of apis for rpm where ever necessary.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add marvell cn10k support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['octeontx2-af ']
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['h', 'maintainers', 'c', 'makefile']
| 12
| 479
| 106
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--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +m: hariprasad <hkelam@marvell.com> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/makefile b/drivers/net/ethernet/marvell/octeontx2/af/makefile --- a/drivers/net/ethernet/marvell/octeontx2/af/makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/makefile - rvu_cpt.o rvu_devlink.o + rvu_cpt.o rvu_devlink.o rpm.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +#include "rvu.h" +#include "lmac_common.h" -#define drv_name "octeontx2-cgx" -#define drv_string "marvell octeontx2 cgx/mac driver" - -/** - * struct lmac - * @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion - * @cmd_lock: lock to serialize the command interface - * @resp: command response - * @link_info: link related information - * @event_cb: callback for linkchange events - * @event_cb_lock: lock for serializing callback with unregister - * @cmd_pend: flag set before new command is started - * flag cleared after command response is received - * @cgx: parent cgx port - * @lmac_id: lmac port id - * @name: lmac port name - */ -struct lmac { - wait_queue_head_t wq_cmd_cmplt; - struct mutex cmd_lock; - u64 resp; - struct cgx_link_user_info link_info; - struct cgx_event_cb event_cb; - spinlock_t event_cb_lock; - bool cmd_pend; - struct cgx *cgx; - u8 lmac_id; - char *name; -}; - -struct cgx { - void __iomem *reg_base; - struct pci_dev *pdev; - u8 cgx_id; - u8 lmac_count; - struct lmac *lmac_idmap[max_lmac_per_cgx]; - struct work_struct cgx_cmd_work; - struct workqueue_struct *cgx_cmd_workq; - struct list_head cgx_list; -}; +#define drv_name "marvell-cgx/rpm" +#define drv_string "marvell cgx/rpm driver" + { pci_device(pci_vendor_id_cavium, pci_devid_cn10k_rpm) }, -static void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) +static bool is_dev_rpm(void *cgxd) - writeq(val, cgx->reg_base + (lmac << 18) + offset); + struct cgx *cgx = cgxd; + + return (cgx->pdev->device == pci_devid_cn10k_rpm); +} + +bool is_lmac_valid(struct cgx *cgx, int lmac_id) +{ + return cgx && test_bit(lmac_id, &cgx->lmac_bmap); -static u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) +struct mac_ops *get_mac_ops(void *cgxd) - return readq(cgx->reg_base + (lmac << 18) + offset); + if (!cgxd) + return cgxd; + + return ((struct cgx *)cgxd)->mac_ops; -static inline struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) +void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val) +{ + writeq(val, cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + + offset); +} + +u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset) +{ + return readq(cgx->reg_base + (lmac << cgx->mac_ops->lmac_offset) + + offset); +} + +struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx) + struct mac_ops *mac_ops; + mac_ops = cgx_dev->mac_ops; + struct mac_ops *mac_ops; + mac_ops = cgx_dev->mac_ops; + - if (!cgx || lmac_id >= cgx->lmac_count) + if (!is_lmac_valid(cgx, lmac_id)) - if (!cgx || lmac_id >= cgx->lmac_count) + if (!is_lmac_valid(cgx, lmac_id)) + struct mac_ops *mac_ops; + mac_ops = cgx->mac_ops; + if (is_dev_rpm(cgx)) + return; + + struct mac_ops *mac_ops; - if (!cgx || lmac_id >= cgx->lmac_count) + mac_ops = cgx->mac_ops; + if (!is_lmac_valid(cgx, lmac_id)) + struct mac_ops *mac_ops; - if (!cgx || lmac_id >= cgx->lmac_count) + mac_ops = cgx->mac_ops; + if (!is_lmac_valid(cgx, lmac_id)) +u64 cgx_features_get(void *cgxd) +{ + return ((struct cgx *)cgxd)->hw_features; +} + - if (!cgx || lmac_id >= cgx->lmac_count) + if (!is_lmac_valid(cgx, lmac_id)) - if (!cgx || lmac_id >= cgx->lmac_count) + if (!is_lmac_valid(cgx, lmac_id)) - if (!cgx || lmac_id >= cgx->lmac_count) + if (is_dev_rpm(cgx)) + return 0; + + if (!is_lmac_valid(cgx, lmac_id)) - if (!cgx || lmac_id >= cgx->lmac_count) + if (is_dev_rpm(cgx)) + return 0; + + if (!is_lmac_valid(cgx, lmac_id)) - if (!cgx || lmac_id >= cgx->lmac_count) + if (is_dev_rpm(cgx)) + return; + + if (!is_lmac_valid(cgx, lmac_id)) + if (is_dev_rpm(cgx)) + return; + -static int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) +int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac) -static inline int cgx_fwi_cmd_generic(u64 req, u64 *resp, - struct cgx *cgx, int lmac_id) +int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id) + u64 event, offset, clear_bit; - u64 event; + /* clear sw_int for rpm and cmr_int for cgx */ + offset = cgx->mac_ops->int_register; + clear_bit = cgx->mac_ops->int_ena_bit; + - cgx_write(lmac->cgx, lmac->lmac_id, cgxx_cmrx_int, fw_cgx_int); + cgx_write(lmac->cgx, lmac->lmac_id, offset, clear_bit); + int first_lmac; + first_lmac = find_first_bit(&cgx->lmac_bmap, max_lmac_per_cgx); - err = cgx_fwi_cmd_generic(req, &resp, cgx, 0); + err = cgx_fwi_cmd_generic(req, &resp, cgx, first_lmac); + int first_lmac = find_first_bit(&cgx->lmac_bmap, max_lmac_per_cgx); - return cgx_fwi_cmd_generic(req, resp, cgx, 0); + return cgx_fwi_cmd_generic(req, resp, cgx, first_lmac); - /* do link up for all the lmacs */ - for (i = 0; i < cgx->lmac_count; i++) { + /* do link up for all the enabled lmacs */ + for_each_set_bit(i, &cgx->lmac_bmap, max_lmac_per_cgx) { +static int cgx_configure_interrupt(struct cgx *cgx, struct lmac *lmac, + int cnt, bool req_free) +{ + struct mac_ops *mac_ops = cgx->mac_ops; + u64 offset, ena_bit; + unsigned int irq; + int err; + + irq = pci_irq_vector(cgx->pdev, mac_ops->lmac_fwi + + cnt * mac_ops->irq_offset); + offset = mac_ops->int_set_reg; + ena_bit = mac_ops->int_ena_bit; + + if (req_free) { + free_irq(irq, lmac); + return 0; + } + + err = request_irq(irq, cgx_fwi_event_handler, 0, lmac->name, lmac); + if (err) + return err; + + /* enable interrupt */ + cgx_write(cgx, lmac->lmac_id, offset, ena_bit); + return 0; +} + +int cgx_get_nr_lmacs(void *cgxd) +{ + struct cgx *cgx = cgxd; + + return cgx_read(cgx, 0, cgxx_cmrx_rx_lmacs) & 0x7ull; +} + +u8 cgx_get_lmacid(void *cgxd, u8 lmac_index) +{ + struct cgx *cgx = cgxd; + + return cgx->lmac_idmap[lmac_index]->lmac_id; +} + +unsigned long cgx_get_lmac_bmap(void *cgxd) +{ + struct cgx *cgx = cgxd; + + return cgx->lmac_bmap; +} + + u64 lmac_list; - cgx->lmac_count = cgx_read(cgx, 0, cgxx_cmrx_rx_lmacs) & 0x7; + cgx->lmac_count = cgx->mac_ops->get_nr_lmacs(cgx); + /* lmac_list specifies which lmacs are enabled + * when bit n is set to 1, lmac[n] is enabled + */ + if (cgx->mac_ops->non_contiguous_serdes_lane) + lmac_list = cgx_read(cgx, 0, cgxx_cmrx_rx_lmacs) & 0xfull; + - lmac->lmac_id = i; + if (cgx->mac_ops->non_contiguous_serdes_lane) { + lmac->lmac_id = __ffs64(lmac_list); + lmac_list &= ~bit_ull(lmac->lmac_id); + } else { + lmac->lmac_id = i; + } + - err = request_irq(pci_irq_vector(cgx->pdev, - cgx_lmac_fwi + i * 9), - cgx_fwi_event_handler, 0, lmac->name, lmac); + err = cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, false); - /* enable interrupt */ - cgx_write(cgx, lmac->lmac_id, cgxx_cmrx_int_ena_w1s, - fw_cgx_int); - - cgx->lmac_idmap[i] = lmac; - cgx_lmac_pause_frm_config(cgx, i, true); + cgx->lmac_idmap[lmac->lmac_id] = lmac; + cgx_lmac_pause_frm_config(cgx, lmac->lmac_id, true); + set_bit(lmac->lmac_id, &cgx->lmac_bmap); - for (i = 0; i < cgx->lmac_count; i++) { - cgx_lmac_pause_frm_config(cgx, i, false); + for_each_set_bit(i, &cgx->lmac_bmap, max_lmac_per_cgx) { - free_irq(pci_irq_vector(cgx->pdev, cgx_lmac_fwi + i * 9), lmac); + cgx_lmac_pause_frm_config(cgx, lmac->lmac_id, false); + cgx_configure_interrupt(cgx, lmac, lmac->lmac_id, true); +static void cgx_populate_features(struct cgx *cgx) +{ + if (is_dev_rpm(cgx)) + cgx->hw_features = rvu_mac_rpm; + else + cgx->hw_features = (rvu_lmac_feat_fc | rvu_lmac_feat_ptp); +} + +static struct mac_ops cgx_mac_ops = { + .name = "cgx", + .csr_offset = 0, + .lmac_offset = 18, + .int_register = cgxx_cmrx_int, + .int_set_reg = cgxx_cmrx_int_ena_w1s, + .irq_offset = 9, + .int_ena_bit = fw_cgx_int, + .lmac_fwi = cgx_lmac_fwi, + .non_contiguous_serdes_lane = false, + .get_nr_lmacs = cgx_get_nr_lmacs, +}; + + /* use mac_ops to get mac specific features */ + if (pdev->device == pci_devid_cn10k_rpm) + cgx->mac_ops = rpm_get_mac_ops(); + else + cgx->mac_ops = &cgx_mac_ops; + - nvec = cgx_nvec; + nvec = pci_msix_vec_count(cgx->pdev); + cgx_populate_features(cgx); + - cgx_lmac_exit(cgx); - list_del(&cgx->cgx_list); + if (cgx) { + cgx_lmac_exit(cgx); + list_del(&cgx->cgx_list); + } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +#include "rpm.h" -#define cgxx_cmrx_rx_stat0 0x070 +#define cgxx_cmrx_rx_stat0 (0x070 + mac_ops->csr_offset) -#define cgxx_cmrx_rx_dmac_ctl0 0x1f8 +#define cgxx_cmrx_rx_dmac_ctl0 (0x1f8 + mac_ops->csr_offset) -#define cgxx_cmrx_rx_dmac_cam0 0x200 +#define cgxx_cmrx_rx_dmac_cam0 (0x200 + mac_ops->csr_offset) -#define cgxx_cmrx_tx_stat0 0x700 +#define cgxx_cmrx_tx_stat0 (0x700 + mac_ops->csr_offset) -#define cgx_nvec 37 - +u64 cgx_features_get(void *cgxd); +struct mac_ops *get_mac_ops(void *cgxd); +int cgx_get_nr_lmacs(void *cgxd); +u8 cgx_get_lmacid(void *cgxd, u8 lmac_index); +unsigned long cgx_get_lmac_bmap(void *cgxd); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h +/* spdx-license-identifier: gpl-2.0 */ +/* marvell octeontx2 rpm driver + * + * copyright (c) 2020 marvell. + */ + +#ifndef lmac_common_h +#define lmac_common_h + +#include "rvu.h" +#include "cgx.h" +/** + * struct lmac + * @wq_cmd_cmplt: waitq to keep the process blocked until cmd completion + * @cmd_lock: lock to serialize the command interface + * @resp: command response + * @link_info: link related information + * @event_cb: callback for linkchange events + * @event_cb_lock: lock for serializing callback with unregister + * @cmd_pend: flag set before new command is started + * flag cleared after command response is received + * @cgx: parent cgx port + * @lmac_id: lmac port id + * @name: lmac port name + */ +struct lmac { + wait_queue_head_t wq_cmd_cmplt; + /* lock to serialize the command interface */ + struct mutex cmd_lock; + u64 resp; + struct cgx_link_user_info link_info; + struct cgx_event_cb event_cb; + /* lock for serializing callback with unregister */ + spinlock_t event_cb_lock; + bool cmd_pend; + struct cgx *cgx; + u8 lmac_id; + char *name; +}; + +/* cgx & rpm has different feature set + * update the structure fields with different one + */ +struct mac_ops { + char *name; + /* features like rxstat, txstat, dmac filter csrs differs by fixed + * bar offset for example + * cgx dmac_ctl0 0x1f8 + * rpm dmac_ctl0 0x4ff8 + */ + u64 csr_offset; + /* for atf to send events to kernel, there is no dedicated interrupt + * defined hence cgx uses overflow bit in cmr_int. rpm block supports + * sw_int so that atf triggers this interrupt after processing of + * requested command + */ + u64 int_register; + u64 int_set_reg; + /* lmac offset is different is rpm */ + u8 lmac_offset; + u8 irq_offset; + u8 int_ena_bit; + u8 lmac_fwi; + bool non_contiguous_serdes_lane; + /* incase of rpm get number of lmacs from rpmx_cmr_rx_lmacs[lmac_exist] + * number of setbits in lmac_exist tells number of lmacs + */ + int (*get_nr_lmacs)(void *cgx); +}; + +struct cgx { + void __iomem *reg_base; + struct pci_dev *pdev; + u8 cgx_id; + u8 lmac_count; + struct lmac *lmac_idmap[max_lmac_per_cgx]; + struct work_struct cgx_cmd_work; + struct workqueue_struct *cgx_cmd_workq; + struct list_head cgx_list; + u64 hw_features; + struct mac_ops *mac_ops; + unsigned long lmac_bmap; /* bitmap of enabled lmacs */ +}; + +typedef struct cgx rpm_t; + +/* function declarations */ +void cgx_write(struct cgx *cgx, u64 lmac, u64 offset, u64 val); +u64 cgx_read(struct cgx *cgx, u64 lmac, u64 offset); +struct lmac *lmac_pdata(u8 lmac_id, struct cgx *cgx); +int cgx_fwi_cmd_send(u64 req, u64 *resp, struct lmac *lmac); +int cgx_fwi_cmd_generic(u64 req, u64 *resp, struct cgx *cgx, int lmac_id); +bool is_lmac_valid(struct cgx *cgx, int lmac_id); +struct mac_ops *rpm_get_mac_ops(void); + +#endif /* lmac_common_h */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +m(cgx_features_get, 0x215, cgx_features_get, msg_req, \ + cgx_features_info_msg) \ -#define cgx_rx_stats_count 13 +#define cgx_rx_stats_count 9 +#define rvu_lmac_feat_fc bit_ull(0) /* pause frames */ +#define rvu_lmac_feat_ptp bit_ull(1) /* precison time protocol */ +#define rvu_mac_version bit_ull(2) +#define rvu_mac_cgx 0 +#define rvu_mac_rpm 1 + +struct cgx_features_info_msg { + struct mbox_msghdr hdr; + u64 lmac_features; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +// spdx-license-identifier: gpl-2.0 +/* marvell octeontx2 rpm driver + * + * copyright (c) 2020 marvell. + * + */ + +#include "cgx.h" +#include "lmac_common.h" + +static struct mac_ops rpm_mac_ops = { + .name = "rpm", + .csr_offset = 0x4e00, + .lmac_offset = 20, + .int_register = rpmx_cmrx_sw_int, + .int_set_reg = rpmx_cmrx_sw_int_ena_w1s, + .irq_offset = 1, + .int_ena_bit = bit_ull(0), + .lmac_fwi = rpm_lmac_fwi, + .non_contiguous_serdes_lane = true, + .get_nr_lmacs = rpm_get_nr_lmacs, +}; + +struct mac_ops *rpm_get_mac_ops(void) +{ + return &rpm_mac_ops; +} + +static u64 rpm_read(rpm_t *rpm, u64 lmac, u64 offset) +{ + return cgx_read(rpm, lmac, offset); +} + +int rpm_get_nr_lmacs(void *rpmd) +{ + rpm_t *rpm = rpmd; + + return hweight8(rpm_read(rpm, 0, cgxx_cmrx_rx_lmacs) & 0xfull); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +/* spdx-license-identifier: gpl-2.0 */ +/* marvell octeontx2 rpm driver + * + * copyright (c) 2020 marvell. + * + */ + +#ifndef rpm_h +#define rpm_h + +/* pci device ids */ +#define pci_devid_cn10k_rpm 0xa060 + +/* registers */ +#define rpmx_cmrx_sw_int 0x180 +#define rpmx_cmrx_sw_int_w1s 0x188 +#define rpmx_cmrx_sw_int_ena_w1s 0x198 + +#define rpm_lmac_fwi 0xa + +/* function declarations */ +int rpm_get_nr_lmacs(void *cgxd); +#endif /* rpm_h */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature) +{ + u8 cgx_id, lmac_id; + void *cgxd; + + if (!is_pf_cgxmapped(rvu, pf)) + return 0; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + cgxd = rvu_cgx_pdata(cgx_id, rvu); + + return (cgx_features_get(cgxd) & feature); +} + - int cgx, lmac_cnt, lmac; + unsigned long lmac_bmap; + int cgx, lmac, iter; - lmac_cnt = cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); - for (lmac = 0; lmac < lmac_cnt; lmac++, pf++) { + lmac_bmap = cgx_get_lmac_bmap(rvu_cgx_pdata(cgx, rvu)); + for_each_set_bit(iter, &lmac_bmap, max_lmac_per_cgx) { + lmac = cgx_get_lmacid(rvu_cgx_pdata(cgx, rvu), + iter); + pf++; - if (err) + if (err) { + kfree(qentry); + } + unsigned long lmac_bmap; - for (lmac = 0; lmac < cgx_get_lmac_cnt(cgxd); lmac++) { + lmac_bmap = cgx_get_lmac_bmap(cgxd); + for_each_set_bit(lmac, &lmac_bmap, max_lmac_per_cgx) { + unsigned long lmac_bmap; - for (lmac = 0; lmac < cgx_get_lmac_cnt(cgxd); lmac++) + lmac_bmap = cgx_get_lmac_bmap(cgxd); + for_each_set_bit(lmac, &lmac_bmap, max_lmac_per_cgx) + if (!is_mac_feature_supported(rvu, pf, rvu_lmac_feat_ptp)) + return 0; + +int rvu_mbox_handler_cgx_features_get(struct rvu *rvu, + struct msg_req *req, + struct cgx_features_info_msg *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_idx, lmac; + void *cgxd; + + if (!is_pf_cgxmapped(rvu, pf)) + return 0; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); + cgxd = rvu_cgx_pdata(cgx_idx, rvu); + rsp->lmac_features = cgx_features_get(cgxd); + + return 0; +} + + if (!is_mac_feature_supported(rvu, pf, rvu_lmac_feat_fc)) + return 0; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +#include "lmac_common.h" + struct mac_ops *mac_ops; + int rvu_def_cgx_id = 0; - seq_puts(filp, "pci dev rvu pf func nix block cgx lmac "); + mac_ops = get_mac_ops(rvu_cgx_pdata(rvu_def_cgx_id, rvu)); + seq_printf(filp, "pci dev rvu pf func nix block %s lmac ", + mac_ops->name); - sprintf(cgx, "cgx%d", cgx_id); + sprintf(cgx, "%s%d", mac_ops->name, cgx_id); + struct mac_ops *mac_ops; + mac_ops = get_mac_ops(cgxd); + + if (!mac_ops) + return 0; + - seq_puts(s, " =======nix rx_stats(cgx port level)====== "); + seq_printf(s, " =======nix rx_stats(%s port level)====== ", + mac_ops->name); - seq_puts(s, " =======nix tx_stats(cgx port level)====== "); + seq_printf(s, " =======nix tx_stats(%s port level)====== ", + mac_ops->name); - seq_puts(s, " =======cgx rx_stats====== "); + seq_printf(s, " =======%s rx_stats====== ", mac_ops->name); - seq_puts(s, " =======cgx tx_stats====== "); + seq_printf(s, " =======%s tx_stats====== ", mac_ops->name); + struct mac_ops *mac_ops; + unsigned long lmac_bmap; + int rvu_def_cgx_id = 0; - rvu->rvu_dbg.cgx_root = debugfs_create_dir("cgx", rvu->rvu_dbg.root); + mac_ops = get_mac_ops(rvu_cgx_pdata(rvu_def_cgx_id, rvu)); + if (!mac_ops) + return; + + rvu->rvu_dbg.cgx_root = debugfs_create_dir(mac_ops->name, + rvu->rvu_dbg.root); + lmac_bmap = cgx_get_lmac_bmap(cgx); - sprintf(dname, "cgx%d", i); + sprintf(dname, "%s%d", mac_ops->name, i); - for (lmac_id = 0; lmac_id < cgx_get_lmac_cnt(cgx); lmac_id++) { + + for_each_set_bit(lmac_id, &lmac_bmap, max_lmac_per_cgx) { - debugfs_create_file("rvu_pf_cgx_map", 0444, rvu->rvu_dbg.root, rvu, - &rvu_dbg_rvu_pf_cgx_map_fops); + if (!cgx_get_cgxcnt_max()) + goto create; + + if (is_rvu_otx2(rvu)) + debugfs_create_file("rvu_pf_cgx_map", 0444, rvu->rvu_dbg.root, + rvu, &rvu_dbg_rvu_pf_cgx_map_fops); + else + debugfs_create_file("rvu_pf_cgx_map", 0444, rvu->rvu_dbg.root, + rvu, &rvu_dbg_rvu_pf_cgx_map_fops); + +create: diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c - int blkaddr; + int blkaddr, pf; + pf = rvu_get_pf(pcifunc); + if (!is_mac_feature_supported(rvu, pf, rvu_lmac_feat_ptp)) + return 0; +
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Networking
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91c6945ea1f9059fea886630d0fd8070740e2aaf
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hariprasad kelam
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drivers
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net
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af, ethernet, marvell, octeontx2
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octeontx2-af: cn10k: add support for programmable channels
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nix uses unique channel numbers to identify the packet sources/sinks like cgx,lbk and sdp. the channel numbers assigned to each block are hardwired in cn9xxx silicon. the fixed channel numbers in cn9xxx are:
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add marvell cn10k support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'maintainers', 'c', 'makefile']
| 12
| 360
| 17
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--- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +m: subbaraya sundeep <sbhatta@marvell.com> diff --git a/drivers/net/ethernet/marvell/octeontx2/af/makefile b/drivers/net/ethernet/marvell/octeontx2/af/makefile --- a/drivers/net/ethernet/marvell/octeontx2/af/makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/makefile - rvu_cpt.o rvu_devlink.o rpm.o + rvu_cpt.o rvu_devlink.o rpm.o rvu_cn10k.o diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val) +{ + struct cgx *cgx_dev = cgx_get_pdata(cgx_id); + + cgx_write(cgx_dev, lmac_id, offset, val); +} + +u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset) +{ + struct cgx *cgx_dev = cgx_get_pdata(cgx_id); + + return cgx_read(cgx_dev, lmac_id, offset); +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val); +u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/net/ethernet/marvell/octeontx2/af/common.h --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h +#define nix_chan_sdp_ch_start (0x700ull) + +#define sdp_channels 256 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +#include <linux/bits.h> + +#define rpmx_cmrx_link_cfg 0x1070 + +#define rpmx_cmrx_link_range_mask genmask_ull(19, 16) +#define rpmx_cmrx_link_base_mask genmask_ull(11, 0) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c + err = rvu_set_channels_base(rvu); + if (err) + goto msix_err; + + rvu_program_channels(rvu); + -#define pci_devid_octeontx2_lbk 0xa061 - diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +#include "rvu_reg.h" +#define pci_devid_octeontx2_lbk 0xa061 + bool programmable_chans; /* channels programmable ? */ + u16 cgx_chan_base; /* cgx base channel number */ + u16 lbk_chan_base; /* lbk base channel number */ + u16 sdp_chan_base; /* sdp base channel number */ + u16 cpt_chan_base; /* cpt base channel number */ + u8 cpt_links; /* number of cpt links */ +static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid, + u8 lmacid, u8 chan) +{ + u64 nix_const = rvu_read64(rvu, blkaddr_nix0, nix_af_const); + u16 cgx_chans = nix_const & 0xffull; + struct rvu_hwinfo *hw = rvu->hw; + + if (!hw->cap.programmable_chans) + return nix_chan_cgx_lmac_chx(cgxid, lmacid, chan); + + return rvu->hw->cgx_chan_base + + (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan; +} + +static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid, + u8 chan) +{ + u64 nix_const = rvu_read64(rvu, blkaddr_nix0, nix_af_const); + u16 lbk_chans = (nix_const >> 16) & 0xffull; + struct rvu_hwinfo *hw = rvu->hw; + + if (!hw->cap.programmable_chans) + return nix_chan_lbk_chx(lbkid, chan); + + return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan; +} + +static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan) +{ + return rvu->hw->cpt_chan_base + chan; +} + +/* cn10k rvu */ +int rvu_set_channels_base(struct rvu *rvu); +void rvu_program_channels(struct rvu *rvu); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c --- /dev/null +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c +// spdx-license-identifier: gpl-2.0 +/* marvell rpm cn10k driver + * + * copyright (c) 2020 marvell. + */ + +#include <linux/bitfield.h> +#include <linux/pci.h> +#include "rvu.h" +#include "cgx.h" +#include "rvu_reg.h" + +int rvu_set_channels_base(struct rvu *rvu) +{ + struct rvu_hwinfo *hw = rvu->hw; + u16 cpt_chan_base; + u64 nix_const; + int blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return blkaddr; + + nix_const = rvu_read64(rvu, blkaddr, nix_af_const); + + hw->cgx = (nix_const >> 12) & 0xfull; + hw->lmac_per_cgx = (nix_const >> 8) & 0xfull; + hw->cgx_links = hw->cgx * hw->lmac_per_cgx; + hw->lbk_links = (nix_const >> 24) & 0xfull; + hw->cpt_links = (nix_const >> 44) & 0xfull; + hw->sdp_links = 1; + + hw->cgx_chan_base = nix_chan_cgx_lmac_chx(0, 0, 0); + hw->lbk_chan_base = nix_chan_lbk_chx(0, 0); + hw->sdp_chan_base = nix_chan_sdp_ch_start; + + /* no programmable channels */ + if (!(nix_const & bit_ull(60))) + return 0; + + hw->cap.programmable_chans = true; + + /* if programmable channels are present then configure + * channels such that all channel numbers are contiguous + * leaving no holes. this way the new cpt channels can be + * accomodated. the order of channel numbers assigned is + * lbk, sdp, cgx and cpt. + */ + hw->sdp_chan_base = hw->lbk_chan_base + hw->lbk_links * + ((nix_const >> 16) & 0xffull); + hw->cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * sdp_channels; + + cpt_chan_base = hw->cgx_chan_base + hw->cgx_links * + (nix_const & 0xffull); + + /* out of 4096 channels start cpt from 2048 so + * that msb for cpt channels is always set + */ + if (cpt_chan_base <= 0x800) { + hw->cpt_chan_base = 0x800; + } else { + dev_err(rvu->dev, + "cpt channels could not fit in the range 2048-4095 "); + return -einval; + } + + return 0; +} + +#define lbk_connect_nixx(a) (0x0 + (a)) + +static void __rvu_lbk_set_chans(struct rvu *rvu, void __iomem *base, + u64 offset, int lbkid, u16 chans) +{ + struct rvu_hwinfo *hw = rvu->hw; + u64 cfg; + + cfg = readq(base + offset); + cfg &= ~(lbk_link_cfg_range_mask | + lbk_link_cfg_id_mask | lbk_link_cfg_base_mask); + cfg |= field_prep(lbk_link_cfg_range_mask, ilog2(chans)); + cfg |= field_prep(lbk_link_cfg_id_mask, lbkid); + cfg |= field_prep(lbk_link_cfg_base_mask, hw->lbk_chan_base); + + writeq(cfg, base + offset); +} + +static void rvu_lbk_set_channels(struct rvu *rvu) +{ + struct pci_dev *pdev = null; + void __iomem *base; + u64 lbk_const; + u8 src, dst; + u16 chans; + + /* to loopback packets between multiple nix blocks + * mutliple lbk blocks are needed. with two nix blocks, + * four lbk blocks are needed and each lbk block + * source and destination are as follows: + * lbk0 - source nix0 and destination nix1 + * lbk1 - source nix0 and destination nix1 + * lbk2 - source nix1 and destination nix0 + * lbk3 - source nix1 and destination nix1 + * as per the hrm channel numbers should be programmed as: + * p2x and x2p of lbk0 as same + * p2x and x2p of lbk3 as same + * p2x of lbk1 and x2p of lbk2 as same + * p2x of lbk2 and x2p of lbk1 as same + */ + while (true) { + pdev = pci_get_device(pci_vendor_id_cavium, + pci_devid_octeontx2_lbk, pdev); + if (!pdev) + return; + + base = pci_ioremap_bar(pdev, 0); + if (!base) + goto err_put; + + lbk_const = readq(base + lbk_const); + chans = field_get(lbk_const_chans, lbk_const); + dst = field_get(lbk_const_dst, lbk_const); + src = field_get(lbk_const_src, lbk_const); + + if (src == dst) { + if (src == lbk_connect_nixx(0)) { /* lbk0 */ + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_x2p, + 0, chans); + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_p2x, + 0, chans); + } else if (src == lbk_connect_nixx(1)) { /* lbk3 */ + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_x2p, + 1, chans); + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_p2x, + 1, chans); + } + } else { + if (src == lbk_connect_nixx(0)) { /* lbk1 */ + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_x2p, + 0, chans); + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_p2x, + 1, chans); + } else if (src == lbk_connect_nixx(1)) { /* lbk2 */ + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_x2p, + 1, chans); + __rvu_lbk_set_chans(rvu, base, lbk_link_cfg_p2x, + 0, chans); + } + } + iounmap(base); + } +err_put: + pci_dev_put(pdev); +} + +static void __rvu_nix_set_channels(struct rvu *rvu, int blkaddr) +{ + u64 nix_const = rvu_read64(rvu, blkaddr, nix_af_const); + u16 cgx_chans, lbk_chans, sdp_chans, cpt_chans; + struct rvu_hwinfo *hw = rvu->hw; + int link, nix_link = 0; + u16 start; + u64 cfg; + + cgx_chans = nix_const & 0xffull; + lbk_chans = (nix_const >> 16) & 0xffull; + sdp_chans = sdp_channels; + cpt_chans = (nix_const >> 32) & 0xfffull; + + start = hw->cgx_chan_base; + for (link = 0; link < hw->cgx_links; link++, nix_link++) { + cfg = rvu_read64(rvu, blkaddr, nix_af_linkx_cfg(nix_link)); + cfg &= ~(nix_af_linkx_base_mask | nix_af_linkx_range_mask); + cfg |= field_prep(nix_af_linkx_range_mask, ilog2(cgx_chans)); + cfg |= field_prep(nix_af_linkx_base_mask, start); + rvu_write64(rvu, blkaddr, nix_af_linkx_cfg(nix_link), cfg); + start += cgx_chans; + } + + start = hw->lbk_chan_base; + for (link = 0; link < hw->lbk_links; link++, nix_link++) { + cfg = rvu_read64(rvu, blkaddr, nix_af_linkx_cfg(nix_link)); + cfg &= ~(nix_af_linkx_base_mask | nix_af_linkx_range_mask); + cfg |= field_prep(nix_af_linkx_range_mask, ilog2(lbk_chans)); + cfg |= field_prep(nix_af_linkx_base_mask, start); + rvu_write64(rvu, blkaddr, nix_af_linkx_cfg(nix_link), cfg); + start += lbk_chans; + } + + start = hw->sdp_chan_base; + for (link = 0; link < hw->sdp_links; link++, nix_link++) { + cfg = rvu_read64(rvu, blkaddr, nix_af_linkx_cfg(nix_link)); + cfg &= ~(nix_af_linkx_base_mask | nix_af_linkx_range_mask); + cfg |= field_prep(nix_af_linkx_range_mask, ilog2(sdp_chans)); + cfg |= field_prep(nix_af_linkx_base_mask, start); + rvu_write64(rvu, blkaddr, nix_af_linkx_cfg(nix_link), cfg); + start += sdp_chans; + } + + start = hw->cpt_chan_base; + for (link = 0; link < hw->cpt_links; link++, nix_link++) { + cfg = rvu_read64(rvu, blkaddr, nix_af_linkx_cfg(nix_link)); + cfg &= ~(nix_af_linkx_base_mask | nix_af_linkx_range_mask); + cfg |= field_prep(nix_af_linkx_range_mask, ilog2(cpt_chans)); + cfg |= field_prep(nix_af_linkx_base_mask, start); + rvu_write64(rvu, blkaddr, nix_af_linkx_cfg(nix_link), cfg); + start += cpt_chans; + } +} + +static void rvu_nix_set_channels(struct rvu *rvu) +{ + int blkaddr = 0; + + blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); + while (blkaddr) { + __rvu_nix_set_channels(rvu, blkaddr); + blkaddr = rvu_get_next_nix_blkaddr(rvu, blkaddr); + } +} + +static void __rvu_rpm_set_channels(int cgxid, int lmacid, u16 base) +{ + u64 cfg; + + cfg = cgx_lmac_read(cgxid, lmacid, rpmx_cmrx_link_cfg); + cfg &= ~(rpmx_cmrx_link_base_mask | rpmx_cmrx_link_range_mask); + + /* there is no read-only constant register to read + * the number of channels for lmac and it is always 16. + */ + cfg |= field_prep(rpmx_cmrx_link_range_mask, ilog2(16)); + cfg |= field_prep(rpmx_cmrx_link_base_mask, base); + cgx_lmac_write(cgxid, lmacid, rpmx_cmrx_link_cfg, cfg); +} + +static void rvu_rpm_set_channels(struct rvu *rvu) +{ + struct rvu_hwinfo *hw = rvu->hw; + u16 base = hw->cgx_chan_base; + int cgx, lmac; + + for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) { + for (lmac = 0; lmac < hw->lmac_per_cgx; lmac++) { + __rvu_rpm_set_channels(cgx, lmac, base); + base += 16; + } + } +} + +void rvu_program_channels(struct rvu *rvu) +{ + struct rvu_hwinfo *hw = rvu->hw; + + if (!hw->cap.programmable_chans) + return; + + rvu_nix_set_channels(rvu); + rvu_lbk_set_channels(rvu); + rvu_rpm_set_channels(rvu); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c - pfvf->rx_chan_base = nix_chan_cgx_lmac_chx(cgx_id, lmac_id, 0); + pfvf->rx_chan_base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0); - pfvf->rx_chan_base = nix_chan_lbk_chx(lbkid, vf); + pfvf->rx_chan_base = rvu_nix_chan_lbk(rvu, lbkid, vf); - nix_chan_lbk_chx(lbkid, vf - 1) : - nix_chan_lbk_chx(lbkid, vf + 1); + rvu_nix_chan_lbk(rvu, lbkid, vf - 1) : + rvu_nix_chan_lbk(rvu, lbkid, vf + 1); - /* set num of links of each type */ - cfg = rvu_read64(rvu, blkaddr, nix_af_const); - hw->cgx = (cfg >> 12) & 0xf; - hw->lmac_per_cgx = (cfg >> 8) & 0xf; - hw->cgx_links = hw->cgx * hw->lmac_per_cgx; - hw->lbk_links = (cfg >> 24) & 0xf; - hw->sdp_links = 1; - diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c - base = nix_chan_cgx_lmac_chx(cgx_id, lmac_id, 0x0); + base = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0x0); - end = nix_chan_cgx_lmac_chx(cgx_id, lmac_id, 0xf); + end = rvu_nix_chan_cgx(rvu, cgx_id, lmac_id, 0xf); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +#define nix_af_linkx_cfg(a) (0x4010 | (a) << 17) +#define nix_af_linkx_base_mask genmask_ull(11, 0) +#define nix_af_linkx_range_mask genmask_ull(19, 16) + + +/* lbk */ +#define lbk_const (0x10ull) +#define lbk_link_cfg_p2x (0x400ull) +#define lbk_link_cfg_x2p (0x408ull) +#define lbk_const_chans genmask_ull(47, 32) +#define lbk_const_dst genmask_ull(31, 28) +#define lbk_const_src genmask_ull(27, 24) +#define lbk_link_cfg_range_mask genmask_ull(19, 16) +#define lbk_link_cfg_id_mask genmask_ull(11, 6) +#define lbk_link_cfg_base_mask genmask_ull(5, 0) +
|
Networking
|
242da439214be9e61b75376d90e71c5c61744c92
|
subbaraya sundeep
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: cn10k: add mtu configuration
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octeontx3 cn10k silicon supports bigger mtu when compared to 9216 mtu supported by octeontx2 silicon variants. lookback interface supports upto 64k and rpm lmac interfaces support upto 16k.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add marvell cn10k support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['octeontx2-af ']
|
['h', 'c', 'makefile']
| 11
| 138
| 12
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/makefile b/drivers/net/ethernet/marvell/octeontx2/af/makefile --- a/drivers/net/ethernet/marvell/octeontx2/af/makefile +++ b/drivers/net/ethernet/marvell/octeontx2/af/makefile -obj-$(config_octeontx2_mbox) += octeontx2_mbox.o -obj-$(config_octeontx2_af) += octeontx2_af.o +obj-$(config_octeontx2_mbox) += rvu_mbox.o +obj-$(config_octeontx2_af) += rvu_af.o -octeontx2_mbox-y := mbox.o rvu_trace.o -octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ +rvu_mbox-y := mbox.o rvu_trace.o +rvu_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +static void cgx_lmac_get_fifolen(struct cgx *cgx) +{ + u64 cfg; + + cfg = cgx_read(cgx, 0, cgx_const); + cgx->mac_ops->fifo_len = field_get(cgx_const_rxfifo_size, cfg); +} + + cgx_lmac_get_fifolen(cgx); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +#define cgx_const_rxfifo_size genmask_ull(23, 0) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h b/drivers/net/ethernet/marvell/octeontx2/af/common.h --- a/drivers/net/ethernet/marvell/octeontx2/af/common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h +#define cn10k_lmac_link_max_frs 16380 /* 16k - fcs */ +#define cn10k_lbk_link_max_frs 65535 /* 64k */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h --- a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h + u32 fifo_len; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h - nix_cn10k_aq_enq_rsp) + nix_cn10k_aq_enq_rsp) \ +m(nix_get_hw_info, 0x801a, nix_get_hw_info, msg_req, nix_hw_info) +struct nix_hw_info { + struct mbox_msghdr hdr; + u16 max_mtu; + u16 min_mtu; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c -#define drv_name "octeontx2-af" +#define drv_name "rvu_af" +static void rvu_get_lbk_bufsize(struct rvu *rvu) +{ + struct pci_dev *pdev = null; + void __iomem *base; + u64 lbk_const; + + pdev = pci_get_device(pci_vendor_id_cavium, + pci_devid_octeontx2_lbk, pdev); + if (!pdev) + return; + + base = pci_ioremap_bar(pdev, 0); + if (!base) + goto err_put; + + lbk_const = readq(base + lbk_const); + + /* cache fifo size */ + rvu->hw->lbk_bufsize = field_get(lbk_const_buf_size, lbk_const); + + iounmap(base); +err_put: + pci_dev_put(pdev); +} + + rvu_get_lbk_bufsize(rvu); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h + u32 lbk_bufsize; /* fifo size supported by lbk */ +u32 rvu_cgx_get_fifolen(struct rvu *rvu); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +#include "lmac_common.h" +u32 rvu_cgx_get_fifolen(struct rvu *rvu) +{ + struct mac_ops *mac_ops; + int rvu_def_cgx_id = 0; + u32 fifo_len; + + mac_ops = get_mac_ops(rvu_cgx_pdata(rvu_def_cgx_id, rvu)); + fifo_len = mac_ops ? mac_ops->fifo_len : 0; + + return fifo_len; +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +static void rvu_get_lbk_link_max_frs(struct rvu *rvu, u16 *max_mtu) +{ + /* cn10k supports lbk fifo size 72 kb */ + if (rvu->hw->lbk_bufsize == 0x12000) + *max_mtu = cn10k_lbk_link_max_frs; + else + *max_mtu = nic_hw_max_frs; +} + +static void rvu_get_lmac_link_max_frs(struct rvu *rvu, u16 *max_mtu) +{ + /* rpm supports fifo len 128 kb */ + if (rvu_cgx_get_fifolen(rvu) == 0x20000) + *max_mtu = cn10k_lmac_link_max_frs; + else + *max_mtu = nic_hw_max_frs; +} + +int rvu_mbox_handler_nix_get_hw_info(struct rvu *rvu, struct msg_req *req, + struct nix_hw_info *rsp) +{ + u16 pcifunc = req->hdr.pcifunc; + int blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, pcifunc); + if (blkaddr < 0) + return nix_af_err_af_lf_invalid; + + if (is_afvf(pcifunc)) + rvu_get_lbk_link_max_frs(rvu, &rsp->max_mtu); + else + rvu_get_lmac_link_max_frs(rvu, &rsp->max_mtu); + + rsp->min_mtu = nic_hw_min_frs; + return 0; +} + + u16 max_mtu; - if (!req->sdp_link && req->maxlen > nic_hw_max_frs) + if (is_afvf(pcifunc)) + rvu_get_lbk_link_max_frs(rvu, &max_mtu); + else + rvu_get_lmac_link_max_frs(rvu, &max_mtu); + + if (!req->sdp_link && req->maxlen > max_mtu) - cgx_fifo_len / cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); + rvu_cgx_get_fifolen(rvu) / + cgx_get_lmac_cnt(rvu_cgx_pdata(cgx, rvu)); +static u64 rvu_get_lbk_link_credits(struct rvu *rvu, u16 lbk_max_frs) +{ + /* cn10k supports 72kb fifo size and max packet size of 64k */ + if (rvu->hw->lbk_bufsize == 0x12000) + return (rvu->hw->lbk_bufsize - lbk_max_frs) / 16; + + return 1600; /* 16 * max lbk datarate = 16 * 100gbps */ +} + + u16 lbk_max_frs, lmac_max_frs; + rvu_get_lbk_link_max_frs(rvu, &lbk_max_frs); + rvu_get_lmac_link_max_frs(rvu, &lmac_max_frs); + - for (link = 0; link < (hw->cgx_links + hw->lbk_links); link++) { + for (link = 0; link < hw->cgx_links; link++) { - nic_hw_max_frs << 16 | nic_hw_min_frs); + ((u64)lmac_max_frs << 16) | nic_hw_min_frs); + for (link = hw->cgx_links; link < hw->lbk_links; link++) { + rvu_write64(rvu, blkaddr, nix_af_rx_linkx_cfg(link), + ((u64)lbk_max_frs << 16) | nic_hw_min_frs); + } - tx_credits = ((cgx_fifo_len / lmac_cnt) - nic_hw_max_frs) / 16; + tx_credits = ((rvu_cgx_get_fifolen(rvu) / lmac_cnt) - + lmac_max_frs) / 16; - tx_credits = 1000; /* 10 * max lbk datarate = 10 * 100gbps */ + tx_credits = rvu_get_lbk_link_credits(rvu, lbk_max_frs); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +#define lbk_const_buf_size genmask_ull(23, 0)
|
Networking
|
6e54e1c5399a22e30f69771dfd70d5a847c809b4
|
hariprasad kelam
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-pf: cn10k: get max mtu supported from admin function
|
cn10k supports max mtu of 16k on lmac links and 64k on lbk links and octeontx2 silicon supports 9k mtu on both links. get the same from nix_get_hw_info mbox message in netdev probe.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 7
| 97
| 18
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c - aq->sq.smq_rr_weight = otx2_max_mtu; + aq->sq.smq_rr_weight = pfvf->netdev->mtu; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c - pfvf->max_frs = mtu + otx2_eth_hlen; - req->regval[0] = ((otx2_max_mtu + otx2_eth_hlen) << 8) | - otx2_min_mtu; + req->regval[0] = ((pfvf->netdev->max_mtu + otx2_eth_hlen) << 8) + | otx2_min_mtu; +u16 otx2_get_max_mtu(struct otx2_nic *pfvf) +{ + struct nix_hw_info *rsp; + struct msg_req *req; + u16 max_mtu; + int rc; + + mutex_lock(&pfvf->mbox.lock); + + req = otx2_mbox_alloc_msg_nix_get_hw_info(&pfvf->mbox); + if (!req) { + rc = -enomem; + goto out; + } + + rc = otx2_sync_mbox_msg(&pfvf->mbox); + if (!rc) { + rsp = (struct nix_hw_info *) + otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); + + /* hw counts vlan insertion bytes (8 for double tag) + * irrespective of whether sqe is requesting to insert vlan + * in the packet or not. hence these 8 bytes have to be + * discounted from max packet size otherwise hw will throw + * smq errors + */ + max_mtu = rsp->max_mtu - 8 - otx2_eth_hlen; + } + +out: + mutex_unlock(&pfvf->mbox.lock); + if (rc) { + dev_warn(pfvf->dev, + "failed to get mtu from hardware setting default value(1500) "); + max_mtu = 1500; + } + return max_mtu; +} +export_symbol(otx2_get_max_mtu); + diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h - +u16 otx2_get_max_mtu(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) +{ + int frame_size; + int total_size; + int rbuf_size; + + /* the data transferred by nix to memory consists of actual packet + * plus additional data which has timestamp and/or edsa/higig2 + * headers if interface is configured in corresponding modes. + * nix transfers entire data using 6 segments/buffers and writes + * a cqe_rx descriptor with those segment addresses. first segment + * has additional data prepended to packet. also software omits a + * headroom of 128 bytes and sizeof(struct skb_shared_info) in + * each segment. hence the total size of memory needed + * to receive a packet with 'mtu' is: + * frame size = mtu + additional data; + * memory = frame_size + (headroom + struct skb_shared_info size) * 6; + * each receive buffer size = memory / 6; + */ + frame_size = mtu + otx2_eth_hlen + otx2_hw_timestamp_len; + total_size = frame_size + (otx2_head_room + + otx2_data_align(sizeof(struct skb_shared_info))) * 6; + rbuf_size = total_size / 6; + + return align(rbuf_size, 2048); +} + - /* get the size of receive buffers to allocate */ - pf->rbsize = rcv_frag_len(otx2_hw_timestamp_len + pf->netdev->mtu + - otx2_eth_hlen); + pf->max_frs = pf->netdev->mtu + otx2_eth_hlen + otx2_hw_timestamp_len; + + pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); - netdev->max_mtu = otx2_max_mtu; + netdev->max_mtu = otx2_get_max_mtu(pf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c - if (cqe->sg.segs == 1) - return false; + return false; - if (cqe->sg.segs == 1 && (pfvf->netdev->features & netif_f_rxall)) + if (pfvf->netdev->features & netif_f_rxall) + struct nix_rx_sg_s *sg = &cqe->sg; + void *end, *start; + u64 *seg_addr; + u16 *seg_size; + int seg; - if (unlikely(parse->errlev || parse->errcode || cqe->sg.segs > 1)) { + if (unlikely(parse->errlev || parse->errcode)) { - otx2_skb_add_frag(pfvf, skb, cqe->sg.seg_addr, cqe->sg.seg_size, parse); - cq->pool_ptrs++; - + start = (void *)sg; + end = start + ((cqe->parse.desc_sizem1 + 1) * 16); + while (start < end) { + sg = (struct nix_rx_sg_s *)start; + seg_addr = &sg->seg_addr; + seg_size = (void *)sg; + for (seg = 0; seg < sg->segs; seg++, seg_addr++) { + otx2_skb_add_frag(pfvf, skb, *seg_addr, seg_size[seg], + parse); + cq->pool_ptrs++; + } + start += sizeof(*sg); + } diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.h -#define otx2_max_mtu (9212 - otx2_eth_hlen) diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_vf.c - netdev->max_mtu = otx2_max_mtu; + netdev->max_mtu = otx2_get_max_mtu(vf);
|
Networking
|
ab58a416c93f134b72ec7e10d8d74509c3985243
|
hariprasad kelam
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-af: cn10k: add rpm lmac pause frame support
|
flow control configuration is different for cgx(octeontx2) and rpm(cn10k) functional blocks. this patch adds the necessary changes for rpm to support 802.3 pause frames configuration on cn10k platforms.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 6
| 201
| 23
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c - if (is_dev_rpm(cgx)) - return; - -int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id, - u8 *tx_pause, u8 *rx_pause) +static int cgx_lmac_get_pause_frm_status(void *cgxd, int lmac_id, + u8 *tx_pause, u8 *rx_pause) -int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id, - u8 tx_pause, u8 rx_pause) +static int cgx_lmac_enadis_pause_frm(void *cgxd, int lmac_id, + u8 tx_pause, u8 rx_pause) -static void cgx_lmac_pause_frm_config(struct cgx *cgx, int lmac_id, bool enable) +static void cgx_lmac_pause_frm_config(void *cgxd, int lmac_id, bool enable) + struct cgx *cgx = cgxd; - if (is_dev_rpm(cgx)) - return; - - cgx_lmac_pause_frm_config(cgx, lmac->lmac_id, true); + cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, true); - cgx_lmac_pause_frm_config(cgx, lmac->lmac_id, false); + cgx->mac_ops->mac_pause_frm_config(cgx, lmac->lmac_id, false); - cgx->hw_features = rvu_mac_rpm; + cgx->hw_features = (rvu_mac_rpm | rvu_lmac_feat_fc); + .mac_enadis_rx_pause_fwding = cgx_lmac_enadis_rx_pause_fwding, + .mac_get_pause_frm_status = cgx_lmac_get_pause_frm_status, + .mac_enadis_pause_frm = cgx_lmac_enadis_pause_frm, + .mac_pause_frm_config = cgx_lmac_pause_frm_config, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h --- a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h + + /* enable lmac pause frame configuration */ + void (*mac_enadis_rx_pause_fwding)(void *cgxd, + int lmac_id, + bool enable); + int (*mac_get_pause_frm_status)(void *cgxd, + int lmac_id, + u8 *tx_pause, + u8 *rx_pause); + + int (*mac_enadis_pause_frm)(void *cgxd, + int lmac_id, + u8 tx_pause, + u8 rx_pause); + void (*mac_pause_frm_config)(void *cgxd, + int lmac_id, + bool enable); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c + .mac_enadis_rx_pause_fwding = rpm_lmac_enadis_rx_pause_fwding, + .mac_get_pause_frm_status = rpm_lmac_get_pause_frm_status, + .mac_enadis_pause_frm = rpm_lmac_enadis_pause_frm, + .mac_pause_frm_config = rpm_lmac_pause_frm_config, +static void rpm_write(rpm_t *rpm, u64 lmac, u64 offset, u64 val) +{ + cgx_write(rpm, lmac, offset, val); +} + + +void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable) +{ + struct cgx *rpm = rpmd; + u64 cfg; + + if (!rpm) + return; + + if (enable) { + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_pause_ignore; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + } else { + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg |= rpmx_mti_mac100x_command_config_pause_ignore; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + } +} + +int rpm_lmac_get_pause_frm_status(void *rpmd, int lmac_id, + u8 *tx_pause, u8 *rx_pause) +{ + rpm_t *rpm = rpmd; + u64 cfg; + + if (!is_lmac_valid(rpm, lmac_id)) + return -enodev; + + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + *rx_pause = !(cfg & rpmx_mti_mac100x_command_config_rx_p_disable); + + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + *tx_pause = !(cfg & rpmx_mti_mac100x_command_config_tx_p_disable); + return 0; +} + +int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, + u8 rx_pause) +{ + rpm_t *rpm = rpmd; + u64 cfg; + + if (!is_lmac_valid(rpm, lmac_id)) + return -enodev; + + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_rx_p_disable; + cfg |= rx_pause ? 0x0 : rpmx_mti_mac100x_command_config_rx_p_disable; + cfg &= ~rpmx_mti_mac100x_command_config_pause_ignore; + cfg |= rx_pause ? 0x0 : rpmx_mti_mac100x_command_config_pause_ignore; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_tx_p_disable; + cfg |= tx_pause ? 0x0 : rpmx_mti_mac100x_command_config_tx_p_disable; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + cfg = rpm_read(rpm, 0, rpmx_cmr_rx_ovr_bp); + if (tx_pause) { + cfg &= ~rpmx_cmr_rx_ovr_bp_en(lmac_id); + } else { + cfg |= rpmx_cmr_rx_ovr_bp_en(lmac_id); + cfg &= ~rpmx_cmr_rx_ovr_bp_bp(lmac_id); + } + rpm_write(rpm, 0, rpmx_cmr_rx_ovr_bp, cfg); + return 0; +} + +void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable) +{ + rpm_t *rpm = rpmd; + u64 cfg; + + if (enable) { + /* enable 802.3 pause frame mode */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_pfc_mode; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + /* enable receive pause frames */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_rx_p_disable; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + /* enable forward pause to tx block */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_pause_ignore; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + /* enable pause frames transmission */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg &= ~rpmx_mti_mac100x_command_config_tx_p_disable; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + /* set pause time and interval */ + cfg = rpm_read(rpm, lmac_id, + rpmx_mti_mac100x_cl01_pause_quanta); + cfg &= ~0xffffull; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_cl01_pause_quanta, + cfg | rpm_default_pause_time); + /* set pause interval as the hardware default is too short */ + cfg = rpm_read(rpm, lmac_id, + rpmx_mti_mac100x_cl01_quanta_thresh); + cfg &= ~0xffffull; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_cl01_quanta_thresh, + cfg | (rpm_default_pause_time / 2)); + + } else { + /* all pause frames received are completely ignored */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg |= rpmx_mti_mac100x_command_config_rx_p_disable; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + /* disable forward pause to tx block */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg |= rpmx_mti_mac100x_command_config_pause_ignore; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + + /* disable pause frames transmission */ + cfg = rpm_read(rpm, lmac_id, rpmx_mti_mac100x_command_config); + cfg |= rpmx_mti_mac100x_command_config_tx_p_disable; + rpm_write(rpm, lmac_id, rpmx_mti_mac100x_command_config, cfg); + } +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h - +#define rpmx_mti_mac100x_command_config 0x8010 +#define rpmx_mti_mac100x_command_config_rx_p_disable bit_ull(29) +#define rpmx_mti_mac100x_command_config_tx_p_disable bit_ull(28) +#define rpmx_mti_mac100x_command_config_pause_ignore bit_ull(8) +#define rpmx_mti_mac100x_command_config_pfc_mode bit_ull(19) +#define rpmx_mti_mac100x_cl01_pause_quanta 0x80a8 +#define rpmx_mti_mac100x_cl01_quanta_thresh 0x80c8 +#define rpm_default_pause_time 0xffff +#define rpmx_cmr_rx_ovr_bp 0x4120 +#define rpmx_cmr_rx_ovr_bp_en(x) bit_ull((x) + 8) +#define rpmx_cmr_rx_ovr_bp_bp(x) bit_ull((x) + 4) +void rpm_lmac_enadis_rx_pause_fwding(void *rpmd, int lmac_id, bool enable); +int rpm_lmac_get_pause_frm_status(void *cgxd, int lmac_id, u8 *tx_pause, + u8 *rx_pause); +void rpm_lmac_pause_frm_config(void *rpmd, int lmac_id, bool enable); +int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, + u8 rx_pause); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c + struct mac_ops *mac_ops; + mac_ops = get_mac_ops(cgxd); - cgx_lmac_enadis_rx_pause_fwding(cgxd, lmac_id, true); + mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, true); - cgx_lmac_enadis_rx_pause_fwding(cgxd, lmac_id, false); + mac_ops->mac_enadis_rx_pause_fwding(cgxd, lmac_id, false); + struct mac_ops *mac_ops; + void *cgxd; + cgxd = rvu_cgx_pdata(cgx_id, rvu); + mac_ops = get_mac_ops(cgxd); - cgx_lmac_set_pause_frm(rvu_cgx_pdata(cgx_id, rvu), lmac_id, - req->tx_pause, req->rx_pause); + mac_ops->mac_enadis_pause_frm(cgxd, lmac_id, + req->tx_pause, req->rx_pause); - cgx_lmac_get_pause_frm(rvu_cgx_pdata(cgx_id, rvu), lmac_id, - &rsp->tx_pause, &rsp->rx_pause); + mac_ops->mac_get_pause_frm_status(cgxd, lmac_id, + &rsp->tx_pause, + &rsp->rx_pause); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +#include "lmac_common.h" + struct mac_ops *mac_ops; + mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu)); - cgx_lmac_set_pause_frm(rvu_cgx_pdata(cgx_id, rvu), - lmac_id, true, true); + mac_ops->mac_enadis_pause_frm(rvu_cgx_pdata(cgx_id, + rvu), + lmac_id, true, true);
|
Networking
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1845ada47f6de392b2f4de0764e1c4b38d7d7bc0
|
rakesh babu
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
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octeontx2-af: cn10k: add rpm rx/tx stats support
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rpm supports below list of counters as an extension to existing counters * class based flow control pause frames * vlan/jabber/fragmented packets * fcs/alignment/oversized error packets
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add marvell cn10k support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['octeontx2-af ']
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['h', 'c']
| 8
| 227
| 26
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--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c - struct mac_ops *mac_ops; - mac_ops = cgx->mac_ops; - struct mac_ops *mac_ops; - mac_ops = cgx->mac_ops; + .rx_stats_cnt = 9, + .tx_stats_cnt = 18, + .mac_get_rx_stats = cgx_get_rx_stats, + .mac_get_tx_stats = cgx_get_tx_stats, + mutex_init(&cgx->lock); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h -#define cgxx_cmrx_rx_stat0 (0x070 + mac_ops->csr_offset) +#define cgxx_cmrx_rx_stat0 0x070 -#define cgxx_cmrx_tx_stat0 (0x700 + mac_ops->csr_offset) +#define cgxx_cmrx_tx_stat0 0x700 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h --- a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h + /* rpm & cgx differs in number of receive/transmit stats */ + u8 rx_stats_cnt; + u8 tx_stats_cnt; + /* register stats related functions */ + int (*mac_get_rx_stats)(void *cgx, int lmac_id, + int idx, u64 *rx_stat); + int (*mac_get_tx_stats)(void *cgx, int lmac_id, + int idx, u64 *tx_stat); + + + - + /* lock to serialize read/write of global csrs like + * rpmx_mti_stat_data_hi_cdc etc + */ + struct mutex lock; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +m(rpm_stats, 0x216, rpm_stats, msg_req, rpm_stats_rsp) \ -#define rvu_mac_cgx 0 -#define rvu_mac_rpm 1 +#define rvu_mac_cgx bit_ull(3) +#define rvu_mac_rpm bit_ull(4) +struct rpm_stats_rsp { + struct mbox_msghdr hdr; +#define rpm_rx_stats_count 43 +#define rpm_tx_stats_count 34 + u64 rx_stats[rpm_rx_stats_count]; + u64 tx_stats[rpm_tx_stats_count]; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c + .rx_stats_cnt = 43, + .tx_stats_cnt = 34, + .mac_get_rx_stats = rpm_get_rx_stats, + .mac_get_tx_stats = rpm_get_tx_stats, - struct cgx *rpm = rpmd; + rpm_t *rpm = rpmd; + +int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat) +{ + rpm_t *rpm = rpmd; + u64 val_lo, val_hi; + + if (!rpm || lmac_id >= rpm->lmac_count) + return -enodev; + + mutex_lock(&rpm->lock); + + /* update idx to point per lmac rx statistics page */ + idx += lmac_id * rpm->mac_ops->rx_stats_cnt; + + /* read lower 32 bits of counter */ + val_lo = rpm_read(rpm, 0, rpmx_mti_stat_rx_stat_pages_counterx + + (idx * 8)); + + /* upon read of lower 32 bits, higher 32 bits are written + * to rpmx_mti_stat_data_hi_cdc + */ + val_hi = rpm_read(rpm, 0, rpmx_mti_stat_data_hi_cdc); + + *rx_stat = (val_hi << 32 | val_lo); + + mutex_unlock(&rpm->lock); + return 0; +} + +int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat) +{ + rpm_t *rpm = rpmd; + u64 val_lo, val_hi; + + if (!rpm || lmac_id >= rpm->lmac_count) + return -enodev; + + mutex_lock(&rpm->lock); + + /* update idx to point per lmac tx statistics page */ + idx += lmac_id * rpm->mac_ops->tx_stats_cnt; + + val_lo = rpm_read(rpm, 0, rpmx_mti_stat_tx_stat_pages_counterx + + (idx * 8)); + val_hi = rpm_read(rpm, 0, rpmx_mti_stat_data_hi_cdc); + + *tx_stat = (val_hi << 32 | val_lo); + + mutex_unlock(&rpm->lock); + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +#define rpmx_mti_lpcsx_control(id) (0x30000 | ((id) * 0x100)) +#define rpmx_mti_stat_rx_stat_pages_counterx 0x12000 +#define rpmx_mti_stat_tx_stat_pages_counterx 0x13000 +#define rpmx_mti_stat_data_hi_cdc 0x10038 + +int rpm_get_nr_lmacs(void *rpmd); -int rpm_get_nr_lmacs(void *cgxd); +int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat); +int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c -int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, - struct cgx_stats_rsp *rsp) +static int rvu_lmac_get_stats(struct rvu *rvu, struct msg_req *req, + void *rsp) + struct mac_ops *mac_ops; + mac_ops = get_mac_ops(cgxd); - while (stat < cgx_rx_stats_count) { - err = cgx_get_rx_stats(cgxd, lmac, stat, &rx_stat); + while (stat < mac_ops->rx_stats_cnt) { + err = mac_ops->mac_get_rx_stats(cgxd, lmac, stat, &rx_stat); - rsp->rx_stats[stat] = rx_stat; + if (mac_ops->rx_stats_cnt == rpm_rx_stats_count) + ((struct rpm_stats_rsp *)rsp)->rx_stats[stat] = rx_stat; + else + ((struct cgx_stats_rsp *)rsp)->rx_stats[stat] = rx_stat; - while (stat < cgx_tx_stats_count) { - err = cgx_get_tx_stats(cgxd, lmac, stat, &tx_stat); + while (stat < mac_ops->tx_stats_cnt) { + err = mac_ops->mac_get_tx_stats(cgxd, lmac, stat, &tx_stat); - rsp->tx_stats[stat] = tx_stat; + if (mac_ops->tx_stats_cnt == rpm_tx_stats_count) + ((struct rpm_stats_rsp *)rsp)->tx_stats[stat] = tx_stat; + else + ((struct cgx_stats_rsp *)rsp)->tx_stats[stat] = tx_stat; +int rvu_mbox_handler_cgx_stats(struct rvu *rvu, struct msg_req *req, + struct cgx_stats_rsp *rsp) +{ + return rvu_lmac_get_stats(rvu, req, (void *)rsp); +} + +int rvu_mbox_handler_rpm_stats(struct rvu *rvu, struct msg_req *req, + struct rpm_stats_rsp *rsp) +{ + return rvu_lmac_get_stats(rvu, req, (void *)rsp); +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +static char *rpm_rx_stats_fields[] = { + "octets of received packets", + "octets of received packets with out error", + "received packets with alignment errors", + "control/pause packets received", + "packets received with frame too long errors", + "packets received with a1nrange length errors", + "received packets", + "packets received with framechecksequenceerrors", + "packets received with vlan header", + "error packets", + "packets recievd with unicast dmac", + "packets received with multicast dmac", + "packets received with broadcast dmac", + "dropped packets", + "total frames received on interface", + "packets received with an octet count < 64", + "packets received with an octet count == 64", + "packets received with an octet count of 65127", + "packets received with an octet count of 128-255", + "packets received with an octet count of 256-511", + "packets received with an octet count of 512-1023", + "packets received with an octet count of 1024-1518", + "packets received with an octet count of > 1518", + "oversized packets", + "jabber packets", + "fragmented packets", + "cbfc(class based flow control) pause frames received for class 0", + "cbfc pause frames received for class 1", + "cbfc pause frames received for class 2", + "cbfc pause frames received for class 3", + "cbfc pause frames received for class 4", + "cbfc pause frames received for class 5", + "cbfc pause frames received for class 6", + "cbfc pause frames received for class 7", + "cbfc pause frames received for class 8", + "cbfc pause frames received for class 9", + "cbfc pause frames received for class 10", + "cbfc pause frames received for class 11", + "cbfc pause frames received for class 12", + "cbfc pause frames received for class 13", + "cbfc pause frames received for class 14", + "cbfc pause frames received for class 15", + "mac control packets received", +}; + +static char *rpm_tx_stats_fields[] = { + "total octets sent on the interface", + "total octets transmitted ok", + "control/pause frames sent", + "total frames transmitted ok", + "total frames sent with vlan header", + "error packets", + "packets sent to unicast dmac", + "packets sent to the multicast dmac", + "packets sent to a broadcast dmac", + "packets sent with an octet count == 64", + "packets sent with an octet count of 65127", + "packets sent with an octet count of 128-255", + "packets sent with an octet count of 256-511", + "packets sent with an octet count of 512-1023", + "packets sent with an octet count of 1024-1518", + "packets sent with an octet count of > 1518", + "cbfc(class based flow control) pause frames transmitted for class 0", + "cbfc pause frames transmitted for class 1", + "cbfc pause frames transmitted for class 2", + "cbfc pause frames transmitted for class 3", + "cbfc pause frames transmitted for class 4", + "cbfc pause frames transmitted for class 5", + "cbfc pause frames transmitted for class 6", + "cbfc pause frames transmitted for class 7", + "cbfc pause frames transmitted for class 8", + "cbfc pause frames transmitted for class 9", + "cbfc pause frames transmitted for class 10", + "cbfc pause frames transmitted for class 11", + "cbfc pause frames transmitted for class 12", + "cbfc pause frames transmitted for class 13", + "cbfc pause frames transmitted for class 14", + "cbfc pause frames transmitted for class 15", + "mac control packets sent", + "total frames sent on the interface" +}; + - while (stat < cgx_rx_stats_count) { - err = cgx_get_rx_stats(cgxd, lmac_id, stat, &rx_stat); + while (stat < mac_ops->rx_stats_cnt) { + err = mac_ops->mac_get_rx_stats(cgxd, lmac_id, stat, &rx_stat); - seq_printf(s, "%s: %llu ", cgx_rx_stats_fields[stat], rx_stat); + if (is_rvu_otx2(rvu)) + seq_printf(s, "%s: %llu ", cgx_rx_stats_fields[stat], + rx_stat); + else + seq_printf(s, "%s: %llu ", rpm_rx_stats_fields[stat], + rx_stat); - while (stat < cgx_tx_stats_count) { - err = cgx_get_tx_stats(cgxd, lmac_id, stat, &tx_stat); + while (stat < mac_ops->tx_stats_cnt) { + err = mac_ops->mac_get_tx_stats(cgxd, lmac_id, stat, &tx_stat); - seq_printf(s, "%s: %llu ", cgx_tx_stats_fields[stat], tx_stat); - stat++; + + if (is_rvu_otx2(rvu)) + seq_printf(s, "%s: %llu ", cgx_tx_stats_fields[stat], + tx_stat); + else + seq_printf(s, "%s: %llu ", rpm_tx_stats_fields[stat], + tx_stat); + stat++;
|
Networking
|
ce7a6c3106de5724c45d555ed84acdd3930e8e71
|
hariprasad kelam
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: cn10k: mac internal loopback support
|
mac on cn10k silicon support loopback for selftest or debug purposes. this patch does necessary configuration to loopback packets upon receiving request from lmac mapped rvu pf's netdev via mailbox.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add marvell cn10k support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 6
| 61
| 6
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c -static inline u8 cgx_get_lmac_type(struct cgx *cgx, int lmac_id) +static u8 cgx_get_lmac_type(void *cgxd, int lmac_id) + struct cgx *cgx = cgxd; - lmac_type = cgx_get_lmac_type(cgx, lmac_id); + lmac_type = cgx->mac_ops->get_lmac_type(cgx, lmac_id); + .get_lmac_type = cgx_get_lmac_type, + .mac_lmac_intl_lbk = cgx_lmac_internal_loopback, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +#define resp_linkstat_lmac_type genmask_ull(35, 28) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h --- a/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h - + u8 (*get_lmac_type)(void *cgx, int lmac_id); + int (*mac_lmac_intl_lbk)(void *cgx, int lmac_id, + bool enable); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.c + .get_lmac_type = rpm_get_lmac_type, + .mac_lmac_intl_lbk = rpm_lmac_internal_loopback, + +u8 rpm_get_lmac_type(void *rpmd, int lmac_id) +{ + rpm_t *rpm = rpmd; + u64 req = 0, resp; + int err; + + req = field_set(cmdreg_id, cgx_cmd_get_link_sts, req); + err = cgx_fwi_cmd_generic(req, &resp, rpm, 0); + if (!err) + return field_get(resp_linkstat_lmac_type, resp); + return err; +} + +int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable) +{ + rpm_t *rpm = rpmd; + u8 lmac_type; + u64 cfg; + + if (!rpm || lmac_id >= rpm->lmac_count) + return -enodev; + lmac_type = rpm->mac_ops->get_lmac_type(rpm, lmac_id); + if (lmac_type == lmac_mode_100g_r) { + cfg = rpm_read(rpm, lmac_id, rpmx_mti_pcs100x_control1); + + if (enable) + cfg |= rpmx_mti_pcs_lbk; + else + cfg &= ~rpmx_mti_pcs_lbk; + rpm_write(rpm, lmac_id, rpmx_mti_pcs100x_control1, cfg); + } else { + cfg = rpm_read(rpm, lmac_id, rpmx_mti_lpcsx_control1); + if (enable) + cfg |= rpmx_mti_pcs_lbk; + else + cfg &= ~rpmx_mti_pcs_lbk; + rpm_write(rpm, lmac_id, rpmx_mti_lpcsx_control1, cfg); + } + + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rpm.h +#define rpmx_mti_pcs100x_control1 0x20000 +#define rpmx_mti_lpcsx_control1 0x30000 +#define rpmx_mti_pcs_lbk bit_ull(14) +u8 rpm_get_lmac_type(void *rpmd, int lmac_id); +int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c - int pf = rvu_get_pf(pcifunc); + struct mac_ops *mac_ops; - rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + mac_ops = get_mac_ops(rvu_cgx_pdata(cgx_id, rvu)); - return cgx_lmac_internal_loopback(rvu_cgx_pdata(cgx_id, rvu), + return mac_ops->mac_lmac_intl_lbk(rvu_cgx_pdata(cgx_id, rvu),
|
Networking
|
3ad3f8f93c81f81d6e28b2e286b03669cc1fb3b0
|
hariprasad kelam
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: add devlink health reporters for nix
|
add health reporters for rvu nix block. nix health reporters handle following hw event groups - general events - error events - ras events - rvu event
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add devlink and devlink health reporters
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 3
| 688
| 1
|
- general events - error events - ras events - rvu event --- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.c +static void rvu_nix_intr_work(struct work_struct *work) +{ + struct rvu_nix_health_reporters *rvu_nix_health_reporter; + + rvu_nix_health_reporter = container_of(work, struct rvu_nix_health_reporters, intr_work); + devlink_health_report(rvu_nix_health_reporter->rvu_hw_nix_intr_reporter, + "nix_af_rvu error", + rvu_nix_health_reporter->nix_event_ctx); +} + +static irqreturn_t rvu_nix_af_rvu_intr_handler(int irq, void *rvu_irq) +{ + struct rvu_nix_event_ctx *nix_event_context; + struct rvu_devlink *rvu_dl = rvu_irq; + struct rvu *rvu; + int blkaddr; + u64 intr; + + rvu = rvu_dl->rvu; + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return irq_none; + + nix_event_context = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + intr = rvu_read64(rvu, blkaddr, nix_af_rvu_int); + nix_event_context->nix_af_rvu_int = intr; + + /* clear interrupts */ + rvu_write64(rvu, blkaddr, nix_af_rvu_int, intr); + rvu_write64(rvu, blkaddr, nix_af_rvu_int_ena_w1c, ~0ull); + queue_work(rvu_dl->devlink_wq, &rvu_dl->rvu_nix_health_reporter->intr_work); + + return irq_handled; +} + +static void rvu_nix_gen_work(struct work_struct *work) +{ + struct rvu_nix_health_reporters *rvu_nix_health_reporter; + + rvu_nix_health_reporter = container_of(work, struct rvu_nix_health_reporters, gen_work); + devlink_health_report(rvu_nix_health_reporter->rvu_hw_nix_gen_reporter, + "nix_af_gen error", + rvu_nix_health_reporter->nix_event_ctx); +} + +static irqreturn_t rvu_nix_af_rvu_gen_handler(int irq, void *rvu_irq) +{ + struct rvu_nix_event_ctx *nix_event_context; + struct rvu_devlink *rvu_dl = rvu_irq; + struct rvu *rvu; + int blkaddr; + u64 intr; + + rvu = rvu_dl->rvu; + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return irq_none; + + nix_event_context = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + intr = rvu_read64(rvu, blkaddr, nix_af_gen_int); + nix_event_context->nix_af_rvu_gen = intr; + + /* clear interrupts */ + rvu_write64(rvu, blkaddr, nix_af_gen_int, intr); + rvu_write64(rvu, blkaddr, nix_af_gen_int_ena_w1c, ~0ull); + queue_work(rvu_dl->devlink_wq, &rvu_dl->rvu_nix_health_reporter->gen_work); + + return irq_handled; +} + +static void rvu_nix_err_work(struct work_struct *work) +{ + struct rvu_nix_health_reporters *rvu_nix_health_reporter; + + rvu_nix_health_reporter = container_of(work, struct rvu_nix_health_reporters, err_work); + devlink_health_report(rvu_nix_health_reporter->rvu_hw_nix_err_reporter, + "nix_af_err error", + rvu_nix_health_reporter->nix_event_ctx); +} + +static irqreturn_t rvu_nix_af_rvu_err_handler(int irq, void *rvu_irq) +{ + struct rvu_nix_event_ctx *nix_event_context; + struct rvu_devlink *rvu_dl = rvu_irq; + struct rvu *rvu; + int blkaddr; + u64 intr; + + rvu = rvu_dl->rvu; + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return irq_none; + + nix_event_context = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + intr = rvu_read64(rvu, blkaddr, nix_af_err_int); + nix_event_context->nix_af_rvu_err = intr; + + /* clear interrupts */ + rvu_write64(rvu, blkaddr, nix_af_err_int, intr); + rvu_write64(rvu, blkaddr, nix_af_err_int_ena_w1c, ~0ull); + queue_work(rvu_dl->devlink_wq, &rvu_dl->rvu_nix_health_reporter->err_work); + + return irq_handled; +} + +static void rvu_nix_ras_work(struct work_struct *work) +{ + struct rvu_nix_health_reporters *rvu_nix_health_reporter; + + rvu_nix_health_reporter = container_of(work, struct rvu_nix_health_reporters, ras_work); + devlink_health_report(rvu_nix_health_reporter->rvu_hw_nix_ras_reporter, + "nix_af_ras error", + rvu_nix_health_reporter->nix_event_ctx); +} + +static irqreturn_t rvu_nix_af_rvu_ras_handler(int irq, void *rvu_irq) +{ + struct rvu_nix_event_ctx *nix_event_context; + struct rvu_devlink *rvu_dl = rvu_irq; + struct rvu *rvu; + int blkaddr; + u64 intr; + + rvu = rvu_dl->rvu; + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return irq_none; + + nix_event_context = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + intr = rvu_read64(rvu, blkaddr, nix_af_err_int); + nix_event_context->nix_af_rvu_ras = intr; + + /* clear interrupts */ + rvu_write64(rvu, blkaddr, nix_af_ras, intr); + rvu_write64(rvu, blkaddr, nix_af_ras_ena_w1c, ~0ull); + queue_work(rvu_dl->devlink_wq, &rvu_dl->rvu_nix_health_reporter->ras_work); + + return irq_handled; +} + +static void rvu_nix_unregister_interrupts(struct rvu *rvu) +{ + struct rvu_devlink *rvu_dl = rvu->rvu_dl; + int offs, i, blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return; + + offs = rvu_read64(rvu, blkaddr, nix_priv_af_int_cfg) & 0x3ff; + if (!offs) + return; + + rvu_write64(rvu, blkaddr, nix_af_rvu_int_ena_w1c, ~0ull); + rvu_write64(rvu, blkaddr, nix_af_gen_int_ena_w1c, ~0ull); + rvu_write64(rvu, blkaddr, nix_af_err_int_ena_w1c, ~0ull); + rvu_write64(rvu, blkaddr, nix_af_ras_ena_w1c, ~0ull); + + if (rvu->irq_allocated[offs + nix_af_int_vec_rvu]) { + free_irq(pci_irq_vector(rvu->pdev, offs + nix_af_int_vec_rvu), + rvu_dl); + rvu->irq_allocated[offs + nix_af_int_vec_rvu] = false; + } + + for (i = nix_af_int_vec_af_err; i < nix_af_int_vec_cnt; i++) + if (rvu->irq_allocated[offs + i]) { + free_irq(pci_irq_vector(rvu->pdev, offs + i), rvu_dl); + rvu->irq_allocated[offs + i] = false; + } +} + +static int rvu_nix_register_interrupts(struct rvu *rvu) +{ + int blkaddr, base; + bool rc; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return blkaddr; + + /* get nix af msix vectors offset. */ + base = rvu_read64(rvu, blkaddr, nix_priv_af_int_cfg) & 0x3ff; + if (!base) { + dev_warn(rvu->dev, + "failed to get nix%d nix_af_int vector offsets ", + blkaddr - blkaddr_nix0); + return 0; + } + /* register and enable nix_af_rvu_int interrupt */ + rc = rvu_common_request_irq(rvu, base + nix_af_int_vec_rvu, + "nix_af_rvu_int", + rvu_nix_af_rvu_intr_handler); + if (!rc) + goto err; + rvu_write64(rvu, blkaddr, nix_af_rvu_int_ena_w1s, ~0ull); + + /* register and enable nix_af_gen_int interrupt */ + rc = rvu_common_request_irq(rvu, base + nix_af_int_vec_gen, + "nix_af_gen_int", + rvu_nix_af_rvu_gen_handler); + if (!rc) + goto err; + rvu_write64(rvu, blkaddr, nix_af_gen_int_ena_w1s, ~0ull); + + /* register and enable nix_af_err_int interrupt */ + rc = rvu_common_request_irq(rvu, base + nix_af_int_vec_af_err, + "nix_af_err_int", + rvu_nix_af_rvu_err_handler); + if (!rc) + goto err; + rvu_write64(rvu, blkaddr, nix_af_err_int_ena_w1s, ~0ull); + + /* register and enable nix_af_ras interrupt */ + rc = rvu_common_request_irq(rvu, base + nix_af_int_vec_poison, + "nix_af_ras", + rvu_nix_af_rvu_ras_handler); + if (!rc) + goto err; + rvu_write64(rvu, blkaddr, nix_af_ras_ena_w1s, ~0ull); + + return 0; +err: + rvu_nix_unregister_interrupts(rvu); + return rc; +} + +static int rvu_nix_report_show(struct devlink_fmsg *fmsg, void *ctx, + enum nix_af_rvu_health health_reporter) +{ + struct rvu_nix_event_ctx *nix_event_context; + u64 intr_val; + int err; + + nix_event_context = ctx; + switch (health_reporter) { + case nix_af_rvu_intr: + intr_val = nix_event_context->nix_af_rvu_int; + err = rvu_report_pair_start(fmsg, "nix_af_rvu"); + if (err) + return err; + err = devlink_fmsg_u64_pair_put(fmsg, " nix rvu interrupt reg ", + nix_event_context->nix_af_rvu_int); + if (err) + return err; + if (intr_val & bit_ull(0)) { + err = devlink_fmsg_string_put(fmsg, " unmap slot error"); + if (err) + return err; + } + err = rvu_report_pair_end(fmsg); + if (err) + return err; + break; + case nix_af_rvu_gen: + intr_val = nix_event_context->nix_af_rvu_gen; + err = rvu_report_pair_start(fmsg, "nix_af_general"); + if (err) + return err; + err = devlink_fmsg_u64_pair_put(fmsg, " nix general interrupt reg ", + nix_event_context->nix_af_rvu_gen); + if (err) + return err; + if (intr_val & bit_ull(0)) { + err = devlink_fmsg_string_put(fmsg, " rx multicast pkt drop"); + if (err) + return err; + } + if (intr_val & bit_ull(1)) { + err = devlink_fmsg_string_put(fmsg, " rx mirror pkt drop"); + if (err) + return err; + } + if (intr_val & bit_ull(4)) { + err = devlink_fmsg_string_put(fmsg, " smq flush done"); + if (err) + return err; + } + err = rvu_report_pair_end(fmsg); + if (err) + return err; + break; + case nix_af_rvu_err: + intr_val = nix_event_context->nix_af_rvu_err; + err = rvu_report_pair_start(fmsg, "nix_af_err"); + if (err) + return err; + err = devlink_fmsg_u64_pair_put(fmsg, " nix error interrupt reg ", + nix_event_context->nix_af_rvu_err); + if (err) + return err; + if (intr_val & bit_ull(14)) { + err = devlink_fmsg_string_put(fmsg, " fault on nix_aq_inst_s read"); + if (err) + return err; + } + if (intr_val & bit_ull(13)) { + err = devlink_fmsg_string_put(fmsg, " fault on nix_aq_res_s write"); + if (err) + return err; + } + if (intr_val & bit_ull(12)) { + err = devlink_fmsg_string_put(fmsg, " aq doorbell error"); + if (err) + return err; + } + if (intr_val & bit_ull(6)) { + err = devlink_fmsg_string_put(fmsg, " rx on unmapped pf_func"); + if (err) + return err; + } + if (intr_val & bit_ull(5)) { + err = devlink_fmsg_string_put(fmsg, " rx multicast replication error"); + if (err) + return err; + } + if (intr_val & bit_ull(4)) { + err = devlink_fmsg_string_put(fmsg, " fault on nix_rx_mce_s read"); + if (err) + return err; + } + if (intr_val & bit_ull(3)) { + err = devlink_fmsg_string_put(fmsg, " fault on multicast wqe read"); + if (err) + return err; + } + if (intr_val & bit_ull(2)) { + err = devlink_fmsg_string_put(fmsg, " fault on mirror wqe read"); + if (err) + return err; + } + if (intr_val & bit_ull(1)) { + err = devlink_fmsg_string_put(fmsg, " fault on mirror pkt write"); + if (err) + return err; + } + if (intr_val & bit_ull(0)) { + err = devlink_fmsg_string_put(fmsg, " fault on multicast pkt write"); + if (err) + return err; + } + err = rvu_report_pair_end(fmsg); + if (err) + return err; + break; + case nix_af_rvu_ras: + intr_val = nix_event_context->nix_af_rvu_err; + err = rvu_report_pair_start(fmsg, "nix_af_ras"); + if (err) + return err; + err = devlink_fmsg_u64_pair_put(fmsg, " nix ras interrupt reg ", + nix_event_context->nix_af_rvu_err); + if (err) + return err; + err = devlink_fmsg_string_put(fmsg, " poison data on:"); + if (err) + return err; + if (intr_val & bit_ull(34)) { + err = devlink_fmsg_string_put(fmsg, " nix_aq_inst_s"); + if (err) + return err; + } + if (intr_val & bit_ull(33)) { + err = devlink_fmsg_string_put(fmsg, " nix_aq_res_s"); + if (err) + return err; + } + if (intr_val & bit_ull(32)) { + err = devlink_fmsg_string_put(fmsg, " hw ctx"); + if (err) + return err; + } + if (intr_val & bit_ull(4)) { + err = devlink_fmsg_string_put(fmsg, " packet from mirror buffer"); + if (err) + return err; + } + if (intr_val & bit_ull(3)) { + err = devlink_fmsg_string_put(fmsg, " packet from multicast buffer"); + + if (err) + return err; + } + if (intr_val & bit_ull(2)) { + err = devlink_fmsg_string_put(fmsg, " wqe read from mirror buffer"); + if (err) + return err; + } + if (intr_val & bit_ull(1)) { + err = devlink_fmsg_string_put(fmsg, " wqe read from multicast buffer"); + if (err) + return err; + } + if (intr_val & bit_ull(0)) { + err = devlink_fmsg_string_put(fmsg, " nix_rx_mce_s read"); + if (err) + return err; + } + err = rvu_report_pair_end(fmsg); + if (err) + return err; + break; + default: + return -einval; + } + + return 0; +} + +static int rvu_hw_nix_intr_dump(struct devlink_health_reporter *reporter, + struct devlink_fmsg *fmsg, void *ctx, + struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_devlink *rvu_dl = rvu->rvu_dl; + struct rvu_nix_event_ctx *nix_ctx; + + nix_ctx = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + + return ctx ? rvu_nix_report_show(fmsg, ctx, nix_af_rvu_intr) : + rvu_nix_report_show(fmsg, nix_ctx, nix_af_rvu_intr); +} + +static int rvu_hw_nix_intr_recover(struct devlink_health_reporter *reporter, + void *ctx, struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_nix_event_ctx *nix_event_ctx = ctx; + int blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return blkaddr; + + if (nix_event_ctx->nix_af_rvu_int) + rvu_write64(rvu, blkaddr, nix_af_rvu_int_ena_w1s, ~0ull); + + return 0; +} + +static int rvu_hw_nix_gen_dump(struct devlink_health_reporter *reporter, + struct devlink_fmsg *fmsg, void *ctx, + struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_devlink *rvu_dl = rvu->rvu_dl; + struct rvu_nix_event_ctx *nix_ctx; + + nix_ctx = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + + return ctx ? rvu_nix_report_show(fmsg, ctx, nix_af_rvu_gen) : + rvu_nix_report_show(fmsg, nix_ctx, nix_af_rvu_gen); +} + +static int rvu_hw_nix_gen_recover(struct devlink_health_reporter *reporter, + void *ctx, struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_nix_event_ctx *nix_event_ctx = ctx; + int blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return blkaddr; + + if (nix_event_ctx->nix_af_rvu_gen) + rvu_write64(rvu, blkaddr, nix_af_gen_int_ena_w1s, ~0ull); + + return 0; +} + +static int rvu_hw_nix_err_dump(struct devlink_health_reporter *reporter, + struct devlink_fmsg *fmsg, void *ctx, + struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_devlink *rvu_dl = rvu->rvu_dl; + struct rvu_nix_event_ctx *nix_ctx; + + nix_ctx = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + + return ctx ? rvu_nix_report_show(fmsg, ctx, nix_af_rvu_err) : + rvu_nix_report_show(fmsg, nix_ctx, nix_af_rvu_err); +} + +static int rvu_hw_nix_err_recover(struct devlink_health_reporter *reporter, + void *ctx, struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_nix_event_ctx *nix_event_ctx = ctx; + int blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return blkaddr; + + if (nix_event_ctx->nix_af_rvu_err) + rvu_write64(rvu, blkaddr, nix_af_err_int_ena_w1s, ~0ull); + + return 0; +} + +static int rvu_hw_nix_ras_dump(struct devlink_health_reporter *reporter, + struct devlink_fmsg *fmsg, void *ctx, + struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_devlink *rvu_dl = rvu->rvu_dl; + struct rvu_nix_event_ctx *nix_ctx; + + nix_ctx = rvu_dl->rvu_nix_health_reporter->nix_event_ctx; + + return ctx ? rvu_nix_report_show(fmsg, ctx, nix_af_rvu_ras) : + rvu_nix_report_show(fmsg, nix_ctx, nix_af_rvu_ras); +} + +static int rvu_hw_nix_ras_recover(struct devlink_health_reporter *reporter, + void *ctx, struct netlink_ext_ack *netlink_extack) +{ + struct rvu *rvu = devlink_health_reporter_priv(reporter); + struct rvu_nix_event_ctx *nix_event_ctx = ctx; + int blkaddr; + + blkaddr = rvu_get_blkaddr(rvu, blktype_nix, 0); + if (blkaddr < 0) + return blkaddr; + + if (nix_event_ctx->nix_af_rvu_int) + rvu_write64(rvu, blkaddr, nix_af_ras_ena_w1s, ~0ull); + + return 0; +} + +rvu_reporters(hw_nix_intr); +rvu_reporters(hw_nix_gen); +rvu_reporters(hw_nix_err); +rvu_reporters(hw_nix_ras); + +static void rvu_nix_health_reporters_destroy(struct rvu_devlink *rvu_dl); + +static int rvu_nix_register_reporters(struct rvu_devlink *rvu_dl) +{ + struct rvu_nix_health_reporters *rvu_reporters; + struct rvu_nix_event_ctx *nix_event_context; + struct rvu *rvu = rvu_dl->rvu; + + rvu_reporters = kzalloc(sizeof(*rvu_reporters), gfp_kernel); + if (!rvu_reporters) + return -enomem; + + rvu_dl->rvu_nix_health_reporter = rvu_reporters; + nix_event_context = kzalloc(sizeof(*nix_event_context), gfp_kernel); + if (!nix_event_context) + return -enomem; + + rvu_reporters->nix_event_ctx = nix_event_context; + rvu_reporters->rvu_hw_nix_intr_reporter = + devlink_health_reporter_create(rvu_dl->dl, &rvu_hw_nix_intr_reporter_ops, 0, rvu); + if (is_err(rvu_reporters->rvu_hw_nix_intr_reporter)) { + dev_warn(rvu->dev, "failed to create hw_nix_intr reporter, err=%ld ", + ptr_err(rvu_reporters->rvu_hw_nix_intr_reporter)); + return ptr_err(rvu_reporters->rvu_hw_nix_intr_reporter); + } + + rvu_reporters->rvu_hw_nix_gen_reporter = + devlink_health_reporter_create(rvu_dl->dl, &rvu_hw_nix_gen_reporter_ops, 0, rvu); + if (is_err(rvu_reporters->rvu_hw_nix_gen_reporter)) { + dev_warn(rvu->dev, "failed to create hw_nix_gen reporter, err=%ld ", + ptr_err(rvu_reporters->rvu_hw_nix_gen_reporter)); + return ptr_err(rvu_reporters->rvu_hw_nix_gen_reporter); + } + + rvu_reporters->rvu_hw_nix_err_reporter = + devlink_health_reporter_create(rvu_dl->dl, &rvu_hw_nix_err_reporter_ops, 0, rvu); + if (is_err(rvu_reporters->rvu_hw_nix_err_reporter)) { + dev_warn(rvu->dev, "failed to create hw_nix_err reporter, err=%ld ", + ptr_err(rvu_reporters->rvu_hw_nix_err_reporter)); + return ptr_err(rvu_reporters->rvu_hw_nix_err_reporter); + } + + rvu_reporters->rvu_hw_nix_ras_reporter = + devlink_health_reporter_create(rvu_dl->dl, &rvu_hw_nix_ras_reporter_ops, 0, rvu); + if (is_err(rvu_reporters->rvu_hw_nix_ras_reporter)) { + dev_warn(rvu->dev, "failed to create hw_nix_ras reporter, err=%ld ", + ptr_err(rvu_reporters->rvu_hw_nix_ras_reporter)); + return ptr_err(rvu_reporters->rvu_hw_nix_ras_reporter); + } + + rvu_dl->devlink_wq = create_workqueue("rvu_devlink_wq"); + if (!rvu_dl->devlink_wq) + goto err; + + init_work(&rvu_reporters->intr_work, rvu_nix_intr_work); + init_work(&rvu_reporters->gen_work, rvu_nix_gen_work); + init_work(&rvu_reporters->err_work, rvu_nix_err_work); + init_work(&rvu_reporters->ras_work, rvu_nix_ras_work); + + return 0; +err: + rvu_nix_health_reporters_destroy(rvu_dl); + return -enomem; +} + +static int rvu_nix_health_reporters_create(struct rvu_devlink *rvu_dl) +{ + struct rvu *rvu = rvu_dl->rvu; + int err; + + err = rvu_nix_register_reporters(rvu_dl); + if (err) { + dev_warn(rvu->dev, "failed to create nix reporter, err =%d ", + err); + return err; + } + rvu_nix_register_interrupts(rvu); + + return 0; +} + +static void rvu_nix_health_reporters_destroy(struct rvu_devlink *rvu_dl) +{ + struct rvu_nix_health_reporters *nix_reporters; + struct rvu *rvu = rvu_dl->rvu; + + nix_reporters = rvu_dl->rvu_nix_health_reporter; + + if (!nix_reporters->rvu_hw_nix_ras_reporter) + return; + if (!is_err_or_null(nix_reporters->rvu_hw_nix_intr_reporter)) + devlink_health_reporter_destroy(nix_reporters->rvu_hw_nix_intr_reporter); + + if (!is_err_or_null(nix_reporters->rvu_hw_nix_gen_reporter)) + devlink_health_reporter_destroy(nix_reporters->rvu_hw_nix_gen_reporter); + + if (!is_err_or_null(nix_reporters->rvu_hw_nix_err_reporter)) + devlink_health_reporter_destroy(nix_reporters->rvu_hw_nix_err_reporter); + + if (!is_err_or_null(nix_reporters->rvu_hw_nix_ras_reporter)) + devlink_health_reporter_destroy(nix_reporters->rvu_hw_nix_ras_reporter); + + rvu_nix_unregister_interrupts(rvu); + kfree(rvu_dl->rvu_nix_health_reporter->nix_event_ctx); + kfree(rvu_dl->rvu_nix_health_reporter); +} + + int err; - return rvu_npa_health_reporters_create(rvu_dl); + err = rvu_npa_health_reporters_create(rvu_dl); + if (err) + return err; + + return rvu_nix_health_reporters_create(rvu_dl); + rvu_nix_health_reporters_destroy(rvu_dl); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_devlink.h +enum nix_af_rvu_health { + nix_af_rvu_intr, + nix_af_rvu_gen, + nix_af_rvu_err, + nix_af_rvu_ras, +}; + +struct rvu_nix_event_ctx { + u64 nix_af_rvu_int; + u64 nix_af_rvu_gen; + u64 nix_af_rvu_err; + u64 nix_af_rvu_ras; +}; + +struct rvu_nix_health_reporters { + struct rvu_nix_event_ctx *nix_event_ctx; + struct devlink_health_reporter *rvu_hw_nix_intr_reporter; + struct work_struct intr_work; + struct devlink_health_reporter *rvu_hw_nix_gen_reporter; + struct work_struct gen_work; + struct devlink_health_reporter *rvu_hw_nix_err_reporter; + struct work_struct err_work; + struct devlink_health_reporter *rvu_hw_nix_ras_reporter; + struct work_struct ras_work; +}; + + struct rvu_nix_health_reporters *rvu_nix_health_reporter; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h +/* nix admin function interrupt vector enumeration */ +enum nix_af_int_vec_e { + nix_af_int_vec_rvu = 0x0, + nix_af_int_vec_gen = 0x1, + nix_af_int_vec_aq_done = 0x2, + nix_af_int_vec_af_err = 0x3, + nix_af_int_vec_poison = 0x4, + nix_af_int_vec_cnt = 0x5, +}; +
|
Networking
|
5ed66306eab6953197c88e082d9ecc0b35e21538
|
george cherian
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: forward error correction configuration
|
cgx block supports forward error correction modes baser and rs. this patch adds support to set encoding mode and to read corrected/uncorrected block counters
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 5
| 155
| 2
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +static int cgx_set_fec_stats_count(struct cgx_link_user_info *linfo) +{ + if (!linfo->fec) + return 0; + + switch (linfo->lmac_type_id) { + case lmac_mode_sgmii: + case lmac_mode_xaui: + case lmac_mode_rxaui: + case lmac_mode_qsgmii: + return 0; + case lmac_mode_10g_r: + case lmac_mode_25g_r: + case lmac_mode_100g_r: + case lmac_mode_usxgmii: + return 1; + case lmac_mode_40g_r: + return 4; + case lmac_mode_50g_r: + if (linfo->fec == otx2_fec_baser) + return 2; + else + return 1; + default: + return 0; + } +} + +int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp) +{ + int stats, fec_stats_count = 0; + int corr_reg, uncorr_reg; + struct cgx *cgx = cgxd; + + if (!cgx || lmac_id >= cgx->lmac_count) + return -enodev; + fec_stats_count = + cgx_set_fec_stats_count(&cgx->lmac_idmap[lmac_id]->link_info); + if (cgx->lmac_idmap[lmac_id]->link_info.fec == otx2_fec_baser) { + corr_reg = cgxx_spux_lnx_fec_corr_blocks; + uncorr_reg = cgxx_spux_lnx_fec_uncorr_blocks; + } else { + corr_reg = cgxx_spux_rsfec_corr; + uncorr_reg = cgxx_spux_rsfec_uncorr; + } + for (stats = 0; stats < fec_stats_count; stats++) { + rsp->fec_corr_blks += + cgx_read(cgx, lmac_id, corr_reg + (stats * 8)); + rsp->fec_uncorr_blks += + cgx_read(cgx, lmac_id, uncorr_reg + (stats * 8)); + } + return 0; +} + + linfo->fec = field_get(resp_linkstat_fec, lstat); +int cgx_set_fec(u64 fec, int cgx_id, int lmac_id) +{ + u64 req = 0, resp; + struct cgx *cgx; + int err = 0; + + cgx = cgx_get_pdata(cgx_id); + if (!cgx) + return -enxio; + + req = field_set(cmdreg_id, cgx_cmd_set_fec, req); + req = field_set(cmdsetfec, fec, req); + err = cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); + if (err) + return err; + + cgx->lmac_idmap[lmac_id]->link_info.fec = + field_get(resp_linkstat_fec, resp); + return cgx->lmac_idmap[lmac_id]->link_info.fec; +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +#define cgxx_spux_lnx_fec_corr_blocks 0x10700 +#define cgxx_spux_lnx_fec_uncorr_blocks 0x10800 +#define cgxx_spux_rsfec_corr 0x10088 +#define cgxx_spux_rsfec_uncorr 0x10090 + +int cgx_set_fec(u64 fec, int cgx_id, int lmac_id); +int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h + cgx_cmd_get_link_modes, /* supported link modes */ + cgx_cmd_set_link_mode, + cgx_cmd_get_supported_fec, + cgx_cmd_set_fec, + cgx_cmd_get_an, + cgx_cmd_set_an, + cgx_cmd_get_adv_link_modes, + cgx_cmd_get_adv_fec, - uint64_t reserved2:39; + uint64_t an:1; /* an supported or not */ + uint64_t fec:2; /* fec type if enabled, if not 0 */ + uint64_t port:8; + uint64_t reserved2:28; +#define resp_linkstat_an genmask_ull(25, 25) +#define resp_linkstat_fec genmask_ull(27, 26) +#define resp_linkstat_port genmask_ull(35, 28) +#define cmdsetfec genmask_ull(9, 8) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h -#define mbox_rsp_timeout 2000 /* time(ms) to wait for mbox response */ +#define mbox_rsp_timeout 3000 /* time(ms) to wait for mbox response */ +m(cgx_fec_set, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \ +m(cgx_fec_stats, 0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \ + /* npa mbox ids (range 0x400 - 0x5ff) */ \ +struct cgx_fec_stats_rsp { + struct mbox_msghdr hdr; + u64 fec_corr_blks; + u64 fec_uncorr_blks; +}; + uint64_t fec:2; /* fec type if enabled else 0 */ +enum fec_type { + otx2_fec_none, + otx2_fec_baser, + otx2_fec_rs, + otx2_fec_stats_cnt = 2, + otx2_fec_off, +}; + +struct fec_mode { + struct mbox_msghdr hdr; + int fec; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +int rvu_mbox_handler_cgx_fec_stats(struct rvu *rvu, + struct msg_req *req, + struct cgx_fec_stats_rsp *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_idx, lmac; + void *cgxd; + + if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) + return -eperm; + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); + + cgxd = rvu_cgx_pdata(cgx_idx, rvu); + return cgx_get_fec_stats(cgxd, lmac, rsp); +} + + +int rvu_mbox_handler_cgx_set_fec_param(struct rvu *rvu, + struct fec_mode *req, + struct fec_mode *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_id, lmac_id; + + if (!is_pf_cgxmapped(rvu, pf)) + return -eperm; + + if (req->fec == otx2_fec_off) + req->fec = otx2_fec_none; + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + rsp->fec = cgx_set_fec(req->fec, cgx_id, lmac_id); + return 0; +}
|
Networking
|
84c4f9cab4f99e774a8d9bbee299d288bdb2d792
|
christina jacob
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: add new cgx_cmd to get phy fec statistics
|
this patch adds support to fetch fec stats from phy. the stats are put in the shared data struct fwdata. a phy driver indicates that it has fec stats by setting the flag fwdata.phy.misc.has_fec_stats
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 6
| 97
| 0
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +int cgx_get_phy_fec_stats(void *cgxd, int lmac_id) +{ + struct cgx *cgx = cgxd; + u64 req = 0, resp; + + if (!cgx) + return -enodev; + + req = field_set(cmdreg_id, cgx_cmd_get_phy_fec_stats, req); + return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +int cgx_get_phy_fec_stats(void *cgxd, int lmac_id); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h + cgx_cmd_get_phy_mod_type, /* line-side modulation type: nrz or pam4 */ + cgx_cmd_set_phy_mod_type, + cgx_cmd_prbs, + cgx_cmd_display_eye, + cgx_cmd_get_phy_fec_stats, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +m(cgx_get_phy_fec_stats, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \ +m(cgx_fw_data_get, 0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \ +struct sfp_eeprom_s { +#define sfp_eeprom_size 256 + u16 sff_id; + u8 buf[sfp_eeprom_size]; + u64 reserved; +}; + +struct phy_s { + struct { + u64 can_change_mod_type:1; + u64 mod_type:1; + u64 has_fec_stats:1; + } misc; + struct fec_stats_s { + u32 rsfec_corr_cws; + u32 rsfec_uncorr_cws; + u32 brfec_corr_blks; + u32 brfec_uncorr_blks; + } fec_stats; +}; + +struct cgx_lmac_fwdata_s { + u16 rw_valid; + u64 supported_fec; + u64 supported_an; + u64 supported_link_modes; + /* only applicable if an is supported */ + u64 advertised_fec; + u64 advertised_link_modes; + /* only applicable if sfp/qsfp slot is present */ + struct sfp_eeprom_s sfp_eeprom; + struct phy_s phy; +#define lmac_fwdata_reserved_mem 1021 + u64 reserved[lmac_fwdata_reserved_mem]; +}; + +struct cgx_fw_data { + struct mbox_msghdr hdr; + struct cgx_lmac_fwdata_s fwdata; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +#define cgx_max 5 +#define cgx_lmacs_max 4 + struct cgx_lmac_fwdata_s cgx_fw_data[cgx_max][cgx_lmacs_max]; + /* do not add new fields below this line */ diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +int rvu_mbox_handler_cgx_get_phy_fec_stats(struct rvu *rvu, struct msg_req *req, + struct msg_rsp *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_id, lmac_id; + + if (!is_pf_cgxmapped(rvu, pf)) + return -eperm; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + return cgx_get_phy_fec_stats(rvu_cgx_pdata(cgx_id, rvu), lmac_id); +} + + +int rvu_mbox_handler_cgx_get_aux_link_info(struct rvu *rvu, struct msg_req *req, + struct cgx_fw_data *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_id, lmac_id; + + if (!rvu->fwdata) + return -enxio; + + if (!is_pf_cgxmapped(rvu, pf)) + return -eperm; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id); + + memcpy(&rsp->fwdata, &rvu->fwdata->cgx_fw_data[cgx_id][lmac_id], + sizeof(struct cgx_lmac_fwdata_s)); + return 0; +}
|
Networking
|
bd74d4ea29cc3c0520d9af109bb7a7c769325746
|
felix manlunas
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-pf: ethtool fec mode support
|
add ethtool support to configure fec modes baser/rs and support to fecth fec stats from cgx as well phy.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 4
| 188
| 1
|
- ethtool --set-fec eth0 encoding rs/baser/off/auto - ethtool --show-fec eth0 --- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf) +{ + struct msg_req *req; + + if (!netif_running(pfvf->netdev)) + return; + mutex_lock(&pfvf->mbox.lock); + req = otx2_mbox_alloc_msg_cgx_fec_stats(&pfvf->mbox); + if (req) + otx2_sync_mbox_msg(&pfvf->mbox); + mutex_unlock(&pfvf->mbox.lock); +} + +void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, + struct cgx_fec_stats_rsp *rsp) +{ + pfvf->hw.cgx_fec_corr_blks += rsp->fec_corr_blks; + pfvf->hw.cgx_fec_uncorr_blks += rsp->fec_uncorr_blks; +} + diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h + u64 cgx_fec_corr_blks; + u64 cgx_fec_uncorr_blks; +void mbox_handler_cgx_fec_stats(struct otx2_nic *pfvf, + struct cgx_fec_stats_rsp *rsp); +void otx2_set_fec_stats_count(struct otx2_nic *pfvf); +void otx2_update_lmac_fec_stats(struct otx2_nic *pfvf); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf); + + sprintf(data, "fec corrected errors: "); + data += eth_gstring_len; + sprintf(data, "fec uncorrected errors: "); + data += eth_gstring_len; +static int otx2_get_phy_fec_stats(struct otx2_nic *pfvf) +{ + struct msg_req *req; + int rc = -enomem; + + mutex_lock(&pfvf->mbox.lock); + req = otx2_mbox_alloc_msg_cgx_get_phy_fec_stats(&pfvf->mbox); + if (!req) + goto end; + + if (!otx2_sync_mbox_msg(&pfvf->mbox)) + rc = 0; +end: + mutex_unlock(&pfvf->mbox.lock); + return rc; +} + + u64 fec_corr_blks, fec_uncorr_blks; + struct cgx_fw_data *rsp; + + fec_corr_blks = pfvf->hw.cgx_fec_corr_blks; + fec_uncorr_blks = pfvf->hw.cgx_fec_uncorr_blks; + + rsp = otx2_get_fwdata(pfvf); + if (!is_err(rsp) && rsp->fwdata.phy.misc.has_fec_stats && + !otx2_get_phy_fec_stats(pfvf)) { + /* fetch fwdata again because it's been recently populated with + * latest phy fec stats. + */ + rsp = otx2_get_fwdata(pfvf); + if (!is_err(rsp)) { + struct fec_stats_s *p = &rsp->fwdata.phy.fec_stats; + + if (pfvf->linfo.fec == otx2_fec_baser) { + fec_corr_blks = p->brfec_corr_blks; + fec_uncorr_blks = p->brfec_uncorr_blks; + } else { + fec_corr_blks = p->rsfec_corr_cws; + fec_uncorr_blks = p->rsfec_uncorr_cws; + } + } + } + + *(data++) = fec_corr_blks; + *(data++) = fec_uncorr_blks; + otx2_update_lmac_fec_stats(pfvf); - cgx_rx_stats_count + cgx_tx_stats_count + 1; + cgx_rx_stats_count + cgx_tx_stats_count + otx2_fec_stats_cnt + + 1; +static struct cgx_fw_data *otx2_get_fwdata(struct otx2_nic *pfvf) +{ + struct cgx_fw_data *rsp = null; + struct msg_req *req; + int err = 0; + + mutex_lock(&pfvf->mbox.lock); + req = otx2_mbox_alloc_msg_cgx_get_aux_link_info(&pfvf->mbox); + if (!req) { + mutex_unlock(&pfvf->mbox.lock); + return err_ptr(-enomem); + } + + err = otx2_sync_mbox_msg(&pfvf->mbox); + if (!err) { + rsp = (struct cgx_fw_data *) + otx2_mbox_get_rsp(&pfvf->mbox.mbox, 0, &req->hdr); + } else { + rsp = err_ptr(err); + } + + mutex_unlock(&pfvf->mbox.lock); + return rsp; +} + +static int otx2_get_fecparam(struct net_device *netdev, + struct ethtool_fecparam *fecparam) +{ + struct otx2_nic *pfvf = netdev_priv(netdev); + struct cgx_fw_data *rsp; + const int fec[] = { + ethtool_fec_off, + ethtool_fec_baser, + ethtool_fec_rs, + ethtool_fec_baser | ethtool_fec_rs}; +#define fec_max_index 4 + if (pfvf->linfo.fec < fec_max_index) + fecparam->active_fec = fec[pfvf->linfo.fec]; + + rsp = otx2_get_fwdata(pfvf); + if (is_err(rsp)) + return ptr_err(rsp); + + if (rsp->fwdata.supported_fec <= fec_max_index) { + if (!rsp->fwdata.supported_fec) + fecparam->fec = ethtool_fec_none; + else + fecparam->fec = fec[rsp->fwdata.supported_fec]; + } + return 0; +} + +static int otx2_set_fecparam(struct net_device *netdev, + struct ethtool_fecparam *fecparam) +{ + struct otx2_nic *pfvf = netdev_priv(netdev); + struct mbox *mbox = &pfvf->mbox; + struct fec_mode *req, *rsp; + int err = 0, fec = 0; + + switch (fecparam->fec) { + /* firmware does not support auto mode consider it as fec_off */ + case ethtool_fec_off: + case ethtool_fec_auto: + fec = otx2_fec_off; + break; + case ethtool_fec_rs: + fec = otx2_fec_rs; + break; + case ethtool_fec_baser: + fec = otx2_fec_baser; + break; + default: + netdev_warn(pfvf->netdev, "unsupported fec mode: %d", + fecparam->fec); + return -einval; + } + + if (fec == pfvf->linfo.fec) + return 0; + + mutex_lock(&mbox->lock); + req = otx2_mbox_alloc_msg_cgx_set_fec_param(&pfvf->mbox); + if (!req) { + err = -enomem; + goto end; + } + req->fec = fec; + err = otx2_sync_mbox_msg(&pfvf->mbox); + if (err) + goto end; + + rsp = (struct fec_mode *)otx2_mbox_get_rsp(&pfvf->mbox.mbox, + 0, &req->hdr); + if (rsp->fec >= 0) + pfvf->linfo.fec = rsp->fec; + else + err = rsp->fec; +end: + mutex_unlock(&mbox->lock); + return err; +} + + .get_fecparam = otx2_get_fecparam, + .set_fecparam = otx2_set_fecparam, diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c + case mbox_msg_cgx_fec_stats: + mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); + break;
|
Networking
|
d0cf9503e908ee7b235a5efecedeb74aabc482f3
|
christina jacob
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-af: physical link configuration support
|
cgx lmac, the physical interface support link configuration parameters like speed, auto negotiation, duplex etc. firmware saves these into memory region shared between firmware and this driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 5
| 113
| 3
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +static int cgx_link_usertable_index_map(int speed) +{ + switch (speed) { + case speed_10: + return cgx_link_10m; + case speed_100: + return cgx_link_100m; + case speed_1000: + return cgx_link_1g; + case speed_2500: + return cgx_link_2hg; + case speed_5000: + return cgx_link_5g; + case speed_10000: + return cgx_link_10g; + case speed_20000: + return cgx_link_20g; + case speed_25000: + return cgx_link_25g; + case speed_40000: + return cgx_link_40g; + case speed_50000: + return cgx_link_50g; + case 80000: + return cgx_link_80g; + case speed_100000: + return cgx_link_100g; + case speed_unknown: + return cgx_link_none; + } + return cgx_link_none; +} + + linfo->an = field_get(resp_linkstat_an, lstat); + if (err_type == cgx_err_speed_change_invalid) + return; + - id == cgx_cmd_link_bring_down) + id == cgx_cmd_link_bring_down || + id == cgx_cmd_mode_change) +int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, + int cgx_id, int lmac_id) +{ + struct cgx *cgx = cgxd; + u64 req = 0, resp; + + if (!cgx) + return -enodev; + + req = field_set(cmdreg_id, cgx_cmd_mode_change, req); + req = field_set(cmdmodechange_speed, + cgx_link_usertable_index_map(args.speed), req); + req = field_set(cmdmodechange_duplex, args.duplex, req); + req = field_set(cmdmodechange_an, args.an, req); + req = field_set(cmdmodechange_port, args.ports, req); + req = field_set(cmdmodechange_flags, args.flags, req); + return cgx_fwi_cmd_generic(req, &resp, cgx, lmac_id); +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h +int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args, + int cgx_id, int lmac_id); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h - cgx_err_spux_rsfec_algn_fail, /* = 22 */ + cgx_err_spux_rsfec_algn_fail, + cgx_err_spux_marker_lock_fail, + cgx_err_set_fec_invalid, + cgx_err_set_fec_fail, + cgx_err_module_invalid, + cgx_err_module_not_present, + cgx_err_speed_change_invalid, + cgx_link_80g, - cgx_cmd_link_state_change, + cgx_cmd_link_stat_change, +/* command argument to be passed for cmd id - cgx_cmd_mode_change */ +#define cmdmodechange_speed genmask_ull(11, 8) +#define cmdmodechange_duplex genmask_ull(12, 12) +#define cmdmodechange_an genmask_ull(13, 13) +#define cmdmodechange_port genmask_ull(21, 14) +#define cmdmodechange_flags genmask_ull(29, 22) + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +m(cgx_set_link_mode, 0x214, cgx_set_link_mode, cgx_set_link_mode_req,\ + cgx_set_link_mode_rsp) \ + uint64_t an:1; /* an supported or not */ +struct cgx_set_link_mode_args { + u32 speed; + u8 duplex; + u8 an; + u8 ports; + u8 flags; +}; + +struct cgx_set_link_mode_req { + struct mbox_msghdr hdr; + struct cgx_set_link_mode_args args; +}; + +struct cgx_set_link_mode_rsp { + struct mbox_msghdr hdr; + int status; +}; + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c + +int rvu_mbox_handler_cgx_set_link_mode(struct rvu *rvu, + struct cgx_set_link_mode_req *req, + struct cgx_set_link_mode_rsp *rsp) +{ + int pf = rvu_get_pf(req->hdr.pcifunc); + u8 cgx_idx, lmac; + void *cgxd; + + if (!is_cgx_config_permitted(rvu, req->hdr.pcifunc)) + return -eperm; + + rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_idx, &lmac); + cgxd = rvu_cgx_pdata(cgx_idx, rvu); + rsp->status = cgx_set_link_mode(cgxd, req->args, cgx_idx, lmac); + return 0; +}
|
Networking
|
56b6d539861358884debbe4bfb19ca0d86aaf0cb
|
christina jacob
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: advertised link modes support on cgx
|
cgx supports setting advertised link modes on physical link. this patch adds support to derive cgx mode from ethtool link mode and pass it to firmware to configure the same.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 3
| 146
| 3
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c +#include <linux/ethtool.h> + cgx_speed_mbps[cgx_link_80g] = 80000; +static void set_mod_args(struct cgx_set_link_mode_args *args, + u32 speed, u8 duplex, u8 autoneg, u64 mode) +{ + /* fill default values incase of user did not pass + * valid parameters + */ + if (args->duplex == duplex_unknown) + args->duplex = duplex; + if (args->speed == speed_unknown) + args->speed = speed; + if (args->an == autoneg_unknown) + args->an = autoneg; + args->mode = mode; + args->ports = 0; +} + +static void otx2_map_ethtool_link_modes(u64 bitmask, + struct cgx_set_link_mode_args *args) +{ + switch (bitmask) { + case ethtool_link_mode_10baset_half_bit: + set_mod_args(args, 10, 1, 1, bit_ull(cgx_mode_sgmii)); + break; + case ethtool_link_mode_10baset_full_bit: + set_mod_args(args, 10, 0, 1, bit_ull(cgx_mode_sgmii)); + break; + case ethtool_link_mode_100baset_half_bit: + set_mod_args(args, 100, 1, 1, bit_ull(cgx_mode_sgmii)); + break; + case ethtool_link_mode_100baset_full_bit: + set_mod_args(args, 100, 0, 1, bit_ull(cgx_mode_sgmii)); + break; + case ethtool_link_mode_1000baset_half_bit: + set_mod_args(args, 1000, 1, 1, bit_ull(cgx_mode_sgmii)); + break; + case ethtool_link_mode_1000baset_full_bit: + set_mod_args(args, 1000, 0, 1, bit_ull(cgx_mode_sgmii)); + break; + case ethtool_link_mode_1000basex_full_bit: + set_mod_args(args, 1000, 0, 0, bit_ull(cgx_mode_1000_basex)); + break; + case ethtool_link_mode_10000baset_full_bit: + set_mod_args(args, 1000, 0, 1, bit_ull(cgx_mode_qsgmii)); + break; + case ethtool_link_mode_10000basesr_full_bit: + set_mod_args(args, 10000, 0, 0, bit_ull(cgx_mode_10g_c2c)); + break; + case ethtool_link_mode_10000baselr_full_bit: + set_mod_args(args, 10000, 0, 0, bit_ull(cgx_mode_10g_c2m)); + break; + case ethtool_link_mode_10000basekr_full_bit: + set_mod_args(args, 10000, 0, 1, bit_ull(cgx_mode_10g_kr)); + break; + case ethtool_link_mode_25000basesr_full_bit: + set_mod_args(args, 25000, 0, 0, bit_ull(cgx_mode_25g_c2c)); + break; + case ethtool_link_mode_25000basecr_full_bit: + set_mod_args(args, 25000, 0, 1, bit_ull(cgx_mode_25g_cr)); + break; + case ethtool_link_mode_25000basekr_full_bit: + set_mod_args(args, 25000, 0, 1, bit_ull(cgx_mode_25g_kr)); + break; + case ethtool_link_mode_40000basesr4_full_bit: + set_mod_args(args, 40000, 0, 0, bit_ull(cgx_mode_40g_c2c)); + break; + case ethtool_link_mode_40000baselr4_full_bit: + set_mod_args(args, 40000, 0, 0, bit_ull(cgx_mode_40g_c2m)); + break; + case ethtool_link_mode_40000basecr4_full_bit: + set_mod_args(args, 40000, 0, 1, bit_ull(cgx_mode_40g_cr4)); + break; + case ethtool_link_mode_40000basekr4_full_bit: + set_mod_args(args, 40000, 0, 1, bit_ull(cgx_mode_40g_kr4)); + break; + case ethtool_link_mode_50000basesr_full_bit: + set_mod_args(args, 50000, 0, 0, bit_ull(cgx_mode_50g_c2c)); + break; + case ethtool_link_mode_50000baselr_er_fr_full_bit: + set_mod_args(args, 50000, 0, 0, bit_ull(cgx_mode_50g_c2m)); + break; + case ethtool_link_mode_50000basecr_full_bit: + set_mod_args(args, 50000, 0, 1, bit_ull(cgx_mode_50g_cr)); + break; + case ethtool_link_mode_50000basekr_full_bit: + set_mod_args(args, 50000, 0, 1, bit_ull(cgx_mode_50g_kr)); + break; + case ethtool_link_mode_100000basesr4_full_bit: + set_mod_args(args, 100000, 0, 0, bit_ull(cgx_mode_100g_c2c)); + break; + case ethtool_link_mode_100000baselr4_er4_full_bit: + set_mod_args(args, 100000, 0, 0, bit_ull(cgx_mode_100g_c2m)); + break; + case ethtool_link_mode_100000basecr4_full_bit: + set_mod_args(args, 100000, 0, 1, bit_ull(cgx_mode_100g_cr4)); + break; + case ethtool_link_mode_100000basekr4_full_bit: + set_mod_args(args, 100000, 0, 1, bit_ull(cgx_mode_100g_kr4)); + break; + default: + set_mod_args(args, 0, 1, 0, bit_ull(cgx_mode_max)); + break; + } +} + + if (args.mode) + otx2_map_ethtool_link_modes(args.mode, &args); + if (!args.speed && args.duplex && !args.an) + return -einval; + - req = field_set(cmdmodechange_flags, args.flags, req); + req = field_set(cmdmodechange_flags, args.mode, req); + diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h --- a/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h +enum cgx_mode_ { + cgx_mode_sgmii, + cgx_mode_1000_basex, + cgx_mode_qsgmii, + cgx_mode_10g_c2c, + cgx_mode_10g_c2m, + cgx_mode_10g_kr, + cgx_mode_20g_c2c, + cgx_mode_25g_c2c, + cgx_mode_25g_c2m, + cgx_mode_25g_2_c2c, + cgx_mode_25g_cr, + cgx_mode_25g_kr, + cgx_mode_40g_c2c, + cgx_mode_40g_c2m, + cgx_mode_40g_cr4, + cgx_mode_40g_kr4, + cgx_mode_40gaui_c2c, + cgx_mode_50g_c2c, + cgx_mode_50g_c2m, + cgx_mode_50g_4_c2c, + cgx_mode_50g_cr, + cgx_mode_50g_kr, + cgx_mode_80gaui_c2c, + cgx_mode_100g_c2c, + cgx_mode_100g_c2m, + cgx_mode_100g_cr4, + cgx_mode_100g_kr4, + cgx_mode_max /* = 29 */ +}; -#define cmdmodechange_flags genmask_ull(29, 22) +#define cmdmodechange_flags genmask_ull(63, 22) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h - u8 flags; + u64 mode; +#define autoneg_unknown 0xff
|
Networking
|
9d8711b25584160121c56c2d817036c6ef0c5b4c
|
christina jacob jesse brandeburg jesse brandeburg intel com
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-pf: ethtool physical link status
|
register get_link_ksettings callback to get link status information from the driver. as virtual function (vf) shares same physical link same api is used for both the drivers and for loop back drivers simply returns the fixed values as its does not have physical link.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['c']
| 1
| 158
| 0
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +#include <linux/linkmode.h> +/* physical link config */ +#define otx2_ethtool_supported_modes 0x638ccbf //110001110001100110010111111 + +enum link_mode { + otx2_mode_supported, + otx2_mode_advertised +}; + +static void otx2_get_fec_info(u64 index, int req_mode, + struct ethtool_link_ksettings *link_ksettings) +{ + __ethtool_declare_link_mode_mask(otx2_fec_modes) = { 0, }; + + switch (index) { + case otx2_fec_none: + linkmode_set_bit(ethtool_link_mode_fec_none_bit, + otx2_fec_modes); + break; + case otx2_fec_baser: + linkmode_set_bit(ethtool_link_mode_fec_baser_bit, + otx2_fec_modes); + break; + case otx2_fec_rs: + linkmode_set_bit(ethtool_link_mode_fec_rs_bit, + otx2_fec_modes); + break; + case otx2_fec_baser | otx2_fec_rs: + linkmode_set_bit(ethtool_link_mode_fec_baser_bit, + otx2_fec_modes); + linkmode_set_bit(ethtool_link_mode_fec_rs_bit, + otx2_fec_modes); + break; + } + + /* add fec modes to existing modes */ + if (req_mode == otx2_mode_advertised) + linkmode_or(link_ksettings->link_modes.advertising, + link_ksettings->link_modes.advertising, + otx2_fec_modes); + else + linkmode_or(link_ksettings->link_modes.supported, + link_ksettings->link_modes.supported, + otx2_fec_modes); +} + +static void otx2_get_link_mode_info(u64 link_mode_bmap, + bool req_mode, + struct ethtool_link_ksettings + *link_ksettings) +{ + __ethtool_declare_link_mode_mask(otx2_link_modes) = { 0, }; + const int otx2_sgmii_features[6] = { + ethtool_link_mode_10baset_half_bit, + ethtool_link_mode_10baset_full_bit, + ethtool_link_mode_100baset_half_bit, + ethtool_link_mode_100baset_full_bit, + ethtool_link_mode_1000baset_half_bit, + ethtool_link_mode_1000baset_full_bit, + }; + /* cgx link modes to ethtool link mode mapping */ + const int cgx_link_mode[27] = { + 0, /* sgmii mode */ + ethtool_link_mode_1000basex_full_bit, + ethtool_link_mode_10000baset_full_bit, + ethtool_link_mode_10000basesr_full_bit, + ethtool_link_mode_10000baselr_full_bit, + ethtool_link_mode_10000basekr_full_bit, + 0, + ethtool_link_mode_25000basesr_full_bit, + 0, + 0, + ethtool_link_mode_25000basecr_full_bit, + ethtool_link_mode_25000basekr_full_bit, + ethtool_link_mode_40000basesr4_full_bit, + ethtool_link_mode_40000baselr4_full_bit, + ethtool_link_mode_40000basecr4_full_bit, + ethtool_link_mode_40000basekr4_full_bit, + 0, + ethtool_link_mode_50000basesr_full_bit, + 0, + ethtool_link_mode_50000baselr_er_fr_full_bit, + ethtool_link_mode_50000basecr_full_bit, + ethtool_link_mode_50000basekr_full_bit, + 0, + ethtool_link_mode_100000basesr4_full_bit, + ethtool_link_mode_100000baselr4_er4_full_bit, + ethtool_link_mode_100000basecr4_full_bit, + ethtool_link_mode_100000basekr4_full_bit + }; + u8 bit; + + link_mode_bmap = link_mode_bmap & otx2_ethtool_supported_modes; + + for_each_set_bit(bit, (unsigned long *)&link_mode_bmap, 27) { + /* sgmii mode is set */ + if (bit == 0) + linkmode_set_bit_array(otx2_sgmii_features, + array_size(otx2_sgmii_features), + otx2_link_modes); + else + linkmode_set_bit(cgx_link_mode[bit], otx2_link_modes); + } + + if (req_mode == otx2_mode_advertised) + linkmode_copy(link_ksettings->link_modes.advertising, + otx2_link_modes); + else + linkmode_copy(link_ksettings->link_modes.supported, + otx2_link_modes); +} + +static int otx2_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *cmd) +{ + struct otx2_nic *pfvf = netdev_priv(netdev); + struct cgx_fw_data *rsp = null; + + cmd->base.duplex = pfvf->linfo.full_duplex; + cmd->base.speed = pfvf->linfo.speed; + cmd->base.autoneg = pfvf->linfo.an; + + rsp = otx2_get_fwdata(pfvf); + if (is_err(rsp)) + return ptr_err(rsp); + + if (rsp->fwdata.supported_an) + ethtool_link_ksettings_add_link_mode(cmd, + supported, + autoneg); + + otx2_get_link_mode_info(rsp->fwdata.advertised_link_modes, + otx2_mode_advertised, cmd); + otx2_get_fec_info(rsp->fwdata.advertised_fec, + otx2_mode_advertised, cmd); + otx2_get_link_mode_info(rsp->fwdata.supported_link_modes, + otx2_mode_supported, cmd); + otx2_get_fec_info(rsp->fwdata.supported_fec, + otx2_mode_supported, cmd); + return 0; +} + + .get_link_ksettings = otx2_get_link_ksettings, +static int otx2vf_get_link_ksettings(struct net_device *netdev, + struct ethtool_link_ksettings *cmd) +{ + struct otx2_nic *pfvf = netdev_priv(netdev); + + if (is_otx2_lbkvf(pfvf->pdev)) { + cmd->base.duplex = duplex_full; + cmd->base.speed = speed_100000; + } else { + return otx2_get_link_ksettings(netdev, cmd); + } + return 0; +} + + .get_link_ksettings = otx2vf_get_link_ksettings,
|
Networking
|
1a50280c25ecfb1243e40eb3e9d3404cbc754d7a
|
christina jacob
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-pf: ethtool physical link configuration
|
register set_link_ksetting callback with driver such that link configurations parameters like advertised mode,speed, duplex and autoneg can be configured.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
ethtool support for fec and link configuration
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['c']
| 1
| 63
| 0
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +static void otx2_get_advertised_mode(const struct ethtool_link_ksettings *cmd, + u64 *mode) +{ + u32 bit_pos; + + /* firmware does not support requesting multiple advertised modes + * return first set bit + */ + bit_pos = find_first_bit(cmd->link_modes.advertising, + __ethtool_link_mode_mask_nbits); + if (bit_pos != __ethtool_link_mode_mask_nbits) + *mode = bit_pos; +} + +static int otx2_set_link_ksettings(struct net_device *netdev, + const struct ethtool_link_ksettings *cmd) +{ + struct otx2_nic *pf = netdev_priv(netdev); + struct ethtool_link_ksettings cur_ks; + struct cgx_set_link_mode_req *req; + struct mbox *mbox = &pf->mbox; + int err = 0; + + memset(&cur_ks, 0, sizeof(struct ethtool_link_ksettings)); + + if (!ethtool_validate_speed(cmd->base.speed) || + !ethtool_validate_duplex(cmd->base.duplex)) + return -einval; + + if (cmd->base.autoneg != autoneg_enable && + cmd->base.autoneg != autoneg_disable) + return -einval; + + otx2_get_link_ksettings(netdev, &cur_ks); + + /* check requested modes against supported modes by hardware */ + if (!bitmap_subset(cmd->link_modes.advertising, + cur_ks.link_modes.supported, + __ethtool_link_mode_mask_nbits)) + return -einval; + + mutex_lock(&mbox->lock); + req = otx2_mbox_alloc_msg_cgx_set_link_mode(&pf->mbox); + if (!req) { + err = -enomem; + goto end; + } + + req->args.speed = cmd->base.speed; + /* firmware expects 1 for half duplex and 0 for full duplex + * hence inverting + */ + req->args.duplex = cmd->base.duplex ^ 0x1; + req->args.an = cmd->base.autoneg; + otx2_get_advertised_mode(cmd, &req->args.mode); + + err = otx2_sync_mbox_msg(&pf->mbox); +end: + mutex_unlock(&mbox->lock); + return err; +} + + .set_link_ksettings = otx2_set_link_ksettings,
|
Networking
|
cff713ce6c1307f0701cf905e05c944d75369dbc
|
christina jacob
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-af: mailbox changes for 98xx cpt block
|
this patch changes cpt mailbox message format to support new block cpt1 in 98xx silicon.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support for octeontx2 98xx cpt block
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 2
| 27
| 16
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h + int blkaddr; + int blkaddr; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c + blkaddr = req->blkaddr ? req->blkaddr : blkaddr_cpt0; + if (blkaddr != blkaddr_cpt0 && blkaddr != blkaddr_cpt1) + return -enodev; + - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return blkaddr; - -int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req, - struct msg_rsp *rsp) +static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr) + int num_lfs, cptlf, slot; - int cptlf, blkaddr; - int num_lfs, slot; - - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return blkaddr; - return cpt_af_err_lf_invalid; + return 0; +int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req, + struct msg_rsp *rsp) +{ + int ret; + + ret = cpt_lf_free(rvu, req, blkaddr_cpt0); + if (ret) + return ret; + + if (is_block_implemented(rvu->hw, blkaddr_cpt1)) + ret = cpt_lf_free(rvu, req, blkaddr_cpt1); + + return ret; +} + - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return blkaddr; + blkaddr = req->blkaddr ? req->blkaddr : blkaddr_cpt0; + if (blkaddr != blkaddr_cpt0 && blkaddr != blkaddr_cpt1) + return -enodev;
|
Networking
|
de2854c87c64788f94e34217d06e60422e4a1842
|
srujana challa
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: add support for cpt1 in debugfs
|
adds support to display block cpt1 stats at "/sys/kernel/debug/octeontx2/cpt1".
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support for octeontx2 98xx cpt block
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 2
| 49
| 44
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +#define max_cpt_blks 2 +struct cpt_ctx { + int blkaddr; + struct rvu *rvu; +}; + + struct cpt_ctx cpt_ctx[max_cpt_blks]; diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c -/* cpt debugfs apis */ - struct rvu *rvu = filp->private; + struct cpt_ctx *ctx = filp->private; - int blkaddr; + struct rvu *rvu = ctx->rvu; + int blkaddr = ctx->blkaddr; - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return -enodev; - - struct rvu *rvu = filp->private; + struct cpt_ctx *ctx = filp->private; + struct rvu *rvu = ctx->rvu; + int blkaddr = ctx->blkaddr; - int blkaddr; - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return -enodev; - - struct rvu *rvu = filp->private; - struct rvu_hwinfo *hw = rvu->hw; + struct cpt_ctx *ctx = filp->private; + int blkaddr = ctx->blkaddr; + struct rvu *rvu = ctx->rvu; - int blkaddr; + struct rvu_hwinfo *hw; - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return -enodev; - + hw = rvu->hw; - struct rvu *rvu = filp->private; + struct cpt_ctx *ctx = filp->private; + struct rvu *rvu = ctx->rvu; + int blkaddr = ctx->blkaddr; - int blkaddr; - - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return -enodev; - struct rvu *rvu; - int blkaddr; + struct cpt_ctx *ctx = filp->private; + struct rvu *rvu = ctx->rvu; + int blkaddr = ctx->blkaddr; - rvu = filp->private; - blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, 0); - if (blkaddr < 0) - return -enodev; - -static void rvu_dbg_cpt_init(struct rvu *rvu) +static void rvu_dbg_cpt_init(struct rvu *rvu, int blkaddr) - if (!is_block_implemented(rvu->hw, blkaddr_cpt0)) + struct cpt_ctx *ctx; + + if (!is_block_implemented(rvu->hw, blkaddr)) - rvu->rvu_dbg.cpt = debugfs_create_dir("cpt", rvu->rvu_dbg.root); + if (blkaddr == blkaddr_cpt0) { + rvu->rvu_dbg.cpt = debugfs_create_dir("cpt", rvu->rvu_dbg.root); + ctx = &rvu->rvu_dbg.cpt_ctx[0]; + ctx->blkaddr = blkaddr_cpt0; + ctx->rvu = rvu; + } else { + rvu->rvu_dbg.cpt = debugfs_create_dir("cpt1", + rvu->rvu_dbg.root); + ctx = &rvu->rvu_dbg.cpt_ctx[1]; + ctx->blkaddr = blkaddr_cpt1; + ctx->rvu = rvu; + } - debugfs_create_file("cpt_pc", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_pc", 0600, rvu->rvu_dbg.cpt, ctx, - debugfs_create_file("cpt_ae_sts", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_ae_sts", 0600, rvu->rvu_dbg.cpt, ctx, - debugfs_create_file("cpt_se_sts", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_se_sts", 0600, rvu->rvu_dbg.cpt, ctx, - debugfs_create_file("cpt_ie_sts", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_ie_sts", 0600, rvu->rvu_dbg.cpt, ctx, - debugfs_create_file("cpt_engines_info", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_engines_info", 0600, rvu->rvu_dbg.cpt, ctx, - debugfs_create_file("cpt_lfs_info", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_lfs_info", 0600, rvu->rvu_dbg.cpt, ctx, - debugfs_create_file("cpt_err_info", 0600, rvu->rvu_dbg.cpt, rvu, + debugfs_create_file("cpt_err_info", 0600, rvu->rvu_dbg.cpt, ctx, - rvu_dbg_cpt_init(rvu); + rvu_dbg_cpt_init(rvu, blkaddr_cpt0); + rvu_dbg_cpt_init(rvu, blkaddr_cpt1);
|
Networking
|
b0f60fab7805cb013311ede0127f8abbf1bdc986
|
srujana challa
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: handle cpt function level reset
|
when flr is initiated for a vf (pci function level reset), the parent pf gets a interrupt. pf then sends a message to admin function (af), which then cleans up all resources attached to that vf. this patch adds support to handle cpt flr.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support for octeontx2 98xx cpt block
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 4
| 102
| 0
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c + else if ((block->addr == blkaddr_cpt0) || + (block->addr == blkaddr_cpt1)) + rvu_cpt_lf_teardown(rvu, pcifunc, lf, slot); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +/* cpt apis */ +int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c + +#define inprog_inflight(reg) ((reg) & 0x1ff) +#define inprog_grb_partial(reg) ((reg) & bit_ull(31)) +#define inprog_grb(reg) (((reg) >> 32) & 0xff) +#define inprog_gwb(reg) (((reg) >> 40) & 0xff) + +static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot) +{ + int i = 0, hard_lp_ctr = 100000; + u64 inprog, grp_ptr; + u16 nq_ptr, dq_ptr; + + /* disable instructions enqueuing */ + rvu_write64(rvu, blkaddr, cpt_af_bar2_aliasx(slot, cpt_lf_ctl), 0x0); + + /* disable executions in the lf's queue */ + inprog = rvu_read64(rvu, blkaddr, + cpt_af_bar2_aliasx(slot, cpt_lf_inprog)); + inprog &= ~bit_ull(16); + rvu_write64(rvu, blkaddr, + cpt_af_bar2_aliasx(slot, cpt_lf_inprog), inprog); + + /* wait for cpt queue to become execution-quiescent */ + do { + inprog = rvu_read64(rvu, blkaddr, + cpt_af_bar2_aliasx(slot, cpt_lf_inprog)); + if (inprog_grb_partial(inprog)) { + i = 0; + hard_lp_ctr--; + } else { + i++; + } + + grp_ptr = rvu_read64(rvu, blkaddr, + cpt_af_bar2_aliasx(slot, + cpt_lf_q_grp_ptr)); + nq_ptr = (grp_ptr >> 32) & 0x7fff; + dq_ptr = grp_ptr & 0x7fff; + + } while (hard_lp_ctr && (i < 10) && (nq_ptr != dq_ptr)); + + if (hard_lp_ctr == 0) + dev_warn(rvu->dev, "cpt flr hits hard loop counter "); + + i = 0; + hard_lp_ctr = 100000; + do { + inprog = rvu_read64(rvu, blkaddr, + cpt_af_bar2_aliasx(slot, cpt_lf_inprog)); + + if ((inprog_inflight(inprog) == 0) && + (inprog_gwb(inprog) < 40) && + ((inprog_grb(inprog) == 0) || + (inprog_grb((inprog)) == 40))) { + i++; + } else { + i = 0; + hard_lp_ctr--; + } + } while (hard_lp_ctr && (i < 10)); + + if (hard_lp_ctr == 0) + dev_warn(rvu->dev, "cpt flr hits hard loop counter "); +} + +int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int lf, int slot) +{ + int blkaddr; + u64 reg; + + blkaddr = rvu_get_blkaddr(rvu, blktype_cpt, pcifunc); + if (blkaddr != blkaddr_cpt0 && blkaddr != blkaddr_cpt1) + return -einval; + + /* enable bar2 alias for this pcifunc. */ + reg = bit_ull(16) | pcifunc; + rvu_write64(rvu, blkaddr, cpt_af_bar2_sel, reg); + + cpt_lf_disable_iqueue(rvu, blkaddr, slot); + + /* set group drop to help clear out hardware */ + reg = rvu_read64(rvu, blkaddr, cpt_af_bar2_aliasx(slot, cpt_lf_inprog)); + reg |= bit_ull(17); + rvu_write64(rvu, blkaddr, cpt_af_bar2_aliasx(slot, cpt_lf_inprog), reg); + + rvu_write64(rvu, blkaddr, cpt_af_bar2_sel, 0); + + return 0; +} diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h +#define af_bar2_aliasx(a, b) (0x9100000ull | (a) << 12 | (b)) +#define cpt_af_bar2_sel 0x9000000 +#define cpt_af_bar2_aliasx(a, b) af_bar2_aliasx(a, b) + +#define cpt_lf_ctl 0x10 +#define cpt_lf_inprog 0x40 +#define cpt_lf_q_grp_ptr 0x120 +
|
Networking
|
c57c58fd5c4fd288f5aca0970982c9bd547d6288
|
srujana challa
|
drivers
|
net
|
af, ethernet, marvell, octeontx2
|
octeontx2-af: support esp/ah rss hashing
|
support spi and sequence number fields of esp/ah header to be hashed for rss. by default esp/ah fields are not considered for rss and needs to be set explicitly as below: ethtool -u eth0 rx-flow-hash esp4 sdfn or ethtool -u eth0 rx-flow-hash ah4 sdfn or ethtool -u eth0 rx-flow-hash esp6 sdfn or ethtool -u eth0 rx-flow-hash ah6 sdfn
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support esp/ah rss hashing
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 3
| 65
| 1
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +#define nix_flow_key_type_ah bit(22) +#define nix_flow_key_type_esp bit(23) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c + int l4_key_offset; + + /* tcp/udp/sctp and esp/ah falls at same offset so + * remember the tcp key offset of 40 byte hash key. + */ + if (key_type == nix_flow_key_type_tcp) + l4_key_offset = key_off; + case nix_flow_key_type_ah: + case nix_flow_key_type_esp: + field->hdr_offset = 0; + field->bytesm1 = 7; /* spi + sequence number */ + field->ltype_mask = 0xf; + field->lid = npc_lid_le; + field->ltype_match = npc_lt_le_esp; + if (key_type == nix_flow_key_type_ah) { + field->lid = npc_lid_ld; + field->ltype_match = npc_lt_ld_ah; + field->hdr_offset = 4; + keyoff_marker = false; + } + break; + /* use the key offset of tcp/udp/sctp fields + * for esp/ah fields. + */ + if (key_type == nix_flow_key_type_esp || + key_type == nix_flow_key_type_ah) + key_off = l4_key_offset; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c + case ah_esp_v6_flow: + if (rss->flowkey_cfg & nix_flow_key_type_esp) + nfc->data |= rxh_l4_b_0_1 | rxh_l4_b_2_3; + break; - case ah_esp_v6_flow: + break; + + case ah_esp_v4_flow: + case ah_esp_v6_flow: + switch (nfc->data & rxh_l4) { + case 0: + rss_cfg &= ~(nix_flow_key_type_esp | + nix_flow_key_type_ah); + rss_cfg |= nix_flow_key_type_vlan | + nix_flow_key_type_ipv4_proto; + break; + case (rxh_l4_b_0_1 | rxh_l4_b_2_3): + /* if vlan hashing is also requested for esp then do not + * allow because of hardware 40 bytes flow key limit. + */ + if (rss_cfg & nix_flow_key_type_vlan) { + netdev_err(pfvf->netdev, + "rss hash of esp or ah with vlan is not supported "); + return -eopnotsupp; + } + + rss_cfg |= nix_flow_key_type_esp | nix_flow_key_type_ah; + /* disable ipv4 proto hashing since ipv6 sa+da(32 bytes) + * and esp spi+sequence(8 bytes) uses hardware maximum + * limit of 40 byte flow key. + */ + rss_cfg &= ~nix_flow_key_type_ipv4_proto; + break; + default: + return -einval; + } + break;
|
Networking
|
b9b7421a01d82c474227fce04f0468f1c70be306
|
subbaraya sundeep
|
drivers
|
net
|
af, ethernet, marvell, nic, octeontx2
|
octeontx2-pf: add rss multi group support
|
hardware supports 8 rss groups per interface. currently we are using only group '0'. this patch allows user to create new rss groups/contexts and use the same as destination for flow steering rules.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add rss multi group support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 4
| 163
| 44
|
- fixed compiletime warning. - address saeed's comments on v3. - coverted otx2_set_rxfh() to use new function. - removed unrelated whitespace - coverted otx2_get_rxfh() to use new function. --- diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.c -int otx2_set_rss_table(struct otx2_nic *pfvf) +int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id) + const int index = rss->rss_size * ctx_id; + struct otx2_rss_ctx *rss_ctx; + rss_ctx = rss->rss_ctx[ctx_id]; - aq->rss.rq = rss->ind_tbl[idx]; + aq->rss.rq = rss_ctx->ind_tbl[idx]; - aq->qidx = idx; + aq->qidx = index + idx; + struct otx2_rss_ctx *rss_ctx; - rss->rss_size = sizeof(rss->ind_tbl); + rss->rss_size = sizeof(*rss->rss_ctx[default_rss_context_group]); - /* default indirection table */ + /* set rss group 0 as default indirection table */ + rss->rss_ctx[default_rss_context_group] = kzalloc(rss->rss_size, + gfp_kernel); + if (!rss->rss_ctx[default_rss_context_group]) + return -enomem; + + rss_ctx = rss->rss_ctx[default_rss_context_group]; - rss->ind_tbl[idx] = + rss_ctx->ind_tbl[idx] = - ret = otx2_set_rss_table(pfvf); + ret = otx2_set_rss_table(pfvf, default_rss_context_group); - nixlf->rss_grps = 1; /* single rss indir table supported, for now */ + nixlf->rss_grps = max_rss_groups; diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h +struct otx2_rss_ctx { + u8 ind_tbl[max_rss_indir_tbl_size]; +}; + - u8 ind_tbl[max_rss_indir_tbl_size]; + struct otx2_rss_ctx *rss_ctx[max_rss_groups]; -int otx2_set_rss_table(struct otx2_nic *pfvf); +int otx2_set_rss_table(struct otx2_nic *pfvf, int ctx_id); - struct ethtool_rx_flow_spec *fsp); + struct ethtool_rxnfc *nfc); +void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id); diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c - ret = otx2_add_flow(pfvf, &nfc->fs); + ret = otx2_add_flow(pfvf, nfc); - struct otx2_nic *pfvf = netdev_priv(dev); - - return pfvf->hw.rss_info.rss_size; + return max_rss_indir_tbl_size; -/* get rss configuration */ -static int otx2_get_rxfh(struct net_device *dev, u32 *indir, - u8 *hkey, u8 *hfunc) +static int otx2_rss_ctx_delete(struct otx2_nic *pfvf, int ctx_id) - struct otx2_nic *pfvf = netdev_priv(dev); - struct otx2_rss_info *rss; - int idx; + struct otx2_rss_info *rss = &pfvf->hw.rss_info; - rss = &pfvf->hw.rss_info; + otx2_rss_ctx_flow_del(pfvf, ctx_id); + kfree(rss->rss_ctx[ctx_id]); + rss->rss_ctx[ctx_id] = null; - if (indir) { - for (idx = 0; idx < rss->rss_size; idx++) - indir[idx] = rss->ind_tbl[idx]; - } + return 0; +} - if (hkey) - memcpy(hkey, rss->key, sizeof(rss->key)); +static int otx2_rss_ctx_create(struct otx2_nic *pfvf, + u32 *rss_context) +{ + struct otx2_rss_info *rss = &pfvf->hw.rss_info; + u8 ctx; - if (hfunc) - *hfunc = eth_rss_hash_top; + for (ctx = 0; ctx < max_rss_groups; ctx++) { + if (!rss->rss_ctx[ctx]) + break; + } + if (ctx == max_rss_groups) + return -einval; + + rss->rss_ctx[ctx] = kzalloc(sizeof(*rss->rss_ctx[ctx]), gfp_kernel); + if (!rss->rss_ctx[ctx]) + return -enomem; + *rss_context = ctx; -/* configure rss table and hash key */ -static int otx2_set_rxfh(struct net_device *dev, const u32 *indir, - const u8 *hkey, const u8 hfunc) +/* rss context configuration */ +static int otx2_set_rxfh_context(struct net_device *dev, const u32 *indir, + const u8 *hkey, const u8 hfunc, + u32 *rss_context, bool delete) + struct otx2_rss_ctx *rss_ctx; - int idx; + int ret, idx; + if (hkey) { + memcpy(rss->key, hkey, sizeof(rss->key)); + otx2_set_rss_key(pfvf); + } + if (delete) + return otx2_rss_ctx_delete(pfvf, *rss_context); + + if (*rss_context == eth_rxfh_context_alloc) { + ret = otx2_rss_ctx_create(pfvf, rss_context); + if (ret) + return ret; + } + rss_ctx = rss->rss_ctx[*rss_context]; - rss->ind_tbl[idx] = indir[idx]; + rss_ctx->ind_tbl[idx] = indir[idx]; + otx2_set_rss_table(pfvf, *rss_context); - if (hkey) { - memcpy(rss->key, hkey, sizeof(rss->key)); - otx2_set_rss_key(pfvf); + return 0; +} + +static int otx2_get_rxfh_context(struct net_device *dev, u32 *indir, + u8 *hkey, u8 *hfunc, u32 rss_context) +{ + struct otx2_nic *pfvf = netdev_priv(dev); + struct otx2_rss_ctx *rss_ctx; + struct otx2_rss_info *rss; + int idx, rx_queues; + + rss = &pfvf->hw.rss_info; + + if (hfunc) + *hfunc = eth_rss_hash_top; + + if (!indir) + return 0; + + if (!rss->enable && rss_context == default_rss_context_group) { + rx_queues = pfvf->hw.rx_queues; + for (idx = 0; idx < max_rss_indir_tbl_size; idx++) + indir[idx] = ethtool_rxfh_indir_default(idx, rx_queues); + return 0; + } + if (rss_context >= max_rss_groups) + return -enoent; + + rss_ctx = rss->rss_ctx[rss_context]; + if (!rss_ctx) + return -enoent; + + if (indir) { + for (idx = 0; idx < rss->rss_size; idx++) + indir[idx] = rss_ctx->ind_tbl[idx]; + if (hkey) + memcpy(hkey, rss->key, sizeof(rss->key)); - otx2_set_rss_table(pfvf); +/* get rss configuration */ +static int otx2_get_rxfh(struct net_device *dev, u32 *indir, + u8 *hkey, u8 *hfunc) +{ + return otx2_get_rxfh_context(dev, indir, hkey, hfunc, + default_rss_context_group); +} + +/* configure rss table and hash key */ +static int otx2_set_rxfh(struct net_device *dev, const u32 *indir, + const u8 *hkey, const u8 hfunc) +{ + + u32 rss_context = default_rss_context_group; + + return otx2_set_rxfh_context(dev, indir, hkey, hfunc, &rss_context, 0); +} + + .get_rxfh_context = otx2_get_rxfh_context, + .set_rxfh_context = otx2_set_rxfh_context, + .get_rxfh_context = otx2_get_rxfh_context, + .set_rxfh_context = otx2_set_rxfh_context, diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c + u8 rss_ctx_id; + nfc->rss_context = iter->rss_ctx_id; - flow_type = fsp->flow_type & ~(flow_ext | flow_mac_ext); + flow_type = fsp->flow_type & ~(flow_ext | flow_mac_ext | flow_rss); - if (req->op != nix_rx_action_default) + if (flow->flow_spec.flow_type & flow_rss) { + req->op = nix_rx_actionop_rss; + req->index = flow->rss_ctx_id; + } else { - req->index = ethtool_get_flow_spec_ring(ring_cookie); + req->index = ethtool_get_flow_spec_ring(ring_cookie); + } -int otx2_add_flow(struct otx2_nic *pfvf, struct ethtool_rx_flow_spec *fsp) +int otx2_add_flow(struct otx2_nic *pfvf, struct ethtool_rxnfc *nfc) - u32 ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); + struct ethtool_rx_flow_spec *fsp = &nfc->fs; + u32 ring; + ring = ethtool_get_flow_spec_ring(fsp->ring_cookie); + if (fsp->flow_type & flow_rss) + flow->rss_ctx_id = nfc->rss_context; + +void otx2_rss_ctx_flow_del(struct otx2_nic *pfvf, int ctx_id) +{ + struct otx2_flow *flow, *tmp; + int err; + + list_for_each_entry_safe(flow, tmp, &pfvf->flow_cfg->flow_list, list) { + if (flow->rss_ctx_id != ctx_id) + continue; + err = otx2_remove_flow(pfvf, flow->location); + if (err) + netdev_warn(pfvf->netdev, + "can't delete the rule %d associated with this rss group err:%d", + flow->location, err); + } +} +
|
Networking
|
81a4362016e7d8b17031fe1aa43cdb58a7f0f163
|
geetha sowjanya
|
drivers
|
net
|
ethernet, marvell, nic, octeontx2
|
octeontx2-pf: add flow classification using ip next level protocol
|
this patch adds support to install flow rules using ipv4 proto or ipv6 next header field to distinguish between tcp/udp/sctp/esp/ah flows when user doesn't specify the other match creteria related to the flow such as tcp/udp/sctp source port and destination port, ah/esp spi value. this is achieved by matching the layer type extracted by npc hw into the search key. modified the driver to use ethertype as match criteria when user doesn't specify source ip address and dest ip address. the esp/ah flow rule matching using security parameter index (spi) is not supported as of now since the field is not extracted into mcam search key. modified npc_check_field function to return bool.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add flow classification using ip next level protocol
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['octeontx2-af ']
|
['h', 'c']
| 4
| 153
| 21
|
--- diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h b/drivers/net/ethernet/marvell/octeontx2/af/npc.h --- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h + npc_ipproto_tcp, + npc_ipproto_udp, + npc_ipproto_sctp, + npc_ipproto_ah, + npc_ipproto_esp, diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c + seq_puts(s, " "); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc_fs.c + [npc_ipproto_tcp] = "ip proto tcp", + [npc_ipproto_udp] = "ip proto udp", + [npc_ipproto_sctp] = "ip proto sctp", + [npc_ipproto_ah] = "ip proto ah", + [npc_ipproto_esp] = "ip proto esp", -static int npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, - u8 intf) +static bool npc_check_field(struct rvu *rvu, int blkaddr, enum key_fields type, + u8 intf) - return -eopnotsupp; - return 0; + return false; + return true; - int err, hdr; + int hdr; - err = npc_check_field(rvu, blkaddr, hdr, intf); - if (!err) + if (npc_check_field(rvu, blkaddr, hdr, intf)) - if (*features & tcp_udp_sctp) - if (npc_check_field(rvu, blkaddr, npc_ld, intf)) + if (*features & tcp_udp_sctp) { + if (!npc_check_field(rvu, blkaddr, npc_ld, intf)) + else + *features |= bit_ull(npc_ipproto_tcp) | + bit_ull(npc_ipproto_udp) | + bit_ull(npc_ipproto_sctp); + } + + /* for ah, check if corresponding layer type is present in the key */ + if (npc_check_field(rvu, blkaddr, npc_ld, intf)) + *features |= bit_ull(npc_ipproto_ah); + + /* for esp, check if corresponding layer type is present in the key */ + if (npc_check_field(rvu, blkaddr, npc_le, intf)) + *features |= bit_ull(npc_ipproto_esp); - if (npc_check_field(rvu, blkaddr, npc_lb, intf)) + if (!npc_check_field(rvu, blkaddr, npc_lb, intf)) - if (features & (bit_ull(npc_sport_tcp) | bit_ull(npc_dport_tcp))) + if (features & bit_ull(npc_ipproto_tcp)) - if (features & (bit_ull(npc_sport_udp) | bit_ull(npc_dport_udp))) + if (features & bit_ull(npc_ipproto_udp)) - if (features & (bit_ull(npc_sport_sctp) | bit_ull(npc_dport_sctp))) + if (features & bit_ull(npc_ipproto_sctp)) + /* for ah, ltype should be present in entry */ + if (features & bit_ull(npc_ipproto_ah)) + npc_update_entry(rvu, npc_ld, entry, npc_lt_ld_ah, + 0, ~0ull, 0, intf); + /* for esp, ltype should be present in entry */ + if (features & bit_ull(npc_ipproto_esp)) + npc_update_entry(rvu, npc_le, entry, npc_lt_le_esp, + 0, ~0ull, 0, intf); + diff --git a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_flows.c -static void otx2_prepare_ipv4_flow(struct ethtool_rx_flow_spec *fsp, - struct npc_install_flow_req *req, - u32 flow_type) +static int otx2_prepare_ipv4_flow(struct ethtool_rx_flow_spec *fsp, + struct npc_install_flow_req *req, + u32 flow_type) + struct ethtool_ah_espip4_spec *ah_esp_hdr = &fsp->h_u.ah_ip4_spec; + struct ethtool_ah_espip4_spec *ah_esp_mask = &fsp->m_u.ah_ip4_spec; + pkt->etype = cpu_to_be16(eth_p_ip); + pmask->etype = cpu_to_be16(0xffff); + req->features |= bit_ull(npc_etype); + pkt->etype = cpu_to_be16(eth_p_ip); + pmask->etype = cpu_to_be16(0xffff); + req->features |= bit_ull(npc_etype); + if (flow_type == udp_v4_flow) + req->features |= bit_ull(npc_ipproto_udp); + else if (flow_type == tcp_v4_flow) + req->features |= bit_ull(npc_ipproto_tcp); + else + req->features |= bit_ull(npc_ipproto_sctp); + break; + case ah_v4_flow: + case esp_v4_flow: + pkt->etype = cpu_to_be16(eth_p_ip); + pmask->etype = cpu_to_be16(0xffff); + req->features |= bit_ull(npc_etype); + if (ah_esp_mask->ip4src) { + memcpy(&pkt->ip4src, &ah_esp_hdr->ip4src, + sizeof(pkt->ip4src)); + memcpy(&pmask->ip4src, &ah_esp_mask->ip4src, + sizeof(pmask->ip4src)); + req->features |= bit_ull(npc_sip_ipv4); + } + if (ah_esp_mask->ip4dst) { + memcpy(&pkt->ip4dst, &ah_esp_hdr->ip4dst, + sizeof(pkt->ip4dst)); + memcpy(&pmask->ip4dst, &ah_esp_mask->ip4dst, + sizeof(pmask->ip4dst)); + req->features |= bit_ull(npc_dip_ipv4); + } + + /* npc profile doesn't extract ah/esp header fields */ + if ((ah_esp_mask->spi & ah_esp_hdr->spi) || + (ah_esp_mask->tos & ah_esp_mask->tos)) + return -eopnotsupp; + + if (flow_type == ah_v4_flow) + req->features |= bit_ull(npc_ipproto_ah); + else + req->features |= bit_ull(npc_ipproto_esp); + + return 0; -static void otx2_prepare_ipv6_flow(struct ethtool_rx_flow_spec *fsp, - struct npc_install_flow_req *req, - u32 flow_type) +static int otx2_prepare_ipv6_flow(struct ethtool_rx_flow_spec *fsp, + struct npc_install_flow_req *req, + u32 flow_type) + struct ethtool_ah_espip6_spec *ah_esp_hdr = &fsp->h_u.ah_ip6_spec; + struct ethtool_ah_espip6_spec *ah_esp_mask = &fsp->m_u.ah_ip6_spec; + pkt->etype = cpu_to_be16(eth_p_ipv6); + pmask->etype = cpu_to_be16(0xffff); + req->features |= bit_ull(npc_etype); + pkt->etype = cpu_to_be16(eth_p_ipv6); + pmask->etype = cpu_to_be16(0xffff); + req->features |= bit_ull(npc_etype); + if (flow_type == udp_v6_flow) + req->features |= bit_ull(npc_ipproto_udp); + else if (flow_type == tcp_v6_flow) + req->features |= bit_ull(npc_ipproto_tcp); + else + req->features |= bit_ull(npc_ipproto_sctp); + case ah_v6_flow: + case esp_v6_flow: + pkt->etype = cpu_to_be16(eth_p_ipv6); + pmask->etype = cpu_to_be16(0xffff); + req->features |= bit_ull(npc_etype); + if (!ipv6_addr_any((struct in6_addr *)ah_esp_hdr->ip6src)) { + memcpy(&pkt->ip6src, &ah_esp_hdr->ip6src, + sizeof(pkt->ip6src)); + memcpy(&pmask->ip6src, &ah_esp_mask->ip6src, + sizeof(pmask->ip6src)); + req->features |= bit_ull(npc_sip_ipv6); + } + if (!ipv6_addr_any((struct in6_addr *)ah_esp_hdr->ip6dst)) { + memcpy(&pkt->ip6dst, &ah_esp_hdr->ip6dst, + sizeof(pkt->ip6dst)); + memcpy(&pmask->ip6dst, &ah_esp_mask->ip6dst, + sizeof(pmask->ip6dst)); + req->features |= bit_ull(npc_dip_ipv6); + } + + /* npc profile doesn't extract ah/esp header fields */ + if ((ah_esp_mask->spi & ah_esp_hdr->spi) || + (ah_esp_mask->tclass & ah_esp_mask->tclass)) + return -eopnotsupp; + + if (flow_type == ah_v6_flow) + req->features |= bit_ull(npc_ipproto_ah); + else + req->features |= bit_ull(npc_ipproto_esp); + + return 0; + int ret; - otx2_prepare_ipv4_flow(fsp, req, flow_type); + case ah_v4_flow: + case esp_v4_flow: + ret = otx2_prepare_ipv4_flow(fsp, req, flow_type); + if (ret) + return ret; - otx2_prepare_ipv6_flow(fsp, req, flow_type); + case ah_v6_flow: + case esp_v6_flow: + ret = otx2_prepare_ipv6_flow(fsp, req, flow_type); + if (ret) + return ret;
|
Networking
|
b7cf966126eb16c96bcd13e5ba63657b7e2baef2
|
naveen mamindlapalli
|
drivers
|
net
|
af, ethernet, marvell, nic, octeontx2
|
net: pcs: add pcs-lynx 1000base-x support
|
add support for 1000base-x to pcs-lynx for the lx2160a.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pcs-lynx 1000base-x support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['pcs']
|
['c']
| 1
| 36
| 0
|
--- diff --git a/drivers/net/pcs/pcs-lynx.c b/drivers/net/pcs/pcs-lynx.c --- a/drivers/net/pcs/pcs-lynx.c +++ b/drivers/net/pcs/pcs-lynx.c +#define ieee8023_link_timer_ns 10000000 + case phy_interface_mode_1000basex: +static int lynx_pcs_config_1000basex(struct mdio_device *pcs, + unsigned int mode, + const unsigned long *advertising) +{ + struct mii_bus *bus = pcs->bus; + int addr = pcs->addr; + u32 link_timer; + int err; + + link_timer = link_timer_val(ieee8023_link_timer_ns); + mdiobus_write(bus, addr, link_timer_lo, link_timer & 0xffff); + mdiobus_write(bus, addr, link_timer_hi, link_timer >> 16); + + err = mdiobus_modify(bus, addr, if_mode, + if_mode_sgmii_en | if_mode_use_sgmii_an, + 0); + if (err) + return err; + + return phylink_mii_c22_pcs_config(pcs, mode, + phy_interface_mode_1000basex, + advertising); +} + + case phy_interface_mode_1000basex: + return lynx_pcs_config_1000basex(lynx->mdio, mode, advertising); +static void lynx_pcs_an_restart(struct phylink_pcs *pcs) +{ + struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs); + + phylink_mii_c22_pcs_an_restart(lynx->mdio); +} + + .pcs_an_restart = lynx_pcs_an_restart,
|
Networking
|
694a0006c0b15ed22aa53dc4b244d64c5f12e45e
|
russell king
|
drivers
|
net
|
pcs
|
net: phy: icplus: use phy_id_match_model() macro
|
simpify the initializations of the structures. there is no functional change.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 10
| 9
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c +#define ip175c_phy_id 0x02430d80 +#define ip1001_phy_id 0x02430d90 +#define ip101a_phy_id 0x02430c54 + - .phy_id = 0x02430d80, + phy_id_match_model(ip175c_phy_id), - .phy_id_mask = 0x0ffffff0, - .phy_id = 0x02430d90, + phy_id_match_model(ip1001_phy_id), - .phy_id_mask = 0x0ffffff0, - .phy_id = 0x02430c54, + phy_id_match_model(ip101a_phy_id), - .phy_id_mask = 0x0ffffff0, - { 0x02430d80, 0x0ffffff0 }, - { 0x02430d90, 0x0ffffff0 }, - { 0x02430c54, 0x0ffffff0 }, + { phy_id_match_model(ip175c_phy_id) }, + { phy_id_match_model(ip1001_phy_id) }, + { phy_id_match_model(ip101a_phy_id) },
|
Networking
|
2ad4758cec48c159d776352b02e6984c3c362bff
|
michael walle andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phy: icplus: use phy_id_match_exact() for ip101a/g
|
according to the datasheet of the ip101a/g there is no revision field and mii_physid2 always reads as 0x0c54. use phy_id_match_exact() then.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 2
| 2
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c - phy_id_match_model(ip101a_phy_id), + phy_id_match_exact(ip101a_phy_id), - { phy_id_match_model(ip101a_phy_id) }, + { phy_id_match_exact(ip101a_phy_id) },
|
Networking
|
7360a4de36a4826cc998ce5a89fbc9b5a2182758
|
michael walle andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phy: icplus: drop address operator for functions
|
don't sometimes use the address operator and sometimes not. drop it and make the code look uniform.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 5
| 5
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c - .config_init = &ip175c_config_init, - .config_aneg = &ip175c_config_aneg, - .read_status = &ip175c_read_status, + .config_init = ip175c_config_init, + .config_aneg = ip175c_config_aneg, + .read_status = ip175c_read_status, - .config_init = &ip1001_config_init, + .config_init = ip1001_config_init, - .config_init = &ip101a_g_config_init, + .config_init = ip101a_g_config_init,
|
Networking
|
8edf206cc2b5c98f7c59e01c22cdbc291b713e38
|
michael walle andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phy: icplus: use the .soft_reset() of the phy-core
|
the phy core already resets the phy before .config_init() if a .soft_reset() op is registered. drop the open-coded ip1xx_reset().
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 2
| 30
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c -static int ip1xx_reset(struct phy_device *phydev) -{ - int bmcr; - - /* software reset phy */ - bmcr = phy_read(phydev, mii_bmcr); - if (bmcr < 0) - return bmcr; - bmcr |= bmcr_reset; - bmcr = phy_write(phydev, mii_bmcr, bmcr); - if (bmcr < 0) - return bmcr; - - do { - bmcr = phy_read(phydev, mii_bmcr); - if (bmcr < 0) - return bmcr; - } while (bmcr & bmcr_reset); - - return 0; -} - - c = ip1xx_reset(phydev); - if (c < 0) - return c; - - c = ip1xx_reset(phydev); - if (c < 0) - return c; - + .soft_reset = genphy_soft_reset, + .soft_reset = genphy_soft_reset,
|
Networking
|
df22de9a6f130e85ba174fe6bb3ed190b1cded36
|
michael walle andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phy: icplus: split ip101a/g driver
|
unfortunately, the ip101a and ip101g share the same phy identifier. while most of the functions are somewhat backwards compatible, there is for example the aps_en bit on the ip101a but on the ip101g this bit reserved. also, the ip101g has many more functionalities.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 66
| 3
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c +#define ip101g_page_control 0x14 +#define ip101g_page_control_mask genmask(4, 0) +static int ip101a_g_has_page_register(struct phy_device *phydev) +{ + int oldval, val, ret; + + oldval = phy_read(phydev, ip101g_page_control); + if (oldval < 0) + return oldval; + + ret = phy_write(phydev, ip101g_page_control, 0xffff); + if (ret) + return ret; + + val = phy_read(phydev, ip101g_page_control); + if (val < 0) + return val; + + ret = phy_write(phydev, ip101g_page_control, oldval); + if (ret) + return ret; + + return val == ip101g_page_control_mask; +} + +static int ip101a_g_match_phy_device(struct phy_device *phydev, bool ip101a) +{ + int ret; + + if (phydev->phy_id != ip101a_phy_id) + return 0; + + /* the ip101a and the ip101g share the same phy identifier.the ip101g + * seems to be a successor of the ip101a and implements more functions. + * amongst other things there is a page select register, which is not + * available on the ip101a. use this to distinguish these two. + */ + ret = ip101a_g_has_page_register(phydev); + if (ret < 0) + return ret; + + return ip101a == !ret; +} + +static int ip101a_match_phy_device(struct phy_device *phydev) +{ + return ip101a_g_match_phy_device(phydev, true); +} + +static int ip101g_match_phy_device(struct phy_device *phydev) +{ + return ip101a_g_match_phy_device(phydev, false); +} + - phy_id_match_exact(ip101a_phy_id), - .name = "icplus ip101a/g", - /* phy_basic_features */ + .name = "icplus ip101a", + .match_phy_device = ip101a_match_phy_device, + .probe = ip101a_g_probe, + .config_intr = ip101a_g_config_intr, + .handle_interrupt = ip101a_g_handle_interrupt, + .config_init = ip101a_g_config_init, + .soft_reset = genphy_soft_reset, + .suspend = genphy_suspend, + .resume = genphy_resume, +}, { + .name = "icplus ip101g", + .match_phy_device = ip101g_match_phy_device,
|
Networking
|
675115bf8c3dd51e91aa97cdbc7b14dc0e7e0698
|
michael walle
|
drivers
|
net
|
phy
|
net: phy: icplus: don't set aps_en bit on ip101g
|
this bit is reserved as 'always-write-1'. while this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 20
| 7
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c -static int ip101a_g_config_init(struct phy_device *phydev) +static int ip101a_g_config_intr_pin(struct phy_device *phydev) - int err, c; + int err; + return 0; +} + +static int ip101a_config_init(struct phy_device *phydev) +{ + int ret; + - c = phy_read(phydev, ip10xx_spec_ctrl_status); - c |= ip101a_g_aps_on; + ret = phy_set_bits(phydev, ip10xx_spec_ctrl_status, ip101a_g_aps_on); + if (ret) + return ret; - return phy_write(phydev, ip10xx_spec_ctrl_status, c); + return ip101a_g_config_intr_pin(phydev); +} + +static int ip101g_config_init(struct phy_device *phydev) +{ + return ip101a_g_config_intr_pin(phydev); - .config_init = ip101a_g_config_init, + .config_init = ip101a_config_init, - .config_init = ip101a_g_config_init, + .config_init = ip101g_config_init,
|
Networking
|
eeac7d43d4dd037882a288edb1c9d41f31f142c1
|
michael walle andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phy: icplus: fix paged register access
|
registers >= 16 are paged. be sure to set the page. it seems this was working for now, because the default is correct for the registers used in the driver at the moment. but this will also assume, nobody will change the page select register before linux is started. the page select register is _not_ reset with a soft reset of the phy.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 54
| 13
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c +#define ip101g_default_page 16 + - int err; + int oldpage, err = 0; + + oldpage = phy_select_page(phydev, ip101g_default_page); + if (oldpage < 0) + return oldpage; - err = phy_modify(phydev, ip101g_digital_io_spec_ctrl, - ip101g_digital_io_spec_ctrl_sel_intr32, 0); + err = __phy_modify(phydev, ip101g_digital_io_spec_ctrl, + ip101g_digital_io_spec_ctrl_sel_intr32, 0); - return err; + goto out; - err = phy_modify(phydev, ip101g_digital_io_spec_ctrl, - ip101g_digital_io_spec_ctrl_sel_intr32, - ip101g_digital_io_spec_ctrl_sel_intr32); + err = __phy_modify(phydev, ip101g_digital_io_spec_ctrl, + ip101g_digital_io_spec_ctrl_sel_intr32, + ip101g_digital_io_spec_ctrl_sel_intr32); - return err; + goto out; - return 0; +out: + return phy_restore_page(phydev, oldpage, err); - int err = phy_read(phydev, ip101a_g_irq_conf_status); + int err; + err = phy_read_paged(phydev, ip101g_default_page, + ip101a_g_irq_conf_status); - err = phy_write(phydev, ip101a_g_irq_conf_status, val); + err = phy_write_paged(phydev, ip101g_default_page, + ip101a_g_irq_conf_status, val); - err = phy_write(phydev, ip101a_g_irq_conf_status, val); + err = phy_write_paged(phydev, ip101g_default_page, + ip101a_g_irq_conf_status, val); - irq_status = phy_read(phydev, ip101a_g_irq_conf_status); + irq_status = phy_read_paged(phydev, ip101g_default_page, + ip101a_g_irq_conf_status); +/* the ip101a doesn't really have a page register. we just pretend to have one + * so we can use the paged versions of the callbacks of the ip101g. + */ +static int ip101a_read_page(struct phy_device *phydev) +{ + return ip101g_default_page; +} + +static int ip101a_write_page(struct phy_device *phydev, int page) +{ + warn_once(page != ip101g_default_page, "wrong page selected "); + + return 0; +} + +static int ip101g_read_page(struct phy_device *phydev) +{ + return __phy_read(phydev, ip101g_page_control); +} + +static int ip101g_write_page(struct phy_device *phydev, int page) +{ + return __phy_write(phydev, ip101g_page_control, page); +} + + .read_page = ip101a_read_page, + .write_page = ip101a_write_page, + .read_page = ip101g_read_page, + .write_page = ip101g_write_page,
|
Networking
|
f9bc51e6cce2171e4d8f28c575278dfa07085b44
|
michael walle
|
drivers
|
net
|
phy
|
net: phy: icplus: add phy counter for ip101g
|
the ip101g provides three counters: rx packets, crc errors and symbol errors. the error counters can be configured to clear automatically on read. unfortunately, this isn't true for the rx packet counter. because of this and because the rx packet counter is more likely to overflow, than the error counters implement only support for the error counters.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 75
| 0
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c +#define ip101g_p1_cnt_ctrl 17 +#define cnt_ctrl_rx_en bit(13) +#define ip101g_p8_cnt_ctrl 17 +#define cnt_ctrl_rdclr_en bit(15) +#define ip101g_cnt_reg 18 + +struct ip101g_hw_stat { + const char *name; + int page; +}; + +static struct ip101g_hw_stat ip101g_hw_stats[] = { + { "phy_crc_errors", 1 }, + { "phy_symbol_errors", 11, }, +}; + + u64 stats[array_size(ip101g_hw_stats)]; + int ret; + + /* enable the phy counters */ + ret = phy_modify_paged(phydev, 1, ip101g_p1_cnt_ctrl, + cnt_ctrl_rx_en, cnt_ctrl_rx_en); + if (ret) + return ret; + + /* clear error counters on read */ + ret = phy_modify_paged(phydev, 8, ip101g_p8_cnt_ctrl, + cnt_ctrl_rdclr_en, cnt_ctrl_rdclr_en); + if (ret) + return ret; + +static int ip101g_get_sset_count(struct phy_device *phydev) +{ + return array_size(ip101g_hw_stats); +} + +static void ip101g_get_strings(struct phy_device *phydev, u8 *data) +{ + int i; + + for (i = 0; i < array_size(ip101g_hw_stats); i++) + strscpy(data + i * eth_gstring_len, + ip101g_hw_stats[i].name, eth_gstring_len); +} + +static u64 ip101g_get_stat(struct phy_device *phydev, int i) +{ + struct ip101g_hw_stat stat = ip101g_hw_stats[i]; + struct ip101a_g_phy_priv *priv = phydev->priv; + int val; + u64 ret; + + val = phy_read_paged(phydev, stat.page, ip101g_cnt_reg); + if (val < 0) { + ret = u64_max; + } else { + priv->stats[i] += val; + ret = priv->stats[i]; + } + + return ret; +} + +static void ip101g_get_stats(struct phy_device *phydev, + struct ethtool_stats *stats, u64 *data) +{ + int i; + + for (i = 0; i < array_size(ip101g_hw_stats); i++) + data[i] = ip101g_get_stat(phydev, i); +} + + .get_sset_count = ip101g_get_sset_count, + .get_strings = ip101g_get_strings, + .get_stats = ip101g_get_stats,
|
Networking
|
a0750d42e95192fa8d57796f35ca7189bd231bb4
|
michael walle andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phy: icplus: add mdi/mdix support for ip101a/g
|
implement the operations to set desired mode and retrieve the current mode.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
cleanups and new features
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'icplus']
|
['c']
| 1
| 97
| 0
|
--- diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c --- a/drivers/net/phy/icplus.c +++ b/drivers/net/phy/icplus.c +#define ip101a_g_auto_mdix_dis bit(11) +#define ip101a_g_phy_status 18 +#define ip101a_g_mdix bit(9) +#define ip101a_g_phy_spec_ctrl 30 +#define ip101a_g_force_mdix bit(3) +static int ip101a_g_read_status(struct phy_device *phydev) +{ + int oldpage, ret, stat1, stat2; + + ret = genphy_read_status(phydev); + if (ret) + return ret; + + oldpage = phy_select_page(phydev, ip101g_default_page); + if (oldpage < 0) + return oldpage; + + ret = __phy_read(phydev, ip10xx_spec_ctrl_status); + if (ret < 0) + goto out; + stat1 = ret; + + ret = __phy_read(phydev, ip101a_g_phy_spec_ctrl); + if (ret < 0) + goto out; + stat2 = ret; + + if (stat1 & ip101a_g_auto_mdix_dis) { + if (stat2 & ip101a_g_force_mdix) + phydev->mdix_ctrl = eth_tp_mdi_x; + else + phydev->mdix_ctrl = eth_tp_mdi; + } else { + phydev->mdix_ctrl = eth_tp_mdi_auto; + } + + if (stat2 & ip101a_g_mdix) + phydev->mdix = eth_tp_mdi_x; + else + phydev->mdix = eth_tp_mdi; + + ret = 0; + +out: + return phy_restore_page(phydev, oldpage, ret); +} + +static int ip101a_g_config_mdix(struct phy_device *phydev) +{ + u16 ctrl = 0, ctrl2 = 0; + int oldpage, ret; + + switch (phydev->mdix_ctrl) { + case eth_tp_mdi: + ctrl = ip101a_g_auto_mdix_dis; + break; + case eth_tp_mdi_x: + ctrl = ip101a_g_auto_mdix_dis; + ctrl2 = ip101a_g_force_mdix; + break; + case eth_tp_mdi_auto: + break; + default: + return 0; + } + + oldpage = phy_select_page(phydev, ip101g_default_page); + if (oldpage < 0) + return oldpage; + + ret = __phy_modify(phydev, ip10xx_spec_ctrl_status, + ip101a_g_auto_mdix_dis, ctrl); + if (ret) + goto out; + + ret = __phy_modify(phydev, ip101a_g_phy_spec_ctrl, + ip101a_g_force_mdix, ctrl2); + +out: + return phy_restore_page(phydev, oldpage, ret); +} + +static int ip101a_g_config_aneg(struct phy_device *phydev) +{ + int ret; + + ret = ip101a_g_config_mdix(phydev); + if (ret) + return ret; + + return genphy_config_aneg(phydev); +} + + .config_aneg = ip101a_g_config_aneg, + .read_status = ip101a_g_read_status, + .config_aneg = ip101a_g_config_aneg, + .read_status = ip101a_g_read_status,
|
Networking
|
32ab60e5392066e5c5f71a93e37ea36ab726a526
|
michael walle
|
drivers
|
net
|
phy
|
net: phy: add 100 base-x mode
|
sparx-5 supports this mode and it is missing in the phy core.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add 100 base-x mode
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ']
|
['h', 'rst']
| 2
| 9
| 0
|
--- diff --git a/documentation/networking/phy.rst b/documentation/networking/phy.rst --- a/documentation/networking/phy.rst +++ b/documentation/networking/phy.rst +''phy_interface_mode_100basex'' + this defines ieee 802.3 clause 24. the link operates at a fixed data + rate of 125mpbs using a 4b/5b encoding scheme, resulting in an underlying + data rate of 100mpbs. + diff --git a/include/linux/phy.h b/include/linux/phy.h --- a/include/linux/phy.h +++ b/include/linux/phy.h + * @phy_interface_mode_100basex: 100 basex + phy_interface_mode_100basex, + case phy_interface_mode_100basex: + return "100base-x";
|
Networking
|
b1ae3587d16a8c8fc9453e147c8708d6f006ffbb
|
bjarni jonasson russell king rmk kernel armlinux org uk
|
include
|
linux
| |
net: phy: add 5gbaser interface mode
|
add 5gbase-r phy interface mode
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add 5gbaser interface mode
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ']
|
['h', 'rst']
| 2
| 10
| 0
|
--- diff --git a/documentation/networking/phy.rst b/documentation/networking/phy.rst --- a/documentation/networking/phy.rst +++ b/documentation/networking/phy.rst +''phy_interface_mode_5gbaser'' + this is the ieee 802.3 clause 129 defined 5gbase-r protocol. it is + identical to the 10gbase-r protocol defined in clause 49, with the + exception that it operates at half the frequency. please refer to the + ieee standard for the definition. + diff --git a/include/linux/phy.h b/include/linux/phy.h --- a/include/linux/phy.h +++ b/include/linux/phy.h + * @phy_interface_mode_5gbaser: 5g baser + phy_interface_mode_5gbaser, + case phy_interface_mode_5gbaser: + return "5gbase-r";
|
Networking
|
7331d1d4622ba7e668ec19cfba2ed7feb4a3084e
|
pavana sharma andrew lunn andrew lunn ch florian fainelli f fainelli gmail com
|
include
|
linux
| |
net: phy: at803x: add support for configuring smarteee
|
smarteee for the atheros phy was deemed buggy by freescale and commits were added to disable it for their boards.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for configuring smarteee
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'at803x']
|
['c']
| 1
| 64
| 1
|
--- diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c +#define at803x_mmd3_smarteee_ctl1 0x805b +#define at803x_mmd3_smarteee_ctl2 0x805c +#define at803x_mmd3_smarteee_ctl3 0x805d +#define at803x_mmd3_smarteee_ctl3_lpi_en bit(8) + +#define at803x_disable_smarteee bit(1) + u8 smarteee_lpi_tw_1g; + u8 smarteee_lpi_tw_100m; - u32 freq, strength; + u32 freq, strength, tw; + if (of_property_read_bool(node, "qca,disable-smarteee")) + priv->flags |= at803x_disable_smarteee; + + if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) { + if (!tw || tw > 255) { + phydev_err(phydev, "invalid qca,smarteee-tw-us-1g "); + return -einval; + } + priv->smarteee_lpi_tw_1g = tw; + } + + if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) { + if (!tw || tw > 255) { + phydev_err(phydev, "invalid qca,smarteee-tw-us-100m "); + return -einval; + } + priv->smarteee_lpi_tw_100m = tw; + } + +static int at803x_smarteee_config(struct phy_device *phydev) +{ + struct at803x_priv *priv = phydev->priv; + u16 mask = 0, val = 0; + int ret; + + if (priv->flags & at803x_disable_smarteee) + return phy_modify_mmd(phydev, mdio_mmd_pcs, + at803x_mmd3_smarteee_ctl3, + at803x_mmd3_smarteee_ctl3_lpi_en, 0); + + if (priv->smarteee_lpi_tw_1g) { + mask |= 0xff00; + val |= priv->smarteee_lpi_tw_1g << 8; + } + if (priv->smarteee_lpi_tw_100m) { + mask |= 0x00ff; + val |= priv->smarteee_lpi_tw_100m; + } + if (!mask) + return 0; + + ret = phy_modify_mmd(phydev, mdio_mmd_pcs, at803x_mmd3_smarteee_ctl1, + mask, val); + if (ret) + return ret; + + return phy_modify_mmd(phydev, mdio_mmd_pcs, at803x_mmd3_smarteee_ctl3, + at803x_mmd3_smarteee_ctl3_lpi_en, + at803x_mmd3_smarteee_ctl3_lpi_en); +} + + ret = at803x_smarteee_config(phydev); + if (ret < 0) + return ret; +
|
Networking
|
390b4cad81484124db2b676ed20a265adc032bae
|
russell king
|
drivers
|
net
|
phy
|
net: phy: bcm7xxx: add an entry for bcm72116
|
bcm72116 features a 28nm integrated ephy, add an entry to match this phy oui.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add an entry for bcm72116
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'bcm7xxx']
|
['h', 'c']
| 2
| 3
| 0
|
--- diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c --- a/drivers/net/phy/bcm7xxx.c +++ b/drivers/net/phy/bcm7xxx.c + bcm7xxx_28nm_ephy(phy_id_bcm72116, "broadcom bcm72116"), + { phy_id_bcm72116, 0xfffffff0, }, diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h +#define phy_id_bcm72116 0x35905350
|
Networking
|
8b86850bf9ef259e194ce49c776aded3b8c281fb
|
florian fainelli andrew lunn andrew lunn ch
|
include
|
linux
|
phy
|
net: phy: broadcom: set proper 1000basex/sgmii interface mode for bcm54616s
|
the default configuration for the bcm54616s phy may not match the desired mode when using 1000basex or sgmii interface modes, such as when it is on an sfp module. add code to explicitly set the correct mode using programming sequences provided by bel-fuse:
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
set proper 1000basex/sgmii interface mode for bcm54616s
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy ', 'broadcom']
|
['h', 'c']
| 2
| 76
| 12
|
--- diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c +static int bcm54616s_config_init(struct phy_device *phydev) +{ + int rc, val; + + if (phydev->interface != phy_interface_mode_sgmii && + phydev->interface != phy_interface_mode_1000basex) + return 0; + + /* ensure proper interface mode is selected. */ + /* disable rgmii mode */ + val = bcm54xx_auxctl_read(phydev, mii_bcm54xx_auxctl_shdwsel_misc); + if (val < 0) + return val; + val &= ~mii_bcm54xx_auxctl_shdwsel_misc_rgmii_en; + val |= mii_bcm54xx_auxctl_misc_wren; + rc = bcm54xx_auxctl_write(phydev, mii_bcm54xx_auxctl_shdwsel_misc, + val); + if (rc < 0) + return rc; + + /* select 1000base-x register set (primary serdes) */ + val = bcm_phy_read_shadow(phydev, bcm54xx_shd_mode); + if (val < 0) + return val; + val |= bcm54xx_shd_mode_1000bx; + rc = bcm_phy_write_shadow(phydev, bcm54xx_shd_mode, val); + if (rc < 0) + return rc; + + /* power down serdes interface */ + rc = phy_set_bits(phydev, mii_bmcr, bmcr_pdown); + if (rc < 0) + return rc; + + /* select proper interface mode */ + val &= ~bcm54xx_shd_intf_sel_mask; + val |= phydev->interface == phy_interface_mode_sgmii ? + bcm54xx_shd_intf_sel_sgmii : + bcm54xx_shd_intf_sel_gbic; + rc = bcm_phy_write_shadow(phydev, bcm54xx_shd_mode, val); + if (rc < 0) + return rc; + + /* power up serdes interface */ + rc = phy_clear_bits(phydev, mii_bmcr, bmcr_pdown); + if (rc < 0) + return rc; + + /* select copper register set */ + val &= ~bcm54xx_shd_mode_1000bx; + rc = bcm_phy_write_shadow(phydev, bcm54xx_shd_mode, val); + if (rc < 0) + return rc; + + /* power up copper interface */ + return phy_clear_bits(phydev, mii_bmcr, bmcr_pdown); +} + - if (brcm_phy_model(phydev) == phy_id_bcm54210e) { + switch (brcm_phy_model(phydev)) { + case phy_id_bcm54210e: - if (err) - return err; - } else if (brcm_phy_model(phydev) == phy_id_bcm54612e) { + break; + case phy_id_bcm54612e: - if (err) - return err; - } else if (brcm_phy_model(phydev) == phy_id_bcm54810) { + break; + case phy_id_bcm54616s: + err = bcm54616s_config_init(phydev); + break; + case phy_id_bcm54810: - if (err < 0) - return err; + break; + if (err) + return err; - int val, intf_sel; + int val; - intf_sel = (val & bcm54xx_shd_intf_sel_mask) >> 1; - if (intf_sel == 1) { + if ((val & bcm54xx_shd_intf_sel_mask) == bcm54xx_shd_intf_sel_rgmii) { diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h --- a/include/linux/brcmphy.h +++ b/include/linux/brcmphy.h +#define mii_bcm54xx_auxctl_shdwsel_misc_rgmii_en 0x0080 +#define bcm54xx_shd_intf_sel_rgmii 0x02 +#define bcm54xx_shd_intf_sel_sgmii 0x04 +#define bcm54xx_shd_intf_sel_gbic 0x06
|
Networking
|
3afd0218992a8d1398e9791d6c2edd4c948ae7ee
|
robert hancock
|
include
|
linux
|
phy
|
net: phy: introduce phydev->port
|
at the moment, port_mii is reported in the ethtool ops. this is odd because it is an interface between the mac and the phy and no external port. some network card drivers will overwrite the port to twisted pair or fiber, though. even worse, the mdi/mdix setting is only used by ethtool if the port is twisted pair.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce phydev->port
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy']
|
['h', 'c']
| 10
| 36
| 4
|
--- diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c --- a/drivers/net/phy/broadcom.c +++ b/drivers/net/phy/broadcom.c + + phydev->port = port_fibre; diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c + if (dp83822->fx_enabled) + phydev->port = port_fibre; + diff --git a/drivers/net/phy/dp83869.c b/drivers/net/phy/dp83869.c --- a/drivers/net/phy/dp83869.c +++ b/drivers/net/phy/dp83869.c + if (dp83869->mode == dp83869_rgmii_100_base || + dp83869->mode == dp83869_rgmii_1000_base) + phydev->port = port_fibre; + diff --git a/drivers/net/phy/lxt.c b/drivers/net/phy/lxt.c --- a/drivers/net/phy/lxt.c +++ b/drivers/net/phy/lxt.c + phydev->port = port_fibre; diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c + phydev->port = fiber ? port_fibre : port_tp; diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c --- a/drivers/net/phy/marvell10g.c +++ b/drivers/net/phy/marvell10g.c + phydev->port = port_fibre; + phydev->port = port_tp; diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c +static int ksz8041_fiber_mode(struct phy_device *phydev) +{ + struct device_node *of_node = phydev->mdio.dev.of_node; + + return of_property_read_bool(of_node, "micrel,fiber-mode"); +} + - struct device_node *of_node = phydev->mdio.dev.of_node; - - if (of_property_read_bool(of_node, "micrel,fiber-mode")) { + if (ksz8041_fiber_mode(phydev)) { + if (ksz8041_fiber_mode(phydev)) + phydev->port = port_fibre; + diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c - cmd->base.port = port_mii; + cmd->base.port = phydev->port; diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c + dev->port = port_tp; + /* port is set to port_tp by default and the actual phy driver will set + * it to different value depending on the phy configuration. if we have + * the generic phy driver we can't figure it out, thus set the old + * legacy port_mii value. + */ + if (using_genphy) + phydev->port = port_mii; + diff --git a/include/linux/phy.h b/include/linux/phy.h --- a/include/linux/phy.h +++ b/include/linux/phy.h + * @port: current port + int port;
|
Networking
|
4217a64e18a1647a0dbc68cb3169a5a06f054ec8
|
michael walle
|
include
|
linux
|
phy
|
net: phy: micrel: add ks8851 phy support
|
the ks8851 has a reduced internal phy, which is accessible through its registers at offset 0xe4. the phy is compatible with ks886x phy present in micrel switches, including the phy id low/high registers swap, which is present both in the mac and the switch.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ks8851 phy support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phy', 'micrel']
|
['c']
| 1
| 1
| 1
|
--- diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c - .name = "micrel ksz886x switch", + .name = "micrel ksz8851 ethernet mac or ksz886x switch",
|
Networking
|
ab36a3a2e67834687b85b46bc74add45894cdb3d
|
marek vasut andrew lunn andrew lunn ch
|
drivers
|
net
|
phy
|
net: phylink: add 5gbase-r support
|
add 5gbaser interface type and speed to phylink.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add 5gbase-r support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['phylink']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c + case phy_interface_mode_5gbaser: + phylink_set(pl->supported, 5000baset_full); + break; +
|
Networking
|
f6813bdafdb370d4fb371922d86ff85b681a736b
|
marek beh n
|
drivers
|
net
|
phy
|
qede: add netpoll support for qede driver
|
handle netpoll case when qede_poll is called by netpoll layer with budget 0
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add netpoll and per-queue coalesce support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qede']
|
['c']
| 1
| 2
| 1
|
--- diff --git a/drivers/net/ethernet/qlogic/qede/qede_fp.c b/drivers/net/ethernet/qlogic/qede/qede_fp.c --- a/drivers/net/ethernet/qlogic/qede/qede_fp.c +++ b/drivers/net/ethernet/qlogic/qede/qede_fp.c - if (rx_work_done < budget) { + /* handle case where we are called by netpoll with a budget of 0 */ + if (rx_work_done < budget || !budget) {
|
Networking
|
961aa716235f58088e99acafbe66027d678061ce
|
bhaskar upadhaya
|
drivers
|
net
|
ethernet, qede, qlogic
|
qede: add per queue coalesce support for qede driver
|
per queue coalescing allows better and more finegrained control over interrupt rates.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add netpoll and per-queue coalesce support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qede']
|
['c']
| 1
| 124
| 0
|
--- diff --git a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c --- a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c +++ b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c +static int qede_set_per_coalesce(struct net_device *dev, + u32 queue, + struct ethtool_coalesce *coal) +{ + struct qede_dev *edev = netdev_priv(dev); + struct qede_fastpath *fp; + u16 rxc, txc; + int rc = 0; + + if (coal->rx_coalesce_usecs > qed_coalesce_max || + coal->tx_coalesce_usecs > qed_coalesce_max) { + dp_info(edev, + "can't support requested %s coalesce value [max supported value %d] ", + coal->rx_coalesce_usecs > qed_coalesce_max ? "rx" + : "tx", + qed_coalesce_max); + return -einval; + } + + rxc = (u16)coal->rx_coalesce_usecs; + txc = (u16)coal->tx_coalesce_usecs; + + __qede_lock(edev); + if (queue >= edev->num_queues) { + dp_info(edev, "invalid queue "); + rc = -einval; + goto out; + } + + if (edev->state != qede_state_open) { + rc = -einval; + goto out; + } + + fp = &edev->fp_array[queue]; + + if (edev->fp_array[queue].type & qede_fastpath_rx) { + rc = edev->ops->common->set_coalesce(edev->cdev, + rxc, 0, + fp->rxq->handle); + if (rc) { + dp_info(edev, + "set rx coalesce error, rc = %d ", rc); + goto out; + } + } + + if (edev->fp_array[queue].type & qede_fastpath_tx) { + rc = edev->ops->common->set_coalesce(edev->cdev, + 0, txc, + fp->txq->handle); + if (rc) { + dp_info(edev, + "set tx coalesce error, rc = %d ", rc); + goto out; + } + } +out: + __qede_unlock(edev); + + return rc; +} + +static int qede_get_per_coalesce(struct net_device *dev, + u32 queue, + struct ethtool_coalesce *coal) +{ + void *rx_handle = null, *tx_handle = null; + struct qede_dev *edev = netdev_priv(dev); + struct qede_fastpath *fp; + u16 rx_coal, tx_coal; + int rc = 0; + + rx_coal = qed_default_rx_usecs; + tx_coal = qed_default_tx_usecs; + + memset(coal, 0, sizeof(struct ethtool_coalesce)); + + __qede_lock(edev); + if (queue >= edev->num_queues) { + dp_info(edev, "invalid queue "); + rc = -einval; + goto out; + } + + if (edev->state != qede_state_open) { + rc = -einval; + goto out; + } + + fp = &edev->fp_array[queue]; + + if (fp->type & qede_fastpath_rx) + rx_handle = fp->rxq->handle; + + rc = edev->ops->get_coalesce(edev->cdev, &rx_coal, + rx_handle); + if (rc) { + dp_info(edev, "read rx coalesce error "); + goto out; + } + + fp = &edev->fp_array[queue]; + if (fp->type & qede_fastpath_tx) + tx_handle = fp->txq->handle; + + rc = edev->ops->get_coalesce(edev->cdev, &tx_coal, + tx_handle); + if (rc) + dp_info(edev, "read tx coalesce error "); + +out: + __qede_unlock(edev); + + coal->rx_coalesce_usecs = rx_coal; + coal->tx_coalesce_usecs = tx_coal; + + return rc; +} + + .get_per_queue_coalesce = qede_get_per_coalesce, + .set_per_queue_coalesce = qede_set_per_coalesce, + .get_per_queue_coalesce = qede_get_per_coalesce, + .set_per_queue_coalesce = qede_set_per_coalesce,
|
Networking
|
a0d2d97d742cc04817017e4c623256b9583a095d
|
bhaskar upadhaya
|
drivers
|
net
|
ethernet, qede, qlogic
|
qede: preserve per queue stats across up/down of interface
|
here we do the initialization of coalescing values on load. per queue coalesce values are also restored across up/down of ethernet interface.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add netpoll and per-queue coalesce support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qede']
|
['h', 'c']
| 3
| 48
| 7
|
--- diff --git a/drivers/net/ethernet/qlogic/qede/qede.h b/drivers/net/ethernet/qlogic/qede/qede.h --- a/drivers/net/ethernet/qlogic/qede/qede.h +++ b/drivers/net/ethernet/qlogic/qede/qede.h +struct qede_coalesce { + bool isvalid; + u16 rxc; + u16 txc; +}; + + struct qede_coalesce *coal_entry; +int qede_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal); +int qede_set_per_coalesce(struct net_device *dev, u32 queue, + struct ethtool_coalesce *coal); diff --git a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c --- a/drivers/net/ethernet/qlogic/qede/qede_ethtool.c +++ b/drivers/net/ethernet/qlogic/qede/qede_ethtool.c -static int qede_set_coalesce(struct net_device *dev, - struct ethtool_coalesce *coal) +int qede_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal) + edev->coal_entry[i].rxc = rxc; + edev->coal_entry[i].isvalid = true; + edev->coal_entry[i].txc = txc; + edev->coal_entry[i].isvalid = true; -static int qede_set_per_coalesce(struct net_device *dev, - u32 queue, - struct ethtool_coalesce *coal) +int qede_set_per_coalesce(struct net_device *dev, u32 queue, + struct ethtool_coalesce *coal) + edev->coal_entry[queue].rxc = rxc; + edev->coal_entry[queue].isvalid = true; + edev->coal_entry[queue].txc = txc; + edev->coal_entry[queue].isvalid = true; diff --git a/drivers/net/ethernet/qlogic/qede/qede_main.c b/drivers/net/ethernet/qlogic/qede/qede_main.c --- a/drivers/net/ethernet/qlogic/qede/qede_main.c +++ b/drivers/net/ethernet/qlogic/qede/qede_main.c + void *mem; + mem = krealloc(edev->coal_entry, qede_queue_cnt(edev) * + sizeof(*edev->coal_entry), gfp_kernel); + if (!mem) { + dp_err(edev, "coalesce entry allocation failed "); + kfree(edev->coal_entry); + goto err; + } + edev->coal_entry = mem; + - if (mode != qede_remove_recovery) + if (mode != qede_remove_recovery) { + kfree(edev->coal_entry); + } + struct ethtool_coalesce coal = {}; - int rc; + int rc, i; + coal.rx_coalesce_usecs = qed_default_rx_usecs; + coal.tx_coalesce_usecs = qed_default_tx_usecs; + + for_each_queue(i) { + if (edev->coal_entry[i].isvalid) { + coal.rx_coalesce_usecs = edev->coal_entry[i].rxc; + coal.tx_coalesce_usecs = edev->coal_entry[i].txc; + } + __qede_unlock(edev); + qede_set_per_coalesce(edev->ndev, i, &coal); + __qede_lock(edev); + }
|
Networking
|
b0ec5489c480e4875ee2e19286e3cf228c6905ed
|
bhaskar upadhaya
|
drivers
|
net
|
ethernet, qede, qlogic
|
r8169: add support for another rtl8168fp
|
according to the vendor driver, the new chip with xid 0x54b is essentially the same as the one with xid 0x54a, but it doesn't need the firmware.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for another rtl8168fp
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['r8169 ']
|
['h', 'c']
| 3
| 13
| 6
|
--- diff --git a/drivers/net/ethernet/realtek/r8169.h b/drivers/net/ethernet/realtek/r8169.h --- a/drivers/net/ethernet/realtek/r8169.h +++ b/drivers/net/ethernet/realtek/r8169.h + rtl_giga_mac_ver_53, diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c + [rtl_giga_mac_ver_53] = {"rtl8168fp/rtl8117", }, - tp->mac_version <= rtl_giga_mac_ver_52; + tp->mac_version <= rtl_giga_mac_ver_53; - if (tp->mac_version == rtl_giga_mac_ver_52 && type == eriar_oob) + if (type == eriar_oob && + (tp->mac_version == rtl_giga_mac_ver_52 || + tp->mac_version == rtl_giga_mac_ver_53)) - case rtl_giga_mac_ver_49 ... rtl_giga_mac_ver_52: + case rtl_giga_mac_ver_49 ... rtl_giga_mac_ver_53: + { 0x7cf, 0x54b, rtl_giga_mac_ver_53 }, - case rtl_giga_mac_ver_40 ... rtl_giga_mac_ver_52: + case rtl_giga_mac_ver_40 ... rtl_giga_mac_ver_53: - case rtl_giga_mac_ver_40 ... rtl_giga_mac_ver_52: + case rtl_giga_mac_ver_40 ... rtl_giga_mac_ver_53: + [rtl_giga_mac_ver_53] = rtl_hw_start_8117, - case rtl_giga_mac_ver_49 ... rtl_giga_mac_ver_52: + case rtl_giga_mac_ver_49 ... rtl_giga_mac_ver_53: diff --git a/drivers/net/ethernet/realtek/r8169_phy_config.c b/drivers/net/ethernet/realtek/r8169_phy_config.c --- a/drivers/net/ethernet/realtek/r8169_phy_config.c +++ b/drivers/net/ethernet/realtek/r8169_phy_config.c + [rtl_giga_mac_ver_53] = rtl8117_hw_phy_config,
|
Networking
|
e6d6ca6e12049dfbff6ac8b029678d2d2c55c34f
|
kai heng feng
|
drivers
|
net
|
ethernet, realtek
|
r8169: improve dash support
|
instead of doing the full dash check each time r8168_check_dash() is called, let's do it once in probe and store dash capabilities in a new rtl8169_private member.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
improve dash support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['r8169 ']
|
['c']
| 1
| 22
| 31
|
--- diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c +enum rtl_dash_type { + rtl_dash_none, + rtl_dash_dp, + rtl_dash_ep, +}; + + enum rtl_dash_type dash_type; - switch (tp->mac_version) { - case rtl_giga_mac_ver_27: - case rtl_giga_mac_ver_28: - case rtl_giga_mac_ver_31: + if (tp->dash_type == rtl_dash_dp) - break; - case rtl_giga_mac_ver_49 ... rtl_giga_mac_ver_52: + else - break; - default: - bug(); - break; - } - switch (tp->mac_version) { - case rtl_giga_mac_ver_27: - case rtl_giga_mac_ver_28: - case rtl_giga_mac_ver_31: + if (tp->dash_type == rtl_dash_dp) - break; - case rtl_giga_mac_ver_49 ... rtl_giga_mac_ver_52: + else - break; - default: - bug(); - break; - } - return !!(r8168dp_ocp_read(tp, reg) & 0x00008000); + return r8168dp_ocp_read(tp, reg) & bit(15); - return r8168ep_ocp_read(tp, 0x128) & 0x00000001; + return r8168ep_ocp_read(tp, 0x128) & bit(0); -static bool r8168_check_dash(struct rtl8169_private *tp) +static enum rtl_dash_type rtl_check_dash(struct rtl8169_private *tp) - return r8168dp_check_dash(tp); + return r8168dp_check_dash(tp) ? rtl_dash_dp : rtl_dash_none; - return r8168ep_check_dash(tp); + return r8168ep_check_dash(tp) ? rtl_dash_ep : rtl_dash_none; - return false; + return rtl_dash_none; - if (r8168_check_dash(tp)) + if (tp->dash_type != rtl_dash_none) - if (r8168_check_dash(tp)) + if (tp->dash_type != rtl_dash_none) + tp->dash_type = rtl_check_dash(tp); + - if (r8168_check_dash(tp)) { + if (tp->dash_type != rtl_dash_none) {
|
Networking
|
e0d38b5880758432f74fe17fea8281691d1eb3c0
|
heiner kallweit saeed mahameed saeedm nvidia com
|
drivers
|
net
|
ethernet, realtek
|
rt2800usb: add sweex lw163v2 id's
|
add support for sweex lw163v2 device.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add sweex lw163v2 id's
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['rt2800usb']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c --- a/drivers/net/wireless/ralink/rt2x00/rt2800usb.c +++ b/drivers/net/wireless/ralink/rt2x00/rt2800usb.c + { usb_device(0x177f, 0x1163) },
|
Networking
|
93476ca7445793101b803db881f2d755d5184e36
|
stanislaw gruszka
|
drivers
|
net
|
ralink, rt2x00, wireless
|
rtw88: 8821c: support rfe type2 wifi nic
|
rfe type2 is a new nic which has one rf antenna shares with bt. update phy parameter to verstion v57 to allow initial procedure to load extra agc table for sharing antenna nic.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support rfe type2 wifi nic
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['rtw88 ', '8821c']
|
['h', 'c']
| 6
| 468
| 0
|
--- diff --git a/drivers/net/wireless/realtek/rtw88/main.c b/drivers/net/wireless/realtek/rtw88/main.c --- a/drivers/net/wireless/realtek/rtw88/main.c +++ b/drivers/net/wireless/realtek/rtw88/main.c + if (rfe_def->agc_btg_tbl) + rtw_load_table(rtwdev, rfe_def->agc_btg_tbl); diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h --- a/drivers/net/wireless/realtek/rtw88/main.h +++ b/drivers/net/wireless/realtek/rtw88/main.h + const struct rtw_table *agc_btg_tbl; +#define rtw_def_rfe_ext(chip, bb_pg, pwrlmt, btg) { \ + .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ + .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ + .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ + } + diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.c b/drivers/net/wireless/realtek/rtw88/rtw8821c.c --- a/drivers/net/wireless/realtek/rtw88/rtw8821c.c +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.c +enum rtw8821ce_rf_set { + switch_to_btg, + switch_to_wlg, + switch_to_wla, + switch_to_bt, +}; + +static void rtw8821c_switch_rf_set(struct rtw_dev *rtwdev, u8 rf_set) +{ + u32 reg; + + rtw_write32_set(rtwdev, reg_dmem_ctrl, bit_wl_rst); + rtw_write32_set(rtwdev, reg_sys_ctrl, bit_fen_en); + + reg = rtw_read32(rtwdev, reg_rfectl); + switch (rf_set) { + case switch_to_btg: + reg |= b_btg_switch; + reg &= ~(b_ctrl_switch | b_wl_switch | b_wlg_switch | + b_wla_switch); + rtw_write32_mask(rtwdev, reg_enrxcca, maskbyte2, btg_cca); + rtw_write32_mask(rtwdev, reg_entxcck, masklword, btg_lna); + break; + case switch_to_wlg: + reg |= b_wl_switch | b_wlg_switch; + reg &= ~(b_btg_switch | b_ctrl_switch | b_wla_switch); + rtw_write32_mask(rtwdev, reg_enrxcca, maskbyte2, wlg_cca); + rtw_write32_mask(rtwdev, reg_entxcck, masklword, wlg_lna); + break; + case switch_to_wla: + reg |= b_wl_switch | b_wla_switch; + reg &= ~(b_btg_switch | b_ctrl_switch | b_wlg_switch); + break; + case switch_to_bt: + default: + break; + } + + rtw_write32(rtwdev, reg_rfectl, reg); +} + + if (rtwdev->efuse.rfe_option == 0) + rtw8821c_switch_rf_set(rtwdev, switch_to_wlg); + else if (rtwdev->efuse.rfe_option == 2) + rtw8821c_switch_rf_set(rtwdev, switch_to_btg); + rtw8821c_switch_rf_set(rtwdev, switch_to_wla); + [2] = rtw_def_rfe_ext(8821c, 0, 0, 2), diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c.h b/drivers/net/wireless/realtek/rtw88/rtw8821c.h --- a/drivers/net/wireless/realtek/rtw88/rtw8821c.h +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c.h +#define reg_sys_ctrl 0x000 +#define bit_fen_en bit(26) +#define btg_lna 0xfc84 +#define wlg_lna 0x7532 +#define reg_enrxcca 0xa84 +#define btg_cca 0x0e +#define wlg_cca 0x12 +#define b_btg_switch bit(16) +#define b_ctrl_switch bit(18) +#define b_wl_switch (bit(20) | bit(22)) +#define b_wlg_switch bit(21) +#define b_wla_switch bit(23) +#define reg_dmem_ctrl 0x1080 +#define bit_wl_rst bit(16) diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c_table.c b/drivers/net/wireless/realtek/rtw88/rtw8821c_table.c --- a/drivers/net/wireless/realtek/rtw88/rtw8821c_table.c +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c_table.c +static const u32 rtw8821c_agc_btg_type2[] = { + 0x80001004, 0x00000000, 0x40000000, 0x00000000, + 0x81c, 0xff000013, + 0x81c, 0xfe020013, + 0x81c, 0xfd040013, + 0x81c, 0xfc060013, + 0x81c, 0xfb080013, + 0x81c, 0xfa0a0013, + 0x81c, 0xf90c0013, + 0x81c, 0xf80e0013, + 0x81c, 0xf7100013, + 0x81c, 0xf6120013, + 0x81c, 0xf5140013, + 0x81c, 0xf4160013, + 0x81c, 0xf3180013, + 0x81c, 0xf21a0013, + 0x81c, 0xf11c0013, + 0x81c, 0xf01e0013, + 0x81c, 0xef200013, + 0x81c, 0xee220013, + 0x81c, 0xed240013, + 0x81c, 0xec260013, + 0x81c, 0xeb280013, + 0x81c, 0xea2a0013, + 0x81c, 0xe92c0013, + 0x81c, 0xe82e0013, + 0x81c, 0xe7300013, + 0x81c, 0x8b320013, + 0x81c, 0x8a340013, + 0x81c, 0x89360013, + 0x81c, 0x88380013, + 0x81c, 0x873a0013, + 0x81c, 0x863c0013, + 0x81c, 0x853e0013, + 0x81c, 0x84400013, + 0x81c, 0x83420013, + 0x81c, 0x82440013, + 0x81c, 0x81460013, + 0x81c, 0x08480013, + 0x81c, 0x074a0013, + 0x81c, 0x064c0013, + 0x81c, 0x054e0013, + 0x81c, 0x04500013, + 0x81c, 0x03520013, + 0x81c, 0x88540003, + 0x81c, 0x87560003, + 0x81c, 0x86580003, + 0x81c, 0x855a0003, + 0x81c, 0x845c0003, + 0x81c, 0x835e0003, + 0x81c, 0x82600003, + 0x81c, 0x81620003, + 0x81c, 0x07640003, + 0x81c, 0x06660003, + 0x81c, 0x05680003, + 0x81c, 0x046a0003, + 0x81c, 0x036c0003, + 0x81c, 0x026e0003, + 0x81c, 0x01700003, + 0x81c, 0x01720003, + 0x81c, 0x01740003, + 0x81c, 0x01760003, + 0x81c, 0x01780003, + 0x81c, 0x017a0003, + 0x81c, 0x017c0003, + 0x81c, 0x017e0003, + 0x81c, 0xff000813, + 0x81c, 0xfe020813, + 0x81c, 0xfd040813, + 0x81c, 0xfc060813, + 0x81c, 0xfb080813, + 0x81c, 0xfa0a0813, + 0x81c, 0xf90c0813, + 0x81c, 0xf80e0813, + 0x81c, 0xf7100813, + 0x81c, 0xf6120813, + 0x81c, 0xf5140813, + 0x81c, 0xf4160813, + 0x81c, 0xf3180813, + 0x81c, 0xf21a0813, + 0x81c, 0xf11c0813, + 0x81c, 0x941e0813, + 0x81c, 0x93200813, + 0x81c, 0x92220813, + 0x81c, 0x91240813, + 0x81c, 0x90260813, + 0x81c, 0x8f280813, + 0x81c, 0x8e2a0813, + 0x81c, 0x8d2c0813, + 0x81c, 0x8c2e0813, + 0x81c, 0x8b300813, + 0x81c, 0x8a320813, + 0x81c, 0x89340813, + 0x81c, 0x88360813, + 0x81c, 0x87380813, + 0x81c, 0x863a0813, + 0x81c, 0x853c0813, + 0x81c, 0x843e0813, + 0x81c, 0x83400813, + 0x81c, 0x82420813, + 0x81c, 0x81440813, + 0x81c, 0x07460813, + 0x81c, 0x06480813, + 0x81c, 0x054a0813, + 0x81c, 0x044c0813, + 0x81c, 0x034e0813, + 0x81c, 0x02500813, + 0x81c, 0x01520813, + 0x81c, 0x88540803, + 0x81c, 0x87560803, + 0x81c, 0x86580803, + 0x81c, 0x855a0803, + 0x81c, 0x845c0803, + 0x81c, 0x835e0803, + 0x81c, 0x82600803, + 0x81c, 0x81620803, + 0x81c, 0x07640803, + 0x81c, 0x06660803, + 0x81c, 0x05680803, + 0x81c, 0x046a0803, + 0x81c, 0x036c0803, + 0x81c, 0x026e0803, + 0x81c, 0x01700803, + 0x81c, 0x01720803, + 0x81c, 0x01740803, + 0x81c, 0x01760803, + 0x81c, 0x01780803, + 0x81c, 0x017a0803, + 0x81c, 0x017c0803, + 0x81c, 0x017e0803, + 0x90001005, 0x00000000, 0x40000000, 0x00000000, + 0x81c, 0xff000013, + 0x81c, 0xfe020013, + 0x81c, 0xfd040013, + 0x81c, 0xfc060013, + 0x81c, 0xfb080013, + 0x81c, 0xfa0a0013, + 0x81c, 0xf90c0013, + 0x81c, 0xf80e0013, + 0x81c, 0xf7100013, + 0x81c, 0xf6120013, + 0x81c, 0xf5140013, + 0x81c, 0xf4160013, + 0x81c, 0xf3180013, + 0x81c, 0xf21a0013, + 0x81c, 0xf11c0013, + 0x81c, 0xf01e0013, + 0x81c, 0xef200013, + 0x81c, 0xee220013, + 0x81c, 0xed240013, + 0x81c, 0xec260013, + 0x81c, 0xeb280013, + 0x81c, 0xea2a0013, + 0x81c, 0xe92c0013, + 0x81c, 0xe82e0013, + 0x81c, 0xe7300013, + 0x81c, 0x8b320013, + 0x81c, 0x8a340013, + 0x81c, 0x89360013, + 0x81c, 0x88380013, + 0x81c, 0x873a0013, + 0x81c, 0x863c0013, + 0x81c, 0x853e0013, + 0x81c, 0x84400013, + 0x81c, 0x83420013, + 0x81c, 0x82440013, + 0x81c, 0x81460013, + 0x81c, 0x08480013, + 0x81c, 0x074a0013, + 0x81c, 0x064c0013, + 0x81c, 0x054e0013, + 0x81c, 0x04500013, + 0x81c, 0x03520013, + 0x81c, 0x88540003, + 0x81c, 0x87560003, + 0x81c, 0x86580003, + 0x81c, 0x855a0003, + 0x81c, 0x845c0003, + 0x81c, 0x835e0003, + 0x81c, 0x82600003, + 0x81c, 0x81620003, + 0x81c, 0x07640003, + 0x81c, 0x06660003, + 0x81c, 0x05680003, + 0x81c, 0x046a0003, + 0x81c, 0x036c0003, + 0x81c, 0x026e0003, + 0x81c, 0x01700003, + 0x81c, 0x01720003, + 0x81c, 0x01740003, + 0x81c, 0x01760003, + 0x81c, 0x01780003, + 0x81c, 0x017a0003, + 0x81c, 0x017c0003, + 0x81c, 0x017e0003, + 0x81c, 0xff000813, + 0x81c, 0xfe020813, + 0x81c, 0xfd040813, + 0x81c, 0xfc060813, + 0x81c, 0xfb080813, + 0x81c, 0xfa0a0813, + 0x81c, 0xf90c0813, + 0x81c, 0xf80e0813, + 0x81c, 0xf7100813, + 0x81c, 0xf6120813, + 0x81c, 0xf5140813, + 0x81c, 0xf4160813, + 0x81c, 0xf3180813, + 0x81c, 0xf21a0813, + 0x81c, 0xf11c0813, + 0x81c, 0x941e0813, + 0x81c, 0x93200813, + 0x81c, 0x92220813, + 0x81c, 0x91240813, + 0x81c, 0x90260813, + 0x81c, 0x8f280813, + 0x81c, 0x8e2a0813, + 0x81c, 0x8d2c0813, + 0x81c, 0x8c2e0813, + 0x81c, 0x8b300813, + 0x81c, 0x8a320813, + 0x81c, 0x89340813, + 0x81c, 0x88360813, + 0x81c, 0x87380813, + 0x81c, 0x863a0813, + 0x81c, 0x853c0813, + 0x81c, 0x843e0813, + 0x81c, 0x83400813, + 0x81c, 0x82420813, + 0x81c, 0x81440813, + 0x81c, 0x07460813, + 0x81c, 0x06480813, + 0x81c, 0x054a0813, + 0x81c, 0x044c0813, + 0x81c, 0x034e0813, + 0x81c, 0x02500813, + 0x81c, 0x01520813, + 0x81c, 0x88540803, + 0x81c, 0x87560803, + 0x81c, 0x86580803, + 0x81c, 0x855a0803, + 0x81c, 0x845c0803, + 0x81c, 0x835e0803, + 0x81c, 0x82600803, + 0x81c, 0x81620803, + 0x81c, 0x07640803, + 0x81c, 0x06660803, + 0x81c, 0x05680803, + 0x81c, 0x046a0803, + 0x81c, 0x036c0803, + 0x81c, 0x026e0803, + 0x81c, 0x01700803, + 0x81c, 0x01720803, + 0x81c, 0x01740803, + 0x81c, 0x01760803, + 0x81c, 0x01780803, + 0x81c, 0x017a0803, + 0x81c, 0x017c0803, + 0x81c, 0x017e0803, + 0xa0000000, 0x00000000, + 0x81c, 0xff000013, + 0x81c, 0xfe020013, + 0x81c, 0xfd040013, + 0x81c, 0xfc060013, + 0x81c, 0xfb080013, + 0x81c, 0xfa0a0013, + 0x81c, 0xf90c0013, + 0x81c, 0xf80e0013, + 0x81c, 0xf7100013, + 0x81c, 0xf6120013, + 0x81c, 0xf5140013, + 0x81c, 0xf4160013, + 0x81c, 0xf3180013, + 0x81c, 0xf21a0013, + 0x81c, 0xf11c0013, + 0x81c, 0xf01e0013, + 0x81c, 0xef200013, + 0x81c, 0xee220013, + 0x81c, 0xed240013, + 0x81c, 0xec260013, + 0x81c, 0xeb280013, + 0x81c, 0xea2a0013, + 0x81c, 0xe92c0013, + 0x81c, 0xe82e0013, + 0x81c, 0xe7300013, + 0x81c, 0x8a320013, + 0x81c, 0x89340013, + 0x81c, 0x88360013, + 0x81c, 0x87380013, + 0x81c, 0x863a0013, + 0x81c, 0x853c0013, + 0x81c, 0x843e0013, + 0x81c, 0x83400013, + 0x81c, 0x82420013, + 0x81c, 0x81440013, + 0x81c, 0x07460013, + 0x81c, 0x06480013, + 0x81c, 0x054a0013, + 0x81c, 0x044c0013, + 0x81c, 0x034e0013, + 0x81c, 0x02500013, + 0x81c, 0x01520013, + 0x81c, 0x88540003, + 0x81c, 0x87560003, + 0x81c, 0x86580003, + 0x81c, 0x855a0003, + 0x81c, 0x845c0003, + 0x81c, 0x835e0003, + 0x81c, 0x82600003, + 0x81c, 0x81620003, + 0x81c, 0x07640003, + 0x81c, 0x06660003, + 0x81c, 0x05680003, + 0x81c, 0x046a0003, + 0x81c, 0x036c0003, + 0x81c, 0x026e0003, + 0x81c, 0x01700003, + 0x81c, 0x01720003, + 0x81c, 0x01740003, + 0x81c, 0x01760003, + 0x81c, 0x01780003, + 0x81c, 0x017a0003, + 0x81c, 0x017c0003, + 0x81c, 0x017e0003, + 0x81c, 0xff000813, + 0x81c, 0xfe020813, + 0x81c, 0xfd040813, + 0x81c, 0xfc060813, + 0x81c, 0xfb080813, + 0x81c, 0xfa0a0813, + 0x81c, 0xf90c0813, + 0x81c, 0xf80e0813, + 0x81c, 0xf7100813, + 0x81c, 0xf6120813, + 0x81c, 0xf5140813, + 0x81c, 0xf4160813, + 0x81c, 0xf3180813, + 0x81c, 0xf21a0813, + 0x81c, 0xf11c0813, + 0x81c, 0x961e0813, + 0x81c, 0x95200813, + 0x81c, 0x94220813, + 0x81c, 0x93240813, + 0x81c, 0x92260813, + 0x81c, 0x91280813, + 0x81c, 0x8f2a0813, + 0x81c, 0x8e2c0813, + 0x81c, 0x8d2e0813, + 0x81c, 0x8c300813, + 0x81c, 0x8b320813, + 0x81c, 0x8a340813, + 0x81c, 0x89360813, + 0x81c, 0x88380813, + 0x81c, 0x873a0813, + 0x81c, 0x863c0813, + 0x81c, 0x853e0813, + 0x81c, 0x84400813, + 0x81c, 0x83420813, + 0x81c, 0x82440813, + 0x81c, 0x08460813, + 0x81c, 0x07480813, + 0x81c, 0x064a0813, + 0x81c, 0x054c0813, + 0x81c, 0x044e0813, + 0x81c, 0x03500813, + 0x81c, 0x02520813, + 0x81c, 0x89540803, + 0x81c, 0x88560803, + 0x81c, 0x87580803, + 0x81c, 0x865a0803, + 0x81c, 0x855c0803, + 0x81c, 0x845e0803, + 0x81c, 0x83600803, + 0x81c, 0x82620803, + 0x81c, 0x07640803, + 0x81c, 0x06660803, + 0x81c, 0x05680803, + 0x81c, 0x046a0803, + 0x81c, 0x036c0803, + 0x81c, 0x026e0803, + 0x81c, 0x01700803, + 0x81c, 0x01720803, + 0x81c, 0x01740803, + 0x81c, 0x01760803, + 0x81c, 0x01780803, + 0x81c, 0x017a0803, + 0x81c, 0x017c0803, + 0x81c, 0x017e0803, + 0xb0000000, 0x00000000, +}; + +rtw_decl_table_phy_cond(rtw8821c_agc_btg_type2, rtw_phy_cfg_agc); + + 0x82000400, 0x00000000, 0x40000000, 0x00000000, + 0x8cc, 0x08190492, + 0xa0000000, 0x00000000, + 0xb0000000, 0x00000000, diff --git a/drivers/net/wireless/realtek/rtw88/rtw8821c_table.h b/drivers/net/wireless/realtek/rtw88/rtw8821c_table.h --- a/drivers/net/wireless/realtek/rtw88/rtw8821c_table.h +++ b/drivers/net/wireless/realtek/rtw88/rtw8821c_table.h +extern const struct rtw_table rtw8821c_agc_btg_type2_tbl;
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Networking
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5d6651fe85837b11564a2e2c3c6279c057d078d6
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guo feng fan kai heng feng kai heng feng canonical com
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drivers
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net
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realtek, rtw88, wireless
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rtw88: add dynamic rrsr configuration
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register rrsr determines the response rate we send. in field tests, using rate higher than current tx rate could lead to difficulty for the receiving end to receive management/control frames. calculate current modulation level by tx rate then cross out rate higher than those.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add dynamic rrsr configuration
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['rtw88 ']
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['h', 'c']
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| 74
| 3
|
--- diff --git a/drivers/net/wireless/realtek/rtw88/main.c b/drivers/net/wireless/realtek/rtw88/main.c --- a/drivers/net/wireless/realtek/rtw88/main.c +++ b/drivers/net/wireless/realtek/rtw88/main.c + struct rtw_dm_info *dm_info = &rtwdev->dm_info; + dm_info->rrsr_val_init = rrsr_init_5g; + dm_info->rrsr_val_init = rrsr_init_2g; diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h --- a/drivers/net/wireless/realtek/rtw88/main.h +++ b/drivers/net/wireless/realtek/rtw88/main.h +#define rrsr_init_2g 0x15f +#define rrsr_init_5g 0x150 + + u32 rrsr_val_init; + u32 rrsr_mask_min; diff --git a/drivers/net/wireless/realtek/rtw88/phy.c b/drivers/net/wireless/realtek/rtw88/phy.c --- a/drivers/net/wireless/realtek/rtw88/phy.c +++ b/drivers/net/wireless/realtek/rtw88/phy.c +static u32 rtw_phy_get_rrsr_mask(struct rtw_dev *rtwdev, u8 rate_idx) +{ + u8 rate_order; + + rate_order = rate_idx; + + if (rate_idx >= desc_ratevht4ss_mcs0) + rate_order -= desc_ratevht4ss_mcs0; + else if (rate_idx >= desc_ratevht3ss_mcs0) + rate_order -= desc_ratevht3ss_mcs0; + else if (rate_idx >= desc_ratevht2ss_mcs0) + rate_order -= desc_ratevht2ss_mcs0; + else if (rate_idx >= desc_ratevht1ss_mcs0) + rate_order -= desc_ratevht1ss_mcs0; + else if (rate_idx >= desc_ratemcs24) + rate_order -= desc_ratemcs24; + else if (rate_idx >= desc_ratemcs16) + rate_order -= desc_ratemcs16; + else if (rate_idx >= desc_ratemcs8) + rate_order -= desc_ratemcs8; + else if (rate_idx >= desc_ratemcs0) + rate_order -= desc_ratemcs0; + else if (rate_idx >= desc_rate6m) + rate_order -= desc_rate6m; + else + rate_order -= desc_rate1m; + + if (rate_idx >= desc_ratemcs0 || rate_order == 0) + rate_order++; + + return genmask(rate_order + rrsr_rate_order_cck_len - 1, 0); +} + +static void rtw_phy_rrsr_mask_min_iter(void *data, struct ieee80211_sta *sta) +{ + struct rtw_dev *rtwdev = (struct rtw_dev *)data; + struct rtw_sta_info *si = (struct rtw_sta_info *)sta->drv_priv; + struct rtw_dm_info *dm_info = &rtwdev->dm_info; + u32 mask = 0; + + mask = rtw_phy_get_rrsr_mask(rtwdev, si->ra_report.desc_rate); + if (mask < dm_info->rrsr_mask_min) + dm_info->rrsr_mask_min = mask; +} + +static void rtw_phy_rrsr_update(struct rtw_dev *rtwdev) +{ + struct rtw_dm_info *dm_info = &rtwdev->dm_info; + + dm_info->rrsr_mask_min = rrsr_rate_order_max; + rtw_iterate_stas_atomic(rtwdev, rtw_phy_rrsr_mask_min_iter, rtwdev); + rtw_write32(rtwdev, reg_rrsr, dm_info->rrsr_val_init & dm_info->rrsr_mask_min); +} + +static void rtw_phy_ra_track(struct rtw_dev *rtwdev) +{ + rtw_phy_ra_info_update(rtwdev); + rtw_phy_rrsr_update(rtwdev); +} + - rtw_phy_ra_info_update(rtwdev); + rtw_phy_ra_track(rtwdev); diff --git a/drivers/net/wireless/realtek/rtw88/phy.h b/drivers/net/wireless/realtek/rtw88/phy.h --- a/drivers/net/wireless/realtek/rtw88/phy.h +++ b/drivers/net/wireless/realtek/rtw88/phy.h +#define rrsr_rate_order_max 0xfffff +#define rrsr_rate_order_cck_len 4 + diff --git a/drivers/net/wireless/realtek/rtw88/reg.h b/drivers/net/wireless/realtek/rtw88/reg.h --- a/drivers/net/wireless/realtek/rtw88/reg.h +++ b/drivers/net/wireless/realtek/rtw88/reg.h +#define reg_rrsr 0x0440 +#define bits_rrsr_rsc genmask(22, 21) diff --git a/drivers/net/wireless/realtek/rtw88/rtw8822c.h b/drivers/net/wireless/realtek/rtw88/rtw8822c.h --- a/drivers/net/wireless/realtek/rtw88/rtw8822c.h +++ b/drivers/net/wireless/realtek/rtw88/rtw8822c.h -#define reg_rrsr 0x0440 -#define bits_rrsr_rsc (bit(21) | bit(22))
|
Networking
|
4830872685f80666b29bab6a930254809c18c40a
|
po hao huang brian norris briannorris chromium org
|
drivers
|
net
|
realtek, rtw88, wireless
|
rtw88: add napi support
|
use napi to reduce overhead on rx interrupts.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add napi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['rtw88 ']
|
['h', 'c']
| 3
| 145
| 24
|
--- diff --git a/drivers/net/wireless/realtek/rtw88/main.h b/drivers/net/wireless/realtek/rtw88/main.h --- a/drivers/net/wireless/realtek/rtw88/main.h +++ b/drivers/net/wireless/realtek/rtw88/main.h +#define rtw_napi_weight_num 64 diff --git a/drivers/net/wireless/realtek/rtw88/pci.c b/drivers/net/wireless/realtek/rtw88/pci.c --- a/drivers/net/wireless/realtek/rtw88/pci.c +++ b/drivers/net/wireless/realtek/rtw88/pci.c - struct rtw_pci *rtwpci) + struct rtw_pci *rtwpci, bool exclude_rx) + u32 imr0_unmask = exclude_rx ? imr_rok : 0; - rtw_write32(rtwdev, rtk_pci_himr0, rtwpci->irq_mask[0]); + rtw_write32(rtwdev, rtk_pci_himr0, rtwpci->irq_mask[0] & ~imr0_unmask); +static void rtw_pci_napi_start(struct rtw_dev *rtwdev) +{ + struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; + + if (test_and_set_bit(rtw_pci_flag_napi_running, rtwpci->flags)) + return; + + napi_enable(&rtwpci->napi); +} + +static void rtw_pci_napi_stop(struct rtw_dev *rtwdev) +{ + struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; + + if (!test_and_clear_bit(rtw_pci_flag_napi_running, rtwpci->flags)) + return; + + napi_synchronize(&rtwpci->napi); + napi_disable(&rtwpci->napi); +} + - rtw_pci_enable_interrupt(rtwdev, rtwpci); + rtw_pci_enable_interrupt(rtwdev, rtwpci, false); + rtw_pci_napi_start(rtwdev); + + rtw_pci_napi_stop(rtwdev); + -static void rtw_pci_rx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, - u8 hw_queue) +static void rtw_pci_rx_isr(struct rtw_dev *rtwdev) +{ + struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; + struct napi_struct *napi = &rtwpci->napi; + + napi_schedule(napi); +} + +static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev, + struct rtw_pci *rtwpci) - struct rtw_chip_info *chip = rtwdev->chip; + int count = 0; + u32 tmp, cur_wp; + + ring = &rtwpci->rx_rings[rtw_rx_queue_mpdu]; + tmp = rtw_read32(rtwdev, rtk_pci_rxbd_idx_mpduq); + cur_wp = u32_get_bits(tmp, trx_bd_hw_idx_mask); + if (cur_wp >= ring->r.wp) + count = cur_wp - ring->r.wp; + else + count = ring->r.len - (ring->r.wp - cur_wp); + + return count; +} + +static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, + u8 hw_queue, u32 limit) +{ + struct rtw_chip_info *chip = rtwdev->chip; + struct napi_struct *napi = &rtwpci->napi; + struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[rtw_rx_queue_mpdu]; - u32 cur_wp, cur_rp, tmp; - u32 count; + u32 cur_rp = ring->r.rp; + u32 count, rx_done = 0; - ring = &rtwpci->rx_rings[rtw_rx_queue_mpdu]; + count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci); + count = min(count, limit); - tmp = rtw_read32(rtwdev, rtk_pci_rxbd_idx_mpduq); - cur_wp = tmp >> 16; - cur_wp &= trx_bd_idx_mask; - if (cur_wp >= ring->r.wp) - count = cur_wp - ring->r.wp; - else - count = ring->r.len - (ring->r.wp - cur_wp); - - cur_rp = ring->r.rp; - ieee80211_rx_irqsafe(rtwdev->hw, new); + ieee80211_rx_napi(rtwdev->hw, null, new, napi); + rx_done++; - ring->r.wp = cur_wp; + /* 'rp', the last position we have read, is seen as previous posistion + * of 'wp' that is used to calculate 'count' next time. + */ + ring->r.wp = cur_rp; + + return rx_done; + bool rx = false; - if (irq_status[0] & imr_rok) - rtw_pci_rx_isr(rtwdev, rtwpci, rtw_rx_queue_mpdu); + if (irq_status[0] & imr_rok) { + rtw_pci_rx_isr(rtwdev); + rx = true; + } - rtw_pci_enable_interrupt(rtwdev, rtwpci); + rtw_pci_enable_interrupt(rtwdev, rtwpci, rx); +static int rtw_pci_napi_poll(struct napi_struct *napi, int budget) +{ + struct rtw_pci *rtwpci = container_of(napi, struct rtw_pci, napi); + struct rtw_dev *rtwdev = container_of((void *)rtwpci, struct rtw_dev, + priv); + int work_done = 0; + + while (work_done < budget) { + u32 work_done_once; + + work_done_once = rtw_pci_rx_napi(rtwdev, rtwpci, rtw_rx_queue_mpdu, + budget - work_done); + if (work_done_once == 0) + break; + work_done += work_done_once; + } + if (work_done < budget) { + napi_complete_done(napi, work_done); + spin_lock_bh(&rtwpci->irq_lock); + rtw_pci_enable_interrupt(rtwdev, rtwpci, false); + spin_unlock_bh(&rtwpci->irq_lock); + /* when isr happens during polling and before napi_complete + * while no further data is received. data on the dma_ring will + * not be processed immediately. check whether dma ring is + * empty and perform napi_schedule accordingly. + */ + if (rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci)) + napi_schedule(napi); + } + + return work_done; +} + +static void rtw_pci_napi_init(struct rtw_dev *rtwdev) +{ + struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; + + init_dummy_netdev(&rtwpci->netdev); + netif_napi_add(&rtwpci->netdev, &rtwpci->napi, rtw_pci_napi_poll, + rtw_napi_weight_num); +} + +static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev) +{ + struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; + + rtw_pci_napi_stop(rtwdev); + netif_napi_del(&rtwpci->napi); +} + + rtw_pci_napi_init(rtwdev); + + rtw_pci_napi_deinit(rtwdev); + rtw_pci_napi_deinit(rtwdev); diff --git a/drivers/net/wireless/realtek/rtw88/pci.h b/drivers/net/wireless/realtek/rtw88/pci.h --- a/drivers/net/wireless/realtek/rtw88/pci.h +++ b/drivers/net/wireless/realtek/rtw88/pci.h +#define trx_bd_hw_idx_mask genmask(27, 16) +enum rtw_pci_flags { + rtw_pci_flag_napi_running, + + num_of_rtw_pci_flags, +}; + - /* used for pci tx queueing. */ + /* used for pci tx ring/queueing, and enable int. */ + /* napi structure */ + struct net_device netdev; + struct napi_struct napi; + + declare_bitmap(flags, num_of_rtw_pci_flags);
|
Networking
|
9e2fd29864c5c677e80846442be192090f16fdb3
|
po hao huang
|
drivers
|
net
|
realtek, rtw88, wireless
|
net: sfp: add debugfs support
|
add debugfs support to sfp so that the internal state of the sfp state machines and hardware signal state can be viewed from userspace, rather than having to compile a debug kernel to view state transitions in the kernel log. the 'state' output looks like:
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add debugfs support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sfp ']
|
['c']
| 1
| 55
| 0
|
--- diff --git a/drivers/net/phy/sfp.c b/drivers/net/phy/sfp.c --- a/drivers/net/phy/sfp.c +++ b/drivers/net/phy/sfp.c +#include <linux/debugfs.h> +#if is_enabled(config_debug_fs) + struct dentry *debugfs_dir; +#endif +#if is_enabled(config_debug_fs) +static int sfp_debug_state_show(struct seq_file *s, void *data) +{ + struct sfp *sfp = s->private; + + seq_printf(s, "module state: %s ", + mod_state_to_str(sfp->sm_mod_state)); + seq_printf(s, "module probe attempts: %d %d ", + r_probe_retry_init - sfp->sm_mod_tries_init, + r_probe_retry_slow - sfp->sm_mod_tries); + seq_printf(s, "device state: %s ", + dev_state_to_str(sfp->sm_dev_state)); + seq_printf(s, "main state: %s ", + sm_state_to_str(sfp->sm_state)); + seq_printf(s, "fault recovery remaining retries: %d ", + sfp->sm_fault_retries); + seq_printf(s, "phy probe remaining retries: %d ", + sfp->sm_phy_retries); + seq_printf(s, "moddef0: %d ", !!(sfp->state & sfp_f_present)); + seq_printf(s, "rx_los: %d ", !!(sfp->state & sfp_f_los)); + seq_printf(s, "tx_fault: %d ", !!(sfp->state & sfp_f_tx_fault)); + seq_printf(s, "tx_disable: %d ", !!(sfp->state & sfp_f_tx_disable)); + return 0; +} +define_show_attribute(sfp_debug_state); + +static void sfp_debugfs_init(struct sfp *sfp) +{ + sfp->debugfs_dir = debugfs_create_dir(dev_name(sfp->dev), null); + + debugfs_create_file("state", 0600, sfp->debugfs_dir, sfp, + &sfp_debug_state_fops); +} + +static void sfp_debugfs_exit(struct sfp *sfp) +{ + debugfs_remove_recursive(sfp->debugfs_dir); +} +#else +static void sfp_debugfs_init(struct sfp *sfp) +{ +} + +static void sfp_debugfs_exit(struct sfp *sfp) +{ +} +#endif + + sfp_debugfs_init(sfp); + + sfp_debugfs_exit(sfp);
|
Networking
|
9cc8976c69eb626a7a5100239eb7c69b1a1a609f
|
russell king
|
drivers
|
net
|
phy
|
sfp: add support for 100 base-x sfps
|
add support for 100base-fx, 100base-lx, 100base-px and 100base-bx10 modules this is needed for sparx-5 switch.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for 100 base-x sfps
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sfp ']
|
['c']
| 1
| 9
| 0
|
--- diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c --- a/drivers/net/phy/sfp-bus.c +++ b/drivers/net/phy/sfp-bus.c + /* 100base-fx, 100base-lx, 100base-px, 100base-bx10 */ + if (id->base.e100_base_fx || id->base.e100_base_lx) + phylink_set(modes, 100basefx_full); + if ((id->base.e_base_px || id->base.e_base_bx10) && br_nom == 100) + phylink_set(modes, 100basefx_full); + + if (phylink_test(link_modes, 100basefx_full)) + return phy_interface_mode_100basex; +
|
Networking
|
6e12f35cef6b8a458d7ecf507ae330e0bffaad8c
|
bjarni jonasson russell king rmk kernel armlinux org uk
|
drivers
|
net
|
phy
|
sfp: add support for 5gbase-t sfps
|
the sfp_parse_support() function is setting 5000baset_full in some cases. now that we have phy_interface_mode_5gbaser interface mode available, change sfp_select_interface() to return phy_interface_mode_5gbaser if 5000baset_full is set in the link mode mask.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for 5gbase-t sfps
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['sfp ']
|
['c']
| 1
| 3
| 0
|
--- diff --git a/drivers/net/phy/sfp-bus.c b/drivers/net/phy/sfp-bus.c --- a/drivers/net/phy/sfp-bus.c +++ b/drivers/net/phy/sfp-bus.c + if (phylink_test(link_modes, 5000baset_full)) + return phy_interface_mode_5gbaser; +
|
Networking
|
cfb971dec56b0ea1afe34b67d9481a9d29e65a58
|
marek beh n
|
drivers
|
net
|
phy
|
net: stmmac: add pci bus info to ethtool driver query output
|
this patch populates the pci bus info in the ethtool driver query data.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pci bus info to ethtool driver query output
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ']
|
['h', 'c']
| 3
| 6
| 0
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c + plat->pdev = pdev; diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c + if (priv->plat->pdev) { + strlcpy(info->bus_info, pci_name(priv->plat->pdev), + sizeof(info->bus_info)); + } diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h + struct pci_dev *pdev;
|
Networking
|
20e07e2c3cf310578ef19fb4f1e64dc9832abd9d
|
wong vee khee
|
include
|
linux
|
ethernet, stmicro, stmmac
|
net: stmmac: add toshiba visconti socs glue driver
|
add dwmac-visconti to the stmmac driver in toshiba visconti arm socs. this patch contains only the basic function of the device. there is no clock control, pm, etc. yet. these will be added in the future.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add toshiba visconti socs glue driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ']
|
['kconfig', 'c', 'makefile']
| 3
| 294
| 0
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/kconfig b/drivers/net/ethernet/stmicro/stmmac/kconfig --- a/drivers/net/ethernet/stmicro/stmmac/kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/kconfig + +config dwmac_visconti + tristate "toshiba visconti dwmac support" + default arch_visconti + depends on of && common_clk && (arch_visconti || compile_test) + help + support for ethernet controller on visconti socs. + diff --git a/drivers/net/ethernet/stmicro/stmmac/makefile b/drivers/net/ethernet/stmicro/stmmac/makefile --- a/drivers/net/ethernet/stmicro/stmmac/makefile +++ b/drivers/net/ethernet/stmicro/stmmac/makefile +obj-$(config_dwmac_visconti) += dwmac-visconti.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c +// spdx-license-identifier: gpl-2.0 +/* toshiba visconti ethernet support + * + * (c) copyright 2020 toshiba corporation + * (c) copyright 2020 toshiba electronic devices & storage corporation + */ + +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_net.h> +#include <linux/stmmac.h> + +#include "stmmac_platform.h" +#include "dwmac4.h" + +#define reg_ether_control 0x52d4 +#define ether_eth_control_reset bit(17) + +#define reg_ether_clock_sel 0x52d0 +#define ether_clk_sel_tx_clk_en bit(0) +#define ether_clk_sel_rx_clk_en bit(1) +#define ether_clk_sel_rmii_clk_en bit(2) +#define ether_clk_sel_rmii_clk_rst bit(3) +#define ether_clk_sel_div_sel_2 bit(4) +#define ether_clk_sel_div_sel_20 bit(0) +#define ether_clk_sel_freq_sel_125m (bit(9) | bit(8)) +#define ether_clk_sel_freq_sel_50m bit(9) +#define ether_clk_sel_freq_sel_25m bit(8) +#define ether_clk_sel_freq_sel_2p5m bit(0) +#define ether_clk_sel_tx_clk_ext_sel_in bit(0) +#define ether_clk_sel_tx_clk_ext_sel_txc bit(10) +#define ether_clk_sel_tx_clk_ext_sel_div bit(11) +#define ether_clk_sel_rx_clk_ext_sel_in bit(0) +#define ether_clk_sel_rx_clk_ext_sel_rxc bit(12) +#define ether_clk_sel_rx_clk_ext_sel_div bit(13) +#define ether_clk_sel_tx_clk_o_tx_i bit(0) +#define ether_clk_sel_tx_clk_o_rmii_i bit(14) +#define ether_clk_sel_tx_o_e_n_in bit(15) +#define ether_clk_sel_rmii_clk_sel_in bit(0) +#define ether_clk_sel_rmii_clk_sel_rx_c bit(16) + +#define ether_clk_sel_rx_tx_clk_en (ether_clk_sel_rx_clk_en | ether_clk_sel_tx_clk_en) + +#define ether_config_intf_mii 0 +#define ether_config_intf_rgmii bit(0) +#define ether_config_intf_rmii bit(2) + +struct visconti_eth { + void __iomem *reg; + u32 phy_intf_sel; + struct clk *phy_ref_clk; + spinlock_t lock; /* lock to protect register update */ +}; + +static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed) +{ + struct visconti_eth *dwmac = priv; + unsigned int val, clk_sel_val; + unsigned long flags; + + spin_lock_irqsave(&dwmac->lock, flags); + + /* adjust link */ + val = readl(dwmac->reg + mac_ctrl_reg); + val &= ~(gmac_config_ps | gmac_config_fes); + + switch (speed) { + case speed_1000: + if (dwmac->phy_intf_sel == ether_config_intf_rgmii) + clk_sel_val = ether_clk_sel_freq_sel_125m; + break; + case speed_100: + if (dwmac->phy_intf_sel == ether_config_intf_rgmii) + clk_sel_val = ether_clk_sel_freq_sel_25m; + if (dwmac->phy_intf_sel == ether_config_intf_rmii) + clk_sel_val = ether_clk_sel_div_sel_2; + val |= gmac_config_ps | gmac_config_fes; + break; + case speed_10: + if (dwmac->phy_intf_sel == ether_config_intf_rgmii) + clk_sel_val = ether_clk_sel_freq_sel_2p5m; + if (dwmac->phy_intf_sel == ether_config_intf_rmii) + clk_sel_val = ether_clk_sel_div_sel_20; + val |= gmac_config_ps; + break; + default: + /* no bit control */ + break; + } + + writel(val, dwmac->reg + mac_ctrl_reg); + + /* stop internal clock */ + val = readl(dwmac->reg + reg_ether_clock_sel); + val &= ~(ether_clk_sel_rmii_clk_en | ether_clk_sel_rx_tx_clk_en); + val |= ether_clk_sel_tx_o_e_n_in; + writel(val, dwmac->reg + reg_ether_clock_sel); + + switch (dwmac->phy_intf_sel) { + case ether_config_intf_rgmii: + val = clk_sel_val | ether_clk_sel_rx_clk_ext_sel_rxc; + break; + case ether_config_intf_rmii: + val = clk_sel_val | ether_clk_sel_rx_clk_ext_sel_div | + ether_clk_sel_tx_clk_ext_sel_txc | ether_clk_sel_tx_o_e_n_in | + ether_clk_sel_rmii_clk_sel_rx_c; + break; + case ether_config_intf_mii: + default: + val = clk_sel_val | ether_clk_sel_rx_clk_ext_sel_rxc | + ether_clk_sel_tx_clk_ext_sel_div | ether_clk_sel_tx_o_e_n_in | + ether_clk_sel_rmii_clk_en; + break; + } + + /* start clock */ + writel(val, dwmac->reg + reg_ether_clock_sel); + val |= ether_clk_sel_rx_tx_clk_en; + writel(val, dwmac->reg + reg_ether_clock_sel); + + val &= ~ether_clk_sel_tx_o_e_n_in; + writel(val, dwmac->reg + reg_ether_clock_sel); + + spin_unlock_irqrestore(&dwmac->lock, flags); +} + +static int visconti_eth_init_hw(struct platform_device *pdev, struct plat_stmmacenet_data *plat_dat) +{ + struct visconti_eth *dwmac = plat_dat->bsp_priv; + unsigned int reg_val, clk_sel_val; + + switch (plat_dat->phy_interface) { + case phy_interface_mode_rgmii: + case phy_interface_mode_rgmii_id: + case phy_interface_mode_rgmii_rxid: + case phy_interface_mode_rgmii_txid: + dwmac->phy_intf_sel = ether_config_intf_rgmii; + break; + case phy_interface_mode_mii: + dwmac->phy_intf_sel = ether_config_intf_mii; + break; + case phy_interface_mode_rmii: + dwmac->phy_intf_sel = ether_config_intf_rmii; + break; + default: + dev_err(&pdev->dev, "unsupported phy-mode (%d) ", plat_dat->phy_interface); + return -eopnotsupp; + } + + reg_val = dwmac->phy_intf_sel; + writel(reg_val, dwmac->reg + reg_ether_control); + + /* enable tx/rx clock */ + clk_sel_val = ether_clk_sel_freq_sel_125m; + writel(clk_sel_val, dwmac->reg + reg_ether_clock_sel); + + writel((clk_sel_val | ether_clk_sel_rmii_clk_en | ether_clk_sel_rx_tx_clk_en), + dwmac->reg + reg_ether_clock_sel); + + /* release internal-reset */ + reg_val |= ether_eth_control_reset; + writel(reg_val, dwmac->reg + reg_ether_control); + + return 0; +} + +static int visconti_eth_clock_probe(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat) +{ + struct visconti_eth *dwmac = plat_dat->bsp_priv; + int err; + + dwmac->phy_ref_clk = devm_clk_get(&pdev->dev, "phy_ref_clk"); + if (is_err(dwmac->phy_ref_clk)) { + dev_err(&pdev->dev, "phy_ref_clk clock not found. "); + return ptr_err(dwmac->phy_ref_clk); + } + + err = clk_prepare_enable(dwmac->phy_ref_clk); + if (err < 0) { + dev_err(&pdev->dev, "failed to enable phy_ref clock: %d ", err); + return err; + } + + return 0; +} + +static int visconti_eth_clock_remove(struct platform_device *pdev) +{ + struct visconti_eth *dwmac = get_stmmac_bsp_priv(&pdev->dev); + struct net_device *ndev = platform_get_drvdata(pdev); + struct stmmac_priv *priv = netdev_priv(ndev); + + clk_disable_unprepare(dwmac->phy_ref_clk); + clk_disable_unprepare(priv->plat->stmmac_clk); + + return 0; +} + +static int visconti_eth_dwmac_probe(struct platform_device *pdev) +{ + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + struct visconti_eth *dwmac; + int ret; + + ret = stmmac_get_platform_resources(pdev, &stmmac_res); + if (ret) + return ret; + + plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac); + if (is_err(plat_dat)) + return ptr_err(plat_dat); + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), gfp_kernel); + if (!dwmac) { + ret = -enomem; + goto remove_config; + } + + dwmac->reg = stmmac_res.addr; + plat_dat->bsp_priv = dwmac; + plat_dat->fix_mac_speed = visconti_eth_fix_mac_speed; + + ret = visconti_eth_clock_probe(pdev, plat_dat); + if (ret) + goto remove_config; + + visconti_eth_init_hw(pdev, plat_dat); + + plat_dat->dma_cfg->aal = 1; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto remove; + + return ret; + +remove: + visconti_eth_clock_remove(pdev); +remove_config: + stmmac_remove_config_dt(pdev, plat_dat); + + return ret; +} + +static int visconti_eth_dwmac_remove(struct platform_device *pdev) +{ + struct net_device *ndev = platform_get_drvdata(pdev); + struct stmmac_priv *priv = netdev_priv(ndev); + int err; + + err = stmmac_pltfr_remove(pdev); + if (err < 0) + dev_err(&pdev->dev, "failed to remove platform: %d ", err); + + err = visconti_eth_clock_remove(pdev); + if (err < 0) + dev_err(&pdev->dev, "failed to remove clock: %d ", err); + + stmmac_remove_config_dt(pdev, priv->plat); + + return err; +} + +static const struct of_device_id visconti_eth_dwmac_match[] = { + { .compatible = "toshiba,visconti-dwmac" }, + { } +}; +module_device_table(of, visconti_eth_dwmac_match); + +static struct platform_driver visconti_eth_dwmac_driver = { + .probe = visconti_eth_dwmac_probe, + .remove = visconti_eth_dwmac_remove, + .driver = { + .name = "visconti-eth-dwmac", + .of_match_table = visconti_eth_dwmac_match, + }, +}; +module_platform_driver(visconti_eth_dwmac_driver); + +module_author("toshiba"); +module_description("toshiba visconti ethernet dwmac glue driver"); +module_author("nobuhiro iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp"); +module_license("gpl v2");
|
Networking
|
b38dd98ff8d0d951770bffdca49b387dc63ba92b
|
nobuhiro iwamatsu
|
drivers
|
net
|
ethernet, stmicro, stmmac
|
dt-bindings: net: dwmac-meson: use picoseconds for the rgmii rx delay
|
amlogic meson g12a, g12b and sm1 socs have a more advanced rgmii rx delay register which allows picoseconds precision. deprecate the old "amlogic,rx-delay-ns" in favour of the generic "rx-internal-delay-ps" property.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
picosecond precision rx delay support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ', 'dwmac-meson8b']
|
['yaml']
| 1
| 49
| 6
|
--- diff --git a/documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml --- a/documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml + deprecated: true - 0 - 2 - the internal rgmii rx clock delay (provided by this ip block) in - nanoseconds. when phy-mode is set to "rgmii" then the rx delay - should be explicitly configured. when the phy-mode is set to - either "rgmii-id" or "rgmii-rxid" the rx clock delay is already - provided by the phy. any configuration is ignored when the - phy-mode is set to "rmii". + the internal rgmii rx clock delay in nanoseconds. deprecated, use + rx-internal-delay-ps instead. + + rx-internal-delay-ps: + default: 0 + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson8b-dwmac + - amlogic,meson8m2-dwmac + - amlogic,meson-gxbb-dwmac + - amlogic,meson-axg-dwmac + then: + properties: + rx-internal-delay-ps: + enum: + - 0 + - 2000 + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-g12a-dwmac + then: + properties: + rx-internal-delay-ps: + enum: + - 0 + - 200 + - 400 + - 600 + - 800 + - 1000 + - 1200 + - 1400 + - 1600 + - 1800 + - 2000 + - 2200 + - 2400 + - 2600 + - 2800 + - 3000
|
Networking
|
6b5903f58df44d4cb35319555b974d6a10f1b03f
|
martin blumenstingl
|
documentation
|
devicetree
|
bindings, net
|
net: stmmac: dwmac-meson8b: fix enabling the timing-adjustment clock
|
the timing-adjustment clock only has to be enabled when a) there is a 2ns rx delay configured using device-tree and b) the phy-mode indicates that the rx delay should be enabled.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
picosecond precision rx delay support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ', 'dwmac-meson8b']
|
['c']
| 1
| 1
| 1
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c - if (rx_dly_config & prg_eth0_adj_enable) { + if (delay_config & prg_eth0_adj_enable) {
|
Networking
|
025822884a4fd2d0af51dcf77ddc494e60c5ff63
|
martin blumenstingl
|
drivers
|
net
|
ethernet, stmicro, stmmac
|
net: stmmac: dwmac-meson8b: use picoseconds for the rgmii rx delay
|
amlogic meson g12a, g12b and sm1 socs have a more advanced rgmii rx delay register which allows picoseconds precision. parse the new "rx-internal-delay-ps" property or fall back to the value from the old "amlogic,rx-delay-ns" property.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
picosecond precision rx delay support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ', 'dwmac-meson8b']
|
['c']
| 1
| 13
| 8
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c - u32 rx_delay_ns; + u32 rx_delay_ps; - if (dwmac->rx_delay_ns == 2) + if (dwmac->rx_delay_ps == 2000) - /* use 0ns as fallback since this is what most boards actually use */ - if (of_property_read_u32(pdev->dev.of_node, "amlogic,rx-delay-ns", - &dwmac->rx_delay_ns)) - dwmac->rx_delay_ns = 0; + /* rx delay defaults to 0ps since this is what many boards use */ + if (of_property_read_u32(pdev->dev.of_node, "rx-internal-delay-ps", + &dwmac->rx_delay_ps)) { + if (!of_property_read_u32(pdev->dev.of_node, + "amlogic,rx-delay-ns", + &dwmac->rx_delay_ps)) + /* convert ns to ps */ + dwmac->rx_delay_ps *= 1000; + } - if (dwmac->rx_delay_ns != 0 && dwmac->rx_delay_ns != 2) { + if (dwmac->rx_delay_ps != 0 && dwmac->rx_delay_ps != 2000) { - "the only allowed rx delays values are: 0ns, 2ns"); + "the only allowed rx delays values are: 0ps, 2000ps");
|
Networking
|
140ddf0633dfb923fcf4132289fd022dde0145fc
|
martin blumenstingl
|
drivers
|
net
|
ethernet, stmicro, stmmac
|
net: stmmac: dwmac-meson8b: move rgmii delays into a separate function
|
newer socs starting with the amlogic meson g12a have more a precise rgmii rx delay configuration register. this means more complexity in the code. extract the existing rgmii delay configuration code into a separate function to make it easier to read/understand even when adding more logic in the future.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
picosecond precision rx delay support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ', 'dwmac-meson8b']
|
['c']
| 1
| 12
| 1
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c -static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) +static int meson8b_init_rgmii_delays(struct meson8b_dwmac *dwmac) + return 0; +} + +static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac) +{ + int ret; + + ret = meson8b_init_rgmii_delays(dwmac); + if (ret) + goto err_remove_config_dt; +
|
Networking
|
7985244d10eada10d36804752f21dfce1fea0018
|
martin blumenstingl andrew lunn andrew lunn ch florian fainelli f fainelli gmail com
|
drivers
|
net
|
ethernet, stmicro, stmmac
|
net: stmmac: dwmac-meson8b: add support for the rgmii rx delay on g12a
|
amlogic meson g12a (and newer: g12b, sm1) socs have a more advanced rx delay logic. instead of fine-tuning the delay in the nanoseconds range it now allows tuning in 200 picosecond steps. this support comes with new bits in the prg_eth1[19:16] register.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
picosecond precision rx delay support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ', 'dwmac-meson8b']
|
['c']
| 1
| 48
| 13
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson8b.c +#define prg_eth1 0x4 + +/* defined for adding a delay to the input rx_clk for better timing. + * each step is 200ps. these bits are used with external rgmii phys + * because rgmii rx only has the small window. cfg_rxclk_dly can + * adjust the window between rx_clk and rx_data and improve the stability + * of "rx data valid". + */ +#define prg_eth1_cfg_rxclk_dly genmask(19, 16) + + bool has_prg_eth1_rgmii_rx_delay; - u32 tx_dly_config, rx_dly_config, delay_config; + u32 tx_dly_config, rx_adj_config, cfg_rxclk_dly, delay_config; + rx_adj_config = 0; + cfg_rxclk_dly = 0; - if (dwmac->rx_delay_ps == 2000) - rx_dly_config = prg_eth0_adj_enable | prg_eth0_adj_setup; - else - rx_dly_config = 0; + if (dwmac->data->has_prg_eth1_rgmii_rx_delay) + cfg_rxclk_dly = field_prep(prg_eth1_cfg_rxclk_dly, + dwmac->rx_delay_ps / 200); + else if (dwmac->rx_delay_ps == 2000) + rx_adj_config = prg_eth0_adj_enable | prg_eth0_adj_setup; - delay_config = tx_dly_config | rx_dly_config; + delay_config = tx_dly_config | rx_adj_config; + cfg_rxclk_dly = 0; - delay_config = rx_dly_config; + delay_config = rx_adj_config; + cfg_rxclk_dly = 0; + meson8b_dwmac_mask_bits(dwmac, prg_eth1, prg_eth1_cfg_rxclk_dly, + cfg_rxclk_dly); + - if (dwmac->rx_delay_ps != 0 && dwmac->rx_delay_ps != 2000) { - dev_err(&pdev->dev, - "the only allowed rx delays values are: 0ps, 2000ps"); - ret = -einval; - goto err_remove_config_dt; + if (dwmac->data->has_prg_eth1_rgmii_rx_delay) { + if (dwmac->rx_delay_ps != 0 && dwmac->rx_delay_ps != 2000) { + dev_err(dwmac->dev, + "the only allowed rgmii rx delays values are: 0ps, 2000ps"); + ret = -einval; + goto err_remove_config_dt; + } + } else { + if (dwmac->rx_delay_ps > 3000 || dwmac->rx_delay_ps % 200) { + dev_err(dwmac->dev, + "the rgmii rx delay range is 0..3000ps in 200ps steps"); + ret = -einval; + goto err_remove_config_dt; + } + .has_prg_eth1_rgmii_rx_delay = false, + .has_prg_eth1_rgmii_rx_delay = false, +}; + +static const struct meson8b_dwmac_data meson_g12a_dwmac_data = { + .set_phy_mode = meson_axg_set_phy_mode, + .has_prg_eth1_rgmii_rx_delay = true, - .data = &meson_axg_dwmac_data, + .data = &meson_g12a_dwmac_data,
|
Networking
|
de94fc104d58ea2f53e46404b0c2b73b9bdf5774
|
martin blumenstingl
|
drivers
|
net
|
ethernet, stmicro, stmmac
|
stmmac: intel: add adl-s 1gbps pci ids
|
added pci ids for both ethernet tsn controllers on the adl-s.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add adl-s 1gbps pci ids
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['stmmac ', 'intel']
|
['c']
| 1
| 19
| 0
|
--- diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +static int adls_sgmii_data(struct pci_dev *pdev, + struct plat_stmmacenet_data *plat) +{ + plat->bus_id = 1; + plat->phy_interface = phy_interface_mode_sgmii; + + /* serdes power up and power down are done in bios for adl */ + + return tgl_common_data(pdev, plat); +} + +static struct stmmac_pci_info adls_sgmii1g_info = { + .setup = adls_sgmii_data, +}; + +#define pci_device_id_intel_adls_sgmii1g_0_id 0x7aac +#define pci_device_id_intel_adls_sgmii1g_1_id 0x7aad + { pci_device_data(intel, adls_sgmii1g_0_id, &adls_sgmii1g_info) }, + { pci_device_data(intel, adls_sgmii1g_1_id, &adls_sgmii1g_info) },
|
Networking
|
88af9bd4efbd4d171eea537486493c9601c9a486
|
wong vee khee
|
drivers
|
net
|
ethernet, stmicro, stmmac
|
net: ti: am65-cpsw-nuss: add devlink support
|
am65 nuss ethernet switch on k3 devices can be configured to work either in independent mac mode where each port acts as independent network interface (multi mac) or switch mode.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add switchdev support for am65 cpsw nuss driver to support multi port cpsw present on j721e and am64 socs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ti']
|
['h', 'kconfig', 'c', 'rst']
| 5
| 404
| 18
|
--- diff --git a/documentation/networking/devlink/am65-nuss-cpsw-switch.rst b/documentation/networking/devlink/am65-nuss-cpsw-switch.rst --- /dev/null +++ b/documentation/networking/devlink/am65-nuss-cpsw-switch.rst +.. spdx-license-identifier: gpl-2.0 + +============================== +am65-cpsw-nuss devlink support +============================== + +this document describes the devlink features implemented by the ''am65-cpsw-nuss'' +device driver. + +parameters +========== + +the ''am65-cpsw-nuss'' driver implements the following driver-specific +parameters. + +.. list-table:: driver-specific parameters implemented + :widths: 5 5 5 85 + + * - name + - type + - mode + - description + * - ''switch_mode'' + - boolean + - runtime + - enable switch mode diff --git a/documentation/networking/devlink/index.rst b/documentation/networking/devlink/index.rst --- a/documentation/networking/devlink/index.rst +++ b/documentation/networking/devlink/index.rst + am65-nuss-cpsw-switch diff --git a/drivers/net/ethernet/ti/kconfig b/drivers/net/ethernet/ti/kconfig --- a/drivers/net/ethernet/ti/kconfig +++ b/drivers/net/ethernet/ti/kconfig + select net_devlink +config ti_k3_am65_cpsw_switchdev + bool "ti k3 am654x/j721e cpsw switch mode support" + depends on ti_k3_am65_cpsw_nuss + depends on net_switchdev + help + this enables switchdev support for ti k3 cpswxg ethernet + switch. enable this driver to support hardware switch support for am65 + cpsw nuss driver. + diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c +static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); +static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); +static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); +static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); + - if (am65_cpsw_is_cpsw2g(common)) - cpsw_ale_control_set(common->ale, host_port_num, - ale_port_nolearn, 1); + if (common->is_emac_mode) + am65_cpsw_init_host_port_emac(common); + else + am65_cpsw_init_host_port_switch(common); + - u32 port_mask; - if (port->slave.mac_only) { - /* enable mac-only mode on port */ - cpsw_ale_control_set(common->ale, port->port_id, - ale_port_maconly, 1); - cpsw_ale_control_set(common->ale, port->port_id, - ale_port_nolearn, 1); - } - - port_mask = bit(port->port_id) | ale_port_host; - cpsw_ale_add_ucast(common->ale, ndev->dev_addr, - host_port_num, ale_secure, 0); - cpsw_ale_add_mcast(common->ale, ndev->broadcast, - port_mask, 0, 0, ale_mcast_fwd_2); + if (common->is_emac_mode) + am65_cpsw_init_port_emac_ale(port); + else + am65_cpsw_init_port_switch_ale(port); +static struct devlink_port *am65_cpsw_ndo_get_devlink_port(struct net_device *ndev) +{ + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + + return &port->devlink_port; +} + + .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port, +static const struct devlink_ops am65_cpsw_devlink_ops = {}; + +static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) +{ + cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ale_port_host, ale_super, 0, + ale_mcast_block_learn_fwd); +} + +static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) +{ + struct am65_cpsw_host *host = am65_common_get_host(common); + + writel(common->default_vlan, host->port_base + am65_cpsw_port_vlan_reg_offset); + + am65_cpsw_init_stp_ale_entry(common); + + cpsw_ale_control_set(common->ale, host_port_num, ale_p0_uni_flood, 1); + dev_dbg(common->dev, "set p0_uni_flood "); + cpsw_ale_control_set(common->ale, host_port_num, ale_port_nolearn, 0); +} + +static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) +{ + struct am65_cpsw_host *host = am65_common_get_host(common); + + writel(0, host->port_base + am65_cpsw_port_vlan_reg_offset); + + cpsw_ale_control_set(common->ale, host_port_num, ale_p0_uni_flood, 0); + dev_dbg(common->dev, "unset p0_uni_flood "); + + /* learning make no sense in multi-mac mode */ + cpsw_ale_control_set(common->ale, host_port_num, ale_port_nolearn, 1); +} + +static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); + struct am65_cpsw_common *common = dl_priv->common; + + dev_dbg(common->dev, "%s id:%u ", __func__, id); + + if (id != am65_cpsw_dl_param_switch_mode) + return -eopnotsupp; + + ctx->val.vbool = !common->is_emac_mode; + + return 0; +} + +static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) +{ + struct am65_cpsw_slave_data *slave = &port->slave; + struct am65_cpsw_common *common = port->common; + u32 port_mask; + + writel(slave->port_vlan, port->port_base + am65_cpsw_port_vlan_reg_offset); + + if (slave->mac_only) + /* enable mac-only mode on port */ + cpsw_ale_control_set(common->ale, port->port_id, + ale_port_maconly, 1); + + cpsw_ale_control_set(common->ale, port->port_id, ale_port_nolearn, 1); + + port_mask = bit(port->port_id) | ale_port_host; + + cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, + host_port_num, ale_secure, slave->port_vlan); + cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, + port_mask, ale_vlan, slave->port_vlan, ale_mcast_fwd_2); +} + +static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) +{ + struct am65_cpsw_slave_data *slave = &port->slave; + struct am65_cpsw_common *cpsw = port->common; + u32 port_mask; + + cpsw_ale_control_set(cpsw->ale, port->port_id, + ale_port_nolearn, 0); + + cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, + host_port_num, ale_secure | ale_blocked | ale_vlan, + slave->port_vlan); + + port_mask = bit(port->port_id) | ale_port_host; + + cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, + port_mask, ale_vlan, slave->port_vlan, + ale_mcast_fwd_2); + + writel(slave->port_vlan, port->port_base + am65_cpsw_port_vlan_reg_offset); + + cpsw_ale_control_set(cpsw->ale, port->port_id, + ale_port_maconly, 0); +} + +static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, + struct devlink_param_gset_ctx *ctx) +{ + struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); + struct am65_cpsw_common *cpsw = dl_priv->common; + bool switch_en = ctx->val.vbool; + bool if_running = false; + int i; + + dev_dbg(cpsw->dev, "%s id:%u ", __func__, id); + + if (id != am65_cpsw_dl_param_switch_mode) + return -eopnotsupp; + + if (switch_en == !cpsw->is_emac_mode) + return 0; + + if (!switch_en && cpsw->br_members) { + dev_err(cpsw->dev, "remove ports from bridge before disabling switch mode "); + return -einval; + } + + rtnl_lock(); + + cpsw->is_emac_mode = !switch_en; + + for (i = 0; i < cpsw->port_num; i++) { + struct net_device *sl_ndev = cpsw->ports[i].ndev; + + if (!sl_ndev || !netif_running(sl_ndev)) + continue; + + if_running = true; + } + + if (!if_running) { + /* all ndevs are down */ + for (i = 0; i < cpsw->port_num; i++) { + struct net_device *sl_ndev = cpsw->ports[i].ndev; + struct am65_cpsw_slave_data *slave; + + if (!sl_ndev) + continue; + + slave = am65_ndev_to_slave(sl_ndev); + if (switch_en) + slave->port_vlan = cpsw->default_vlan; + else + slave->port_vlan = 0; + } + + goto exit; + } + + cpsw_ale_control_set(cpsw->ale, 0, ale_bypass, 1); + /* clean up ale table */ + cpsw_ale_control_set(cpsw->ale, host_port_num, ale_clear, 1); + cpsw_ale_control_get(cpsw->ale, host_port_num, ale_ageout); + + if (switch_en) { + dev_info(cpsw->dev, "enable switch mode "); + + am65_cpsw_init_host_port_switch(cpsw); + + for (i = 0; i < cpsw->port_num; i++) { + struct net_device *sl_ndev = cpsw->ports[i].ndev; + struct am65_cpsw_slave_data *slave; + struct am65_cpsw_port *port; + + if (!sl_ndev) + continue; + + port = am65_ndev_to_port(sl_ndev); + slave = am65_ndev_to_slave(sl_ndev); + slave->port_vlan = cpsw->default_vlan; + + if (netif_running(sl_ndev)) + am65_cpsw_init_port_switch_ale(port); + } + + } else { + dev_info(cpsw->dev, "disable switch mode "); + + am65_cpsw_init_host_port_emac(cpsw); + + for (i = 0; i < cpsw->port_num; i++) { + struct net_device *sl_ndev = cpsw->ports[i].ndev; + struct am65_cpsw_port *port; + + if (!sl_ndev) + continue; + + port = am65_ndev_to_port(sl_ndev); + port->slave.port_vlan = 0; + if (netif_running(sl_ndev)) + am65_cpsw_init_port_emac_ale(port); + } + } + cpsw_ale_control_set(cpsw->ale, host_port_num, ale_bypass, 0); +exit: + rtnl_unlock(); + + return 0; +} + +static const struct devlink_param am65_cpsw_devlink_params[] = { + devlink_param_driver(am65_cpsw_dl_param_switch_mode, "switch_mode", + devlink_param_type_bool, + bit(devlink_param_cmode_runtime), + am65_cpsw_dl_switch_mode_get, + am65_cpsw_dl_switch_mode_set, null), +}; + +static void am65_cpsw_unregister_devlink_ports(struct am65_cpsw_common *common) +{ + struct devlink_port *dl_port; + struct am65_cpsw_port *port; + int i; + + for (i = 1; i <= common->port_num; i++) { + port = am65_common_get_port(common, i); + dl_port = &port->devlink_port; + + if (dl_port->registered) + devlink_port_unregister(dl_port); + } +} + +static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) +{ + struct devlink_port_attrs attrs = {}; + struct am65_cpsw_devlink *dl_priv; + struct device *dev = common->dev; + struct devlink_port *dl_port; + struct am65_cpsw_port *port; + int ret = 0; + int i; + + common->devlink = + devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv)); + if (!common->devlink) + return -enomem; + + dl_priv = devlink_priv(common->devlink); + dl_priv->common = common; + + ret = devlink_register(common->devlink, dev); + if (ret) { + dev_err(dev, "devlink reg fail ret:%d ", ret); + goto dl_free; + } + + /* provide devlink hook to switch mode when multiple external ports + * are present nuss switchdev driver is enabled. + */ + if (!am65_cpsw_is_cpsw2g(common) && + is_enabled(config_ti_k3_am65_cpsw_switchdev)) { + ret = devlink_params_register(common->devlink, + am65_cpsw_devlink_params, + array_size(am65_cpsw_devlink_params)); + if (ret) { + dev_err(dev, "devlink params reg fail ret:%d ", ret); + goto dl_unreg; + } + devlink_params_publish(common->devlink); + } + + for (i = 1; i <= common->port_num; i++) { + port = am65_common_get_port(common, i); + dl_port = &port->devlink_port; + + attrs.flavour = devlink_port_flavour_physical; + attrs.phys.port_number = port->port_id; + attrs.switch_id.id_len = sizeof(resource_size_t); + memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); + devlink_port_attrs_set(dl_port, &attrs); + + ret = devlink_port_register(common->devlink, dl_port, port->port_id); + if (ret) { + dev_err(dev, "devlink_port reg fail for port %d, ret:%d ", + port->port_id, ret); + goto dl_port_unreg; + } + devlink_port_type_eth_set(dl_port, port->ndev); + } + + return ret; + +dl_port_unreg: + am65_cpsw_unregister_devlink_ports(common); +dl_unreg: + devlink_unregister(common->devlink); +dl_free: + devlink_free(common->devlink); + + return ret; +} + +static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) +{ + if (!am65_cpsw_is_cpsw2g(common) && + is_enabled(config_ti_k3_am65_cpsw_switchdev)) { + devlink_params_unpublish(common->devlink); + devlink_params_unregister(common->devlink, am65_cpsw_devlink_params, + array_size(am65_cpsw_devlink_params)); + } + + am65_cpsw_unregister_devlink_ports(common); + devlink_unregister(common->devlink); + devlink_free(common->devlink); +} + + ret = am65_cpsw_nuss_register_devlink(common); + if (ret) + goto err_cleanup_ndev; - return 0; + return 0; + u64 id_temp; + /* use device's physical base address as switch id */ + id_temp = cpu_to_be64(res->start); + memcpy(common->switch_id, &id_temp, sizeof(res->start)); + common->default_vlan = 1; + common->is_emac_mode = true; + + am65_cpsw_unregister_devlink(common); + diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h +#include <linux/if_ether.h> +#include <net/devlink.h> +#define am65_cpsw_port_vlan_reg_offset 0x014 + + int port_vlan; + struct devlink_port devlink_port; +enum cpsw_devlink_param_id { + am65_cpsw_devlink_param_id_base = devlink_param_generic_id_max, + am65_cpsw_dl_param_switch_mode, +}; + +struct am65_cpsw_devlink { + struct am65_cpsw_common *common; +}; + + + bool is_emac_mode; + u16 br_members; + int default_vlan; + struct devlink *devlink; + unsigned char switch_id[max_phys_item_id_len]; + bool offload_fwd_mark;
|
Networking
|
58356eb31d60dd8994e5067096ef1a09e4d9ceda
|
vignesh raghavendra
|
documentation
|
networking
|
devlink, ethernet, ti
|
net: ti: am65-cpsw-nuss: add netdevice notifiers
|
register netdevice notifiers in order to receive notification when individual mac ports are added to the hw bridge.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add switchdev support for am65 cpsw nuss driver to support multi port cpsw present on j721e and am64 socs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ti']
|
['h', 'c']
| 2
| 133
| 1
|
--- diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c +static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) +{ + int set_val = 0; + int i; + + if (common->br_members == (genmask(common->port_num, 1) & ~common->disabled_ports_mask)) + set_val = 1; + + dev_dbg(common->dev, "set offload_fwd_mark %d ", set_val); + + for (i = 1; i <= common->port_num; i++) { + struct am65_cpsw_port *port = am65_common_get_port(common, i); + struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(port->ndev); + + priv->offload_fwd_mark = set_val; + } +} + +bool am65_cpsw_port_dev_check(const struct net_device *ndev) +{ + if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { + struct am65_cpsw_common *common = am65_ndev_to_common(ndev); + + return !common->is_emac_mode; + } + + return false; +} + +static int am65_cpsw_netdevice_port_link(struct net_device *ndev, struct net_device *br_ndev) +{ + struct am65_cpsw_common *common = am65_ndev_to_common(ndev); + struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); + + if (!common->br_members) { + common->hw_bridge_dev = br_ndev; + } else { + /* this is adding the port to a second bridge, this is + * unsupported + */ + if (common->hw_bridge_dev != br_ndev) + return -eopnotsupp; + } + + common->br_members |= bit(priv->port->port_id); + + am65_cpsw_port_offload_fwd_mark_update(common); + + return notify_done; +} + +static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) +{ + struct am65_cpsw_common *common = am65_ndev_to_common(ndev); + struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); + + common->br_members &= ~bit(priv->port->port_id); + + am65_cpsw_port_offload_fwd_mark_update(common); + + if (!common->br_members) + common->hw_bridge_dev = null; +} + +/* netdev notifier */ +static int am65_cpsw_netdevice_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *ndev = netdev_notifier_info_to_dev(ptr); + struct netdev_notifier_changeupper_info *info; + int ret = notify_done; + + if (!am65_cpsw_port_dev_check(ndev)) + return notify_done; + + switch (event) { + case netdev_changeupper: + info = ptr; + + if (netif_is_bridge_master(info->upper_dev)) { + if (info->linking) + ret = am65_cpsw_netdevice_port_link(ndev, info->upper_dev); + else + am65_cpsw_netdevice_port_unlink(ndev); + } + break; + default: + return notify_done; + } + + return notifier_from_errno(ret); +} + +static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) +{ + int ret = 0; + + if (am65_cpsw_is_cpsw2g(cpsw) || + !is_reachable(config_ti_k3_am65_cpsw_switchdev)) + return 0; + + cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; + ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); + if (ret) { + dev_err(cpsw->dev, "can't register netdevice notifier "); + return ret; + } + + return ret; +} + +static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) +{ + if (am65_cpsw_is_cpsw2g(cpsw) || + !is_reachable(config_ti_k3_am65_cpsw_switchdev)) + return; + + unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); +} + - ret = am65_cpsw_nuss_register_devlink(common); + ret = am65_cpsw_register_notifiers(common); + ret = am65_cpsw_nuss_register_devlink(common); + if (ret) + goto clean_unregister_notifiers; + +clean_unregister_notifiers: + am65_cpsw_unregister_notifiers(common); + + am65_cpsw_unregister_notifiers(common); diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.h b/drivers/net/ethernet/ti/am65-cpsw-nuss.h --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.h +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.h + struct net_device *hw_bridge_dev; + struct notifier_block am65_cpsw_netdevice_nb; +bool am65_cpsw_port_dev_check(const struct net_device *dev); +
|
Networking
|
2934db9bcb300ee1df5cfe9a1134e6e1f6a81906
|
vignesh raghavendra
|
drivers
|
net
|
ethernet, ti
|
net: ti: am65-cpsw-nuss: add switchdev support
|
j721e, j7200 and am64 have multi port switches which can work in multi mac mode and in switch mode. add support for configuring this hw in switch mode using devlink and switchdev notifiers.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add switchdev support for am65 cpsw nuss driver to support multi port cpsw present on j721e and am64 socs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ti']
|
['h', 'c', 'makefile']
| 4
| 587
| 1
|
- switchdev_attr_id_port_pre_bridge_flags - switchdev_attr_id_port_bridge_flags - switchdev_attr_id_port_stp_state - switchdev_obj_id_port_vlan - switchdev_obj_id_port_mdb - switchdev_obj_id_host_mdb - fdb offloading - mdb offloading - vlan filtering and offloading - stp --- diff --git a/drivers/net/ethernet/ti/makefile b/drivers/net/ethernet/ti/makefile --- a/drivers/net/ethernet/ti/makefile +++ b/drivers/net/ethernet/ti/makefile +ti-am65-cpsw-nuss-$(config_ti_k3_am65_cpsw_switchdev) += am65-cpsw-switchdev.o diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c +#include "am65-cpsw-switchdev.h" + if (!common->is_emac_mode) + return 0; + + if (!common->is_emac_mode) + return 0; + + if (promisc && !common->is_emac_mode) { + dev_dbg(common->dev, "promisc mode requested in switch mode"); + return; + } + + ndev_priv = netdev_priv(ndev); + am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); - ndev_priv = netdev_priv(ndev); + ret = am65_cpsw_switchdev_register_notifiers(cpsw); + if (ret) + unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); + + am65_cpsw_switchdev_unregister_notifiers(cpsw); diff --git a/drivers/net/ethernet/ti/am65-cpsw-switchdev.c b/drivers/net/ethernet/ti/am65-cpsw-switchdev.c --- /dev/null +++ b/drivers/net/ethernet/ti/am65-cpsw-switchdev.c +/* spdx-license-identifier: gpl-2.0 */ +/* texas instruments k3 am65 ethernet switchdev driver + * + * copyright (c) 2020 texas instruments incorporated - https://www.ti.com/ + * + */ + +#include <linux/etherdevice.h> +#include <linux/if_bridge.h> +#include <linux/netdevice.h> +#include <linux/workqueue.h> +#include <net/switchdev.h> + +#include "am65-cpsw-nuss.h" +#include "am65-cpsw-switchdev.h" +#include "cpsw_ale.h" + +struct am65_cpsw_switchdev_event_work { + struct work_struct work; + struct switchdev_notifier_fdb_info fdb_info; + struct am65_cpsw_port *port; + unsigned long event; +}; + +static int am65_cpsw_port_stp_state_set(struct am65_cpsw_port *port, u8 state) +{ + struct am65_cpsw_common *cpsw = port->common; + u8 cpsw_state; + int ret = 0; + + switch (state) { + case br_state_forwarding: + cpsw_state = ale_port_state_forward; + break; + case br_state_learning: + cpsw_state = ale_port_state_learn; + break; + case br_state_disabled: + cpsw_state = ale_port_state_disable; + break; + case br_state_listening: + case br_state_blocking: + cpsw_state = ale_port_state_block; + break; + default: + return -eopnotsupp; + } + + ret = cpsw_ale_control_set(cpsw->ale, port->port_id, + ale_port_state, cpsw_state); + netdev_dbg(port->ndev, "ale state: %u ", cpsw_state); + + return ret; +} + +static int am65_cpsw_port_attr_br_flags_set(struct am65_cpsw_port *port, + struct net_device *orig_dev, + unsigned long brport_flags) +{ + struct am65_cpsw_common *cpsw = port->common; + bool unreg_mcast_add = false; + + if (brport_flags & br_mcast_flood) + unreg_mcast_add = true; + netdev_dbg(port->ndev, "br_mcast_flood: %d port %u ", + unreg_mcast_add, port->port_id); + + cpsw_ale_set_unreg_mcast(cpsw->ale, bit(port->port_id), + unreg_mcast_add); + + return 0; +} + +static int am65_cpsw_port_attr_br_flags_pre_set(struct net_device *netdev, + unsigned long flags) +{ + if (flags & ~(br_learning | br_mcast_flood)) + return -einval; + + return 0; +} + +static int am65_cpsw_port_attr_set(struct net_device *ndev, + const struct switchdev_attr *attr) +{ + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + int ret; + + netdev_dbg(ndev, "attr: id %u port: %u ", attr->id, port->port_id); + + switch (attr->id) { + case switchdev_attr_id_port_pre_bridge_flags: + ret = am65_cpsw_port_attr_br_flags_pre_set(ndev, + attr->u.brport_flags); + break; + case switchdev_attr_id_port_stp_state: + ret = am65_cpsw_port_stp_state_set(port, attr->u.stp_state); + netdev_dbg(ndev, "stp state: %u ", attr->u.stp_state); + break; + case switchdev_attr_id_port_bridge_flags: + ret = am65_cpsw_port_attr_br_flags_set(port, attr->orig_dev, + attr->u.brport_flags); + break; + default: + ret = -eopnotsupp; + break; + } + + return ret; +} + +static u16 am65_cpsw_get_pvid(struct am65_cpsw_port *port) +{ + struct am65_cpsw_common *cpsw = port->common; + struct am65_cpsw_host *host_p = am65_common_get_host(cpsw); + u32 pvid; + + if (port->port_id) + pvid = readl(port->port_base + am65_cpsw_port_vlan_reg_offset); + else + pvid = readl(host_p->port_base + am65_cpsw_port_vlan_reg_offset); + + pvid = pvid & 0xfff; + + return pvid; +} + +static void am65_cpsw_set_pvid(struct am65_cpsw_port *port, u16 vid, bool cfi, u32 cos) +{ + struct am65_cpsw_common *cpsw = port->common; + struct am65_cpsw_host *host_p = am65_common_get_host(cpsw); + u32 pvid; + + pvid = vid; + pvid |= cfi ? bit(12) : 0; + pvid |= (cos & 0x7) << 13; + + if (port->port_id) + writel(pvid, port->port_base + am65_cpsw_port_vlan_reg_offset); + else + writel(pvid, host_p->port_base + am65_cpsw_port_vlan_reg_offset); +} + +static int am65_cpsw_port_vlan_add(struct am65_cpsw_port *port, bool untag, bool pvid, + u16 vid, struct net_device *orig_dev) +{ + bool cpu_port = netif_is_bridge_master(orig_dev); + struct am65_cpsw_common *cpsw = port->common; + int unreg_mcast_mask = 0; + int reg_mcast_mask = 0; + int untag_mask = 0; + int port_mask; + int ret = 0; + u32 flags; + + if (cpu_port) { + port_mask = bit(host_port_num); + flags = orig_dev->flags; + unreg_mcast_mask = port_mask; + } else { + port_mask = bit(port->port_id); + flags = port->ndev->flags; + } + + if (flags & iff_multicast) + reg_mcast_mask = port_mask; + + if (untag) + untag_mask = port_mask; + + ret = cpsw_ale_vlan_add_modify(cpsw->ale, vid, port_mask, untag_mask, + reg_mcast_mask, unreg_mcast_mask); + if (ret) { + netdev_err(port->ndev, "unable to add vlan "); + return ret; + } + + if (cpu_port) + cpsw_ale_add_ucast(cpsw->ale, port->slave.mac_addr, + host_port_num, ale_vlan | ale_secure, vid); + if (!pvid) + return ret; + + am65_cpsw_set_pvid(port, vid, 0, 0); + + netdev_dbg(port->ndev, "vid add: %s: vid:%u ports:%x ", + port->ndev->name, vid, port_mask); + + return ret; +} + +static int am65_cpsw_port_vlan_del(struct am65_cpsw_port *port, u16 vid, + struct net_device *orig_dev) +{ + bool cpu_port = netif_is_bridge_master(orig_dev); + struct am65_cpsw_common *cpsw = port->common; + int port_mask; + int ret = 0; + + if (cpu_port) + port_mask = bit(host_port_num); + else + port_mask = bit(port->port_id); + + ret = cpsw_ale_del_vlan(cpsw->ale, vid, port_mask); + if (ret != 0) + return ret; + + /* we don't care for the return value here, error is returned only if + * the unicast entry is not present + */ + if (cpu_port) + cpsw_ale_del_ucast(cpsw->ale, port->slave.mac_addr, + host_port_num, ale_vlan, vid); + + if (vid == am65_cpsw_get_pvid(port)) + am65_cpsw_set_pvid(port, 0, 0, 0); + + /* we don't care for the return value here, error is returned only if + * the multicast entry is not present + */ + cpsw_ale_del_mcast(cpsw->ale, port->ndev->broadcast, port_mask, + ale_vlan, vid); + netdev_dbg(port->ndev, "vid del: %s: vid:%u ports:%x ", + port->ndev->name, vid, port_mask); + + return ret; +} + +static int am65_cpsw_port_vlans_add(struct am65_cpsw_port *port, + const struct switchdev_obj_port_vlan *vlan) +{ + bool untag = vlan->flags & bridge_vlan_info_untagged; + struct net_device *orig_dev = vlan->obj.orig_dev; + bool cpu_port = netif_is_bridge_master(orig_dev); + bool pvid = vlan->flags & bridge_vlan_info_pvid; + + netdev_dbg(port->ndev, "vid add: %s: vid:%u flags:%x ", + port->ndev->name, vlan->vid, vlan->flags); + + if (cpu_port && !(vlan->flags & bridge_vlan_info_brentry)) + return 0; + + return am65_cpsw_port_vlan_add(port, untag, pvid, vlan->vid, orig_dev); +} + +static int am65_cpsw_port_vlans_del(struct am65_cpsw_port *port, + const struct switchdev_obj_port_vlan *vlan) + +{ + return am65_cpsw_port_vlan_del(port, vlan->vid, vlan->obj.orig_dev); +} + +static int am65_cpsw_port_mdb_add(struct am65_cpsw_port *port, + struct switchdev_obj_port_mdb *mdb) + +{ + struct net_device *orig_dev = mdb->obj.orig_dev; + bool cpu_port = netif_is_bridge_master(orig_dev); + struct am65_cpsw_common *cpsw = port->common; + int port_mask; + int err; + + if (cpu_port) + port_mask = bit(host_port_num); + else + port_mask = bit(port->port_id); + + err = cpsw_ale_add_mcast(cpsw->ale, mdb->addr, port_mask, + ale_vlan, mdb->vid, 0); + netdev_dbg(port->ndev, "mdb add: %s: vid %u:%pm ports: %x ", + port->ndev->name, mdb->vid, mdb->addr, port_mask); + + return err; +} + +static int am65_cpsw_port_mdb_del(struct am65_cpsw_port *port, + struct switchdev_obj_port_mdb *mdb) + +{ + struct net_device *orig_dev = mdb->obj.orig_dev; + bool cpu_port = netif_is_bridge_master(orig_dev); + struct am65_cpsw_common *cpsw = port->common; + int del_mask; + + if (cpu_port) + del_mask = bit(host_port_num); + else + del_mask = bit(port->port_id); + + /* ignore error as error code is returned only when entry is already removed */ + cpsw_ale_del_mcast(cpsw->ale, mdb->addr, del_mask, + ale_vlan, mdb->vid); + netdev_dbg(port->ndev, "mdb del: %s: vid %u:%pm ports: %x ", + port->ndev->name, mdb->vid, mdb->addr, del_mask); + + return 0; +} + +static int am65_cpsw_port_obj_add(struct net_device *ndev, + const struct switchdev_obj *obj, + struct netlink_ext_ack *extack) +{ + struct switchdev_obj_port_vlan *vlan = switchdev_obj_port_vlan(obj); + struct switchdev_obj_port_mdb *mdb = switchdev_obj_port_mdb(obj); + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + int err = 0; + + netdev_dbg(ndev, "obj_add: id %u port: %u ", obj->id, port->port_id); + + switch (obj->id) { + case switchdev_obj_id_port_vlan: + err = am65_cpsw_port_vlans_add(port, vlan); + break; + case switchdev_obj_id_port_mdb: + case switchdev_obj_id_host_mdb: + err = am65_cpsw_port_mdb_add(port, mdb); + break; + default: + err = -eopnotsupp; + break; + } + + return err; +} + +static int am65_cpsw_port_obj_del(struct net_device *ndev, + const struct switchdev_obj *obj) +{ + struct switchdev_obj_port_vlan *vlan = switchdev_obj_port_vlan(obj); + struct switchdev_obj_port_mdb *mdb = switchdev_obj_port_mdb(obj); + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + int err = 0; + + netdev_dbg(ndev, "obj_del: id %u port: %u ", obj->id, port->port_id); + + switch (obj->id) { + case switchdev_obj_id_port_vlan: + err = am65_cpsw_port_vlans_del(port, vlan); + break; + case switchdev_obj_id_port_mdb: + case switchdev_obj_id_host_mdb: + err = am65_cpsw_port_mdb_del(port, mdb); + break; + default: + err = -eopnotsupp; + break; + } + + return err; +} + +static void am65_cpsw_fdb_offload_notify(struct net_device *ndev, + struct switchdev_notifier_fdb_info *rcv) +{ + struct switchdev_notifier_fdb_info info; + + info.addr = rcv->addr; + info.vid = rcv->vid; + info.offloaded = true; + call_switchdev_notifiers(switchdev_fdb_offloaded, + ndev, &info.info, null); +} + +static void am65_cpsw_switchdev_event_work(struct work_struct *work) +{ + struct am65_cpsw_switchdev_event_work *switchdev_work = + container_of(work, struct am65_cpsw_switchdev_event_work, work); + struct am65_cpsw_port *port = switchdev_work->port; + struct switchdev_notifier_fdb_info *fdb; + struct am65_cpsw_common *cpsw = port->common; + int port_id = port->port_id; + + rtnl_lock(); + switch (switchdev_work->event) { + case switchdev_fdb_add_to_device: + fdb = &switchdev_work->fdb_info; + + netdev_dbg(port->ndev, "cpsw_fdb_add: macid = %pm vid = %u flags = %u %u -- port %d ", + fdb->addr, fdb->vid, fdb->added_by_user, + fdb->offloaded, port_id); + + if (!fdb->added_by_user) + break; + if (memcmp(port->slave.mac_addr, (u8 *)fdb->addr, eth_alen) == 0) + port_id = host_port_num; + + cpsw_ale_add_ucast(cpsw->ale, (u8 *)fdb->addr, port_id, + fdb->vid ? ale_vlan : 0, fdb->vid); + am65_cpsw_fdb_offload_notify(port->ndev, fdb); + break; + case switchdev_fdb_del_to_device: + fdb = &switchdev_work->fdb_info; + + netdev_dbg(port->ndev, "cpsw_fdb_del: macid = %pm vid = %u flags = %u %u -- port %d ", + fdb->addr, fdb->vid, fdb->added_by_user, + fdb->offloaded, port_id); + + if (!fdb->added_by_user) + break; + if (memcmp(port->slave.mac_addr, (u8 *)fdb->addr, eth_alen) == 0) + port_id = host_port_num; + + cpsw_ale_del_ucast(cpsw->ale, (u8 *)fdb->addr, port_id, + fdb->vid ? ale_vlan : 0, fdb->vid); + break; + default: + break; + } + rtnl_unlock(); + + kfree(switchdev_work->fdb_info.addr); + kfree(switchdev_work); + dev_put(port->ndev); +} + +/* called under rcu_read_lock() */ +static int am65_cpsw_switchdev_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *ndev = switchdev_notifier_info_to_dev(ptr); + struct am65_cpsw_switchdev_event_work *switchdev_work; + struct am65_cpsw_port *port = am65_ndev_to_port(ndev); + struct switchdev_notifier_fdb_info *fdb_info = ptr; + int err; + + if (event == switchdev_port_attr_set) { + err = switchdev_handle_port_attr_set(ndev, ptr, + am65_cpsw_port_dev_check, + am65_cpsw_port_attr_set); + return notifier_from_errno(err); + } + + if (!am65_cpsw_port_dev_check(ndev)) + return notify_done; + + switchdev_work = kzalloc(sizeof(*switchdev_work), gfp_atomic); + if (warn_on(!switchdev_work)) + return notify_bad; + + init_work(&switchdev_work->work, am65_cpsw_switchdev_event_work); + switchdev_work->port = port; + switchdev_work->event = event; + + switch (event) { + case switchdev_fdb_add_to_device: + case switchdev_fdb_del_to_device: + memcpy(&switchdev_work->fdb_info, ptr, + sizeof(switchdev_work->fdb_info)); + switchdev_work->fdb_info.addr = kzalloc(eth_alen, gfp_atomic); + if (!switchdev_work->fdb_info.addr) + goto err_addr_alloc; + ether_addr_copy((u8 *)switchdev_work->fdb_info.addr, + fdb_info->addr); + dev_hold(ndev); + break; + default: + kfree(switchdev_work); + return notify_done; + } + + queue_work(system_long_wq, &switchdev_work->work); + + return notify_done; + +err_addr_alloc: + kfree(switchdev_work); + return notify_bad; +} + +static struct notifier_block cpsw_switchdev_notifier = { + .notifier_call = am65_cpsw_switchdev_event, +}; + +static int am65_cpsw_switchdev_blocking_event(struct notifier_block *unused, + unsigned long event, void *ptr) +{ + struct net_device *dev = switchdev_notifier_info_to_dev(ptr); + int err; + + switch (event) { + case switchdev_port_obj_add: + err = switchdev_handle_port_obj_add(dev, ptr, + am65_cpsw_port_dev_check, + am65_cpsw_port_obj_add); + return notifier_from_errno(err); + case switchdev_port_obj_del: + err = switchdev_handle_port_obj_del(dev, ptr, + am65_cpsw_port_dev_check, + am65_cpsw_port_obj_del); + return notifier_from_errno(err); + case switchdev_port_attr_set: + err = switchdev_handle_port_attr_set(dev, ptr, + am65_cpsw_port_dev_check, + am65_cpsw_port_attr_set); + return notifier_from_errno(err); + default: + break; + } + + return notify_done; +} + +static struct notifier_block cpsw_switchdev_bl_notifier = { + .notifier_call = am65_cpsw_switchdev_blocking_event, +}; + +int am65_cpsw_switchdev_register_notifiers(struct am65_cpsw_common *cpsw) +{ + int ret = 0; + + ret = register_switchdev_notifier(&cpsw_switchdev_notifier); + if (ret) { + dev_err(cpsw->dev, "register switchdev notifier fail ret:%d ", + ret); + return ret; + } + + ret = register_switchdev_blocking_notifier(&cpsw_switchdev_bl_notifier); + if (ret) { + dev_err(cpsw->dev, "register switchdev blocking notifier ret:%d ", + ret); + unregister_switchdev_notifier(&cpsw_switchdev_notifier); + } + + return ret; +} + +void am65_cpsw_switchdev_unregister_notifiers(struct am65_cpsw_common *cpsw) +{ + unregister_switchdev_blocking_notifier(&cpsw_switchdev_bl_notifier); + unregister_switchdev_notifier(&cpsw_switchdev_notifier); +} diff --git a/drivers/net/ethernet/ti/am65-cpsw-switchdev.h b/drivers/net/ethernet/ti/am65-cpsw-switchdev.h --- /dev/null +++ b/drivers/net/ethernet/ti/am65-cpsw-switchdev.h +/* spdx-license-identifier: gpl-2.0 */ +/* copyright (c) 2020 texas instruments incorporated - https://www.ti.com/ + */ + +#ifndef drivers_net_ethernet_ti_am65_cpsw_switchdev_h_ +#define drivers_net_ethernet_ti_am65_cpsw_switchdev_h_ + +#include <linux/skbuff.h> + +#if is_enabled(config_ti_k3_am65_cpsw_switchdev) +static inline void am65_cpsw_nuss_set_offload_fwd_mark(struct sk_buff *skb, bool val) +{ + skb->offload_fwd_mark = val; +} + +int am65_cpsw_switchdev_register_notifiers(struct am65_cpsw_common *cpsw); +void am65_cpsw_switchdev_unregister_notifiers(struct am65_cpsw_common *cpsw); +#else +static inline int am65_cpsw_switchdev_register_notifiers(struct am65_cpsw_common *cpsw) +{ + return -eopnotsupp; +} + +static inline void am65_cpsw_switchdev_unregister_notifiers(struct am65_cpsw_common *cpsw) +{ +} + +static inline void am65_cpsw_nuss_set_offload_fwd_mark(struct sk_buff *skb, bool val) +{ +} + +#endif + +#endif /* drivers_net_ethernet_ti_am65_cpsw_switchdev_h_ */
|
Networking
|
86e8b070b25e3cb459d0a4e293327a56f344515e
|
vignesh raghavendra
|
drivers
|
net
|
ethernet, ti
|
docs: networking: ti: add driver doc for am65 nuss switch driver
|
j721e, j7200 and am64 have multi port switches which can work in multi mac mode and in switch mode. add documentation explaining how to use different modes.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add switchdev support for am65 cpsw nuss driver to support multi port cpsw present on j721e and am64 socs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ti']
|
['rst']
| 2
| 144
| 0
|
--- diff --git a/documentation/networking/device_drivers/ethernet/index.rst b/documentation/networking/device_drivers/ethernet/index.rst --- a/documentation/networking/device_drivers/ethernet/index.rst +++ b/documentation/networking/device_drivers/ethernet/index.rst + ti/am65_nuss_cpsw_switchdev diff --git a/documentation/networking/device_drivers/ethernet/ti/am65_nuss_cpsw_switchdev.rst b/documentation/networking/device_drivers/ethernet/ti/am65_nuss_cpsw_switchdev.rst --- /dev/null +++ b/documentation/networking/device_drivers/ethernet/ti/am65_nuss_cpsw_switchdev.rst +.. spdx-license-identifier: gpl-2.0 + +=================================================================== +texas instruments k3 am65 cpsw nuss switchdev based ethernet driver +=================================================================== + +:version: 1.0 + +port renaming +============= + +in order to rename via udev:: + + ip -d link show dev sw0p1 | grep switchid + + subsystem=="net", action=="add", attr{phys_switch_id}==<switchid>, \ + attr{phys_port_name}!="", name="sw0$attr{phys_port_name}" + + +multi mac mode +============== + +- the driver is operating in multi-mac mode by default, thus + working as n individual network interfaces. + +devlink configuration parameters +================================ + +see documentation/networking/devlink/am65-nuss-cpsw-switch.rst + +enabling "switch" +================= + +the switch mode can be enabled by configuring devlink driver parameter +"switch_mode" to 1/true:: + + devlink dev param set platform/c000000.ethernet \ + name switch_mode value true cmode runtime + +this can be done regardless of the state of port's netdev devices - up/down, but +port's netdev devices have to be in up before joining to the bridge to avoid +overwriting of bridge configuration as cpsw switch driver completely reloads its +configuration when first port changes its state to up. + +when the both interfaces joined the bridge - cpsw switch driver will enable +marking packets with offload_fwd_mark flag. + +all configuration is implemented via switchdev api. + +bridge setup +============ + +:: + + devlink dev param set platform/c000000.ethernet \ + name switch_mode value true cmode runtime + + ip link add name br0 type bridge + ip link set dev br0 type bridge ageing_time 1000 + ip link set dev sw0p1 up + ip link set dev sw0p2 up + ip link set dev sw0p1 master br0 + ip link set dev sw0p2 master br0 + + [*] bridge vlan add dev br0 vid 1 pvid untagged self + + [*] if vlan_filtering=1. where default_pvid=1 + + note. steps [*] are mandatory. + + +on/off stp +========== + +:: + + ip link set dev brdev type bridge stp_state 1/0 + +vlan configuration +================== + +:: + + bridge vlan add dev br0 vid 1 pvid untagged self <---- add cpu port to vlan 1 + +note. this step is mandatory for bridge/default_pvid. + +add extra vlans +=============== + + 1. untagged:: + + bridge vlan add dev sw0p1 vid 100 pvid untagged master + bridge vlan add dev sw0p2 vid 100 pvid untagged master + bridge vlan add dev br0 vid 100 pvid untagged self <---- add cpu port to vlan100 + + 2. tagged:: + + bridge vlan add dev sw0p1 vid 100 master + bridge vlan add dev sw0p2 vid 100 master + bridge vlan add dev br0 vid 100 pvid tagged self <---- add cpu port to vlan100 + +fdbs +---- + +fdbs are automatically added on the appropriate switch port upon detection + +manually adding fdbs:: + + bridge fdb add aa:bb:cc:dd:ee:ff dev sw0p1 master vlan 100 + bridge fdb add aa:bb:cc:dd:ee:fe dev sw0p2 master <---- add on all vlans + +mdbs +---- + +mdbs are automatically added on the appropriate switch port upon detection + +manually adding mdbs:: + + bridge mdb add dev br0 port sw0p1 grp 239.1.1.1 permanent vid 100 + bridge mdb add dev br0 port sw0p1 grp 239.1.1.1 permanent <---- add on all vlans + +multicast flooding +================== +cpu port mcast_flooding is always on + +turning flooding on/off on swithch ports: +bridge link set dev sw0p1 mcast_flood on/off + +access and trunk port +===================== + +:: + + bridge vlan add dev sw0p1 vid 100 pvid untagged master + bridge vlan add dev sw0p2 vid 100 master + + + bridge vlan add dev br0 vid 100 self + ip link add link br0 name br0.100 type vlan id 100 + +note. setting pvid on bridge device itself works only for +default vlan (default_pvid).
|
Networking
|
e276cfb9cd5bd68984a200e3f2d39484b9e87b47
|
vignesh raghavendra
|
documentation
|
networking
|
device_drivers, ethernet, ti
|
net: ti: cpsw_ale: add driver data for am64 cpsw3g
|
the am642x cpsw3g is similar to j721e-cpswxg except its ale table size is 512 entries. add entry for the same.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add driver data for am64 cpsw3g
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ti', 'cpsw_ale']
|
['c']
| 1
| 7
| 0
|
--- diff --git a/drivers/net/ethernet/ti/cpsw_ale.c b/drivers/net/ethernet/ti/cpsw_ale.c --- a/drivers/net/ethernet/ti/cpsw_ale.c +++ b/drivers/net/ethernet/ti/cpsw_ale.c + { + .dev_id = "am64-cpswxg", + .features = cpsw_ale_f_status_reg | cpsw_ale_f_hw_autoaging, + .major_ver_mask = 0x7, + .vlan_entry_tbl = vlan_entry_k3_cpswxg, + .tbl_entries = 512, + },
|
Networking
|
1dd3841033b3ad5a507b714d6db0cd401b3ca996
|
vignesh raghavendra
|
drivers
|
net
|
ethernet, ti
|
net: qmi_wwan: add pass through mode
|
pass through mode is to allow packets in map format to be passed on to the stack. rmnet driver can be used to process and demultiplex these packets.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add pass through mode
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qmi_wwan ', 'qmi_wwan']
|
['c']
| 1
| 58
| 0
|
--- diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c + qmi_wwan_flag_pass_through = 1 << 2, + /* ip mode cannot be cleared when pass through mode is set */ + if (!enable && (info->flags & qmi_wwan_flag_pass_through)) { + netdev_err(dev->net, + "cannot clear ip mode on pass through device "); + return -einval; + } + +static ssize_t pass_through_show(struct device *d, + struct device_attribute *attr, char *buf) +{ + struct usbnet *dev = netdev_priv(to_net_dev(d)); + struct qmi_wwan_state *info; + + info = (void *)&dev->data; + return sprintf(buf, "%c ", + info->flags & qmi_wwan_flag_pass_through ? 'y' : 'n'); +} + +static ssize_t pass_through_store(struct device *d, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct usbnet *dev = netdev_priv(to_net_dev(d)); + struct qmi_wwan_state *info; + bool enable; + + if (strtobool(buf, &enable)) + return -einval; + + info = (void *)&dev->data; + + /* no change? */ + if (enable == (info->flags & qmi_wwan_flag_pass_through)) + return len; + + /* pass through mode can be set for raw ip devices only */ + if (!(info->flags & qmi_wwan_flag_rawip)) { + netdev_err(dev->net, + "cannot set pass through mode on non ip device "); + return -einval; + } + + if (enable) + info->flags |= qmi_wwan_flag_pass_through; + else + info->flags &= ~qmi_wwan_flag_pass_through; + + return len; +} + +static device_attr_rw(pass_through); + &dev_attr_pass_through.attr, + if (info->flags & qmi_wwan_flag_pass_through) { + skb->protocol = htons(eth_p_map); + return (netif_rx(skb) == net_rx_success); + } +
|
Networking
|
59e139cf0b32a7a08ef20453927ecd57db086d8e
|
subash abhinov kasiviswanathan
|
drivers
|
net
|
usb
|
net: usb: qmi_wwan: add qmap id sysfs file for qmimux interfaces
|
add qmimux interface sysfs file qmap/mux_id to show qmap id set during the interface creation, in order to provide a method for userspace to associate qmi control channels to network interfaces.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qmap id sysfs file for qmimux interfaces
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qmi_wwan ']
|
['c']
| 1
| 24
| 0
|
--- diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c +static ssize_t mux_id_show(struct device *d, struct device_attribute *attr, char *buf) +{ + struct net_device *dev = to_net_dev(d); + struct qmimux_priv *priv; + + priv = netdev_priv(dev); + + return sysfs_emit(buf, "0x%02x ", priv->mux_id); +} + +static device_attr_ro(mux_id); + +static struct attribute *qmi_wwan_sysfs_qmimux_attrs[] = { + &dev_attr_mux_id.attr, + null, +}; + +static struct attribute_group qmi_wwan_sysfs_qmimux_attr_group = { + .name = "qmap", + .attrs = qmi_wwan_sysfs_qmimux_attrs, +}; + + new_dev->sysfs_groups[0] = &qmi_wwan_sysfs_qmimux_attr_group; +
|
Networking
|
e594ad980ec26fb7351d02c84abaa77ecdb4e522
|
daniele palmas bj rn mork bjorn mork no aleksander morgado aleksander aleksander es
|
drivers
|
net
|
usb
|
net: qmi_wwan: document qmap/mux_id sysfs file
|
document qmap/mux_id sysfs file showing qmimux interface id
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add qmap id sysfs file for qmimux interfaces
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qmi_wwan ']
|
['sysfs-class-net-qmi']
| 1
| 10
| 0
|
--- diff --git a/documentation/abi/testing/sysfs-class-net-qmi b/documentation/abi/testing/sysfs-class-net-qmi --- a/documentation/abi/testing/sysfs-class-net-qmi +++ b/documentation/abi/testing/sysfs-class-net-qmi + +what: /sys/class/net/<qmimux iface>/qmap/mux_id +date: january 2021 +kernelversion: 5.12 +contact: daniele palmas <dnlplm@gmail.com> +description: + unsigned integer + + indicates the mux id associated to the qmimux network interface + during its creation.
|
Networking
|
b4b91e24094ad54b3d176e3fd2997fae62a315dc
|
daniele palmas bj rn mork bjorn mork no
|
documentation
|
abi
|
testing
|
net: usb: qmi_wwan: support zte p685m modem
|
now that interface 3 in "option" driver is no longer mapped, add device id matching it to qmi_wwan.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support zte p685m modem
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['qmi_wwan ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c --- a/drivers/net/usb/qmi_wwan.c +++ b/drivers/net/usb/qmi_wwan.c + {qmi_fixed_intf(0x19d2, 0x1275, 3)}, /* zte p685m */
|
Networking
|
88eee9b7b42e69fb622ddb3ff6f37e8e4347f5b2
|
lech perczak
|
drivers
|
net
|
usb
|
wil6210: add support for extended dmg mcs 12.1
|
fw reports tx/rx extended mcs 12.1 to driver as "26". driver will convert this into base mcs 7 + extended_sc_dmg flag so kernel can do the correct phy rate conversion. also add log prints to print "12.1" instead of "26" for extended mcs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for extended dmg mcs 12.1
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['wil6210']
|
['h', 'c']
| 5
| 52
| 19
|
--- diff --git a/drivers/net/wireless/ath/wil6210/cfg80211.c b/drivers/net/wireless/ath/wil6210/cfg80211.c --- a/drivers/net/wireless/ath/wil6210/cfg80211.c +++ b/drivers/net/wireless/ath/wil6210/cfg80211.c - u8 txflag = rate_info_flags_dmg; + u8 tx_mcs, rx_mcs; + u8 tx_rate_flag = rate_info_flags_dmg; + u8 rx_rate_flag = rate_info_flags_dmg; + tx_mcs = le16_to_cpu(reply.evt.bf_mcs); + - " mcs %d tsf 0x%016llx " + " mcs %s tsf 0x%016llx " - cid, vif->mid, le16_to_cpu(reply.evt.bf_mcs), + cid, vif->mid, wil_extended_mcs_check(tx_mcs), - if (wil->use_enhanced_dma_hw && reply.evt.tx_mode != wmi_tx_mode_dmg) - txflag = rate_info_flags_edmg; + if (wil->use_enhanced_dma_hw && reply.evt.tx_mode != wmi_tx_mode_dmg) { + tx_rate_flag = rate_info_flags_edmg; + rx_rate_flag = rate_info_flags_edmg; + } + + rx_mcs = stats->last_mcs_rx; + + /* check extended mcs (12.1) and convert it into + * base mcs (7) + extended_sc_dmg flag + */ + if (tx_mcs == wil_extended_mcs_26) { + tx_rate_flag = rate_info_flags_extended_sc_dmg; + tx_mcs = wil_base_mcs_for_extended_26; + } + if (rx_mcs == wil_extended_mcs_26) { + rx_rate_flag = rate_info_flags_extended_sc_dmg; + rx_mcs = wil_base_mcs_for_extended_26; + } + + sinfo->txrate.flags = tx_rate_flag; + sinfo->rxrate.flags = rx_rate_flag; + sinfo->txrate.mcs = tx_mcs; + sinfo->rxrate.mcs = rx_mcs; - sinfo->txrate.flags = txflag; - sinfo->txrate.mcs = le16_to_cpu(reply.evt.bf_mcs); - sinfo->rxrate.mcs = stats->last_mcs_rx; diff --git a/drivers/net/wireless/ath/wil6210/debugfs.c b/drivers/net/wireless/ath/wil6210/debugfs.c --- a/drivers/net/wireless/ath/wil6210/debugfs.c +++ b/drivers/net/wireless/ath/wil6210/debugfs.c + u8 bf_mcs; + bf_mcs = le16_to_cpu(reply.evt.bf_mcs); - " txmcs = %2d txtpt = %4d " + " txmcs = %s txtpt = %4d " - le16_to_cpu(reply.evt.bf_mcs), + wil_extended_mcs_check(bf_mcs), - seq_printf(s, " tx_mcs = %d ", sinfo->txrate.mcs); - seq_printf(s, " rx_mcs = %d ", sinfo->rxrate.mcs); + seq_printf(s, " tx_mcs = %s ", + wil_extended_mcs_check(sinfo->txrate.mcs)); + seq_printf(s, " rx_mcs = %s ", + wil_extended_mcs_check(sinfo->rxrate.mcs)); - " txmcs %d txtpt %d " + " txmcs %s txtpt %d " - basic->bf_mcs, le32_to_cpu(basic->tx_tpt), + wil_extended_mcs_check(basic->bf_mcs), + le32_to_cpu(basic->tx_tpt), diff --git a/drivers/net/wireless/ath/wil6210/txrx_edma.c b/drivers/net/wireless/ath/wil6210/txrx_edma.c --- a/drivers/net/wireless/ath/wil6210/txrx_edma.c +++ b/drivers/net/wireless/ath/wil6210/txrx_edma.c + else if (stats->last_mcs_rx == wil_extended_mcs_26) + stats->rx_per_mcs[wil_base_mcs_for_extended_26]++; diff --git a/drivers/net/wireless/ath/wil6210/wil6210.h b/drivers/net/wireless/ath/wil6210/wil6210.h --- a/drivers/net/wireless/ath/wil6210/wil6210.h +++ b/drivers/net/wireless/ath/wil6210/wil6210.h +#define wil_extended_mcs_26 (26) /* fw reports mcs 12.1 to driver as "26" */ +#define wil_base_mcs_for_extended_26 (7) /* mcs 7 is base mcs for mcs 12.1 */ +#define wil_extended_mcs_check(x) (((x) == wil_extended_mcs_26) ? "12.1" : #x) diff --git a/drivers/net/wireless/ath/wil6210/wmi.c b/drivers/net/wireless/ath/wil6210/wmi.c --- a/drivers/net/wireless/ath/wil6210/wmi.c +++ b/drivers/net/wireless/ath/wil6210/wmi.c - wil_dbg_wmi(wil, "mgmt rx: channel %d mcs %d rssi %d sqi %d%% ", - data->info.channel, data->info.mcs, data->info.rssi, - data->info.sqi); + wil_dbg_wmi(wil, "mgmt rx: channel %d mcs %s rssi %d sqi %d%% ", + data->info.channel, wil_extended_mcs_check(data->info.mcs), + data->info.rssi, data->info.sqi); - wil_dbg_wmi(wil, "sched scan result: channel %d mcs %d rssi %d ", - data->info.channel, data->info.mcs, data->info.rssi); + wil_dbg_wmi(wil, "sched scan result: channel %d mcs %s rssi %d ", + data->info.channel, wil_extended_mcs_check(data->info.mcs), + data->info.rssi);
|
Networking
|
7064e2193cabcdb8faa9008744e6ceb7f86d314d
|
max chen
|
drivers
|
net
|
ath, wil6210, wireless
|
net: remove aurora nb8800 driver
|
the tango4 platform is getting removed, and this driver has no other known users, so it can be removed.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
remove aurora nb8800 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['h', 'kconfig', 'c', 'makefile']
| 6
| 0
| 1,863
|
--- diff --git a/drivers/net/ethernet/kconfig b/drivers/net/ethernet/kconfig --- a/drivers/net/ethernet/kconfig +++ b/drivers/net/ethernet/kconfig -source "drivers/net/ethernet/aurora/kconfig" diff --git a/drivers/net/ethernet/makefile b/drivers/net/ethernet/makefile --- a/drivers/net/ethernet/makefile +++ b/drivers/net/ethernet/makefile -obj-$(config_net_vendor_aurora) += aurora/ diff --git a/drivers/net/ethernet/aurora/kconfig b/drivers/net/ethernet/aurora/kconfig --- a/drivers/net/ethernet/aurora/kconfig +++ /dev/null -# spdx-license-identifier: gpl-2.0-only -config net_vendor_aurora - bool "aurora vlsi devices" - default y - help - if you have a network (ethernet) device belonging to this class, - say y. - - note that the answer to this question doesn't directly affect the - kernel: saying n will just cause the configurator to skip all - questions about aurora devices. if you say y, you will be asked - for your specific device in the following questions. - -if net_vendor_aurora - -config aurora_nb8800 - tristate "aurora au-nb8800 support" - depends on has_dma - select phylib - help - support for the au-nb8800 gigabit ethernet controller. - -endif diff --git a/drivers/net/ethernet/aurora/makefile b/drivers/net/ethernet/aurora/makefile --- a/drivers/net/ethernet/aurora/makefile +++ /dev/null -# spdx-license-identifier: gpl-2.0-only -obj-$(config_aurora_nb8800) += nb8800.o diff --git a/drivers/net/ethernet/aurora/nb8800.c b/drivers/net/ethernet/aurora/nb8800.c --- a/drivers/net/ethernet/aurora/nb8800.c +++ /dev/null -// spdx-license-identifier: gpl-2.0-or-later -/* - * copyright (c) 2015 mans rullgard <mans@mansr.com> - * - * mostly rewritten, based on driver from sigma designs. original - * copyright notice below. - * - * driver for tangox smp864x/smp865x/smp867x/smp868x builtin ethernet mac. - * - * copyright (c) 2005 maxime bizon <mbizon@freebox.fr> - */ - -#include <linux/module.h> -#include <linux/etherdevice.h> -#include <linux/delay.h> -#include <linux/ethtool.h> -#include <linux/interrupt.h> -#include <linux/platform_device.h> -#include <linux/of_device.h> -#include <linux/of_mdio.h> -#include <linux/of_net.h> -#include <linux/dma-mapping.h> -#include <linux/phy.h> -#include <linux/cache.h> -#include <linux/jiffies.h> -#include <linux/io.h> -#include <linux/iopoll.h> -#include <asm/barrier.h> - -#include "nb8800.h" - -static void nb8800_tx_done(struct net_device *dev); -static int nb8800_dma_stop(struct net_device *dev); - -static inline u8 nb8800_readb(struct nb8800_priv *priv, int reg) -{ - return readb_relaxed(priv->base + reg); -} - -static inline u32 nb8800_readl(struct nb8800_priv *priv, int reg) -{ - return readl_relaxed(priv->base + reg); -} - -static inline void nb8800_writeb(struct nb8800_priv *priv, int reg, u8 val) -{ - writeb_relaxed(val, priv->base + reg); -} - -static inline void nb8800_writew(struct nb8800_priv *priv, int reg, u16 val) -{ - writew_relaxed(val, priv->base + reg); -} - -static inline void nb8800_writel(struct nb8800_priv *priv, int reg, u32 val) -{ - writel_relaxed(val, priv->base + reg); -} - -static inline void nb8800_maskb(struct nb8800_priv *priv, int reg, - u32 mask, u32 val) -{ - u32 old = nb8800_readb(priv, reg); - u32 new = (old & ~mask) | (val & mask); - - if (new != old) - nb8800_writeb(priv, reg, new); -} - -static inline void nb8800_maskl(struct nb8800_priv *priv, int reg, - u32 mask, u32 val) -{ - u32 old = nb8800_readl(priv, reg); - u32 new = (old & ~mask) | (val & mask); - - if (new != old) - nb8800_writel(priv, reg, new); -} - -static inline void nb8800_modb(struct nb8800_priv *priv, int reg, u8 bits, - bool set) -{ - nb8800_maskb(priv, reg, bits, set ? bits : 0); -} - -static inline void nb8800_setb(struct nb8800_priv *priv, int reg, u8 bits) -{ - nb8800_maskb(priv, reg, bits, bits); -} - -static inline void nb8800_clearb(struct nb8800_priv *priv, int reg, u8 bits) -{ - nb8800_maskb(priv, reg, bits, 0); -} - -static inline void nb8800_modl(struct nb8800_priv *priv, int reg, u32 bits, - bool set) -{ - nb8800_maskl(priv, reg, bits, set ? bits : 0); -} - -static inline void nb8800_setl(struct nb8800_priv *priv, int reg, u32 bits) -{ - nb8800_maskl(priv, reg, bits, bits); -} - -static inline void nb8800_clearl(struct nb8800_priv *priv, int reg, u32 bits) -{ - nb8800_maskl(priv, reg, bits, 0); -} - -static int nb8800_mdio_wait(struct mii_bus *bus) -{ - struct nb8800_priv *priv = bus->priv; - u32 val; - - return readl_poll_timeout_atomic(priv->base + nb8800_mdio_cmd, - val, !(val & mdio_cmd_go), 1, 1000); -} - -static int nb8800_mdio_cmd(struct mii_bus *bus, u32 cmd) -{ - struct nb8800_priv *priv = bus->priv; - int err; - - err = nb8800_mdio_wait(bus); - if (err) - return err; - - nb8800_writel(priv, nb8800_mdio_cmd, cmd); - udelay(10); - nb8800_writel(priv, nb8800_mdio_cmd, cmd | mdio_cmd_go); - - return nb8800_mdio_wait(bus); -} - -static int nb8800_mdio_read(struct mii_bus *bus, int phy_id, int reg) -{ - struct nb8800_priv *priv = bus->priv; - u32 val; - int err; - - err = nb8800_mdio_cmd(bus, mdio_cmd_addr(phy_id) | mdio_cmd_reg(reg)); - if (err) - return err; - - val = nb8800_readl(priv, nb8800_mdio_sts); - if (val & mdio_sts_err) - return 0xffff; - - return val & 0xffff; -} - -static int nb8800_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) -{ - u32 cmd = mdio_cmd_addr(phy_id) | mdio_cmd_reg(reg) | - mdio_cmd_data(val) | mdio_cmd_wr; - - return nb8800_mdio_cmd(bus, cmd); -} - -static void nb8800_mac_tx(struct net_device *dev, bool enable) -{ - struct nb8800_priv *priv = netdev_priv(dev); - - while (nb8800_readl(priv, nb8800_txc_cr) & tcr_en) - cpu_relax(); - - nb8800_modb(priv, nb8800_tx_ctl1, tx_en, enable); -} - -static void nb8800_mac_rx(struct net_device *dev, bool enable) -{ - nb8800_modb(netdev_priv(dev), nb8800_rx_ctl, rx_en, enable); -} - -static void nb8800_mac_af(struct net_device *dev, bool enable) -{ - nb8800_modb(netdev_priv(dev), nb8800_rx_ctl, rx_af_en, enable); -} - -static void nb8800_start_rx(struct net_device *dev) -{ - nb8800_setl(netdev_priv(dev), nb8800_rxc_cr, rcr_en); -} - -static int nb8800_alloc_rx(struct net_device *dev, unsigned int i, bool napi) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_rx_desc *rxd = &priv->rx_descs[i]; - struct nb8800_rx_buf *rxb = &priv->rx_bufs[i]; - int size = l1_cache_align(rx_buf_size); - dma_addr_t dma_addr; - struct page *page; - unsigned long offset; - void *data; - - data = napi ? napi_alloc_frag(size) : netdev_alloc_frag(size); - if (!data) - return -enomem; - - page = virt_to_head_page(data); - offset = data - page_address(page); - - dma_addr = dma_map_page(&dev->dev, page, offset, rx_buf_size, - dma_from_device); - - if (dma_mapping_error(&dev->dev, dma_addr)) { - skb_free_frag(data); - return -enomem; - } - - rxb->page = page; - rxb->offset = offset; - rxd->desc.s_addr = dma_addr; - - return 0; -} - -static void nb8800_receive(struct net_device *dev, unsigned int i, - unsigned int len) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_rx_desc *rxd = &priv->rx_descs[i]; - struct page *page = priv->rx_bufs[i].page; - int offset = priv->rx_bufs[i].offset; - void *data = page_address(page) + offset; - dma_addr_t dma = rxd->desc.s_addr; - struct sk_buff *skb; - unsigned int size; - int err; - - size = len <= rx_copybreak ? len : rx_copyhdr; - - skb = napi_alloc_skb(&priv->napi, size); - if (!skb) { - netdev_err(dev, "rx skb allocation failed "); - dev->stats.rx_dropped++; - return; - } - - if (len <= rx_copybreak) { - dma_sync_single_for_cpu(&dev->dev, dma, len, dma_from_device); - skb_put_data(skb, data, len); - dma_sync_single_for_device(&dev->dev, dma, len, - dma_from_device); - } else { - err = nb8800_alloc_rx(dev, i, true); - if (err) { - netdev_err(dev, "rx buffer allocation failed "); - dev->stats.rx_dropped++; - dev_kfree_skb(skb); - return; - } - - dma_unmap_page(&dev->dev, dma, rx_buf_size, dma_from_device); - skb_put_data(skb, data, rx_copyhdr); - skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, - offset + rx_copyhdr, len - rx_copyhdr, - rx_buf_size); - } - - skb->protocol = eth_type_trans(skb, dev); - napi_gro_receive(&priv->napi, skb); -} - -static void nb8800_rx_error(struct net_device *dev, u32 report) -{ - if (report & rx_length_err) - dev->stats.rx_length_errors++; - - if (report & rx_fcs_err) - dev->stats.rx_crc_errors++; - - if (report & rx_fifo_overrun) - dev->stats.rx_fifo_errors++; - - if (report & rx_alignment_error) - dev->stats.rx_frame_errors++; - - dev->stats.rx_errors++; -} - -static int nb8800_poll(struct napi_struct *napi, int budget) -{ - struct net_device *dev = napi->dev; - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_rx_desc *rxd; - unsigned int last = priv->rx_eoc; - unsigned int next; - int work = 0; - - nb8800_tx_done(dev); - -again: - do { - unsigned int len; - - next = (last + 1) % rx_desc_count; - - rxd = &priv->rx_descs[next]; - - if (!rxd->report) - break; - - len = rx_bytes_transferred(rxd->report); - - if (is_rx_error(rxd->report)) - nb8800_rx_error(dev, rxd->report); - else - nb8800_receive(dev, next, len); - - dev->stats.rx_packets++; - dev->stats.rx_bytes += len; - - if (rxd->report & rx_multicast_pkt) - dev->stats.multicast++; - - rxd->report = 0; - last = next; - work++; - } while (work < budget); - - if (work) { - priv->rx_descs[last].desc.config |= desc_eoc; - wmb(); /* ensure new eoc is written before clearing old */ - priv->rx_descs[priv->rx_eoc].desc.config &= ~desc_eoc; - priv->rx_eoc = last; - nb8800_start_rx(dev); - } - - if (work < budget) { - nb8800_writel(priv, nb8800_rx_itr, priv->rx_itr_irq); - - /* if a packet arrived after we last checked but - * before writing rx_itr, the interrupt will be - * delayed, so we retrieve it now. - */ - if (priv->rx_descs[next].report) - goto again; - - napi_complete_done(napi, work); - } - - return work; -} - -static void __nb8800_tx_dma_start(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_tx_buf *txb; - u32 txc_cr; - - txb = &priv->tx_bufs[priv->tx_queue]; - if (!txb->ready) - return; - - txc_cr = nb8800_readl(priv, nb8800_txc_cr); - if (txc_cr & tcr_en) - return; - - nb8800_writel(priv, nb8800_tx_desc_addr, txb->dma_desc); - wmb(); /* ensure desc addr is written before starting dma */ - nb8800_writel(priv, nb8800_txc_cr, txc_cr | tcr_en); - - priv->tx_queue = (priv->tx_queue + txb->chain_len) % tx_desc_count; -} - -static void nb8800_tx_dma_start(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - - spin_lock_irq(&priv->tx_lock); - __nb8800_tx_dma_start(dev); - spin_unlock_irq(&priv->tx_lock); -} - -static void nb8800_tx_dma_start_irq(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - - spin_lock(&priv->tx_lock); - __nb8800_tx_dma_start(dev); - spin_unlock(&priv->tx_lock); -} - -static netdev_tx_t nb8800_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_tx_desc *txd; - struct nb8800_tx_buf *txb; - struct nb8800_dma_desc *desc; - dma_addr_t dma_addr; - unsigned int dma_len; - unsigned int align; - unsigned int next; - bool xmit_more; - - if (atomic_read(&priv->tx_free) <= nb8800_desc_low) { - netif_stop_queue(dev); - return netdev_tx_busy; - } - - align = (8 - (uintptr_t)skb->data) & 7; - - dma_len = skb->len - align; - dma_addr = dma_map_single(&dev->dev, skb->data + align, - dma_len, dma_to_device); - - if (dma_mapping_error(&dev->dev, dma_addr)) { - netdev_err(dev, "tx dma mapping error "); - kfree_skb(skb); - dev->stats.tx_dropped++; - return netdev_tx_ok; - } - - xmit_more = netdev_xmit_more(); - if (atomic_dec_return(&priv->tx_free) <= nb8800_desc_low) { - netif_stop_queue(dev); - xmit_more = false; - } - - next = priv->tx_next; - txb = &priv->tx_bufs[next]; - txd = &priv->tx_descs[next]; - desc = &txd->desc[0]; - - next = (next + 1) % tx_desc_count; - - if (align) { - memcpy(txd->buf, skb->data, align); - - desc->s_addr = - txb->dma_desc + offsetof(struct nb8800_tx_desc, buf); - desc->n_addr = txb->dma_desc + sizeof(txd->desc[0]); - desc->config = desc_bts(2) | desc_ds | align; - - desc++; - } - - desc->s_addr = dma_addr; - desc->n_addr = priv->tx_bufs[next].dma_desc; - desc->config = desc_bts(2) | desc_ds | desc_eof | dma_len; - - if (!xmit_more) - desc->config |= desc_eoc; - - txb->skb = skb; - txb->dma_addr = dma_addr; - txb->dma_len = dma_len; - - if (!priv->tx_chain) { - txb->chain_len = 1; - priv->tx_chain = txb; - } else { - priv->tx_chain->chain_len++; - } - - netdev_sent_queue(dev, skb->len); - - priv->tx_next = next; - - if (!xmit_more) { - smp_wmb(); - priv->tx_chain->ready = true; - priv->tx_chain = null; - nb8800_tx_dma_start(dev); - } - - return netdev_tx_ok; -} - -static void nb8800_tx_error(struct net_device *dev, u32 report) -{ - if (report & tx_late_collision) - dev->stats.collisions++; - - if (report & tx_packet_dropped) - dev->stats.tx_dropped++; - - if (report & tx_fifo_underrun) - dev->stats.tx_fifo_errors++; - - dev->stats.tx_errors++; -} - -static void nb8800_tx_done(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - unsigned int limit = priv->tx_next; - unsigned int done = priv->tx_done; - unsigned int packets = 0; - unsigned int len = 0; - - while (done != limit) { - struct nb8800_tx_desc *txd = &priv->tx_descs[done]; - struct nb8800_tx_buf *txb = &priv->tx_bufs[done]; - struct sk_buff *skb; - - if (!txd->report) - break; - - skb = txb->skb; - len += skb->len; - - dma_unmap_single(&dev->dev, txb->dma_addr, txb->dma_len, - dma_to_device); - - if (is_tx_error(txd->report)) { - nb8800_tx_error(dev, txd->report); - kfree_skb(skb); - } else { - consume_skb(skb); - } - - dev->stats.tx_packets++; - dev->stats.tx_bytes += tx_bytes_transferred(txd->report); - dev->stats.collisions += tx_early_collisions(txd->report); - - txb->skb = null; - txb->ready = false; - txd->report = 0; - - done = (done + 1) % tx_desc_count; - packets++; - } - - if (packets) { - smp_mb__before_atomic(); - atomic_add(packets, &priv->tx_free); - netdev_completed_queue(dev, packets, len); - netif_wake_queue(dev); - priv->tx_done = done; - } -} - -static irqreturn_t nb8800_irq(int irq, void *dev_id) -{ - struct net_device *dev = dev_id; - struct nb8800_priv *priv = netdev_priv(dev); - irqreturn_t ret = irq_none; - u32 val; - - /* tx interrupt */ - val = nb8800_readl(priv, nb8800_txc_sr); - if (val) { - nb8800_writel(priv, nb8800_txc_sr, val); - - if (val & tsr_di) - nb8800_tx_dma_start_irq(dev); - - if (val & tsr_ti) - napi_schedule_irqoff(&priv->napi); - - if (unlikely(val & tsr_de)) - netdev_err(dev, "tx dma error "); - - /* should never happen with automatic status retrieval */ - if (unlikely(val & tsr_to)) - netdev_err(dev, "tx status fifo overflow "); - - ret = irq_handled; - } - - /* rx interrupt */ - val = nb8800_readl(priv, nb8800_rxc_sr); - if (val) { - nb8800_writel(priv, nb8800_rxc_sr, val); - - if (likely(val & (rsr_ri | rsr_di))) { - nb8800_writel(priv, nb8800_rx_itr, priv->rx_itr_poll); - napi_schedule_irqoff(&priv->napi); - } - - if (unlikely(val & rsr_de)) - netdev_err(dev, "rx dma error "); - - /* should never happen with automatic status retrieval */ - if (unlikely(val & rsr_ro)) - netdev_err(dev, "rx status fifo overflow "); - - ret = irq_handled; - } - - return ret; -} - -static void nb8800_mac_config(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - bool gigabit = priv->speed == speed_1000; - u32 mac_mode_mask = rgmii_mode | half_duplex | gmac_mode; - u32 mac_mode = 0; - u32 slot_time; - u32 phy_clk; - u32 ict; - - if (!priv->duplex) - mac_mode |= half_duplex; - - if (gigabit) { - if (phy_interface_is_rgmii(dev->phydev)) - mac_mode |= rgmii_mode; - - mac_mode |= gmac_mode; - phy_clk = 125000000; - - /* should be 512 but register is only 8 bits */ - slot_time = 255; - } else { - phy_clk = 25000000; - slot_time = 128; - } - - ict = div_round_up(phy_clk, clk_get_rate(priv->clk)); - - nb8800_writeb(priv, nb8800_ic_threshold, ict); - nb8800_writeb(priv, nb8800_slot_time, slot_time); - nb8800_maskb(priv, nb8800_mac_mode, mac_mode_mask, mac_mode); -} - -static void nb8800_pause_config(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - u32 rxcr; - - if (priv->pause_aneg) { - if (!phydev || !phydev->link) - return; - - priv->pause_rx = phydev->pause; - priv->pause_tx = phydev->pause ^ phydev->asym_pause; - } - - nb8800_modb(priv, nb8800_rx_ctl, rx_pause_en, priv->pause_rx); - - rxcr = nb8800_readl(priv, nb8800_rxc_cr); - if (!!(rxcr & rcr_fl) == priv->pause_tx) - return; - - if (netif_running(dev)) { - napi_disable(&priv->napi); - netif_tx_lock_bh(dev); - nb8800_dma_stop(dev); - nb8800_modl(priv, nb8800_rxc_cr, rcr_fl, priv->pause_tx); - nb8800_start_rx(dev); - netif_tx_unlock_bh(dev); - napi_enable(&priv->napi); - } else { - nb8800_modl(priv, nb8800_rxc_cr, rcr_fl, priv->pause_tx); - } -} - -static void nb8800_link_reconfigure(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - int change = 0; - - if (phydev->link) { - if (phydev->speed != priv->speed) { - priv->speed = phydev->speed; - change = 1; - } - - if (phydev->duplex != priv->duplex) { - priv->duplex = phydev->duplex; - change = 1; - } - - if (change) - nb8800_mac_config(dev); - - nb8800_pause_config(dev); - } - - if (phydev->link != priv->link) { - priv->link = phydev->link; - change = 1; - } - - if (change) - phy_print_status(phydev); -} - -static void nb8800_update_mac_addr(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - int i; - - for (i = 0; i < eth_alen; i++) - nb8800_writeb(priv, nb8800_src_addr(i), dev->dev_addr[i]); - - for (i = 0; i < eth_alen; i++) - nb8800_writeb(priv, nb8800_uc_addr(i), dev->dev_addr[i]); -} - -static int nb8800_set_mac_address(struct net_device *dev, void *addr) -{ - struct sockaddr *sock = addr; - - if (netif_running(dev)) - return -ebusy; - - ether_addr_copy(dev->dev_addr, sock->sa_data); - nb8800_update_mac_addr(dev); - - return 0; -} - -static void nb8800_mc_init(struct net_device *dev, int val) -{ - struct nb8800_priv *priv = netdev_priv(dev); - - nb8800_writeb(priv, nb8800_mc_init, val); - readb_poll_timeout_atomic(priv->base + nb8800_mc_init, val, !val, - 1, 1000); -} - -static void nb8800_set_rx_mode(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct netdev_hw_addr *ha; - int i; - - if (dev->flags & (iff_promisc | iff_allmulti)) { - nb8800_mac_af(dev, false); - return; - } - - nb8800_mac_af(dev, true); - nb8800_mc_init(dev, 0); - - netdev_for_each_mc_addr(ha, dev) { - for (i = 0; i < eth_alen; i++) - nb8800_writeb(priv, nb8800_mc_addr(i), ha->addr[i]); - - nb8800_mc_init(dev, 0xff); - } -} - -#define rx_desc_size (rx_desc_count * sizeof(struct nb8800_rx_desc)) -#define tx_desc_size (tx_desc_count * sizeof(struct nb8800_tx_desc)) - -static void nb8800_dma_free(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - unsigned int i; - - if (priv->rx_bufs) { - for (i = 0; i < rx_desc_count; i++) - if (priv->rx_bufs[i].page) - put_page(priv->rx_bufs[i].page); - - kfree(priv->rx_bufs); - priv->rx_bufs = null; - } - - if (priv->tx_bufs) { - for (i = 0; i < tx_desc_count; i++) - kfree_skb(priv->tx_bufs[i].skb); - - kfree(priv->tx_bufs); - priv->tx_bufs = null; - } - - if (priv->rx_descs) { - dma_free_coherent(dev->dev.parent, rx_desc_size, priv->rx_descs, - priv->rx_desc_dma); - priv->rx_descs = null; - } - - if (priv->tx_descs) { - dma_free_coherent(dev->dev.parent, tx_desc_size, priv->tx_descs, - priv->tx_desc_dma); - priv->tx_descs = null; - } -} - -static void nb8800_dma_reset(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_rx_desc *rxd; - struct nb8800_tx_desc *txd; - unsigned int i; - - for (i = 0; i < rx_desc_count; i++) { - dma_addr_t rx_dma = priv->rx_desc_dma + i * sizeof(*rxd); - - rxd = &priv->rx_descs[i]; - rxd->desc.n_addr = rx_dma + sizeof(*rxd); - rxd->desc.r_addr = - rx_dma + offsetof(struct nb8800_rx_desc, report); - rxd->desc.config = priv->rx_dma_config; - rxd->report = 0; - } - - rxd->desc.n_addr = priv->rx_desc_dma; - rxd->desc.config |= desc_eoc; - - priv->rx_eoc = rx_desc_count - 1; - - for (i = 0; i < tx_desc_count; i++) { - struct nb8800_tx_buf *txb = &priv->tx_bufs[i]; - dma_addr_t r_dma = txb->dma_desc + - offsetof(struct nb8800_tx_desc, report); - - txd = &priv->tx_descs[i]; - txd->desc[0].r_addr = r_dma; - txd->desc[1].r_addr = r_dma; - txd->report = 0; - } - - priv->tx_next = 0; - priv->tx_queue = 0; - priv->tx_done = 0; - atomic_set(&priv->tx_free, tx_desc_count); - - nb8800_writel(priv, nb8800_rx_desc_addr, priv->rx_desc_dma); - - wmb(); /* ensure all setup is written before starting */ -} - -static int nb8800_dma_init(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - unsigned int n_rx = rx_desc_count; - unsigned int n_tx = tx_desc_count; - unsigned int i; - int err; - - priv->rx_descs = dma_alloc_coherent(dev->dev.parent, rx_desc_size, - &priv->rx_desc_dma, gfp_kernel); - if (!priv->rx_descs) - goto err_out; - - priv->rx_bufs = kcalloc(n_rx, sizeof(*priv->rx_bufs), gfp_kernel); - if (!priv->rx_bufs) - goto err_out; - - for (i = 0; i < n_rx; i++) { - err = nb8800_alloc_rx(dev, i, false); - if (err) - goto err_out; - } - - priv->tx_descs = dma_alloc_coherent(dev->dev.parent, tx_desc_size, - &priv->tx_desc_dma, gfp_kernel); - if (!priv->tx_descs) - goto err_out; - - priv->tx_bufs = kcalloc(n_tx, sizeof(*priv->tx_bufs), gfp_kernel); - if (!priv->tx_bufs) - goto err_out; - - for (i = 0; i < n_tx; i++) - priv->tx_bufs[i].dma_desc = - priv->tx_desc_dma + i * sizeof(struct nb8800_tx_desc); - - nb8800_dma_reset(dev); - - return 0; - -err_out: - nb8800_dma_free(dev); - - return -enomem; -} - -static int nb8800_dma_stop(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct nb8800_tx_buf *txb = &priv->tx_bufs[0]; - struct nb8800_tx_desc *txd = &priv->tx_descs[0]; - int retry = 5; - u32 txcr; - u32 rxcr; - int err; - unsigned int i; - - /* wait for tx to finish */ - err = readl_poll_timeout_atomic(priv->base + nb8800_txc_cr, txcr, - !(txcr & tcr_en) && - priv->tx_done == priv->tx_next, - 1000, 1000000); - if (err) - return err; - - /* the rx dma only stops if it reaches the end of chain. - * to make this happen, we set the eoc flag on all rx - * descriptors, put the device in loopback mode, and send - * a few dummy frames. the interrupt handler will ignore - * these since napi is disabled and no real frames are in - * the tx queue. - */ - - for (i = 0; i < rx_desc_count; i++) - priv->rx_descs[i].desc.config |= desc_eoc; - - txd->desc[0].s_addr = - txb->dma_desc + offsetof(struct nb8800_tx_desc, buf); - txd->desc[0].config = desc_bts(2) | desc_ds | desc_eof | desc_eoc | 8; - memset(txd->buf, 0, sizeof(txd->buf)); - - nb8800_mac_af(dev, false); - nb8800_setb(priv, nb8800_mac_mode, loopback_en); - - do { - nb8800_writel(priv, nb8800_tx_desc_addr, txb->dma_desc); - wmb(); - nb8800_writel(priv, nb8800_txc_cr, txcr | tcr_en); - - err = readl_poll_timeout_atomic(priv->base + nb8800_rxc_cr, - rxcr, !(rxcr & rcr_en), - 1000, 100000); - } while (err && --retry); - - nb8800_mac_af(dev, true); - nb8800_clearb(priv, nb8800_mac_mode, loopback_en); - nb8800_dma_reset(dev); - - return retry ? 0 : -etimedout; -} - -static void nb8800_pause_adv(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - - if (!phydev) - return; - - phy_set_asym_pause(phydev, priv->pause_rx, priv->pause_tx); -} - -static int nb8800_open(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct phy_device *phydev; - int err; - - /* clear any pending interrupts */ - nb8800_writel(priv, nb8800_rxc_sr, 0xf); - nb8800_writel(priv, nb8800_txc_sr, 0xf); - - err = nb8800_dma_init(dev); - if (err) - return err; - - err = request_irq(dev->irq, nb8800_irq, 0, dev_name(&dev->dev), dev); - if (err) - goto err_free_dma; - - nb8800_mac_rx(dev, true); - nb8800_mac_tx(dev, true); - - phydev = of_phy_connect(dev, priv->phy_node, - nb8800_link_reconfigure, 0, - priv->phy_mode); - if (!phydev) { - err = -enodev; - goto err_free_irq; - } - - nb8800_pause_adv(dev); - - netdev_reset_queue(dev); - napi_enable(&priv->napi); - netif_start_queue(dev); - - nb8800_start_rx(dev); - phy_start(phydev); - - return 0; - -err_free_irq: - free_irq(dev->irq, dev); -err_free_dma: - nb8800_dma_free(dev); - - return err; -} - -static int nb8800_stop(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - - phy_stop(phydev); - - netif_stop_queue(dev); - napi_disable(&priv->napi); - - nb8800_dma_stop(dev); - nb8800_mac_rx(dev, false); - nb8800_mac_tx(dev, false); - - phy_disconnect(phydev); - - free_irq(dev->irq, dev); - - nb8800_dma_free(dev); - - return 0; -} - -static const struct net_device_ops nb8800_netdev_ops = { - .ndo_open = nb8800_open, - .ndo_stop = nb8800_stop, - .ndo_start_xmit = nb8800_xmit, - .ndo_set_mac_address = nb8800_set_mac_address, - .ndo_set_rx_mode = nb8800_set_rx_mode, - .ndo_do_ioctl = phy_do_ioctl, - .ndo_validate_addr = eth_validate_addr, -}; - -static void nb8800_get_pauseparam(struct net_device *dev, - struct ethtool_pauseparam *pp) -{ - struct nb8800_priv *priv = netdev_priv(dev); - - pp->autoneg = priv->pause_aneg; - pp->rx_pause = priv->pause_rx; - pp->tx_pause = priv->pause_tx; -} - -static int nb8800_set_pauseparam(struct net_device *dev, - struct ethtool_pauseparam *pp) -{ - struct nb8800_priv *priv = netdev_priv(dev); - struct phy_device *phydev = dev->phydev; - - priv->pause_aneg = pp->autoneg; - priv->pause_rx = pp->rx_pause; - priv->pause_tx = pp->tx_pause; - - nb8800_pause_adv(dev); - - if (!priv->pause_aneg) - nb8800_pause_config(dev); - else if (phydev) - phy_start_aneg(phydev); - - return 0; -} - -static const char nb8800_stats_names[][eth_gstring_len] = { - "rx_bytes_ok", - "rx_frames_ok", - "rx_undersize_frames", - "rx_fragment_frames", - "rx_64_byte_frames", - "rx_127_byte_frames", - "rx_255_byte_frames", - "rx_511_byte_frames", - "rx_1023_byte_frames", - "rx_max_size_frames", - "rx_oversize_frames", - "rx_bad_fcs_frames", - "rx_broadcast_frames", - "rx_multicast_frames", - "rx_control_frames", - "rx_pause_frames", - "rx_unsup_control_frames", - "rx_align_error_frames", - "rx_overrun_frames", - "rx_jabber_frames", - "rx_bytes", - "rx_frames", - - "tx_bytes_ok", - "tx_frames_ok", - "tx_64_byte_frames", - "tx_127_byte_frames", - "tx_255_byte_frames", - "tx_511_byte_frames", - "tx_1023_byte_frames", - "tx_max_size_frames", - "tx_oversize_frames", - "tx_broadcast_frames", - "tx_multicast_frames", - "tx_control_frames", - "tx_pause_frames", - "tx_underrun_frames", - "tx_single_collision_frames", - "tx_multi_collision_frames", - "tx_deferred_collision_frames", - "tx_late_collision_frames", - "tx_excessive_collision_frames", - "tx_bytes", - "tx_frames", - "tx_collisions", -}; - -#define nb8800_num_stats array_size(nb8800_stats_names) - -static int nb8800_get_sset_count(struct net_device *dev, int sset) -{ - if (sset == eth_ss_stats) - return nb8800_num_stats; - - return -eopnotsupp; -} - -static void nb8800_get_strings(struct net_device *dev, u32 sset, u8 *buf) -{ - if (sset == eth_ss_stats) - memcpy(buf, &nb8800_stats_names, sizeof(nb8800_stats_names)); -} - -static u32 nb8800_read_stat(struct net_device *dev, int index) -{ - struct nb8800_priv *priv = netdev_priv(dev); - - nb8800_writeb(priv, nb8800_stat_index, index); - - return nb8800_readl(priv, nb8800_stat_data); -} - -static void nb8800_get_ethtool_stats(struct net_device *dev, - struct ethtool_stats *estats, u64 *st) -{ - unsigned int i; - u32 rx, tx; - - for (i = 0; i < nb8800_num_stats / 2; i++) { - rx = nb8800_read_stat(dev, i); - tx = nb8800_read_stat(dev, i | 0x80); - st[i] = rx; - st[i + nb8800_num_stats / 2] = tx; - } -} - -static const struct ethtool_ops nb8800_ethtool_ops = { - .nway_reset = phy_ethtool_nway_reset, - .get_link = ethtool_op_get_link, - .get_pauseparam = nb8800_get_pauseparam, - .set_pauseparam = nb8800_set_pauseparam, - .get_sset_count = nb8800_get_sset_count, - .get_strings = nb8800_get_strings, - .get_ethtool_stats = nb8800_get_ethtool_stats, - .get_link_ksettings = phy_ethtool_get_link_ksettings, - .set_link_ksettings = phy_ethtool_set_link_ksettings, -}; - -static int nb8800_hw_init(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - u32 val; - - val = tx_retry_en | tx_pad_en | tx_append_fcs; - nb8800_writeb(priv, nb8800_tx_ctl1, val); - - /* collision retry count */ - nb8800_writeb(priv, nb8800_tx_ctl2, 5); - - val = rx_pad_strip | rx_af_en; - nb8800_writeb(priv, nb8800_rx_ctl, val); - - /* chosen by fair dice roll */ - nb8800_writeb(priv, nb8800_random_seed, 4); - - /* tx cycles per deferral period */ - nb8800_writeb(priv, nb8800_tx_sdp, 12); - - /* the following three threshold values have been - * experimentally determined for good results. - */ - - /* rx/tx fifo threshold for partial empty (64-bit entries) */ - nb8800_writeb(priv, nb8800_pe_threshold, 0); - - /* rx/tx fifo threshold for partial full (64-bit entries) */ - nb8800_writeb(priv, nb8800_pf_threshold, 255); - - /* buffer size for transmit (64-bit entries) */ - nb8800_writeb(priv, nb8800_tx_bufsize, 64); - - /* configure tx dma */ - - val = nb8800_readl(priv, nb8800_txc_cr); - val &= tcr_le; /* keep endian setting */ - val |= tcr_dm; /* dma descriptor mode */ - val |= tcr_rs; /* automatically store tx status */ - val |= tcr_die; /* interrupt on dma chain completion */ - val |= tcr_tfi(7); /* interrupt after 7 frames transmitted */ - val |= tcr_bts(2); /* 32-byte bus transaction size */ - nb8800_writel(priv, nb8800_txc_cr, val); - - /* tx complete interrupt after 10 ms or 7 frames (see above) */ - val = clk_get_rate(priv->clk) / 100; - nb8800_writel(priv, nb8800_tx_itr, val); - - /* configure rx dma */ - - val = nb8800_readl(priv, nb8800_rxc_cr); - val &= rcr_le; /* keep endian setting */ - val |= rcr_dm; /* dma descriptor mode */ - val |= rcr_rs; /* automatically store rx status */ - val |= rcr_die; /* interrupt at end of dma chain */ - val |= rcr_rfi(7); /* interrupt after 7 frames received */ - val |= rcr_bts(2); /* 32-byte bus transaction size */ - nb8800_writel(priv, nb8800_rxc_cr, val); - - /* the rx interrupt can fire before the dma has completed - * unless a small delay is added. 50 us is hopefully enough. - */ - priv->rx_itr_irq = clk_get_rate(priv->clk) / 20000; - - /* in napi poll mode we want to disable interrupts, but the - * hardware does not permit this. delay 10 ms instead. - */ - priv->rx_itr_poll = clk_get_rate(priv->clk) / 100; - - nb8800_writel(priv, nb8800_rx_itr, priv->rx_itr_irq); - - priv->rx_dma_config = rx_buf_size | desc_bts(2) | desc_ds | desc_eof; - - /* flow control settings */ - - /* pause time of 0.1 ms */ - val = 100000 / 512; - nb8800_writeb(priv, nb8800_pq1, val >> 8); - nb8800_writeb(priv, nb8800_pq2, val & 0xff); - - /* auto-negotiate by default */ - priv->pause_aneg = true; - priv->pause_rx = true; - priv->pause_tx = true; - - nb8800_mc_init(dev, 0); - - return 0; -} - -static int nb8800_tangox_init(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - u32 pad_mode = pad_mode_mii; - - switch (priv->phy_mode) { - case phy_interface_mode_mii: - case phy_interface_mode_gmii: - pad_mode = pad_mode_mii; - break; - - case phy_interface_mode_rgmii: - case phy_interface_mode_rgmii_id: - case phy_interface_mode_rgmii_rxid: - case phy_interface_mode_rgmii_txid: - pad_mode = pad_mode_rgmii; - break; - - default: - dev_err(dev->dev.parent, "unsupported phy mode %s ", - phy_modes(priv->phy_mode)); - return -einval; - } - - nb8800_writeb(priv, nb8800_tangox_pad_mode, pad_mode); - - return 0; -} - -static int nb8800_tangox_reset(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - int clk_div; - - nb8800_writeb(priv, nb8800_tangox_reset, 0); - usleep_range(1000, 10000); - nb8800_writeb(priv, nb8800_tangox_reset, 1); - - wmb(); /* ensure reset is cleared before proceeding */ - - clk_div = div_round_up(clk_get_rate(priv->clk), 2 * max_mdc_clock); - nb8800_writew(priv, nb8800_tangox_mdio_clkdiv, clk_div); - - return 0; -} - -static const struct nb8800_ops nb8800_tangox_ops = { - .init = nb8800_tangox_init, - .reset = nb8800_tangox_reset, -}; - -static int nb8800_tango4_init(struct net_device *dev) -{ - struct nb8800_priv *priv = netdev_priv(dev); - int err; - - err = nb8800_tangox_init(dev); - if (err) - return err; - - /* on tango4 interrupt on dma completion per frame works and gives - * better performance despite generating more rx interrupts. - */ - - /* disable unnecessary interrupt on rx completion */ - nb8800_clearl(priv, nb8800_rxc_cr, rcr_rfi(7)); - - /* request interrupt on descriptor dma completion */ - priv->rx_dma_config |= desc_id; - - return 0; -} - -static const struct nb8800_ops nb8800_tango4_ops = { - .init = nb8800_tango4_init, - .reset = nb8800_tangox_reset, -}; - -static const struct of_device_id nb8800_dt_ids[] = { - { - .compatible = "aurora,nb8800", - }, - { - .compatible = "sigma,smp8642-ethernet", - .data = &nb8800_tangox_ops, - }, - { - .compatible = "sigma,smp8734-ethernet", - .data = &nb8800_tango4_ops, - }, - { } -}; -module_device_table(of, nb8800_dt_ids); - -static int nb8800_probe(struct platform_device *pdev) -{ - const struct of_device_id *match; - const struct nb8800_ops *ops = null; - struct nb8800_priv *priv; - struct resource *res; - struct net_device *dev; - struct mii_bus *bus; - const unsigned char *mac; - void __iomem *base; - int irq; - int ret; - - match = of_match_device(nb8800_dt_ids, &pdev->dev); - if (match) - ops = match->data; - - irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -einval; - - res = platform_get_resource(pdev, ioresource_mem, 0); - base = devm_ioremap_resource(&pdev->dev, res); - if (is_err(base)) - return ptr_err(base); - - dev_dbg(&pdev->dev, "au-nb8800 ethernet at %pa ", &res->start); - - dev = alloc_etherdev(sizeof(*priv)); - if (!dev) - return -enomem; - - platform_set_drvdata(pdev, dev); - set_netdev_dev(dev, &pdev->dev); - - priv = netdev_priv(dev); - priv->base = base; - - ret = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode); - if (ret) - priv->phy_mode = phy_interface_mode_rgmii; - - priv->clk = devm_clk_get(&pdev->dev, null); - if (is_err(priv->clk)) { - dev_err(&pdev->dev, "failed to get clock "); - ret = ptr_err(priv->clk); - goto err_free_dev; - } - - ret = clk_prepare_enable(priv->clk); - if (ret) - goto err_free_dev; - - spin_lock_init(&priv->tx_lock); - - if (ops && ops->reset) { - ret = ops->reset(dev); - if (ret) - goto err_disable_clk; - } - - bus = devm_mdiobus_alloc(&pdev->dev); - if (!bus) { - ret = -enomem; - goto err_disable_clk; - } - - bus->name = "nb8800-mii"; - bus->read = nb8800_mdio_read; - bus->write = nb8800_mdio_write; - bus->parent = &pdev->dev; - snprintf(bus->id, mii_bus_id_size, "%lx.nb8800-mii", - (unsigned long)res->start); - bus->priv = priv; - - ret = of_mdiobus_register(bus, pdev->dev.of_node); - if (ret) { - dev_err(&pdev->dev, "failed to register mii bus "); - goto err_disable_clk; - } - - if (of_phy_is_fixed_link(pdev->dev.of_node)) { - ret = of_phy_register_fixed_link(pdev->dev.of_node); - if (ret < 0) { - dev_err(&pdev->dev, "bad fixed-link spec "); - goto err_free_bus; - } - priv->phy_node = of_node_get(pdev->dev.of_node); - } - - if (!priv->phy_node) - priv->phy_node = of_parse_phandle(pdev->dev.of_node, - "phy-handle", 0); - - if (!priv->phy_node) { - dev_err(&pdev->dev, "no phy specified "); - ret = -enodev; - goto err_free_bus; - } - - priv->mii_bus = bus; - - ret = nb8800_hw_init(dev); - if (ret) - goto err_deregister_fixed_link; - - if (ops && ops->init) { - ret = ops->init(dev); - if (ret) - goto err_deregister_fixed_link; - } - - dev->netdev_ops = &nb8800_netdev_ops; - dev->ethtool_ops = &nb8800_ethtool_ops; - dev->flags |= iff_multicast; - dev->irq = irq; - - mac = of_get_mac_address(pdev->dev.of_node); - if (!is_err(mac)) - ether_addr_copy(dev->dev_addr, mac); - - if (!is_valid_ether_addr(dev->dev_addr)) - eth_hw_addr_random(dev); - - nb8800_update_mac_addr(dev); - - netif_carrier_off(dev); - - ret = register_netdev(dev); - if (ret) { - netdev_err(dev, "failed to register netdev "); - goto err_free_dma; - } - - netif_napi_add(dev, &priv->napi, nb8800_poll, napi_poll_weight); - - netdev_info(dev, "mac address %pm ", dev->dev_addr); - - return 0; - -err_free_dma: - nb8800_dma_free(dev); -err_deregister_fixed_link: - if (of_phy_is_fixed_link(pdev->dev.of_node)) - of_phy_deregister_fixed_link(pdev->dev.of_node); -err_free_bus: - of_node_put(priv->phy_node); - mdiobus_unregister(bus); -err_disable_clk: - clk_disable_unprepare(priv->clk); -err_free_dev: - free_netdev(dev); - - return ret; -} - -static int nb8800_remove(struct platform_device *pdev) -{ - struct net_device *ndev = platform_get_drvdata(pdev); - struct nb8800_priv *priv = netdev_priv(ndev); - - unregister_netdev(ndev); - if (of_phy_is_fixed_link(pdev->dev.of_node)) - of_phy_deregister_fixed_link(pdev->dev.of_node); - of_node_put(priv->phy_node); - - mdiobus_unregister(priv->mii_bus); - - clk_disable_unprepare(priv->clk); - - nb8800_dma_free(ndev); - free_netdev(ndev); - - return 0; -} - -static struct platform_driver nb8800_driver = { - .driver = { - .name = "nb8800", - .of_match_table = nb8800_dt_ids, - }, - .probe = nb8800_probe, - .remove = nb8800_remove, -}; - -module_platform_driver(nb8800_driver); - -module_description("aurora au-nb8800 ethernet driver"); -module_author("mans rullgard <mans@mansr.com>"); -module_license("gpl"); diff --git a/drivers/net/ethernet/aurora/nb8800.h b/drivers/net/ethernet/aurora/nb8800.h --- a/drivers/net/ethernet/aurora/nb8800.h +++ /dev/null -/* spdx-license-identifier: gpl-2.0 */ -#ifndef _nb8800_h_ -#define _nb8800_h_ - -#include <linux/types.h> -#include <linux/skbuff.h> -#include <linux/phy.h> -#include <linux/clk.h> -#include <linux/bitops.h> - -#define rx_desc_count 256 -#define tx_desc_count 256 - -#define nb8800_desc_low 4 - -#define rx_buf_size 1552 - -#define rx_copybreak 256 -#define rx_copyhdr 128 - -#define max_mdc_clock 2500000 - -/* stargate solutions ssn8800 core registers */ -#define nb8800_tx_ctl1 0x000 -#define tx_tpd bit(5) -#define tx_append_fcs bit(4) -#define tx_pad_en bit(3) -#define tx_retry_en bit(2) -#define tx_en bit(0) - -#define nb8800_tx_ctl2 0x001 - -#define nb8800_rx_ctl 0x004 -#define rx_bc_disable bit(7) -#define rx_runt bit(6) -#define rx_af_en bit(5) -#define rx_pause_en bit(3) -#define rx_send_crc bit(2) -#define rx_pad_strip bit(1) -#define rx_en bit(0) - -#define nb8800_random_seed 0x008 -#define nb8800_tx_sdp 0x14 -#define nb8800_tx_tpdp1 0x18 -#define nb8800_tx_tpdp2 0x19 -#define nb8800_slot_time 0x1c - -#define nb8800_mdio_cmd 0x020 -#define mdio_cmd_go bit(31) -#define mdio_cmd_wr bit(26) -#define mdio_cmd_addr(x) ((x) << 21) -#define mdio_cmd_reg(x) ((x) << 16) -#define mdio_cmd_data(x) ((x) << 0) - -#define nb8800_mdio_sts 0x024 -#define mdio_sts_err bit(31) - -#define nb8800_mc_addr(i) (0x028 + (i)) -#define nb8800_mc_init 0x02e -#define nb8800_uc_addr(i) (0x03c + (i)) - -#define nb8800_mac_mode 0x044 -#define rgmii_mode bit(7) -#define half_duplex bit(4) -#define burst_en bit(3) -#define loopback_en bit(2) -#define gmac_mode bit(0) - -#define nb8800_ic_threshold 0x050 -#define nb8800_pe_threshold 0x051 -#define nb8800_pf_threshold 0x052 -#define nb8800_tx_bufsize 0x054 -#define nb8800_fifo_ctl 0x056 -#define nb8800_pq1 0x060 -#define nb8800_pq2 0x061 -#define nb8800_src_addr(i) (0x06a + (i)) -#define nb8800_stat_data 0x078 -#define nb8800_stat_index 0x07c -#define nb8800_stat_clear 0x07d - -#define nb8800_sleep_mode 0x07e -#define sleep_mode bit(0) - -#define nb8800_wakeup 0x07f -#define wakeup bit(0) - -/* aurora nb8800 host interface registers */ -#define nb8800_txc_cr 0x100 -#define tcr_lk bit(12) -#define tcr_ds bit(11) -#define tcr_bts(x) (((x) & 0x7) << 8) -#define tcr_die bit(7) -#define tcr_tfi(x) (((x) & 0x7) << 4) -#define tcr_le bit(3) -#define tcr_rs bit(2) -#define tcr_dm bit(1) -#define tcr_en bit(0) - -#define nb8800_txc_sr 0x104 -#define tsr_de bit(3) -#define tsr_di bit(2) -#define tsr_to bit(1) -#define tsr_ti bit(0) - -#define nb8800_tx_sar 0x108 -#define nb8800_tx_desc_addr 0x10c - -#define nb8800_tx_report_addr 0x110 -#define tx_bytes_transferred(x) (((x) >> 16) & 0xffff) -#define tx_first_deferral bit(7) -#define tx_early_collisions(x) (((x) >> 3) & 0xf) -#define tx_late_collision bit(2) -#define tx_packet_dropped bit(1) -#define tx_fifo_underrun bit(0) -#define is_tx_error(r) ((r) & 0x07) - -#define nb8800_tx_fifo_sr 0x114 -#define nb8800_tx_itr 0x118 - -#define nb8800_rxc_cr 0x200 -#define rcr_fl bit(13) -#define rcr_lk bit(12) -#define rcr_ds bit(11) -#define rcr_bts(x) (((x) & 7) << 8) -#define rcr_die bit(7) -#define rcr_rfi(x) (((x) & 7) << 4) -#define rcr_le bit(3) -#define rcr_rs bit(2) -#define rcr_dm bit(1) -#define rcr_en bit(0) - -#define nb8800_rxc_sr 0x204 -#define rsr_de bit(3) -#define rsr_di bit(2) -#define rsr_ro bit(1) -#define rsr_ri bit(0) - -#define nb8800_rx_sar 0x208 -#define nb8800_rx_desc_addr 0x20c - -#define nb8800_rx_report_addr 0x210 -#define rx_bytes_transferred(x) (((x) >> 16) & 0xffff) -#define rx_multicast_pkt bit(9) -#define rx_broadcast_pkt bit(8) -#define rx_length_err bit(7) -#define rx_fcs_err bit(6) -#define rx_runt_pkt bit(5) -#define rx_fifo_overrun bit(4) -#define rx_late_collision bit(3) -#define rx_alignment_error bit(2) -#define rx_error_mask 0xfc -#define is_rx_error(r) ((r) & rx_error_mask) - -#define nb8800_rx_fifo_sr 0x214 -#define nb8800_rx_itr 0x218 - -/* sigma designs smp86xx additional registers */ -#define nb8800_tangox_pad_mode 0x400 -#define pad_mode_mask 0x7 -#define pad_mode_mii 0x0 -#define pad_mode_rgmii 0x1 -#define pad_mode_gtx_clk_inv bit(3) -#define pad_mode_gtx_clk_delay bit(4) - -#define nb8800_tangox_mdio_clkdiv 0x420 -#define nb8800_tangox_reset 0x424 - -/* hardware dma descriptor */ -struct nb8800_dma_desc { - u32 s_addr; /* start address */ - u32 n_addr; /* next descriptor address */ - u32 r_addr; /* report address */ - u32 config; -} __aligned(8); - -#define desc_id bit(23) -#define desc_eoc bit(22) -#define desc_eof bit(21) -#define desc_lk bit(20) -#define desc_ds bit(19) -#define desc_bts(x) (((x) & 0x7) << 16) - -/* dma descriptor and associated data for rx. - * allocated from coherent memory. - */ -struct nb8800_rx_desc { - /* dma descriptor */ - struct nb8800_dma_desc desc; - - /* status report filled in by hardware */ - u32 report; -}; - -/* address of buffer on rx ring */ -struct nb8800_rx_buf { - struct page *page; - unsigned long offset; -}; - -/* dma descriptors and associated data for tx. - * allocated from coherent memory. - */ -struct nb8800_tx_desc { - /* dma descriptor. the second descriptor is used if packet - * data is unaligned. - */ - struct nb8800_dma_desc desc[2]; - - /* status report filled in by hardware */ - u32 report; - - /* bounce buffer for initial unaligned part of packet */ - u8 buf[8] __aligned(8); -}; - -/* packet in tx queue */ -struct nb8800_tx_buf { - /* currently queued skb */ - struct sk_buff *skb; - - /* dma address of the first descriptor */ - dma_addr_t dma_desc; - - /* dma address of packet data */ - dma_addr_t dma_addr; - - /* length of dma mapping, less than skb->len if alignment - * buffer is used. - */ - unsigned int dma_len; - - /* number of packets in chain starting here */ - unsigned int chain_len; - - /* packet chain ready to be submitted to hardware */ - bool ready; -}; - -struct nb8800_priv { - struct napi_struct napi; - - void __iomem *base; - - /* rx dma descriptors */ - struct nb8800_rx_desc *rx_descs; - - /* rx buffers referenced by dma descriptors */ - struct nb8800_rx_buf *rx_bufs; - - /* current end of chain */ - u32 rx_eoc; - - /* value for rx interrupt time register in napi interrupt mode */ - u32 rx_itr_irq; - - /* value for rx interrupt time register in napi poll mode */ - u32 rx_itr_poll; - - /* value for config field of rx dma descriptors */ - u32 rx_dma_config; - - /* tx dma descriptors */ - struct nb8800_tx_desc *tx_descs; - - /* tx packet queue */ - struct nb8800_tx_buf *tx_bufs; - - /* number of free tx queue entries */ - atomic_t tx_free; - - /* first free tx queue entry */ - u32 tx_next; - - /* next buffer to transmit */ - u32 tx_queue; - - /* start of current packet chain */ - struct nb8800_tx_buf *tx_chain; - - /* next buffer to reclaim */ - u32 tx_done; - - /* lock for dma activation */ - spinlock_t tx_lock; - - struct mii_bus *mii_bus; - struct device_node *phy_node; - - /* phy connection type from dt */ - phy_interface_t phy_mode; - - /* current link status */ - int speed; - int duplex; - int link; - - /* pause settings */ - bool pause_aneg; - bool pause_rx; - bool pause_tx; - - /* dma base address of rx descriptors, see rx_descs above */ - dma_addr_t rx_desc_dma; - - /* dma base address of tx descriptors, see tx_descs above */ - dma_addr_t tx_desc_dma; - - struct clk *clk; -}; - -struct nb8800_ops { - int (*init)(struct net_device *dev); - int (*reset)(struct net_device *dev); -}; - -#endif /* _nb8800_h_ */
|
Networking
|
19038523a7353e7413c5428f20376fa3ccd2c8e9
|
arnd bergmann mans rullgard mans mansr com
|
drivers
|
net
|
aurora, ethernet
|
sound: add n64 driver
|
this adds support for the nintendo 64 console's sound.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add n64 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
[]
|
['kconfig', 'c', 'makefile']
| 3
| 380
| 0
|
--- diff --git a/sound/mips/kconfig b/sound/mips/kconfig --- a/sound/mips/kconfig +++ b/sound/mips/kconfig +config snd_n64 + bool "n64 audio" + depends on mach_nintendo64 && snd=y + select snd_pcm + help + sound support for the n64. + diff --git a/sound/mips/makefile b/sound/mips/makefile --- a/sound/mips/makefile +++ b/sound/mips/makefile +obj-$(config_snd_n64) += snd-n64.o diff --git a/sound/mips/snd-n64.c b/sound/mips/snd-n64.c --- /dev/null +++ b/sound/mips/snd-n64.c +// spdx-license-identifier: gpl-2.0 +/* + * sound driver for nintendo 64. + * + * copyright 2021 lauri kasanen + */ + +#include <linux/dma-mapping.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/log2.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/spinlock.h> + +#include <sound/control.h> +#include <sound/core.h> +#include <sound/initval.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> + +module_author("lauri kasanen <cand@gmx.com>"); +module_description("n64 audio"); +module_license("gpl"); + +#define ai_ntsc_dacrate 48681812 +#define ai_status_busy (1 << 30) +#define ai_status_full (1 << 31) + +#define ai_addr_reg 0 +#define ai_len_reg 1 +#define ai_control_reg 2 +#define ai_status_reg 3 +#define ai_rate_reg 4 +#define ai_bitclock_reg 5 + +#define mi_intr_reg 2 +#define mi_mask_reg 3 + +#define mi_intr_ai 0x04 + +#define mi_mask_clr_ai 0x0010 +#define mi_mask_set_ai 0x0020 + + +struct n64audio { + u32 __iomem *ai_reg_base; + u32 __iomem *mi_reg_base; + + void *ring_base; + dma_addr_t ring_base_dma; + + struct snd_card *card; + + struct { + struct snd_pcm_substream *substream; + int pos, nextpos; + u32 writesize; + u32 bufsize; + spinlock_t lock; + } chan; +}; + +static void n64audio_write_reg(struct n64audio *priv, const u8 reg, const u32 value) +{ + writel(value, priv->ai_reg_base + reg); +} + +static void n64mi_write_reg(struct n64audio *priv, const u8 reg, const u32 value) +{ + writel(value, priv->mi_reg_base + reg); +} + +static u32 n64mi_read_reg(struct n64audio *priv, const u8 reg) +{ + return readl(priv->mi_reg_base + reg); +} + +static void n64audio_push(struct n64audio *priv) +{ + struct snd_pcm_runtime *runtime = priv->chan.substream->runtime; + unsigned long flags; + u32 count; + + spin_lock_irqsave(&priv->chan.lock, flags); + + count = priv->chan.writesize; + + memcpy(priv->ring_base + priv->chan.nextpos, + runtime->dma_area + priv->chan.nextpos, count); + + /* + * the hw registers are double-buffered, and the irq fires essentially + * one period behind. the core only allows one period's distance, so we + * keep a private dma buffer to afford two. + */ + n64audio_write_reg(priv, ai_addr_reg, priv->ring_base_dma + priv->chan.nextpos); + barrier(); + n64audio_write_reg(priv, ai_len_reg, count); + + priv->chan.nextpos += count; + priv->chan.nextpos %= priv->chan.bufsize; + + runtime->delay = runtime->period_size; + + spin_unlock_irqrestore(&priv->chan.lock, flags); +} + +static irqreturn_t n64audio_isr(int irq, void *dev_id) +{ + struct n64audio *priv = dev_id; + const u32 intrs = n64mi_read_reg(priv, mi_intr_reg); + unsigned long flags; + + // check it's ours + if (!(intrs & mi_intr_ai)) + return irq_none; + + n64audio_write_reg(priv, ai_status_reg, 1); + + if (priv->chan.substream && snd_pcm_running(priv->chan.substream)) { + spin_lock_irqsave(&priv->chan.lock, flags); + + priv->chan.pos = priv->chan.nextpos; + + spin_unlock_irqrestore(&priv->chan.lock, flags); + + snd_pcm_period_elapsed(priv->chan.substream); + if (priv->chan.substream && snd_pcm_running(priv->chan.substream)) + n64audio_push(priv); + } + + return irq_handled; +} + +static const struct snd_pcm_hardware n64audio_pcm_hw = { + .info = (sndrv_pcm_info_mmap | + sndrv_pcm_info_mmap_valid | + sndrv_pcm_info_interleaved | + sndrv_pcm_info_block_transfer), + .formats = sndrv_pcm_fmtbit_s16_be, + .rates = sndrv_pcm_rate_8000_48000, + .rate_min = 8000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, + .buffer_bytes_max = 32768, + .period_bytes_min = 1024, + .period_bytes_max = 32768, + .periods_min = 3, + // 3 periods lets the double-buffering hw read one buffer behind safely + .periods_max = 128, +}; + +static int hw_rule_period_size(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule) +{ + struct snd_interval *c = hw_param_interval(params, + sndrv_pcm_hw_param_period_size); + int changed = 0; + + /* + * the dma unit has errata on (start + len) & 0x3fff == 0x2000. + * this constraint makes sure that the period size is not a power of two, + * which combined with dma_alloc_coherent aligning the buffer to the largest + * pot <= size guarantees it won't be hit. + */ + + if (is_power_of_2(c->min)) { + c->min += 2; + changed = 1; + } + if (is_power_of_2(c->max)) { + c->max -= 2; + changed = 1; + } + if (snd_interval_checkempty(c)) { + c->empty = 1; + return -einval; + } + + return changed; +} + +static int n64audio_pcm_open(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + int err; + + runtime->hw = n64audio_pcm_hw; + err = snd_pcm_hw_constraint_integer(runtime, sndrv_pcm_hw_param_periods); + if (err < 0) + return err; + + err = snd_pcm_hw_constraint_step(runtime, 0, sndrv_pcm_hw_param_period_size, 2); + if (err < 0) + return err; + + err = snd_pcm_hw_rule_add(runtime, 0, sndrv_pcm_hw_param_period_size, + hw_rule_period_size, null, sndrv_pcm_hw_param_period_size, -1); + if (err < 0) + return err; + + return 0; +} + +static int n64audio_pcm_prepare(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + struct n64audio *priv = substream->pcm->private_data; + u32 rate; + + rate = ((2 * ai_ntsc_dacrate / runtime->rate) + 1) / 2 - 1; + + n64audio_write_reg(priv, ai_rate_reg, rate); + + rate /= 66; + if (rate > 16) + rate = 16; + n64audio_write_reg(priv, ai_bitclock_reg, rate - 1); + + spin_lock_irq(&priv->chan.lock); + + /* setup the pseudo-dma transfer pointers. */ + priv->chan.pos = 0; + priv->chan.nextpos = 0; + priv->chan.substream = substream; + priv->chan.writesize = snd_pcm_lib_period_bytes(substream); + priv->chan.bufsize = snd_pcm_lib_buffer_bytes(substream); + + spin_unlock_irq(&priv->chan.lock); + return 0; +} + +static int n64audio_pcm_trigger(struct snd_pcm_substream *substream, + int cmd) +{ + struct n64audio *priv = substream->pcm->private_data; + + switch (cmd) { + case sndrv_pcm_trigger_start: + n64audio_push(substream->pcm->private_data); + n64audio_write_reg(priv, ai_control_reg, 1); + n64mi_write_reg(priv, mi_mask_reg, mi_mask_set_ai); + break; + case sndrv_pcm_trigger_stop: + n64audio_write_reg(priv, ai_control_reg, 0); + n64mi_write_reg(priv, mi_mask_reg, mi_mask_clr_ai); + break; + default: + return -einval; + } + return 0; +} + +static snd_pcm_uframes_t n64audio_pcm_pointer(struct snd_pcm_substream *substream) +{ + struct n64audio *priv = substream->pcm->private_data; + + return bytes_to_frames(substream->runtime, + priv->chan.pos); +} + +static int n64audio_pcm_close(struct snd_pcm_substream *substream) +{ + struct n64audio *priv = substream->pcm->private_data; + + priv->chan.substream = null; + + return 0; +} + +static const struct snd_pcm_ops n64audio_pcm_ops = { + .open = n64audio_pcm_open, + .prepare = n64audio_pcm_prepare, + .trigger = n64audio_pcm_trigger, + .pointer = n64audio_pcm_pointer, + .close = n64audio_pcm_close, +}; + +/* + * the target device is embedded and ram-constrained. we save ram + * by initializing in __init code that gets dropped late in boot. + * for the same reason there is no module or unloading support. + */ +static int __init n64audio_probe(struct platform_device *pdev) +{ + struct snd_card *card; + struct snd_pcm *pcm; + struct n64audio *priv; + struct resource *res; + int err; + + err = snd_card_new(&pdev->dev, sndrv_default_idx1, + sndrv_default_str1, + this_module, sizeof(*priv), &card); + if (err < 0) + return err; + + priv = card->private_data; + + spin_lock_init(&priv->chan.lock); + + priv->card = card; + + priv->ring_base = dma_alloc_coherent(card->dev, 32 * 1024, &priv->ring_base_dma, + gfp_dma|gfp_kernel); + if (!priv->ring_base) { + err = -enomem; + goto fail_card; + } + + priv->mi_reg_base = devm_platform_ioremap_resource(pdev, 0); + if (!priv->mi_reg_base) { + err = -einval; + goto fail_dma_alloc; + } + + priv->ai_reg_base = devm_platform_ioremap_resource(pdev, 1); + if (!priv->ai_reg_base) { + err = -einval; + goto fail_dma_alloc; + } + + err = snd_pcm_new(card, "n64 audio", 0, 1, 0, &pcm); + if (err < 0) + goto fail_dma_alloc; + + pcm->private_data = priv; + strcpy(pcm->name, "n64 audio"); + + snd_pcm_set_ops(pcm, sndrv_pcm_stream_playback, &n64audio_pcm_ops); + snd_pcm_set_managed_buffer_all(pcm, sndrv_dma_type_vmalloc, card->dev, 0, 0); + + strcpy(card->driver, "n64 audio"); + strcpy(card->shortname, "n64 audio"); + strcpy(card->longname, "n64 audio"); + + res = platform_get_resource(pdev, ioresource_irq, 0); + if (devm_request_irq(&pdev->dev, res->start, n64audio_isr, + irqf_shared, "n64 audio", priv)) { + err = -ebusy; + goto fail_dma_alloc; + } + + err = snd_card_register(card); + if (err < 0) + goto fail_dma_alloc; + + return 0; + +fail_dma_alloc: + dma_free_coherent(card->dev, 32 * 1024, priv->ring_base, priv->ring_base_dma); + +fail_card: + snd_card_free(card); + return err; +} + +static struct platform_driver n64audio_driver = { + .driver = { + .name = "n64audio", + }, +}; + +static int __init n64audio_init(void) +{ + return platform_driver_probe(&n64audio_driver, n64audio_probe); +} + +module_init(n64audio_init);
|
Audio
|
1448f8acf4cc61197a228bdb7126e7eeb92760fe
|
lauri kasanen takashi iwai tiwai suse de
|
sound
|
mips
| |
alsa: dice: add support for lexicon i-onix fw810s
|
i-onix fw810s was shipped in lexicon brand of harman international industries, inc 2009. the model uses tcd2220 asic as its communication engine. tcat general protocol is supported, its extension isn't.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for lexicon i-onix fw810s
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dice']
|
['h', 'c', 'makefile']
| 4
| 41
| 1
|
----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- ----------------------------------------------------------------- --- diff --git a/sound/firewire/dice/makefile b/sound/firewire/dice/makefile --- a/sound/firewire/dice/makefile +++ b/sound/firewire/dice/makefile - dice-alesis.o dice-extension.o dice-mytek.o dice-presonus.o + dice-alesis.o dice-extension.o dice-mytek.o dice-presonus.o \ + dice-harman.o diff --git a/sound/firewire/dice/dice-harman.c b/sound/firewire/dice/dice-harman.c --- /dev/null +++ b/sound/firewire/dice/dice-harman.c +// spdx-license-identifier: gpl-2.0 +// dice-harman.c - a part of driver for dice based devices +// +// copyright (c) 2021 takashi sakamoto +// +// licensed under the terms of the gnu general public license, version 2. + +#include "dice.h" + +int snd_dice_detect_harman_formats(struct snd_dice *dice) +{ + int i; + + // lexicon i-onyx fw810s supports sampling transfer frequency up to + // 96.0 khz, 12 pcm channels and 1 midi channel in its first tx stream + // , 10 pcm channels and 1 midi channel in its first rx stream for all + // of the frequencies. + for (i = 0; i < 2; ++i) { + dice->tx_pcm_chs[0][i] = 12; + dice->tx_midi_ports[0] = 1; + dice->rx_pcm_chs[0][i] = 10; + dice->rx_midi_ports[0] = 1; + } + + return 0; +} diff --git a/sound/firewire/dice/dice.c b/sound/firewire/dice/dice.c --- a/sound/firewire/dice/dice.c +++ b/sound/firewire/dice/dice.c +#define oui_harman 0x000fd7 +#define harman_category_id 0x20 + else if (vendor == oui_harman) + category = harman_category_id; + // lexicon i-onyx fw810s. + { + .match_flags = ieee1394_match_vendor_id | + ieee1394_match_model_id, + .vendor_id = oui_harman, + .model_id = 0x000001, + .driver_data = (kernel_ulong_t)snd_dice_detect_harman_formats, + }, diff --git a/sound/firewire/dice/dice.h b/sound/firewire/dice/dice.h --- a/sound/firewire/dice/dice.h +++ b/sound/firewire/dice/dice.h +int snd_dice_detect_harman_formats(struct snd_dice *dice);
|
Audio
|
9a08676fc5968be8575ee2fa8926e55d8aef166c
|
takashi sakamoto
|
sound
|
firewire
|
dice
|
alsa: hda/ca0132: add sound blasterx ae-5 plus support
|
the new ae-5 plus model has a different subsystem id compared to the non-plus model. adding the new id to the list of quirks.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add sound blasterx ae-5 plus support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hda ', 'ca0132']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/sound/pci/hda/patch_ca0132.c b/sound/pci/hda/patch_ca0132.c --- a/sound/pci/hda/patch_ca0132.c +++ b/sound/pci/hda/patch_ca0132.c + snd_pci_quirk(0x1102, 0x0191, "sound blaster ae-5 plus", quirk_ae5),
|
Audio
|
f15c5c11abfbf8909eb30598315ecbec2311cfdc
|
simeon simeonoff
|
sound
|
pci
|
hda
|
alsa: hda: add another cometlake-h pci id
|
add one more hd audio pci id for cometlake-h pch.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add another cometlake-h pci id
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hda ']
|
['c']
| 1
| 2
| 0
|
--- diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c + { pci_device(0x8086, 0xf1c8), + .driver_data = azx_driver_skl | azx_dcaps_intel_skylake},
|
Audio
|
0d3070f5e6551d8a759619e85736e49a3bf40398
|
kai vehmanen pierre louis bossart pierre louis bossart linux intel com
|
sound
|
pci
|
hda
|
alsa: hda: intel-dsp-config: add alder lake support
|
add rules to select sof driver for alder lake systems if a digital microphone or soundwire codecs are present in the system. this is following same rules as for older tiger lake systems.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add alder lake support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hda ', 'intel-dsp-config']
|
['c']
| 1
| 12
| 0
|
--- diff --git a/sound/hda/intel-dsp-config.c b/sound/hda/intel-dsp-config.c --- a/sound/hda/intel-dsp-config.c +++ b/sound/hda/intel-dsp-config.c +/* alder lake */ +#if is_enabled(config_snd_soc_sof_alderlake) + { + .flags = flag_sof | flag_sof_only_if_dmic_or_soundwire, + .device = 0x7ad0, + }, + { + .flags = flag_sof | flag_sof_only_if_dmic_or_soundwire, + .device = 0x51c8, + }, +#endif +
|
Audio
|
c4294d7f057d05053412ebd0d5700228d0f2588d
|
kai vehmanen xiuli pan xiuli pan intel com ranjani sridharan ranjani sridharan linux intel com pierre louis bossart pierre louis bossart linux intel com
|
sound
|
hda
| |
alsa: hda: intel-dsp-config: add snd_intel_byt_prefer_sof kconfig option
|
the kernel has 2 drivers for the low power engine audio-block on bay- and cherry-trail socs. the old sst driver and the new sof driver. if both drivers are enabled then the kernel will default to using the old sst driver, unless told otherwise through the snd_intel_dspcfg.dsp_driver module-parameter.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add snd_intel_byt_prefer_sof kconfig option
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hda ', 'intel-dsp-config']
|
['kconfig', 'c']
| 2
| 26
| 17
|
--- diff --git a/sound/hda/kconfig b/sound/hda/kconfig --- a/sound/hda/kconfig +++ b/sound/hda/kconfig + +config snd_intel_byt_prefer_sof + bool "prefer sof driver over sst on by/cht platforms" + depends on snd_sst_atom_hifi2_platform_acpi && snd_soc_sof_baytrail + default n + help + the kernel has 2 drivers for the low power engine audio-block on + bay- and cherry-trail socs. the old sst driver and the new sof + driver. if both drivers are enabled then the kernel will default + to using the old sst driver, unless told otherwise through the + snd_intel_dspcfg.dsp_driver module-parameter. + + set this option to y to make the kernel default to the new sof + driver instead. diff --git a/sound/hda/intel-dsp-config.c b/sound/hda/intel-dsp-config.c --- a/sound/hda/intel-dsp-config.c +++ b/sound/hda/intel-dsp-config.c +/* should we default to sof or sst for byt/cht ? */ +#if is_enabled(config_snd_intel_byt_prefer_sof) || \ + !is_enabled(config_snd_sst_atom_hifi2_platform_acpi) +#define flag_sst_or_sof_byt flag_sof +#else +#define flag_sst_or_sof_byt flag_sst +#endif + +#if is_enabled(config_snd_sst_atom_hifi2_platform_acpi) || \ + is_enabled(config_snd_soc_sof_baytrail) -#if is_enabled(config_snd_sst_atom_hifi2_platform_acpi) - { - .flags = flag_sst, - .acpi_hid = "80860f28", - }, -#endif -#if is_enabled(config_snd_soc_sof_baytrail) - .flags = flag_sof, + .flags = flag_sst_or_sof_byt, -#endif -#if is_enabled(config_snd_sst_atom_hifi2_platform_acpi) - { - .flags = flag_sst, - .acpi_hid = "808622a8", - }, -#endif -#if is_enabled(config_snd_soc_sof_baytrail) - .flags = flag_sof, + .flags = flag_sst_or_sof_byt,
|
Audio
|
5427c7d6296ee574037c4a6649ac45a9474d1f13
|
hans de goede
|
sound
|
hda
| |
alsa: hdsp: hardware output loopback
|
output loopback is a feature where you can record what you hear. the hdsp series of the rme interfaces provides this functionality at the hardware level and this patch exposes controls to enable or disable it per output (playback) channel.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
hardware output loopback
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hdsp']
|
['c']
| 1
| 73
| 1
|
--- diff --git a/sound/pci/rme9652/hdsp.c b/sound/pci/rme9652/hdsp.c --- a/sound/pci/rme9652/hdsp.c +++ b/sound/pci/rme9652/hdsp.c + u32 io_loopback; /* output loopback channel states*/ + +static bool hdsp_loopback_get(struct hdsp *const hdsp, const u8 channel) +{ + return hdsp->io_loopback & (1 << channel); +} + +static int hdsp_loopback_set(struct hdsp *const hdsp, const u8 channel, const bool enable) +{ + if (hdsp_loopback_get(hdsp, channel) == enable) + return 0; + + hdsp->io_loopback ^= (1 << channel); + + hdsp_write(hdsp, hdsp_inputenable + (4 * (hdsp->max_channels + channel)), enable); + + return 1; +} + +static int snd_hdsp_loopback_get(struct snd_kcontrol *const kcontrol, + struct snd_ctl_elem_value *const ucontrol) +{ + struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol); + const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id); + + if (channel >= hdsp->max_channels) + return -enoent; + + ucontrol->value.integer.value[0] = hdsp_loopback_get(hdsp, channel); + + return 0; +} + +static int snd_hdsp_loopback_put(struct snd_kcontrol *const kcontrol, + struct snd_ctl_elem_value *const ucontrol) +{ + struct hdsp *const hdsp = snd_kcontrol_chip(kcontrol); + const u8 channel = snd_ctl_get_ioff(kcontrol, &ucontrol->id); + const bool enable = ucontrol->value.integer.value[0] & 1; + + if (channel >= hdsp->max_channels) + return -enoent; + + return hdsp_loopback_set(hdsp, channel, enable); +} + +static struct snd_kcontrol_new snd_hdsp_loopback_control = { + .iface = sndrv_ctl_elem_iface_hwdep, + .name = "output loopback", + .access = sndrv_ctl_elem_access_readwrite, + .info = snd_ctl_boolean_mono_info, + .get = snd_hdsp_loopback_get, + .put = snd_hdsp_loopback_put +}; + + /* output loopback controls for h9632 cards */ + if (hdsp->io_type == h9632) { + snd_hdsp_loopback_control.count = hdsp->max_channels; + kctl = snd_ctl_new1(&snd_hdsp_loopback_control, hdsp); + if (kctl == null) + return -enomem; + err = snd_ctl_add(card, kctl); + if (err < 0) + return err; + } + - int status, aebi_channels, aebo_channels; + int status, aebi_channels, aebo_channels, i; + /* disable loopback of output channels, as the set function + * only sets on a change we fake all bits (channels) as enabled. + */ + hdsp->io_loopback = 0xffffffff; + for (i = 0; i < hdsp->max_channels; ++i) + hdsp_loopback_set(hdsp, i, false);
|
Audio
|
da2a040ee7cfe1dd57d5bec7906cb979c5787a86
|
jasmin fazlic
|
sound
|
pci
|
rme9652
|
alsa: jack: implement software jack injection via debugfs
|
this change adds audio jack injection feature through debugfs, with this feature, we could validate alsa userspace changes by injecting plugin or plugout events to the non-phantom audio jacks.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement software jack injection via debugfs
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['jack']
|
['h', 'kconfig', 'c', 'rst']
| 8
| 512
| 4
|
--- diff --git a/documentation/sound/designs/index.rst b/documentation/sound/designs/index.rst --- a/documentation/sound/designs/index.rst +++ b/documentation/sound/designs/index.rst + jack-injection diff --git a/documentation/sound/designs/jack-injection.rst b/documentation/sound/designs/jack-injection.rst --- /dev/null +++ b/documentation/sound/designs/jack-injection.rst +============================ +alsa jack software injection +============================ + +simple introduction on jack injection +===================================== + +here jack injection means users could inject plugin or plugout events +to the audio jacks through debugfs interface, it is helpful to +validate alsa userspace changes. for example, we change the audio +profile switching code in the pulseaudio, and we want to verify if the +change works as expected and if the change introduce the regression, +in this case, we could inject plugin or plugout events to an audio +jack or to some audio jacks, we don't need to physically access the +machine and plug/unplug physical devices to the audio jack. + +in this design, an audio jack doesn't equal to a physical audio jack. +sometimes a physical audio jack contains multi functions, and the +alsa driver creates multi ''jack_kctl'' for a ''snd_jack'', here the +''snd_jack'' represents a physical audio jack and the ''jack_kctl'' +represents a function, for example a physical jack has two functions: +headphone and mic_in, the alsa asoc driver will build 2 ''jack_kctl'' +for this jack. the jack injection is implemented based on the +''jack_kctl'' instead of ''snd_jack''. + +to inject events to audio jacks, we need to enable the jack injection +via ''sw_inject_enable'' first, once it is enabled, this jack will not +change the state by hardware events anymore, we could inject plugin or +plugout events via ''jackin_inject'' and check the jack state via +''status'', after we finish our test, we need to disable the jack +injection via ''sw_inject_enable'' too, once it is disabled, the jack +state will be restored according to the last reported hardware events +and will change by future hardware events. + +the layout of jack injection interface +====================================== + +if users enable the snd_jack_injection_debug in the kernel, the audio +jack injection interface will be created as below: +:: + + $debugfs_mount_dir/sound + |-- card0 + |-- |-- hdmi_dp_pcm_10_jack + |-- |-- |-- jackin_inject + |-- |-- |-- kctl_id + |-- |-- |-- mask_bits + |-- |-- |-- status + |-- |-- |-- sw_inject_enable + |-- |-- |-- type + ... + |-- |-- hdmi_dp_pcm_9_jack + |-- |-- jackin_inject + |-- |-- kctl_id + |-- |-- mask_bits + |-- |-- status + |-- |-- sw_inject_enable + |-- |-- type + |-- card1 + |-- hdmi_dp_pcm_5_jack + |-- |-- jackin_inject + |-- |-- kctl_id + |-- |-- mask_bits + |-- |-- status + |-- |-- sw_inject_enable + |-- |-- type + ... + |-- headphone_jack + |-- |-- jackin_inject + |-- |-- kctl_id + |-- |-- mask_bits + |-- |-- status + |-- |-- sw_inject_enable + |-- |-- type + |-- headset_mic_jack + |-- jackin_inject + |-- kctl_id + |-- mask_bits + |-- status + |-- sw_inject_enable + |-- type + +the explanation of the nodes +====================================== + +kctl_id + read-only, get jack_kctl->kctl's id + :: + + sound/card1/headphone_jack# cat kctl_id + headphone jack + +mask_bits + read-only, get jack_kctl's supported events mask_bits + :: + + sound/card1/headphone_jack# cat mask_bits + 0x0001 headphone(0x0001) + +status + read-only, get jack_kctl's current status + +- headphone unplugged: + + :: + + sound/card1/headphone_jack# cat status + unplugged + +- headphone plugged: + + :: + + sound/card1/headphone_jack# cat status + plugged + +type + read-only, get snd_jack's supported events from type (all supported events on the physical audio jack) + :: + + sound/card1/headphone_jack# cat type + 0x7803 headphone(0x0001) microphone(0x0002) btn_3(0x0800) btn_2(0x1000) btn_1(0x2000) btn_0(0x4000) + +sw_inject_enable + read-write, enable or disable injection + +- injection disabled: + + :: + + sound/card1/headphone_jack# cat sw_inject_enable + jack: headphone jack inject enabled: 0 + +- injection enabled: + + :: + + sound/card1/headphone_jack# cat sw_inject_enable + jack: headphone jack inject enabled: 1 + +- to enable jack injection: + + :: + + sound/card1/headphone_jack# echo 1 > sw_inject_enable + +- to disable jack injection: + + :: + + sound/card1/headphone_jack# echo 0 > sw_inject_enable + +jackin_inject + write-only, inject plugin or plugout + +- to inject plugin: + + :: + + sound/card1/headphone_jack# echo 1 > jackin_inject + +- to inject plugout: + + :: + + sound/card1/headphone_jack# echo 0 > jackin_inject diff --git a/include/sound/core.h b/include/sound/core.h --- a/include/sound/core.h +++ b/include/sound/core.h +#ifdef config_snd_debug + struct dentry *debugfs_root; /* debugfs root for card */ +#endif +#ifdef config_snd_debug +extern struct dentry *sound_debugfs_root; +#endif diff --git a/include/sound/jack.h b/include/sound/jack.h --- a/include/sound/jack.h +++ b/include/sound/jack.h + int hw_status_cache; diff --git a/sound/core/kconfig b/sound/core/kconfig --- a/sound/core/kconfig +++ b/sound/core/kconfig +config snd_jack_injection_debug + bool "sound jack injection interface via debugfs" + depends on snd_jack && snd_debug && debug_fs + help + this option can be used to enable or disable sound jack + software injection. + say y if you are debugging via jack injection interface. + if unsure select "n". + diff --git a/sound/core/init.c b/sound/core/init.c --- a/sound/core/init.c +++ b/sound/core/init.c +#include <linux/debugfs.h> +#ifdef config_snd_debug + char name[8]; +#endif + +#ifdef config_snd_debug + sprintf(name, "card%d", idx); + card->debugfs_root = debugfs_create_dir(name, sound_debugfs_root); +#endif + + +#ifdef config_snd_debug + debugfs_remove(card->debugfs_root); + card->debugfs_root = null; +#endif + diff --git a/sound/core/jack.c b/sound/core/jack.c --- a/sound/core/jack.c +++ b/sound/core/jack.c +#include <linux/ctype.h> +#include <linux/mm.h> +#include <linux/debugfs.h> + struct snd_jack *jack; /* pointer to struct snd_jack */ + bool sw_inject_enable; /* allow to inject plug event via debugfs */ +#ifdef config_snd_jack_injection_debug + struct dentry *jack_debugfs_root; /* jack_kctl debugfs root */ +#endif +#ifdef config_snd_jack_injection_debug +static void snd_jack_inject_report(struct snd_jack_kctl *jack_kctl, int status) +{ + struct snd_jack *jack; +#ifdef config_snd_jack_input_dev + int i; +#endif + if (!jack_kctl) + return; + + jack = jack_kctl->jack; + + if (jack_kctl->sw_inject_enable) + snd_kctl_jack_report(jack->card, jack_kctl->kctl, + status & jack_kctl->mask_bits); + +#ifdef config_snd_jack_input_dev + if (!jack->input_dev) + return; + + for (i = 0; i < array_size(jack->key); i++) { + int testbit = ((snd_jack_btn_0 >> i) & jack_kctl->mask_bits); + + if (jack->type & testbit) + input_report_key(jack->input_dev, jack->key[i], + status & testbit); + } + + for (i = 0; i < array_size(jack_switch_types); i++) { + int testbit = ((1 << i) & jack_kctl->mask_bits); + + if (jack->type & testbit) + input_report_switch(jack->input_dev, + jack_switch_types[i], + status & testbit); + } + + input_sync(jack->input_dev); +#endif /* config_snd_jack_input_dev */ +} + +static ssize_t sw_inject_enable_read(struct file *file, + char __user *to, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + int len, ret; + char buf[128]; + + len = scnprintf(buf, sizeof(buf), "%s: %s %s: %i ", "jack", jack_kctl->kctl->id.name, + "inject enabled", jack_kctl->sw_inject_enable); + ret = simple_read_from_buffer(to, count, ppos, buf, len); + + return ret; +} + +static ssize_t sw_inject_enable_write(struct file *file, + const char __user *from, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + int ret, err; + unsigned long enable; + char buf[8] = { 0 }; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); + err = kstrtoul(buf, 0, &enable); + if (err) + return err; + + if (jack_kctl->sw_inject_enable == (!!enable)) + return ret; + + jack_kctl->sw_inject_enable = !!enable; + + if (!jack_kctl->sw_inject_enable) + snd_jack_report(jack_kctl->jack, jack_kctl->jack->hw_status_cache); + + return ret; +} + +static ssize_t jackin_inject_write(struct file *file, + const char __user *from, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + int ret, err; + unsigned long enable; + char buf[8] = { 0 }; + + if (!jack_kctl->sw_inject_enable) + return -einval; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, from, count); + err = kstrtoul(buf, 0, &enable); + if (err) + return err; + + snd_jack_inject_report(jack_kctl, !!enable ? jack_kctl->mask_bits : 0); + + return ret; +} + +static ssize_t jack_kctl_id_read(struct file *file, + char __user *to, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + char buf[64]; + int len, ret; + + len = scnprintf(buf, sizeof(buf), "%s ", jack_kctl->kctl->id.name); + ret = simple_read_from_buffer(to, count, ppos, buf, len); + + return ret; +} + +/* the bit definition is aligned with snd_jack_types in jack.h */ +static const char * const jack_events_name[] = { + "headphone(0x0001)", "microphone(0x0002)", "lineout(0x0004)", + "mechanical(0x0008)", "videoout(0x0010)", "linein(0x0020)", + "", "", "", "btn_5(0x0200)", "btn_4(0x0400)", "btn_3(0x0800)", + "btn_2(0x1000)", "btn_1(0x2000)", "btn_0(0x4000)", "", +}; + +/* the recommended buffer size is 256 */ +static int parse_mask_bits(unsigned int mask_bits, char *buf, size_t buf_size) +{ + int i; + + scnprintf(buf, buf_size, "0x%04x", mask_bits); + + for (i = 0; i < array_size(jack_events_name); i++) + if (mask_bits & (1 << i)) { + strlcat(buf, " ", buf_size); + strlcat(buf, jack_events_name[i], buf_size); + } + strlcat(buf, " ", buf_size); + + return strlen(buf); +} + +static ssize_t jack_kctl_mask_bits_read(struct file *file, + char __user *to, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + char buf[256]; + int len, ret; + + len = parse_mask_bits(jack_kctl->mask_bits, buf, sizeof(buf)); + ret = simple_read_from_buffer(to, count, ppos, buf, len); + + return ret; +} + +static ssize_t jack_kctl_status_read(struct file *file, + char __user *to, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + char buf[16]; + int len, ret; + + len = scnprintf(buf, sizeof(buf), "%s ", jack_kctl->kctl->private_value ? + "plugged" : "unplugged"); + ret = simple_read_from_buffer(to, count, ppos, buf, len); + + return ret; +} + +#ifdef config_snd_jack_input_dev +static ssize_t jack_type_read(struct file *file, + char __user *to, size_t count, loff_t *ppos) +{ + struct snd_jack_kctl *jack_kctl = file->private_data; + char buf[256]; + int len, ret; + + len = parse_mask_bits(jack_kctl->jack->type, buf, sizeof(buf)); + ret = simple_read_from_buffer(to, count, ppos, buf, len); + + return ret; +} + +static const struct file_operations jack_type_fops = { + .open = simple_open, + .read = jack_type_read, + .llseek = default_llseek, +}; +#endif + +static const struct file_operations sw_inject_enable_fops = { + .open = simple_open, + .read = sw_inject_enable_read, + .write = sw_inject_enable_write, + .llseek = default_llseek, +}; + +static const struct file_operations jackin_inject_fops = { + .open = simple_open, + .write = jackin_inject_write, + .llseek = default_llseek, +}; + +static const struct file_operations jack_kctl_id_fops = { + .open = simple_open, + .read = jack_kctl_id_read, + .llseek = default_llseek, +}; + +static const struct file_operations jack_kctl_mask_bits_fops = { + .open = simple_open, + .read = jack_kctl_mask_bits_read, + .llseek = default_llseek, +}; + +static const struct file_operations jack_kctl_status_fops = { + .open = simple_open, + .read = jack_kctl_status_read, + .llseek = default_llseek, +}; + +static int snd_jack_debugfs_add_inject_node(struct snd_jack *jack, + struct snd_jack_kctl *jack_kctl) +{ + char *tname; + int i; + + /* don't create injection interface for phantom jacks */ + if (strstr(jack_kctl->kctl->id.name, "phantom")) + return 0; + + tname = kstrdup(jack_kctl->kctl->id.name, gfp_kernel); + if (!tname) + return -enomem; + + /* replace the chars which are not suitable for folder's name with _ */ + for (i = 0; tname[i]; i++) + if (!isalnum(tname[i])) + tname[i] = '_'; + + jack_kctl->jack_debugfs_root = debugfs_create_dir(tname, jack->card->debugfs_root); + kfree(tname); + + debugfs_create_file("sw_inject_enable", 0644, jack_kctl->jack_debugfs_root, jack_kctl, + &sw_inject_enable_fops); + + debugfs_create_file("jackin_inject", 0200, jack_kctl->jack_debugfs_root, jack_kctl, + &jackin_inject_fops); + + debugfs_create_file("kctl_id", 0444, jack_kctl->jack_debugfs_root, jack_kctl, + &jack_kctl_id_fops); + + debugfs_create_file("mask_bits", 0444, jack_kctl->jack_debugfs_root, jack_kctl, + &jack_kctl_mask_bits_fops); + + debugfs_create_file("status", 0444, jack_kctl->jack_debugfs_root, jack_kctl, + &jack_kctl_status_fops); + +#ifdef config_snd_jack_input_dev + debugfs_create_file("type", 0444, jack_kctl->jack_debugfs_root, jack_kctl, + &jack_type_fops); +#endif + return 0; +} + +static void snd_jack_debugfs_clear_inject_node(struct snd_jack_kctl *jack_kctl) +{ + debugfs_remove(jack_kctl->jack_debugfs_root); + jack_kctl->jack_debugfs_root = null; +} +#else /* config_snd_jack_injection_debug */ +static int snd_jack_debugfs_add_inject_node(struct snd_jack *jack, + struct snd_jack_kctl *jack_kctl) +{ + return 0; +} + +static void snd_jack_debugfs_clear_inject_node(struct snd_jack_kctl *jack_kctl) +{ +} +#endif /* config_snd_jack_injection_debug */ + + snd_jack_debugfs_clear_inject_node(jack_kctl); + jack_kctl->jack = jack; + snd_jack_debugfs_add_inject_node(jack, jack_kctl); + unsigned int mask_bits = 0; + jack->hw_status_cache = status; + - snd_kctl_jack_report(jack->card, jack_kctl->kctl, - status & jack_kctl->mask_bits); + if (jack_kctl->sw_inject_enable) + mask_bits |= jack_kctl->mask_bits; + else + snd_kctl_jack_report(jack->card, jack_kctl->kctl, + status & jack_kctl->mask_bits); - int testbit = snd_jack_btn_0 >> i; + int testbit = ((snd_jack_btn_0 >> i) & ~mask_bits); - int testbit = 1 << i; + int testbit = ((1 << i) & ~mask_bits); + diff --git a/sound/core/sound.c b/sound/core/sound.c --- a/sound/core/sound.c +++ b/sound/core/sound.c +#include <linux/debugfs.h> +#ifdef config_snd_debug +struct dentry *sound_debugfs_root; +export_symbol_gpl(sound_debugfs_root); +#endif + + +#ifdef config_snd_debug + sound_debugfs_root = debugfs_create_dir("sound", null); +#endif +#ifdef config_snd_debug + debugfs_remove(sound_debugfs_root); +#endif
|
Audio
|
2d670ea2bd53a9792f453bb5b97cb8ef695988ff
|
hui wang
|
documentation
|
sound
|
designs
|
alsa: usb-audio: add support for pioneer djm-750
|
this adds the pioneer dj djm-750 to the quirks table and ensures skip_pioneer_sync_ep() is (also) called: this device uses the vendor id of 0x08e4 (i'm not sure why they use multiple vendor ids but many just like to be awkward it seems).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for pioneer djm-750
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['usb-audio']
|
['h', 'c']
| 2
| 62
| 1
|
--- diff --git a/sound/usb/implicit.c b/sound/usb/implicit.c --- a/sound/usb/implicit.c +++ b/sound/usb/implicit.c - usb_id_vendor(chip->usb_id) == 0x2b73 /* pioneer */) { + (usb_id_vendor(chip->usb_id) == 0x2b73 || /* pioneer */ + usb_id_vendor(chip->usb_id) == 0x08e4 /* pioneer */)) { diff --git a/sound/usb/quirks-table.h b/sound/usb/quirks-table.h --- a/sound/usb/quirks-table.h +++ b/sound/usb/quirks-table.h +{ + /* + * pioneer dj djm-750 + * 8 channels playback & 8 channels capture @ 44.1/48/96khz s24le + */ + usb_device_vendor_spec(0x08e4, 0x017f), + .driver_info = (unsigned long) &(const struct snd_usb_audio_quirk) { + .ifnum = quirk_any_interface, + .type = quirk_composite, + .data = (const struct snd_usb_audio_quirk[]) { + { + .ifnum = 0, + .type = quirk_audio_fixed_endpoint, + .data = &(const struct audioformat) { + .formats = sndrv_pcm_fmtbit_s24_3le, + .channels = 8, + .iface = 0, + .altsetting = 1, + .altset_idx = 1, + .endpoint = 0x05, + .ep_attr = usb_endpoint_xfer_isoc| + usb_endpoint_sync_async, + .rates = sndrv_pcm_rate_44100| + sndrv_pcm_rate_48000| + sndrv_pcm_rate_96000, + .rate_min = 44100, + .rate_max = 96000, + .nr_rates = 3, + .rate_table = (unsigned int[]) { 44100, 48000, 96000 } + } + }, + { + .ifnum = 0, + .type = quirk_audio_fixed_endpoint, + .data = &(const struct audioformat) { + .formats = sndrv_pcm_fmtbit_s24_3le, + .channels = 8, + .iface = 0, + .altsetting = 1, + .altset_idx = 1, + .endpoint = 0x86, + .ep_idx = 1, + .ep_attr = usb_endpoint_xfer_isoc| + usb_endpoint_sync_async| + usb_endpoint_usage_implicit_fb, + .rates = sndrv_pcm_rate_44100| + sndrv_pcm_rate_48000| + sndrv_pcm_rate_96000, + .rate_min = 44100, + .rate_max = 96000, + .nr_rates = 3, + .rate_table = (unsigned int[]) { 44100, 48000, 96000 } + } + }, + { + .ifnum = -1 + } + } + } +},
|
Audio
|
b952ac76a20bc0b23cd7e22de19fb407713238a3
|
olivia mackintosh
|
sound
|
usb
| |
asoc: intel: kmb: support iec958 encoded pcm format
|
support alsa iec958 plugin for keembay i2s driver. bit manipulation needed as iec958 format supported by adv7511 hdmi chip is not compatible with the alsa iec958 plugin format.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support iec958 encoded pcm format
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'intel', 'kmb']
|
['h', 'c']
| 2
| 73
| 1
|
--- diff --git a/sound/soc/intel/keembay/kmb_platform.c b/sound/soc/intel/keembay/kmb_platform.c --- a/sound/soc/intel/keembay/kmb_platform.c +++ b/sound/soc/intel/keembay/kmb_platform.c +#include <linux/bitrev.h> - sndrv_pcm_fmtbit_s32_le, + sndrv_pcm_fmtbit_s32_le | + sndrv_pcm_fmtbit_iec958_subframe_le, +/* + * convert to adv7511 hdmi hardware format. + * adv7511 hdmi chip need parity bit replaced by block start bit and + * with the preamble bits left out. + * alsa iec958 subframe format: + * bit 0-3 = preamble (0x8 = block start) + * 4-7 = aux (=0) + * 8-27 = audio data (without aux if 24bit sample) + * 28 = validity + * 29 = user data + * 30 = channel status + * 31 = parity + * + * adv7511 iec958 subframe format: + * bit 0-23 = audio data + * 24 = validity + * 25 = user data + * 26 = channel status + * 27 = block start + * 28-31 = 0 + * msb to lsb bit reverse by software as hardware not supporting it. + */ +static void hdmi_reformat_iec958(struct snd_pcm_runtime *runtime, + struct kmb_i2s_info *kmb_i2s, + unsigned int tx_ptr) +{ + u32(*buf)[2] = (void *)runtime->dma_area; + unsigned long temp; + u32 i, j, sample; + + for (i = 0; i < kmb_i2s->fifo_th; i++) { + j = 0; + do { + temp = buf[tx_ptr][j]; + /* replace parity with block start*/ + assign_bit(31, &temp, (bit(3) & temp)); + sample = bitrev32(temp); + buf[tx_ptr][j] = sample << 4; + j++; + } while (j < 2); + tx_ptr++; + } +} + + if (kmb_i2s->iec958_fmt) + hdmi_reformat_iec958(runtime, kmb_i2s, tx_ptr); + kmb_i2s->iec958_fmt = false; + case sndrv_pcm_format_iec958_subframe_le: + kmb_i2s->iec958_fmt = true; + fallthrough; +static struct snd_soc_dai_driver intel_kmb_hdmi_dai[] = { + { + .name = "intel_kmb_hdmi_i2s", + .playback = { + .channels_min = 2, + .channels_max = 2, + .rates = sndrv_pcm_rate_48000, + .rate_min = 48000, + .rate_max = 48000, + .formats = (sndrv_pcm_fmtbit_s16_le | + sndrv_pcm_fmtbit_s24_le | + sndrv_pcm_fmtbit_iec958_subframe_le), + }, + .ops = &kmb_dai_ops, + .probe = kmb_probe, + }, +}; + + { .compatible = "intel,keembay-hdmi-i2s", .data = &intel_kmb_hdmi_dai}, diff --git a/sound/soc/intel/keembay/kmb_platform.h b/sound/soc/intel/keembay/kmb_platform.h --- a/sound/soc/intel/keembay/kmb_platform.h +++ b/sound/soc/intel/keembay/kmb_platform.h + bool iec958_fmt;
|
Audio
|
1c5f6e0714c16e3ad8732e49e07082772dcc6f87
|
sia jee heng
|
sound
|
soc
|
intel, keembay
|
asoc: intel: bytcr_wm5102: add machine driver for byt/wm5102
|
add a new asoc machine driver for intel baytrail platforms with a wolfson microelectronics wm5102 codec.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add machine driver for byt/wm5102
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'intel', 'bytcr_wm5102']
|
['kconfig', 'c', 'makefile']
| 4
| 495
| 0
|
--- diff --git a/sound/soc/intel/boards/kconfig b/sound/soc/intel/boards/kconfig --- a/sound/soc/intel/boards/kconfig +++ b/sound/soc/intel/boards/kconfig +config snd_soc_intel_bytcr_wm5102_mach + tristate "baytrail and baytrail-cr with wm5102 codec" + depends on mfd_arizona && mfd_wm5102 && spi_master && acpi + depends on x86_intel_lpss || compile_test + select snd_soc_acpi + select snd_soc_wm5102 + help + this adds support for asoc machine driver for intel(r) baytrail and baytrail-cr + platforms with wm5102 audio codec. + say y if you have such a device. + if unsure select "n". + diff --git a/sound/soc/intel/boards/makefile b/sound/soc/intel/boards/makefile --- a/sound/soc/intel/boards/makefile +++ b/sound/soc/intel/boards/makefile +snd-soc-sst-bytcr-wm5102-objs := bytcr_wm5102.o +obj-$(config_snd_soc_intel_bytcr_wm5102_mach) += snd-soc-sst-bytcr-wm5102.o diff --git a/sound/soc/intel/boards/bytcr_wm5102.c b/sound/soc/intel/boards/bytcr_wm5102.c --- /dev/null +++ b/sound/soc/intel/boards/bytcr_wm5102.c +// spdx-license-identifier: gpl-2.0-only +/* + * bytcr_wm5102.c - asoc machine driver for intel baytrail platforms with a + * wolfson microelectronics wm5102 codec + * + * copyright (c) 2020 hans de goede <hdegoede@redhat.com> + * loosely based on bytcr_rt5640.c which is: + * copyright (c) 2014-2020 intel corp + * author: subhransu s. prusty <subhransu.s.prusty@intel.com> + */ + +#include <linux/acpi.h> +#include <linux/clk.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/moduleparam.h> +#include <linux/platform_device.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-acpi.h> +#include "../../codecs/wm5102.h" +#include "../atom/sst-atom-controls.h" + +#define mclk_freq 25000000 + +#define wm5102_max_sysclk_4k 49152000 /* max sysclk for 4k family */ +#define wm5102_max_sysclk_11025 45158400 /* max sysclk for 11.025k family */ + +struct byt_wm5102_private { + struct clk *mclk; + struct gpio_desc *spkvdd_en_gpio; +}; + +static int byt_wm5102_spkvdd_power_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_card *card = w->dapm->card; + struct byt_wm5102_private *priv = snd_soc_card_get_drvdata(card); + + gpiod_set_value_cansleep(priv->spkvdd_en_gpio, + !!snd_soc_dapm_event_on(event)); + + return 0; +} + +static int byt_wm5102_prepare_and_enable_pll1(struct snd_soc_dai *codec_dai, int rate) +{ + struct snd_soc_component *codec_component = codec_dai->component; + int sr_mult = ((rate % 4000) == 0) ? + (wm5102_max_sysclk_4k / rate) : + (wm5102_max_sysclk_11025 / rate); + int ret; + + /* reset fll1 */ + snd_soc_dai_set_pll(codec_dai, wm5102_fll1_refclk, arizona_fll_src_none, 0, 0); + snd_soc_dai_set_pll(codec_dai, wm5102_fll1, arizona_fll_src_none, 0, 0); + + /* configure the fll1 pll before selecting it */ + ret = snd_soc_dai_set_pll(codec_dai, wm5102_fll1, arizona_clk_src_mclk1, + mclk_freq, rate * sr_mult); + if (ret) { + dev_err(codec_component->dev, "error setting pll: %d ", ret); + return ret; + } + + ret = snd_soc_component_set_sysclk(codec_component, arizona_clk_sysclk, + arizona_clk_src_fll1, rate * sr_mult, + snd_soc_clock_in); + if (ret) { + dev_err(codec_component->dev, "error setting sysclk: %d ", ret); + return ret; + } + + ret = snd_soc_dai_set_sysclk(codec_dai, arizona_clk_sysclk, + rate * 512, snd_soc_clock_in); + if (ret) { + dev_err(codec_component->dev, "error setting clock: %d ", ret); + return ret; + } + + return 0; +} + +static int platform_clock_control(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *k, int event) +{ + struct snd_soc_dapm_context *dapm = w->dapm; + struct snd_soc_card *card = dapm->card; + struct snd_soc_dai *codec_dai; + struct byt_wm5102_private *priv = snd_soc_card_get_drvdata(card); + int ret; + + codec_dai = snd_soc_card_get_codec_dai(card, "wm5102-aif1"); + if (!codec_dai) { + dev_err(card->dev, "error codec dai not found "); + return -eio; + } + + if (snd_soc_dapm_event_on(event)) { + ret = clk_prepare_enable(priv->mclk); + if (ret) { + dev_err(card->dev, "error enabling mclk: %d ", ret); + return ret; + } + ret = byt_wm5102_prepare_and_enable_pll1(codec_dai, 48000); + if (ret) { + dev_err(card->dev, "error setting codec sysclk: %d ", ret); + return ret; + } + } else { + /* + * the wm5102 has a separate 32khz clock for jack-detect + * so we can disable the pll, followed by disabling the + * platform clock which is the source-clock for the pll. + */ + snd_soc_dai_set_pll(codec_dai, wm5102_fll1, arizona_fll_src_none, 0, 0); + clk_disable_unprepare(priv->mclk); + } + + return 0; +} + +static const struct snd_soc_dapm_widget byt_wm5102_widgets[] = { + snd_soc_dapm_hp("headphone", null), + snd_soc_dapm_mic("headset mic", null), + snd_soc_dapm_mic("internal mic", null), + snd_soc_dapm_spk("speaker", null), + snd_soc_dapm_supply("platform clock", snd_soc_nopm, 0, 0, + platform_clock_control, snd_soc_dapm_pre_pmu | + snd_soc_dapm_post_pmd), + snd_soc_dapm_supply("speaker vdd", snd_soc_nopm, 0, 0, + byt_wm5102_spkvdd_power_event, + snd_soc_dapm_pre_pmd | snd_soc_dapm_post_pmu), +}; + +static const struct snd_soc_dapm_route byt_wm5102_audio_map[] = { + {"headphone", null, "platform clock"}, + {"headset mic", null, "platform clock"}, + {"internal mic", null, "platform clock"}, + {"speaker", null, "platform clock"}, + + {"speaker", null, "spkoutlp"}, + {"speaker", null, "spkoutln"}, + {"speaker", null, "spkoutrp"}, + {"speaker", null, "spkoutrn"}, + {"speaker", null, "speaker vdd"}, + + {"headphone", null, "hpout1l"}, + {"headphone", null, "hpout1r"}, + + {"internal mic", null, "micbias3"}, + {"in3l", null, "internal mic"}, + + /* + * the headset mix uses micbias1 or 2 depending on if a ctia/omtp headset + * is connected, as the micbias is applied after the ctia/omtp cross-switch. + */ + {"headset mic", null, "micbias1"}, + {"headset mic", null, "micbias2"}, + {"in1l", null, "headset mic"}, + + {"aif1 playback", null, "ssp0 tx"}, + {"ssp0 tx", null, "modem_out"}, + + {"modem_in", null, "ssp0 rx"}, + {"ssp0 rx", null, "aif1 capture"}, +}; + +static const struct snd_kcontrol_new byt_wm5102_controls[] = { + soc_dapm_pin_switch("headphone"), + soc_dapm_pin_switch("headset mic"), + soc_dapm_pin_switch("internal mic"), + soc_dapm_pin_switch("speaker"), +}; + +static int byt_wm5102_init(struct snd_soc_pcm_runtime *runtime) +{ + struct snd_soc_card *card = runtime->card; + struct byt_wm5102_private *priv = snd_soc_card_get_drvdata(card); + int ret; + + card->dapm.idle_bias_off = true; + + ret = snd_soc_add_card_controls(card, byt_wm5102_controls, + array_size(byt_wm5102_controls)); + if (ret) { + dev_err(card->dev, "error adding card controls: %d ", ret); + return ret; + } + + /* + * the firmware might enable the clock at boot (this information + * may or may not be reflected in the enable clock register). + * to change the rate we must disable the clock first to cover these + * cases. due to common clock framework restrictions that do not allow + * to disable a clock that has not been enabled, we need to enable + * the clock first. + */ + ret = clk_prepare_enable(priv->mclk); + if (!ret) + clk_disable_unprepare(priv->mclk); + + ret = clk_set_rate(priv->mclk, mclk_freq); + if (ret) { + dev_err(card->dev, "error setting mclk rate: %d ", ret); + return ret; + } + + return 0; +} + +static const struct snd_soc_pcm_stream byt_wm5102_dai_params = { + .formats = sndrv_pcm_fmtbit_s16_le, + .rate_min = 48000, + .rate_max = 48000, + .channels_min = 2, + .channels_max = 2, +}; + +static int byt_wm5102_codec_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params) +{ + struct snd_interval *rate = hw_param_interval(params, + sndrv_pcm_hw_param_rate); + struct snd_interval *channels = hw_param_interval(params, + sndrv_pcm_hw_param_channels); + int ret; + + /* the dsp will covert the fe rate to 48k, stereo */ + rate->min = 48000; + rate->max = 48000; + channels->min = 2; + channels->max = 2; + + /* set ssp0 to 16-bit */ + params_set_format(params, sndrv_pcm_format_s16_le); + + /* + * default mode for ssp configuration is tdm 4 slot, override config + * with explicit setting to i2s 2ch 16-bit. the word length is set with + * dai_set_tdm_slot() since there is no other api exposed + */ + ret = snd_soc_dai_set_fmt(asoc_rtd_to_cpu(rtd, 0), + snd_soc_daifmt_i2s | + snd_soc_daifmt_nb_nf | + snd_soc_daifmt_cbs_cfs); + if (ret) { + dev_err(rtd->dev, "error setting format to i2s: %d ", ret); + return ret; + } + + ret = snd_soc_dai_set_tdm_slot(asoc_rtd_to_cpu(rtd, 0), 0x3, 0x3, 2, 16); + if (ret) { + dev_err(rtd->dev, "error setting i2s config: %d ", ret); + return ret; + } + + return 0; +} + +static int byt_wm5102_aif1_startup(struct snd_pcm_substream *substream) +{ + return snd_pcm_hw_constraint_single(substream->runtime, + sndrv_pcm_hw_param_rate, 48000); +} + +static const struct snd_soc_ops byt_wm5102_aif1_ops = { + .startup = byt_wm5102_aif1_startup, +}; + +snd_soc_dailink_def(dummy, + dailink_comp_array(comp_dummy())); + +snd_soc_dailink_def(media, + dailink_comp_array(comp_cpu("media-cpu-dai"))); + +snd_soc_dailink_def(deepbuffer, + dailink_comp_array(comp_cpu("deepbuffer-cpu-dai"))); + +snd_soc_dailink_def(ssp0_port, + dailink_comp_array(comp_cpu("ssp0-port"))); + +snd_soc_dailink_def(ssp0_codec, + dailink_comp_array(comp_codec( + /* + * note there is no need to overwrite the codec-name as is done in + * other bytcr machine drivers, because the codec is a mfd child-dev. + */ + "wm5102-codec", + "wm5102-aif1"))); + +snd_soc_dailink_def(platform, + dailink_comp_array(comp_platform("sst-mfld-platform"))); + +static struct snd_soc_dai_link byt_wm5102_dais[] = { + [merr_dpcm_audio] = { + .name = "baytrail audio port", + .stream_name = "baytrail audio", + .nonatomic = true, + .dynamic = 1, + .dpcm_playback = 1, + .dpcm_capture = 1, + .ops = &byt_wm5102_aif1_ops, + snd_soc_dailink_reg(media, dummy, platform), + + }, + [merr_dpcm_deep_buffer] = { + .name = "deep-buffer audio port", + .stream_name = "deep-buffer audio", + .nonatomic = true, + .dynamic = 1, + .dpcm_playback = 1, + .ops = &byt_wm5102_aif1_ops, + snd_soc_dailink_reg(deepbuffer, dummy, platform), + }, + /* back ends */ + { + /* + * this must be named ssp2-codec even though this machine driver + * always uses ssp0. most machine drivers support both and dynamically + * update the dailink to point to ssp0 or ssp2, while keeping the name + * as "ssp2-codec". the sof tplg files hardcode the "ssp2-codec" even + * in the byt-foo-ssp0.tplg versions because the other machine-drivers + * use "ssp2-codec" even when ssp0 is used. + */ + .name = "ssp2-codec", + .id = 0, + .no_pcm = 1, + .dai_fmt = snd_soc_daifmt_i2s | snd_soc_daifmt_nb_nf + | snd_soc_daifmt_cbs_cfs, + .be_hw_params_fixup = byt_wm5102_codec_fixup, + .nonatomic = true, + .dpcm_playback = 1, + .dpcm_capture = 1, + .init = byt_wm5102_init, + snd_soc_dailink_reg(ssp0_port, ssp0_codec, platform), + }, +}; + +/* use space before codec name to simplify card id, and simplify driver name */ +#define sof_card_name "bytcht wm5102" /* card name will be 'sof-bytcht wm5102' */ +#define sof_driver_name "sof" + +#define card_name "bytcr-wm5102" +#define driver_name null /* card name will be used for driver name */ + +/* soc card */ +static struct snd_soc_card byt_wm5102_card = { + .owner = this_module, + .dai_link = byt_wm5102_dais, + .num_links = array_size(byt_wm5102_dais), + .dapm_widgets = byt_wm5102_widgets, + .num_dapm_widgets = array_size(byt_wm5102_widgets), + .dapm_routes = byt_wm5102_audio_map, + .num_dapm_routes = array_size(byt_wm5102_audio_map), + .fully_routed = true, +}; + +static int snd_byt_wm5102_mc_probe(struct platform_device *pdev) +{ + char codec_name[snd_acpi_i2c_id_len]; + struct device *dev = &pdev->dev; + struct byt_wm5102_private *priv; + struct snd_soc_acpi_mach *mach; + const char *platform_name; + struct acpi_device *adev; + struct device *codec_dev; + bool sof_parent; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), gfp_atomic); + if (!priv) + return -enomem; + + /* get mclk */ + priv->mclk = devm_clk_get(dev, "pmc_plt_clk_3"); + if (is_err(priv->mclk)) + return dev_err_probe(dev, ptr_err(priv->mclk), "getting pmc_plt_clk_3 "); + + /* + * get speaker vdd enable gpio: + * 1. get codec-device-name + * 2. get codec-device + * 3. get gpio from codec-device + */ + mach = dev->platform_data; + adev = acpi_dev_get_first_match_dev(mach->id, null, -1); + if (!adev) { + dev_err(dev, "error cannot find acpi-dev for codec "); + return -enoent; + } + snprintf(codec_name, sizeof(codec_name), "spi-%s", acpi_dev_name(adev)); + put_device(&adev->dev); + + codec_dev = bus_find_device_by_name(&spi_bus_type, null, codec_name); + if (!codec_dev) + return -eprobe_defer; + + /* note no devm_ here since we call gpiod_get on codec_dev rather then dev */ + priv->spkvdd_en_gpio = gpiod_get(codec_dev, "wlf,spkvdd-ena", gpiod_out_low); + put_device(codec_dev); + + if (is_err(priv->spkvdd_en_gpio)) + return dev_err_probe(dev, ptr_err(priv->spkvdd_en_gpio), "getting spkvdd-gpio "); + + /* override platform name, if required */ + byt_wm5102_card.dev = dev; + platform_name = mach->mach_params.platform; + ret = snd_soc_fixup_dai_links_platform_name(&byt_wm5102_card, platform_name); + if (ret) + goto out_put_gpio; + + /* set card and driver name and pm-ops */ + sof_parent = snd_soc_acpi_sof_parent(dev); + if (sof_parent) { + byt_wm5102_card.name = sof_card_name; + byt_wm5102_card.driver_name = sof_driver_name; + dev->driver->pm = &snd_soc_pm_ops; + } else { + byt_wm5102_card.name = card_name; + byt_wm5102_card.driver_name = driver_name; + } + + snd_soc_card_set_drvdata(&byt_wm5102_card, priv); + ret = devm_snd_soc_register_card(dev, &byt_wm5102_card); + if (ret) { + dev_err_probe(dev, ret, "registering card "); + goto out_put_gpio; + } + + platform_set_drvdata(pdev, &byt_wm5102_card); + return 0; + +out_put_gpio: + gpiod_put(priv->spkvdd_en_gpio); + return ret; +} + +static int snd_byt_wm5102_mc_remove(struct platform_device *pdev) +{ + struct snd_soc_card *card = platform_get_drvdata(pdev); + struct byt_wm5102_private *priv = snd_soc_card_get_drvdata(card); + + gpiod_put(priv->spkvdd_en_gpio); + return 0; +} + +static struct platform_driver snd_byt_wm5102_mc_driver = { + .driver = { + .name = "bytcr_wm5102", + }, + .probe = snd_byt_wm5102_mc_probe, + .remove = snd_byt_wm5102_mc_remove, +}; + +module_platform_driver(snd_byt_wm5102_mc_driver); + +module_description("asoc baytrail with wm5102 codec machine driver"); +module_author("hans de goede <hdegoede@redhat.com>"); +module_license("gpl v2"); +module_alias("platform:bytcr_wm5102"); diff --git a/sound/soc/intel/common/soc-acpi-intel-byt-match.c b/sound/soc/intel/common/soc-acpi-intel-byt-match.c --- a/sound/soc/intel/common/soc-acpi-intel-byt-match.c +++ b/sound/soc/intel/common/soc-acpi-intel-byt-match.c + { + .id = "wm510204", + .drv_name = "bytcr_wm5102", + .fw_filename = "intel/fw_sst_0f28.bin", + .board = "bytcr_wm5102", + .sof_fw_filename = "sof-byt.ri", + .sof_tplg_filename = "sof-byt-wm5102.tplg", + }, + { + .id = "wm510205", + .drv_name = "bytcr_wm5102", + .fw_filename = "intel/fw_sst_0f28.bin", + .board = "bytcr_wm5102", + .sof_fw_filename = "sof-byt.ri", + .sof_tplg_filename = "sof-byt-wm5102.tplg", + },
|
Audio
|
9a87fc1e061900e81ab13d823e85012a78849244
|
pierre louis bossart
|
sound
|
soc
|
boards, common, intel
|
asoc: sof: intel: initial support to alderlake-p
|
add pci id for the alderlake-p.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
initial support to alderlake-p
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'sof', 'intel']
|
['c']
| 1
| 5
| 1
|
--- diff --git a/sound/soc/sof/sof-pci-dev.c b/sound/soc/sof/sof-pci-dev.c --- a/sound/soc/sof/sof-pci-dev.c +++ b/sound/soc/sof/sof-pci-dev.c -#if is_enabled(config_snd_soc_sof_tigerlake) +#if is_enabled(config_snd_soc_sof_tigerlake) || is_enabled(config_snd_soc_sof_alderlake) +#endif +#if is_enabled(config_snd_soc_sof_tigerlake) + { pci_device(0x8086, 0x51c8), + .driver_data = (unsigned long)&tgl_desc},
|
Audio
|
39860fe070c97e62ae9e80addce40ce0b3c2b082
|
kai vehmanen ranjani sridharan ranjani sridharan linux intel com pierre louis bossart pierre louis bossart linux intel com guennadi liakhovetski guennadi liakhovetski linux intel com
|
sound
|
soc
|
sof
|
asoc: codec: add driver for jz4760 internal codec
|
add support for the internal codec found in the jz4760 soc from ingenic.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add driver for jz4760 internal codec
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'codec']
|
['kconfig', 'c', 'makefile']
| 3
| 904
| 0
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--- diff --git a/sound/soc/codecs/kconfig b/sound/soc/codecs/kconfig --- a/sound/soc/codecs/kconfig +++ b/sound/soc/codecs/kconfig + imply snd_soc_jz4760_codec +config snd_soc_jz4760_codec + depends on mach_ingenic || compile_test + depends on of + select regmap + tristate "ingenic jz4760 internal codec" + help + enable support for the internal codec found in the jz4760 soc + from ingenic. + + this driver can also be built as a module. if so, the module + will be called snd-soc-jz4760-codec. + diff --git a/sound/soc/codecs/makefile b/sound/soc/codecs/makefile --- a/sound/soc/codecs/makefile +++ b/sound/soc/codecs/makefile +snd-soc-jz4760-codec-objs := jz4760.o +obj-$(config_snd_soc_jz4760_codec) += snd-soc-jz4760-codec.o diff --git a/sound/soc/codecs/jz4760.c b/sound/soc/codecs/jz4760.c --- /dev/null +++ b/sound/soc/codecs/jz4760.c +// spdx-license-identifier: gpl-2.0 +// +// ingenic jz4760 codec driver +// +// copyright (c) 2021, christophe branchereau <cbranchereau@gmail.com> +// copyright (c) 2021, paul cercueil <paul@crapouillou.net> + +#include <linux/bitfield.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/regmap.h> +#include <linux/time64.h> + +#include <sound/pcm_params.h> +#include <sound/soc.h> +#include <sound/soc-dai.h> +#include <sound/soc-dapm.h> +#include <sound/tlv.h> + +#define icdc_rgadw_offset 0x00 +#define icdc_rgdata_offset 0x04 + +/* icdc internal register access control register(rgadw) */ +#define icdc_rgadw_rgwr bit(16) +#define icdc_rgadw_rgaddr_mask genmask(14, 8) +#define icdc_rgadw_rgdin_mask genmask(7, 0) + +/* icdc internal register data output register (rgdata)*/ +#define icdc_rgdata_irq bit(8) +#define icdc_rgdata_rgdout_mask genmask(7, 0) + +/* internal register space, accessed through regmap */ +enum { + jz4760_codec_reg_sr, + jz4760_codec_reg_aicr, + jz4760_codec_reg_cr1, + jz4760_codec_reg_cr2, + jz4760_codec_reg_cr3, + jz4760_codec_reg_cr4, + jz4760_codec_reg_ccr1, + jz4760_codec_reg_ccr2, + jz4760_codec_reg_pmr1, + jz4760_codec_reg_pmr2, + jz4760_codec_reg_icr, + jz4760_codec_reg_ifr, + jz4760_codec_reg_gcr1, + jz4760_codec_reg_gcr2, + jz4760_codec_reg_gcr3, + jz4760_codec_reg_gcr4, + jz4760_codec_reg_gcr5, + jz4760_codec_reg_gcr6, + jz4760_codec_reg_gcr7, + jz4760_codec_reg_gcr8, + jz4760_codec_reg_gcr9, + jz4760_codec_reg_agc1, + jz4760_codec_reg_agc2, + jz4760_codec_reg_agc3, + jz4760_codec_reg_agc4, + jz4760_codec_reg_agc5, + jz4760_codec_reg_mix1, + jz4760_codec_reg_mix2, +}; + +#define reg_aicr_dac_adwl_mask genmask(7, 6) +#define reg_aicr_dac_serial bit(3) +#define reg_aicr_dac_i2s bit(1) + +#define reg_aicr_adc_adwl_mask genmask(5, 4) + +#define reg_aicr_adc_serial bit(2) +#define reg_aicr_adc_i2s bit(0) + +#define reg_cr1_hp_load bit(7) +#define reg_cr1_hp_mute bit(5) +#define reg_cr1_lo_mute_offset 4 +#define reg_cr1_btl_mute_offset 3 +#define reg_cr1_outsel_offset 0 +#define reg_cr1_outsel_mask genmask(1, reg_cr1_outsel_offset) + +#define reg_cr2_dac_mono bit(7) +#define reg_cr2_dac_mute bit(5) +#define reg_cr2_dac_nomad bit(1) +#define reg_cr2_dac_right_only bit(0) + +#define reg_cr3_adc_insel_offset 2 +#define reg_cr3_adc_insel_mask genmask(3, reg_cr3_adc_insel_offset) +#define reg_cr3_micstereo_offset 1 +#define reg_cr3_micdiff_offset 0 + +#define reg_cr4_adc_hpf_offset 7 +#define reg_cr4_adc_right_only bit(0) + +#define reg_ccr1_crystal_mask genmask(3, 0) + +#define reg_ccr2_dac_freq_mask genmask(7, 4) +#define reg_ccr2_adc_freq_mask genmask(3, 0) + +#define reg_pmr1_sb bit(7) +#define reg_pmr1_sb_sleep bit(6) +#define reg_pmr1_sb_aip_offset 5 +#define reg_pmr1_sb_line_offset 4 +#define reg_pmr1_sb_mic1_offset 3 +#define reg_pmr1_sb_mic2_offset 2 +#define reg_pmr1_sb_bypass_offset 1 +#define reg_pmr1_sb_micbias_offset 0 + +#define reg_pmr2_sb_adc_offset 4 +#define reg_pmr2_sb_hp_offset 3 +#define reg_pmr2_sb_btl_offset 2 +#define reg_pmr2_sb_lout_offset 1 +#define reg_pmr2_sb_dac_offset 0 + +#define reg_icr_int_form_mask genmask(7, 6) +#define reg_icr_all_mask genmask(5, 0) +#define reg_icr_jack_mask bit(5) +#define reg_icr_scmc_mask bit(4) +#define reg_icr_rup_mask bit(3) +#define reg_icr_rdo_mask bit(2) +#define reg_icr_gup_mask bit(1) +#define reg_icr_gdo_mask bit(0) + +#define reg_ifr_all_mask genmask(5, 0) +#define reg_ifr_jack bit(6) +#define reg_ifr_jack_event bit(5) +#define reg_ifr_scmc bit(4) +#define reg_ifr_rup bit(3) +#define reg_ifr_rdo bit(2) +#define reg_ifr_gup bit(1) +#define reg_ifr_gdo bit(0) + +#define reg_gcr_gain_offset 0 +#define reg_gcr_gain_max 0x1f + +#define reg_gcr_rl bit(7) + +#define reg_gcr_gim1_mask genmask(5, 3) +#define reg_gcr_gim2_mask genmask(2, 0) +#define reg_gcr_gim_gain_max 7 + +#define reg_agc1_en bit(7) +#define reg_agc1_target_mask genmask(5, 2) + +#define reg_agc2_ng_thr_mask genmask(6, 4) +#define reg_agc2_hold_mask genmask(3, 0) + +#define reg_agc3_atk_mask genmask(7, 4) +#define reg_agc3_dcy_mask genmask(3, 0) + +#define reg_agc4_agc_max_mask genmask(4, 0) + +#define reg_agc5_agc_min_mask genmask(4, 0) + +#define reg_mix1_mix_rec_mask genmask(7, 6) +#define reg_mix1_gimix_mask genmask(4, 0) + +#define reg_mix2_dac_mix_mask genmask(7, 6) +#define reg_mix2_gomix_mask genmask(4, 0) + +/* codec private data */ +struct jz_codec { + struct device *dev; + struct regmap *regmap; + void __iomem *base; + struct clk *clk; +}; + +static int jz4760_codec_set_bias_level(struct snd_soc_component *codec, + enum snd_soc_bias_level level) +{ + struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); + struct regmap *regmap = jz_codec->regmap; + + switch (level) { + case snd_soc_bias_prepare: + /* reset all interrupt flags. */ + regmap_write(regmap, jz4760_codec_reg_ifr, reg_ifr_all_mask); + + regmap_clear_bits(regmap, jz4760_codec_reg_pmr1, reg_pmr1_sb); + msleep(250); + regmap_clear_bits(regmap, jz4760_codec_reg_pmr1, reg_pmr1_sb_sleep); + msleep(400); + break; + case snd_soc_bias_standby: + regmap_set_bits(regmap, jz4760_codec_reg_pmr1, reg_pmr1_sb_sleep); + regmap_set_bits(regmap, jz4760_codec_reg_pmr1, reg_pmr1_sb); + break; + default: + break; + } + + return 0; +} + +static int jz4760_codec_startup(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec); + int ret; + + /* + * sysclk output from the codec to the aic is required to keep the + * dma transfer going during playback when all audible outputs have + * been disabled. + */ + if (substream->stream == sndrv_pcm_stream_playback) + ret = snd_soc_dapm_force_enable_pin(dapm, "sysclk"); + return 0; +} + +static void jz4760_codec_shutdown(struct snd_pcm_substream *substream, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec); + + if (substream->stream == sndrv_pcm_stream_playback) + snd_soc_dapm_disable_pin(dapm, "sysclk"); +} + + +static int jz4760_codec_pcm_trigger(struct snd_pcm_substream *substream, + int cmd, struct snd_soc_dai *dai) +{ + struct snd_soc_component *codec = dai->component; + int ret = 0; + + switch (cmd) { + case sndrv_pcm_trigger_start: + case sndrv_pcm_trigger_resume: + case sndrv_pcm_trigger_pause_release: + if (substream->stream != sndrv_pcm_stream_playback) + snd_soc_component_force_bias_level(codec, snd_soc_bias_on); + break; + case sndrv_pcm_trigger_stop: + case sndrv_pcm_trigger_suspend: + case sndrv_pcm_trigger_pause_push: + /* do nothing */ + break; + default: + ret = -einval; + } + + return ret; +} + +static int jz4760_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction) +{ + struct snd_soc_component *codec = dai->component; + struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); + unsigned int gain_bit = mute ? reg_ifr_gdo : reg_ifr_gup; + unsigned int val, reg; + int change, err; + + change = snd_soc_component_update_bits(codec, jz4760_codec_reg_cr2, + reg_cr2_dac_mute, + mute ? reg_cr2_dac_mute : 0); + if (change == 1) { + regmap_read(jz_codec->regmap, jz4760_codec_reg_pmr2, &val); + + if (val & bit(reg_pmr2_sb_dac_offset)) + return 1; + + err = regmap_read_poll_timeout(jz_codec->regmap, + jz4760_codec_reg_ifr, + val, val & gain_bit, + 1000, 1 * usec_per_sec); + if (err) { + dev_err(jz_codec->dev, + "timeout while setting digital mute: %d", err); + return err; + } + + /* clear gup/gdo flag */ + regmap_write(jz_codec->regmap, jz4760_codec_reg_ifr, gain_bit); + } + + regmap_read(jz_codec->regmap, jz4760_codec_reg_cr2, ®); + + return 0; +} + +/* unit: 0.01db */ +static const declare_tlv_db_minmax_mute(dac_tlv, -3100, 100); +static const declare_tlv_db_scale(adc_tlv, 0, 100, 0); +static const declare_tlv_db_minmax(out_tlv, -2500, 100); +static const declare_tlv_db_scale(linein_tlv, -2500, 100, 0); + +/* unconditional controls. */ +static const struct snd_kcontrol_new jz4760_codec_snd_controls[] = { + /* record gain control */ + soc_double_r_tlv("pcm capture volume", + jz4760_codec_reg_gcr9, jz4760_codec_reg_gcr8, + reg_gcr_gain_offset, reg_gcr_gain_max, 0, adc_tlv), + + soc_double_r_tlv("line in bypass playback volume", + jz4760_codec_reg_gcr4, jz4760_codec_reg_gcr3, + reg_gcr_gain_offset, reg_gcr_gain_max, 1, linein_tlv), + + soc_single("high-pass filter capture switch", + jz4760_codec_reg_cr4, + reg_cr4_adc_hpf_offset, 1, 0), +}; + +static const struct snd_kcontrol_new jz4760_codec_pcm_playback_controls[] = { + { + .iface = sndrv_ctl_elem_iface_mixer, + .name = "volume", + .info = snd_soc_info_volsw, + .access = sndrv_ctl_elem_access_tlv_read + | sndrv_ctl_elem_access_readwrite, + .tlv.p = dac_tlv, + .get = snd_soc_dapm_get_volsw, + .put = snd_soc_dapm_put_volsw, + .private_value = soc_double_r_value(jz4760_codec_reg_gcr6, + jz4760_codec_reg_gcr5, + reg_gcr_gain_offset, + reg_gcr_gain_max, 1), + }, +}; + +static const struct snd_kcontrol_new jz4760_codec_hp_playback_controls[] = { + { + .iface = sndrv_ctl_elem_iface_mixer, + .name = "volume", + .info = snd_soc_info_volsw, + .access = sndrv_ctl_elem_access_tlv_read + | sndrv_ctl_elem_access_readwrite, + .tlv.p = out_tlv, + .get = snd_soc_dapm_get_volsw, + .put = snd_soc_dapm_put_volsw, + .private_value = soc_double_r_value(jz4760_codec_reg_gcr2, + jz4760_codec_reg_gcr1, + reg_gcr_gain_offset, + reg_gcr_gain_max, 1), + }, +}; + +static int hpout_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm); + struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); + unsigned int val; + int err; + + switch (event) { + case snd_soc_dapm_pre_pmu: + /* unmute hp */ + regmap_clear_bits(jz_codec->regmap, jz4760_codec_reg_cr1, + reg_cr1_hp_mute); + break; + + case snd_soc_dapm_post_pmu: + /* wait for ramp-up complete (rup) */ + err = regmap_read_poll_timeout(jz_codec->regmap, + jz4760_codec_reg_ifr, + val, val & reg_ifr_rup, + 1000, 1 * usec_per_sec); + if (err) { + dev_err(jz_codec->dev, "rup timeout: %d", err); + return err; + } + + /* clear rup flag */ + regmap_set_bits(jz_codec->regmap, jz4760_codec_reg_ifr, + reg_ifr_rup); + + break; + + case snd_soc_dapm_post_pmd: + /* mute hp */ + regmap_set_bits(jz_codec->regmap, jz4760_codec_reg_cr1, + reg_cr1_hp_mute); + + err = regmap_read_poll_timeout(jz_codec->regmap, + jz4760_codec_reg_ifr, + val, val & reg_ifr_rdo, + 1000, 1 * usec_per_sec); + if (err) { + dev_err(jz_codec->dev, "rdo timeout: %d", err); + return err; + } + + /* clear rdo flag */ + regmap_set_bits(jz_codec->regmap, jz4760_codec_reg_ifr, + reg_ifr_rdo); + + break; + } + + return 0; +} + +static const char * const jz4760_codec_hp_texts[] = { + "pcm", "line in", "mic 1", "mic 2" +}; + +static const unsigned int jz4760_codec_hp_values[] = { 3, 2, 0, 1 }; + +static soc_value_enum_single_decl(jz4760_codec_hp_enum, + jz4760_codec_reg_cr1, + reg_cr1_outsel_offset, + reg_cr1_outsel_mask >> reg_cr1_outsel_offset, + jz4760_codec_hp_texts, + jz4760_codec_hp_values); +static const struct snd_kcontrol_new jz4760_codec_hp_source = + soc_dapm_enum("route", jz4760_codec_hp_enum); + +static const char * const jz4760_codec_cap_texts[] = { + "line in", "mic 1", "mic 2" +}; + +static const unsigned int jz4760_codec_cap_values[] = { 2, 0, 1 }; + +static soc_value_enum_single_decl(jz4760_codec_cap_enum, + jz4760_codec_reg_cr3, + reg_cr3_adc_insel_offset, + reg_cr3_adc_insel_mask >> reg_cr3_adc_insel_offset, + jz4760_codec_cap_texts, + jz4760_codec_cap_values); +static const struct snd_kcontrol_new jz4760_codec_cap_source = + soc_dapm_enum("route", jz4760_codec_cap_enum); + +static const struct snd_kcontrol_new jz4760_codec_mic_controls[] = { + soc_dapm_single("stereo capture switch", jz4760_codec_reg_cr3, + reg_cr3_micstereo_offset, 1, 0), +}; + +static const struct snd_kcontrol_new jz4760_codec_line_out_switch = + soc_dapm_single("switch", jz4760_codec_reg_cr1, + reg_cr1_lo_mute_offset, 0, 0); +static const struct snd_kcontrol_new jz4760_codec_btl_out_switch = + soc_dapm_single("switch", jz4760_codec_reg_cr1, + reg_cr1_btl_mute_offset, 0, 0); + +static const struct snd_soc_dapm_widget jz4760_codec_dapm_widgets[] = { + snd_soc_dapm_pga_e("hp out", jz4760_codec_reg_pmr2, + reg_pmr2_sb_hp_offset, 1, null, 0, hpout_event, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + + snd_soc_dapm_switch("line out", jz4760_codec_reg_pmr2, + reg_pmr2_sb_lout_offset, 1, + &jz4760_codec_line_out_switch), + + snd_soc_dapm_switch("btl out", jz4760_codec_reg_pmr2, + reg_pmr2_sb_btl_offset, 1, + &jz4760_codec_btl_out_switch), + + snd_soc_dapm_pga("line in", jz4760_codec_reg_pmr1, + reg_pmr1_sb_line_offset, 1, null, 0), + + snd_soc_dapm_mux("headphones source", snd_soc_nopm, 0, 0, + &jz4760_codec_hp_source), + + snd_soc_dapm_mux("capture source", snd_soc_nopm, 0, 0, + &jz4760_codec_cap_source), + + snd_soc_dapm_pga("mic 1", jz4760_codec_reg_pmr1, + reg_pmr1_sb_mic1_offset, 1, null, 0), + + snd_soc_dapm_pga("mic 2", jz4760_codec_reg_pmr1, + reg_pmr1_sb_mic2_offset, 1, null, 0), + + snd_soc_dapm_pga("mic diff", jz4760_codec_reg_cr3, + reg_cr3_micdiff_offset, 0, null, 0), + + snd_soc_dapm_mixer("mic", snd_soc_nopm, 0, 0, + jz4760_codec_mic_controls, + array_size(jz4760_codec_mic_controls)), + + snd_soc_dapm_pga("line in bypass", jz4760_codec_reg_pmr1, + reg_pmr1_sb_bypass_offset, 1, null, 0), + + snd_soc_dapm_adc("adc", "capture", jz4760_codec_reg_pmr2, + reg_pmr2_sb_adc_offset, 1), + + snd_soc_dapm_dac("dac", "playback", jz4760_codec_reg_pmr2, + reg_pmr2_sb_dac_offset, 1), + + snd_soc_dapm_mixer("pcm playback", snd_soc_nopm, 0, 0, + jz4760_codec_pcm_playback_controls, + array_size(jz4760_codec_pcm_playback_controls)), + + snd_soc_dapm_mixer("headphones playback", snd_soc_nopm, 0, 0, + jz4760_codec_hp_playback_controls, + array_size(jz4760_codec_hp_playback_controls)), + + snd_soc_dapm_supply("micbias", jz4760_codec_reg_pmr1, + reg_pmr1_sb_micbias_offset, 1, null, 0), + + snd_soc_dapm_input("mic1p"), + snd_soc_dapm_input("mic1n"), + snd_soc_dapm_input("mic2p"), + snd_soc_dapm_input("mic2n"), + + snd_soc_dapm_input("llinein"), + snd_soc_dapm_input("rlinein"), + + snd_soc_dapm_output("lhpout"), + snd_soc_dapm_output("rhpout"), + + snd_soc_dapm_output("lout"), + snd_soc_dapm_output("rout"), + + snd_soc_dapm_output("btlp"), + snd_soc_dapm_output("btln"), + + snd_soc_dapm_output("sysclk"), +}; + +/* unconditional routes. */ +static const struct snd_soc_dapm_route jz4760_codec_dapm_routes[] = { + { "mic 1", null, "mic1p" }, + { "mic diff", null, "mic1n" }, + { "mic 1", null, "mic diff" }, + { "mic 2", null, "mic2p" }, + { "mic diff", null, "mic2n" }, + { "mic 2", null, "mic diff" }, + + { "line in", null, "llinein" }, + { "line in", null, "rlinein" }, + + { "mic", "stereo capture switch", "mic 1" }, + { "mic", "stereo capture switch", "mic 2" }, + { "headphones source", "mic 1", "mic" }, + { "headphones source", "mic 2", "mic" }, + { "capture source", "mic 1", "mic" }, + { "capture source", "mic 2", "mic" }, + + { "capture source", "line in", "line in" }, + { "capture source", "mic 1", "mic 1" }, + { "capture source", "mic 2", "mic 2" }, + { "adc", null, "capture source" }, + + { "line in bypass", null, "line in" }, + + { "headphones source", "mic 1", "mic 1" }, + { "headphones source", "mic 2", "mic 2" }, + { "headphones source", "line in", "line in bypass" }, + { "headphones source", "pcm", "headphones playback" }, + { "hp out", null, "headphones source" }, + + { "lhpout", null, "hp out" }, + { "rhpout", null, "hp out" }, + { "line out", "switch", "hp out" }, + + { "lout", null, "line out" }, + { "rout", null, "line out" }, + { "btl out", "switch", "line out" }, + + { "btlp", null, "btl out"}, + { "btln", null, "btl out"}, + + { "pcm playback", "volume", "dac" }, + { "headphones playback", "volume", "pcm playback" }, + + { "sysclk", null, "dac" }, +}; + +static void jz4760_codec_codec_init_regs(struct snd_soc_component *codec) +{ + struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); + struct regmap *regmap = jz_codec->regmap; + + /* collect updates for later sending. */ + regcache_cache_only(regmap, true); + + /* default amp output to pcm */ + regmap_set_bits(regmap, jz4760_codec_reg_cr1, reg_cr1_outsel_mask); + + /* disable stereo mic */ + regmap_clear_bits(regmap, jz4760_codec_reg_cr3, + bit(reg_cr3_micstereo_offset)); + + /* set mic 1 as default source for adc */ + regmap_clear_bits(regmap, jz4760_codec_reg_cr3, + reg_cr3_adc_insel_mask); + + /* adc/dac: serial + i2s */ + regmap_set_bits(regmap, jz4760_codec_reg_aicr, + reg_aicr_adc_serial | reg_aicr_adc_i2s | + reg_aicr_dac_serial | reg_aicr_dac_i2s); + + /* the generated irq is a high level */ + regmap_clear_bits(regmap, jz4760_codec_reg_icr, reg_icr_int_form_mask); + regmap_update_bits(regmap, jz4760_codec_reg_icr, reg_icr_all_mask, + reg_icr_jack_mask | reg_icr_rup_mask | + reg_icr_rdo_mask | reg_icr_gup_mask | + reg_icr_gdo_mask); + + /* 12m oscillator */ + regmap_clear_bits(regmap, jz4760_codec_reg_ccr1, reg_ccr1_crystal_mask); + + /* 0: 16ohm/220uf, 1: 10kohm/1uf */ + regmap_clear_bits(regmap, jz4760_codec_reg_cr1, reg_cr1_hp_load); + + /* default to nomad */ + regmap_set_bits(jz_codec->regmap, jz4760_codec_reg_cr2, + reg_cr2_dac_nomad); + + /* disable automatic gain */ + regmap_clear_bits(regmap, jz4760_codec_reg_agc1, reg_agc1_en); + + /* independent l/r dac gain control */ + regmap_clear_bits(regmap, jz4760_codec_reg_gcr5, + reg_gcr_rl); + + /* send collected updates. */ + regcache_cache_only(regmap, false); + regcache_sync(regmap); +} + +static int jz4760_codec_codec_probe(struct snd_soc_component *codec) +{ + struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); + + clk_prepare_enable(jz_codec->clk); + + jz4760_codec_codec_init_regs(codec); + + return 0; +} + +static void jz4760_codec_codec_remove(struct snd_soc_component *codec) +{ + struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); + + clk_disable_unprepare(jz_codec->clk); +} + +static const struct snd_soc_component_driver jz4760_codec_soc_codec_dev = { + .probe = jz4760_codec_codec_probe, + .remove = jz4760_codec_codec_remove, + .set_bias_level = jz4760_codec_set_bias_level, + .controls = jz4760_codec_snd_controls, + .num_controls = array_size(jz4760_codec_snd_controls), + .dapm_widgets = jz4760_codec_dapm_widgets, + .num_dapm_widgets = array_size(jz4760_codec_dapm_widgets), + .dapm_routes = jz4760_codec_dapm_routes, + .num_dapm_routes = array_size(jz4760_codec_dapm_routes), + .suspend_bias_off = 1, + .use_pmdown_time = 1, +}; + +static const unsigned int jz4760_codec_sample_rates[] = { + 96000, 48000, 44100, 32000, + 24000, 22050, 16000, 12000, + 11025, 9600, 8000, +}; + +static int jz4760_codec_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct jz_codec *codec = snd_soc_component_get_drvdata(dai->component); + unsigned int rate, bit_width; + + switch (params_format(params)) { + case sndrv_pcm_format_s16_le: + bit_width = 0; + break; + case sndrv_pcm_format_s18_3le: + bit_width = 1; + break; + case sndrv_pcm_format_s20_3le: + bit_width = 2; + break; + case sndrv_pcm_format_s24_3le: + bit_width = 3; + break; + default: + return -einval; + } + + for (rate = 0; rate < array_size(jz4760_codec_sample_rates); rate++) { + if (jz4760_codec_sample_rates[rate] == params_rate(params)) + break; + } + + if (rate == array_size(jz4760_codec_sample_rates)) + return -einval; + + if (substream->stream == sndrv_pcm_stream_playback) { + regmap_update_bits(codec->regmap, jz4760_codec_reg_aicr, + reg_aicr_dac_adwl_mask, + field_prep(reg_aicr_dac_adwl_mask, bit_width)); + regmap_update_bits(codec->regmap, jz4760_codec_reg_ccr2, + reg_ccr2_dac_freq_mask, + field_prep(reg_ccr2_dac_freq_mask, rate)); + } else { + regmap_update_bits(codec->regmap, jz4760_codec_reg_aicr, + reg_aicr_adc_adwl_mask, + field_prep(reg_aicr_adc_adwl_mask, bit_width)); + regmap_update_bits(codec->regmap, jz4760_codec_reg_ccr2, + reg_ccr2_adc_freq_mask, + field_prep(reg_ccr2_adc_freq_mask, rate)); + } + + return 0; +} + +static const struct snd_soc_dai_ops jz4760_codec_dai_ops = { + .startup = jz4760_codec_startup, + .shutdown = jz4760_codec_shutdown, + .hw_params = jz4760_codec_hw_params, + .trigger = jz4760_codec_pcm_trigger, + .mute_stream = jz4760_codec_mute_stream, + .no_capture_mute = 1, +}; + +#define jz_codec_formats (sndrv_pcm_fmtbit_s16_le | \ + sndrv_pcm_fmtbit_s18_3le | \ + sndrv_pcm_fmtbit_s20_3le | \ + sndrv_pcm_fmtbit_s24_3le) + +static struct snd_soc_dai_driver jz4760_codec_dai = { + .name = "jz4760-hifi", + .playback = { + .stream_name = "playback", + .channels_min = 2, + .channels_max = 2, + .rates = sndrv_pcm_rate_8000_96000, + .formats = jz_codec_formats, + }, + .capture = { + .stream_name = "capture", + .channels_min = 2, + .channels_max = 2, + .rates = sndrv_pcm_rate_8000_96000, + .formats = jz_codec_formats, + }, + .ops = &jz4760_codec_dai_ops, +}; + +static bool jz4760_codec_volatile(struct device *dev, unsigned int reg) +{ + return reg == jz4760_codec_reg_sr || reg == jz4760_codec_reg_ifr; +} + +static bool jz4760_codec_writeable(struct device *dev, unsigned int reg) +{ + switch (reg) { + case jz4760_codec_reg_sr: + return false; + default: + return true; + } +} + +static int jz4760_codec_io_wait(struct jz_codec *codec) +{ + u32 reg; + + return readl_poll_timeout(codec->base + icdc_rgadw_offset, reg, + !(reg & icdc_rgadw_rgwr), + 1000, 1 * usec_per_sec); +} + +static int jz4760_codec_reg_read(void *context, unsigned int reg, + unsigned int *val) +{ + struct jz_codec *codec = context; + unsigned int i; + u32 tmp; + int ret; + + ret = jz4760_codec_io_wait(codec); + if (ret) + return ret; + + tmp = readl(codec->base + icdc_rgadw_offset); + tmp &= ~icdc_rgadw_rgaddr_mask; + tmp |= field_prep(icdc_rgadw_rgaddr_mask, reg); + writel(tmp, codec->base + icdc_rgadw_offset); + + /* wait 6+ cycles */ + for (i = 0; i < 6; i++) + *val = readl(codec->base + icdc_rgdata_offset) & + icdc_rgdata_rgdout_mask; + + return 0; +} + +static int jz4760_codec_reg_write(void *context, unsigned int reg, + unsigned int val) +{ + struct jz_codec *codec = context; + int ret; + + ret = jz4760_codec_io_wait(codec); + if (ret) + return ret; + + writel(icdc_rgadw_rgwr | field_prep(icdc_rgadw_rgaddr_mask, reg) | val, + codec->base + icdc_rgadw_offset); + + ret = jz4760_codec_io_wait(codec); + if (ret) + return ret; + + return 0; +} + +static const u8 jz4760_codec_reg_defaults[] = { + 0x00, 0xfc, 0x1b, 0x20, 0x00, 0x80, 0x00, 0x00, + 0xff, 0x1f, 0x3f, 0x00, 0x06, 0x06, 0x06, 0x06, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x07, 0x44, + 0x1f, 0x00, 0x00, 0x00 +}; + +static struct regmap_config jz4760_codec_regmap_config = { + .reg_bits = 7, + .val_bits = 8, + + .max_register = jz4760_codec_reg_mix2, + .volatile_reg = jz4760_codec_volatile, + .writeable_reg = jz4760_codec_writeable, + + .reg_read = jz4760_codec_reg_read, + .reg_write = jz4760_codec_reg_write, + + .reg_defaults_raw = jz4760_codec_reg_defaults, + .num_reg_defaults_raw = array_size(jz4760_codec_reg_defaults), + .cache_type = regcache_flat, +}; + +static int jz4760_codec_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct jz_codec *codec; + int ret; + + codec = devm_kzalloc(dev, sizeof(*codec), gfp_kernel); + if (!codec) + return -enomem; + + codec->dev = dev; + + codec->base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(codec->base)) { + ret = ptr_err(codec->base); + dev_err(dev, "failed to ioremap mmio memory: %d ", ret); + return ret; + } + + codec->regmap = devm_regmap_init(dev, null, codec, + &jz4760_codec_regmap_config); + if (is_err(codec->regmap)) + return ptr_err(codec->regmap); + + codec->clk = devm_clk_get(dev, "aic"); + if (is_err(codec->clk)) + return ptr_err(codec->clk); + + platform_set_drvdata(pdev, codec); + + ret = devm_snd_soc_register_component(dev, &jz4760_codec_soc_codec_dev, + &jz4760_codec_dai, 1); + if (ret) { + dev_err(dev, "failed to register codec: %d ", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id jz4760_codec_of_matches[] = { + { .compatible = "ingenic,jz4760-codec", }, + { /* sentinel */ } +}; +module_device_table(of, jz4760_codec_of_matches); + +static struct platform_driver jz4760_codec_driver = { + .probe = jz4760_codec_probe, + .driver = { + .name = "jz4760-codec", + .of_match_table = jz4760_codec_of_matches, + }, +}; +module_platform_driver(jz4760_codec_driver); + +module_description("jz4760 soc internal codec driver"); +module_author("christophe branchereau <cbranchereau@gmail.com>"); +module_author("paul cercueil <paul@crapouillou.net>"); +module_license("gpl v2");
|
Audio
|
d9cd22e9c87cb61488d00f7279cfb2abf5238879
|
christophe branchereau
|
sound
|
soc
|
codecs
|
asoc: codec: hdmi-codec: support iec958 encoded pcm format
|
existing hdmi-codec driver only support standard pcm format. support of iec958 encoded format pass from alsa iec958 plugin is needed so that the iec958 encoded data can be streamed to the hdmi chip.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support iec958 encoded pcm format
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'codec', 'hdmi-codec']
|
['h', 'c']
| 2
| 8
| 1
|
--- diff --git a/include/sound/hdmi-codec.h b/include/sound/hdmi-codec.h --- a/include/sound/hdmi-codec.h +++ b/include/sound/hdmi-codec.h + /* bit_fmt could be standard pcm format or + * iec958 encoded format. alsa iec958 plugin will pass + * iec958_subframe format to the underneath driver. + */ + snd_pcm_format_t bit_fmt; diff --git a/sound/soc/codecs/hdmi-codec.c b/sound/soc/codecs/hdmi-codec.c --- a/sound/soc/codecs/hdmi-codec.c +++ b/sound/soc/codecs/hdmi-codec.c + cf->bit_fmt = params_format(params); - sndrv_pcm_fmtbit_s32_le | sndrv_pcm_fmtbit_s32_be) + sndrv_pcm_fmtbit_s32_le | sndrv_pcm_fmtbit_s32_be |\ + sndrv_pcm_fmtbit_iec958_subframe_le)
|
Audio
|
28785f548d18e6d52785a1172e5c176784ce74cd
|
sia jee heng
|
include
|
sound
|
codecs
|
asoc: qcom: dt-bindings: add bindings for lpass rx macro codec
|
this binding is for lpass has internal codec rx macro which is for connecting with soundwire rx codecs like wcd938x.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
adds support for two codec macro blocks(tx and rx) available in qualcomm lpass (low power audio subsystem)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'codecs']
|
['yaml']
| 1
| 62
| 0
|
--- diff --git a/documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml b/documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml --- /dev/null +++ b/documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +# spdx-license-identifier: (gpl-2.0-only or bsd-2-clause) +%yaml 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,lpass-rx-macro.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: lpass(low power audio subsystem) rx macro audio codec dt bindings + +maintainers: + - srinivas kandagatla <srinivas.kandagatla@linaro.org> + +properties: + compatible: + const: qcom,sm8250-lpass-rx-macro + + reg: + maxitems: 1 + + "#sound-dai-cells": + const: 1 + + '#clock-cells': + const: 0 + + clocks: + maxitems: 5 + + clock-names: + items: + - const: mclk + - const: npl + - const: macro + - const: dcodec + - const: fsgen + + clock-output-names: + items: + - const: mclk + +required: + - compatible + - reg + - "#sound-dai-cells" + +additionalproperties: false + +examples: + - | + #include <dt-bindings/sound/qcom,q6afe.h> + codec@3200000 { + compatible = "qcom,sm8250-lpass-rx-macro"; + reg = <0x3200000 0x1000>; + #sound-dai-cells = <1>; + #clock-cells = <0>; + clocks = <&audiocc 0>, + <&audiocc 1>, + <&q6afecc lpass_hw_macro_vote lpass_clk_attribute_couple_no>, + <&q6afecc lpass_hw_dcodec_vote lpass_clk_attribute_couple_no>, + <&vamacro>; + clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + clock-output-names = "mclk"; + };
|
Audio
|
f133de9e32374841c5ed1ad5cf18ed14098a0f4c
|
srinivas kandagatla rob herring robh kernel org
|
documentation
|
devicetree
|
bindings, sound
|
asoc: codecs: lpass-rx-macro: add support for lpass rx macro
|
lpass rx codec macro is available in qualcomm lpass (low power audio subsystem). this is used for connecting with soundwire devices like wcd938x codecs to provide headphone/ear/lineout functionality.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
adds support for two codec macro blocks(tx and rx) available in qualcomm lpass (low power audio subsystem)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'codecs']
|
['kconfig', 'c', 'makefile']
| 3
| 2,001
| 0
|
--- diff --git a/sound/soc/codecs/kconfig b/sound/soc/codecs/kconfig --- a/sound/soc/codecs/kconfig +++ b/sound/soc/codecs/kconfig + imply snd_soc_lpass_rx_macro +config snd_soc_lpass_rx_macro + depends on common_clk + tristate "qualcomm rx macro in lpass(low power audio subsystem)" + diff --git a/sound/soc/codecs/makefile b/sound/soc/codecs/makefile --- a/sound/soc/codecs/makefile +++ b/sound/soc/codecs/makefile +snd-soc-lpass-rx-macro-objs := lpass-rx-macro.o +obj-$(config_snd_soc_lpass_rx_macro) += snd-soc-lpass-rx-macro.o diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c --- /dev/null +++ b/sound/soc/codecs/lpass-rx-macro.c +// spdx-license-identifier: gpl-2.0-only +// copyright (c) 2018-2020, the linux foundation. all rights reserved. + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/platform_device.h> +#include <linux/clk.h> +#include <sound/soc.h> +#include <sound/pcm.h> +#include <sound/pcm_params.h> +#include <sound/soc-dapm.h> +#include <sound/tlv.h> +#include <linux/of_clk.h> +#include <linux/clk-provider.h> + +#define cdc_rx_top_top_cfg0 (0x0000) +#define cdc_rx_top_swr_ctrl (0x0008) +#define cdc_rx_top_debug (0x000c) +#define cdc_rx_top_debug_bus (0x0010) +#define cdc_rx_top_debug_en0 (0x0014) +#define cdc_rx_top_debug_en1 (0x0018) +#define cdc_rx_top_debug_en2 (0x001c) +#define cdc_rx_top_hphl_comp_wr_lsb (0x0020) +#define cdc_rx_top_hphl_comp_wr_msb (0x0024) +#define cdc_rx_top_hphl_comp_lut (0x0028) +#define cdc_rx_top_hph_lut_bypass_mask bit(7) +#define cdc_rx_top_hphl_comp_rd_lsb (0x002c) +#define cdc_rx_top_hphl_comp_rd_msb (0x0030) +#define cdc_rx_top_hphr_comp_wr_lsb (0x0034) +#define cdc_rx_top_hphr_comp_wr_msb (0x0038) +#define cdc_rx_top_hphr_comp_lut (0x003c) +#define cdc_rx_top_hphr_comp_rd_lsb (0x0040) +#define cdc_rx_top_hphr_comp_rd_msb (0x0044) +#define cdc_rx_top_dsd0_debug_cfg0 (0x0070) +#define cdc_rx_top_dsd0_debug_cfg1 (0x0074) +#define cdc_rx_top_dsd0_debug_cfg2 (0x0078) +#define cdc_rx_top_dsd0_debug_cfg3 (0x007c) +#define cdc_rx_top_dsd1_debug_cfg0 (0x0080) +#define cdc_rx_top_dsd1_debug_cfg1 (0x0084) +#define cdc_rx_top_dsd1_debug_cfg2 (0x0088) +#define cdc_rx_top_dsd1_debug_cfg3 (0x008c) +#define cdc_rx_top_rx_i2s_ctl (0x0090) +#define cdc_rx_top_tx_i2s2_ctl (0x0094) +#define cdc_rx_top_i2s_clk (0x0098) +#define cdc_rx_top_i2s_reset (0x009c) +#define cdc_rx_top_i2s_mux (0x00a0) +#define cdc_rx_clk_rst_ctrl_mclk_control (0x0100) +#define cdc_rx_clk_mclk_en_mask bit(0) +#define cdc_rx_clk_mclk_enable bit(0) +#define cdc_rx_clk_mclk2_en_mask bit(1) +#define cdc_rx_clk_mclk2_enable bit(1) +#define cdc_rx_clk_rst_ctrl_fs_cnt_control (0x0104) +#define cdc_rx_fs_mclk_cnt_en_mask bit(0) +#define cdc_rx_fs_mclk_cnt_enable bit(0) +#define cdc_rx_fs_mclk_cnt_clr_mask bit(1) +#define cdc_rx_fs_mclk_cnt_clr bit(1) +#define cdc_rx_clk_rst_ctrl_swr_control (0x0108) +#define cdc_rx_swr_clk_en_mask bit(0) +#define cdc_rx_swr_reset_mask bit(1) +#define cdc_rx_swr_reset bit(1) +#define cdc_rx_clk_rst_ctrl_dsd_control (0x010c) +#define cdc_rx_clk_rst_ctrl_asrc_share_control (0x0110) +#define cdc_rx_softclip_crc (0x0140) +#define cdc_rx_softclip_clk_en_mask bit(0) +#define cdc_rx_softclip_softclip_ctrl (0x0144) +#define cdc_rx_softclip_en_mask bit(0) +#define cdc_rx_inp_mux_rx_int0_cfg0 (0x0180) +#define cdc_rx_intx_1_mix_inp0_sel_mask genmask(3, 0) +#define cdc_rx_intx_1_mix_inp1_sel_mask genmask(7, 4) +#define cdc_rx_inp_mux_rx_int0_cfg1 (0x0184) +#define cdc_rx_intx_2_sel_mask genmask(3, 0) +#define cdc_rx_intx_1_mix_inp2_sel_mask genmask(7, 4) +#define cdc_rx_inp_mux_rx_int1_cfg0 (0x0188) +#define cdc_rx_inp_mux_rx_int1_cfg1 (0x018c) +#define cdc_rx_inp_mux_rx_int2_cfg0 (0x0190) +#define cdc_rx_inp_mux_rx_int2_cfg1 (0x0194) +#define cdc_rx_inp_mux_rx_mix_cfg4 (0x0198) +#define cdc_rx_inp_mux_rx_mix_cfg5 (0x019c) +#define cdc_rx_inp_mux_sidetone_src_cfg0 (0x01a0) +#define cdc_rx_clsh_crc (0x0200) +#define cdc_rx_clsh_clk_en_mask bit(0) +#define cdc_rx_clsh_dly_ctrl (0x0204) +#define cdc_rx_clsh_decay_ctrl (0x0208) +#define cdc_rx_clsh_decay_rate_mask genmask(2, 0) +#define cdc_rx_clsh_hph_v_pa (0x020c) +#define cdc_rx_clsh_hph_v_pa_min_mask genmask(5, 0) +#define cdc_rx_clsh_ear_v_pa (0x0210) +#define cdc_rx_clsh_hph_v_hd (0x0214) +#define cdc_rx_clsh_ear_v_hd (0x0218) +#define cdc_rx_clsh_k1_msb (0x021c) +#define cdc_rx_clsh_k1_msb_coeff_mask genmask(3, 0) +#define cdc_rx_clsh_k1_lsb (0x0220) +#define cdc_rx_clsh_k2_msb (0x0224) +#define cdc_rx_clsh_k2_lsb (0x0228) +#define cdc_rx_clsh_idle_ctrl (0x022c) +#define cdc_rx_clsh_idle_hph (0x0230) +#define cdc_rx_clsh_idle_ear (0x0234) +#define cdc_rx_clsh_test0 (0x0238) +#define cdc_rx_clsh_test1 (0x023c) +#define cdc_rx_clsh_ovr_vref (0x0240) +#define cdc_rx_clsh_clsg_ctl (0x0244) +#define cdc_rx_clsh_clsg_cfg1 (0x0248) +#define cdc_rx_clsh_clsg_cfg2 (0x024c) +#define cdc_rx_bcl_vbat_path_ctl (0x0280) +#define cdc_rx_bcl_vbat_cfg (0x0284) +#define cdc_rx_bcl_vbat_adc_cal1 (0x0288) +#define cdc_rx_bcl_vbat_adc_cal2 (0x028c) +#define cdc_rx_bcl_vbat_adc_cal3 (0x0290) +#define cdc_rx_bcl_vbat_pk_est1 (0x0294) +#define cdc_rx_bcl_vbat_pk_est2 (0x0298) +#define cdc_rx_bcl_vbat_pk_est3 (0x029c) +#define cdc_rx_bcl_vbat_rf_proc1 (0x02a0) +#define cdc_rx_bcl_vbat_rf_proc2 (0x02a4) +#define cdc_rx_bcl_vbat_tac1 (0x02a8) +#define cdc_rx_bcl_vbat_tac2 (0x02ac) +#define cdc_rx_bcl_vbat_tac3 (0x02b0) +#define cdc_rx_bcl_vbat_tac4 (0x02b4) +#define cdc_rx_bcl_vbat_gain_upd1 (0x02b8) +#define cdc_rx_bcl_vbat_gain_upd2 (0x02bc) +#define cdc_rx_bcl_vbat_gain_upd3 (0x02c0) +#define cdc_rx_bcl_vbat_gain_upd4 (0x02c4) +#define cdc_rx_bcl_vbat_gain_upd5 (0x02c8) +#define cdc_rx_bcl_vbat_debug1 (0x02cc) +#define cdc_rx_bcl_vbat_gain_upd_mon (0x02d0) +#define cdc_rx_bcl_vbat_gain_mon_val (0x02d4) +#define cdc_rx_bcl_vbat_ban (0x02d8) +#define cdc_rx_bcl_vbat_bcl_gain_upd1 (0x02dc) +#define cdc_rx_bcl_vbat_bcl_gain_upd2 (0x02e0) +#define cdc_rx_bcl_vbat_bcl_gain_upd3 (0x02e4) +#define cdc_rx_bcl_vbat_bcl_gain_upd4 (0x02e8) +#define cdc_rx_bcl_vbat_bcl_gain_upd5 (0x02ec) +#define cdc_rx_bcl_vbat_bcl_gain_upd6 (0x02f0) +#define cdc_rx_bcl_vbat_bcl_gain_upd7 (0x02f4) +#define cdc_rx_bcl_vbat_bcl_gain_upd8 (0x02f8) +#define cdc_rx_bcl_vbat_bcl_gain_upd9 (0x02fc) +#define cdc_rx_bcl_vbat_attn1 (0x0300) +#define cdc_rx_bcl_vbat_attn2 (0x0304) +#define cdc_rx_bcl_vbat_attn3 (0x0308) +#define cdc_rx_bcl_vbat_decode_ctl1 (0x030c) +#define cdc_rx_bcl_vbat_decode_ctl2 (0x0310) +#define cdc_rx_bcl_vbat_decode_cfg1 (0x0314) +#define cdc_rx_bcl_vbat_decode_cfg2 (0x0318) +#define cdc_rx_bcl_vbat_decode_cfg3 (0x031c) +#define cdc_rx_bcl_vbat_decode_cfg4 (0x0320) +#define cdc_rx_bcl_vbat_decode_st (0x0324) +#define cdc_rx_intr_ctrl_cfg (0x0340) +#define cdc_rx_intr_ctrl_clr_commit (0x0344) +#define cdc_rx_intr_ctrl_pin1_mask0 (0x0360) +#define cdc_rx_intr_ctrl_pin1_status0 (0x0368) +#define cdc_rx_intr_ctrl_pin1_clear0 (0x0370) +#define cdc_rx_intr_ctrl_pin2_mask0 (0x0380) +#define cdc_rx_intr_ctrl_pin2_status0 (0x0388) +#define cdc_rx_intr_ctrl_pin2_clear0 (0x0390) +#define cdc_rx_intr_ctrl_level0 (0x03c0) +#define cdc_rx_intr_ctrl_bypass0 (0x03c8) +#define cdc_rx_intr_ctrl_set0 (0x03d0) +#define cdc_rx_rxn_rx_path_ctl(n) (0x0400 + 0x80 * n) +#define cdc_rx_rx0_rx_path_ctl (0x0400) +#define cdc_rx_path_reset_en_mask bit(6) +#define cdc_rx_path_clk_en_mask bit(5) +#define cdc_rx_path_clk_enable bit(5) +#define cdc_rx_path_pga_mute_mask bit(4) +#define cdc_rx_path_pga_mute_enable bit(4) +#define cdc_rx_path_pcm_rate_mask genmask(3, 0) +#define cdc_rx_rxn_rx_path_cfg0(n) (0x0404 + 0x80 * n) +#define cdc_rx_rxn_comp_en_mask bit(1) +#define cdc_rx_rx0_rx_path_cfg0 (0x0404) +#define cdc_rx_rxn_clsh_en_mask bit(6) +#define cdc_rx_dly_zn_en_mask bit(3) +#define cdc_rx_dly_zn_enable bit(3) +#define cdc_rx_rxn_hd2_en_mask bit(2) +#define cdc_rx_rxn_rx_path_cfg1(n) (0x0408 + 0x80 * n) +#define cdc_rx_rxn_sidetone_en_mask bit(4) +#define cdc_rx_rx0_rx_path_cfg1 (0x0408) +#define cdc_rx_rx0_hph_l_ear_sel_mask bit(1) +#define cdc_rx_rxn_rx_path_cfg2(n) (0x040c + 0x80 * n) +#define cdc_rx_rxn_hpf_cut_freq_mask genmask(1, 0) +#define cdc_rx_rx0_rx_path_cfg2 (0x040c) +#define cdc_rx_rxn_rx_path_cfg3(n) (0x0410 + 0x80 * n) +#define cdc_rx_rx0_rx_path_cfg3 (0x0410) +#define cdc_rx_dc_coeff_sel_mask genmask(1, 0) +#define cdc_rx_dc_coeff_sel_two 0x2 +#define cdc_rx_rxn_rx_vol_ctl(n) (0x0414 + 0x80 * n) +#define cdc_rx_rx0_rx_vol_ctl (0x0414) +#define cdc_rx_rxn_rx_path_mix_ctl(n) (0x0418 + 0x80 * n) +#define cdc_rx_rxn_mix_pcm_rate_mask genmask(3, 0) +#define cdc_rx_rxn_mix_reset_mask bit(6) +#define cdc_rx_rxn_mix_reset bit(6) +#define cdc_rx_rxn_mix_clk_en_mask bit(5) +#define cdc_rx_rx0_rx_path_mix_ctl (0x0418) +#define cdc_rx_rx0_rx_path_mix_cfg (0x041c) +#define cdc_rx_rxn_rx_vol_mix_ctl(n) (0x0420 + 0x80 * n) +#define cdc_rx_rx0_rx_vol_mix_ctl (0x0420) +#define cdc_rx_rx0_rx_path_sec1 (0x0424) +#define cdc_rx_rx0_rx_path_sec2 (0x0428) +#define cdc_rx_rx0_rx_path_sec3 (0x042c) +#define cdc_rx_rx0_rx_path_sec4 (0x0430) +#define cdc_rx_rx0_rx_path_sec7 (0x0434) +#define cdc_rx_dsm_out_delay_sel_mask genmask(2, 0) +#define cdc_rx_dsm_out_delay_two_sample 0x2 +#define cdc_rx_rx0_rx_path_mix_sec0 (0x0438) +#define cdc_rx_rx0_rx_path_mix_sec1 (0x043c) +#define cdc_rx_rxn_rx_path_dsm_ctl(n) (0x0440 + 0x80 * n) +#define cdc_rx_rxn_dsm_clk_en_mask bit(0) +#define cdc_rx_rx0_rx_path_dsm_ctl (0x0440) +#define cdc_rx_rx0_rx_path_dsm_data1 (0x0444) +#define cdc_rx_rx0_rx_path_dsm_data2 (0x0448) +#define cdc_rx_rx0_rx_path_dsm_data3 (0x044c) +#define cdc_rx_rx0_rx_path_dsm_data4 (0x0450) +#define cdc_rx_rx0_rx_path_dsm_data5 (0x0454) +#define cdc_rx_rx0_rx_path_dsm_data6 (0x0458) +#define cdc_rx_rx1_rx_path_ctl (0x0480) +#define cdc_rx_rx1_rx_path_cfg0 (0x0484) +#define cdc_rx_rx1_rx_path_cfg1 (0x0488) +#define cdc_rx_rx1_rx_path_cfg2 (0x048c) +#define cdc_rx_rx1_rx_path_cfg3 (0x0490) +#define cdc_rx_rx1_rx_vol_ctl (0x0494) +#define cdc_rx_rx1_rx_path_mix_ctl (0x0498) +#define cdc_rx_rx1_rx_path_mix_cfg (0x049c) +#define cdc_rx_rx1_rx_vol_mix_ctl (0x04a0) +#define cdc_rx_rx1_rx_path_sec1 (0x04a4) +#define cdc_rx_rx1_rx_path_sec2 (0x04a8) +#define cdc_rx_rx1_rx_path_sec3 (0x04ac) +#define cdc_rx_rxn_hd2_alpha_mask genmask(5, 2) +#define cdc_rx_rx1_rx_path_sec4 (0x04b0) +#define cdc_rx_rx1_rx_path_sec7 (0x04b4) +#define cdc_rx_rx1_rx_path_mix_sec0 (0x04b8) +#define cdc_rx_rx1_rx_path_mix_sec1 (0x04bc) +#define cdc_rx_rx1_rx_path_dsm_ctl (0x04c0) +#define cdc_rx_rx1_rx_path_dsm_data1 (0x04c4) +#define cdc_rx_rx1_rx_path_dsm_data2 (0x04c8) +#define cdc_rx_rx1_rx_path_dsm_data3 (0x04cc) +#define cdc_rx_rx1_rx_path_dsm_data4 (0x04d0) +#define cdc_rx_rx1_rx_path_dsm_data5 (0x04d4) +#define cdc_rx_rx1_rx_path_dsm_data6 (0x04d8) +#define cdc_rx_rx2_rx_path_ctl (0x0500) +#define cdc_rx_rx2_rx_path_cfg0 (0x0504) +#define cdc_rx_rx2_clsh_en_mask bit(4) +#define cdc_rx_rx2_dly_z_en_mask bit(3) +#define cdc_rx_rx2_rx_path_cfg1 (0x0508) +#define cdc_rx_rx2_rx_path_cfg2 (0x050c) +#define cdc_rx_rx2_rx_path_cfg3 (0x0510) +#define cdc_rx_rx2_rx_vol_ctl (0x0514) +#define cdc_rx_rx2_rx_path_mix_ctl (0x0518) +#define cdc_rx_rx2_rx_path_mix_cfg (0x051c) +#define cdc_rx_rx2_rx_vol_mix_ctl (0x0520) +#define cdc_rx_rx2_rx_path_sec0 (0x0524) +#define cdc_rx_rx2_rx_path_sec1 (0x0528) +#define cdc_rx_rx2_rx_path_sec2 (0x052c) +#define cdc_rx_rx2_rx_path_sec3 (0x0530) +#define cdc_rx_rx2_rx_path_sec4 (0x0534) +#define cdc_rx_rx2_rx_path_sec5 (0x0538) +#define cdc_rx_rx2_rx_path_sec6 (0x053c) +#define cdc_rx_rx2_rx_path_sec7 (0x0540) +#define cdc_rx_rx2_rx_path_mix_sec0 (0x0544) +#define cdc_rx_rx2_rx_path_mix_sec1 (0x0548) +#define cdc_rx_rx2_rx_path_dsm_ctl (0x054c) +#define cdc_rx_idle_detect_path_ctl (0x0780) +#define cdc_rx_idle_detect_cfg0 (0x0784) +#define cdc_rx_idle_detect_cfg1 (0x0788) +#define cdc_rx_idle_detect_cfg2 (0x078c) +#define cdc_rx_idle_detect_cfg3 (0x0790) +#define cdc_rx_compandern_ctl0(n) (0x0800 + 0x40 * n) +#define cdc_rx_compandern_clk_en_mask bit(0) +#define cdc_rx_compandern_soft_rst_mask bit(1) +#define cdc_rx_compandern_halt_mask bit(2) +#define cdc_rx_compander0_ctl0 (0x0800) +#define cdc_rx_compander0_ctl1 (0x0804) +#define cdc_rx_compander0_ctl2 (0x0808) +#define cdc_rx_compander0_ctl3 (0x080c) +#define cdc_rx_compander0_ctl4 (0x0810) +#define cdc_rx_compander0_ctl5 (0x0814) +#define cdc_rx_compander0_ctl6 (0x0818) +#define cdc_rx_compander0_ctl7 (0x081c) +#define cdc_rx_compander1_ctl0 (0x0840) +#define cdc_rx_compander1_ctl1 (0x0844) +#define cdc_rx_compander1_ctl2 (0x0848) +#define cdc_rx_compander1_ctl3 (0x084c) +#define cdc_rx_compander1_ctl4 (0x0850) +#define cdc_rx_compander1_ctl5 (0x0854) +#define cdc_rx_compander1_ctl6 (0x0858) +#define cdc_rx_compander1_ctl7 (0x085c) +#define cdc_rx_compander1_hph_low_pwr_mode_mask bit(5) +#define cdc_rx_sidetone_iir0_iir_path_ctl (0x0a00) +#define cdc_rx_sidetone_iir0_iir_gain_b1_ctl (0x0a04) +#define cdc_rx_sidetone_iir0_iir_gain_b2_ctl (0x0a08) +#define cdc_rx_sidetone_iir0_iir_gain_b3_ctl (0x0a0c) +#define cdc_rx_sidetone_iir0_iir_gain_b4_ctl (0x0a10) +#define cdc_rx_sidetone_iir0_iir_gain_b5_ctl (0x0a14) +#define cdc_rx_sidetone_iir0_iir_gain_b6_ctl (0x0a18) +#define cdc_rx_sidetone_iir0_iir_gain_b7_ctl (0x0a1c) +#define cdc_rx_sidetone_iir0_iir_gain_b8_ctl (0x0a20) +#define cdc_rx_sidetone_iir0_iir_ctl (0x0a24) +#define cdc_rx_sidetone_iir0_iir_gain_timer_ctl (0x0a28) +#define cdc_rx_sidetone_iir0_iir_coef_b1_ctl (0x0a2c) +#define cdc_rx_sidetone_iir0_iir_coef_b2_ctl (0x0a30) +#define cdc_rx_sidetone_iir1_iir_path_ctl (0x0a80) +#define cdc_rx_sidetone_iir1_iir_gain_b1_ctl (0x0a84) +#define cdc_rx_sidetone_iir1_iir_gain_b2_ctl (0x0a88) +#define cdc_rx_sidetone_iir1_iir_gain_b3_ctl (0x0a8c) +#define cdc_rx_sidetone_iir1_iir_gain_b4_ctl (0x0a90) +#define cdc_rx_sidetone_iir1_iir_gain_b5_ctl (0x0a94) +#define cdc_rx_sidetone_iir1_iir_gain_b6_ctl (0x0a98) +#define cdc_rx_sidetone_iir1_iir_gain_b7_ctl (0x0a9c) +#define cdc_rx_sidetone_iir1_iir_gain_b8_ctl (0x0aa0) +#define cdc_rx_sidetone_iir1_iir_ctl (0x0aa4) +#define cdc_rx_sidetone_iir1_iir_gain_timer_ctl (0x0aa8) +#define cdc_rx_sidetone_iir1_iir_coef_b1_ctl (0x0aac) +#define cdc_rx_sidetone_iir1_iir_coef_b2_ctl (0x0ab0) +#define cdc_rx_iir_inp_mux_iir0_mix_cfg0 (0x0b00) +#define cdc_rx_iir_inp_mux_iir0_mix_cfg1 (0x0b04) +#define cdc_rx_iir_inp_mux_iir0_mix_cfg2 (0x0b08) +#define cdc_rx_iir_inp_mux_iir0_mix_cfg3 (0x0b0c) +#define cdc_rx_iir_inp_mux_iir1_mix_cfg0 (0x0b10) +#define cdc_rx_iir_inp_mux_iir1_mix_cfg1 (0x0b14) +#define cdc_rx_iir_inp_mux_iir1_mix_cfg2 (0x0b18) +#define cdc_rx_iir_inp_mux_iir1_mix_cfg3 (0x0b1c) +#define cdc_rx_sidetone_src0_st_src_path_ctl (0x0b40) +#define cdc_rx_sidetone_src0_st_src_path_cfg1 (0x0b44) +#define cdc_rx_sidetone_src1_st_src_path_ctl (0x0b50) +#define cdc_rx_sidetone_src1_st_src_path_cfg1 (0x0b54) +#define cdc_rx_ec_ref_hq0_ec_ref_hq_path_ctl (0x0c00) +#define cdc_rx_ec_ref_hq0_ec_ref_hq_cfg0 (0x0c04) +#define cdc_rx_ec_ref_hq1_ec_ref_hq_path_ctl (0x0c40) +#define cdc_rx_ec_ref_hq1_ec_ref_hq_cfg0 (0x0c44) +#define cdc_rx_ec_ref_hq2_ec_ref_hq_path_ctl (0x0c80) +#define cdc_rx_ec_ref_hq2_ec_ref_hq_cfg0 (0x0c84) +#define cdc_rx_ec_asrc0_clk_rst_ctl (0x0d00) +#define cdc_rx_ec_asrc0_ctl0 (0x0d04) +#define cdc_rx_ec_asrc0_ctl1 (0x0d08) +#define cdc_rx_ec_asrc0_fifo_ctl (0x0d0c) +#define cdc_rx_ec_asrc0_status_fmin_cntr_lsb (0x0d10) +#define cdc_rx_ec_asrc0_status_fmin_cntr_msb (0x0d14) +#define cdc_rx_ec_asrc0_status_fmax_cntr_lsb (0x0d18) +#define cdc_rx_ec_asrc0_status_fmax_cntr_msb (0x0d1c) +#define cdc_rx_ec_asrc0_status_fifo (0x0d20) +#define cdc_rx_ec_asrc1_clk_rst_ctl (0x0d40) +#define cdc_rx_ec_asrc1_ctl0 (0x0d44) +#define cdc_rx_ec_asrc1_ctl1 (0x0d48) +#define cdc_rx_ec_asrc1_fifo_ctl (0x0d4c) +#define cdc_rx_ec_asrc1_status_fmin_cntr_lsb (0x0d50) +#define cdc_rx_ec_asrc1_status_fmin_cntr_msb (0x0d54) +#define cdc_rx_ec_asrc1_status_fmax_cntr_lsb (0x0d58) +#define cdc_rx_ec_asrc1_status_fmax_cntr_msb (0x0d5c) +#define cdc_rx_ec_asrc1_status_fifo (0x0d60) +#define cdc_rx_ec_asrc2_clk_rst_ctl (0x0d80) +#define cdc_rx_ec_asrc2_ctl0 (0x0d84) +#define cdc_rx_ec_asrc2_ctl1 (0x0d88) +#define cdc_rx_ec_asrc2_fifo_ctl (0x0d8c) +#define cdc_rx_ec_asrc2_status_fmin_cntr_lsb (0x0d90) +#define cdc_rx_ec_asrc2_status_fmin_cntr_msb (0x0d94) +#define cdc_rx_ec_asrc2_status_fmax_cntr_lsb (0x0d98) +#define cdc_rx_ec_asrc2_status_fmax_cntr_msb (0x0d9c) +#define cdc_rx_ec_asrc2_status_fifo (0x0da0) +#define cdc_rx_dsd0_path_ctl (0x0f00) +#define cdc_rx_dsd0_cfg0 (0x0f04) +#define cdc_rx_dsd0_cfg1 (0x0f08) +#define cdc_rx_dsd0_cfg2 (0x0f0c) +#define cdc_rx_dsd1_path_ctl (0x0f80) +#define cdc_rx_dsd1_cfg0 (0x0f84) +#define cdc_rx_dsd1_cfg1 (0x0f88) +#define cdc_rx_dsd1_cfg2 (0x0f8c) +#define rx_max_offset (0x0f8c) + +#define mclk_freq 9600000 + +#define rx_macro_rates (sndrv_pcm_rate_8000 | sndrv_pcm_rate_16000 |\ + sndrv_pcm_rate_32000 | sndrv_pcm_rate_48000 |\ + sndrv_pcm_rate_96000 | sndrv_pcm_rate_192000 |\ + sndrv_pcm_rate_384000) +/* fractional rates */ +#define rx_macro_frac_rates (sndrv_pcm_rate_44100 | sndrv_pcm_rate_88200 |\ + sndrv_pcm_rate_176400 | sndrv_pcm_rate_352800) + +#define rx_macro_formats (sndrv_pcm_fmtbit_s16_le |\ + sndrv_pcm_fmtbit_s24_le |\ + sndrv_pcm_fmtbit_s24_3le | sndrv_pcm_fmtbit_s32_le) + +#define rx_macro_echo_rates (sndrv_pcm_rate_8000 | sndrv_pcm_rate_16000 |\ + sndrv_pcm_rate_48000) +#define rx_macro_echo_formats (sndrv_pcm_fmtbit_s16_le |\ + sndrv_pcm_fmtbit_s24_le |\ + sndrv_pcm_fmtbit_s24_3le) + +#define rx_macro_max_dma_ch_per_port 2 + +#define rx_macro_ec_mix_tx0_mask 0xf0 +#define rx_macro_ec_mix_tx1_mask 0x0f +#define rx_macro_ec_mix_tx2_mask 0x0f + +#define comp_max_coeff 25 +#define rx_num_clks_max 5 + +struct comp_coeff_val { + u8 lsb; + u8 msb; +}; + +enum { + hph_ulp, + hph_lohifi, + hph_mode_max, +}; + +static const struct comp_coeff_val comp_coeff_table[hph_mode_max][comp_max_coeff] = { + { + {0x40, 0x00}, + {0x4c, 0x00}, + {0x5a, 0x00}, + {0x6b, 0x00}, + {0x7f, 0x00}, + {0x97, 0x00}, + {0xb3, 0x00}, + {0xd5, 0x00}, + {0xfd, 0x00}, + {0x2d, 0x01}, + {0x66, 0x01}, + {0xa7, 0x01}, + {0xf8, 0x01}, + {0x57, 0x02}, + {0xc7, 0x02}, + {0x4b, 0x03}, + {0xe9, 0x03}, + {0xa3, 0x04}, + {0x7d, 0x05}, + {0x90, 0x06}, + {0xd1, 0x07}, + {0x49, 0x09}, + {0x00, 0x0b}, + {0x01, 0x0d}, + {0x59, 0x0f}, + }, + { + {0x40, 0x00}, + {0x4c, 0x00}, + {0x5a, 0x00}, + {0x6b, 0x00}, + {0x80, 0x00}, + {0x98, 0x00}, + {0xb4, 0x00}, + {0xd5, 0x00}, + {0xfe, 0x00}, + {0x2e, 0x01}, + {0x66, 0x01}, + {0xa9, 0x01}, + {0xf8, 0x01}, + {0x56, 0x02}, + {0xc4, 0x02}, + {0x4f, 0x03}, + {0xf0, 0x03}, + {0xae, 0x04}, + {0x8b, 0x05}, + {0x8e, 0x06}, + {0xbc, 0x07}, + {0x56, 0x09}, + {0x0f, 0x0b}, + {0x13, 0x0d}, + {0x6f, 0x0f}, + }, +}; + +struct rx_macro_reg_mask_val { + u16 reg; + u8 mask; + u8 val; +}; + +enum { + interp_hphl, + interp_hphr, + interp_aux, + interp_max +}; + +enum { + rx_macro_rx0, + rx_macro_rx1, + rx_macro_rx2, + rx_macro_rx3, + rx_macro_rx4, + rx_macro_rx5, + rx_macro_ports_max +}; + +enum { + rx_macro_comp1, /* hph_l */ + rx_macro_comp2, /* hph_r */ + rx_macro_comp_max +}; + +enum { + rx_macro_ec0_mux = 0, + rx_macro_ec1_mux, + rx_macro_ec2_mux, + rx_macro_ec_mux_max, +}; + +enum { + intn_1_inp_sel_zero = 0, + intn_1_inp_sel_dec0, + intn_1_inp_sel_dec1, + intn_1_inp_sel_iir0, + intn_1_inp_sel_iir1, + intn_1_inp_sel_rx0, + intn_1_inp_sel_rx1, + intn_1_inp_sel_rx2, + intn_1_inp_sel_rx3, + intn_1_inp_sel_rx4, + intn_1_inp_sel_rx5, +}; + +enum { + intn_2_inp_sel_zero = 0, + intn_2_inp_sel_rx0, + intn_2_inp_sel_rx1, + intn_2_inp_sel_rx2, + intn_2_inp_sel_rx3, + intn_2_inp_sel_rx4, + intn_2_inp_sel_rx5, +}; + +enum { + interp_main_path, + interp_mix_path, +}; + +struct interp_sample_rate { + int sample_rate; + int rate_val; +}; + +static struct interp_sample_rate sr_val_tbl[] = { + {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5}, + {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xa}, + {176400, 0xb}, {352800, 0xc}, +}; + +enum { + rx_macro_aif_invalid = 0, + rx_macro_aif1_pb, + rx_macro_aif2_pb, + rx_macro_aif3_pb, + rx_macro_aif4_pb, + rx_macro_aif_echo, + rx_macro_max_dais, +}; + +enum { + rx_macro_aif1_cap = 0, + rx_macro_aif2_cap, + rx_macro_aif3_cap, + rx_macro_max_aif_cap_dais +}; + +struct rx_macro { + struct device *dev; + int comp_enabled[rx_macro_comp_max]; + /* main path clock users count */ + int main_clk_users[interp_max]; + int rx_port_value[rx_macro_ports_max]; + u16 prim_int_users[interp_max]; + int rx_mclk_users; + bool reset_swr; + int clsh_users; + int rx_mclk_cnt; + bool is_ear_mode_on; + bool hph_pwr_mode; + bool hph_hd2_mode; + struct snd_soc_component *component; + unsigned long active_ch_mask[rx_macro_max_dais]; + unsigned long active_ch_cnt[rx_macro_max_dais]; + u16 bit_width[rx_macro_max_dais]; + int is_softclip_on; + int is_aux_hpf_on; + int softclip_clk_users; + + struct regmap *regmap; + struct clk_bulk_data clks[rx_num_clks_max]; + struct clk_hw hw; +}; +#define to_rx_macro(_hw) container_of(_hw, struct rx_macro, hw) + +static const declare_tlv_db_scale(digital_gain, -8400, 100, -8400); + +static const char *const rx_macro_hph_pwr_mode_text[] = { + "ulp", "lohifi" +}; + +static const struct soc_enum rx_macro_hph_pwr_mode_enum = + soc_enum_single_ext(2, rx_macro_hph_pwr_mode_text); + +static const struct reg_default rx_defaults[] = { + /* rx macro */ + { cdc_rx_top_top_cfg0, 0x00 }, + { cdc_rx_top_swr_ctrl, 0x00 }, + { cdc_rx_top_debug, 0x00 }, + { cdc_rx_top_debug_bus, 0x00 }, + { cdc_rx_top_debug_en0, 0x00 }, + { cdc_rx_top_debug_en1, 0x00 }, + { cdc_rx_top_debug_en2, 0x00 }, + { cdc_rx_top_hphl_comp_wr_lsb, 0x00 }, + { cdc_rx_top_hphl_comp_wr_msb, 0x00 }, + { cdc_rx_top_hphl_comp_lut, 0x00 }, + { cdc_rx_top_hphl_comp_rd_lsb, 0x00 }, + { cdc_rx_top_hphl_comp_rd_msb, 0x00 }, + { cdc_rx_top_hphr_comp_wr_lsb, 0x00 }, + { cdc_rx_top_hphr_comp_wr_msb, 0x00 }, + { cdc_rx_top_hphr_comp_lut, 0x00 }, + { cdc_rx_top_hphr_comp_rd_lsb, 0x00 }, + { cdc_rx_top_hphr_comp_rd_msb, 0x00 }, + { cdc_rx_top_dsd0_debug_cfg0, 0x11 }, + { cdc_rx_top_dsd0_debug_cfg1, 0x20 }, + { cdc_rx_top_dsd0_debug_cfg2, 0x00 }, + { cdc_rx_top_dsd0_debug_cfg3, 0x00 }, + { cdc_rx_top_dsd1_debug_cfg0, 0x11 }, + { cdc_rx_top_dsd1_debug_cfg1, 0x20 }, + { cdc_rx_top_dsd1_debug_cfg2, 0x00 }, + { cdc_rx_top_dsd1_debug_cfg3, 0x00 }, + { cdc_rx_top_rx_i2s_ctl, 0x0c }, + { cdc_rx_top_tx_i2s2_ctl, 0x0c }, + { cdc_rx_top_i2s_clk, 0x0c }, + { cdc_rx_top_i2s_reset, 0x00 }, + { cdc_rx_top_i2s_mux, 0x00 }, + { cdc_rx_clk_rst_ctrl_mclk_control, 0x00 }, + { cdc_rx_clk_rst_ctrl_fs_cnt_control, 0x00 }, + { cdc_rx_clk_rst_ctrl_swr_control, 0x00 }, + { cdc_rx_clk_rst_ctrl_dsd_control, 0x00 }, + { cdc_rx_clk_rst_ctrl_asrc_share_control, 0x08 }, + { cdc_rx_softclip_crc, 0x00 }, + { cdc_rx_softclip_softclip_ctrl, 0x38 }, + { cdc_rx_inp_mux_rx_int0_cfg0, 0x00 }, + { cdc_rx_inp_mux_rx_int0_cfg1, 0x00 }, + { cdc_rx_inp_mux_rx_int1_cfg0, 0x00 }, + { cdc_rx_inp_mux_rx_int1_cfg1, 0x00 }, + { cdc_rx_inp_mux_rx_int2_cfg0, 0x00 }, + { cdc_rx_inp_mux_rx_int2_cfg1, 0x00 }, + { cdc_rx_inp_mux_rx_mix_cfg4, 0x00 }, + { cdc_rx_inp_mux_rx_mix_cfg5, 0x00 }, + { cdc_rx_inp_mux_sidetone_src_cfg0, 0x00 }, + { cdc_rx_clsh_crc, 0x00 }, + { cdc_rx_clsh_dly_ctrl, 0x03 }, + { cdc_rx_clsh_decay_ctrl, 0x02 }, + { cdc_rx_clsh_hph_v_pa, 0x1c }, + { cdc_rx_clsh_ear_v_pa, 0x39 }, + { cdc_rx_clsh_hph_v_hd, 0x0c }, + { cdc_rx_clsh_ear_v_hd, 0x0c }, + { cdc_rx_clsh_k1_msb, 0x01 }, + { cdc_rx_clsh_k1_lsb, 0x00 }, + { cdc_rx_clsh_k2_msb, 0x00 }, + { cdc_rx_clsh_k2_lsb, 0x80 }, + { cdc_rx_clsh_idle_ctrl, 0x00 }, + { cdc_rx_clsh_idle_hph, 0x00 }, + { cdc_rx_clsh_idle_ear, 0x00 }, + { cdc_rx_clsh_test0, 0x07 }, + { cdc_rx_clsh_test1, 0x00 }, + { cdc_rx_clsh_ovr_vref, 0x00 }, + { cdc_rx_clsh_clsg_ctl, 0x02 }, + { cdc_rx_clsh_clsg_cfg1, 0x9a }, + { cdc_rx_clsh_clsg_cfg2, 0x10 }, + { cdc_rx_bcl_vbat_path_ctl, 0x00 }, + { cdc_rx_bcl_vbat_cfg, 0x10 }, + { cdc_rx_bcl_vbat_adc_cal1, 0x00 }, + { cdc_rx_bcl_vbat_adc_cal2, 0x00 }, + { cdc_rx_bcl_vbat_adc_cal3, 0x04 }, + { cdc_rx_bcl_vbat_pk_est1, 0xe0 }, + { cdc_rx_bcl_vbat_pk_est2, 0x01 }, + { cdc_rx_bcl_vbat_pk_est3, 0x40 }, + { cdc_rx_bcl_vbat_rf_proc1, 0x2a }, + { cdc_rx_bcl_vbat_rf_proc1, 0x00 }, + { cdc_rx_bcl_vbat_tac1, 0x00 }, + { cdc_rx_bcl_vbat_tac2, 0x18 }, + { cdc_rx_bcl_vbat_tac3, 0x18 }, + { cdc_rx_bcl_vbat_tac4, 0x03 }, + { cdc_rx_bcl_vbat_gain_upd1, 0x01 }, + { cdc_rx_bcl_vbat_gain_upd2, 0x00 }, + { cdc_rx_bcl_vbat_gain_upd3, 0x00 }, + { cdc_rx_bcl_vbat_gain_upd4, 0x64 }, + { cdc_rx_bcl_vbat_gain_upd5, 0x01 }, + { cdc_rx_bcl_vbat_debug1, 0x00 }, + { cdc_rx_bcl_vbat_gain_upd_mon, 0x00 }, + { cdc_rx_bcl_vbat_gain_mon_val, 0x00 }, + { cdc_rx_bcl_vbat_ban, 0x0c }, + { cdc_rx_bcl_vbat_bcl_gain_upd1, 0x00 }, + { cdc_rx_bcl_vbat_bcl_gain_upd2, 0x77 }, + { cdc_rx_bcl_vbat_bcl_gain_upd3, 0x01 }, + { cdc_rx_bcl_vbat_bcl_gain_upd4, 0x00 }, + { cdc_rx_bcl_vbat_bcl_gain_upd5, 0x4b }, + { cdc_rx_bcl_vbat_bcl_gain_upd6, 0x00 }, + { cdc_rx_bcl_vbat_bcl_gain_upd7, 0x01 }, + { cdc_rx_bcl_vbat_bcl_gain_upd8, 0x00 }, + { cdc_rx_bcl_vbat_bcl_gain_upd9, 0x00 }, + { cdc_rx_bcl_vbat_attn1, 0x04 }, + { cdc_rx_bcl_vbat_attn2, 0x08 }, + { cdc_rx_bcl_vbat_attn3, 0x0c }, + { cdc_rx_bcl_vbat_decode_ctl1, 0xe0 }, + { cdc_rx_bcl_vbat_decode_ctl2, 0x00 }, + { cdc_rx_bcl_vbat_decode_cfg1, 0x00 }, + { cdc_rx_bcl_vbat_decode_cfg2, 0x00 }, + { cdc_rx_bcl_vbat_decode_cfg3, 0x00 }, + { cdc_rx_bcl_vbat_decode_cfg4, 0x00 }, + { cdc_rx_bcl_vbat_decode_st, 0x00 }, + { cdc_rx_intr_ctrl_cfg, 0x00 }, + { cdc_rx_intr_ctrl_clr_commit, 0x00 }, + { cdc_rx_intr_ctrl_pin1_mask0, 0xff }, + { cdc_rx_intr_ctrl_pin1_status0, 0x00 }, + { cdc_rx_intr_ctrl_pin1_clear0, 0x00 }, + { cdc_rx_intr_ctrl_pin2_mask0, 0xff }, + { cdc_rx_intr_ctrl_pin2_status0, 0x00 }, + { cdc_rx_intr_ctrl_pin2_clear0, 0x00 }, + { cdc_rx_intr_ctrl_level0, 0x00 }, + { cdc_rx_intr_ctrl_bypass0, 0x00 }, + { cdc_rx_intr_ctrl_set0, 0x00 }, + { cdc_rx_rx0_rx_path_ctl, 0x04 }, + { cdc_rx_rx0_rx_path_cfg0, 0x00 }, + { cdc_rx_rx0_rx_path_cfg1, 0x64 }, + { cdc_rx_rx0_rx_path_cfg2, 0x8f }, + { cdc_rx_rx0_rx_path_cfg3, 0x00 }, + { cdc_rx_rx0_rx_vol_ctl, 0x00 }, + { cdc_rx_rx0_rx_path_mix_ctl, 0x04 }, + { cdc_rx_rx0_rx_path_mix_cfg, 0x7e }, + { cdc_rx_rx0_rx_vol_mix_ctl, 0x00 }, + { cdc_rx_rx0_rx_path_sec1, 0x08 }, + { cdc_rx_rx0_rx_path_sec2, 0x00 }, + { cdc_rx_rx0_rx_path_sec3, 0x00 }, + { cdc_rx_rx0_rx_path_sec4, 0x00 }, + { cdc_rx_rx0_rx_path_sec7, 0x00 }, + { cdc_rx_rx0_rx_path_mix_sec0, 0x08 }, + { cdc_rx_rx0_rx_path_mix_sec1, 0x00 }, + { cdc_rx_rx0_rx_path_dsm_ctl, 0x08 }, + { cdc_rx_rx0_rx_path_dsm_data1, 0x00 }, + { cdc_rx_rx0_rx_path_dsm_data2, 0x00 }, + { cdc_rx_rx0_rx_path_dsm_data3, 0x00 }, + { cdc_rx_rx0_rx_path_dsm_data4, 0x55 }, + { cdc_rx_rx0_rx_path_dsm_data5, 0x55 }, + { cdc_rx_rx0_rx_path_dsm_data6, 0x55 }, + { cdc_rx_rx1_rx_path_ctl, 0x04 }, + { cdc_rx_rx1_rx_path_cfg0, 0x00 }, + { cdc_rx_rx1_rx_path_cfg1, 0x64 }, + { cdc_rx_rx1_rx_path_cfg2, 0x8f }, + { cdc_rx_rx1_rx_path_cfg3, 0x00 }, + { cdc_rx_rx1_rx_vol_ctl, 0x00 }, + { cdc_rx_rx1_rx_path_mix_ctl, 0x04 }, + { cdc_rx_rx1_rx_path_mix_cfg, 0x7e }, + { cdc_rx_rx1_rx_vol_mix_ctl, 0x00 }, + { cdc_rx_rx1_rx_path_sec1, 0x08 }, + { cdc_rx_rx1_rx_path_sec2, 0x00 }, + { cdc_rx_rx1_rx_path_sec3, 0x00 }, + { cdc_rx_rx1_rx_path_sec4, 0x00 }, + { cdc_rx_rx1_rx_path_sec7, 0x00 }, + { cdc_rx_rx1_rx_path_mix_sec0, 0x08 }, + { cdc_rx_rx1_rx_path_mix_sec1, 0x00 }, + { cdc_rx_rx1_rx_path_dsm_ctl, 0x08 }, + { cdc_rx_rx1_rx_path_dsm_data1, 0x00 }, + { cdc_rx_rx1_rx_path_dsm_data2, 0x00 }, + { cdc_rx_rx1_rx_path_dsm_data3, 0x00 }, + { cdc_rx_rx1_rx_path_dsm_data4, 0x55 }, + { cdc_rx_rx1_rx_path_dsm_data5, 0x55 }, + { cdc_rx_rx1_rx_path_dsm_data6, 0x55 }, + { cdc_rx_rx2_rx_path_ctl, 0x04 }, + { cdc_rx_rx2_rx_path_cfg0, 0x00 }, + { cdc_rx_rx2_rx_path_cfg1, 0x64 }, + { cdc_rx_rx2_rx_path_cfg2, 0x8f }, + { cdc_rx_rx2_rx_path_cfg3, 0x00 }, + { cdc_rx_rx2_rx_vol_ctl, 0x00 }, + { cdc_rx_rx2_rx_path_mix_ctl, 0x04 }, + { cdc_rx_rx2_rx_path_mix_cfg, 0x7e }, + { cdc_rx_rx2_rx_vol_mix_ctl, 0x00 }, + { cdc_rx_rx2_rx_path_sec0, 0x04 }, + { cdc_rx_rx2_rx_path_sec1, 0x08 }, + { cdc_rx_rx2_rx_path_sec2, 0x00 }, + { cdc_rx_rx2_rx_path_sec3, 0x00 }, + { cdc_rx_rx2_rx_path_sec4, 0x00 }, + { cdc_rx_rx2_rx_path_sec5, 0x00 }, + { cdc_rx_rx2_rx_path_sec6, 0x00 }, + { cdc_rx_rx2_rx_path_sec7, 0x00 }, + { cdc_rx_rx2_rx_path_mix_sec0, 0x08 }, + { cdc_rx_rx2_rx_path_mix_sec1, 0x00 }, + { cdc_rx_rx2_rx_path_dsm_ctl, 0x00 }, + { cdc_rx_idle_detect_path_ctl, 0x00 }, + { cdc_rx_idle_detect_cfg0, 0x07 }, + { cdc_rx_idle_detect_cfg1, 0x3c }, + { cdc_rx_idle_detect_cfg2, 0x00 }, + { cdc_rx_idle_detect_cfg3, 0x00 }, + { cdc_rx_compander0_ctl0, 0x60 }, + { cdc_rx_compander0_ctl1, 0xdb }, + { cdc_rx_compander0_ctl2, 0xff }, + { cdc_rx_compander0_ctl3, 0x35 }, + { cdc_rx_compander0_ctl4, 0xff }, + { cdc_rx_compander0_ctl5, 0x00 }, + { cdc_rx_compander0_ctl6, 0x01 }, + { cdc_rx_compander0_ctl7, 0x28 }, + { cdc_rx_compander1_ctl0, 0x60 }, + { cdc_rx_compander1_ctl1, 0xdb }, + { cdc_rx_compander1_ctl2, 0xff }, + { cdc_rx_compander1_ctl3, 0x35 }, + { cdc_rx_compander1_ctl4, 0xff }, + { cdc_rx_compander1_ctl5, 0x00 }, + { cdc_rx_compander1_ctl6, 0x01 }, + { cdc_rx_compander1_ctl7, 0x28 }, + { cdc_rx_sidetone_iir0_iir_path_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b1_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b2_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b3_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b4_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b5_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b6_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b7_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_gain_b8_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_ctl, 0x40 }, + { cdc_rx_sidetone_iir0_iir_gain_timer_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_coef_b1_ctl, 0x00 }, + { cdc_rx_sidetone_iir0_iir_coef_b2_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_path_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b1_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b2_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b3_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b4_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b5_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b6_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b7_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_gain_b8_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_ctl, 0x40 }, + { cdc_rx_sidetone_iir1_iir_gain_timer_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_coef_b1_ctl, 0x00 }, + { cdc_rx_sidetone_iir1_iir_coef_b2_ctl, 0x00 }, + { cdc_rx_iir_inp_mux_iir0_mix_cfg0, 0x00 }, + { cdc_rx_iir_inp_mux_iir0_mix_cfg1, 0x00 }, + { cdc_rx_iir_inp_mux_iir0_mix_cfg2, 0x00 }, + { cdc_rx_iir_inp_mux_iir0_mix_cfg3, 0x00 }, + { cdc_rx_iir_inp_mux_iir1_mix_cfg0, 0x00 }, + { cdc_rx_iir_inp_mux_iir1_mix_cfg1, 0x00 }, + { cdc_rx_iir_inp_mux_iir1_mix_cfg2, 0x00 }, + { cdc_rx_iir_inp_mux_iir1_mix_cfg3, 0x00 }, + { cdc_rx_sidetone_src0_st_src_path_ctl, 0x04 }, + { cdc_rx_sidetone_src0_st_src_path_cfg1, 0x00 }, + { cdc_rx_sidetone_src1_st_src_path_ctl, 0x04 }, + { cdc_rx_sidetone_src1_st_src_path_cfg1, 0x00 }, + { cdc_rx_ec_ref_hq0_ec_ref_hq_path_ctl, 0x00 }, + { cdc_rx_ec_ref_hq0_ec_ref_hq_cfg0, 0x01 }, + { cdc_rx_ec_ref_hq1_ec_ref_hq_path_ctl, 0x00 }, + { cdc_rx_ec_ref_hq1_ec_ref_hq_cfg0, 0x01 }, + { cdc_rx_ec_ref_hq2_ec_ref_hq_path_ctl, 0x00 }, + { cdc_rx_ec_ref_hq2_ec_ref_hq_cfg0, 0x01 }, + { cdc_rx_ec_asrc0_clk_rst_ctl, 0x00 }, + { cdc_rx_ec_asrc0_ctl0, 0x00 }, + { cdc_rx_ec_asrc0_ctl1, 0x00 }, + { cdc_rx_ec_asrc0_fifo_ctl, 0xa8 }, + { cdc_rx_ec_asrc0_status_fmin_cntr_lsb, 0x00 }, + { cdc_rx_ec_asrc0_status_fmin_cntr_msb, 0x00 }, + { cdc_rx_ec_asrc0_status_fmax_cntr_lsb, 0x00 }, + { cdc_rx_ec_asrc0_status_fmax_cntr_msb, 0x00 }, + { cdc_rx_ec_asrc0_status_fifo, 0x00 }, + { cdc_rx_ec_asrc1_clk_rst_ctl, 0x00 }, + { cdc_rx_ec_asrc1_ctl0, 0x00 }, + { cdc_rx_ec_asrc1_ctl1, 0x00 }, + { cdc_rx_ec_asrc1_fifo_ctl, 0xa8 }, + { cdc_rx_ec_asrc1_status_fmin_cntr_lsb, 0x00 }, + { cdc_rx_ec_asrc1_status_fmin_cntr_msb, 0x00 }, + { cdc_rx_ec_asrc1_status_fmax_cntr_lsb, 0x00 }, + { cdc_rx_ec_asrc1_status_fmax_cntr_msb, 0x00 }, + { cdc_rx_ec_asrc1_status_fifo, 0x00 }, + { cdc_rx_ec_asrc2_clk_rst_ctl, 0x00 }, + { cdc_rx_ec_asrc2_ctl0, 0x00 }, + { cdc_rx_ec_asrc2_ctl1, 0x00 }, + { cdc_rx_ec_asrc2_fifo_ctl, 0xa8 }, + { cdc_rx_ec_asrc2_status_fmin_cntr_lsb, 0x00 }, + { cdc_rx_ec_asrc2_status_fmin_cntr_msb, 0x00 }, + { cdc_rx_ec_asrc2_status_fmax_cntr_lsb, 0x00 }, + { cdc_rx_ec_asrc2_status_fmax_cntr_msb, 0x00 }, + { cdc_rx_ec_asrc2_status_fifo, 0x00 }, + { cdc_rx_dsd0_path_ctl, 0x00 }, + { cdc_rx_dsd0_cfg0, 0x00 }, + { cdc_rx_dsd0_cfg1, 0x62 }, + { cdc_rx_dsd0_cfg2, 0x96 }, + { cdc_rx_dsd1_path_ctl, 0x00 }, + { cdc_rx_dsd1_cfg0, 0x00 }, + { cdc_rx_dsd1_cfg1, 0x62 }, + { cdc_rx_dsd1_cfg2, 0x96 }, +}; + +static bool rx_is_wronly_register(struct device *dev, + unsigned int reg) +{ + switch (reg) { + case cdc_rx_bcl_vbat_gain_upd_mon: + case cdc_rx_intr_ctrl_clr_commit: + case cdc_rx_intr_ctrl_pin1_clear0: + case cdc_rx_intr_ctrl_pin2_clear0: + return true; + } + + return false; +} + +static bool rx_is_volatile_register(struct device *dev, unsigned int reg) +{ + /* update volatile list for rx/tx macros */ + switch (reg) { + case cdc_rx_top_hphl_comp_rd_lsb: + case cdc_rx_top_hphl_comp_wr_lsb: + case cdc_rx_top_hphl_comp_rd_msb: + case cdc_rx_top_hphl_comp_wr_msb: + case cdc_rx_top_hphr_comp_rd_lsb: + case cdc_rx_top_hphr_comp_wr_lsb: + case cdc_rx_top_hphr_comp_rd_msb: + case cdc_rx_top_hphr_comp_wr_msb: + case cdc_rx_top_dsd0_debug_cfg2: + case cdc_rx_top_dsd1_debug_cfg2: + case cdc_rx_bcl_vbat_gain_mon_val: + case cdc_rx_bcl_vbat_decode_st: + case cdc_rx_intr_ctrl_pin1_status0: + case cdc_rx_intr_ctrl_pin2_status0: + case cdc_rx_compander0_ctl6: + case cdc_rx_compander1_ctl6: + case cdc_rx_ec_asrc0_status_fmin_cntr_lsb: + case cdc_rx_ec_asrc0_status_fmin_cntr_msb: + case cdc_rx_ec_asrc0_status_fmax_cntr_lsb: + case cdc_rx_ec_asrc0_status_fmax_cntr_msb: + case cdc_rx_ec_asrc0_status_fifo: + case cdc_rx_ec_asrc1_status_fmin_cntr_lsb: + case cdc_rx_ec_asrc1_status_fmin_cntr_msb: + case cdc_rx_ec_asrc1_status_fmax_cntr_lsb: + case cdc_rx_ec_asrc1_status_fmax_cntr_msb: + case cdc_rx_ec_asrc1_status_fifo: + case cdc_rx_ec_asrc2_status_fmin_cntr_lsb: + case cdc_rx_ec_asrc2_status_fmin_cntr_msb: + case cdc_rx_ec_asrc2_status_fmax_cntr_lsb: + case cdc_rx_ec_asrc2_status_fmax_cntr_msb: + case cdc_rx_ec_asrc2_status_fifo: + return true; + } + return false; +} + +static bool rx_is_rw_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case cdc_rx_top_top_cfg0: + case cdc_rx_top_swr_ctrl: + case cdc_rx_top_debug: + case cdc_rx_top_debug_bus: + case cdc_rx_top_debug_en0: + case cdc_rx_top_debug_en1: + case cdc_rx_top_debug_en2: + case cdc_rx_top_hphl_comp_wr_lsb: + case cdc_rx_top_hphl_comp_wr_msb: + case cdc_rx_top_hphl_comp_lut: + case cdc_rx_top_hphr_comp_wr_lsb: + case cdc_rx_top_hphr_comp_wr_msb: + case cdc_rx_top_hphr_comp_lut: + case cdc_rx_top_dsd0_debug_cfg0: + case cdc_rx_top_dsd0_debug_cfg1: + case cdc_rx_top_dsd0_debug_cfg3: + case cdc_rx_top_dsd1_debug_cfg0: + case cdc_rx_top_dsd1_debug_cfg1: + case cdc_rx_top_dsd1_debug_cfg3: + case cdc_rx_top_rx_i2s_ctl: + case cdc_rx_top_tx_i2s2_ctl: + case cdc_rx_top_i2s_clk: + case cdc_rx_top_i2s_reset: + case cdc_rx_top_i2s_mux: + case cdc_rx_clk_rst_ctrl_mclk_control: + case cdc_rx_clk_rst_ctrl_fs_cnt_control: + case cdc_rx_clk_rst_ctrl_swr_control: + case cdc_rx_clk_rst_ctrl_dsd_control: + case cdc_rx_clk_rst_ctrl_asrc_share_control: + case cdc_rx_softclip_crc: + case cdc_rx_softclip_softclip_ctrl: + case cdc_rx_inp_mux_rx_int0_cfg0: + case cdc_rx_inp_mux_rx_int0_cfg1: + case cdc_rx_inp_mux_rx_int1_cfg0: + case cdc_rx_inp_mux_rx_int1_cfg1: + case cdc_rx_inp_mux_rx_int2_cfg0: + case cdc_rx_inp_mux_rx_int2_cfg1: + case cdc_rx_inp_mux_rx_mix_cfg4: + case cdc_rx_inp_mux_rx_mix_cfg5: + case cdc_rx_inp_mux_sidetone_src_cfg0: + case cdc_rx_clsh_crc: + case cdc_rx_clsh_dly_ctrl: + case cdc_rx_clsh_decay_ctrl: + case cdc_rx_clsh_hph_v_pa: + case cdc_rx_clsh_ear_v_pa: + case cdc_rx_clsh_hph_v_hd: + case cdc_rx_clsh_ear_v_hd: + case cdc_rx_clsh_k1_msb: + case cdc_rx_clsh_k1_lsb: + case cdc_rx_clsh_k2_msb: + case cdc_rx_clsh_k2_lsb: + case cdc_rx_clsh_idle_ctrl: + case cdc_rx_clsh_idle_hph: + case cdc_rx_clsh_idle_ear: + case cdc_rx_clsh_test0: + case cdc_rx_clsh_test1: + case cdc_rx_clsh_ovr_vref: + case cdc_rx_clsh_clsg_ctl: + case cdc_rx_clsh_clsg_cfg1: + case cdc_rx_clsh_clsg_cfg2: + case cdc_rx_bcl_vbat_path_ctl: + case cdc_rx_bcl_vbat_cfg: + case cdc_rx_bcl_vbat_adc_cal1: + case cdc_rx_bcl_vbat_adc_cal2: + case cdc_rx_bcl_vbat_adc_cal3: + case cdc_rx_bcl_vbat_pk_est1: + case cdc_rx_bcl_vbat_pk_est2: + case cdc_rx_bcl_vbat_pk_est3: + case cdc_rx_bcl_vbat_rf_proc1: + case cdc_rx_bcl_vbat_rf_proc2: + case cdc_rx_bcl_vbat_tac1: + case cdc_rx_bcl_vbat_tac2: + case cdc_rx_bcl_vbat_tac3: + case cdc_rx_bcl_vbat_tac4: + case cdc_rx_bcl_vbat_gain_upd1: + case cdc_rx_bcl_vbat_gain_upd2: + case cdc_rx_bcl_vbat_gain_upd3: + case cdc_rx_bcl_vbat_gain_upd4: + case cdc_rx_bcl_vbat_gain_upd5: + case cdc_rx_bcl_vbat_debug1: + case cdc_rx_bcl_vbat_ban: + case cdc_rx_bcl_vbat_bcl_gain_upd1: + case cdc_rx_bcl_vbat_bcl_gain_upd2: + case cdc_rx_bcl_vbat_bcl_gain_upd3: + case cdc_rx_bcl_vbat_bcl_gain_upd4: + case cdc_rx_bcl_vbat_bcl_gain_upd5: + case cdc_rx_bcl_vbat_bcl_gain_upd6: + case cdc_rx_bcl_vbat_bcl_gain_upd7: + case cdc_rx_bcl_vbat_bcl_gain_upd8: + case cdc_rx_bcl_vbat_bcl_gain_upd9: + case cdc_rx_bcl_vbat_attn1: + case cdc_rx_bcl_vbat_attn2: + case cdc_rx_bcl_vbat_attn3: + case cdc_rx_bcl_vbat_decode_ctl1: + case cdc_rx_bcl_vbat_decode_ctl2: + case cdc_rx_bcl_vbat_decode_cfg1: + case cdc_rx_bcl_vbat_decode_cfg2: + case cdc_rx_bcl_vbat_decode_cfg3: + case cdc_rx_bcl_vbat_decode_cfg4: + case cdc_rx_intr_ctrl_cfg: + case cdc_rx_intr_ctrl_pin1_mask0: + case cdc_rx_intr_ctrl_pin2_mask0: + case cdc_rx_intr_ctrl_level0: + case cdc_rx_intr_ctrl_bypass0: + case cdc_rx_intr_ctrl_set0: + case cdc_rx_rx0_rx_path_ctl: + case cdc_rx_rx0_rx_path_cfg0: + case cdc_rx_rx0_rx_path_cfg1: + case cdc_rx_rx0_rx_path_cfg2: + case cdc_rx_rx0_rx_path_cfg3: + case cdc_rx_rx0_rx_vol_ctl: + case cdc_rx_rx0_rx_path_mix_ctl: + case cdc_rx_rx0_rx_path_mix_cfg: + case cdc_rx_rx0_rx_vol_mix_ctl: + case cdc_rx_rx0_rx_path_sec1: + case cdc_rx_rx0_rx_path_sec2: + case cdc_rx_rx0_rx_path_sec3: + case cdc_rx_rx0_rx_path_sec4: + case cdc_rx_rx0_rx_path_sec7: + case cdc_rx_rx0_rx_path_mix_sec0: + case cdc_rx_rx0_rx_path_mix_sec1: + case cdc_rx_rx0_rx_path_dsm_ctl: + case cdc_rx_rx0_rx_path_dsm_data1: + case cdc_rx_rx0_rx_path_dsm_data2: + case cdc_rx_rx0_rx_path_dsm_data3: + case cdc_rx_rx0_rx_path_dsm_data4: + case cdc_rx_rx0_rx_path_dsm_data5: + case cdc_rx_rx0_rx_path_dsm_data6: + case cdc_rx_rx1_rx_path_ctl: + case cdc_rx_rx1_rx_path_cfg0: + case cdc_rx_rx1_rx_path_cfg1: + case cdc_rx_rx1_rx_path_cfg2: + case cdc_rx_rx1_rx_path_cfg3: + case cdc_rx_rx1_rx_vol_ctl: + case cdc_rx_rx1_rx_path_mix_ctl: + case cdc_rx_rx1_rx_path_mix_cfg: + case cdc_rx_rx1_rx_vol_mix_ctl: + case cdc_rx_rx1_rx_path_sec1: + case cdc_rx_rx1_rx_path_sec2: + case cdc_rx_rx1_rx_path_sec3: + case cdc_rx_rx1_rx_path_sec4: + case cdc_rx_rx1_rx_path_sec7: + case cdc_rx_rx1_rx_path_mix_sec0: + case cdc_rx_rx1_rx_path_mix_sec1: + case cdc_rx_rx1_rx_path_dsm_ctl: + case cdc_rx_rx1_rx_path_dsm_data1: + case cdc_rx_rx1_rx_path_dsm_data2: + case cdc_rx_rx1_rx_path_dsm_data3: + case cdc_rx_rx1_rx_path_dsm_data4: + case cdc_rx_rx1_rx_path_dsm_data5: + case cdc_rx_rx1_rx_path_dsm_data6: + case cdc_rx_rx2_rx_path_ctl: + case cdc_rx_rx2_rx_path_cfg0: + case cdc_rx_rx2_rx_path_cfg1: + case cdc_rx_rx2_rx_path_cfg2: + case cdc_rx_rx2_rx_path_cfg3: + case cdc_rx_rx2_rx_vol_ctl: + case cdc_rx_rx2_rx_path_mix_ctl: + case cdc_rx_rx2_rx_path_mix_cfg: + case cdc_rx_rx2_rx_vol_mix_ctl: + case cdc_rx_rx2_rx_path_sec0: + case cdc_rx_rx2_rx_path_sec1: + case cdc_rx_rx2_rx_path_sec2: + case cdc_rx_rx2_rx_path_sec3: + case cdc_rx_rx2_rx_path_sec4: + case cdc_rx_rx2_rx_path_sec5: + case cdc_rx_rx2_rx_path_sec6: + case cdc_rx_rx2_rx_path_sec7: + case cdc_rx_rx2_rx_path_mix_sec0: + case cdc_rx_rx2_rx_path_mix_sec1: + case cdc_rx_rx2_rx_path_dsm_ctl: + case cdc_rx_idle_detect_path_ctl: + case cdc_rx_idle_detect_cfg0: + case cdc_rx_idle_detect_cfg1: + case cdc_rx_idle_detect_cfg2: + case cdc_rx_idle_detect_cfg3: + case cdc_rx_compander0_ctl0: + case cdc_rx_compander0_ctl1: + case cdc_rx_compander0_ctl2: + case cdc_rx_compander0_ctl3: + case cdc_rx_compander0_ctl4: + case cdc_rx_compander0_ctl5: + case cdc_rx_compander0_ctl7: + case cdc_rx_compander1_ctl0: + case cdc_rx_compander1_ctl1: + case cdc_rx_compander1_ctl2: + case cdc_rx_compander1_ctl3: + case cdc_rx_compander1_ctl4: + case cdc_rx_compander1_ctl5: + case cdc_rx_compander1_ctl7: + case cdc_rx_sidetone_iir0_iir_path_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b1_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b2_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b3_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b4_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b5_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b6_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b7_ctl: + case cdc_rx_sidetone_iir0_iir_gain_b8_ctl: + case cdc_rx_sidetone_iir0_iir_ctl: + case cdc_rx_sidetone_iir0_iir_gain_timer_ctl: + case cdc_rx_sidetone_iir0_iir_coef_b1_ctl: + case cdc_rx_sidetone_iir0_iir_coef_b2_ctl: + case cdc_rx_sidetone_iir1_iir_path_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b1_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b2_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b3_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b4_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b5_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b6_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b7_ctl: + case cdc_rx_sidetone_iir1_iir_gain_b8_ctl: + case cdc_rx_sidetone_iir1_iir_ctl: + case cdc_rx_sidetone_iir1_iir_gain_timer_ctl: + case cdc_rx_sidetone_iir1_iir_coef_b1_ctl: + case cdc_rx_sidetone_iir1_iir_coef_b2_ctl: + case cdc_rx_iir_inp_mux_iir0_mix_cfg0: + case cdc_rx_iir_inp_mux_iir0_mix_cfg1: + case cdc_rx_iir_inp_mux_iir0_mix_cfg2: + case cdc_rx_iir_inp_mux_iir0_mix_cfg3: + case cdc_rx_iir_inp_mux_iir1_mix_cfg0: + case cdc_rx_iir_inp_mux_iir1_mix_cfg1: + case cdc_rx_iir_inp_mux_iir1_mix_cfg2: + case cdc_rx_iir_inp_mux_iir1_mix_cfg3: + case cdc_rx_sidetone_src0_st_src_path_ctl: + case cdc_rx_sidetone_src0_st_src_path_cfg1: + case cdc_rx_sidetone_src1_st_src_path_ctl: + case cdc_rx_sidetone_src1_st_src_path_cfg1: + case cdc_rx_ec_ref_hq0_ec_ref_hq_path_ctl: + case cdc_rx_ec_ref_hq0_ec_ref_hq_cfg0: + case cdc_rx_ec_ref_hq1_ec_ref_hq_path_ctl: + case cdc_rx_ec_ref_hq1_ec_ref_hq_cfg0: + case cdc_rx_ec_ref_hq2_ec_ref_hq_path_ctl: + case cdc_rx_ec_ref_hq2_ec_ref_hq_cfg0: + case cdc_rx_ec_asrc0_clk_rst_ctl: + case cdc_rx_ec_asrc0_ctl0: + case cdc_rx_ec_asrc0_ctl1: + case cdc_rx_ec_asrc0_fifo_ctl: + case cdc_rx_ec_asrc1_clk_rst_ctl: + case cdc_rx_ec_asrc1_ctl0: + case cdc_rx_ec_asrc1_ctl1: + case cdc_rx_ec_asrc1_fifo_ctl: + case cdc_rx_ec_asrc2_clk_rst_ctl: + case cdc_rx_ec_asrc2_ctl0: + case cdc_rx_ec_asrc2_ctl1: + case cdc_rx_ec_asrc2_fifo_ctl: + case cdc_rx_dsd0_path_ctl: + case cdc_rx_dsd0_cfg0: + case cdc_rx_dsd0_cfg1: + case cdc_rx_dsd0_cfg2: + case cdc_rx_dsd1_path_ctl: + case cdc_rx_dsd1_cfg0: + case cdc_rx_dsd1_cfg1: + case cdc_rx_dsd1_cfg2: + return true; + } + + return false; +} + +static bool rx_is_writeable_register(struct device *dev, unsigned int reg) +{ + bool ret; + + ret = rx_is_rw_register(dev, reg); + if (!ret) + return rx_is_wronly_register(dev, reg); + + return ret; +} + +static bool rx_is_readable_register(struct device *dev, unsigned int reg) +{ + switch (reg) { + case cdc_rx_top_hphl_comp_rd_lsb: + case cdc_rx_top_hphl_comp_rd_msb: + case cdc_rx_top_hphr_comp_rd_lsb: + case cdc_rx_top_hphr_comp_rd_msb: + case cdc_rx_top_dsd0_debug_cfg2: + case cdc_rx_top_dsd1_debug_cfg2: + case cdc_rx_bcl_vbat_gain_mon_val: + case cdc_rx_bcl_vbat_decode_st: + case cdc_rx_intr_ctrl_pin1_status0: + case cdc_rx_intr_ctrl_pin2_status0: + case cdc_rx_compander0_ctl6: + case cdc_rx_compander1_ctl6: + case cdc_rx_ec_asrc0_status_fmin_cntr_lsb: + case cdc_rx_ec_asrc0_status_fmin_cntr_msb: + case cdc_rx_ec_asrc0_status_fmax_cntr_lsb: + case cdc_rx_ec_asrc0_status_fmax_cntr_msb: + case cdc_rx_ec_asrc0_status_fifo: + case cdc_rx_ec_asrc1_status_fmin_cntr_lsb: + case cdc_rx_ec_asrc1_status_fmin_cntr_msb: + case cdc_rx_ec_asrc1_status_fmax_cntr_lsb: + case cdc_rx_ec_asrc1_status_fmax_cntr_msb: + case cdc_rx_ec_asrc1_status_fifo: + case cdc_rx_ec_asrc2_status_fmin_cntr_lsb: + case cdc_rx_ec_asrc2_status_fmin_cntr_msb: + case cdc_rx_ec_asrc2_status_fmax_cntr_lsb: + case cdc_rx_ec_asrc2_status_fmax_cntr_msb: + case cdc_rx_ec_asrc2_status_fifo: + return true; + } + + return rx_is_rw_register(dev, reg); +} + +static const struct regmap_config rx_regmap_config = { + .name = "rx_macro", + .reg_bits = 16, + .val_bits = 32, /* 8 but with 32 bit read/write */ + .reg_stride = 4, + .cache_type = regcache_flat, + .reg_defaults = rx_defaults, + .num_reg_defaults = array_size(rx_defaults), + .max_register = rx_max_offset, + .writeable_reg = rx_is_writeable_register, + .volatile_reg = rx_is_volatile_register, + .readable_reg = rx_is_readable_register, +}; + +static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, + int rate_reg_val, u32 sample_rate) +{ + + u8 int_1_mix1_inp; + u32 j, port; + u16 int_mux_cfg0, int_mux_cfg1; + u16 int_fs_reg; + u8 inp0_sel, inp1_sel, inp2_sel; + struct snd_soc_component *component = dai->component; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + for_each_set_bit(port, &rx->active_ch_mask[dai->id], rx_macro_ports_max) { + int_1_mix1_inp = port; + int_mux_cfg0 = cdc_rx_inp_mux_rx_int0_cfg0; + /* + * loop through all interpolator mux inputs and find out + * to which interpolator input, the rx port + * is connected + */ + for (j = 0; j < interp_max; j++) { + int_mux_cfg1 = int_mux_cfg0 + 4; + + inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, + cdc_rx_intx_1_mix_inp0_sel_mask); + inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, + cdc_rx_intx_1_mix_inp1_sel_mask); + inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, + cdc_rx_intx_1_mix_inp2_sel_mask); + + if ((inp0_sel == int_1_mix1_inp + intn_1_inp_sel_rx0) || + (inp1_sel == int_1_mix1_inp + intn_1_inp_sel_rx0) || + (inp2_sel == int_1_mix1_inp + intn_1_inp_sel_rx0)) { + int_fs_reg = cdc_rx_rxn_rx_path_ctl(j); + /* sample_rate is in hz */ + snd_soc_component_update_bits(component, int_fs_reg, + cdc_rx_path_pcm_rate_mask, + rate_reg_val); + } + int_mux_cfg0 += 8; + } + } + + return 0; +} + +static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, + int rate_reg_val, u32 sample_rate) +{ + + u8 int_2_inp; + u32 j, port; + u16 int_mux_cfg1, int_fs_reg; + u8 int_mux_cfg1_val; + struct snd_soc_component *component = dai->component; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + for_each_set_bit(port, &rx->active_ch_mask[dai->id], rx_macro_ports_max) { + int_2_inp = port; + + int_mux_cfg1 = cdc_rx_inp_mux_rx_int0_cfg1; + for (j = 0; j < interp_max; j++) { + int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, + cdc_rx_intx_2_sel_mask); + + if (int_mux_cfg1_val == int_2_inp + intn_2_inp_sel_rx0) { + int_fs_reg = cdc_rx_rxn_rx_path_mix_ctl(j); + snd_soc_component_update_bits(component, int_fs_reg, + cdc_rx_rxn_mix_pcm_rate_mask, + rate_reg_val); + } + int_mux_cfg1 += 8; + } + } + return 0; +} + +static int rx_macro_set_interpolator_rate(struct snd_soc_dai *dai, + u32 sample_rate) +{ + int rate_val = 0; + int i, ret; + + for (i = 0; i < array_size(sr_val_tbl); i++) + if (sample_rate == sr_val_tbl[i].sample_rate) + rate_val = sr_val_tbl[i].rate_val; + + ret = rx_macro_set_prim_interpolator_rate(dai, rate_val, sample_rate); + if (ret) + return ret; + + ret = rx_macro_set_mix_interpolator_rate(dai, rate_val, sample_rate); + if (ret) + return ret; + + return ret; +} + +static int rx_macro_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + struct snd_soc_component *component = dai->component; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + int ret; + + switch (substream->stream) { + case sndrv_pcm_stream_playback: + ret = rx_macro_set_interpolator_rate(dai, params_rate(params)); + if (ret) { + dev_err(component->dev, "%s: cannot set sample rate: %u ", + __func__, params_rate(params)); + return ret; + } + rx->bit_width[dai->id] = params_width(params); + break; + default: + break; + } + return 0; +} + +static int rx_macro_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot) +{ + struct snd_soc_component *component = dai->component; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + u16 val, mask = 0, cnt = 0, temp; + + switch (dai->id) { + case rx_macro_aif1_pb: + case rx_macro_aif2_pb: + case rx_macro_aif3_pb: + case rx_macro_aif4_pb: + for_each_set_bit(temp, &rx->active_ch_mask[dai->id], + rx_macro_ports_max) { + mask |= (1 << temp); + if (++cnt == rx_macro_max_dma_ch_per_port) + break; + } + /* + * cdc_dma_rx_0 port drives rx0/rx1 -- ch_mask 0x1/0x2/0x3 + * cdc_dma_rx_1 port drives rx2/rx3 -- ch_mask 0x1/0x2/0x3 + * cdc_dma_rx_2 port drives rx4 -- ch_mask 0x1 + * cdc_dma_rx_3 port drives rx5 -- ch_mask 0x1 + * aifn can pair to any cdc_dma_rx_n port. + * in general, below convention is used:: + * cdc_dma_rx_0(aif1)/cdc_dma_rx_1(aif2)/ + * cdc_dma_rx_2(aif3)/cdc_dma_rx_3(aif4) + */ + if (mask & 0x0c) + mask = mask >> 2; + if ((mask & 0x10) || (mask & 0x20)) + mask = 0x1; + *rx_slot = mask; + *rx_num = rx->active_ch_cnt[dai->id]; + break; + case rx_macro_aif_echo: + val = snd_soc_component_read(component, cdc_rx_inp_mux_rx_mix_cfg4); + if (val & rx_macro_ec_mix_tx0_mask) { + mask |= 0x1; + cnt++; + } + if (val & rx_macro_ec_mix_tx1_mask) { + mask |= 0x2; + cnt++; + } + val = snd_soc_component_read(component, + cdc_rx_inp_mux_rx_mix_cfg5); + if (val & rx_macro_ec_mix_tx2_mask) { + mask |= 0x4; + cnt++; + } + *tx_slot = mask; + *tx_num = cnt; + break; + default: + dev_err(component->dev, "%s: invalid aif ", __func__); + break; + } + return 0; +} + +static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) +{ + struct snd_soc_component *component = dai->component; + uint16_t j, reg, mix_reg, dsm_reg; + u16 int_mux_cfg0, int_mux_cfg1; + u8 int_mux_cfg0_val, int_mux_cfg1_val; + + switch (dai->id) { + case rx_macro_aif1_pb: + case rx_macro_aif2_pb: + case rx_macro_aif3_pb: + case rx_macro_aif4_pb: + for (j = 0; j < interp_max; j++) { + reg = cdc_rx_rxn_rx_path_ctl(j); + mix_reg = cdc_rx_rxn_rx_path_mix_ctl(j); + dsm_reg = cdc_rx_rxn_rx_path_dsm_ctl(j); + + if (mute) { + snd_soc_component_update_bits(component, reg, + cdc_rx_path_pga_mute_mask, + cdc_rx_path_pga_mute_enable); + snd_soc_component_update_bits(component, mix_reg, + cdc_rx_path_pga_mute_mask, + cdc_rx_path_pga_mute_enable); + } else { + snd_soc_component_update_bits(component, reg, + cdc_rx_path_pga_mute_mask, 0x0); + snd_soc_component_update_bits(component, mix_reg, + cdc_rx_path_pga_mute_mask, 0x0); + } + + if (j == interp_aux) + dsm_reg = cdc_rx_rx2_rx_path_dsm_ctl; + + int_mux_cfg0 = cdc_rx_inp_mux_rx_int0_cfg0 + j * 8; + int_mux_cfg1 = int_mux_cfg0 + 4; + int_mux_cfg0_val = snd_soc_component_read(component, int_mux_cfg0); + int_mux_cfg1_val = snd_soc_component_read(component, int_mux_cfg1); + + if (snd_soc_component_read(component, dsm_reg) & 0x01) { + if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xf0)) + snd_soc_component_update_bits(component, reg, 0x20, 0x20); + if (int_mux_cfg1_val & 0x0f) { + snd_soc_component_update_bits(component, reg, 0x20, 0x20); + snd_soc_component_update_bits(component, mix_reg, 0x20, 0x20); + } + } + } + break; + default: + break; + } + return 0; +} + +static struct snd_soc_dai_ops rx_macro_dai_ops = { + .hw_params = rx_macro_hw_params, + .get_channel_map = rx_macro_get_channel_map, + .mute_stream = rx_macro_digital_mute, +}; + +static struct snd_soc_dai_driver rx_macro_dai[] = { + { + .name = "rx_macro_rx1", + .id = rx_macro_aif1_pb, + .playback = { + .stream_name = "rx_macro_aif1 playback", + .rates = rx_macro_rates | rx_macro_frac_rates, + .formats = rx_macro_formats, + .rate_max = 384000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &rx_macro_dai_ops, + }, + { + .name = "rx_macro_rx2", + .id = rx_macro_aif2_pb, + .playback = { + .stream_name = "rx_macro_aif2 playback", + .rates = rx_macro_rates | rx_macro_frac_rates, + .formats = rx_macro_formats, + .rate_max = 384000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &rx_macro_dai_ops, + }, + { + .name = "rx_macro_rx3", + .id = rx_macro_aif3_pb, + .playback = { + .stream_name = "rx_macro_aif3 playback", + .rates = rx_macro_rates | rx_macro_frac_rates, + .formats = rx_macro_formats, + .rate_max = 384000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &rx_macro_dai_ops, + }, + { + .name = "rx_macro_rx4", + .id = rx_macro_aif4_pb, + .playback = { + .stream_name = "rx_macro_aif4 playback", + .rates = rx_macro_rates | rx_macro_frac_rates, + .formats = rx_macro_formats, + .rate_max = 384000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 2, + }, + .ops = &rx_macro_dai_ops, + }, + { + .name = "rx_macro_echo", + .id = rx_macro_aif_echo, + .capture = { + .stream_name = "rx_aif_echo capture", + .rates = rx_macro_echo_rates, + .formats = rx_macro_echo_formats, + .rate_max = 48000, + .rate_min = 8000, + .channels_min = 1, + .channels_max = 3, + }, + .ops = &rx_macro_dai_ops, + }, +}; + +static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) +{ + struct regmap *regmap = rx->regmap; + + if (mclk_enable) { + if (rx->rx_mclk_users == 0) { + regmap_update_bits(regmap, cdc_rx_clk_rst_ctrl_mclk_control, + cdc_rx_clk_mclk_en_mask | + cdc_rx_clk_mclk2_en_mask, + cdc_rx_clk_mclk_enable | + cdc_rx_clk_mclk2_enable); + regmap_update_bits(regmap, cdc_rx_clk_rst_ctrl_fs_cnt_control, + cdc_rx_fs_mclk_cnt_clr_mask, 0x00); + regmap_update_bits(regmap, cdc_rx_clk_rst_ctrl_fs_cnt_control, + cdc_rx_fs_mclk_cnt_en_mask, + cdc_rx_fs_mclk_cnt_enable); + regcache_mark_dirty(regmap); + regcache_sync(regmap); + } + rx->rx_mclk_users++; + } else { + if (rx->rx_mclk_users <= 0) { + dev_err(rx->dev, "%s: clock already disabled ", __func__); + rx->rx_mclk_users = 0; + return; + } + rx->rx_mclk_users--; + if (rx->rx_mclk_users == 0) { + regmap_update_bits(regmap, cdc_rx_clk_rst_ctrl_fs_cnt_control, + cdc_rx_fs_mclk_cnt_en_mask, 0x0); + regmap_update_bits(regmap, cdc_rx_clk_rst_ctrl_fs_cnt_control, + cdc_rx_fs_mclk_cnt_clr_mask, + cdc_rx_fs_mclk_cnt_clr); + regmap_update_bits(regmap, cdc_rx_clk_rst_ctrl_mclk_control, + cdc_rx_clk_mclk_en_mask | + cdc_rx_clk_mclk2_en_mask, 0x0); + } + } +} + +static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) +{ + if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) + snd_soc_component_update_bits(rx->component, cdc_rx_clsh_crc, + cdc_rx_clsh_clk_en_mask, enable); + if (rx->clsh_users < 0) + rx->clsh_users = 0; +} + +static int rx_macro_get_compander(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = + snd_soc_kcontrol_component(kcontrol); + int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; + return 0; +} + +static int rx_macro_set_compander(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; + int value = ucontrol->value.integer.value[0]; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + rx->comp_enabled[comp] = value; + + return 0; +} + +static int rx_macro_get_ear_mode(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rx->is_ear_mode_on; + return 0; +} + +static int rx_macro_put_ear_mode(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); + return 0; +} + +static int rx_macro_get_hph_hd2_mode(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rx->hph_hd2_mode; + return 0; +} + +static int rx_macro_put_hph_hd2_mode(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + rx->hph_hd2_mode = ucontrol->value.integer.value[0]; + return 0; +} + +static int rx_macro_get_hph_pwr_mode(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rx->hph_pwr_mode; + return 0; +} + +static int rx_macro_put_hph_pwr_mode(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + rx->hph_pwr_mode = ucontrol->value.integer.value[0]; + return 0; +} + +static int rx_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rx->is_softclip_on; + + return 0; +} + +static int rx_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + rx->is_softclip_on = ucontrol->value.integer.value[0]; + + return 0; +} + +static int rx_macro_aux_hpf_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; + + return 0; +} + +static int rx_macro_aux_hpf_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; + + return 0; +} + +static const struct snd_kcontrol_new rx_macro_snd_controls[] = { + soc_single_s8_tlv("rx_rx0 digital volume", cdc_rx_rx0_rx_vol_ctl, + -84, 40, digital_gain), + soc_single_s8_tlv("rx_rx1 digital volume", cdc_rx_rx1_rx_vol_ctl, + -84, 40, digital_gain), + soc_single_s8_tlv("rx_rx2 digital volume", cdc_rx_rx2_rx_vol_ctl, + -84, 40, digital_gain), + soc_single_s8_tlv("rx_rx0 mix digital volume", cdc_rx_rx0_rx_vol_mix_ctl, + -84, 40, digital_gain), + soc_single_s8_tlv("rx_rx1 mix digital volume", cdc_rx_rx1_rx_vol_mix_ctl, + -84, 40, digital_gain), + soc_single_s8_tlv("rx_rx2 mix digital volume", cdc_rx_rx2_rx_vol_mix_ctl, + -84, 40, digital_gain), + + soc_single_ext("rx_comp1 switch", snd_soc_nopm, rx_macro_comp1, 1, 0, + rx_macro_get_compander, rx_macro_set_compander), + soc_single_ext("rx_comp2 switch", snd_soc_nopm, rx_macro_comp2, 1, 0, + rx_macro_get_compander, rx_macro_set_compander), + + soc_single_ext("rx_ear mode switch", snd_soc_nopm, 0, 1, 0, + rx_macro_get_ear_mode, rx_macro_put_ear_mode), + + soc_single_ext("rx_hph hd2 mode switch", snd_soc_nopm, 0, 1, 0, + rx_macro_get_hph_hd2_mode, rx_macro_put_hph_hd2_mode), + + soc_enum_ext("rx_hph pwr mode", rx_macro_hph_pwr_mode_enum, + rx_macro_get_hph_pwr_mode, rx_macro_put_hph_pwr_mode), + + soc_single_ext("rx_softclip switch", snd_soc_nopm, 0, 1, 0, + rx_macro_soft_clip_enable_get, + rx_macro_soft_clip_enable_put), + soc_single_ext("aux_hpf switch", snd_soc_nopm, 0, 1, 0, + rx_macro_aux_hpf_mode_get, + rx_macro_aux_hpf_mode_put), +}; + +static int rx_macro_component_probe(struct snd_soc_component *component) +{ + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + snd_soc_component_init_regmap(component, rx->regmap); + + snd_soc_component_update_bits(component, cdc_rx_rx0_rx_path_sec7, + cdc_rx_dsm_out_delay_sel_mask, + cdc_rx_dsm_out_delay_two_sample); + snd_soc_component_update_bits(component, cdc_rx_rx1_rx_path_sec7, + cdc_rx_dsm_out_delay_sel_mask, + cdc_rx_dsm_out_delay_two_sample); + snd_soc_component_update_bits(component, cdc_rx_rx2_rx_path_sec7, + cdc_rx_dsm_out_delay_sel_mask, + cdc_rx_dsm_out_delay_two_sample); + snd_soc_component_update_bits(component, cdc_rx_rx0_rx_path_cfg3, + cdc_rx_dc_coeff_sel_mask, + cdc_rx_dc_coeff_sel_two); + snd_soc_component_update_bits(component, cdc_rx_rx1_rx_path_cfg3, + cdc_rx_dc_coeff_sel_mask, + cdc_rx_dc_coeff_sel_two); + snd_soc_component_update_bits(component, cdc_rx_rx2_rx_path_cfg3, + cdc_rx_dc_coeff_sel_mask, + cdc_rx_dc_coeff_sel_two); + + rx->component = component; + + return 0; +} + +static int swclk_gate_enable(struct clk_hw *hw) +{ + struct rx_macro *rx = to_rx_macro(hw); + + rx_macro_mclk_enable(rx, true); + if (rx->reset_swr) + regmap_update_bits(rx->regmap, cdc_rx_clk_rst_ctrl_swr_control, + cdc_rx_swr_reset_mask, + cdc_rx_swr_reset); + + regmap_update_bits(rx->regmap, cdc_rx_clk_rst_ctrl_swr_control, + cdc_rx_swr_clk_en_mask, 1); + + if (rx->reset_swr) + regmap_update_bits(rx->regmap, cdc_rx_clk_rst_ctrl_swr_control, + cdc_rx_swr_reset_mask, 0); + rx->reset_swr = false; + + return 0; +} + +static void swclk_gate_disable(struct clk_hw *hw) +{ + struct rx_macro *rx = to_rx_macro(hw); + + regmap_update_bits(rx->regmap, cdc_rx_clk_rst_ctrl_swr_control, + cdc_rx_swr_clk_en_mask, 0); + + rx_macro_mclk_enable(rx, false); +} + +static int swclk_gate_is_enabled(struct clk_hw *hw) +{ + struct rx_macro *rx = to_rx_macro(hw); + int ret, val; + + regmap_read(rx->regmap, cdc_rx_clk_rst_ctrl_swr_control, &val); + ret = val & bit(0); + + return ret; +} + +static unsigned long swclk_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + return parent_rate / 2; +} + +static const struct clk_ops swclk_gate_ops = { + .prepare = swclk_gate_enable, + .unprepare = swclk_gate_disable, + .is_enabled = swclk_gate_is_enabled, + .recalc_rate = swclk_recalc_rate, + +}; + +static struct clk *rx_macro_register_mclk_output(struct rx_macro *rx) +{ + struct device *dev = rx->dev; + struct device_node *np = dev->of_node; + const char *parent_clk_name = null; + const char *clk_name = "lpass-rx-mclk"; + struct clk_hw *hw; + struct clk_init_data init; + int ret; + + parent_clk_name = __clk_get_name(rx->clks[2].clk); + + init.name = clk_name; + init.ops = &swclk_gate_ops; + init.flags = 0; + init.parent_names = &parent_clk_name; + init.num_parents = 1; + rx->hw.init = &init; + hw = &rx->hw; + ret = clk_hw_register(rx->dev, hw); + if (ret) + return err_ptr(ret); + + of_clk_add_provider(np, of_clk_src_simple_get, hw->clk); + + return null; +} + +static const struct snd_soc_component_driver rx_macro_component_drv = { + .name = "rx-macro", + .probe = rx_macro_component_probe, + .controls = rx_macro_snd_controls, + .num_controls = array_size(rx_macro_snd_controls), +}; + +static int rx_macro_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rx_macro *rx; + void __iomem *base; + int ret; + + rx = devm_kzalloc(dev, sizeof(*rx), gfp_kernel); + if (!rx) + return -enomem; + + rx->clks[0].id = "macro"; + rx->clks[1].id = "dcodec"; + rx->clks[2].id = "mclk"; + rx->clks[3].id = "npl"; + rx->clks[4].id = "fsgen"; + + ret = devm_clk_bulk_get(dev, rx_num_clks_max, rx->clks); + if (ret) { + dev_err(dev, "error getting rx clocks (%d) ", ret); + return ret; + } + + base = devm_platform_ioremap_resource(pdev, 0); + if (is_err(base)) + return ptr_err(base); + + rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config); + + dev_set_drvdata(dev, rx); + + rx->reset_swr = true; + rx->dev = dev; + + /* set mclk and npl rates */ + clk_set_rate(rx->clks[2].clk, mclk_freq); + clk_set_rate(rx->clks[3].clk, mclk_freq); + + ret = clk_bulk_prepare_enable(rx_num_clks_max, rx->clks); + if (ret) + return ret; + + rx_macro_register_mclk_output(rx); + + ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv, + rx_macro_dai, + array_size(rx_macro_dai)); + if (ret) + clk_bulk_disable_unprepare(rx_num_clks_max, rx->clks); + + return ret; +} + +static int rx_macro_remove(struct platform_device *pdev) +{ + struct rx_macro *rx = dev_get_drvdata(&pdev->dev); + + of_clk_del_provider(pdev->dev.of_node); + clk_bulk_disable_unprepare(rx_num_clks_max, rx->clks); + return 0; +} + +static const struct of_device_id rx_macro_dt_match[] = { + { .compatible = "qcom,sm8250-lpass-rx-macro" }, + { } +}; + +static struct platform_driver rx_macro_driver = { + .driver = { + .name = "rx_macro", + .owner = this_module, + .of_match_table = rx_macro_dt_match, + .suppress_bind_attrs = true, + }, + .probe = rx_macro_probe, + .remove = rx_macro_remove, +}; + +module_platform_driver(rx_macro_driver); + +module_description("rx macro driver"); +module_license("gpl");
|
Audio
|
af3d54b99764f0bdd83fcbd1895d23b83f8276be
|
srinivas kandagatla
|
sound
|
soc
|
codecs
|
asoc: codecs: lpass-rx-macro: add dapm widgets and route
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this patch adds dapm widgets and routes on this codec
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
adds support for two codec macro blocks(tx and rx) available in qualcomm lpass (low power audio subsystem)
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['asoc ', 'codecs']
|
['c']
| 1
| 1,341
| 0
|
--- diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c --- a/sound/soc/codecs/lpass-rx-macro.c +++ b/sound/soc/codecs/lpass-rx-macro.c +static const char * const rx_int_mix_mux_text[] = { + "zero", "rx0", "rx1", "rx2", "rx3", "rx4", "rx5" +}; + +static const char * const rx_prim_mix_text[] = { + "zero", "dec0", "dec1", "iir0", "iir1", "rx0", "rx1", "rx2", + "rx3", "rx4", "rx5" +}; + +static const char * const rx_sidetone_mix_text[] = { + "zero", "src0", "src1", "src_sum" +}; + +static const char * const iir_inp_mux_text[] = { + "zero", "dec0", "dec1", "dec2", "dec3", + "rx0", "rx1", "rx2", "rx3", "rx4", "rx5" +}; + +static const char * const rx_int_dem_inp_mux_text[] = { + "normal_dsm_out", "clsh_dsm_out", +}; + +static const char * const rx_int0_1_interp_mux_text[] = { + "zero", "rx int0_1 mix1", +}; + +static const char * const rx_int1_1_interp_mux_text[] = { + "zero", "rx int1_1 mix1", +}; + +static const char * const rx_int2_1_interp_mux_text[] = { + "zero", "rx int2_1 mix1", +}; + +static const char * const rx_int0_2_interp_mux_text[] = { + "zero", "rx int0_2 mux", +}; + +static const char * const rx_int1_2_interp_mux_text[] = { + "zero", "rx int1_2 mux", +}; + +static const char * const rx_int2_2_interp_mux_text[] = { + "zero", "rx int2_2 mux", +}; + +static const char *const rx_macro_mux_text[] = { + "zero", "aif1_pb", "aif2_pb", "aif3_pb", "aif4_pb" +}; + +static const char * const rx_echo_mux_text[] = { + "zero", "rx_mix0", "rx_mix1", "rx_mix2" +}; + +static const struct soc_enum rx_mix_tx2_mux_enum = + soc_enum_single(cdc_rx_inp_mux_rx_mix_cfg5, 0, 4, rx_echo_mux_text); +static const struct soc_enum rx_mix_tx1_mux_enum = + soc_enum_single(cdc_rx_inp_mux_rx_mix_cfg4, 0, 4, rx_echo_mux_text); +static const struct soc_enum rx_mix_tx0_mux_enum = + soc_enum_single(cdc_rx_inp_mux_rx_mix_cfg4, 4, 4, rx_echo_mux_text); + +static soc_enum_single_decl(rx_int0_2_enum, cdc_rx_inp_mux_rx_int0_cfg1, 0, + rx_int_mix_mux_text); +static soc_enum_single_decl(rx_int1_2_enum, cdc_rx_inp_mux_rx_int1_cfg1, 0, + rx_int_mix_mux_text); +static soc_enum_single_decl(rx_int2_2_enum, cdc_rx_inp_mux_rx_int2_cfg1, 0, + rx_int_mix_mux_text); + +static soc_enum_single_decl(rx_int0_1_mix_inp0_enum, cdc_rx_inp_mux_rx_int0_cfg0, 0, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int0_1_mix_inp1_enum, cdc_rx_inp_mux_rx_int0_cfg0, 4, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int0_1_mix_inp2_enum, cdc_rx_inp_mux_rx_int0_cfg1, 4, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int1_1_mix_inp0_enum, cdc_rx_inp_mux_rx_int1_cfg0, 0, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int1_1_mix_inp1_enum, cdc_rx_inp_mux_rx_int1_cfg0, 4, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int1_1_mix_inp2_enum, cdc_rx_inp_mux_rx_int1_cfg1, 4, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int2_1_mix_inp0_enum, cdc_rx_inp_mux_rx_int2_cfg0, 0, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int2_1_mix_inp1_enum, cdc_rx_inp_mux_rx_int2_cfg0, 4, + rx_prim_mix_text); +static soc_enum_single_decl(rx_int2_1_mix_inp2_enum, cdc_rx_inp_mux_rx_int2_cfg1, 4, + rx_prim_mix_text); + +static soc_enum_single_decl(rx_int0_mix2_inp_enum, cdc_rx_inp_mux_sidetone_src_cfg0, 2, + rx_sidetone_mix_text); +static soc_enum_single_decl(rx_int1_mix2_inp_enum, cdc_rx_inp_mux_sidetone_src_cfg0, 4, + rx_sidetone_mix_text); +static soc_enum_single_decl(rx_int2_mix2_inp_enum, cdc_rx_inp_mux_sidetone_src_cfg0, 6, + rx_sidetone_mix_text); +static soc_enum_single_decl(iir0_inp0_enum, cdc_rx_iir_inp_mux_iir0_mix_cfg0, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir0_inp1_enum, cdc_rx_iir_inp_mux_iir0_mix_cfg1, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir0_inp2_enum, cdc_rx_iir_inp_mux_iir0_mix_cfg2, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir0_inp3_enum, cdc_rx_iir_inp_mux_iir0_mix_cfg3, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir1_inp0_enum, cdc_rx_iir_inp_mux_iir1_mix_cfg0, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir1_inp1_enum, cdc_rx_iir_inp_mux_iir1_mix_cfg1, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir1_inp2_enum, cdc_rx_iir_inp_mux_iir1_mix_cfg2, 0, + iir_inp_mux_text); +static soc_enum_single_decl(iir1_inp3_enum, cdc_rx_iir_inp_mux_iir1_mix_cfg3, 0, + iir_inp_mux_text); + +static soc_enum_single_decl(rx_int0_1_interp_enum, snd_soc_nopm, 0, + rx_int0_1_interp_mux_text); +static soc_enum_single_decl(rx_int1_1_interp_enum, snd_soc_nopm, 0, + rx_int1_1_interp_mux_text); +static soc_enum_single_decl(rx_int2_1_interp_enum, snd_soc_nopm, 0, + rx_int2_1_interp_mux_text); +static soc_enum_single_decl(rx_int0_2_interp_enum, snd_soc_nopm, 0, + rx_int0_2_interp_mux_text); +static soc_enum_single_decl(rx_int1_2_interp_enum, snd_soc_nopm, 0, + rx_int1_2_interp_mux_text); +static soc_enum_single_decl(rx_int2_2_interp_enum, snd_soc_nopm, 0, + rx_int2_2_interp_mux_text); +static soc_enum_single_decl(rx_int0_dem_inp_enum, cdc_rx_rx0_rx_path_cfg1, 0, + rx_int_dem_inp_mux_text); +static soc_enum_single_decl(rx_int1_dem_inp_enum, cdc_rx_rx1_rx_path_cfg1, 0, + rx_int_dem_inp_mux_text); + +static soc_enum_single_decl(rx_macro_rx0_enum, snd_soc_nopm, 0, rx_macro_mux_text); +static soc_enum_single_decl(rx_macro_rx1_enum, snd_soc_nopm, 0, rx_macro_mux_text); +static soc_enum_single_decl(rx_macro_rx2_enum, snd_soc_nopm, 0, rx_macro_mux_text); +static soc_enum_single_decl(rx_macro_rx3_enum, snd_soc_nopm, 0, rx_macro_mux_text); +static soc_enum_single_decl(rx_macro_rx4_enum, snd_soc_nopm, 0, rx_macro_mux_text); +static soc_enum_single_decl(rx_macro_rx5_enum, snd_soc_nopm, 0, rx_macro_mux_text); + +static const struct snd_kcontrol_new rx_mix_tx1_mux = + soc_dapm_enum("rx mix tx1_mux mux", rx_mix_tx1_mux_enum); +static const struct snd_kcontrol_new rx_mix_tx2_mux = + soc_dapm_enum("rx mix tx2_mux mux", rx_mix_tx2_mux_enum); +static const struct snd_kcontrol_new rx_int0_2_mux = + soc_dapm_enum("rx_int0_2", rx_int0_2_enum); +static const struct snd_kcontrol_new rx_int1_2_mux = + soc_dapm_enum("rx_int1_2", rx_int1_2_enum); +static const struct snd_kcontrol_new rx_int2_2_mux = + soc_dapm_enum("rx_int2_2", rx_int2_2_enum); +static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux = + soc_dapm_enum("rx_int0_1_mix_inp0", rx_int0_1_mix_inp0_enum); +static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux = + soc_dapm_enum("rx_int0_1_mix_inp1", rx_int0_1_mix_inp1_enum); +static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux = + soc_dapm_enum("rx_int0_1_mix_inp2", rx_int0_1_mix_inp2_enum); +static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux = + soc_dapm_enum("rx_int1_1_mix_inp0", rx_int1_1_mix_inp0_enum); +static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux = + soc_dapm_enum("rx_int1_1_mix_inp1", rx_int1_1_mix_inp1_enum); +static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux = + soc_dapm_enum("rx_int1_1_mix_inp2", rx_int1_1_mix_inp2_enum); +static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux = + soc_dapm_enum("rx_int2_1_mix_inp0", rx_int2_1_mix_inp0_enum); +static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux = + soc_dapm_enum("rx_int2_1_mix_inp1", rx_int2_1_mix_inp1_enum); +static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux = + soc_dapm_enum("rx_int2_1_mix_inp2", rx_int2_1_mix_inp2_enum); +static const struct snd_kcontrol_new rx_int0_mix2_inp_mux = + soc_dapm_enum("rx_int0_mix2_inp", rx_int0_mix2_inp_enum); +static const struct snd_kcontrol_new rx_int1_mix2_inp_mux = + soc_dapm_enum("rx_int1_mix2_inp", rx_int1_mix2_inp_enum); +static const struct snd_kcontrol_new rx_int2_mix2_inp_mux = + soc_dapm_enum("rx_int2_mix2_inp", rx_int2_mix2_inp_enum); +static const struct snd_kcontrol_new iir0_inp0_mux = + soc_dapm_enum("iir0_inp0", iir0_inp0_enum); +static const struct snd_kcontrol_new iir0_inp1_mux = + soc_dapm_enum("iir0_inp1", iir0_inp1_enum); +static const struct snd_kcontrol_new iir0_inp2_mux = + soc_dapm_enum("iir0_inp2", iir0_inp2_enum); +static const struct snd_kcontrol_new iir0_inp3_mux = + soc_dapm_enum("iir0_inp3", iir0_inp3_enum); +static const struct snd_kcontrol_new iir1_inp0_mux = + soc_dapm_enum("iir1_inp0", iir1_inp0_enum); +static const struct snd_kcontrol_new iir1_inp1_mux = + soc_dapm_enum("iir1_inp1", iir1_inp1_enum); +static const struct snd_kcontrol_new iir1_inp2_mux = + soc_dapm_enum("iir1_inp2", iir1_inp2_enum); +static const struct snd_kcontrol_new iir1_inp3_mux = + soc_dapm_enum("iir1_inp3", iir1_inp3_enum); +static const struct snd_kcontrol_new rx_int0_1_interp_mux = + soc_dapm_enum("rx_int0_1_interp", rx_int0_1_interp_enum); +static const struct snd_kcontrol_new rx_int1_1_interp_mux = + soc_dapm_enum("rx_int1_1_interp", rx_int1_1_interp_enum); +static const struct snd_kcontrol_new rx_int2_1_interp_mux = + soc_dapm_enum("rx_int2_1_interp", rx_int2_1_interp_enum); +static const struct snd_kcontrol_new rx_int0_2_interp_mux = + soc_dapm_enum("rx_int0_2_interp", rx_int0_2_interp_enum); +static const struct snd_kcontrol_new rx_int1_2_interp_mux = + soc_dapm_enum("rx_int1_2_interp", rx_int1_2_interp_enum); +static const struct snd_kcontrol_new rx_int2_2_interp_mux = + soc_dapm_enum("rx_int2_2_interp", rx_int2_2_interp_enum); +static const struct snd_kcontrol_new rx_mix_tx0_mux = + soc_dapm_enum("rx mix tx0_mux mux", rx_mix_tx0_mux_enum); +static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + unsigned short look_ahead_dly_reg; + unsigned int val; + + val = ucontrol->value.enumerated.item[0]; + + if (e->reg == cdc_rx_rx0_rx_path_cfg1) + look_ahead_dly_reg = cdc_rx_rx0_rx_path_cfg0; + else if (e->reg == cdc_rx_rx1_rx_path_cfg1) + look_ahead_dly_reg = cdc_rx_rx1_rx_path_cfg0; + + /* set look ahead delay */ + if (val) + snd_soc_component_update_bits(component, look_ahead_dly_reg, + cdc_rx_dly_zn_en_mask, + cdc_rx_dly_zn_enable); + else + snd_soc_component_update_bits(component, look_ahead_dly_reg, + cdc_rx_dly_zn_en_mask, 0); + /* set dem inp select */ + return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); +} + +static const struct snd_kcontrol_new rx_int0_dem_inp_mux = + soc_dapm_enum_ext("rx_int0_dem_inp", rx_int0_dem_inp_enum, + snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); +static const struct snd_kcontrol_new rx_int1_dem_inp_mux = + soc_dapm_enum_ext("rx_int1_dem_inp", rx_int1_dem_inp_enum, + snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put); + +static int rx_macro_mclk_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + int ret = 0; + + switch (event) { + case snd_soc_dapm_pre_pmu: + rx_macro_mclk_enable(rx, true); + break; + case snd_soc_dapm_post_pmd: + rx_macro_mclk_enable(rx, false); + break; + default: + dev_err(component->dev, "%s: invalid dapm event %d ", __func__, event); + ret = -einval; + } + return ret; +} + +static bool rx_macro_adie_lb(struct snd_soc_component *component, + int interp_idx) +{ + u16 int_mux_cfg0, int_mux_cfg1; + u8 int_n_inp0, int_n_inp1, int_n_inp2; + + int_mux_cfg0 = cdc_rx_inp_mux_rx_int0_cfg0 + interp_idx * 8; + int_mux_cfg1 = int_mux_cfg0 + 4; + + int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, + cdc_rx_intx_1_mix_inp0_sel_mask); + int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, + cdc_rx_intx_1_mix_inp1_sel_mask); + int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, + cdc_rx_intx_1_mix_inp2_sel_mask); + + if (int_n_inp0 == intn_1_inp_sel_dec0 || + int_n_inp0 == intn_1_inp_sel_dec1 || + int_n_inp0 == intn_1_inp_sel_iir0 || + int_n_inp0 == intn_1_inp_sel_iir1) + return true; + + if (int_n_inp1 == intn_1_inp_sel_dec0 || + int_n_inp1 == intn_1_inp_sel_dec1 || + int_n_inp1 == intn_1_inp_sel_iir0 || + int_n_inp1 == intn_1_inp_sel_iir1) + return true; + + if (int_n_inp2 == intn_1_inp_sel_dec0 || + int_n_inp2 == intn_1_inp_sel_dec1 || + int_n_inp2 == intn_1_inp_sel_iir0 || + int_n_inp2 == intn_1_inp_sel_iir1) + return true; + + return false; +} + +static int rx_macro_enable_interp_clk(struct snd_soc_component *component, + int event, int interp_idx); +static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + u16 gain_reg, reg; + + reg = cdc_rx_rxn_rx_path_ctl(w->shift); + gain_reg = cdc_rx_rxn_rx_vol_ctl(w->shift); + + switch (event) { + case snd_soc_dapm_pre_pmu: + rx_macro_enable_interp_clk(component, event, w->shift); + if (rx_macro_adie_lb(component, w->shift)) + snd_soc_component_update_bits(component, reg, + cdc_rx_path_clk_en_mask, + cdc_rx_path_clk_enable); + break; + case snd_soc_dapm_post_pmu: + snd_soc_component_write(component, gain_reg, + snd_soc_component_read(component, gain_reg)); + break; + case snd_soc_dapm_post_pmd: + rx_macro_enable_interp_clk(component, event, w->shift); + break; + } + + return 0; +} + +static int rx_macro_config_compander(struct snd_soc_component *component, + struct rx_macro *rx, + int comp, int event) +{ + u8 pcm_rate, val; + + /* aux does not have compander */ + if (comp == interp_aux) + return 0; + + pcm_rate = snd_soc_component_read(component, cdc_rx_rxn_rx_path_ctl(comp)) & 0x0f; + if (pcm_rate < 0x06) + val = 0x03; + else if (pcm_rate < 0x08) + val = 0x01; + else if (pcm_rate < 0x0b) + val = 0x02; + else + val = 0x00; + + if (snd_soc_dapm_event_on(event)) + snd_soc_component_update_bits(component, cdc_rx_rxn_rx_path_cfg3(comp), + cdc_rx_dc_coeff_sel_mask, val); + + if (snd_soc_dapm_event_off(event)) + snd_soc_component_update_bits(component, cdc_rx_rxn_rx_path_cfg3(comp), + cdc_rx_dc_coeff_sel_mask, 0x3); + if (!rx->comp_enabled[comp]) + return 0; + + if (snd_soc_dapm_event_on(event)) { + /* enable compander clock */ + snd_soc_component_write_field(component, cdc_rx_compandern_ctl0(comp), + cdc_rx_compandern_clk_en_mask, 0x1); + snd_soc_component_write_field(component, cdc_rx_compandern_ctl0(comp), + cdc_rx_compandern_soft_rst_mask, 0x1); + snd_soc_component_write_field(component, cdc_rx_compandern_ctl0(comp), + cdc_rx_compandern_soft_rst_mask, 0x0); + snd_soc_component_write_field(component, cdc_rx_rxn_rx_path_cfg0(comp), + cdc_rx_rxn_comp_en_mask, 0x1); + } + + if (snd_soc_dapm_event_off(event)) { + snd_soc_component_write_field(component, cdc_rx_compandern_ctl0(comp), + cdc_rx_compandern_halt_mask, 0x1); + snd_soc_component_write_field(component, cdc_rx_rxn_rx_path_cfg0(comp), + cdc_rx_rxn_comp_en_mask, 0x0); + snd_soc_component_write_field(component, cdc_rx_compandern_ctl0(comp), + cdc_rx_compandern_clk_en_mask, 0x0); + snd_soc_component_write_field(component, cdc_rx_compandern_ctl0(comp), + cdc_rx_compandern_halt_mask, 0x0); + } + + return 0; +} + +static int rx_macro_load_compander_coeff(struct snd_soc_component *component, + struct rx_macro *rx, + int comp, int event) +{ + u16 comp_coeff_lsb_reg, comp_coeff_msb_reg; + int i; + int hph_pwr_mode = hph_lohifi; + + if (!rx->comp_enabled[comp]) + return 0; + + if (comp == interp_hphl) { + comp_coeff_lsb_reg = cdc_rx_top_hphl_comp_wr_lsb; + comp_coeff_msb_reg = cdc_rx_top_hphl_comp_wr_msb; + } else if (comp == interp_hphr) { + comp_coeff_lsb_reg = cdc_rx_top_hphr_comp_wr_lsb; + comp_coeff_msb_reg = cdc_rx_top_hphr_comp_wr_msb; + } else { + /* compander coefficients are loaded only for hph path */ + return 0; + } + + hph_pwr_mode = rx->hph_pwr_mode; + + if (snd_soc_dapm_event_on(event)) { + /* load compander coeff */ + for (i = 0; i < comp_max_coeff; i++) { + snd_soc_component_write(component, comp_coeff_lsb_reg, + comp_coeff_table[hph_pwr_mode][i].lsb); + snd_soc_component_write(component, comp_coeff_msb_reg, + comp_coeff_table[hph_pwr_mode][i].msb); + } + } + + return 0; +} + +static void rx_macro_enable_softclip_clk(struct snd_soc_component *component, + struct rx_macro *rx, bool enable) +{ + if (enable) { + if (rx->softclip_clk_users == 0) + snd_soc_component_write_field(component, cdc_rx_softclip_crc, + cdc_rx_softclip_clk_en_mask, 1); + rx->softclip_clk_users++; + } else { + rx->softclip_clk_users--; + if (rx->softclip_clk_users == 0) + snd_soc_component_write_field(component, cdc_rx_softclip_crc, + cdc_rx_softclip_clk_en_mask, 0); + } +} + +static int rx_macro_config_softclip(struct snd_soc_component *component, + struct rx_macro *rx, int event) +{ + + if (!rx->is_softclip_on) + return 0; + + if (snd_soc_dapm_event_on(event)) { + /* enable softclip clock */ + rx_macro_enable_softclip_clk(component, rx, true); + /* enable softclip control */ + snd_soc_component_write_field(component, cdc_rx_softclip_softclip_ctrl, + cdc_rx_softclip_en_mask, 0x01); + } + + if (snd_soc_dapm_event_off(event)) { + snd_soc_component_write_field(component, cdc_rx_softclip_softclip_ctrl, + cdc_rx_softclip_en_mask, 0x0); + rx_macro_enable_softclip_clk(component, rx, false); + } + + return 0; +} + +static int rx_macro_config_aux_hpf(struct snd_soc_component *component, + struct rx_macro *rx, int event) +{ + if (snd_soc_dapm_event_on(event)) { + /* update aux hpf control */ + if (!rx->is_aux_hpf_on) + snd_soc_component_update_bits(component, + cdc_rx_rx2_rx_path_cfg1, 0x04, 0x00); + } + + if (snd_soc_dapm_event_off(event)) { + /* reset to default (hpf=on) */ + snd_soc_component_update_bits(component, + cdc_rx_rx2_rx_path_cfg1, 0x04, 0x04); + } + + return 0; +} + +static int rx_macro_config_classh(struct snd_soc_component *component, + struct rx_macro *rx, + int interp_n, int event) +{ + if (snd_soc_dapm_event_off(event)) { + rx_macro_enable_clsh_block(rx, false); + return 0; + } + + if (!snd_soc_dapm_event_on(event)) + return 0; + + rx_macro_enable_clsh_block(rx, true); + if (interp_n == interp_hphl || + interp_n == interp_hphr) { + /* + * these k1 values depend on the headphone impedance + * for now it is assumed to be 16 ohm + */ + snd_soc_component_write(component, cdc_rx_clsh_k1_lsb, 0xc0); + snd_soc_component_write_field(component, cdc_rx_clsh_k1_msb, + cdc_rx_clsh_k1_msb_coeff_mask, 0); + } + switch (interp_n) { + case interp_hphl: + if (rx->is_ear_mode_on) + snd_soc_component_update_bits(component, + cdc_rx_clsh_hph_v_pa, + cdc_rx_clsh_hph_v_pa_min_mask, 0x39); + else + snd_soc_component_update_bits(component, + cdc_rx_clsh_hph_v_pa, + cdc_rx_clsh_hph_v_pa_min_mask, 0x1c); + snd_soc_component_update_bits(component, + cdc_rx_clsh_decay_ctrl, + cdc_rx_clsh_decay_rate_mask, 0x0); + snd_soc_component_write_field(component, + cdc_rx_rx0_rx_path_cfg0, + cdc_rx_rxn_clsh_en_mask, 0x1); + break; + case interp_hphr: + if (rx->is_ear_mode_on) + snd_soc_component_update_bits(component, + cdc_rx_clsh_hph_v_pa, + cdc_rx_clsh_hph_v_pa_min_mask, 0x39); + else + snd_soc_component_update_bits(component, + cdc_rx_clsh_hph_v_pa, + cdc_rx_clsh_hph_v_pa_min_mask, 0x1c); + snd_soc_component_update_bits(component, + cdc_rx_clsh_decay_ctrl, + cdc_rx_clsh_decay_rate_mask, 0x0); + snd_soc_component_update_bits(component, + cdc_rx_rx1_rx_path_cfg0, + cdc_rx_rxn_clsh_en_mask, 0x1); + break; + case interp_aux: + snd_soc_component_update_bits(component, + cdc_rx_rx2_rx_path_cfg0, + cdc_rx_rx2_dly_z_en_mask, 1); + snd_soc_component_write_field(component, + cdc_rx_rx2_rx_path_cfg0, + cdc_rx_rx2_clsh_en_mask, 1); + break; + } + + return 0; +} + +static void rx_macro_hd2_control(struct snd_soc_component *component, + u16 interp_idx, int event) +{ + u16 hd2_scale_reg, hd2_enable_reg; + + switch (interp_idx) { + case interp_hphl: + hd2_scale_reg = cdc_rx_rx0_rx_path_sec3; + hd2_enable_reg = cdc_rx_rx0_rx_path_cfg0; + break; + case interp_hphr: + hd2_scale_reg = cdc_rx_rx1_rx_path_sec3; + hd2_enable_reg = cdc_rx_rx1_rx_path_cfg0; + break; + } + + if (hd2_enable_reg && snd_soc_dapm_event_on(event)) { + snd_soc_component_update_bits(component, hd2_scale_reg, + cdc_rx_rxn_hd2_alpha_mask, 0x14); + snd_soc_component_write_field(component, hd2_enable_reg, + cdc_rx_rxn_hd2_en_mask, 1); + } + + if (hd2_enable_reg && snd_soc_dapm_event_off(event)) { + snd_soc_component_write_field(component, hd2_enable_reg, + cdc_rx_rxn_hd2_en_mask, 0); + snd_soc_component_update_bits(component, hd2_scale_reg, + cdc_rx_rxn_hd2_alpha_mask, 0x0); + } +} + +static int rx_macro_mux_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + ucontrol->value.integer.value[0] = + rx->rx_port_value[widget->shift]; + return 0; +} + +static int rx_macro_mux_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); + struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); + struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; + struct snd_soc_dapm_update *update = null; + u32 rx_port_value = ucontrol->value.integer.value[0]; + u32 aif_rst; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + aif_rst = rx->rx_port_value[widget->shift]; + if (!rx_port_value) { + if (aif_rst == 0) { + dev_err(component->dev, "%s:aif reset already ", __func__); + return 0; + } + if (aif_rst > rx_macro_aif4_pb) { + dev_err(component->dev, "%s: invalid aif reset ", __func__); + return 0; + } + } + rx->rx_port_value[widget->shift] = rx_port_value; + + switch (rx_port_value) { + case 0: + if (rx->active_ch_cnt[aif_rst]) { + clear_bit(widget->shift, + &rx->active_ch_mask[aif_rst]); + rx->active_ch_cnt[aif_rst]--; + } + break; + case 1: + case 2: + case 3: + case 4: + set_bit(widget->shift, + &rx->active_ch_mask[rx_port_value]); + rx->active_ch_cnt[rx_port_value]++; + break; + default: + dev_err(component->dev, + "%s:invalid aif_id for rx_macro mux %d ", + __func__, rx_port_value); + goto err; + } + + snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, + rx_port_value, e, update); + return 0; +err: + return -einval; +} + +static const struct snd_kcontrol_new rx_macro_rx0_mux = + soc_dapm_enum_ext("rx_macro_rx0", rx_macro_rx0_enum, + rx_macro_mux_get, rx_macro_mux_put); +static const struct snd_kcontrol_new rx_macro_rx1_mux = + soc_dapm_enum_ext("rx_macro_rx1", rx_macro_rx1_enum, + rx_macro_mux_get, rx_macro_mux_put); +static const struct snd_kcontrol_new rx_macro_rx2_mux = + soc_dapm_enum_ext("rx_macro_rx2", rx_macro_rx2_enum, + rx_macro_mux_get, rx_macro_mux_put); +static const struct snd_kcontrol_new rx_macro_rx3_mux = + soc_dapm_enum_ext("rx_macro_rx3", rx_macro_rx3_enum, + rx_macro_mux_get, rx_macro_mux_put); +static const struct snd_kcontrol_new rx_macro_rx4_mux = + soc_dapm_enum_ext("rx_macro_rx4", rx_macro_rx4_enum, + rx_macro_mux_get, rx_macro_mux_put); +static const struct snd_kcontrol_new rx_macro_rx5_mux = + soc_dapm_enum_ext("rx_macro_rx5", rx_macro_rx5_enum, + rx_macro_mux_get, rx_macro_mux_put); + +static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component, + struct rx_macro *rx, + u16 interp_idx, int event) +{ + u16 hph_lut_bypass_reg; + u16 hph_comp_ctrl7; + + switch (interp_idx) { + case interp_hphl: + hph_lut_bypass_reg = cdc_rx_top_hphl_comp_lut; + hph_comp_ctrl7 = cdc_rx_compander0_ctl7; + break; + case interp_hphr: + hph_lut_bypass_reg = cdc_rx_top_hphr_comp_lut; + hph_comp_ctrl7 = cdc_rx_compander1_ctl7; + break; + default: + return -einval; + } + + if (hph_lut_bypass_reg && snd_soc_dapm_event_on(event)) { + if (interp_idx == interp_hphl) { + if (rx->is_ear_mode_on) + snd_soc_component_write_field(component, + cdc_rx_rx0_rx_path_cfg1, + cdc_rx_rx0_hph_l_ear_sel_mask, 0x1); + else + snd_soc_component_write_field(component, + hph_lut_bypass_reg, + cdc_rx_top_hph_lut_bypass_mask, 1); + } else { + snd_soc_component_write_field(component, hph_lut_bypass_reg, + cdc_rx_top_hph_lut_bypass_mask, 1); + } + if (rx->hph_pwr_mode) + snd_soc_component_write_field(component, hph_comp_ctrl7, + cdc_rx_compander1_hph_low_pwr_mode_mask, 0x0); + } + + if (hph_lut_bypass_reg && snd_soc_dapm_event_off(event)) { + snd_soc_component_write_field(component, + cdc_rx_rx0_rx_path_cfg1, + cdc_rx_rx0_hph_l_ear_sel_mask, 0x0); + snd_soc_component_update_bits(component, hph_lut_bypass_reg, + cdc_rx_top_hph_lut_bypass_mask, 0); + snd_soc_component_write_field(component, hph_comp_ctrl7, + cdc_rx_compander1_hph_low_pwr_mode_mask, 0x1); + } + + return 0; +} + +static int rx_macro_enable_interp_clk(struct snd_soc_component *component, + int event, int interp_idx) +{ + u16 main_reg, dsm_reg, rx_cfg2_reg; + struct rx_macro *rx = snd_soc_component_get_drvdata(component); + + main_reg = cdc_rx_rxn_rx_path_ctl(interp_idx); + dsm_reg = cdc_rx_rxn_rx_path_dsm_ctl(interp_idx); + if (interp_idx == interp_aux) + dsm_reg = cdc_rx_rx2_rx_path_dsm_ctl; + rx_cfg2_reg = cdc_rx_rxn_rx_path_cfg2(interp_idx); + + if (snd_soc_dapm_event_on(event)) { + if (rx->main_clk_users[interp_idx] == 0) { + /* main path pga mute enable */ + snd_soc_component_write_field(component, main_reg, + cdc_rx_path_pga_mute_mask, 0x1); + snd_soc_component_write_field(component, dsm_reg, + cdc_rx_rxn_dsm_clk_en_mask, 0x1); + snd_soc_component_update_bits(component, rx_cfg2_reg, + cdc_rx_rxn_hpf_cut_freq_mask, 0x03); + rx_macro_load_compander_coeff(component, rx, interp_idx, event); + if (rx->hph_hd2_mode) + rx_macro_hd2_control(component, interp_idx, event); + rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); + rx_macro_config_compander(component, rx, interp_idx, event); + if (interp_idx == interp_aux) { + rx_macro_config_softclip(component, rx, event); + rx_macro_config_aux_hpf(component, rx, event); + } + rx_macro_config_classh(component, rx, interp_idx, event); + } + rx->main_clk_users[interp_idx]++; + } + + if (snd_soc_dapm_event_off(event)) { + rx->main_clk_users[interp_idx]--; + if (rx->main_clk_users[interp_idx] <= 0) { + rx->main_clk_users[interp_idx] = 0; + /* main path pga mute enable */ + snd_soc_component_write_field(component, main_reg, + cdc_rx_path_pga_mute_mask, 0x1); + /* clk disable */ + snd_soc_component_write_field(component, dsm_reg, + cdc_rx_rxn_dsm_clk_en_mask, 0); + snd_soc_component_write_field(component, main_reg, + cdc_rx_path_clk_en_mask, 0); + /* reset enable and disable */ + snd_soc_component_write_field(component, main_reg, + cdc_rx_path_reset_en_mask, 1); + snd_soc_component_write_field(component, main_reg, + cdc_rx_path_reset_en_mask, 0); + /* reset rate to 48k*/ + snd_soc_component_update_bits(component, main_reg, + cdc_rx_path_pcm_rate_mask, + 0x04); + snd_soc_component_update_bits(component, rx_cfg2_reg, + cdc_rx_rxn_hpf_cut_freq_mask, 0x00); + rx_macro_config_classh(component, rx, interp_idx, event); + rx_macro_config_compander(component, rx, interp_idx, event); + if (interp_idx == interp_aux) { + rx_macro_config_softclip(component, rx, event); + rx_macro_config_aux_hpf(component, rx, event); + } + rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); + if (rx->hph_hd2_mode) + rx_macro_hd2_control(component, interp_idx, event); + } + } + + return rx->main_clk_users[interp_idx]; +} + +static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + u16 gain_reg, mix_reg; + + gain_reg = cdc_rx_rxn_rx_vol_mix_ctl(w->shift); + mix_reg = cdc_rx_rxn_rx_path_mix_ctl(w->shift); + + switch (event) { + case snd_soc_dapm_pre_pmu: + rx_macro_enable_interp_clk(component, event, w->shift); + break; + case snd_soc_dapm_post_pmu: + snd_soc_component_write(component, gain_reg, + snd_soc_component_read(component, gain_reg)); + break; + case snd_soc_dapm_post_pmd: + /* clk disable */ + snd_soc_component_update_bits(component, mix_reg, + cdc_rx_rxn_mix_clk_en_mask, 0x00); + rx_macro_enable_interp_clk(component, event, w->shift); + /* reset enable and disable */ + snd_soc_component_update_bits(component, mix_reg, + cdc_rx_rxn_mix_reset_mask, + cdc_rx_rxn_mix_reset); + snd_soc_component_update_bits(component, mix_reg, + cdc_rx_rxn_mix_reset_mask, 0x00); + break; + } + + return 0; +} + +static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + + switch (event) { + case snd_soc_dapm_pre_pmu: + rx_macro_enable_interp_clk(component, event, w->shift); + snd_soc_component_write_field(component, cdc_rx_rxn_rx_path_cfg1(w->shift), + cdc_rx_rxn_sidetone_en_mask, 1); + snd_soc_component_write_field(component, cdc_rx_rxn_rx_path_ctl(w->shift), + cdc_rx_path_clk_en_mask, 1); + break; + case snd_soc_dapm_post_pmd: + snd_soc_component_write_field(component, cdc_rx_rxn_rx_path_cfg1(w->shift), + cdc_rx_rxn_sidetone_en_mask, 0); + rx_macro_enable_interp_clk(component, event, w->shift); + break; + default: + break; + }; + return 0; +} + -84, 40, digital_gain), +static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, + int event) +{ + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); + u16 val, ec_hq_reg; + int ec_tx; + + val = snd_soc_component_read(component, + cdc_rx_inp_mux_rx_mix_cfg4); + if (!(strcmp(w->name, "rx mix tx0 mux"))) + ec_tx = ((val & 0xf0) >> 0x4) - 1; + else if (!(strcmp(w->name, "rx mix tx1 mux"))) + ec_tx = (val & 0x0f) - 1; + + val = snd_soc_component_read(component, + cdc_rx_inp_mux_rx_mix_cfg5); + if (!(strcmp(w->name, "rx mix tx2 mux"))) + ec_tx = (val & 0x0f) - 1; + + if (ec_tx < 0 || (ec_tx >= rx_macro_ec_mux_max)) { + dev_err(component->dev, "%s: ec mix control not set correctly ", + __func__); + return -einval; + } + ec_hq_reg = cdc_rx_ec_ref_hq0_ec_ref_hq_path_ctl + + 0x40 * ec_tx; + snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); + ec_hq_reg = cdc_rx_ec_ref_hq0_ec_ref_hq_cfg0 + + 0x40 * ec_tx; + /* default set to 48k */ + snd_soc_component_update_bits(component, ec_hq_reg, 0x1e, 0x08); + + return 0; +} + +static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = { + snd_soc_dapm_aif_in("rx aif1 pb", "rx_macro_aif1 playback", 0, + snd_soc_nopm, 0, 0), + + snd_soc_dapm_aif_in("rx aif2 pb", "rx_macro_aif2 playback", 0, + snd_soc_nopm, 0, 0), + + snd_soc_dapm_aif_in("rx aif3 pb", "rx_macro_aif3 playback", 0, + snd_soc_nopm, 0, 0), + + snd_soc_dapm_aif_in("rx aif4 pb", "rx_macro_aif4 playback", 0, + snd_soc_nopm, 0, 0), + + snd_soc_dapm_aif_out("rx aif_echo", "rx_aif_echo capture", 0, + snd_soc_nopm, 0, 0), + + snd_soc_dapm_mux("rx_macro rx0 mux", snd_soc_nopm, rx_macro_rx0, 0, + &rx_macro_rx0_mux), + snd_soc_dapm_mux("rx_macro rx1 mux", snd_soc_nopm, rx_macro_rx1, 0, + &rx_macro_rx1_mux), + snd_soc_dapm_mux("rx_macro rx2 mux", snd_soc_nopm, rx_macro_rx2, 0, + &rx_macro_rx2_mux), + snd_soc_dapm_mux("rx_macro rx3 mux", snd_soc_nopm, rx_macro_rx3, 0, + &rx_macro_rx3_mux), + snd_soc_dapm_mux("rx_macro rx4 mux", snd_soc_nopm, rx_macro_rx4, 0, + &rx_macro_rx4_mux), + snd_soc_dapm_mux("rx_macro rx5 mux", snd_soc_nopm, rx_macro_rx5, 0, + &rx_macro_rx5_mux), + + snd_soc_dapm_mixer("rx_rx0", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx_rx1", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx_rx2", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx_rx3", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx_rx4", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx_rx5", snd_soc_nopm, 0, 0, null, 0), + + snd_soc_dapm_mux("iir0 inp0 mux", snd_soc_nopm, 0, 0, &iir0_inp0_mux), + snd_soc_dapm_mux("iir0 inp1 mux", snd_soc_nopm, 0, 0, &iir0_inp1_mux), + snd_soc_dapm_mux("iir0 inp2 mux", snd_soc_nopm, 0, 0, &iir0_inp2_mux), + snd_soc_dapm_mux("iir0 inp3 mux", snd_soc_nopm, 0, 0, &iir0_inp3_mux), + snd_soc_dapm_mux("iir1 inp0 mux", snd_soc_nopm, 0, 0, &iir1_inp0_mux), + snd_soc_dapm_mux("iir1 inp1 mux", snd_soc_nopm, 0, 0, &iir1_inp1_mux), + snd_soc_dapm_mux("iir1 inp2 mux", snd_soc_nopm, 0, 0, &iir1_inp2_mux), + snd_soc_dapm_mux("iir1 inp3 mux", snd_soc_nopm, 0, 0, &iir1_inp3_mux), + + snd_soc_dapm_mux_e("rx mix tx0 mux", snd_soc_nopm, + rx_macro_ec0_mux, 0, + &rx_mix_tx0_mux, rx_macro_enable_echo, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx mix tx1 mux", snd_soc_nopm, + rx_macro_ec1_mux, 0, + &rx_mix_tx1_mux, rx_macro_enable_echo, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx mix tx2 mux", snd_soc_nopm, + rx_macro_ec2_mux, 0, + &rx_mix_tx2_mux, rx_macro_enable_echo, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), + snd_soc_dapm_mixer("src0", cdc_rx_sidetone_src0_st_src_path_ctl, + 4, 0, null, 0), + snd_soc_dapm_mixer("src1", cdc_rx_sidetone_src1_st_src_path_ctl, + 4, 0, null, 0), + + snd_soc_dapm_mux("rx int0 dem mux", snd_soc_nopm, 0, 0, + &rx_int0_dem_inp_mux), + snd_soc_dapm_mux("rx int1 dem mux", snd_soc_nopm, 0, 0, + &rx_int1_dem_inp_mux), + + snd_soc_dapm_mux_e("rx int0_2 mux", snd_soc_nopm, interp_hphl, 0, + &rx_int0_2_mux, rx_macro_enable_mix_path, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx int1_2 mux", snd_soc_nopm, interp_hphr, 0, + &rx_int1_2_mux, rx_macro_enable_mix_path, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx int2_2 mux", snd_soc_nopm, interp_aux, 0, + &rx_int2_2_mux, rx_macro_enable_mix_path, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + + snd_soc_dapm_mux("rx int0_1 mix1 inp0", snd_soc_nopm, 0, 0, &rx_int0_1_mix_inp0_mux), + snd_soc_dapm_mux("rx int0_1 mix1 inp1", snd_soc_nopm, 0, 0, &rx_int0_1_mix_inp1_mux), + snd_soc_dapm_mux("rx int0_1 mix1 inp2", snd_soc_nopm, 0, 0, &rx_int0_1_mix_inp2_mux), + snd_soc_dapm_mux("rx int1_1 mix1 inp0", snd_soc_nopm, 0, 0, &rx_int1_1_mix_inp0_mux), + snd_soc_dapm_mux("rx int1_1 mix1 inp1", snd_soc_nopm, 0, 0, &rx_int1_1_mix_inp1_mux), + snd_soc_dapm_mux("rx int1_1 mix1 inp2", snd_soc_nopm, 0, 0, &rx_int1_1_mix_inp2_mux), + snd_soc_dapm_mux("rx int2_1 mix1 inp0", snd_soc_nopm, 0, 0, &rx_int2_1_mix_inp0_mux), + snd_soc_dapm_mux("rx int2_1 mix1 inp1", snd_soc_nopm, 0, 0, &rx_int2_1_mix_inp1_mux), + snd_soc_dapm_mux("rx int2_1 mix1 inp2", snd_soc_nopm, 0, 0, &rx_int2_1_mix_inp2_mux), + + snd_soc_dapm_mux_e("rx int0_1 interp", snd_soc_nopm, interp_hphl, 0, + &rx_int0_1_interp_mux, rx_macro_enable_main_path, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx int1_1 interp", snd_soc_nopm, interp_hphr, 0, + &rx_int1_1_interp_mux, rx_macro_enable_main_path, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx int2_1 interp", snd_soc_nopm, interp_aux, 0, + &rx_int2_1_interp_mux, rx_macro_enable_main_path, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmu | + snd_soc_dapm_post_pmd), + + snd_soc_dapm_mux("rx int0_2 interp", snd_soc_nopm, 0, 0, + &rx_int0_2_interp_mux), + snd_soc_dapm_mux("rx int1_2 interp", snd_soc_nopm, 0, 0, + &rx_int1_2_interp_mux), + snd_soc_dapm_mux("rx int2_2 interp", snd_soc_nopm, 0, 0, + &rx_int2_2_interp_mux), + + snd_soc_dapm_mixer("rx int0_1 mix1", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int0 sec mix", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int1_1 mix1", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int1 sec mix", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int2_1 mix1", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int2 sec mix", snd_soc_nopm, 0, 0, null, 0), + + snd_soc_dapm_mux_e("rx int0 mix2 inp", snd_soc_nopm, interp_hphl, + 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx int1 mix2 inp", snd_soc_nopm, interp_hphr, + 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), + snd_soc_dapm_mux_e("rx int2 mix2 inp", snd_soc_nopm, interp_aux, + 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk, + snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), + + snd_soc_dapm_mixer("rx int0 mix2", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int1 mix2", snd_soc_nopm, 0, 0, null, 0), + snd_soc_dapm_mixer("rx int2 mix2", snd_soc_nopm, 0, 0, null, 0), + + snd_soc_dapm_output("hphl_out"), + snd_soc_dapm_output("hphr_out"), + snd_soc_dapm_output("aux_out"), + + snd_soc_dapm_input("rx_tx dec0_inp"), + snd_soc_dapm_input("rx_tx dec1_inp"), + snd_soc_dapm_input("rx_tx dec2_inp"), + snd_soc_dapm_input("rx_tx dec3_inp"), + + snd_soc_dapm_supply_s("rx_mclk", 0, snd_soc_nopm, 0, 0, + rx_macro_mclk_event, snd_soc_dapm_pre_pmu | snd_soc_dapm_post_pmd), +}; + +static const struct snd_soc_dapm_route rx_audio_map[] = { + {"rx aif1 pb", null, "rx_mclk"}, + {"rx aif2 pb", null, "rx_mclk"}, + {"rx aif3 pb", null, "rx_mclk"}, + {"rx aif4 pb", null, "rx_mclk"}, + + {"rx_macro rx0 mux", "aif1_pb", "rx aif1 pb"}, + {"rx_macro rx1 mux", "aif1_pb", "rx aif1 pb"}, + {"rx_macro rx2 mux", "aif1_pb", "rx aif1 pb"}, + {"rx_macro rx3 mux", "aif1_pb", "rx aif1 pb"}, + {"rx_macro rx4 mux", "aif1_pb", "rx aif1 pb"}, + {"rx_macro rx5 mux", "aif1_pb", "rx aif1 pb"}, + + {"rx_macro rx0 mux", "aif2_pb", "rx aif2 pb"}, + {"rx_macro rx1 mux", "aif2_pb", "rx aif2 pb"}, + {"rx_macro rx2 mux", "aif2_pb", "rx aif2 pb"}, + {"rx_macro rx3 mux", "aif2_pb", "rx aif2 pb"}, + {"rx_macro rx4 mux", "aif2_pb", "rx aif2 pb"}, + {"rx_macro rx5 mux", "aif2_pb", "rx aif2 pb"}, + + {"rx_macro rx0 mux", "aif3_pb", "rx aif3 pb"}, + {"rx_macro rx1 mux", "aif3_pb", "rx aif3 pb"}, + {"rx_macro rx2 mux", "aif3_pb", "rx aif3 pb"}, + {"rx_macro rx3 mux", "aif3_pb", "rx aif3 pb"}, + {"rx_macro rx4 mux", "aif3_pb", "rx aif3 pb"}, + {"rx_macro rx5 mux", "aif3_pb", "rx aif3 pb"}, + + {"rx_macro rx0 mux", "aif4_pb", "rx aif4 pb"}, + {"rx_macro rx1 mux", "aif4_pb", "rx aif4 pb"}, + {"rx_macro rx2 mux", "aif4_pb", "rx aif4 pb"}, + {"rx_macro rx3 mux", "aif4_pb", "rx aif4 pb"}, + {"rx_macro rx4 mux", "aif4_pb", "rx aif4 pb"}, + {"rx_macro rx5 mux", "aif4_pb", "rx aif4 pb"}, + + {"rx_rx0", null, "rx_macro rx0 mux"}, + {"rx_rx1", null, "rx_macro rx1 mux"}, + {"rx_rx2", null, "rx_macro rx2 mux"}, + {"rx_rx3", null, "rx_macro rx3 mux"}, + {"rx_rx4", null, "rx_macro rx4 mux"}, + {"rx_rx5", null, "rx_macro rx5 mux"}, + + {"rx int0_1 mix1 inp0", "rx0", "rx_rx0"}, + {"rx int0_1 mix1 inp0", "rx1", "rx_rx1"}, + {"rx int0_1 mix1 inp0", "rx2", "rx_rx2"}, + {"rx int0_1 mix1 inp0", "rx3", "rx_rx3"}, + {"rx int0_1 mix1 inp0", "rx4", "rx_rx4"}, + {"rx int0_1 mix1 inp0", "rx5", "rx_rx5"}, + {"rx int0_1 mix1 inp0", "iir0", "iir0"}, + {"rx int0_1 mix1 inp0", "iir1", "iir1"}, + {"rx int0_1 mix1 inp0", "dec0", "rx_tx dec0_inp"}, + {"rx int0_1 mix1 inp0", "dec1", "rx_tx dec1_inp"}, + {"rx int0_1 mix1 inp1", "rx0", "rx_rx0"}, + {"rx int0_1 mix1 inp1", "rx1", "rx_rx1"}, + {"rx int0_1 mix1 inp1", "rx2", "rx_rx2"}, + {"rx int0_1 mix1 inp1", "rx3", "rx_rx3"}, + {"rx int0_1 mix1 inp1", "rx4", "rx_rx4"}, + {"rx int0_1 mix1 inp1", "rx5", "rx_rx5"}, + {"rx int0_1 mix1 inp1", "iir0", "iir0"}, + {"rx int0_1 mix1 inp1", "iir1", "iir1"}, + {"rx int0_1 mix1 inp1", "dec0", "rx_tx dec0_inp"}, + {"rx int0_1 mix1 inp1", "dec1", "rx_tx dec1_inp"}, + {"rx int0_1 mix1 inp2", "rx0", "rx_rx0"}, + {"rx int0_1 mix1 inp2", "rx1", "rx_rx1"}, + {"rx int0_1 mix1 inp2", "rx2", "rx_rx2"}, + {"rx int0_1 mix1 inp2", "rx3", "rx_rx3"}, + {"rx int0_1 mix1 inp2", "rx4", "rx_rx4"}, + {"rx int0_1 mix1 inp2", "rx5", "rx_rx5"}, + {"rx int0_1 mix1 inp2", "iir0", "iir0"}, + {"rx int0_1 mix1 inp2", "iir1", "iir1"}, + {"rx int0_1 mix1 inp2", "dec0", "rx_tx dec0_inp"}, + {"rx int0_1 mix1 inp2", "dec1", "rx_tx dec1_inp"}, + + {"rx int1_1 mix1 inp0", "rx0", "rx_rx0"}, + {"rx int1_1 mix1 inp0", "rx1", "rx_rx1"}, + {"rx int1_1 mix1 inp0", "rx2", "rx_rx2"}, + {"rx int1_1 mix1 inp0", "rx3", "rx_rx3"}, + {"rx int1_1 mix1 inp0", "rx4", "rx_rx4"}, + {"rx int1_1 mix1 inp0", "rx5", "rx_rx5"}, + {"rx int1_1 mix1 inp0", "iir0", "iir0"}, + {"rx int1_1 mix1 inp0", "iir1", "iir1"}, + {"rx int1_1 mix1 inp0", "dec0", "rx_tx dec0_inp"}, + {"rx int1_1 mix1 inp0", "dec1", "rx_tx dec1_inp"}, + {"rx int1_1 mix1 inp1", "rx0", "rx_rx0"}, + {"rx int1_1 mix1 inp1", "rx1", "rx_rx1"}, + {"rx int1_1 mix1 inp1", "rx2", "rx_rx2"}, + {"rx int1_1 mix1 inp1", "rx3", "rx_rx3"}, + {"rx int1_1 mix1 inp1", "rx4", "rx_rx4"}, + {"rx int1_1 mix1 inp1", "rx5", "rx_rx5"}, + {"rx int1_1 mix1 inp1", "iir0", "iir0"}, + {"rx int1_1 mix1 inp1", "iir1", "iir1"}, + {"rx int1_1 mix1 inp1", "dec0", "rx_tx dec0_inp"}, + {"rx int1_1 mix1 inp1", "dec1", "rx_tx dec1_inp"}, + {"rx int1_1 mix1 inp2", "rx0", "rx_rx0"}, + {"rx int1_1 mix1 inp2", "rx1", "rx_rx1"}, + {"rx int1_1 mix1 inp2", "rx2", "rx_rx2"}, + {"rx int1_1 mix1 inp2", "rx3", "rx_rx3"}, + {"rx int1_1 mix1 inp2", "rx4", "rx_rx4"}, + {"rx int1_1 mix1 inp2", "rx5", "rx_rx5"}, + {"rx int1_1 mix1 inp2", "iir0", "iir0"}, + {"rx int1_1 mix1 inp2", "iir1", "iir1"}, + {"rx int1_1 mix1 inp2", "dec0", "rx_tx dec0_inp"}, + {"rx int1_1 mix1 inp2", "dec1", "rx_tx dec1_inp"}, + + {"rx int2_1 mix1 inp0", "rx0", "rx_rx0"}, + {"rx int2_1 mix1 inp0", "rx1", "rx_rx1"}, + {"rx int2_1 mix1 inp0", "rx2", "rx_rx2"}, + {"rx int2_1 mix1 inp0", "rx3", "rx_rx3"}, + {"rx int2_1 mix1 inp0", "rx4", "rx_rx4"}, + {"rx int2_1 mix1 inp0", "rx5", "rx_rx5"}, + {"rx int2_1 mix1 inp0", "iir0", "iir0"}, + {"rx int2_1 mix1 inp0", "iir1", "iir1"}, + {"rx int2_1 mix1 inp0", "dec0", "rx_tx dec0_inp"}, + {"rx int2_1 mix1 inp0", "dec1", "rx_tx dec1_inp"}, + {"rx int2_1 mix1 inp1", "rx0", "rx_rx0"}, + {"rx int2_1 mix1 inp1", "rx1", "rx_rx1"}, + {"rx int2_1 mix1 inp1", "rx2", "rx_rx2"}, + {"rx int2_1 mix1 inp1", "rx3", "rx_rx3"}, + {"rx int2_1 mix1 inp1", "rx4", "rx_rx4"}, + {"rx int2_1 mix1 inp1", "rx5", "rx_rx5"}, + {"rx int2_1 mix1 inp1", "iir0", "iir0"}, + {"rx int2_1 mix1 inp1", "iir1", "iir1"}, + {"rx int2_1 mix1 inp1", "dec0", "rx_tx dec0_inp"}, + {"rx int2_1 mix1 inp1", "dec1", "rx_tx dec1_inp"}, + {"rx int2_1 mix1 inp2", "rx0", "rx_rx0"}, + {"rx int2_1 mix1 inp2", "rx1", "rx_rx1"}, + {"rx int2_1 mix1 inp2", "rx2", "rx_rx2"}, + {"rx int2_1 mix1 inp2", "rx3", "rx_rx3"}, + {"rx int2_1 mix1 inp2", "rx4", "rx_rx4"}, + {"rx int2_1 mix1 inp2", "rx5", "rx_rx5"}, + {"rx int2_1 mix1 inp2", "iir0", "iir0"}, + {"rx int2_1 mix1 inp2", "iir1", "iir1"}, + {"rx int2_1 mix1 inp2", "dec0", "rx_tx dec0_inp"}, + {"rx int2_1 mix1 inp2", "dec1", "rx_tx dec1_inp"}, + + {"rx int0_1 mix1", null, "rx int0_1 mix1 inp0"}, + {"rx int0_1 mix1", null, "rx int0_1 mix1 inp1"}, + {"rx int0_1 mix1", null, "rx int0_1 mix1 inp2"}, + {"rx int1_1 mix1", null, "rx int1_1 mix1 inp0"}, + {"rx int1_1 mix1", null, "rx int1_1 mix1 inp1"}, + {"rx int1_1 mix1", null, "rx int1_1 mix1 inp2"}, + {"rx int2_1 mix1", null, "rx int2_1 mix1 inp0"}, + {"rx int2_1 mix1", null, "rx int2_1 mix1 inp1"}, + {"rx int2_1 mix1", null, "rx int2_1 mix1 inp2"}, + + {"rx mix tx0 mux", "rx_mix0", "rx int0 sec mix"}, + {"rx mix tx0 mux", "rx_mix1", "rx int1 sec mix"}, + {"rx mix tx0 mux", "rx_mix2", "rx int2 sec mix"}, + {"rx mix tx1 mux", "rx_mix0", "rx int0 sec mix"}, + {"rx mix tx1 mux", "rx_mix1", "rx int1 sec mix"}, + {"rx mix tx1 mux", "rx_mix2", "rx int2 sec mix"}, + {"rx mix tx2 mux", "rx_mix0", "rx int0 sec mix"}, + {"rx mix tx2 mux", "rx_mix1", "rx int1 sec mix"}, + {"rx mix tx2 mux", "rx_mix2", "rx int2 sec mix"}, + {"rx aif_echo", null, "rx mix tx0 mux"}, + {"rx aif_echo", null, "rx mix tx1 mux"}, + {"rx aif_echo", null, "rx mix tx2 mux"}, + {"rx aif_echo", null, "rx_mclk"}, + + /* mixing path int0 */ + {"rx int0_2 mux", "rx0", "rx_rx0"}, + {"rx int0_2 mux", "rx1", "rx_rx1"}, + {"rx int0_2 mux", "rx2", "rx_rx2"}, + {"rx int0_2 mux", "rx3", "rx_rx3"}, + {"rx int0_2 mux", "rx4", "rx_rx4"}, + {"rx int0_2 mux", "rx5", "rx_rx5"}, + {"rx int0_2 interp", null, "rx int0_2 mux"}, + {"rx int0 sec mix", null, "rx int0_2 interp"}, + + /* mixing path int1 */ + {"rx int1_2 mux", "rx0", "rx_rx0"}, + {"rx int1_2 mux", "rx1", "rx_rx1"}, + {"rx int1_2 mux", "rx2", "rx_rx2"}, + {"rx int1_2 mux", "rx3", "rx_rx3"}, + {"rx int1_2 mux", "rx4", "rx_rx4"}, + {"rx int1_2 mux", "rx5", "rx_rx5"}, + {"rx int1_2 interp", null, "rx int1_2 mux"}, + {"rx int1 sec mix", null, "rx int1_2 interp"}, + + /* mixing path int2 */ + {"rx int2_2 mux", "rx0", "rx_rx0"}, + {"rx int2_2 mux", "rx1", "rx_rx1"}, + {"rx int2_2 mux", "rx2", "rx_rx2"}, + {"rx int2_2 mux", "rx3", "rx_rx3"}, + {"rx int2_2 mux", "rx4", "rx_rx4"}, + {"rx int2_2 mux", "rx5", "rx_rx5"}, + {"rx int2_2 interp", null, "rx int2_2 mux"}, + {"rx int2 sec mix", null, "rx int2_2 interp"}, + + {"rx int0_1 interp", null, "rx int0_1 mix1"}, + {"rx int0 sec mix", null, "rx int0_1 interp"}, + {"rx int0 mix2", null, "rx int0 sec mix"}, + {"rx int0 mix2", null, "rx int0 mix2 inp"}, + {"rx int0 dem mux", "clsh_dsm_out", "rx int0 mix2"}, + {"hphl_out", null, "rx int0 dem mux"}, + {"hphl_out", null, "rx_mclk"}, + + {"rx int1_1 interp", null, "rx int1_1 mix1"}, + {"rx int1 sec mix", null, "rx int1_1 interp"}, + {"rx int1 mix2", null, "rx int1 sec mix"}, + {"rx int1 mix2", null, "rx int1 mix2 inp"}, + {"rx int1 dem mux", "clsh_dsm_out", "rx int1 mix2"}, + {"hphr_out", null, "rx int1 dem mux"}, + {"hphr_out", null, "rx_mclk"}, + + {"rx int2_1 interp", null, "rx int2_1 mix1"}, + + {"rx int2 sec mix", null, "rx int2_1 interp"}, + {"rx int2 mix2", null, "rx int2 sec mix"}, + {"rx int2 mix2", null, "rx int2 mix2 inp"}, + {"aux_out", null, "rx int2 mix2"}, + {"aux_out", null, "rx_mclk"}, + + {"iir0", null, "rx_mclk"}, + {"iir0", null, "iir0 inp0 mux"}, + {"iir0 inp0 mux", "dec0", "rx_tx dec0_inp"}, + {"iir0 inp0 mux", "dec1", "rx_tx dec1_inp"}, + {"iir0 inp0 mux", "dec2", "rx_tx dec2_inp"}, + {"iir0 inp0 mux", "dec3", "rx_tx dec3_inp"}, + {"iir0 inp0 mux", "rx0", "rx_rx0"}, + {"iir0 inp0 mux", "rx1", "rx_rx1"}, + {"iir0 inp0 mux", "rx2", "rx_rx2"}, + {"iir0 inp0 mux", "rx3", "rx_rx3"}, + {"iir0 inp0 mux", "rx4", "rx_rx4"}, + {"iir0 inp0 mux", "rx5", "rx_rx5"}, + {"iir0", null, "iir0 inp1 mux"}, + {"iir0 inp1 mux", "dec0", "rx_tx dec0_inp"}, + {"iir0 inp1 mux", "dec1", "rx_tx dec1_inp"}, + {"iir0 inp1 mux", "dec2", "rx_tx dec2_inp"}, + {"iir0 inp1 mux", "dec3", "rx_tx dec3_inp"}, + {"iir0 inp1 mux", "rx0", "rx_rx0"}, + {"iir0 inp1 mux", "rx1", "rx_rx1"}, + {"iir0 inp1 mux", "rx2", "rx_rx2"}, + {"iir0 inp1 mux", "rx3", "rx_rx3"}, + {"iir0 inp1 mux", "rx4", "rx_rx4"}, + {"iir0 inp1 mux", "rx5", "rx_rx5"}, + {"iir0", null, "iir0 inp2 mux"}, + {"iir0 inp2 mux", "dec0", "rx_tx dec0_inp"}, + {"iir0 inp2 mux", "dec1", "rx_tx dec1_inp"}, + {"iir0 inp2 mux", "dec2", "rx_tx dec2_inp"}, + {"iir0 inp2 mux", "dec3", "rx_tx dec3_inp"}, + {"iir0 inp2 mux", "rx0", "rx_rx0"}, + {"iir0 inp2 mux", "rx1", "rx_rx1"}, + {"iir0 inp2 mux", "rx2", "rx_rx2"}, + {"iir0 inp2 mux", "rx3", "rx_rx3"}, + {"iir0 inp2 mux", "rx4", "rx_rx4"}, + {"iir0 inp2 mux", "rx5", "rx_rx5"}, + {"iir0", null, "iir0 inp3 mux"}, + {"iir0 inp3 mux", "dec0", "rx_tx dec0_inp"}, + {"iir0 inp3 mux", "dec1", "rx_tx dec1_inp"}, + {"iir0 inp3 mux", "dec2", "rx_tx dec2_inp"}, + {"iir0 inp3 mux", "dec3", "rx_tx dec3_inp"}, + {"iir0 inp3 mux", "rx0", "rx_rx0"}, + {"iir0 inp3 mux", "rx1", "rx_rx1"}, + {"iir0 inp3 mux", "rx2", "rx_rx2"}, + {"iir0 inp3 mux", "rx3", "rx_rx3"}, + {"iir0 inp3 mux", "rx4", "rx_rx4"}, + {"iir0 inp3 mux", "rx5", "rx_rx5"}, + + {"iir1", null, "rx_mclk"}, + {"iir1", null, "iir1 inp0 mux"}, + {"iir1 inp0 mux", "dec0", "rx_tx dec0_inp"}, + {"iir1 inp0 mux", "dec1", "rx_tx dec1_inp"}, + {"iir1 inp0 mux", "dec2", "rx_tx dec2_inp"}, + {"iir1 inp0 mux", "dec3", "rx_tx dec3_inp"}, + {"iir1 inp0 mux", "rx0", "rx_rx0"}, + {"iir1 inp0 mux", "rx1", "rx_rx1"}, + {"iir1 inp0 mux", "rx2", "rx_rx2"}, + {"iir1 inp0 mux", "rx3", "rx_rx3"}, + {"iir1 inp0 mux", "rx4", "rx_rx4"}, + {"iir1 inp0 mux", "rx5", "rx_rx5"}, + {"iir1", null, "iir1 inp1 mux"}, + {"iir1 inp1 mux", "dec0", "rx_tx dec0_inp"}, + {"iir1 inp1 mux", "dec1", "rx_tx dec1_inp"}, + {"iir1 inp1 mux", "dec2", "rx_tx dec2_inp"}, + {"iir1 inp1 mux", "dec3", "rx_tx dec3_inp"}, + {"iir1 inp1 mux", "rx0", "rx_rx0"}, + {"iir1 inp1 mux", "rx1", "rx_rx1"}, + {"iir1 inp1 mux", "rx2", "rx_rx2"}, + {"iir1 inp1 mux", "rx3", "rx_rx3"}, + {"iir1 inp1 mux", "rx4", "rx_rx4"}, + {"iir1 inp1 mux", "rx5", "rx_rx5"}, + {"iir1", null, "iir1 inp2 mux"}, + {"iir1 inp2 mux", "dec0", "rx_tx dec0_inp"}, + {"iir1 inp2 mux", "dec1", "rx_tx dec1_inp"}, + {"iir1 inp2 mux", "dec2", "rx_tx dec2_inp"}, + {"iir1 inp2 mux", "dec3", "rx_tx dec3_inp"}, + {"iir1 inp2 mux", "rx0", "rx_rx0"}, + {"iir1 inp2 mux", "rx1", "rx_rx1"}, + {"iir1 inp2 mux", "rx2", "rx_rx2"}, + {"iir1 inp2 mux", "rx3", "rx_rx3"}, + {"iir1 inp2 mux", "rx4", "rx_rx4"}, + {"iir1 inp2 mux", "rx5", "rx_rx5"}, + {"iir1", null, "iir1 inp3 mux"}, + {"iir1 inp3 mux", "dec0", "rx_tx dec0_inp"}, + {"iir1 inp3 mux", "dec1", "rx_tx dec1_inp"}, + {"iir1 inp3 mux", "dec2", "rx_tx dec2_inp"}, + {"iir1 inp3 mux", "dec3", "rx_tx dec3_inp"}, + {"iir1 inp3 mux", "rx0", "rx_rx0"}, + {"iir1 inp3 mux", "rx1", "rx_rx1"}, + {"iir1 inp3 mux", "rx2", "rx_rx2"}, + {"iir1 inp3 mux", "rx3", "rx_rx3"}, + {"iir1 inp3 mux", "rx4", "rx_rx4"}, + {"iir1 inp3 mux", "rx5", "rx_rx5"}, + + {"src0", null, "iir0"}, + {"src1", null, "iir1"}, + {"rx int0 mix2 inp", "src0", "src0"}, + {"rx int0 mix2 inp", "src1", "src1"}, + {"rx int1 mix2 inp", "src0", "src0"}, + {"rx int1 mix2 inp", "src1", "src1"}, + {"rx int2 mix2 inp", "src0", "src0"}, + {"rx int2 mix2 inp", "src1", "src1"}, +}; + + .dapm_widgets = rx_macro_dapm_widgets, + .num_dapm_widgets = array_size(rx_macro_dapm_widgets), + .dapm_routes = rx_audio_map, + .num_dapm_routes = array_size(rx_audio_map),
|
Audio
|
4f692926f562ff48abfcca6b16f36ff8d57473b6
|
srinivas kandagatla
|
sound
|
soc
|
codecs
|
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