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net: dsa: felix: convert to the new .change_tag_protocol dsa api
|
in expectation of the new tag_ocelot_8021q tagger implementation, we need to be able to do runtime switchover between one tagger and another. so we must structure the existing code for the current npi-based tagger in a certain way.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
tag_8021q for ocelot switches
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ']
|
['h', 'c']
| 4
| 154
| 35
|
--- diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c -/* copyright 2019 nxp semiconductors +/* copyright 2019-2021 nxp semiconductors +/* the cpu port module is connected to the node processor interface (npi). this + * is the mode through which frames can be injected from and extracted to an + * external cpu, over ethernet. in nxp socs, the "external cpu" is the arm cpu + * running linux, and this forms a dsa setup together with the enetc or fman + * dsa master. + */ +static void felix_npi_port_init(struct ocelot *ocelot, int port) +{ + ocelot->npi = port; + + ocelot_write(ocelot, qsys_ext_cpu_cfg_ext_cpuq_msk_m | + qsys_ext_cpu_cfg_ext_cpu_port(port), + qsys_ext_cpu_cfg); + + /* npi port injection/extraction configuration */ + ocelot_fields_write(ocelot, port, sys_port_mode_incl_xtr_hdr, + ocelot->npi_xtr_prefix); + ocelot_fields_write(ocelot, port, sys_port_mode_incl_inj_hdr, + ocelot->npi_inj_prefix); + + /* disable transmission of pause frames */ + ocelot_fields_write(ocelot, port, sys_pause_cfg_pause_ena, 0); +} + +static void felix_npi_port_deinit(struct ocelot *ocelot, int port) +{ + /* restore hardware defaults */ + int unused_port = ocelot->num_phys_ports + 2; + + ocelot->npi = -1; + + ocelot_write(ocelot, qsys_ext_cpu_cfg_ext_cpu_port(unused_port), + qsys_ext_cpu_cfg); + + ocelot_fields_write(ocelot, port, sys_port_mode_incl_xtr_hdr, + ocelot_tag_prefix_disabled); + ocelot_fields_write(ocelot, port, sys_port_mode_incl_inj_hdr, + ocelot_tag_prefix_disabled); + + /* enable transmission of pause frames */ + ocelot_fields_write(ocelot, port, sys_pause_cfg_pause_ena, 1); +} + +static int felix_setup_tag_npi(struct dsa_switch *ds, int cpu) +{ + struct ocelot *ocelot = ds->priv; + unsigned long cpu_flood; + + felix_npi_port_init(ocelot, cpu); + + /* include the cpu port module (and indirectly, the npi port) + * in the forwarding mask for unknown unicast - the hardware + * default value for ana_flooding_fld_unicast excludes + * bit(ocelot->num_phys_ports), and so does ocelot_init, + * since ocelot relies on whitelisting mac addresses towards + * pgid_cpu. + * we do this because dsa does not yet perform rx filtering, + * and the npi port does not perform source address learning, + * so traffic sent to linux is effectively unknown from the + * switch's perspective. + */ + cpu_flood = ana_pgid_pgid_pgid(bit(ocelot->num_phys_ports)); + ocelot_rmw_rix(ocelot, cpu_flood, cpu_flood, ana_pgid_pgid, pgid_uc); + + return 0; +} + +static void felix_teardown_tag_npi(struct dsa_switch *ds, int cpu) +{ + struct ocelot *ocelot = ds->priv; + + felix_npi_port_deinit(ocelot, cpu); +} + +static int felix_set_tag_protocol(struct dsa_switch *ds, int cpu, + enum dsa_tag_protocol proto) +{ + int err; + + switch (proto) { + case dsa_tag_proto_ocelot: + err = felix_setup_tag_npi(ds, cpu); + break; + default: + err = -eprotonosupport; + } + + return err; +} + +static void felix_del_tag_protocol(struct dsa_switch *ds, int cpu, + enum dsa_tag_protocol proto) +{ + switch (proto) { + case dsa_tag_proto_ocelot: + felix_teardown_tag_npi(ds, cpu); + break; + default: + break; + } +} + +static int felix_change_tag_protocol(struct dsa_switch *ds, int cpu, + enum dsa_tag_protocol proto) +{ + struct ocelot *ocelot = ds->priv; + struct felix *felix = ocelot_to_felix(ocelot); + enum dsa_tag_protocol old_proto = felix->tag_proto; + int err; + + if (proto != dsa_tag_proto_ocelot) + return -eprotonosupport; + + felix_del_tag_protocol(ds, cpu, old_proto); + + err = felix_set_tag_protocol(ds, cpu, proto); + if (err) { + felix_set_tag_protocol(ds, cpu, old_proto); + return err; + } + + felix->tag_proto = proto; + + return 0; +} + - return dsa_tag_proto_ocelot; + struct ocelot *ocelot = ds->priv; + struct felix *felix = ocelot_to_felix(ocelot); + + return felix->tag_proto; -/* the cpu port module is connected to the node processor interface (npi). this - * is the mode through which frames can be injected from and extracted to an - * external cpu, over ethernet. - */ -static void felix_npi_port_init(struct ocelot *ocelot, int port) -{ - ocelot->npi = port; - - ocelot_write(ocelot, qsys_ext_cpu_cfg_ext_cpuq_msk_m | - qsys_ext_cpu_cfg_ext_cpu_port(port), - qsys_ext_cpu_cfg); - - /* npi port injection/extraction configuration */ - ocelot_fields_write(ocelot, port, sys_port_mode_incl_xtr_hdr, - ocelot->npi_xtr_prefix); - ocelot_fields_write(ocelot, port, sys_port_mode_incl_inj_hdr, - ocelot->npi_inj_prefix); - - /* disable transmission of pause frames */ - ocelot_fields_write(ocelot, port, sys_pause_cfg_pause_ena, 0); -} - - ocelot_init_port(ocelot, port); + if (dsa_is_unused_port(ds, port)) + continue; - if (dsa_is_cpu_port(ds, port)) - felix_npi_port_init(ocelot, port); + ocelot_init_port(ocelot, port); - /* include the cpu port module in the forwarding mask for unknown - * unicast - the hardware default value for ana_flooding_fld_unicast - * excludes bit(ocelot->num_phys_ports), and so does ocelot_init, since - * ocelot relies on whitelisting mac addresses towards pgid_cpu. - */ - ocelot_write_rix(ocelot, - ana_pgid_pgid_pgid(genmask(ocelot->num_phys_ports, 0)), - ana_pgid_pgid, pgid_uc); + for (port = 0; port < ds->num_ports; port++) { + if (!dsa_is_cpu_port(ds, port)) + continue; + + /* the initial tag protocol is npi which always returns 0, so + * there's no real point in checking for errors. + */ + felix_set_tag_protocol(ds, port, felix->tag_proto); + } + for (port = 0; port < ds->num_ports; port++) { + if (!dsa_is_cpu_port(ds, port)) + continue; + + felix_del_tag_protocol(ds, port, felix->tag_proto); + } + + .change_tag_protocol = felix_change_tag_protocol, diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h + enum dsa_tag_protocol tag_proto; diff --git a/drivers/net/dsa/ocelot/felix_vsc9959.c b/drivers/net/dsa/ocelot/felix_vsc9959.c --- a/drivers/net/dsa/ocelot/felix_vsc9959.c +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c + felix->tag_proto = dsa_tag_proto_ocelot; diff --git a/drivers/net/dsa/ocelot/seville_vsc9953.c b/drivers/net/dsa/ocelot/seville_vsc9953.c --- a/drivers/net/dsa/ocelot/seville_vsc9953.c +++ b/drivers/net/dsa/ocelot/seville_vsc9953.c + felix->tag_proto = dsa_tag_proto_ocelot;
|
Networking
|
adb3dccf090bc53ce177cd30bbe5b985336a6f66
|
vladimir oltean
|
drivers
|
net
|
dsa, ocelot
|
net: dsa: add a second tagger for ocelot switches based on tag_8021q
|
there are use cases for which the existing tagger, based on the npi (node processor interface) functionality, is insufficient.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
tag_8021q for ocelot switches
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ']
|
['c', 'h', 'kconfig', 'maintainers', 'makefile']
| 6
| 92
| 3
|
- frames injected through the npi port bypass the frame analyzer, so no - flow control is not functional over an npi port (pause frames are - there can be at most one npi port configured for an ocelot switch. but --- diff --git a/maintainers b/maintainers --- a/maintainers +++ b/maintainers +f: net/dsa/tag_ocelot_8021q.c diff --git a/drivers/net/dsa/ocelot/kconfig b/drivers/net/dsa/ocelot/kconfig --- a/drivers/net/dsa/ocelot/kconfig +++ b/drivers/net/dsa/ocelot/kconfig + select net_dsa_tag_ocelot_8021q + select net_dsa_tag_ocelot_8021q diff --git a/include/net/dsa.h b/include/net/dsa.h --- a/include/net/dsa.h +++ b/include/net/dsa.h +#define dsa_tag_proto_ocelot_8021q_value 20 + dsa_tag_proto_ocelot_8021q = dsa_tag_proto_ocelot_8021q_value, diff --git a/net/dsa/kconfig b/net/dsa/kconfig --- a/net/dsa/kconfig +++ b/net/dsa/kconfig - tristate "tag driver for ocelot family of switches" + tristate "tag driver for ocelot family of switches, using npi port" - say y or m if you want to enable support for tagging frames for the - ocelot switches (vsc7511, vsc7512, vsc7513, vsc7514, vsc9959). + say y or m if you want to enable npi tagging for the ocelot switches + (vsc7511, vsc7512, vsc7513, vsc7514, vsc9953, vsc9959). in this mode, + the frames over the ethernet cpu port are prepended with a + hardware-defined injection/extraction frame header. flow control + (pause frames) over the cpu port is not supported when operating in + this mode. + +config net_dsa_tag_ocelot_8021q + tristate "tag driver for ocelot family of switches, using vlan" + select net_dsa_tag_8021q + help + say y or m if you want to enable support for tagging frames with a + custom vlan-based header. frames that require timestamping, such as + ptp, are not delivered over ethernet but over register-based mmio. + flow control over the cpu port is functional in this mode. when using + this mode, less tcam resources (vcap is1, is2, es0) are available for + use with tc-flower. diff --git a/net/dsa/makefile b/net/dsa/makefile --- a/net/dsa/makefile +++ b/net/dsa/makefile +obj-$(config_net_dsa_tag_ocelot_8021q) += tag_ocelot_8021q.o diff --git a/net/dsa/tag_ocelot_8021q.c b/net/dsa/tag_ocelot_8021q.c --- /dev/null +++ b/net/dsa/tag_ocelot_8021q.c +// spdx-license-identifier: gpl-2.0 +/* copyright 2020-2021 nxp semiconductors + * + * an implementation of the software-defined tag_8021q.c tagger format, which + * also preserves full functionality under a vlan_filtering bridge. it does + * this by using the tcam engines for: + * - pushing the rx vlan as a second, outer tag, on egress towards the cpu port + * - redirecting towards the correct front port based on tx vlan and popping + * that on egress + */ +#include <linux/dsa/8021q.h> +#include "dsa_priv.h" + +static struct sk_buff *ocelot_xmit(struct sk_buff *skb, + struct net_device *netdev) +{ + struct dsa_port *dp = dsa_slave_to_port(netdev); + u16 tx_vid = dsa_8021q_tx_vid(dp->ds, dp->index); + u16 queue_mapping = skb_get_queue_mapping(skb); + u8 pcp = netdev_txq_to_tc(netdev, queue_mapping); + + return dsa_8021q_xmit(skb, netdev, eth_p_8021q, + ((pcp << vlan_prio_shift) | tx_vid)); +} + +static struct sk_buff *ocelot_rcv(struct sk_buff *skb, + struct net_device *netdev, + struct packet_type *pt) +{ + int src_port, switch_id, qos_class; + u16 vid, tci; + + skb_push_rcsum(skb, eth_hlen); + if (skb_vlan_tag_present(skb)) { + tci = skb_vlan_tag_get(skb); + __vlan_hwaccel_clear_tag(skb); + } else { + __skb_vlan_pop(skb, &tci); + } + skb_pull_rcsum(skb, eth_hlen); + + vid = tci & vlan_vid_mask; + src_port = dsa_8021q_rx_source_port(vid); + switch_id = dsa_8021q_rx_switch_id(vid); + qos_class = (tci & vlan_prio_mask) >> vlan_prio_shift; + + skb->dev = dsa_master_find_slave(netdev, switch_id, src_port); + if (!skb->dev) + return null; + + skb->offload_fwd_mark = 1; + skb->priority = qos_class; + + return skb; +} + +static const struct dsa_device_ops ocelot_8021q_netdev_ops = { + .name = "ocelot-8021q", + .proto = dsa_tag_proto_ocelot_8021q, + .xmit = ocelot_xmit, + .rcv = ocelot_rcv, + .overhead = vlan_hlen, +}; + +module_license("gpl v2"); +module_alias_dsa_tag_driver(dsa_tag_proto_ocelot_8021q); + +module_dsa_tag_driver(ocelot_8021q_netdev_ops);
|
Networking
|
7c83a7c539abe9f980996063ac20532a7a7f6eb1
|
vladimir oltean
|
drivers
|
net
|
dsa, ocelot
|
net: dsa: felix: perform switch setup for tag_8021q
|
unlike sja1105, the only other user of the software-defined tag_8021q.c tagger format, the implementation we choose for the felix dsa switch driver preserves full functionality under a vlan_filtering bridge (i.e. ip termination works through the dsa user ports under all circumstances).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
tag_8021q for ocelot switches
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ']
|
['h', 'c']
| 7
| 396
| 12
|
- identifying the ingress switch port based on the rx vlan id, as seen - steering traffic injected into the switch from the network stack --- diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c +#include <linux/dsa/8021q.h> +static int felix_tag_8021q_rxvlan_add(struct felix *felix, int port, u16 vid, + bool pvid, bool untagged) +{ + struct ocelot_vcap_filter *outer_tagging_rule; + struct ocelot *ocelot = &felix->ocelot; + struct dsa_switch *ds = felix->ds; + int key_length, upstream, err; + + /* we don't need to install the rxvlan into the other ports' filtering + * tables, because we're just pushing the rxvlan when sending towards + * the cpu + */ + if (!pvid) + return 0; + + key_length = ocelot->vcap[vcap_es0].keys[vcap_es0_igr_port].length; + upstream = dsa_upstream_port(ds, port); + + outer_tagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), + gfp_kernel); + if (!outer_tagging_rule) + return -enomem; + + outer_tagging_rule->key_type = ocelot_vcap_key_any; + outer_tagging_rule->prio = 1; + outer_tagging_rule->id.cookie = port; + outer_tagging_rule->id.tc_offload = false; + outer_tagging_rule->block_id = vcap_es0; + outer_tagging_rule->type = ocelot_vcap_filter_offload; + outer_tagging_rule->lookup = 0; + outer_tagging_rule->ingress_port.value = port; + outer_tagging_rule->ingress_port.mask = genmask(key_length - 1, 0); + outer_tagging_rule->egress_port.value = upstream; + outer_tagging_rule->egress_port.mask = genmask(key_length - 1, 0); + outer_tagging_rule->action.push_outer_tag = ocelot_es0_tag; + outer_tagging_rule->action.tag_a_tpid_sel = ocelot_tag_tpid_sel_8021ad; + outer_tagging_rule->action.tag_a_vid_sel = 1; + outer_tagging_rule->action.vid_a_val = vid; + + err = ocelot_vcap_filter_add(ocelot, outer_tagging_rule, null); + if (err) + kfree(outer_tagging_rule); + + return err; +} + +static int felix_tag_8021q_txvlan_add(struct felix *felix, int port, u16 vid, + bool pvid, bool untagged) +{ + struct ocelot_vcap_filter *untagging_rule, *redirect_rule; + struct ocelot *ocelot = &felix->ocelot; + struct dsa_switch *ds = felix->ds; + int upstream, err; + + /* tag_8021q.c assumes we are implementing this via port vlan + * membership, which we aren't. so we don't need to add any vcap filter + * for the cpu port. + */ + if (ocelot->ports[port]->is_dsa_8021q_cpu) + return 0; + + untagging_rule = kzalloc(sizeof(struct ocelot_vcap_filter), gfp_kernel); + if (!untagging_rule) + return -enomem; + + redirect_rule = kzalloc(sizeof(struct ocelot_vcap_filter), gfp_kernel); + if (!redirect_rule) { + kfree(untagging_rule); + return -enomem; + } + + upstream = dsa_upstream_port(ds, port); + + untagging_rule->key_type = ocelot_vcap_key_any; + untagging_rule->ingress_port_mask = bit(upstream); + untagging_rule->vlan.vid.value = vid; + untagging_rule->vlan.vid.mask = vlan_vid_mask; + untagging_rule->prio = 1; + untagging_rule->id.cookie = port; + untagging_rule->id.tc_offload = false; + untagging_rule->block_id = vcap_is1; + untagging_rule->type = ocelot_vcap_filter_offload; + untagging_rule->lookup = 0; + untagging_rule->action.vlan_pop_cnt_ena = true; + untagging_rule->action.vlan_pop_cnt = 1; + untagging_rule->action.pag_override_mask = 0xff; + untagging_rule->action.pag_val = port; + + err = ocelot_vcap_filter_add(ocelot, untagging_rule, null); + if (err) { + kfree(untagging_rule); + kfree(redirect_rule); + return err; + } + + redirect_rule->key_type = ocelot_vcap_key_any; + redirect_rule->ingress_port_mask = bit(upstream); + redirect_rule->pag = port; + redirect_rule->prio = 1; + redirect_rule->id.cookie = port; + redirect_rule->id.tc_offload = false; + redirect_rule->block_id = vcap_is2; + redirect_rule->type = ocelot_vcap_filter_offload; + redirect_rule->lookup = 0; + redirect_rule->action.mask_mode = ocelot_mask_mode_redirect; + redirect_rule->action.port_mask = bit(port); + + err = ocelot_vcap_filter_add(ocelot, redirect_rule, null); + if (err) { + ocelot_vcap_filter_del(ocelot, untagging_rule); + kfree(redirect_rule); + return err; + } + + return 0; +} + +static int felix_tag_8021q_vlan_add(struct dsa_switch *ds, int port, u16 vid, + u16 flags) +{ + bool untagged = flags & bridge_vlan_info_untagged; + bool pvid = flags & bridge_vlan_info_pvid; + struct ocelot *ocelot = ds->priv; + + if (vid_is_dsa_8021q_rxvlan(vid)) + return felix_tag_8021q_rxvlan_add(ocelot_to_felix(ocelot), + port, vid, pvid, untagged); + + if (vid_is_dsa_8021q_txvlan(vid)) + return felix_tag_8021q_txvlan_add(ocelot_to_felix(ocelot), + port, vid, pvid, untagged); + + return 0; +} + +static int felix_tag_8021q_rxvlan_del(struct felix *felix, int port, u16 vid) +{ + struct ocelot_vcap_filter *outer_tagging_rule; + struct ocelot_vcap_block *block_vcap_es0; + struct ocelot *ocelot = &felix->ocelot; + + block_vcap_es0 = &ocelot->block[vcap_es0]; + + outer_tagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_es0, + port, false); + /* in rxvlan_add, we had the "if (!pvid) return 0" logic to avoid + * installing outer tagging es0 rules where they weren't needed. + * but in rxvlan_del, the api doesn't give us the "flags" anymore, + * so that forces us to be slightly sloppy here, and just assume that + * if we didn't find an outer_tagging_rule it means that there was + * none in the first place, i.e. rxvlan_del is called on a non-pvid + * port. this is most probably true though. + */ + if (!outer_tagging_rule) + return 0; + + return ocelot_vcap_filter_del(ocelot, outer_tagging_rule); +} + +static int felix_tag_8021q_txvlan_del(struct felix *felix, int port, u16 vid) +{ + struct ocelot_vcap_filter *untagging_rule, *redirect_rule; + struct ocelot_vcap_block *block_vcap_is1; + struct ocelot_vcap_block *block_vcap_is2; + struct ocelot *ocelot = &felix->ocelot; + int err; + + if (ocelot->ports[port]->is_dsa_8021q_cpu) + return 0; + + block_vcap_is1 = &ocelot->block[vcap_is1]; + block_vcap_is2 = &ocelot->block[vcap_is2]; + + untagging_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is1, + port, false); + if (!untagging_rule) + return 0; + + err = ocelot_vcap_filter_del(ocelot, untagging_rule); + if (err) + return err; + + redirect_rule = ocelot_vcap_block_find_filter_by_id(block_vcap_is2, + port, false); + if (!redirect_rule) + return 0; + + return ocelot_vcap_filter_del(ocelot, redirect_rule); +} + +static int felix_tag_8021q_vlan_del(struct dsa_switch *ds, int port, u16 vid) +{ + struct ocelot *ocelot = ds->priv; + + if (vid_is_dsa_8021q_rxvlan(vid)) + return felix_tag_8021q_rxvlan_del(ocelot_to_felix(ocelot), + port, vid); + + if (vid_is_dsa_8021q_txvlan(vid)) + return felix_tag_8021q_txvlan_del(ocelot_to_felix(ocelot), + port, vid); + + return 0; +} + +static const struct dsa_8021q_ops felix_tag_8021q_ops = { + .vlan_add = felix_tag_8021q_vlan_add, + .vlan_del = felix_tag_8021q_vlan_del, +}; + +/* alternatively to using the npi functionality, that same hardware mac + * connected internally to the enetc or fman dsa master can be configured to + * use the software-defined tag_8021q frame format. as far as the hardware is + * concerned, it thinks it is a "dumb switch" - the queues of the cpu port + * module are now disconnected from it, but can still be accessed through + * register-based mmio. + */ +static void felix_8021q_cpu_port_init(struct ocelot *ocelot, int port) +{ + ocelot->ports[port]->is_dsa_8021q_cpu = true; + ocelot->npi = -1; + + /* overwrite pgid_cpu with the non-tagging port */ + ocelot_write_rix(ocelot, bit(port), ana_pgid_pgid, pgid_cpu); + + ocelot_apply_bridge_fwd_mask(ocelot); +} + +static void felix_8021q_cpu_port_deinit(struct ocelot *ocelot, int port) +{ + ocelot->ports[port]->is_dsa_8021q_cpu = false; + + /* restore pgid_cpu */ + ocelot_write_rix(ocelot, bit(ocelot->num_phys_ports), ana_pgid_pgid, + pgid_cpu); + + ocelot_apply_bridge_fwd_mask(ocelot); +} + +static int felix_setup_tag_8021q(struct dsa_switch *ds, int cpu) +{ + struct ocelot *ocelot = ds->priv; + struct felix *felix = ocelot_to_felix(ocelot); + unsigned long cpu_flood; + int port, err; + + felix_8021q_cpu_port_init(ocelot, cpu); + + for (port = 0; port < ds->num_ports; port++) { + if (dsa_is_unused_port(ds, port)) + continue; + + /* this overwrites ocelot_init(): + * do not forward bpdu frames to the cpu port module, + * for 2 reasons: + * - when these packets are injected from the tag_8021q + * cpu port, we want them to go out, not loop back + * into the system. + * - stp traffic ingressing on a user port should go to + * the tag_8021q cpu port, not to the hardware cpu + * port module. + */ + ocelot_write_gix(ocelot, + ana_port_cpu_fwd_bpdu_cfg_bpdu_redir_ena(0), + ana_port_cpu_fwd_bpdu_cfg, port); + } + + /* in tag_8021q mode, the cpu port module is unused. so we + * want to disable flooding of any kind to the cpu port module, + * since packets going there will end in a black hole. + */ + cpu_flood = ana_pgid_pgid_pgid(bit(ocelot->num_phys_ports)); + ocelot_rmw_rix(ocelot, 0, cpu_flood, ana_pgid_pgid, pgid_uc); + ocelot_rmw_rix(ocelot, 0, cpu_flood, ana_pgid_pgid, pgid_mc); + + felix->dsa_8021q_ctx = kzalloc(sizeof(*felix->dsa_8021q_ctx), + gfp_kernel); + if (!felix->dsa_8021q_ctx) + return -enomem; + + felix->dsa_8021q_ctx->ops = &felix_tag_8021q_ops; + felix->dsa_8021q_ctx->proto = htons(eth_p_8021ad); + felix->dsa_8021q_ctx->ds = ds; + + err = dsa_8021q_setup(felix->dsa_8021q_ctx, true); + if (err) + goto out_free_dsa_8021_ctx; + + return 0; + +out_free_dsa_8021_ctx: + kfree(felix->dsa_8021q_ctx); + return err; +} + +static void felix_teardown_tag_8021q(struct dsa_switch *ds, int cpu) +{ + struct ocelot *ocelot = ds->priv; + struct felix *felix = ocelot_to_felix(ocelot); + int err, port; + + err = dsa_8021q_setup(felix->dsa_8021q_ctx, false); + if (err) + dev_err(ds->dev, "dsa_8021q_setup returned %d", err); + + kfree(felix->dsa_8021q_ctx); + + for (port = 0; port < ds->num_ports; port++) { + if (dsa_is_unused_port(ds, port)) + continue; + + /* restore the logic from ocelot_init: + * do not forward bpdu frames to the front ports. + */ + ocelot_write_gix(ocelot, + ana_port_cpu_fwd_bpdu_cfg_bpdu_redir_ena(0xffff), + ana_port_cpu_fwd_bpdu_cfg, + port); + } + + felix_8021q_cpu_port_deinit(ocelot, cpu); +} + + case dsa_tag_proto_ocelot_8021q: + err = felix_setup_tag_8021q(ds, cpu); + break; + case dsa_tag_proto_ocelot_8021q: + felix_teardown_tag_8021q(ds, cpu); + break; +/* this always leaves the switch in a consistent state, because although the + * tag_8021q setup can fail, the npi setup can't. so either the change is made, + * or the restoration is guaranteed to work. + */ - if (proto != dsa_tag_proto_ocelot) + if (proto != dsa_tag_proto_ocelot && + proto != dsa_tag_proto_ocelot_8021q) diff --git a/drivers/net/dsa/ocelot/felix.h b/drivers/net/dsa/ocelot/felix.h --- a/drivers/net/dsa/ocelot/felix.h +++ b/drivers/net/dsa/ocelot/felix.h + struct dsa_8021q_context *dsa_8021q_ctx; diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c -static void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) +static u32 ocelot_get_dsa_8021q_cpu_mask(struct ocelot *ocelot) + u32 mask = 0; + for (port = 0; port < ocelot->num_phys_ports; port++) { + struct ocelot_port *ocelot_port = ocelot->ports[port]; + + if (!ocelot_port) + continue; + + if (ocelot_port->is_dsa_8021q_cpu) + mask |= bit(port); + } + + return mask; +} + +void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot) +{ + unsigned long cpu_fwd_mask; + int port; + + /* if a dsa tag_8021q cpu exists, it needs to be included in the + * regular forwarding path of the front ports regardless of whether + * those are bridged or standalone. + * if dsa tag_8021q is not used, this returns 0, which is fine because + * the hardware-based cpu port module can be a destination for packets + * even if it isn't part of pgid_src. + */ + cpu_fwd_mask = ocelot_get_dsa_8021q_cpu_mask(ocelot); + - if (ocelot->bridge_fwd_mask & bit(port)) { - unsigned long mask = ocelot->bridge_fwd_mask & ~bit(port); + struct ocelot_port *ocelot_port = ocelot->ports[port]; + unsigned long mask; + + if (!ocelot_port) { + /* unused ports can't send anywhere */ + mask = 0; + } else if (ocelot_port->is_dsa_8021q_cpu) { + /* the dsa tag_8021q cpu ports need to be able to + * forward packets to all other ports except for + * themselves + */ + mask = genmask(ocelot->num_phys_ports - 1, 0); + mask &= ~cpu_fwd_mask; + } else if (ocelot->bridge_fwd_mask & bit(port)) { + mask = ocelot->bridge_fwd_mask & ~bit(port); + - - ocelot_write_rix(ocelot, mask, - ana_pgid_pgid, pgid_src + port); - ocelot_write_rix(ocelot, 0, - ana_pgid_pgid, pgid_src + port); + /* standalone ports forward only to dsa tag_8021q cpu + * ports (if those exist), or to the hardware cpu port + * module otherwise. + */ + mask = cpu_fwd_mask; + + ocelot_write_rix(ocelot, mask, ana_pgid_pgid, pgid_src + port); +export_symbol(ocelot_apply_bridge_fwd_mask); diff --git a/drivers/net/ethernet/mscc/ocelot_vcap.c b/drivers/net/ethernet/mscc/ocelot_vcap.c --- a/drivers/net/ethernet/mscc/ocelot_vcap.c +++ b/drivers/net/ethernet/mscc/ocelot_vcap.c +export_symbol(ocelot_vcap_block_find_filter_by_id); diff --git a/drivers/net/ethernet/mscc/ocelot_vcap.h b/drivers/net/ethernet/mscc/ocelot_vcap.h --- a/drivers/net/ethernet/mscc/ocelot_vcap.h +++ b/drivers/net/ethernet/mscc/ocelot_vcap.h -struct ocelot_vcap_filter * -ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block, int id, - bool tc_offload); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h + bool is_dsa_8021q_cpu; +void ocelot_apply_bridge_fwd_mask(struct ocelot *ocelot); diff --git a/include/soc/mscc/ocelot_vcap.h b/include/soc/mscc/ocelot_vcap.h --- a/include/soc/mscc/ocelot_vcap.h +++ b/include/soc/mscc/ocelot_vcap.h +struct ocelot_vcap_filter * +ocelot_vcap_block_find_filter_by_id(struct ocelot_vcap_block *block, int id, + bool tc_offload);
|
Networking
|
e21268efbe26d9ab3f7468577d691b992d76e06a
|
vladimir oltean
|
include
|
soc
|
dsa, ethernet, mscc, ocelot
|
net: dsa: felix: add support for mrp
|
implement functions 'port_mrp_add', 'port_mrp_del', 'port_mrp_add_ring_role' and 'port_mrp_del_ring_role' to call the mrp functions from ocelot.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for mrp
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'felix']
|
['c']
| 2
| 46
| 0
|
--- diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c +static int felix_mrp_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_mrp *mrp) +{ + struct ocelot *ocelot = ds->priv; + + return ocelot_mrp_add(ocelot, port, mrp); +} + +static int felix_mrp_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_mrp *mrp) +{ + struct ocelot *ocelot = ds->priv; + + return ocelot_mrp_add(ocelot, port, mrp); +} + +static int +felix_mrp_add_ring_role(struct dsa_switch *ds, int port, + const struct switchdev_obj_ring_role_mrp *mrp) +{ + struct ocelot *ocelot = ds->priv; + + return ocelot_mrp_add_ring_role(ocelot, port, mrp); +} + +static int +felix_mrp_del_ring_role(struct dsa_switch *ds, int port, + const struct switchdev_obj_ring_role_mrp *mrp) +{ + struct ocelot *ocelot = ds->priv; + + return ocelot_mrp_del_ring_role(ocelot, port, mrp); +} + + .port_mrp_add = felix_mrp_add, + .port_mrp_del = felix_mrp_del, + .port_mrp_add_ring_role = felix_mrp_add_ring_role, + .port_mrp_del_ring_role = felix_mrp_del_ring_role, diff --git a/net/dsa/tag_ocelot.c b/net/dsa/tag_ocelot.c --- a/net/dsa/tag_ocelot.c +++ b/net/dsa/tag_ocelot.c + u64 cpuq; + ocelot_xfh_get_cpuq(extraction, &cpuq); +#if is_enabled(config_bridge_mrp) + if (eth_hdr(skb)->h_proto == cpu_to_be16(eth_p_mrp) && + cpuq & bit(ocelot_mrp_cpuq)) + skb->offload_fwd_mark = 0; +#endif +
|
Networking
|
a026c50b599fab8ad829f87af372866e229d8175
|
horatiu vultur
|
drivers
|
net
|
dsa, ocelot
|
net: dsa: hellcreek: add taprio offloading support
|
the switch has support for the 802.1qbv time aware shaper (tas). traffic schedules may be configured individually on each front port. each port has eight egress queues. the traffic is mapped to a traffic class respectively via the pcp field of a vlan tagged frame.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add taprio offloading support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'hellcreek']
|
['h', 'c']
| 2
| 318
| 2
|
--- diff --git a/drivers/net/dsa/hirschmann/hellcreek.c b/drivers/net/dsa/hirschmann/hellcreek.c --- a/drivers/net/dsa/hirschmann/hellcreek.c +++ b/drivers/net/dsa/hirschmann/hellcreek.c - * copyright (c) 2019,2020 linutronix gmbh + * copyright (c) 2019-2021 linutronix gmbh +static void hellcreek_select_tgd(struct hellcreek *hellcreek, int port) +{ + u16 val = port << tr_tgdsel_tdgsel_shift; + + hellcreek_write(hellcreek, val, tr_tgdsel); +} + +static void hellcreek_setup_gcl(struct hellcreek *hellcreek, int port, + const struct tc_taprio_qopt_offload *schedule) +{ + const struct tc_taprio_sched_entry *cur, *initial, *next; + size_t i; + + cur = initial = &schedule->entries[0]; + next = cur + 1; + + for (i = 1; i <= schedule->num_entries; ++i) { + u16 data; + u8 gates; + + cur++; + next++; + + if (i == schedule->num_entries) + gates = initial->gate_mask ^ + cur->gate_mask; + else + gates = next->gate_mask ^ + cur->gate_mask; + + data = gates; + + if (i == schedule->num_entries) + data |= tr_gcldat_gclwrlast; + + /* gates states */ + hellcreek_write(hellcreek, data, tr_gcldat); + + /* time interval */ + hellcreek_write(hellcreek, + cur->interval & 0x0000ffff, + tr_gcltil); + hellcreek_write(hellcreek, + (cur->interval & 0xffff0000) >> 16, + tr_gcltih); + + /* commit entry */ + data = ((i - 1) << tr_gclcmd_gclwradr_shift) | + (initial->gate_mask << + tr_gclcmd_init_gate_states_shift); + hellcreek_write(hellcreek, data, tr_gclcmd); + } +} + +static void hellcreek_set_cycle_time(struct hellcreek *hellcreek, + const struct tc_taprio_qopt_offload *schedule) +{ + u32 cycle_time = schedule->cycle_time; + + hellcreek_write(hellcreek, cycle_time & 0x0000ffff, tr_ctwrl); + hellcreek_write(hellcreek, (cycle_time & 0xffff0000) >> 16, tr_ctwrh); +} + +static void hellcreek_switch_schedule(struct hellcreek *hellcreek, + ktime_t start_time) +{ + struct timespec64 ts = ktime_to_timespec64(start_time); + + /* start schedule at this point of time */ + hellcreek_write(hellcreek, ts.tv_nsec & 0x0000ffff, tr_estwrl); + hellcreek_write(hellcreek, (ts.tv_nsec & 0xffff0000) >> 16, tr_estwrh); + + /* arm timer, set seconds and switch schedule */ + hellcreek_write(hellcreek, tr_estcmd_estarm | tr_estcmd_estswcfg | + ((ts.tv_sec & tr_estcmd_estsec_mask) << + tr_estcmd_estsec_shift), tr_estcmd); +} + +static bool hellcreek_schedule_startable(struct hellcreek *hellcreek, int port) +{ + struct hellcreek_port *hellcreek_port = &hellcreek->ports[port]; + s64 base_time_ns, current_ns; + + /* the switch allows a schedule to be started only eight seconds within + * the future. therefore, check the current ptp time if the schedule is + * startable or not. + */ + + /* use the "cached" time. that should be alright, as it's updated quite + * frequently in the ptp code. + */ + mutex_lock(&hellcreek->ptp_lock); + current_ns = hellcreek->seconds * nsec_per_sec + hellcreek->last_ts; + mutex_unlock(&hellcreek->ptp_lock); + + /* calculate difference to admin base time */ + base_time_ns = ktime_to_ns(hellcreek_port->current_schedule->base_time); + + return base_time_ns - current_ns < (s64)8 * nsec_per_sec; +} + +static void hellcreek_start_schedule(struct hellcreek *hellcreek, int port) +{ + struct hellcreek_port *hellcreek_port = &hellcreek->ports[port]; + ktime_t base_time, current_time; + s64 current_ns; + u32 cycle_time; + + /* first select port */ + hellcreek_select_tgd(hellcreek, port); + + /* forward base time into the future if needed */ + mutex_lock(&hellcreek->ptp_lock); + current_ns = hellcreek->seconds * nsec_per_sec + hellcreek->last_ts; + mutex_unlock(&hellcreek->ptp_lock); + + current_time = ns_to_ktime(current_ns); + base_time = hellcreek_port->current_schedule->base_time; + cycle_time = hellcreek_port->current_schedule->cycle_time; + + if (ktime_compare(current_time, base_time) > 0) { + s64 n; + + n = div64_s64(ktime_sub_ns(current_time, base_time), + cycle_time); + base_time = ktime_add_ns(base_time, (n + 1) * cycle_time); + } + + /* set admin base time and switch schedule */ + hellcreek_switch_schedule(hellcreek, base_time); + + taprio_offload_free(hellcreek_port->current_schedule); + hellcreek_port->current_schedule = null; + + dev_dbg(hellcreek->dev, "armed est timer for port %d ", + hellcreek_port->port); +} + +static void hellcreek_check_schedule(struct work_struct *work) +{ + struct delayed_work *dw = to_delayed_work(work); + struct hellcreek_port *hellcreek_port; + struct hellcreek *hellcreek; + bool startable; + + hellcreek_port = dw_to_hellcreek_port(dw); + hellcreek = hellcreek_port->hellcreek; + + mutex_lock(&hellcreek->reg_lock); + + /* check starting time */ + startable = hellcreek_schedule_startable(hellcreek, + hellcreek_port->port); + if (startable) { + hellcreek_start_schedule(hellcreek, hellcreek_port->port); + mutex_unlock(&hellcreek->reg_lock); + return; + } + + mutex_unlock(&hellcreek->reg_lock); + + /* reschedule */ + schedule_delayed_work(&hellcreek_port->schedule_work, + hellcreek_schedule_period); +} + +static int hellcreek_port_set_schedule(struct dsa_switch *ds, int port, + struct tc_taprio_qopt_offload *taprio) +{ + struct hellcreek *hellcreek = ds->priv; + struct hellcreek_port *hellcreek_port; + bool startable; + u16 ctrl; + + hellcreek_port = &hellcreek->ports[port]; + + dev_dbg(hellcreek->dev, "configure traffic schedule on port %d ", + port); + + /* first cancel delayed work */ + cancel_delayed_work_sync(&hellcreek_port->schedule_work); + + mutex_lock(&hellcreek->reg_lock); + + if (hellcreek_port->current_schedule) { + taprio_offload_free(hellcreek_port->current_schedule); + hellcreek_port->current_schedule = null; + } + hellcreek_port->current_schedule = taprio_offload_get(taprio); + + /* then select port */ + hellcreek_select_tgd(hellcreek, port); + + /* enable gating and keep defaults */ + ctrl = (0xff << tr_tgdctrl_admingatestates_shift) | tr_tgdctrl_gate_en; + hellcreek_write(hellcreek, ctrl, tr_tgdctrl); + + /* cancel pending schedule */ + hellcreek_write(hellcreek, 0x00, tr_estcmd); + + /* setup a new schedule */ + hellcreek_setup_gcl(hellcreek, port, hellcreek_port->current_schedule); + + /* configure cycle time */ + hellcreek_set_cycle_time(hellcreek, hellcreek_port->current_schedule); + + /* check starting time */ + startable = hellcreek_schedule_startable(hellcreek, port); + if (startable) { + hellcreek_start_schedule(hellcreek, port); + mutex_unlock(&hellcreek->reg_lock); + return 0; + } + + mutex_unlock(&hellcreek->reg_lock); + + /* schedule periodic schedule check */ + schedule_delayed_work(&hellcreek_port->schedule_work, + hellcreek_schedule_period); + + return 0; +} + +static int hellcreek_port_del_schedule(struct dsa_switch *ds, int port) +{ + struct hellcreek *hellcreek = ds->priv; + struct hellcreek_port *hellcreek_port; + + hellcreek_port = &hellcreek->ports[port]; + + dev_dbg(hellcreek->dev, "remove traffic schedule on port %d ", port); + + /* first cancel delayed work */ + cancel_delayed_work_sync(&hellcreek_port->schedule_work); + + mutex_lock(&hellcreek->reg_lock); + + if (hellcreek_port->current_schedule) { + taprio_offload_free(hellcreek_port->current_schedule); + hellcreek_port->current_schedule = null; + } + + /* then select port */ + hellcreek_select_tgd(hellcreek, port); + + /* disable gating and return to regular switching flow */ + hellcreek_write(hellcreek, 0xff << tr_tgdctrl_admingatestates_shift, + tr_tgdctrl); + + mutex_unlock(&hellcreek->reg_lock); + + return 0; +} + +static bool hellcreek_validate_schedule(struct hellcreek *hellcreek, + struct tc_taprio_qopt_offload *schedule) +{ + size_t i; + + /* does this hellcreek version support qbv in hardware? */ + if (!hellcreek->pdata->qbv_support) + return false; + + /* cycle time can only be 32bit */ + if (schedule->cycle_time > (u32)-1) + return false; + + /* cycle time extension is not supported */ + if (schedule->cycle_time_extension) + return false; + + /* only set command is supported */ + for (i = 0; i < schedule->num_entries; ++i) + if (schedule->entries[i].command != tc_taprio_cmd_set_gates) + return false; + + return true; +} + +static int hellcreek_port_setup_tc(struct dsa_switch *ds, int port, + enum tc_setup_type type, void *type_data) +{ + struct tc_taprio_qopt_offload *taprio = type_data; + struct hellcreek *hellcreek = ds->priv; + + if (type != tc_setup_qdisc_taprio) + return -eopnotsupp; + + if (!hellcreek_validate_schedule(hellcreek, taprio)) + return -eopnotsupp; + + if (taprio->enable) + return hellcreek_port_set_schedule(ds, port, taprio); + + return hellcreek_port_del_schedule(ds, port); +} + + .port_setup_tc = hellcreek_port_setup_tc, + + init_delayed_work(&port->schedule_work, + hellcreek_check_schedule); diff --git a/drivers/net/dsa/hirschmann/hellcreek.h b/drivers/net/dsa/hirschmann/hellcreek.h --- a/drivers/net/dsa/hirschmann/hellcreek.h +++ b/drivers/net/dsa/hirschmann/hellcreek.h - * copyright (c) 2019,2020 linutronix gmbh + * copyright (c) 2019-2021 linutronix gmbh +#include <net/pkt_sched.h> + + /* per-port qbv schedule information */ + struct tc_taprio_qopt_offload *current_schedule; + struct delayed_work schedule_work; +/* a qbv schedule can only started up to 8 seconds in the future. if the delta + * between the base time and the current ptp time is larger than 8 seconds, then + * use periodic work to check for the schedule to be started. the delayed work + * cannot be armed directly to $base_time - 8 + x, because for large deltas the + * ptp frequency matters. + */ +#define hellcreek_schedule_period (2 * hz) +#define dw_to_hellcreek_port(dw) \ + container_of(dw, struct hellcreek_port, schedule_work) +
|
Networking
|
24dfc6eb39b26fc3a5a17a606e868b74f6202ee4
|
kurt kanzenbach
|
drivers
|
net
|
dsa, hirschmann
|
net: dsa: mt7530: mt7530 optional gpio support
|
mt7530's led controller can drive up to 15 led/gpios.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mt7530 optional gpio support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'mt7530']
|
['h', 'c']
| 2
| 130
| 0
|
--- diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c +#include <linux/gpio/driver.h> +static inline u32 +mt7530_gpio_to_bit(unsigned int offset) +{ + /* map gpio offset to register bit + * [ 2: 0] port 0 led 0..2 as gpio 0..2 + * [ 6: 4] port 1 led 0..2 as gpio 3..5 + * [10: 8] port 2 led 0..2 as gpio 6..8 + * [14:12] port 3 led 0..2 as gpio 9..11 + * [18:16] port 4 led 0..2 as gpio 12..14 + */ + return bit(offset + offset / 3); +} + +static int +mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) +{ + struct mt7530_priv *priv = gpiochip_get_data(gc); + u32 bit = mt7530_gpio_to_bit(offset); + + return !!(mt7530_read(priv, mt7530_led_gpio_data) & bit); +} + +static void +mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct mt7530_priv *priv = gpiochip_get_data(gc); + u32 bit = mt7530_gpio_to_bit(offset); + + if (value) + mt7530_set(priv, mt7530_led_gpio_data, bit); + else + mt7530_clear(priv, mt7530_led_gpio_data, bit); +} + +static int +mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) +{ + struct mt7530_priv *priv = gpiochip_get_data(gc); + u32 bit = mt7530_gpio_to_bit(offset); + + return (mt7530_read(priv, mt7530_led_gpio_dir) & bit) ? + gpio_line_direction_out : gpio_line_direction_in; +} + +static int +mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) +{ + struct mt7530_priv *priv = gpiochip_get_data(gc); + u32 bit = mt7530_gpio_to_bit(offset); + + mt7530_clear(priv, mt7530_led_gpio_oe, bit); + mt7530_clear(priv, mt7530_led_gpio_dir, bit); + + return 0; +} + +static int +mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) +{ + struct mt7530_priv *priv = gpiochip_get_data(gc); + u32 bit = mt7530_gpio_to_bit(offset); + + mt7530_set(priv, mt7530_led_gpio_dir, bit); + + if (value) + mt7530_set(priv, mt7530_led_gpio_data, bit); + else + mt7530_clear(priv, mt7530_led_gpio_data, bit); + + mt7530_set(priv, mt7530_led_gpio_oe, bit); + + return 0; +} + +static int +mt7530_setup_gpio(struct mt7530_priv *priv) +{ + struct device *dev = priv->dev; + struct gpio_chip *gc; + + gc = devm_kzalloc(dev, sizeof(*gc), gfp_kernel); + if (!gc) + return -enomem; + + mt7530_write(priv, mt7530_led_gpio_oe, 0); + mt7530_write(priv, mt7530_led_gpio_dir, 0); + mt7530_write(priv, mt7530_led_io_mode, 0); + + gc->label = "mt7530"; + gc->parent = dev; + gc->owner = this_module; + gc->get_direction = mt7530_gpio_get_direction; + gc->direction_input = mt7530_gpio_direction_input; + gc->direction_output = mt7530_gpio_direction_output; + gc->get = mt7530_gpio_get; + gc->set = mt7530_gpio_set; + gc->base = -1; + gc->ngpio = 15; + gc->can_sleep = true; + + return devm_gpiochip_add_data(dev, gc, priv); +} + + if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { + ret = mt7530_setup_gpio(priv); + if (ret) + return ret; + } + diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h +/* registers for led gpio control (mt7530 only) + * all registers follow this pattern: + * [ 2: 0] port 0 + * [ 6: 4] port 1 + * [10: 8] port 2 + * [14:12] port 3 + * [18:16] port 4 + */ + +/* led enable, 0: disable, 1: enable (default) */ +#define mt7530_led_en 0x7d00 +/* led mode, 0: gpio mode, 1: phy mode (default) */ +#define mt7530_led_io_mode 0x7d04 +/* gpio direction, 0: input, 1: output */ +#define mt7530_led_gpio_dir 0x7d10 +/* gpio output enable, 0: disable, 1: enable */ +#define mt7530_led_gpio_oe 0x7d14 +/* gpio value, 0: low, 1: high */ +#define mt7530_led_gpio_data 0x7d18 +
|
Networking
|
429a0edeefd88cbfca5c417dfb8561047bb50769
|
deng qingfang
|
drivers
|
net
|
dsa
|
net: dsa: mv88e6xxx: link aggregation support
|
support offloading of lags to hardware. lags may be attached to a bridge in which case vlans, multicast groups, etc. are also offloaded as usual.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
link aggregation support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'mv88e6xxx']
|
['h', 'c']
| 5
| 330
| 5
|
--- diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c + struct dsa_switch_tree *dst = chip->ds->dst; + struct dsa_switch *ds; + struct dsa_port *dp; - if (dev != chip->ds->index) + if (dev != chip->ds->index) { + ds = dsa_switch_find(dst->index, dev); + dp = ds ? dsa_to_port(ds, port) : null; + if (dp && dp->lag_dev) { + /* as the pvt is used to limit flooding of + * forward frames, which use the lag id as the + * source port, we must translate dev/port to + * the special "lag device" in the pvt, using + * the lag id as the port number. + */ + dev = mv88e6xxx_g2_pvt_adrr_dev_trunk; + port = dsa_lag_id(dst, dp->lag_dev); + } + } + +static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, + struct net_device *lag, + struct netdev_lag_upper_info *info) +{ + struct dsa_port *dp; + int id, members = 0; + + id = dsa_lag_id(ds->dst, lag); + if (id < 0 || id >= ds->num_lag_ids) + return false; + + dsa_lag_foreach_port(dp, ds->dst, lag) + /* includes the port joining the lag */ + members++; + + if (members > 8) + return false; + + /* we could potentially relax this to include active + * backup in the future. + */ + if (info->tx_type != netdev_lag_tx_type_hash) + return false; + + /* ideally we would also validate that the hash type matches + * the hardware. alas, this is always set to unknown on team + * interfaces. + */ + return true; +} + +static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) +{ + struct mv88e6xxx_chip *chip = ds->priv; + struct dsa_port *dp; + u16 map = 0; + int id; + + id = dsa_lag_id(ds->dst, lag); + + /* build the map of all ports to distribute flows destined for + * this lag. this can be either a local user port, or a dsa + * port if the lag port is on a remote chip. + */ + dsa_lag_foreach_port(dp, ds->dst, lag) + map |= bit(dsa_towards_port(ds, dp->ds->index, dp->index)); + + return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); +} + +static const u8 mv88e6xxx_lag_mask_table[8][8] = { + /* row number corresponds to the number of active members in a + * lag. each column states which of the eight hash buckets are + * mapped to the column:th port in the lag. + * + * example: in a lag with three active ports, the second port + * ([2][1]) would be selected for traffic mapped to buckets + * 3,4,5 (0x38). + */ + { 0xff, 0, 0, 0, 0, 0, 0, 0 }, + { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, + { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, + { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, + { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, + { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, + { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, + { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, +}; + +static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, + int num_tx, int nth) +{ + u8 active = 0; + int i; + + num_tx = num_tx <= 8 ? num_tx : 8; + if (nth < num_tx) + active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; + + for (i = 0; i < 8; i++) { + if (bit(i) & active) + mask[i] |= bit(port); + } +} + +static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) +{ + struct mv88e6xxx_chip *chip = ds->priv; + unsigned int id, num_tx; + struct net_device *lag; + struct dsa_port *dp; + int i, err, nth; + u16 mask[8]; + u16 ivec; + + /* assume no port is a member of any lag. */ + ivec = bit(mv88e6xxx_num_ports(chip)) - 1; + + /* disable all masks for ports that _are_ members of a lag. */ + list_for_each_entry(dp, &ds->dst->ports, list) { + if (!dp->lag_dev || dp->ds != ds) + continue; + + ivec &= ~bit(dp->index); + } + + for (i = 0; i < 8; i++) + mask[i] = ivec; + + /* enable the correct subset of masks for all lag ports that + * are in the tx set. + */ + dsa_lags_foreach_id(id, ds->dst) { + lag = dsa_lag_dev(ds->dst, id); + if (!lag) + continue; + + num_tx = 0; + dsa_lag_foreach_port(dp, ds->dst, lag) { + if (dp->lag_tx_enabled) + num_tx++; + } + + if (!num_tx) + continue; + + nth = 0; + dsa_lag_foreach_port(dp, ds->dst, lag) { + if (!dp->lag_tx_enabled) + continue; + + if (dp->ds == ds) + mv88e6xxx_lag_set_port_mask(mask, dp->index, + num_tx, nth); + + nth++; + } + } + + for (i = 0; i < 8; i++) { + err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); + if (err) + return err; + } + + return 0; +} + +static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, + struct net_device *lag) +{ + int err; + + err = mv88e6xxx_lag_sync_masks(ds); + + if (!err) + err = mv88e6xxx_lag_sync_map(ds, lag); + + return err; +} + +static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) +{ + struct mv88e6xxx_chip *chip = ds->priv; + int err; + + mv88e6xxx_reg_lock(chip); + err = mv88e6xxx_lag_sync_masks(ds); + mv88e6xxx_reg_unlock(chip); + return err; +} + +static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, + struct net_device *lag, + struct netdev_lag_upper_info *info) +{ + struct mv88e6xxx_chip *chip = ds->priv; + int err, id; + + if (!mv88e6xxx_lag_can_offload(ds, lag, info)) + return -eopnotsupp; + + id = dsa_lag_id(ds->dst, lag); + + mv88e6xxx_reg_lock(chip); + + err = mv88e6xxx_port_set_trunk(chip, port, true, id); + if (err) + goto err_unlock; + + err = mv88e6xxx_lag_sync_masks_map(ds, lag); + if (err) + goto err_clear_trunk; + + mv88e6xxx_reg_unlock(chip); + return 0; + +err_clear_trunk: + mv88e6xxx_port_set_trunk(chip, port, false, 0); +err_unlock: + mv88e6xxx_reg_unlock(chip); + return err; +} + +static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, + struct net_device *lag) +{ + struct mv88e6xxx_chip *chip = ds->priv; + int err_sync, err_trunk; + + mv88e6xxx_reg_lock(chip); + err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); + err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); + mv88e6xxx_reg_unlock(chip); + return err_sync ? : err_trunk; +} + +static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, + int port) +{ + struct mv88e6xxx_chip *chip = ds->priv; + int err; + + mv88e6xxx_reg_lock(chip); + err = mv88e6xxx_lag_sync_masks(ds); + mv88e6xxx_reg_unlock(chip); + return err; +} + +static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, + int port, struct net_device *lag, + struct netdev_lag_upper_info *info) +{ + struct mv88e6xxx_chip *chip = ds->priv; + int err; + + if (!mv88e6xxx_lag_can_offload(ds, lag, info)) + return -eopnotsupp; + + mv88e6xxx_reg_lock(chip); + + err = mv88e6xxx_lag_sync_masks_map(ds, lag); + if (err) + goto unlock; + + err = mv88e6xxx_pvt_map(chip, sw_index, port); + +unlock: + mv88e6xxx_reg_unlock(chip); + return err; +} + +static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, + int port, struct net_device *lag) +{ + struct mv88e6xxx_chip *chip = ds->priv; + int err_sync, err_pvt; + + mv88e6xxx_reg_lock(chip); + err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); + err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); + mv88e6xxx_reg_unlock(chip); + return err_sync ? : err_pvt; +} + + .port_lag_change = mv88e6xxx_port_lag_change, + .port_lag_join = mv88e6xxx_port_lag_join, + .port_lag_leave = mv88e6xxx_port_lag_leave, + .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, + .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, + .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, + /* some chips support up to 32, but that requires enabling the + * 5-bit port mode, which we do not support. 640k^w16 ought to + * be enough for anyone. + */ + ds->num_lag_ids = 16; + diff --git a/drivers/net/dsa/mv88e6xxx/global2.c b/drivers/net/dsa/mv88e6xxx/global2.c --- a/drivers/net/dsa/mv88e6xxx/global2.c +++ b/drivers/net/dsa/mv88e6xxx/global2.c -static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, - bool hash, u16 mask) +int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, + bool hash, u16 mask) -static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, - u16 map) +int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, + u16 map) diff --git a/drivers/net/dsa/mv88e6xxx/global2.h b/drivers/net/dsa/mv88e6xxx/global2.h --- a/drivers/net/dsa/mv88e6xxx/global2.h +++ b/drivers/net/dsa/mv88e6xxx/global2.h +#define mv88e6xxx_g2_pvt_adrr_dev_trunk 0x1f +int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num, + bool hash, u16 mask); +int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id, + u16 map); diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c +int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, + bool trunk, u8 id) +{ + u16 val; + int err; + + err = mv88e6xxx_port_read(chip, port, mv88e6xxx_port_ctl1, &val); + if (err) + return err; + + val &= ~mv88e6xxx_port_ctl1_trunk_id_mask; + + if (trunk) + val |= mv88e6xxx_port_ctl1_trunk_port | + (id << mv88e6xxx_port_ctl1_trunk_id_shift); + else + val &= ~mv88e6xxx_port_ctl1_trunk_port; + + return mv88e6xxx_port_write(chip, port, mv88e6xxx_port_ctl1, val); +} + diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h +#define mv88e6xxx_port_ctl1_trunk_port 0x4000 +#define mv88e6xxx_port_ctl1_trunk_id_mask 0x0f00 +#define mv88e6xxx_port_ctl1_trunk_id_shift 8 +int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, + bool trunk, u8 id);
|
Networking
|
57e661aae6a823140787dbcc34d92e223e2f71c5
|
tobias waldekranz vladimir oltean olteanv gmail com
|
drivers
|
net
|
dsa, mv88e6xxx
|
net: dsa: qca: ar9331: export stats64
|
add stats support for the ar9331 switch.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
export stats64
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'qca', 'ar9331']
|
['c']
| 1
| 162
| 1
|
--- diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c --- a/drivers/net/dsa/qca/ar9331.c +++ b/drivers/net/dsa/qca/ar9331.c +/* mib registers */ +#define ar9331_mib_counter(x) (0x20000 + ((x) * 0x100)) + +/* the interval should be small enough to avoid overflow of 32bit mibs */ +/* + * fixme: until we can read mibs from stats64 call directly (i.e. sleep + * there), we have to poll stats more frequently then it is actually needed. + * for overflow protection, normally, 100 sec interval should have been ok. + */ +#define stats_interval_jiffies (3 * hz) + +struct ar9331_sw_stats_raw { + u32 rxbroad; /* 0x00 */ + u32 rxpause; /* 0x04 */ + u32 rxmulti; /* 0x08 */ + u32 rxfcserr; /* 0x0c */ + u32 rxalignerr; /* 0x10 */ + u32 rxrunt; /* 0x14 */ + u32 rxfragment; /* 0x18 */ + u32 rx64byte; /* 0x1c */ + u32 rx128byte; /* 0x20 */ + u32 rx256byte; /* 0x24 */ + u32 rx512byte; /* 0x28 */ + u32 rx1024byte; /* 0x2c */ + u32 rx1518byte; /* 0x30 */ + u32 rxmaxbyte; /* 0x34 */ + u32 rxtoolong; /* 0x38 */ + u32 rxgoodbyte; /* 0x3c */ + u32 rxgoodbyte_hi; + u32 rxbadbyte; /* 0x44 */ + u32 rxbadbyte_hi; + u32 rxoverflow; /* 0x4c */ + u32 filtered; /* 0x50 */ + u32 txbroad; /* 0x54 */ + u32 txpause; /* 0x58 */ + u32 txmulti; /* 0x5c */ + u32 txunderrun; /* 0x60 */ + u32 tx64byte; /* 0x64 */ + u32 tx128byte; /* 0x68 */ + u32 tx256byte; /* 0x6c */ + u32 tx512byte; /* 0x70 */ + u32 tx1024byte; /* 0x74 */ + u32 tx1518byte; /* 0x78 */ + u32 txmaxbyte; /* 0x7c */ + u32 txoversize; /* 0x80 */ + u32 txbyte; /* 0x84 */ + u32 txbyte_hi; + u32 txcollision; /* 0x8c */ + u32 txabortcol; /* 0x90 */ + u32 txmulticol; /* 0x94 */ + u32 txsinglecol; /* 0x98 */ + u32 txexcdefer; /* 0x9c */ + u32 txdefer; /* 0xa0 */ + u32 txlatecol; /* 0xa4 */ +}; + +struct ar9331_sw_port { + int idx; + struct delayed_work mib_read; + struct rtnl_link_stats64 stats; + struct spinlock stats_lock; +}; + + struct ar9331_sw_port port[ar9331_sw_ports]; +static struct ar9331_sw_priv *ar9331_sw_port_to_priv(struct ar9331_sw_port *port) +{ + struct ar9331_sw_port *p = port - port->idx; + + return (struct ar9331_sw_priv *)((void *)p - + offsetof(struct ar9331_sw_priv, port)); +} + + struct ar9331_sw_port *p = &priv->port[port]; + + cancel_delayed_work_sync(&p->mib_read); + struct ar9331_sw_port *p = &priv->port[port]; + schedule_delayed_work(&p->mib_read, 0); + +static void ar9331_read_stats(struct ar9331_sw_port *port) +{ + struct ar9331_sw_priv *priv = ar9331_sw_port_to_priv(port); + struct rtnl_link_stats64 *stats = &port->stats; + struct ar9331_sw_stats_raw raw; + int ret; + + /* do the slowest part first, to avoid needless locking for long time */ + ret = regmap_bulk_read(priv->regmap, ar9331_mib_counter(port->idx), + &raw, sizeof(raw) / sizeof(u32)); + if (ret) { + dev_err_ratelimited(priv->dev, "%s: %i ", __func__, ret); + return; + } + /* all mib counters are cleared automatically on read */ + + spin_lock(&port->stats_lock); + + stats->rx_bytes += raw.rxgoodbyte; + stats->tx_bytes += raw.txbyte; + + stats->rx_packets += raw.rx64byte + raw.rx128byte + raw.rx256byte + + raw.rx512byte + raw.rx1024byte + raw.rx1518byte + raw.rxmaxbyte; + stats->tx_packets += raw.tx64byte + raw.tx128byte + raw.tx256byte + + raw.tx512byte + raw.tx1024byte + raw.tx1518byte + raw.txmaxbyte; + + stats->rx_length_errors += raw.rxrunt + raw.rxfragment + raw.rxtoolong; + stats->rx_crc_errors += raw.rxfcserr; + stats->rx_frame_errors += raw.rxalignerr; + stats->rx_missed_errors += raw.rxoverflow; + stats->rx_dropped += raw.filtered; + stats->rx_errors += raw.rxfcserr + raw.rxalignerr + raw.rxrunt + + raw.rxfragment + raw.rxoverflow + raw.rxtoolong; + + stats->tx_window_errors += raw.txlatecol; + stats->tx_fifo_errors += raw.txunderrun; + stats->tx_aborted_errors += raw.txabortcol; + stats->tx_errors += raw.txoversize + raw.txabortcol + raw.txunderrun + + raw.txlatecol; + + stats->multicast += raw.rxmulti; + stats->collisions += raw.txcollision; + + spin_unlock(&port->stats_lock); +} + +static void ar9331_do_stats_poll(struct work_struct *work) +{ + struct ar9331_sw_port *port = container_of(work, struct ar9331_sw_port, + mib_read.work); + + ar9331_read_stats(port); + + schedule_delayed_work(&port->mib_read, stats_interval_jiffies); +} + +static void ar9331_get_stats64(struct dsa_switch *ds, int port, + struct rtnl_link_stats64 *s) +{ + struct ar9331_sw_priv *priv = (struct ar9331_sw_priv *)ds->priv; + struct ar9331_sw_port *p = &priv->port[port]; + + spin_lock(&p->stats_lock); + memcpy(s, &p->stats, sizeof(*s)); + spin_unlock(&p->stats_lock); +} + + .get_stats64 = ar9331_get_stats64, - int ret; + int ret, i; + for (i = 0; i < array_size(priv->port); i++) { + struct ar9331_sw_port *port = &priv->port[i]; + + port->idx = i; + spin_lock_init(&port->stats_lock); + init_delayed_work(&port->mib_read, ar9331_do_stats_poll); + } + + unsigned int i; + + for (i = 0; i < array_size(priv->port); i++) { + struct ar9331_sw_port *port = &priv->port[i]; + + cancel_delayed_work_sync(&port->mib_read); + }
|
Networking
|
bf9ce385932b61584684d31e2e5f8f485791e409
|
oleksij rempel
|
drivers
|
net
|
dsa, qca
|
net: dsa: sja1105: offload bridge port flags to device
|
the chip can configure unicast flooding, broadcast flooding and learning. learning is per port, while flooding is per {ingress, egress} port pair and we need to configure the same value for all possible ingress ports towards the requested one.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
offload bridge port flags to device
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'sja1105']
|
['h', 'c']
| 3
| 219
| 11
|
--- diff --git a/drivers/net/dsa/sja1105/sja1105.h b/drivers/net/dsa/sja1105/sja1105.h --- a/drivers/net/dsa/sja1105/sja1105.h +++ b/drivers/net/dsa/sja1105/sja1105.h + bool can_limit_mcast_flood; + unsigned long learn_ena; diff --git a/drivers/net/dsa/sja1105/sja1105_main.c b/drivers/net/dsa/sja1105/sja1105_main.c --- a/drivers/net/dsa/sja1105/sja1105_main.c +++ b/drivers/net/dsa/sja1105/sja1105_main.c +#define sja1105_unknown_multicast 0x010000000000ull + - if (allow) { - l2_fwd[from].bc_domain |= bit(to); + if (allow) - l2_fwd[from].fl_domain |= bit(to); - } else { - l2_fwd[from].bc_domain &= ~bit(to); + else - l2_fwd[from].fl_domain &= ~bit(to); - } + struct sja1105_l2_lookup_entry *l2_lookup; + int port; - /* we only populate the fdb table through dynamic - * l2 address lookup entries + /* we only populate the fdb table through dynamic l2 address lookup + * entries, except for a special entry at the end which is a catch-all + * for unknown multicast and will be used to control flooding domain. + + if (!priv->info->can_limit_mcast_flood) + return 0; + + table->entries = kcalloc(1, table->ops->unpacked_entry_size, + gfp_kernel); + if (!table->entries) + return -enomem; + + table->entry_count = 1; + l2_lookup = table->entries; + + /* all l2 multicast addresses have an odd first octet */ + l2_lookup[0].macaddr = sja1105_unknown_multicast; + l2_lookup[0].mask_macaddr = sja1105_unknown_multicast; + l2_lookup[0].lockeds = true; + l2_lookup[0].index = sja1105_max_l2_lookup_count - 1; + + /* flood multicast to every port by default */ + for (port = 0; port < priv->ds->num_ports; port++) + if (!dsa_is_unused_port(priv->ds, port)) + l2_lookup[0].destports |= bit(port); + + + l2fwd[i].bc_domain = bit(upstream); + l2fwd[i].fl_domain = bit(upstream); + + l2fwd[upstream].bc_domain |= bit(i); + l2fwd[upstream].fl_domain |= bit(i); + + /* we need to hide the fdb entry for unknown multicast */ + if (l2_lookup.macaddr == sja1105_unknown_multicast && + l2_lookup.mask_macaddr == sja1105_unknown_multicast) + continue; + - mac[port].dyn_learn = true; + mac[port].dyn_learn = !!(priv->learn_ena & bit(port)); - mac[port].dyn_learn = true; + mac[port].dyn_learn = !!(priv->learn_ena & bit(port)); +static int sja1105_port_set_learning(struct sja1105_private *priv, int port, + bool enabled) +{ + struct sja1105_mac_config_entry *mac; + int rc; + + mac = priv->static_config.tables[blk_idx_mac_config].entries; + + mac[port].dyn_learn = !!(priv->learn_ena & bit(port)); + + rc = sja1105_dynamic_config_write(priv, blk_idx_mac_config, port, + &mac[port], true); + if (rc) + return rc; + + if (enabled) + priv->learn_ena |= bit(port); + else + priv->learn_ena &= ~bit(port); + + return 0; +} + +/* common function for unicast and broadcast flood configuration. + * flooding is configured between each {ingress, egress} port pair, and since + * the bridge's semantics are those of "egress flooding", it means we must + * enable flooding towards this port from all ingress ports that are in the + * same bridge. in practice, we just enable flooding from all possible ingress + * ports regardless of whether they're in the same bridge or not, since the + * reach_port configuration will not allow flooded frames to leak across + * bridging domains anyway. + */ +static int sja1105_port_ucast_bcast_flood(struct sja1105_private *priv, int to, + struct switchdev_brport_flags flags) +{ + struct sja1105_l2_forwarding_entry *l2_fwd; + int from, rc; + + l2_fwd = priv->static_config.tables[blk_idx_l2_forwarding].entries; + + for (from = 0; from < priv->ds->num_ports; from++) { + if (dsa_is_unused_port(priv->ds, from)) + continue; + if (from == to) + continue; + + /* unicast */ + if (flags.mask & br_flood) { + if (flags.val & br_flood) + l2_fwd[from].fl_domain |= bit(to); + else + l2_fwd[from].fl_domain &= ~bit(to); + } + /* broadcast */ + if (flags.mask & br_bcast_flood) { + if (flags.val & br_bcast_flood) + l2_fwd[from].bc_domain |= bit(to); + else + l2_fwd[from].bc_domain &= ~bit(to); + } + + rc = sja1105_dynamic_config_write(priv, blk_idx_l2_forwarding, + from, &l2_fwd[from], true); + if (rc < 0) + return rc; + } + + return 0; +} + +static int sja1105_port_mcast_flood(struct sja1105_private *priv, int to, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct sja1105_l2_lookup_entry *l2_lookup; + struct sja1105_table *table; + int match; + + table = &priv->static_config.tables[blk_idx_l2_lookup]; + l2_lookup = table->entries; + + for (match = 0; match < table->entry_count; match++) + if (l2_lookup[match].macaddr == sja1105_unknown_multicast && + l2_lookup[match].mask_macaddr == sja1105_unknown_multicast) + break; + + if (match == table->entry_count) { + nl_set_err_msg_mod(extack, + "could not find fdb entry for unknown multicast"); + return -enospc; + } + + if (flags.val & br_mcast_flood) + l2_lookup[match].destports |= bit(to); + else + l2_lookup[match].destports &= ~bit(to); + + return sja1105_dynamic_config_write(priv, blk_idx_l2_lookup, + l2_lookup[match].index, + &l2_lookup[match], + true); +} + +static int sja1105_port_pre_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct sja1105_private *priv = ds->priv; + + if (flags.mask & ~(br_learning | br_flood | br_mcast_flood | + br_bcast_flood)) + return -einval; + + if (flags.mask & (br_flood | br_mcast_flood) && + !priv->info->can_limit_mcast_flood) { + bool multicast = !!(flags.val & br_mcast_flood); + bool unicast = !!(flags.val & br_flood); + + if (unicast != multicast) { + nl_set_err_msg_mod(extack, + "this chip cannot configure multicast flooding independently of unicast"); + return -einval; + } + } + + return 0; +} + +static int sja1105_port_bridge_flags(struct dsa_switch *ds, int port, + struct switchdev_brport_flags flags, + struct netlink_ext_ack *extack) +{ + struct sja1105_private *priv = ds->priv; + int rc; + + if (flags.mask & br_learning) { + bool learn_ena = !!(flags.val & br_learning); + + rc = sja1105_port_set_learning(priv, port, learn_ena); + if (rc) + return rc; + } + + if (flags.mask & (br_flood | br_bcast_flood)) { + rc = sja1105_port_ucast_bcast_flood(priv, port, flags); + if (rc) + return rc; + } + + /* for chips that can't offload br_mcast_flood independently, there + * is nothing to do here, we ensured the configuration is in sync by + * offloading br_flood. + */ + if (flags.mask & br_mcast_flood && priv->info->can_limit_mcast_flood) { + rc = sja1105_port_mcast_flood(priv, port, flags, + extack); + if (rc) + return rc; + } + + return 0; +} + + .port_pre_bridge_flags = sja1105_port_pre_bridge_flags, + .port_bridge_flags = sja1105_port_bridge_flags, diff --git a/drivers/net/dsa/sja1105/sja1105_spi.c b/drivers/net/dsa/sja1105/sja1105_spi.c --- a/drivers/net/dsa/sja1105/sja1105_spi.c +++ b/drivers/net/dsa/sja1105/sja1105_spi.c + .can_limit_mcast_flood = false, + .can_limit_mcast_flood = false, + .can_limit_mcast_flood = true, + .can_limit_mcast_flood = true, + .can_limit_mcast_flood = true, + .can_limit_mcast_flood = true,
|
Networking
|
4d9423549501812dafe6551d4a78db079ea87648
|
vladimir oltean
|
drivers
|
net
|
dsa, sja1105
|
net: dsa: tag_ocelot_8021q: add support for ptp timestamping
|
for tx timestamping, we use the felix_txtstamp method which is common with the regular (non-8021q) ocelot tagger. this method says that skb deferral is needed, prepares a timestamp request id, and puts a clone of the skb in a queue waiting for the timestamp irq.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for ptp timestamping
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'tag_ocelot_8021q']
|
['h', 'c']
| 5
| 115
| 2
|
- the cpu port module (for mmio based extraction) and - if the "no xtr irq" workaround is in place, the dsa_8021q cpu port --- diff --git a/drivers/net/dsa/ocelot/felix.c b/drivers/net/dsa/ocelot/felix.c --- a/drivers/net/dsa/ocelot/felix.c +++ b/drivers/net/dsa/ocelot/felix.c +#include <linux/ptp_classify.h> + /* the ownership of the cpu port module's queues might have just been + * transferred to the tag_8021q tagger from the npi-based tagger. + * so there might still be all sorts of crap in the queues. on the + * other hand, the mmio-based matching of ptp frames is very brittle, + * so we need to be careful that there are no extra frames to be + * dequeued over mmio, since we would never know to discard them. + */ + ocelot_drain_cpu_queue(ocelot, 0); + +static bool felix_check_xtr_pkt(struct ocelot *ocelot, unsigned int ptp_type) +{ + struct felix *felix = ocelot_to_felix(ocelot); + int err, grp = 0; + + if (felix->tag_proto != dsa_tag_proto_ocelot_8021q) + return false; + + if (!felix->info->quirk_no_xtr_irq) + return false; + + if (ptp_type == ptp_class_none) + return false; + + while (ocelot_read(ocelot, qs_xtr_data_present) & bit(grp)) { + struct sk_buff *skb; + unsigned int type; + + err = ocelot_xtr_poll_frame(ocelot, grp, &skb); + if (err) + goto out; + + /* we trap to the cpu port module all ptp frames, but + * felix_rxtstamp() only gets called for event frames. + * so we need to avoid sending duplicate general + * message frames by running a second bpf classifier + * here and dropping those. + */ + __skb_push(skb, eth_hlen); + + type = ptp_classify_raw(skb); + + __skb_pull(skb, eth_hlen); + + if (type == ptp_class_none) { + kfree_skb(skb); + continue; + } + + netif_rx(skb); + } + +out: + if (err < 0) + ocelot_drain_cpu_queue(ocelot, 0); + + return true; +} + + /* if the "no xtr irq" workaround is in use, tell dsa to defer this skb + * for rx timestamping. then free it, and poll for its copy through + * mmio in the cpu port module, and inject that into the stack from + * ocelot_xtr_poll(). + */ + if (felix_check_xtr_pkt(ocelot, type)) { + kfree_skb(skb); + return true; + } + diff --git a/drivers/net/ethernet/mscc/ocelot.c b/drivers/net/ethernet/mscc/ocelot.c --- a/drivers/net/ethernet/mscc/ocelot.c +++ b/drivers/net/ethernet/mscc/ocelot.c +void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) +{ + while (ocelot_read(ocelot, qs_xtr_data_present) & bit(grp)) + ocelot_read_rix(ocelot, qs_xtr_rd, grp); +} +export_symbol(ocelot_drain_cpu_queue); + diff --git a/drivers/net/ethernet/mscc/ocelot_vsc7514.c b/drivers/net/ethernet/mscc/ocelot_vsc7514.c --- a/drivers/net/ethernet/mscc/ocelot_vsc7514.c +++ b/drivers/net/ethernet/mscc/ocelot_vsc7514.c - while (ocelot_read(ocelot, qs_xtr_data_present) & bit(grp)) - ocelot_read_rix(ocelot, qs_xtr_rd, grp); + ocelot_drain_cpu_queue(ocelot, 0); diff --git a/include/soc/mscc/ocelot.h b/include/soc/mscc/ocelot.h --- a/include/soc/mscc/ocelot.h +++ b/include/soc/mscc/ocelot.h +void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp); +static inline void ocelot_drain_cpu_queue(struct ocelot *ocelot, int grp) +{ +} + diff --git a/net/dsa/tag_ocelot_8021q.c b/net/dsa/tag_ocelot_8021q.c --- a/net/dsa/tag_ocelot_8021q.c +++ b/net/dsa/tag_ocelot_8021q.c +#include <soc/mscc/ocelot.h> +#include <soc/mscc/ocelot_ptp.h> +static struct sk_buff *ocelot_xmit_ptp(struct dsa_port *dp, + struct sk_buff *skb, + struct sk_buff *clone) +{ + struct ocelot *ocelot = dp->ds->priv; + struct ocelot_port *ocelot_port; + int port = dp->index; + u32 rew_op; + + if (!ocelot_can_inject(ocelot, 0)) + return null; + + ocelot_port = ocelot->ports[port]; + rew_op = ocelot_port->ptp_cmd; + + /* retrieve timestamp id populated inside skb->cb[0] of the + * clone by ocelot_port_add_txtstamp_skb + */ + if (ocelot_port->ptp_cmd == ifh_rew_op_two_step_ptp) + rew_op |= clone->cb[0] << 3; + + ocelot_port_inject_frame(ocelot, port, 0, rew_op, skb); + + return null; +} + + struct sk_buff *clone = dsa_skb_cb(skb)->clone; + + /* tx timestamping was requested, so inject through mmio */ + if (clone) + return ocelot_xmit_ptp(dp, skb, clone);
|
Networking
|
0a6f17c6ae2116809a7b7eb6dd3eab59ef5460ef
|
vladimir oltean
|
include
|
soc
|
dsa, ethernet, mscc, ocelot
|
net: dsa: xrs700x: add hsr offloading support
|
add offloading for hsr/prp (iec 62439-3) tag insertion, tag removal forwarding and duplication supported by the xrs7000 series switches.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add hsr offloading support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['dsa ', 'xrs700x']
|
['h', 'c']
| 3
| 132
| 1
|
--- diff --git a/drivers/net/dsa/xrs700x/xrs700x.c b/drivers/net/dsa/xrs700x/xrs700x.c --- a/drivers/net/dsa/xrs700x/xrs700x.c +++ b/drivers/net/dsa/xrs700x/xrs700x.c +#include <linux/netdev_features.h> +#include <linux/if_hsr.h> +#define xrs7000x_supported_hsr_features \ + (netif_f_hw_hsr_tag_ins | netif_f_hw_hsr_tag_rm | \ + netif_f_hw_hsr_fwd | netif_f_hw_hsr_dup) + +static int xrs700x_hsr_join(struct dsa_switch *ds, int port, + struct net_device *hsr) +{ + unsigned int val = xrs_hsr_cfg_hsr_prp; + struct dsa_port *partner = null, *dp; + struct xrs700x *priv = ds->priv; + struct net_device *slave; + int ret, i, hsr_pair[2]; + enum hsr_version ver; + + ret = hsr_get_version(hsr, &ver); + if (ret) + return ret; + + /* only ports 1 and 2 can be hsr/prp redundant ports. */ + if (port != 1 && port != 2) + return -eopnotsupp; + + if (ver == hsr_v1) + val |= xrs_hsr_cfg_hsr; + else if (ver == prp_v1) + val |= xrs_hsr_cfg_prp; + else + return -eopnotsupp; + + dsa_hsr_foreach_port(dp, ds, hsr) { + partner = dp; + } + + /* we can't enable redundancy on the switch until both + * redundant ports have signed up. + */ + if (!partner) + return 0; + + regmap_fields_write(priv->ps_forward, partner->index, + xrs_port_disabled); + regmap_fields_write(priv->ps_forward, port, xrs_port_disabled); + + regmap_write(priv->regmap, xrs_hsr_cfg(partner->index), + val | xrs_hsr_cfg_lanid_a); + regmap_write(priv->regmap, xrs_hsr_cfg(port), + val | xrs_hsr_cfg_lanid_b); + + /* clear bits for both redundant ports (hsr only) and the cpu port to + * enable forwarding. + */ + val = genmask(ds->num_ports - 1, 0); + if (ver == hsr_v1) { + val &= ~bit(partner->index); + val &= ~bit(port); + } + val &= ~bit(dsa_upstream_port(ds, port)); + regmap_write(priv->regmap, xrs_port_fwd_mask(partner->index), val); + regmap_write(priv->regmap, xrs_port_fwd_mask(port), val); + + regmap_fields_write(priv->ps_forward, partner->index, + xrs_port_forwarding); + regmap_fields_write(priv->ps_forward, port, xrs_port_forwarding); + + hsr_pair[0] = port; + hsr_pair[1] = partner->index; + for (i = 0; i < array_size(hsr_pair); i++) { + slave = dsa_to_port(ds, hsr_pair[i])->slave; + slave->features |= xrs7000x_supported_hsr_features; + } + + return 0; +} + +static int xrs700x_hsr_leave(struct dsa_switch *ds, int port, + struct net_device *hsr) +{ + struct dsa_port *partner = null, *dp; + struct xrs700x *priv = ds->priv; + struct net_device *slave; + int i, hsr_pair[2]; + unsigned int val; + + dsa_hsr_foreach_port(dp, ds, hsr) { + partner = dp; + } + + if (!partner) + return 0; + + regmap_fields_write(priv->ps_forward, partner->index, + xrs_port_disabled); + regmap_fields_write(priv->ps_forward, port, xrs_port_disabled); + + regmap_write(priv->regmap, xrs_hsr_cfg(partner->index), 0); + regmap_write(priv->regmap, xrs_hsr_cfg(port), 0); + + /* clear bit for the cpu port to enable forwarding. */ + val = genmask(ds->num_ports - 1, 0); + val &= ~bit(dsa_upstream_port(ds, port)); + regmap_write(priv->regmap, xrs_port_fwd_mask(partner->index), val); + regmap_write(priv->regmap, xrs_port_fwd_mask(port), val); + + regmap_fields_write(priv->ps_forward, partner->index, + xrs_port_forwarding); + regmap_fields_write(priv->ps_forward, port, xrs_port_forwarding); + + hsr_pair[0] = port; + hsr_pair[1] = partner->index; + for (i = 0; i < array_size(hsr_pair); i++) { + slave = dsa_to_port(ds, hsr_pair[i])->slave; + slave->features &= ~xrs7000x_supported_hsr_features; + } + + return 0; +} + + .port_hsr_join = xrs700x_hsr_join, + .port_hsr_leave = xrs700x_hsr_leave, diff --git a/drivers/net/dsa/xrs700x/xrs700x_reg.h b/drivers/net/dsa/xrs700x/xrs700x_reg.h --- a/drivers/net/dsa/xrs700x/xrs700x_reg.h +++ b/drivers/net/dsa/xrs700x/xrs700x_reg.h +#define xrs_hsr_cfg_hsr_prp bit(0) +#define xrs_hsr_cfg_hsr 0 +#define xrs_hsr_cfg_prp bit(8) +#define xrs_hsr_cfg_lanid_a 0 +#define xrs_hsr_cfg_lanid_b bit(10) diff --git a/net/dsa/tag_xrs700x.c b/net/dsa/tag_xrs700x.c --- a/net/dsa/tag_xrs700x.c +++ b/net/dsa/tag_xrs700x.c - struct dsa_port *dp = dsa_slave_to_port(dev); + struct dsa_port *partner, *dp = dsa_slave_to_port(dev); + if (dp->hsr_dev) + dsa_hsr_foreach_port(partner, dp->ds, dp->hsr_dev) + if (partner != dp) + trailer[0] |= bit(partner->index); +
|
Networking
|
bd62e6f5e6a98f1657cf9c3b632bdb7a2e78d42c
|
george mccollister
|
drivers
|
net
|
dsa, xrs700x
|
net: ethernet: mediatek: support setting mtu
|
mt762x hw, except for mt7628, supports frame length up to 2048 (maximum length on gdm), so allow setting mtu up to 2030.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support setting mtu
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mediatek']
|
['h', 'c']
| 2
| 47
| 8
|
--- diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c - mcr_new |= mac_mcr_max_rx_1536 | mac_mcr_ipg_cfg | mac_mcr_force_mode | + mcr_new |= mac_mcr_ipg_cfg | mac_mcr_force_mode | - if (mtu + mtk_rx_eth_hlen < mtk_max_rx_length) - mtu = mtk_max_rx_length - mtk_rx_eth_hlen; + if (mtu + mtk_rx_eth_hlen < mtk_max_rx_length_2k) + mtu = mtk_max_rx_length_2k - mtk_rx_eth_hlen; - warn_on(buf_size < mtk_max_rx_length); + warn_on(buf_size < mtk_max_rx_length_2k); +static int mtk_change_mtu(struct net_device *dev, int new_mtu) +{ + int length = new_mtu + mtk_rx_eth_hlen; + struct mtk_mac *mac = netdev_priv(dev); + struct mtk_eth *eth = mac->hw; + u32 mcr_cur, mcr_new; + + if (!mtk_has_caps(eth->soc->caps, mtk_soc_mt7628)) { + mcr_cur = mtk_r32(mac->hw, mtk_mac_mcr(mac->id)); + mcr_new = mcr_cur & ~mac_mcr_max_rx_mask; + + if (length <= 1518) + mcr_new |= mac_mcr_max_rx(mac_mcr_max_rx_1518); + else if (length <= 1536) + mcr_new |= mac_mcr_max_rx(mac_mcr_max_rx_1536); + else if (length <= 1552) + mcr_new |= mac_mcr_max_rx(mac_mcr_max_rx_1552); + else + mcr_new |= mac_mcr_max_rx(mac_mcr_max_rx_2048); + + if (mcr_new != mcr_cur) + mtk_w32(mac->hw, mcr_new, mtk_mac_mcr(mac->id)); + } + + dev->mtu = new_mtu; + + return 0; +} + + .ndo_change_mtu = mtk_change_mtu, - eth->netdev[id]->max_mtu = mtk_max_rx_length - mtk_rx_eth_hlen; + if (mtk_has_caps(eth->soc->caps, mtk_soc_mt7628)) + eth->netdev[id]->max_mtu = mtk_max_rx_length - mtk_rx_eth_hlen; + else + eth->netdev[id]->max_mtu = mtk_max_rx_length_2k - mtk_rx_eth_hlen; diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h -#define mtk_max_rx_length 1536 +#define mtk_max_rx_length 1536 +#define mtk_max_rx_length_2k 2048 -#define mtk_rx_eth_hlen (vlan_eth_hlen + vlan_hlen + eth_fcs_len) +#define mtk_rx_eth_hlen (eth_hlen + eth_fcs_len) -#define mac_mcr_max_rx_1536 bit(24) +#define mac_mcr_max_rx_mask genmask(25, 24) +#define mac_mcr_max_rx(_x) (mac_mcr_max_rx_mask & ((_x) << 24)) +#define mac_mcr_max_rx_1518 0x0 +#define mac_mcr_max_rx_1536 0x1 +#define mac_mcr_max_rx_1552 0x2 +#define mac_mcr_max_rx_2048 0x3
|
Networking
|
4fd59792097a6b2fb949d41264386a7ecade469e
|
deng qingfang
|
drivers
|
net
|
ethernet, mediatek
|
fsl/fman: add mii mode support.
|
set proper value to if_mode register for mii mode.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mii mode support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['fsl/fman']
|
['c']
| 1
| 4
| 0
|
--- diff --git a/drivers/net/ethernet/freescale/fman/fman_memac.c b/drivers/net/ethernet/freescale/fman/fman_memac.c --- a/drivers/net/ethernet/freescale/fman/fman_memac.c +++ b/drivers/net/ethernet/freescale/fman/fman_memac.c +#define if_mode_mii 0x00000001 /* 30-31 mii interface */ + case phy_interface_mode_mii: + tmp |= if_mode_mii; + break;
|
Networking
|
5bc8f5ab3b752306d6a1e0e4fa6c4473c15a2924
|
maxim kochetkov
|
drivers
|
net
|
ethernet, fman, freescale
|
gtp: include role in link info
|
querying link info for the gtp interface doesn't reveal in which "role" the device is set to operate. include this information in the info query result.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
include role in link info
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gtp ']
|
['c']
| 1
| 4
| 1
|
--- diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c --- a/drivers/net/gtp.c +++ b/drivers/net/gtp.c - return nla_total_size(sizeof(__u32)); /* ifla_gtp_pdp_hashsize */ + return nla_total_size(sizeof(__u32)) + /* ifla_gtp_pdp_hashsize */ + nla_total_size(sizeof(__u32)); /* ifla_gtp_role */ + if (nla_put_u32(skb, ifla_gtp_role, gtp->role)) + goto nla_put_failure;
|
Networking
|
e1b2914e645caa702ad6ddf4f1c48bdedb3d43cf
|
jonas bonn harald welte laforge gnumonks org pravin b shelar pshelar ovn org
|
drivers
|
net
| |
gtp: set initial mtu
|
the gtp link is brought up with a default mtu of zero. this can lead to some rather unexpected behaviour for users who are more accustomed to interfaces coming online with reasonable defaults.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sset initial mtu
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['gtp ']
|
['c']
| 1
| 6
| 5
|
--- diff --git a/drivers/net/gtp.c b/drivers/net/gtp.c --- a/drivers/net/gtp.c +++ b/drivers/net/gtp.c + unsigned int max_gtp_header_len = sizeof(struct iphdr) + + sizeof(struct udphdr) + + sizeof(struct gtp0_header); + + dev->mtu = eth_data_len - max_gtp_header_len; - /* assume largest header, ie. gtpv0. */ - dev->needed_headroom = ll_max_header + - sizeof(struct iphdr) + - sizeof(struct udphdr) + - sizeof(struct gtp0_header); + dev->needed_headroom = ll_max_header + max_gtp_header_len;
|
Networking
|
e21eb3a065a2d90ee3bb06cc2e77acad403ec7cd
|
jonas bonn
|
drivers
|
net
| |
net: hns3: add interfaces to query information of tm priority/qset
|
add some interfaces to get information of tm priority and qset, then they can be used by debugfs.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add interfaces to query information of tm priority/qset
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hns3 ']
|
['h', 'c']
| 3
| 234
| 1
|
--- diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h + hclge_opc_tm_nodes = 0x0816, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c + +int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num) +{ + struct hclge_tm_nodes_cmd *nodes; + struct hclge_desc desc; + int ret; + + if (hdev->ae_dev->dev_version <= hnae3_device_version_v2) { + /* each pf has 8 qsets and each vf has 1 qset */ + *qset_num = hclge_tm_pf_max_qset_num + pci_num_vf(hdev->pdev); + return 0; + } + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_nodes, true); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get qset num, ret = %d ", ret); + return ret; + } + + nodes = (struct hclge_tm_nodes_cmd *)desc.data; + *qset_num = le16_to_cpu(nodes->qset_num); + return 0; +} + +int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num) +{ + struct hclge_tm_nodes_cmd *nodes; + struct hclge_desc desc; + int ret; + + if (hdev->ae_dev->dev_version <= hnae3_device_version_v2) { + *pri_num = hclge_tm_pf_max_pri_num; + return 0; + } + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_nodes, true); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get pri num, ret = %d ", ret); + return ret; + } + + nodes = (struct hclge_tm_nodes_cmd *)desc.data; + *pri_num = nodes->pri_num; + return 0; +} + +int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority, + u8 *link_vld) +{ + struct hclge_qs_to_pri_link_cmd *map; + struct hclge_desc desc; + int ret; + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_qs_to_pri_link, true); + map = (struct hclge_qs_to_pri_link_cmd *)desc.data; + map->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get qset map priority, ret = %d ", ret); + return ret; + } + + *priority = map->priority; + *link_vld = map->link_vld; + return 0; +} + +int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode) +{ + struct hclge_qs_sch_mode_cfg_cmd *qs_sch_mode; + struct hclge_desc desc; + int ret; + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_qs_sch_mode_cfg, true); + qs_sch_mode = (struct hclge_qs_sch_mode_cfg_cmd *)desc.data; + qs_sch_mode->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get qset sch mode, ret = %d ", ret); + return ret; + } + + *mode = qs_sch_mode->sch_mode; + return 0; +} + +int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight) +{ + struct hclge_qs_weight_cmd *qs_weight; + struct hclge_desc desc; + int ret; + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_qs_weight, true); + qs_weight = (struct hclge_qs_weight_cmd *)desc.data; + qs_weight->qs_id = cpu_to_le16(qset_id); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get qset weight, ret = %d ", ret); + return ret; + } + + *weight = qs_weight->dwrr; + return 0; +} + +int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode) +{ + struct hclge_pri_sch_mode_cfg_cmd *pri_sch_mode; + struct hclge_desc desc; + int ret; + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_pri_sch_mode_cfg, true); + pri_sch_mode = (struct hclge_pri_sch_mode_cfg_cmd *)desc.data; + pri_sch_mode->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get priority sch mode, ret = %d ", ret); + return ret; + } + + *mode = pri_sch_mode->sch_mode; + return 0; +} + +int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight) +{ + struct hclge_priority_weight_cmd *priority_weight; + struct hclge_desc desc; + int ret; + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_pri_weight, true); + priority_weight = (struct hclge_priority_weight_cmd *)desc.data; + priority_weight->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get priority weight, ret = %d ", ret); + return ret; + } + + *weight = priority_weight->dwrr; + return 0; +} + +int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id, + enum hclge_opcode_type cmd, + struct hclge_pri_shaper_para *para) +{ + struct hclge_pri_shapping_cmd *shap_cfg_cmd; + struct hclge_desc desc; + u32 shapping_para; + int ret; + + if (cmd != hclge_opc_tm_pri_c_shapping && + cmd != hclge_opc_tm_pri_p_shapping) + return -einval; + + hclge_cmd_setup_basic_desc(&desc, cmd, true); + shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data; + shap_cfg_cmd->pri_id = pri_id; + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to get priority shaper(%#x), ret = %d ", + cmd, ret); + return ret; + } + + shapping_para = le32_to_cpu(shap_cfg_cmd->pri_shapping_para); + para->ir_b = hclge_tm_get_field(shapping_para, ir_b); + para->ir_u = hclge_tm_get_field(shapping_para, ir_u); + para->ir_s = hclge_tm_get_field(shapping_para, ir_s); + para->bs_b = hclge_tm_get_field(shapping_para, bs_b); + para->bs_s = hclge_tm_get_field(shapping_para, bs_s); + para->flag = shap_cfg_cmd->flag; + para->rate = le32_to_cpu(shap_cfg_cmd->pri_rate); + return 0; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.h +#define hclge_tm_pf_max_pri_num 8 +#define hclge_tm_pf_max_qset_num 8 + +struct hclge_pri_sch_mode_cfg_cmd { + u8 pri_id; + u8 rsvd[3]; + u8 sch_mode; +}; + +struct hclge_qs_sch_mode_cfg_cmd { + __le16 qs_id; + u8 rsvd[2]; + u8 sch_mode; +}; + +struct hclge_tm_nodes_cmd { + u8 pg_base_id; + u8 pri_base_id; + __le16 qset_base_id; + __le16 queue_base_id; + u8 pg_num; + u8 pri_num; + __le16 qset_num; + __le16 queue_num; +}; + +struct hclge_pri_shaper_para { + u8 ir_b; + u8 ir_u; + u8 ir_s; + u8 bs_b; + u8 bs_s; + u8 flag; + u32 rate; +}; + - +int hclge_tm_get_qset_num(struct hclge_dev *hdev, u16 *qset_num); +int hclge_tm_get_pri_num(struct hclge_dev *hdev, u8 *pri_num); +int hclge_tm_get_qset_map_pri(struct hclge_dev *hdev, u16 qset_id, u8 *priority, + u8 *link_vld); +int hclge_tm_get_qset_sch_mode(struct hclge_dev *hdev, u16 qset_id, u8 *mode); +int hclge_tm_get_qset_weight(struct hclge_dev *hdev, u16 qset_id, u8 *weight); +int hclge_tm_get_pri_sch_mode(struct hclge_dev *hdev, u8 pri_id, u8 *mode); +int hclge_tm_get_pri_weight(struct hclge_dev *hdev, u8 pri_id, u8 *weight); +int hclge_tm_get_pri_shaper(struct hclge_dev *hdev, u8 pri_id, + enum hclge_opcode_type cmd, + struct hclge_pri_shaper_para *para);
|
Networking
|
2bbad0aa40e172e7ed7aba6f6ad4d9977dbd0be3
|
guangbin huang
|
drivers
|
net
|
ethernet, hisilicon, hns3, hns3pf
|
net: hns3: add support for obtaining the maximum frame size
|
since the newer hardware may supports different frame size, so add support to obtain the capability from the firmware instead of the fixed value.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for obtaining the maximum frame size
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hns3 ']
|
['h', 'c']
| 9
| 20
| 8
|
--- diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h + u16 max_frm_size; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c + dev_info(priv->dev, "max frame size: %u ", dev_specs->max_frm_size); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c - /* mtu range: (eth_min_mtu(kernel default) - 9702) */ - netdev->max_mtu = hns3_max_mtu; + netdev->max_mtu = hns3_max_mtu(ae_dev->dev_specs.max_frm_size); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h -#define hns3_mac_max_frame 9728 -#define hns3_max_mtu \ - (hns3_mac_max_frame - (eth_hlen + eth_fcs_len + 2 * vlan_hlen)) +#define hns3_max_mtu(max_frm_size) \ + ((max_frm_size) - (eth_hlen + eth_fcs_len + 2 * vlan_hlen)) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h - __le32 rsv0; + __le16 max_frm_size; + __le16 rsv0; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c + ae_dev->dev_specs.max_frm_size = hclge_mac_max_frame; + ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); + if (!dev_specs->max_frm_size) + dev_specs->max_frm_size = hclge_mac_max_frame; - max_frm_size > hclge_mac_max_frame) + max_frm_size > hdev->ae_dev->dev_specs.max_frm_size) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h - __le32 rsv0; + __le16 max_frm_size; + __le16 rsv0; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c + ae_dev->dev_specs.max_frm_size = hclgevf_mac_max_frame; + ae_dev->dev_specs.max_frm_size = le16_to_cpu(req1->max_frm_size); + if (!dev_specs->max_frm_size) + dev_specs->max_frm_size = hclgevf_mac_max_frame; diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h +#define hclgevf_mac_max_frame 9728 +
|
Networking
|
e070c8b91ac1c7810c8448b1e5534d1895a0c7f4
|
yufeng mo
|
drivers
|
net
|
ethernet, hisilicon, hns3, hns3pf, hns3vf
|
net: hns3: add debugfs support for tm nodes, priority and qset info
|
in order to query tm info of nodes, priority and qset for debugging, adds three debugfs files tm_nodes, tm_priority and tm_qset in newly created tm directory.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add debugfs support for tm nodes, priority and qset info
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hns3 ']
|
['h', 'c']
| 5
| 218
| 1
|
--- diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h b/drivers/net/ethernet/hisilicon/hns3/hnae3.h --- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h +++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h + * dbg_read_cmd + * execute debugfs read command. + int (*dbg_read_cmd)(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len); +#define hnae3_dbg_tm_nodes "tm_nodes" +#define hnae3_dbg_tm_pri "tm_priority" +#define hnae3_dbg_tm_qset "tm_qset" + diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c -#define hns3_dbg_read_len 256 +#define hns3_dbg_read_len 65536 +static ssize_t hns3_dbg_read(struct file *filp, char __user *buffer, + size_t count, loff_t *ppos) +{ + struct hnae3_handle *handle = filp->private_data; + const struct hnae3_ae_ops *ops = handle->ae_algo->ops; + struct hns3_nic_priv *priv = handle->priv; + char *cmd_buf, *read_buf; + ssize_t size = 0; + int ret = 0; + + if (!filp->f_path.dentry->d_iname) + return -einval; + + read_buf = kzalloc(hns3_dbg_read_len, gfp_kernel); + if (!read_buf) + return -enomem; + + cmd_buf = filp->f_path.dentry->d_iname; + + if (ops->dbg_read_cmd) + ret = ops->dbg_read_cmd(handle, cmd_buf, read_buf, + hns3_dbg_read_len); + + if (ret) { + dev_info(priv->dev, "unknown command "); + goto out; + } + + size = simple_read_from_buffer(buffer, count, ppos, read_buf, + strlen(read_buf)); + +out: + kfree(read_buf); + return size; +} + +static const struct file_operations hns3_dbg_fops = { + .owner = this_module, + .open = simple_open, + .read = hns3_dbg_read, +}; + + struct hnae3_ae_dev *ae_dev = pci_get_drvdata(handle->pdev); + struct dentry *entry_dir; + + entry_dir = debugfs_create_dir("tm", handle->hnae3_dbgfs); + if (ae_dev->dev_version > hnae3_device_version_v2) + debugfs_create_file(hnae3_dbg_tm_nodes, 0600, entry_dir, handle, + &hns3_dbg_fops); + debugfs_create_file(hnae3_dbg_tm_pri, 0600, entry_dir, handle, + &hns3_dbg_fops); + debugfs_create_file(hnae3_dbg_tm_qset, 0600, entry_dir, handle, + &hns3_dbg_fops); diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c +static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len) +{ + struct hclge_tm_nodes_cmd *nodes; + struct hclge_desc desc; + int pos = 0; + int ret; + + hclge_cmd_setup_basic_desc(&desc, hclge_opc_tm_nodes, true); + ret = hclge_cmd_send(&hdev->hw, &desc, 1); + if (ret) { + dev_err(&hdev->pdev->dev, + "failed to dump tm nodes, ret = %d ", ret); + return ret; + } + + nodes = (struct hclge_tm_nodes_cmd *)desc.data; + + pos += scnprintf(buf + pos, len - pos, " base_id max_num "); + pos += scnprintf(buf + pos, len - pos, "pg %4u %4u ", + nodes->pg_base_id, nodes->pg_num); + pos += scnprintf(buf + pos, len - pos, "pri %4u %4u ", + nodes->pri_base_id, nodes->pri_num); + pos += scnprintf(buf + pos, len - pos, "qset %4u %4u ", + le16_to_cpu(nodes->qset_base_id), + le16_to_cpu(nodes->qset_num)); + pos += scnprintf(buf + pos, len - pos, "queue %4u %4u ", + le16_to_cpu(nodes->queue_base_id), + le16_to_cpu(nodes->queue_num)); + + return 0; +} + +static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len) +{ + struct hclge_pri_shaper_para c_shaper_para; + struct hclge_pri_shaper_para p_shaper_para; + u8 pri_num, sch_mode, weight; + char *sch_mode_str; + int pos = 0; + int ret; + u8 i; + + ret = hclge_tm_get_pri_num(hdev, &pri_num); + if (ret) + return ret; + + pos += scnprintf(buf + pos, len - pos, + "id mode dwrr c_ir_b c_ir_u c_ir_s c_bs_b "); + pos += scnprintf(buf + pos, len - pos, + "c_bs_s c_flag c_rate(mbps) p_ir_b p_ir_u "); + pos += scnprintf(buf + pos, len - pos, + "p_ir_s p_bs_b p_bs_s p_flag p_rate(mbps) "); + + for (i = 0; i < pri_num; i++) { + ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode); + if (ret) + return ret; + + ret = hclge_tm_get_pri_weight(hdev, i, &weight); + if (ret) + return ret; + + ret = hclge_tm_get_pri_shaper(hdev, i, + hclge_opc_tm_pri_c_shapping, + &c_shaper_para); + if (ret) + return ret; + + ret = hclge_tm_get_pri_shaper(hdev, i, + hclge_opc_tm_pri_p_shapping, + &p_shaper_para); + if (ret) + return ret; + + sch_mode_str = sch_mode & hclge_tm_tx_schd_dwrr_msk ? "dwrr" : + "sp"; + + pos += scnprintf(buf + pos, len - pos, + "%04u %4s %3u %3u %3u %3u ", + i, sch_mode_str, weight, c_shaper_para.ir_b, + c_shaper_para.ir_u, c_shaper_para.ir_s); + pos += scnprintf(buf + pos, len - pos, + "%3u %3u %1u %6u ", + c_shaper_para.bs_b, c_shaper_para.bs_s, + c_shaper_para.flag, c_shaper_para.rate); + pos += scnprintf(buf + pos, len - pos, + "%3u %3u %3u %3u %3u ", + p_shaper_para.ir_b, p_shaper_para.ir_u, + p_shaper_para.ir_s, p_shaper_para.bs_b, + p_shaper_para.bs_s); + pos += scnprintf(buf + pos, len - pos, "%1u %6u ", + p_shaper_para.flag, p_shaper_para.rate); + } + + return 0; +} + +static int hclge_dbg_dump_tm_qset(struct hclge_dev *hdev, char *buf, int len) +{ + u8 priority, link_vld, sch_mode, weight; + char *sch_mode_str; + int ret, pos; + u16 qset_num; + u16 i; + + ret = hclge_tm_get_qset_num(hdev, &qset_num); + if (ret) + return ret; + + pos = scnprintf(buf, len, "id map_pri link_vld mode dwrr "); + + for (i = 0; i < qset_num; i++) { + ret = hclge_tm_get_qset_map_pri(hdev, i, &priority, &link_vld); + if (ret) + return ret; + + ret = hclge_tm_get_qset_sch_mode(hdev, i, &sch_mode); + if (ret) + return ret; + + ret = hclge_tm_get_qset_weight(hdev, i, &weight); + if (ret) + return ret; + + sch_mode_str = sch_mode & hclge_tm_tx_schd_dwrr_msk ? "dwrr" : + "sp"; + pos += scnprintf(buf + pos, len - pos, + "%04u %4u %1u %4s %3u ", + i, priority, link_vld, sch_mode_str, weight); + } + + return 0; +} + + +int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len) +{ + struct hclge_vport *vport = hclge_get_vport(handle); + struct hclge_dev *hdev = vport->back; + + if (strncmp(cmd_buf, hnae3_dbg_tm_nodes, + strlen(hnae3_dbg_tm_nodes)) == 0) + return hclge_dbg_dump_tm_nodes(hdev, buf, len); + else if (strncmp(cmd_buf, hnae3_dbg_tm_pri, + strlen(hnae3_dbg_tm_pri)) == 0) + return hclge_dbg_dump_tm_pri(hdev, buf, len); + else if (strncmp(cmd_buf, hnae3_dbg_tm_qset, + strlen(hnae3_dbg_tm_qset)) == 0) + return hclge_dbg_dump_tm_qset(hdev, buf, len); + + return -einval; +} diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c + .dbg_read_cmd = hclge_dbg_read_cmd, diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h --- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h +int hclge_dbg_read_cmd(struct hnae3_handle *handle, const char *cmd_buf, + char *buf, int len);
|
Networking
|
04987ca1b9b6841cfa5f9b459c5a270b75c89345
|
guangbin huang
|
drivers
|
net
|
ethernet, hisilicon, hns3, hns3pf
|
net: hns3: debugfs add max tm rate specification print
|
in order to add a method to check the specification of max tm rate for debugging, function hns3_dbg_dev_specs() adds this value print.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
debugfs add max tm rate specification print
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['hns3 ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c + dev_info(priv->dev, "max tm rate: %umbps ", dev_specs->max_tm_rate);
|
Networking
|
2783e77b8df96aea2a5719af19b5f85e89d91982
|
guangbin huang
|
drivers
|
net
|
ethernet, hisilicon, hns3
|
i40e: add eee status getting & setting implementation
|
implement energy efficient ethernet (eee) status getting & setting. the i40e_get_eee() requesting phy eee capabilities from firmware. the i40e_set_eee() function requests phy eee capabilities from firmware and sets phy eee advertising to full abilities or 0 depending whether eee is to be enabled or disabled.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement get and set ethtool ops for energy efficient ethernet
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['i40e ']
|
['h', 'c']
| 2
| 123
| 2
|
--- diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c --- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c - return -eopnotsupp; + struct i40e_netdev_priv *np = netdev_priv(netdev); + struct i40e_aq_get_phy_abilities_resp phy_cfg; + enum i40e_status_code status = 0; + struct i40e_vsi *vsi = np->vsi; + struct i40e_pf *pf = vsi->back; + struct i40e_hw *hw = &pf->hw; + + /* get initial phy capabilities */ + status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_cfg, null); + if (status) + return -eagain; + + /* check whether nic configuration is compatible with energy efficient + * ethernet (eee) mode. + */ + if (phy_cfg.eee_capability == 0) + return -eopnotsupp; + + edata->supported = supported_autoneg; + edata->lp_advertised = edata->supported; + + /* get current configuration */ + status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_cfg, null); + if (status) + return -eagain; + + edata->advertised = phy_cfg.eee_capability ? supported_autoneg : 0u; + edata->eee_enabled = !!edata->advertised; + edata->tx_lpi_enabled = pf->stats.tx_lpi_status; + + edata->eee_active = pf->stats.tx_lpi_status && pf->stats.rx_lpi_status; + + return 0; +} + +static int i40e_is_eee_param_supported(struct net_device *netdev, + struct ethtool_eee *edata) +{ + struct i40e_netdev_priv *np = netdev_priv(netdev); + struct i40e_vsi *vsi = np->vsi; + struct i40e_pf *pf = vsi->back; + struct i40e_ethtool_not_used { + u32 value; + const char *name; + } param[] = { + {edata->advertised & ~supported_autoneg, "advertise"}, + {edata->tx_lpi_timer, "tx-timer"}, + {edata->tx_lpi_enabled != pf->stats.tx_lpi_status, "tx-lpi"} + }; + int i; + + for (i = 0; i < array_size(param); i++) { + if (param[i].value) { + netdev_info(netdev, + "eee setting %s not supported ", + param[i].name); + return -eopnotsupp; + } + } + + return 0; - return -eopnotsupp; + struct i40e_netdev_priv *np = netdev_priv(netdev); + struct i40e_aq_get_phy_abilities_resp abilities; + enum i40e_status_code status = i40e_success; + struct i40e_aq_set_phy_config config; + struct i40e_vsi *vsi = np->vsi; + struct i40e_pf *pf = vsi->back; + struct i40e_hw *hw = &pf->hw; + __le16 eee_capability; + + /* deny parameters we don't support */ + if (i40e_is_eee_param_supported(netdev, edata)) + return -eopnotsupp; + + /* get initial phy capabilities */ + status = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, + null); + if (status) + return -eagain; + + /* check whether nic configuration is compatible with energy efficient + * ethernet (eee) mode. + */ + if (abilities.eee_capability == 0) + return -eopnotsupp; + + /* cache initial eee capability */ + eee_capability = abilities.eee_capability; + + /* get current phy configuration */ + status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, + null); + if (status) + return -eagain; + + /* cache current phy configuration */ + config.phy_type = abilities.phy_type; + config.phy_type_ext = abilities.phy_type_ext; + config.link_speed = abilities.link_speed; + config.abilities = abilities.abilities | + i40e_aq_phy_enable_atomic_link; + config.eeer = abilities.eeer_val; + config.low_power_ctrl = abilities.d3_lpan; + config.fec_config = abilities.fec_cfg_curr_mod_ext_info & + i40e_aq_phy_fec_config_mask; + + /* set desired eee state */ + if (edata->eee_enabled) { + config.eee_capability = eee_capability; + config.eeer |= cpu_to_le32(i40e_prtpm_eeer_tx_lpi_en_mask); + } else { + config.eee_capability = 0; + config.eeer &= cpu_to_le32(~i40e_prtpm_eeer_tx_lpi_en_mask); + } + + /* apply modified phy configuration */ + status = i40e_aq_set_phy_config(hw, &config, null); + if (status) + return -eagain; + + return 0; diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h --- a/drivers/net/ethernet/intel/i40e/i40e_register.h +++ b/drivers/net/ethernet/intel/i40e/i40e_register.h +#define i40e_prtpm_eeer_tx_lpi_en_shift 16 +#define i40e_prtpm_eeer_tx_lpi_en_mask i40e_mask(0x1, i40e_prtpm_eeer_tx_lpi_en_shift)
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Networking
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95f352dca19df850ac106ab8ea6793555bf1ad18
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aleksandr loktionov tony brelinski tonyx brelinski intel com
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drivers
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net
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ethernet, i40e, intel
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i40e: add flow director support for ipv6
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flow director for ipv6 is not supported. 1) implementation of support for ipv6 flow director. 2) added handlers for addition of tcp6, udp6, sctp6, ipv6. 3) refactored legacy code to make it more generic. 4) added packet templates for tcp6, udp6, sctp6, ipv6. 5) added handling of ipv6 source and destination address for flow director. 6) improved argument passing for source and destination portin tcp6, udp6 and sctp6. 7) added handling of ethtool -n for ipv6, tcp6,udp6, sctp6. 8) used correct bit flag regarding flexoff field of flow director data descriptor.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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extend support for ntuple filters allowing for flow director ipv6 and vlan filters
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['i40e ']
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['h', 'c']
| 4
| 551
| 119
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--- diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h --- a/drivers/net/ethernet/intel/i40e/i40e.h +++ b/drivers/net/ethernet/intel/i40e/i40e.h - u8 ip4_proto; + u8 ipl4_proto; + __be32 dst_ip6[4]; + __be32 src_ip6[4]; + u16 fd_tcp6_filter_cnt; + u16 fd_udp6_filter_cnt; + u16 fd_sctp6_filter_cnt; + u16 fd_ip6_filter_cnt; + diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c --- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c - /* reverse the src and dest notion, since the hw views them from - * tx perspective where as the user expects it from rx filter view. - */ - fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port; - fsp->h_u.tcp_ip4_spec.pdst = rule->src_port; - fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip; - fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip; + if (fsp->flow_type == ipv6_user_flow || + fsp->flow_type == udp_v6_flow || + fsp->flow_type == tcp_v6_flow || + fsp->flow_type == sctp_v6_flow) { + /* reverse the src and dest notion, since the hw views them + * from tx perspective where as the user expects it from + * rx filter view. + */ + fsp->h_u.tcp_ip6_spec.psrc = rule->dst_port; + fsp->h_u.tcp_ip6_spec.pdst = rule->src_port; + memcpy(fsp->h_u.tcp_ip6_spec.ip6dst, rule->src_ip6, + sizeof(__be32) * 4); + memcpy(fsp->h_u.tcp_ip6_spec.ip6src, rule->dst_ip6, + sizeof(__be32) * 4); + } else { + /* reverse the src and dest notion, since the hw views them + * from tx perspective where as the user expects it from + * rx filter view. + */ + fsp->h_u.tcp_ip4_spec.psrc = rule->dst_port; + fsp->h_u.tcp_ip4_spec.pdst = rule->src_port; + fsp->h_u.tcp_ip4_spec.ip4src = rule->dst_ip; + fsp->h_u.tcp_ip4_spec.ip4dst = rule->src_ip; + } + case sctp_v6_flow: + index = i40e_filter_pctype_nonf_ipv6_sctp; + break; + case tcp_v6_flow: + index = i40e_filter_pctype_nonf_ipv6_tcp; + break; + case udp_v6_flow: + index = i40e_filter_pctype_nonf_ipv6_udp; + break; + case ipv6_user_flow: + index = i40e_filter_pctype_nonf_ipv6_other; + break; + if (input_set & i40e_l3_v6_src_mask) { + fsp->m_u.tcp_ip6_spec.ip6src[0] = htonl(0xffffffff); + fsp->m_u.tcp_ip6_spec.ip6src[1] = htonl(0xffffffff); + fsp->m_u.tcp_ip6_spec.ip6src[2] = htonl(0xffffffff); + fsp->m_u.tcp_ip6_spec.ip6src[3] = htonl(0xffffffff); + } + + if (input_set & i40e_l3_v6_dst_mask) { + fsp->m_u.tcp_ip6_spec.ip6dst[0] = htonl(0xffffffff); + fsp->m_u.tcp_ip6_spec.ip6dst[1] = htonl(0xffffffff); + fsp->m_u.tcp_ip6_spec.ip6dst[2] = htonl(0xffffffff); + fsp->m_u.tcp_ip6_spec.ip6dst[3] = htonl(0xffffffff); + } + + case tcp_v6_flow: + return "tcp6"; + case udp_v6_flow: + return "udp6"; + case sctp_v6_flow: + return "sctp6"; + case ipv6_user_flow: + return "ip6"; - struct i40e_pf *pf = vsi->back; + static const __be32 ipv6_full_mask[4] = {cpu_to_be32(0xffffffff), + cpu_to_be32(0xffffffff), cpu_to_be32(0xffffffff), + cpu_to_be32(0xffffffff)}; + struct ethtool_tcpip6_spec *tcp_ip6_spec; + struct ethtool_usrip6_spec *usr_ip6_spec; + struct i40e_pf *pf = vsi->back; + case sctp_v6_flow: + index = i40e_filter_pctype_nonf_ipv6_sctp; + fdir_filter_count = &pf->fd_sctp6_filter_cnt; + break; + case tcp_v6_flow: + index = i40e_filter_pctype_nonf_ipv6_tcp; + fdir_filter_count = &pf->fd_tcp6_filter_cnt; + break; + case udp_v6_flow: + index = i40e_filter_pctype_nonf_ipv6_udp; + fdir_filter_count = &pf->fd_udp6_filter_cnt; + break; + case ipv6_user_flow: + index = i40e_filter_pctype_nonf_ipv6_other; + fdir_filter_count = &pf->fd_ip6_filter_cnt; + flex_l3 = true; + break; + case sctp_v6_flow: + new_mask &= ~i40e_verify_tag_mask; + fallthrough; + case tcp_v6_flow: + case udp_v6_flow: + tcp_ip6_spec = &fsp->m_u.tcp_ip6_spec; + + /* check if user provided ipv6 source address. */ + if (ipv6_addr_equal((struct in6_addr *)&tcp_ip6_spec->ip6src, + (struct in6_addr *)&ipv6_full_mask)) + new_mask |= i40e_l3_v6_src_mask; + else if (ipv6_addr_any((struct in6_addr *) + &tcp_ip6_spec->ip6src)) + new_mask &= ~i40e_l3_v6_src_mask; + else + return -eopnotsupp; + + /* check if user provided destination address. */ + if (ipv6_addr_equal((struct in6_addr *)&tcp_ip6_spec->ip6dst, + (struct in6_addr *)&ipv6_full_mask)) + new_mask |= i40e_l3_v6_dst_mask; + else if (ipv6_addr_any((struct in6_addr *) + &tcp_ip6_spec->ip6src)) + new_mask &= ~i40e_l3_v6_dst_mask; + else + return -eopnotsupp; + + /* l4 source port */ + if (tcp_ip6_spec->psrc == htons(0xffff)) + new_mask |= i40e_l4_src_mask; + else if (!tcp_ip6_spec->psrc) + new_mask &= ~i40e_l4_src_mask; + else + return -eopnotsupp; + + /* l4 destination port */ + if (tcp_ip6_spec->pdst == htons(0xffff)) + new_mask |= i40e_l4_dst_mask; + else if (!tcp_ip6_spec->pdst) + new_mask &= ~i40e_l4_dst_mask; + else + return -eopnotsupp; + + /* filtering on traffic classes is not supported. */ + if (tcp_ip6_spec->tclass) + return -eopnotsupp; + break; + break; + case ipv6_user_flow: + usr_ip6_spec = &fsp->m_u.usr_ip6_spec; + + /* check if user provided ipv6 source address. */ + if (ipv6_addr_equal((struct in6_addr *)&usr_ip6_spec->ip6src, + (struct in6_addr *)&ipv6_full_mask)) + new_mask |= i40e_l3_v6_src_mask; + else if (ipv6_addr_any((struct in6_addr *) + &usr_ip6_spec->ip6src)) + new_mask &= ~i40e_l3_v6_src_mask; + else + return -eopnotsupp; + + /* check if user provided destination address. */ + if (ipv6_addr_equal((struct in6_addr *)&usr_ip6_spec->ip6dst, + (struct in6_addr *)&ipv6_full_mask)) + new_mask |= i40e_l3_v6_dst_mask; + else if (ipv6_addr_any((struct in6_addr *) + &usr_ip6_spec->ip6src)) + new_mask &= ~i40e_l3_v6_dst_mask; + else + return -eopnotsupp; + + if (usr_ip6_spec->l4_4_bytes == htonl(0xffffffff)) + new_mask |= i40e_l4_src_mask | i40e_l4_dst_mask; + else if (!usr_ip6_spec->l4_4_bytes) + new_mask &= ~(i40e_l4_src_mask | i40e_l4_dst_mask); + else + return -eopnotsupp; + + /* filtering on traffic class is not supported. */ + if (usr_ip6_spec->tclass) + return -eopnotsupp; + + /* filtering on l4 protocol is not supported */ + if (usr_ip6_spec->l4_proto) + return -einval; + - a->ip4_proto != b->ip4_proto) + a->ipl4_proto != b->ipl4_proto) - input->ip4_proto = fsp->h_u.usr_ip4_spec.proto; - /* reverse the src and dest notion, since the hw expects them to be from - * tx perspective where as the input from user is from rx filter view. - */ - input->dst_port = fsp->h_u.tcp_ip4_spec.psrc; - input->src_port = fsp->h_u.tcp_ip4_spec.pdst; - input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src; - input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst; + if (input->flow_type == ipv6_user_flow || + input->flow_type == udp_v6_flow || + input->flow_type == tcp_v6_flow || + input->flow_type == sctp_v6_flow) { + /* reverse the src and dest notion, since the hw expects them + * to be from tx perspective where as the input from user is + * from rx filter view. + */ + input->ipl4_proto = fsp->h_u.usr_ip6_spec.l4_proto; + input->dst_port = fsp->h_u.tcp_ip6_spec.psrc; + input->src_port = fsp->h_u.tcp_ip6_spec.pdst; + memcpy(input->dst_ip6, fsp->h_u.ah_ip6_spec.ip6src, + sizeof(__be32) * 4); + memcpy(input->src_ip6, fsp->h_u.ah_ip6_spec.ip6dst, + sizeof(__be32) * 4); + } else { + /* reverse the src and dest notion, since the hw expects them + * to be from tx perspective where as the input from user is + * from rx filter view. + */ + input->ipl4_proto = fsp->h_u.usr_ip4_spec.proto; + input->dst_port = fsp->h_u.tcp_ip4_spec.psrc; + input->src_port = fsp->h_u.tcp_ip4_spec.pdst; + input->dst_ip = fsp->h_u.tcp_ip4_spec.ip4src; + input->src_ip = fsp->h_u.tcp_ip4_spec.ip4dst; + } diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c +/** + * i40e_reset_fdir_filter_cnt - reset flow director filter counters + * @pf: pointer to the targeted pf + * + * set all flow director counters to 0. + */ +static void i40e_reset_fdir_filter_cnt(struct i40e_pf *pf) +{ + pf->fd_tcp4_filter_cnt = 0; + pf->fd_udp4_filter_cnt = 0; + pf->fd_sctp4_filter_cnt = 0; + pf->fd_ip4_filter_cnt = 0; + pf->fd_tcp6_filter_cnt = 0; + pf->fd_udp6_filter_cnt = 0; + pf->fd_sctp6_filter_cnt = 0; + pf->fd_ip6_filter_cnt = 0; +} + - pf->fd_tcp4_filter_cnt = 0; - pf->fd_udp4_filter_cnt = 0; - pf->fd_sctp4_filter_cnt = 0; - pf->fd_ip4_filter_cnt = 0; + i40e_reset_fdir_filter_cnt(pf); - pf->fd_tcp4_filter_cnt = 0; - pf->fd_udp4_filter_cnt = 0; - pf->fd_sctp4_filter_cnt = 0; - pf->fd_ip4_filter_cnt = 0; + i40e_reset_fdir_filter_cnt(pf); + /* reprogram the default input set for tcp/ipv6 */ + i40e_write_fd_input_set(pf, i40e_filter_pctype_nonf_ipv6_tcp, + i40e_l3_v6_src_mask | i40e_l3_v6_dst_mask | + i40e_l4_src_mask | i40e_l4_dst_mask); + + /* reprogram the default input set for udp/ipv6 */ + i40e_write_fd_input_set(pf, i40e_filter_pctype_nonf_ipv6_udp, + i40e_l3_v6_src_mask | i40e_l3_v6_dst_mask | + i40e_l4_src_mask | i40e_l4_dst_mask); + + /* reprogram the default input set for sctp/ipv6 */ + i40e_write_fd_input_set(pf, i40e_filter_pctype_nonf_ipv6_sctp, + i40e_l3_v6_src_mask | i40e_l3_v6_dst_mask | + i40e_l4_src_mask | i40e_l4_dst_mask); + + + /* reprogram the default input set for other/ipv6 */ + i40e_write_fd_input_set(pf, i40e_filter_pctype_nonf_ipv6_other, + i40e_l3_src_mask | i40e_l3_dst_mask); + + i40e_write_fd_input_set(pf, i40e_filter_pctype_frag_ipv6, + i40e_l3_src_mask | i40e_l3_dst_mask); + case tcp_v6_flow: + pf->fd_tcp6_filter_cnt--; + break; + case udp_v6_flow: + pf->fd_udp6_filter_cnt--; + break; + case sctp_v6_flow: + pf->fd_udp6_filter_cnt--; + break; - switch (filter->ip4_proto) { + switch (filter->ipl4_proto) { + case ipv6_user_flow: + switch (filter->ipl4_proto) { + case ipproto_tcp: + pf->fd_tcp6_filter_cnt--; + break; + case ipproto_udp: + pf->fd_udp6_filter_cnt--; + break; + case ipproto_sctp: + pf->fd_sctp6_filter_cnt--; + break; + case ipproto_ip: + pf->fd_ip6_filter_cnt--; + break; + } + break; - (pf->fd_tcp4_filter_cnt == 0)) + pf->fd_tcp4_filter_cnt == 0 && pf->fd_tcp6_filter_cnt == 0) diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c - flex_ptype |= i40e_txd_fltr_qw0_pctype_mask & - (fdata->flex_offset << i40e_txd_fltr_qw0_flexoff_shift); - -#define ip_header_offset 14 -#define i40e_udpip_dummy_packet_len 42 +#define ip_header_offset 14 +#define i40e_udpip_dummy_packet_len 42 +#define i40e_udpip6_dummy_packet_len 62 - * i40e_add_del_fdir_udpv4 - add/remove udpv4 filters + * i40e_add_del_fdir_udp - add/remove udp filters + * @ipv4: true is v4, false is v6 -static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi, - struct i40e_fdir_filter *fd_data, - bool add) +static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi, + struct i40e_fdir_filter *fd_data, + bool add, + bool ipv4) + struct ipv6hdr *ipv6; - static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, - 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, + 0, 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, + 0xdd, 0x60, 0, 0, 0, 0, 0, 0x11, 0, + /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /*udp header*/ + 0, 0, 0, 0, 0, 0, 0, 0}; - memcpy(raw_packet, packet, i40e_udpip_dummy_packet_len); + if (ipv4) { + memcpy(raw_packet, packet_ipv4, i40e_udpip_dummy_packet_len); - ip = (struct iphdr *)(raw_packet + ip_header_offset); - udp = (struct udphdr *)(raw_packet + ip_header_offset - + sizeof(struct iphdr)); + ip = (struct iphdr *)(raw_packet + ip_header_offset); + udp = (struct udphdr *)(raw_packet + ip_header_offset + + sizeof(struct iphdr)); - ip->daddr = fd_data->dst_ip; + ip->daddr = fd_data->dst_ip; + ip->saddr = fd_data->src_ip; + } else { + memcpy(raw_packet, packet_ipv6, i40e_udpip6_dummy_packet_len); + ipv6 = (struct ipv6hdr *)(raw_packet + ip_header_offset); + udp = (struct udphdr *)(raw_packet + ip_header_offset + + sizeof(struct ipv6hdr)); + + memcpy(ipv6->saddr.in6_u.u6_addr32, + fd_data->src_ip6, sizeof(__be32) * 4); + memcpy(ipv6->daddr.in6_u.u6_addr32, + fd_data->dst_ip6, sizeof(__be32) * 4); + } - ip->saddr = fd_data->src_ip; - u8 *payload = raw_packet + i40e_udpip_dummy_packet_len; + u8 *payload; + if (ipv4) + payload = raw_packet + i40e_udpip_dummy_packet_len; + else + payload = raw_packet + i40e_udpip6_dummy_packet_len; + - fd_data->pctype = i40e_filter_pctype_nonf_ipv4_udp; + if (ipv4) + fd_data->pctype = i40e_filter_pctype_nonf_ipv4_udp; + else + fd_data->pctype = i40e_filter_pctype_nonf_ipv6_udp; + - if (add) - pf->fd_udp4_filter_cnt++; - else - pf->fd_udp4_filter_cnt--; + if (add) { + if (ipv4) + pf->fd_udp4_filter_cnt++; + else + pf->fd_udp6_filter_cnt++; + } else { + if (ipv4) + pf->fd_udp4_filter_cnt--; + else + pf->fd_udp6_filter_cnt--; + } -#define i40e_tcpip_dummy_packet_len 54 +#define i40e_tcpip_dummy_packet_len 54 +#define i40e_tcpip6_dummy_packet_len 74 - * i40e_add_del_fdir_tcpv4 - add/remove tcpv4 filters + * i40e_add_del_fdir_tcp - add/remove tcpv4 filters + * @ipv4: true is v4, false is v6 -static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi, - struct i40e_fdir_filter *fd_data, - bool add) +static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi, + struct i40e_fdir_filter *fd_data, + bool add, + bool ipv4) + struct ipv6hdr *ipv6; - static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, - 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11, + static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, + 0, 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x50, 0x11, + 0x0, 0x72, 0, 0, 0, 0}; + static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, + 0xdd, 0x60, 0, 0, 0, 0, 0, 0x6, 0, + /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x50, 0x11, - memcpy(raw_packet, packet, i40e_tcpip_dummy_packet_len); + if (ipv4) { + memcpy(raw_packet, packet_ipv4, i40e_tcpip_dummy_packet_len); + + ip = (struct iphdr *)(raw_packet + ip_header_offset); + tcp = (struct tcphdr *)(raw_packet + ip_header_offset + + sizeof(struct iphdr)); + + ip->daddr = fd_data->dst_ip; + ip->saddr = fd_data->src_ip; + } else { + memcpy(raw_packet, packet_ipv6, i40e_tcpip6_dummy_packet_len); + + tcp = (struct tcphdr *)(raw_packet + ip_header_offset + + sizeof(struct ipv6hdr)); + ipv6 = (struct ipv6hdr *)(raw_packet + ip_header_offset); + + memcpy(ipv6->saddr.in6_u.u6_addr32, + fd_data->src_ip6, sizeof(__be32) * 4); + memcpy(ipv6->daddr.in6_u.u6_addr32, + fd_data->dst_ip6, sizeof(__be32) * 4); + } + sizeof(struct iphdr)); - ip->daddr = fd_data->dst_ip; - ip->saddr = fd_data->src_ip; - u8 *payload = raw_packet + i40e_tcpip_dummy_packet_len; + u8 *payload; + if (ipv4) + payload = raw_packet + i40e_tcpip_dummy_packet_len; + else + payload = raw_packet + i40e_tcpip6_dummy_packet_len; + - fd_data->pctype = i40e_filter_pctype_nonf_ipv4_tcp; + if (ipv4) + fd_data->pctype = i40e_filter_pctype_nonf_ipv4_tcp; + else + fd_data->pctype = i40e_filter_pctype_nonf_ipv6_tcp; - pf->fd_tcp4_filter_cnt++; + if (ipv4) + pf->fd_tcp4_filter_cnt++; + else + pf->fd_tcp6_filter_cnt++; - pf->fd_tcp4_filter_cnt--; + if (ipv4) + pf->fd_tcp4_filter_cnt--; + else + pf->fd_tcp6_filter_cnt--; -#define i40e_sctpip_dummy_packet_len 46 +#define i40e_sctpip_dummy_packet_len 46 +#define i40e_sctpip6_dummy_packet_len 66 - * i40e_add_del_fdir_sctpv4 - add/remove sctpv4 flow director filters for + * i40e_add_del_fdir_sctp - add/remove sctpv4 flow director filters for + * @ipv4: true is v4, false is v6 -static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi, - struct i40e_fdir_filter *fd_data, - bool add) +static int i40e_add_del_fdir_sctp(struct i40e_vsi *vsi, + struct i40e_fdir_filter *fd_data, + bool add, + bool ipv4) + struct ipv6hdr *ipv6; - /* dummy packet */ - static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, - 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - + /* dummy packets */ + static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, + 0, 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, + 0xdd, 0x60, 0, 0, 0, 0, 0, 0x84, 0, + /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - memcpy(raw_packet, packet, i40e_sctpip_dummy_packet_len); + if (ipv4) { + memcpy(raw_packet, packet_ipv4, i40e_sctpip_dummy_packet_len); - ip = (struct iphdr *)(raw_packet + ip_header_offset); - sctp = (struct sctphdr *)(raw_packet + ip_header_offset - + sizeof(struct iphdr)); + ip = (struct iphdr *)(raw_packet + ip_header_offset); + sctp = (struct sctphdr *)(raw_packet + ip_header_offset + + sizeof(struct iphdr)); + + ip->daddr = fd_data->dst_ip; + ip->saddr = fd_data->src_ip; + } else { + memcpy(raw_packet, packet_ipv6, i40e_sctpip6_dummy_packet_len); + + ipv6 = (struct ipv6hdr *)(raw_packet + ip_header_offset); + sctp = (struct sctphdr *)(raw_packet + ip_header_offset + + sizeof(struct ipv6hdr)); + + memcpy(ipv6->saddr.in6_u.u6_addr32, + fd_data->src_ip6, sizeof(__be32) * 4); + memcpy(ipv6->saddr.in6_u.u6_addr32, + fd_data->src_ip6, sizeof(__be32) * 4); + } - ip->daddr = fd_data->dst_ip; - ip->saddr = fd_data->src_ip; - u8 *payload = raw_packet + i40e_sctpip_dummy_packet_len; + u8 *payload; + if (ipv4) + payload = raw_packet + i40e_sctpip_dummy_packet_len; + else + payload = raw_packet + i40e_sctpip6_dummy_packet_len; - fd_data->pctype = i40e_filter_pctype_nonf_ipv4_sctp; + if (ipv4) + fd_data->pctype = i40e_filter_pctype_nonf_ipv4_sctp; + else + fd_data->pctype = i40e_filter_pctype_nonf_ipv6_sctp; + - if (add) - pf->fd_sctp4_filter_cnt++; - else - pf->fd_sctp4_filter_cnt--; + if (add) { + if (ipv4) + pf->fd_sctp4_filter_cnt++; + else + pf->fd_sctp6_filter_cnt++; + } else { + if (ipv4) + pf->fd_sctp4_filter_cnt--; + else + pf->fd_sctp6_filter_cnt--; + } -#define i40e_ip_dummy_packet_len 34 +#define i40e_ip_dummy_packet_len 34 +#define i40e_ip6_dummy_packet_len 54 - * i40e_add_del_fdir_ipv4 - add/remove ipv4 flow director filters for + * i40e_add_del_fdir_ip - add/remove ipv4 flow director filters for + * @ipv4: true is v4, false is v6 -static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi, - struct i40e_fdir_filter *fd_data, - bool add) +static int i40e_add_del_fdir_ip(struct i40e_vsi *vsi, + struct i40e_fdir_filter *fd_data, + bool add, + bool ipv4) + struct ipv6hdr *ipv6; + int iter_start; + int iter_end; - static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0, - 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0}; + static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, + 0, 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0}; + static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, + 0xdd, 0x60, 0, 0, 0, 0, 0, 0, 0, + /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + if (ipv4) { + iter_start = i40e_filter_pctype_nonf_ipv4_other; + iter_end = i40e_filter_pctype_frag_ipv4; + } else { + iter_start = i40e_filter_pctype_nonf_ipv6_other; + iter_end = i40e_filter_pctype_frag_ipv6; + } - for (i = i40e_filter_pctype_nonf_ipv4_other; - i <= i40e_filter_pctype_frag_ipv4; i++) { + for (i = iter_start; i <= iter_end; i++) { - memcpy(raw_packet, packet, i40e_ip_dummy_packet_len); - ip = (struct iphdr *)(raw_packet + ip_header_offset); - - ip->saddr = fd_data->src_ip; - ip->daddr = fd_data->dst_ip; - ip->protocol = 0; + if (ipv4) { + memcpy(raw_packet, packet_ipv4, + i40e_ip_dummy_packet_len); + ip = (struct iphdr *)(raw_packet + ip_header_offset); + + ip->saddr = fd_data->src_ip; + ip->daddr = fd_data->dst_ip; + ip->protocol = ipproto_ip; + } else { + memcpy(raw_packet, packet_ipv6, + i40e_ip6_dummy_packet_len); + ipv6 = (struct ipv6hdr *)(raw_packet + + ip_header_offset); + memcpy(ipv6->saddr.in6_u.u6_addr32, + fd_data->src_ip6, sizeof(__be32) * 4); + memcpy(ipv6->daddr.in6_u.u6_addr32, + fd_data->dst_ip6, sizeof(__be32) * 4); + + ipv6->nexthdr = ipproto_none; + } - u8 *payload = raw_packet + i40e_ip_dummy_packet_len; + u8 *payload; + if (ipv4) + payload = raw_packet + i40e_ip_dummy_packet_len; + else + payload = raw_packet + + i40e_ip6_dummy_packet_len; - if (add) - pf->fd_ip4_filter_cnt++; - else - pf->fd_ip4_filter_cnt--; + if (add) { + if (ipv4) + pf->fd_ip4_filter_cnt++; + else + pf->fd_ip6_filter_cnt++; + } else { + if (ipv4) + pf->fd_ip4_filter_cnt--; + else + pf->fd_ip6_filter_cnt--; + } + enum ip_ver { ipv6 = 0, ipv4 = 1 }; - ret = i40e_add_del_fdir_tcpv4(vsi, input, add); + ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); - ret = i40e_add_del_fdir_udpv4(vsi, input, add); + ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); - ret = i40e_add_del_fdir_sctpv4(vsi, input, add); + ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); + break; + case tcp_v6_flow: + ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); + break; + case udp_v6_flow: + ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); + break; + case sctp_v6_flow: + ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); - switch (input->ip4_proto) { + switch (input->ipl4_proto) { - ret = i40e_add_del_fdir_tcpv4(vsi, input, add); + ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv4); - ret = i40e_add_del_fdir_udpv4(vsi, input, add); + ret = i40e_add_del_fdir_udp(vsi, input, add, ipv4); - ret = i40e_add_del_fdir_sctpv4(vsi, input, add); + ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv4); - ret = i40e_add_del_fdir_ipv4(vsi, input, add); + ret = i40e_add_del_fdir_ip(vsi, input, add, ipv4); - input->ip4_proto); + input->ipl4_proto); + return -einval; + } + break; + case ipv6_user_flow: + switch (input->ipl4_proto) { + case ipproto_tcp: + ret = i40e_add_del_fdir_tcp(vsi, input, add, ipv6); + break; + case ipproto_udp: + ret = i40e_add_del_fdir_udp(vsi, input, add, ipv6); + break; + case ipproto_sctp: + ret = i40e_add_del_fdir_sctp(vsi, input, add, ipv6); + break; + case ipproto_ip: + ret = i40e_add_del_fdir_ip(vsi, input, add, ipv6); + break; + default: + /* we cannot support masking based on protocol */ + dev_info(&pf->pdev->dev, "unsupported ipv6 protocol 0x%02x ", + input->ipl4_proto);
|
Networking
|
efca91e89b67a6f824aca6abcd8a2e5188aa061c
|
przemyslaw patynowski
|
drivers
|
net
|
ethernet, i40e, intel
|
i40e: vlan field for flow director
|
allow user to specify vlan field and add it to flow director. show vlan field in "ethtool -n ethx" command. handle vlan type and tag field provided by ethtool command. refactored filter addition, by replacing static arrays with runtime dummy packet creation, which allows specifying vlan field. previously, vlan field was omitted.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
extend support for ntuple filters allowing for flow director ipv6 and vlan filters
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['i40e ']
|
['h', 'c']
| 4
| 289
| 292
|
--- diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h --- a/drivers/net/ethernet/intel/i40e/i40e.h +++ b/drivers/net/ethernet/intel/i40e/i40e.h + __be16 vlan_etype; + __be16 vlan_tag; diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c --- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c + if (rule->vlan_tag) { + fsp->h_ext.vlan_etype = rule->vlan_etype; + fsp->m_ext.vlan_etype = htons(0xffff); + fsp->h_ext.vlan_tci = rule->vlan_tag; + fsp->m_ext.vlan_tci = htons(0xffff); + fsp->flow_type |= flow_ext; + } + + if (fsp->flow_type & flow_ext) { + /* allow only 802.1q and no etype defined, as + * later it's modified to 0x8100 + */ + if (fsp->h_ext.vlan_etype != htons(eth_p_8021q) && + fsp->h_ext.vlan_etype != 0) + return -eopnotsupp; + if (fsp->m_ext.vlan_tci == htons(0xffff)) + new_mask |= i40e_vlan_src_mask; + else + new_mask &= ~i40e_vlan_src_mask; + } + - a->ipl4_proto != b->ipl4_proto) + a->ipl4_proto != b->ipl4_proto || + a->vlan_tag != b->vlan_tag || + a->vlan_etype != b->vlan_etype) + input->vlan_etype = fsp->h_ext.vlan_etype; + if (!fsp->m_ext.vlan_etype && fsp->h_ext.vlan_tci) + input->vlan_etype = cpu_to_be16(eth_p_8021q); + if (fsp->m_ext.vlan_tci && input->vlan_etype) + input->vlan_tag = fsp->h_ext.vlan_tci; diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c --- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c +++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c -#define ip_header_offset 14 -#define i40e_udpip_dummy_packet_len 42 -#define i40e_udpip6_dummy_packet_len 62 - * i40e_add_del_fdir_udp - add/remove udp filters - * @vsi: pointer to the targeted vsi - * @fd_data: the flow director data required for the fdir descriptor - * @add: true adds a filter, false removes it - * @ipv4: true is v4, false is v6 + * i40e_create_dummy_packet - constructs dummy packet for hw + * @dummy_packet: preallocated space for dummy packet + * @ipv4: is layer 3 packet of version 4 or 6 + * @l4proto: next level protocol used in data portion of l3 + * @data: filter data - * returns 0 if the filters were successfully added or removed + * returns address of layer 4 protocol dummy packet. -static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi, - struct i40e_fdir_filter *fd_data, - bool add, - bool ipv4) +static char *i40e_create_dummy_packet(u8 *dummy_packet, bool ipv4, u8 l4proto, + struct i40e_fdir_filter *data) - struct i40e_pf *pf = vsi->back; - struct ipv6hdr *ipv6; - struct udphdr *udp; - struct iphdr *ip; - u8 *raw_packet; - int ret; - static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, - 0, 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, - 0xdd, 0x60, 0, 0, 0, 0, 0, 0x11, 0, - /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /*udp header*/ - 0, 0, 0, 0, 0, 0, 0, 0}; + bool is_vlan = !!data->vlan_tag; + struct vlan_hdr vlan; + struct ipv6hdr ipv6; + struct ethhdr eth; + struct iphdr ip; + u8 *tmp; - raw_packet = kzalloc(i40e_fdir_max_raw_packet_size, gfp_kernel); - if (!raw_packet) - return -enomem; - memcpy(raw_packet, packet_ipv4, i40e_udpip_dummy_packet_len); + eth.h_proto = cpu_to_be16(eth_p_ip); + ip.protocol = l4proto; + ip.version = 0x4; + ip.ihl = 0x5; - ip = (struct iphdr *)(raw_packet + ip_header_offset); - udp = (struct udphdr *)(raw_packet + ip_header_offset - + sizeof(struct iphdr)); - - ip->daddr = fd_data->dst_ip; - ip->saddr = fd_data->src_ip; + ip.daddr = data->dst_ip; + ip.saddr = data->src_ip; - memcpy(raw_packet, packet_ipv6, i40e_udpip6_dummy_packet_len); - ipv6 = (struct ipv6hdr *)(raw_packet + ip_header_offset); - udp = (struct udphdr *)(raw_packet + ip_header_offset - + sizeof(struct ipv6hdr)); + eth.h_proto = cpu_to_be16(eth_p_ipv6); + ipv6.nexthdr = l4proto; + ipv6.version = 0x6; + + memcpy(&ipv6.saddr.in6_u.u6_addr32, data->src_ip6, + sizeof(__be32) * 4); + memcpy(&ipv6.daddr.in6_u.u6_addr32, data->dst_ip6, + sizeof(__be32) * 4); + } + + if (is_vlan) { + vlan.h_vlan_tci = data->vlan_tag; + vlan.h_vlan_encapsulated_proto = eth.h_proto; + eth.h_proto = data->vlan_etype; + } + + tmp = dummy_packet; + memcpy(tmp, ð, sizeof(eth)); + tmp += sizeof(eth); - memcpy(ipv6->saddr.in6_u.u6_addr32, - fd_data->src_ip6, sizeof(__be32) * 4); - memcpy(ipv6->daddr.in6_u.u6_addr32, - fd_data->dst_ip6, sizeof(__be32) * 4); + if (is_vlan) { + memcpy(tmp, &vlan, sizeof(vlan)); + tmp += sizeof(vlan); - udp->dest = fd_data->dst_port; - udp->source = fd_data->src_port; + + if (ipv4) { + memcpy(tmp, &ip, sizeof(ip)); + tmp += sizeof(ip); + } else { + memcpy(tmp, &ipv6, sizeof(ipv6)); + tmp += sizeof(ipv6); + } + + return tmp; +} + +/** + * i40e_create_dummy_udp_packet - helper function to create udp packet + * @raw_packet: preallocated space for dummy packet + * @ipv4: is layer 3 packet of version 4 or 6 + * @l4proto: next level protocol used in data portion of l3 + * @data: filter data + * + * helper function to populate udp fields. + **/ +static void i40e_create_dummy_udp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, + struct i40e_fdir_filter *data) +{ + struct udphdr *udp; + u8 *tmp; + + tmp = i40e_create_dummy_packet(raw_packet, ipv4, ipproto_udp, data); + udp = (struct udphdr *)(tmp); + udp->dest = data->dst_port; + udp->source = data->src_port; +} + +/** + * i40e_create_dummy_tcp_packet - helper function to create tcp packet + * @raw_packet: preallocated space for dummy packet + * @ipv4: is layer 3 packet of version 4 or 6 + * @l4proto: next level protocol used in data portion of l3 + * @data: filter data + * + * helper function to populate tcp fields. + **/ +static void i40e_create_dummy_tcp_packet(u8 *raw_packet, bool ipv4, u8 l4proto, + struct i40e_fdir_filter *data) +{ + struct tcphdr *tcp; + u8 *tmp; + /* dummy tcp packet */ + static const char tcp_packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0x50, 0x11, 0x0, 0x72, 0, 0, 0, 0}; + + tmp = i40e_create_dummy_packet(raw_packet, ipv4, ipproto_tcp, data); + + tcp = (struct tcphdr *)tmp; + memcpy(tcp, tcp_packet, sizeof(tcp_packet)); + tcp->dest = data->dst_port; + tcp->source = data->src_port; +} + +/** + * i40e_create_dummy_sctp_packet - helper function to create sctp packet + * @raw_packet: preallocated space for dummy packet + * @ipv4: is layer 3 packet of version 4 or 6 + * @l4proto: next level protocol used in data portion of l3 + * @data: filter data + * + * helper function to populate sctp fields. + **/ +static void i40e_create_dummy_sctp_packet(u8 *raw_packet, bool ipv4, + u8 l4proto, + struct i40e_fdir_filter *data) +{ + struct sctphdr *sctp; + u8 *tmp; + + tmp = i40e_create_dummy_packet(raw_packet, ipv4, ipproto_sctp, data); + + sctp = (struct sctphdr *)tmp; + sctp->dest = data->dst_port; + sctp->source = data->src_port; +} + +/** + * i40e_prepare_fdir_filter - prepare and program fdir filter + * @pf: physical function to attach filter to + * @fd_data: filter data + * @add: add or delete filter + * @packet_addr: address of dummy packet, used in filtering + * @payload_offset: offset from dummy packet address to user defined data + * @pctype: packet type for which filter is used + * + * helper function to offset data of dummy packet, program it and + * handle errors. + **/ +static int i40e_prepare_fdir_filter(struct i40e_pf *pf, + struct i40e_fdir_filter *fd_data, + bool add, char *packet_addr, + int payload_offset, u8 pctype) +{ + int ret; - if (ipv4) - payload = raw_packet + i40e_udpip_dummy_packet_len; - else - payload = raw_packet + i40e_udpip6_dummy_packet_len; + payload = packet_addr + payload_offset; + + /* if user provided vlan, offset payload by vlan header length */ + if (!!fd_data->vlan_tag) + payload += vlan_hlen; - if (ipv4) - fd_data->pctype = i40e_filter_pctype_nonf_ipv4_udp; - else - fd_data->pctype = i40e_filter_pctype_nonf_ipv6_udp; - - ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); + fd_data->pctype = pctype; + ret = i40e_program_fdir_filter(fd_data, packet_addr, pf, add); - kfree(raw_packet); + return ret; +} + +/** + * i40e_change_filter_num - prepare and program fdir filter + * @ipv4: is layer 3 packet of version 4 or 6 + * @add: add or delete filter + * @ipv4_filter_num: field to update + * @ipv6_filter_num: field to update + * + * update filter number field for pf. + **/ +static void i40e_change_filter_num(bool ipv4, bool add, u16 *ipv4_filter_num, + u16 *ipv6_filter_num) +{ - pf->fd_udp4_filter_cnt++; + (*ipv4_filter_num)++; - pf->fd_udp6_filter_cnt++; + (*ipv6_filter_num)++; - pf->fd_udp4_filter_cnt--; + (*ipv4_filter_num)--; - pf->fd_udp6_filter_cnt--; + (*ipv6_filter_num)--; - - return 0; -#define i40e_tcpip_dummy_packet_len 54 -#define i40e_tcpip6_dummy_packet_len 74 +#define ip_header_offset 14 +#define i40e_udpip_dummy_packet_len 42 +#define i40e_udpip6_dummy_packet_len 62 - * i40e_add_del_fdir_tcp - add/remove tcpv4 filters + * i40e_add_del_fdir_udp - add/remove udp filters -static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi, +static int i40e_add_del_fdir_udp(struct i40e_vsi *vsi, - struct ipv6hdr *ipv6; - struct tcphdr *tcp; - struct iphdr *ip; - /* dummy packet */ - static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, - 0, 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x50, 0x11, - 0x0, 0x72, 0, 0, 0, 0}; - static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, - 0xdd, 0x60, 0, 0, 0, 0, 0, 0x6, 0, - /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x50, 0x11, - 0x0, 0x72, 0, 0, 0, 0}; - if (ipv4) { - memcpy(raw_packet, packet_ipv4, i40e_tcpip_dummy_packet_len); - ip = (struct iphdr *)(raw_packet + ip_header_offset); - tcp = (struct tcphdr *)(raw_packet + ip_header_offset - + sizeof(struct iphdr)); + i40e_create_dummy_udp_packet(raw_packet, ipv4, ipproto_udp, fd_data); - ip->daddr = fd_data->dst_ip; - ip->saddr = fd_data->src_ip; - } else { - memcpy(raw_packet, packet_ipv6, i40e_tcpip6_dummy_packet_len); - - tcp = (struct tcphdr *)(raw_packet + ip_header_offset - + sizeof(struct ipv6hdr)); - ipv6 = (struct ipv6hdr *)(raw_packet + ip_header_offset); + if (ipv4) + ret = i40e_prepare_fdir_filter + (pf, fd_data, add, raw_packet, + i40e_udpip_dummy_packet_len, + i40e_filter_pctype_nonf_ipv4_udp); + else + ret = i40e_prepare_fdir_filter + (pf, fd_data, add, raw_packet, + i40e_udpip6_dummy_packet_len, + i40e_filter_pctype_nonf_ipv6_udp); - memcpy(ipv6->saddr.in6_u.u6_addr32, - fd_data->src_ip6, sizeof(__be32) * 4); - memcpy(ipv6->daddr.in6_u.u6_addr32, - fd_data->dst_ip6, sizeof(__be32) * 4); + if (ret) { + kfree(raw_packet); + return ret; - ip = (struct iphdr *)(raw_packet + ip_header_offset); - tcp = (struct tcphdr *)(raw_packet + ip_header_offset - + sizeof(struct iphdr)); + i40e_change_filter_num(ipv4, add, &pf->fd_udp4_filter_cnt, + &pf->fd_udp6_filter_cnt); - tcp->dest = fd_data->dst_port; - tcp->source = fd_data->src_port; - - if (fd_data->flex_filter) { - u8 *payload; - __be16 pattern = fd_data->flex_word; - u16 off = fd_data->flex_offset; + return 0; +} - if (ipv4) - payload = raw_packet + i40e_tcpip_dummy_packet_len; - else - payload = raw_packet + i40e_tcpip6_dummy_packet_len; +#define i40e_tcpip_dummy_packet_len 54 +#define i40e_tcpip6_dummy_packet_len 74 +/** + * i40e_add_del_fdir_tcp - add/remove tcpv4 filters + * @vsi: pointer to the targeted vsi + * @fd_data: the flow director data required for the fdir descriptor + * @add: true adds a filter, false removes it + * @ipv4: true is v4, false is v6 + * + * returns 0 if the filters were successfully added or removed + **/ +static int i40e_add_del_fdir_tcp(struct i40e_vsi *vsi, + struct i40e_fdir_filter *fd_data, + bool add, + bool ipv4) +{ + struct i40e_pf *pf = vsi->back; + u8 *raw_packet; + int ret; - *((__force __be16 *)(payload + off)) = pattern; - } + raw_packet = kzalloc(i40e_fdir_max_raw_packet_size, gfp_kernel); + if (!raw_packet) + return -enomem; + i40e_create_dummy_tcp_packet(raw_packet, ipv4, ipproto_tcp, fd_data); - fd_data->pctype = i40e_filter_pctype_nonf_ipv4_tcp; + ret = i40e_prepare_fdir_filter + (pf, fd_data, add, raw_packet, + i40e_tcpip_dummy_packet_len, + i40e_filter_pctype_nonf_ipv4_tcp); - fd_data->pctype = i40e_filter_pctype_nonf_ipv6_tcp; - ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); + ret = i40e_prepare_fdir_filter + (pf, fd_data, add, raw_packet, + i40e_tcpip6_dummy_packet_len, + i40e_filter_pctype_nonf_ipv6_tcp); + - dev_info(&pf->pdev->dev, - "pctype:%d, filter command send failed for fd_id:%d (ret = %d) ", - fd_data->pctype, fd_data->fd_id, ret); - /* free the packet buffer since it wasn't added to the ring */ - return -eopnotsupp; - } else if (i40e_debug_fd & pf->hw.debug_mask) { - if (add) - dev_info(&pf->pdev->dev, "filter ok for pctype %d loc = %d) ", - fd_data->pctype, fd_data->fd_id); - else - dev_info(&pf->pdev->dev, - "filter deleted for pctype %d loc = %d ", - fd_data->pctype, fd_data->fd_id); + return ret; + i40e_change_filter_num(ipv4, add, &pf->fd_tcp4_filter_cnt, + &pf->fd_tcp6_filter_cnt); + - if (ipv4) - pf->fd_tcp4_filter_cnt++; - else - pf->fd_tcp6_filter_cnt++; - } else { - if (ipv4) - pf->fd_tcp4_filter_cnt--; - else - pf->fd_tcp6_filter_cnt--; - - struct ipv6hdr *ipv6; - struct sctphdr *sctp; - struct iphdr *ip; - /* dummy packets */ - static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, - 0, 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - - static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, - 0xdd, 0x60, 0, 0, 0, 0, 0, 0x84, 0, - /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + - if (ipv4) { - memcpy(raw_packet, packet_ipv4, i40e_sctpip_dummy_packet_len); - - ip = (struct iphdr *)(raw_packet + ip_header_offset); - sctp = (struct sctphdr *)(raw_packet + ip_header_offset - + sizeof(struct iphdr)); - ip->daddr = fd_data->dst_ip; - ip->saddr = fd_data->src_ip; - } else { - memcpy(raw_packet, packet_ipv6, i40e_sctpip6_dummy_packet_len); - - ipv6 = (struct ipv6hdr *)(raw_packet + ip_header_offset); - sctp = (struct sctphdr *)(raw_packet + ip_header_offset - + sizeof(struct ipv6hdr)); - - memcpy(ipv6->saddr.in6_u.u6_addr32, - fd_data->src_ip6, sizeof(__be32) * 4); - memcpy(ipv6->saddr.in6_u.u6_addr32, - fd_data->src_ip6, sizeof(__be32) * 4); - } - - sctp->dest = fd_data->dst_port; - sctp->source = fd_data->src_port; - - if (fd_data->flex_filter) { - u8 *payload; - __be16 pattern = fd_data->flex_word; - u16 off = fd_data->flex_offset; - - if (ipv4) - payload = raw_packet + i40e_sctpip_dummy_packet_len; - else - payload = raw_packet + i40e_sctpip6_dummy_packet_len; - *((__force __be16 *)(payload + off)) = pattern; - } + i40e_create_dummy_sctp_packet(raw_packet, ipv4, ipproto_sctp, fd_data); - fd_data->pctype = i40e_filter_pctype_nonf_ipv4_sctp; + ret = i40e_prepare_fdir_filter + (pf, fd_data, add, raw_packet, + i40e_sctpip_dummy_packet_len, + i40e_filter_pctype_nonf_ipv4_sctp); - fd_data->pctype = i40e_filter_pctype_nonf_ipv6_sctp; + ret = i40e_prepare_fdir_filter + (pf, fd_data, add, raw_packet, + i40e_sctpip6_dummy_packet_len, + i40e_filter_pctype_nonf_ipv6_sctp); - ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); - dev_info(&pf->pdev->dev, - "pctype:%d, filter command send failed for fd_id:%d (ret = %d) ", - fd_data->pctype, fd_data->fd_id, ret); - /* free the packet buffer since it wasn't added to the ring */ - return -eopnotsupp; - } else if (i40e_debug_fd & pf->hw.debug_mask) { - if (add) - dev_info(&pf->pdev->dev, - "filter ok for pctype %d loc = %d ", - fd_data->pctype, fd_data->fd_id); - else - dev_info(&pf->pdev->dev, - "filter deleted for pctype %d loc = %d ", - fd_data->pctype, fd_data->fd_id); + return ret; - if (add) { - if (ipv4) - pf->fd_sctp4_filter_cnt++; - else - pf->fd_sctp6_filter_cnt++; - } else { - if (ipv4) - pf->fd_sctp4_filter_cnt--; - else - pf->fd_sctp6_filter_cnt--; - } + i40e_change_filter_num(ipv4, add, &pf->fd_sctp4_filter_cnt, + &pf->fd_sctp6_filter_cnt); - struct ipv6hdr *ipv6; - struct iphdr *ip; + int payload_offset; - static char packet_ipv4[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, - 0, 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0}; - static char packet_ipv6[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x86, - 0xdd, 0x60, 0, 0, 0, 0, 0, 0, 0, - /*src address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - /*dst address*/0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; - if (ipv4) { - memcpy(raw_packet, packet_ipv4, - i40e_ip_dummy_packet_len); - ip = (struct iphdr *)(raw_packet + ip_header_offset); - - ip->saddr = fd_data->src_ip; - ip->daddr = fd_data->dst_ip; - ip->protocol = ipproto_ip; - } else { - memcpy(raw_packet, packet_ipv6, - i40e_ip6_dummy_packet_len); - ipv6 = (struct ipv6hdr *)(raw_packet + - ip_header_offset); - memcpy(ipv6->saddr.in6_u.u6_addr32, - fd_data->src_ip6, sizeof(__be32) * 4); - memcpy(ipv6->daddr.in6_u.u6_addr32, - fd_data->dst_ip6, sizeof(__be32) * 4); - - ipv6->nexthdr = ipproto_none; - } - if (fd_data->flex_filter) { - u8 *payload; - __be16 pattern = fd_data->flex_word; - u16 off = fd_data->flex_offset; - - if (ipv4) - payload = raw_packet + i40e_ip_dummy_packet_len; - else - payload = raw_packet + - i40e_ip6_dummy_packet_len; - *((__force __be16 *)(payload + off)) = pattern; - } + /* ipv6 no header option differs from ipv4 */ + (void)i40e_create_dummy_packet + (raw_packet, ipv4, (ipv4) ? ipproto_ip : ipproto_none, + fd_data); - fd_data->pctype = i; - ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add); - if (ret) { - dev_info(&pf->pdev->dev, - "pctype:%d, filter command send failed for fd_id:%d (ret = %d) ", - fd_data->pctype, fd_data->fd_id, ret); - /* the packet buffer wasn't added to the ring so we - * need to free it now. - */ - kfree(raw_packet); - return -eopnotsupp; - } else if (i40e_debug_fd & pf->hw.debug_mask) { - if (add) - dev_info(&pf->pdev->dev, - "filter ok for pctype %d loc = %d ", - fd_data->pctype, fd_data->fd_id); - else - dev_info(&pf->pdev->dev, - "filter deleted for pctype %d loc = %d ", - fd_data->pctype, fd_data->fd_id); - } + payload_offset = (ipv4) ? i40e_ip_dummy_packet_len : + i40e_ip6_dummy_packet_len; + ret = i40e_prepare_fdir_filter(pf, fd_data, add, raw_packet, + payload_offset, i); + if (ret) + goto err; - if (add) { - if (ipv4) - pf->fd_ip4_filter_cnt++; - else - pf->fd_ip6_filter_cnt++; - } else { - if (ipv4) - pf->fd_ip4_filter_cnt--; - else - pf->fd_ip6_filter_cnt--; - } + i40e_change_filter_num(ipv4, add, &pf->fd_ip4_filter_cnt, + &pf->fd_ip6_filter_cnt); +err: + kfree(raw_packet); + return ret; diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h --- a/drivers/net/ethernet/intel/i40e/i40e_type.h +++ b/drivers/net/ethernet/intel/i40e/i40e_type.h +#define i40e_vlan_src_shift 55 +#define i40e_vlan_src_mask (0x1ull << i40e_vlan_src_shift)
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Networking
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a9219b332f52093dbf9dae5219e820065f9e2cf6
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przemyslaw patynowski tony brelinski tonyx brelinski intel com
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drivers
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net
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ethernet, i40e, intel
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i40e: add hardware configuration for software based dcb
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add registers and definitions required for applying dcb related hardware configuration.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add support for software controlled dcb
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['i40e ']
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['h', 'c']
| 7
| 1,365
| 13
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--- diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h --- a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h +++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +#define i40e_aqc_add_control_packet_flags_rx 0x0000 +#define set_local_mib_ac_type_dcbx_shift 0 +#define set_local_mib_ac_type_dcbx_mask (1 << \ + set_local_mib_ac_type_dcbx_shift) +#define set_local_mib_ac_type_local_mib 0x0 +#define set_local_mib_ac_type_non_willing_apps_shift (1) +#define set_local_mib_ac_type_non_willing_apps_mask (1 << \ + set_local_mib_ac_type_non_willing_apps_shift) +#define set_local_mib_ac_type_non_willing_apps 0x1 diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c --- a/drivers/net/ethernet/intel/i40e/i40e_common.c +++ b/drivers/net/ethernet/intel/i40e/i40e_common.c -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +/** + * i40e_aq_set_lldp_mib - set the lldp mib + * @hw: pointer to the hw struct + * @mib_type: local, remote or both local and remote mibs + * @buff: pointer to a user supplied buffer to store the mib block + * @buff_size: size of the buffer (in bytes) + * @cmd_details: pointer to command details structure or null + * + * set the lldp mib. + **/ +enum i40e_status_code +i40e_aq_set_lldp_mib(struct i40e_hw *hw, + u8 mib_type, void *buff, u16 buff_size, + struct i40e_asq_cmd_details *cmd_details) +{ + struct i40e_aqc_lldp_set_local_mib *cmd; + enum i40e_status_code status; + struct i40e_aq_desc desc; + + cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw; + if (buff_size == 0 || !buff) + return i40e_err_param; + + i40e_fill_default_direct_cmd_desc(&desc, + i40e_aqc_opc_lldp_set_local_mib); + /* indirect command */ + desc.flags |= cpu_to_le16((u16)(i40e_aq_flag_buf | i40e_aq_flag_rd)); + if (buff_size > i40e_aq_large_buf) + desc.flags |= cpu_to_le16((u16)i40e_aq_flag_lb); + desc.datalen = cpu_to_le16(buff_size); + + cmd->type = mib_type; + cmd->length = cpu_to_le16(buff_size); + cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff)); + cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff)); + + status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details); + return status; +} + +/** + * i40e_aq_suspend_port_tx + * @hw: pointer to the hardware structure + * @seid: port seid + * @cmd_details: pointer to command details structure or null + * + * suspend port's tx traffic + **/ +i40e_status i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, + struct i40e_asq_cmd_details *cmd_details) +{ + struct i40e_aqc_tx_sched_ind *cmd; + struct i40e_aq_desc desc; + i40e_status status; + + cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw; + i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx); + cmd->vsi_seid = cpu_to_le16(seid); + status = i40e_asq_send_command(hw, &desc, null, 0, cmd_details); + + return status; +} + diff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb.c b/drivers/net/ethernet/intel/i40e/i40e_dcb.c --- a/drivers/net/ethernet/intel/i40e/i40e_dcb.c +++ b/drivers/net/ethernet/intel/i40e/i40e_dcb.c -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +/** + * i40e_get_fw_lldp_status + * @hw: pointer to the hw struct + * @lldp_status: pointer to the status enum + * + * get status of fw link layer discovery protocol (lldp) agent. + * status of agent is reported via @lldp_status parameter. + **/ +enum i40e_status_code +i40e_get_fw_lldp_status(struct i40e_hw *hw, + enum i40e_get_fw_lldp_status_resp *lldp_status) +{ + struct i40e_virt_mem mem; + i40e_status ret; + u8 *lldpmib; + + if (!lldp_status) + return i40e_err_param; + + /* allocate buffer for the lldpdu */ + ret = i40e_allocate_virt_mem(hw, &mem, i40e_lldpdu_size); + if (ret) + return ret; + + lldpmib = (u8 *)mem.va; + ret = i40e_aq_get_lldp_mib(hw, 0, 0, (void *)lldpmib, + i40e_lldpdu_size, null, null, null); + + if (!ret) { + *lldp_status = i40e_get_fw_lldp_status_enabled; + } else if (hw->aq.asq_last_status == i40e_aq_rc_enoent) { + /* mib is not available yet but the agent is running */ + *lldp_status = i40e_get_fw_lldp_status_enabled; + ret = 0; + } else if (hw->aq.asq_last_status == i40e_aq_rc_eperm) { + *lldp_status = i40e_get_fw_lldp_status_disabled; + ret = 0; + } + + i40e_free_virt_mem(hw, &mem); + return ret; +} + +/** + * i40e_add_ieee_ets_tlv - prepare ets tlv in ieee format + * @tlv: fill the ets config data in ieee format + * @dcbcfg: local store which holds the dcb config + * + * prepare ieee 802.1qaz ets cfg tlv + **/ +static void i40e_add_ieee_ets_tlv(struct i40e_lldp_org_tlv *tlv, + struct i40e_dcbx_config *dcbcfg) +{ + u8 priority0, priority1, maxtcwilling = 0; + struct i40e_dcb_ets_config *etscfg; + u16 offset = 0, typelength, i; + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + + typelength = (u16)((i40e_tlv_type_org << i40e_lldp_tlv_type_shift) | + i40e_ieee_ets_tlv_length); + tlv->typelength = htons(typelength); + + ouisubtype = (u32)((i40e_ieee_8021qaz_oui << i40e_lldp_tlv_oui_shift) | + i40e_ieee_subtype_ets_cfg); + tlv->ouisubtype = htonl(ouisubtype); + + /* first octet post subtype + * -------------------------- + * |will-|cbs | re- | max | + * |ing | |served| tcs | + * -------------------------- + * |1bit | 1bit|3 bits|3bits| + */ + etscfg = &dcbcfg->etscfg; + if (etscfg->willing) + maxtcwilling = bit(i40e_ieee_ets_willing_shift); + maxtcwilling |= etscfg->maxtcs & i40e_ieee_ets_maxtc_mask; + buf[offset] = maxtcwilling; + + /* move offset to priority assignment table */ + offset++; + + /* priority assignment table (4 octets) + * octets:| 1 | 2 | 3 | 4 | + * ----------------------------------------- + * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7| + * ----------------------------------------- + * bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0| + * ----------------------------------------- + */ + for (i = 0; i < 4; i++) { + priority0 = etscfg->prioritytable[i * 2] & 0xf; + priority1 = etscfg->prioritytable[i * 2 + 1] & 0xf; + buf[offset] = (priority0 << i40e_ieee_ets_prio_1_shift) | + priority1; + offset++; + } + + /* tc bandwidth table (8 octets) + * octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | + * --------------------------------- + * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| + * --------------------------------- + */ + for (i = 0; i < i40e_max_traffic_class; i++) + buf[offset++] = etscfg->tcbwtable[i]; + + /* tsa assignment table (8 octets) + * octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | + * --------------------------------- + * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| + * --------------------------------- + */ + for (i = 0; i < i40e_max_traffic_class; i++) + buf[offset++] = etscfg->tsatable[i]; +} + +/** + * i40e_add_ieee_etsrec_tlv - prepare ets recommended tlv in ieee format + * @tlv: fill ets recommended tlv in ieee format + * @dcbcfg: local store which holds the dcb config + * + * prepare ieee 802.1qaz ets rec tlv + **/ +static void i40e_add_ieee_etsrec_tlv(struct i40e_lldp_org_tlv *tlv, + struct i40e_dcbx_config *dcbcfg) +{ + struct i40e_dcb_ets_config *etsrec; + u16 offset = 0, typelength, i; + u8 priority0, priority1; + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + + typelength = (u16)((i40e_tlv_type_org << i40e_lldp_tlv_type_shift) | + i40e_ieee_ets_tlv_length); + tlv->typelength = htons(typelength); + + ouisubtype = (u32)((i40e_ieee_8021qaz_oui << i40e_lldp_tlv_oui_shift) | + i40e_ieee_subtype_ets_rec); + tlv->ouisubtype = htonl(ouisubtype); + + etsrec = &dcbcfg->etsrec; + /* first octet is reserved */ + /* move offset to priority assignment table */ + offset++; + + /* priority assignment table (4 octets) + * octets:| 1 | 2 | 3 | 4 | + * ----------------------------------------- + * |pri0|pri1|pri2|pri3|pri4|pri5|pri6|pri7| + * ----------------------------------------- + * bits:|7 4|3 0|7 4|3 0|7 4|3 0|7 4|3 0| + * ----------------------------------------- + */ + for (i = 0; i < 4; i++) { + priority0 = etsrec->prioritytable[i * 2] & 0xf; + priority1 = etsrec->prioritytable[i * 2 + 1] & 0xf; + buf[offset] = (priority0 << i40e_ieee_ets_prio_1_shift) | + priority1; + offset++; + } + + /* tc bandwidth table (8 octets) + * octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | + * --------------------------------- + * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| + * --------------------------------- + */ + for (i = 0; i < i40e_max_traffic_class; i++) + buf[offset++] = etsrec->tcbwtable[i]; + + /* tsa assignment table (8 octets) + * octets:| 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | + * --------------------------------- + * |tc0|tc1|tc2|tc3|tc4|tc5|tc6|tc7| + * --------------------------------- + */ + for (i = 0; i < i40e_max_traffic_class; i++) + buf[offset++] = etsrec->tsatable[i]; +} + +/** + * i40e_add_ieee_pfc_tlv - prepare pfc tlv in ieee format + * @tlv: fill pfc tlv in ieee format + * @dcbcfg: local store to get pfc cfg data + * + * prepare ieee 802.1qaz pfc cfg tlv + **/ +static void i40e_add_ieee_pfc_tlv(struct i40e_lldp_org_tlv *tlv, + struct i40e_dcbx_config *dcbcfg) +{ + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + u16 typelength; + + typelength = (u16)((i40e_tlv_type_org << i40e_lldp_tlv_type_shift) | + i40e_ieee_pfc_tlv_length); + tlv->typelength = htons(typelength); + + ouisubtype = (u32)((i40e_ieee_8021qaz_oui << i40e_lldp_tlv_oui_shift) | + i40e_ieee_subtype_pfc_cfg); + tlv->ouisubtype = htonl(ouisubtype); + + /* ---------------------------------------- + * |will-|mbc | re- | pfc | pfc enable | + * |ing | |served| cap | | + * ----------------------------------------- + * |1bit | 1bit|2 bits|4bits| 1 octet | + */ + if (dcbcfg->pfc.willing) + buf[0] = bit(i40e_ieee_pfc_willing_shift); + + if (dcbcfg->pfc.mbc) + buf[0] |= bit(i40e_ieee_pfc_mbc_shift); + + buf[0] |= dcbcfg->pfc.pfccap & 0xf; + buf[1] = dcbcfg->pfc.pfcenable; +} + +/** + * i40e_add_ieee_app_pri_tlv - prepare app tlv in ieee format + * @tlv: fill app tlv in ieee format + * @dcbcfg: local store to get app cfg data + * + * prepare ieee 802.1qaz app cfg tlv + **/ +static void i40e_add_ieee_app_pri_tlv(struct i40e_lldp_org_tlv *tlv, + struct i40e_dcbx_config *dcbcfg) +{ + u16 typelength, length, offset = 0; + u8 priority, selector, i = 0; + u8 *buf = tlv->tlvinfo; + u32 ouisubtype; + + /* no app tlvs then just return */ + if (dcbcfg->numapps == 0) + return; + ouisubtype = (u32)((i40e_ieee_8021qaz_oui << i40e_lldp_tlv_oui_shift) | + i40e_ieee_subtype_app_pri); + tlv->ouisubtype = htonl(ouisubtype); + + /* move offset to app priority table */ + offset++; + /* application priority table (3 octets) + * octets:| 1 | 2 | 3 | + * ----------------------------------------- + * |priority|rsrvd| sel | protocol id | + * ----------------------------------------- + * bits:|23 21|20 19|18 16|15 0| + * ----------------------------------------- + */ + while (i < dcbcfg->numapps) { + priority = dcbcfg->app[i].priority & 0x7; + selector = dcbcfg->app[i].selector & 0x7; + buf[offset] = (priority << i40e_ieee_app_prio_shift) | selector; + buf[offset + 1] = (dcbcfg->app[i].protocolid >> 0x8) & 0xff; + buf[offset + 2] = dcbcfg->app[i].protocolid & 0xff; + /* move to next app */ + offset += 3; + i++; + if (i >= i40e_dcbx_max_apps) + break; + } + /* length includes size of ouisubtype + 1 reserved + 3*numapps */ + length = sizeof(tlv->ouisubtype) + 1 + (i * 3); + typelength = (u16)((i40e_tlv_type_org << i40e_lldp_tlv_type_shift) | + (length & 0x1ff)); + tlv->typelength = htons(typelength); +} + +/** + * i40e_add_dcb_tlv - add all ieee tlvs + * @tlv: pointer to org tlv + * @dcbcfg: pointer to modified dcbx config structure * + * @tlvid: tlv id to be added + * add tlv information + **/ +static void i40e_add_dcb_tlv(struct i40e_lldp_org_tlv *tlv, + struct i40e_dcbx_config *dcbcfg, + u16 tlvid) +{ + switch (tlvid) { + case i40e_ieee_tlv_id_ets_cfg: + i40e_add_ieee_ets_tlv(tlv, dcbcfg); + break; + case i40e_ieee_tlv_id_ets_rec: + i40e_add_ieee_etsrec_tlv(tlv, dcbcfg); + break; + case i40e_ieee_tlv_id_pfc_cfg: + i40e_add_ieee_pfc_tlv(tlv, dcbcfg); + break; + case i40e_ieee_tlv_id_app_pri: + i40e_add_ieee_app_pri_tlv(tlv, dcbcfg); + break; + default: + break; + } +} + +/** + * i40e_set_dcb_config - set the local lldp mib to fw + * @hw: pointer to the hw struct + * + * set dcb configuration to the firmware + **/ +i40e_status i40e_set_dcb_config(struct i40e_hw *hw) +{ + struct i40e_dcbx_config *dcbcfg; + struct i40e_virt_mem mem; + u8 mib_type, *lldpmib; + i40e_status ret; + u16 miblen; + + /* update the hw local config */ + dcbcfg = &hw->local_dcbx_config; + /* allocate the lldpdu */ + ret = i40e_allocate_virt_mem(hw, &mem, i40e_lldpdu_size); + if (ret) + return ret; + + mib_type = set_local_mib_ac_type_local_mib; + if (dcbcfg->app_mode == i40e_dcbx_apps_non_willing) { + mib_type |= set_local_mib_ac_type_non_willing_apps << + set_local_mib_ac_type_non_willing_apps_shift; + } + lldpmib = (u8 *)mem.va; + i40e_dcb_config_to_lldp(lldpmib, &miblen, dcbcfg); + ret = i40e_aq_set_lldp_mib(hw, mib_type, (void *)lldpmib, miblen, null); + + i40e_free_virt_mem(hw, &mem); + return ret; +} + +/** + * i40e_dcb_config_to_lldp - convert dcbconfig to mib format + * @lldpmib: pointer to mib to be output + * @miblen: pointer to u16 for length of lldpmib + * @dcbcfg: store for lldpdu data + * + * send dcb configuration to fw + **/ +i40e_status i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen, + struct i40e_dcbx_config *dcbcfg) +{ + u16 length, offset = 0, tlvid, typelength; + struct i40e_lldp_org_tlv *tlv; + + tlv = (struct i40e_lldp_org_tlv *)lldpmib; + tlvid = i40e_tlv_id_start; + do { + i40e_add_dcb_tlv(tlv, dcbcfg, tlvid++); + typelength = ntohs(tlv->typelength); + length = (u16)((typelength & i40e_lldp_tlv_len_mask) >> + i40e_lldp_tlv_len_shift); + if (length) + offset += length + i40e_ieee_tlv_header_length; + /* end tlv or beyond lldpdu size */ + if (tlvid >= i40e_tlv_id_end_of_lldppdu || + offset >= i40e_lldpdu_size) + break; + /* move to next tlv */ + if (length) + tlv = (struct i40e_lldp_org_tlv *)((char *)tlv + + sizeof(tlv->typelength) + length); + } while (tlvid < i40e_tlv_id_end_of_lldppdu); + *miblen = offset; + return i40e_success; +} + +/** + * i40e_dcb_hw_rx_fifo_config + * @hw: pointer to the hw struct + * @ets_mode: strict priority or round robin mode + * @non_ets_mode: strict priority or round robin + * @max_exponent: exponent to calculate max refill credits + * @lltc_map: low latency tc bitmap + * + * configure hw rx fifo as part of dcb configuration. + **/ +void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw, + enum i40e_dcb_arbiter_mode ets_mode, + enum i40e_dcb_arbiter_mode non_ets_mode, + u32 max_exponent, + u8 lltc_map) +{ + u32 reg = rd32(hw, i40e_prtdcb_retsc); + + reg &= ~i40e_prtdcb_retsc_ets_mode_mask; + reg |= ((u32)ets_mode << i40e_prtdcb_retsc_ets_mode_shift) & + i40e_prtdcb_retsc_ets_mode_mask; + + reg &= ~i40e_prtdcb_retsc_non_ets_mode_mask; + reg |= ((u32)non_ets_mode << i40e_prtdcb_retsc_non_ets_mode_shift) & + i40e_prtdcb_retsc_non_ets_mode_mask; + + reg &= ~i40e_prtdcb_retsc_ets_max_exp_mask; + reg |= (max_exponent << i40e_prtdcb_retsc_ets_max_exp_shift) & + i40e_prtdcb_retsc_ets_max_exp_mask; + + reg &= ~i40e_prtdcb_retsc_lltc_mask; + reg |= (lltc_map << i40e_prtdcb_retsc_lltc_shift) & + i40e_prtdcb_retsc_lltc_mask; + wr32(hw, i40e_prtdcb_retsc, reg); +} + +/** + * i40e_dcb_hw_rx_cmd_monitor_config + * @hw: pointer to the hw struct + * @num_tc: total number of traffic class + * @num_ports: total number of ports on device + * + * configure hw rx command monitor as part of dcb configuration. + **/ +void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw, + u8 num_tc, u8 num_ports) +{ + u32 threshold; + u32 fifo_size; + u32 reg; + + /* set the threshold and fifo_size based on number of ports */ + switch (num_ports) { + case 1: + threshold = i40e_dcb_1_port_threshold; + fifo_size = i40e_dcb_1_port_fifo_size; + break; + case 2: + if (num_tc > 4) { + threshold = i40e_dcb_2_port_threshold_high_num_tc; + fifo_size = i40e_dcb_2_port_fifo_size_high_num_tc; + } else { + threshold = i40e_dcb_2_port_threshold_low_num_tc; + fifo_size = i40e_dcb_2_port_fifo_size_low_num_tc; + } + break; + case 4: + if (num_tc > 4) { + threshold = i40e_dcb_4_port_threshold_high_num_tc; + fifo_size = i40e_dcb_4_port_fifo_size_high_num_tc; + } else { + threshold = i40e_dcb_4_port_threshold_low_num_tc; + fifo_size = i40e_dcb_4_port_fifo_size_low_num_tc; + } + break; + default: + i40e_debug(hw, i40e_debug_dcb, "invalid num_ports %u. ", + (u32)num_ports); + return; + } + + /* the hardware manual describes setting up of i40e_prt_swr_pm_thr + * based on the number of ports and traffic classes for a given port as + * part of dcb configuration. + */ + reg = rd32(hw, i40e_prt_swr_pm_thr); + reg &= ~i40e_prt_swr_pm_thr_threshold_mask; + reg |= (threshold << i40e_prt_swr_pm_thr_threshold_shift) & + i40e_prt_swr_pm_thr_threshold_mask; + wr32(hw, i40e_prt_swr_pm_thr, reg); + + reg = rd32(hw, i40e_prtdcb_rppmc); + reg &= ~i40e_prtdcb_rppmc_rx_fifo_size_mask; + reg |= (fifo_size << i40e_prtdcb_rppmc_rx_fifo_size_shift) & + i40e_prtdcb_rppmc_rx_fifo_size_mask; + wr32(hw, i40e_prtdcb_rppmc, reg); +} + +/** + * i40e_dcb_hw_pfc_config + * @hw: pointer to the hw struct + * @pfc_en: bitmap of pfc enabled priorities + * @prio_tc: priority to tc assignment indexed by priority + * + * configure hw priority flow controller as part of dcb configuration. + **/ +void i40e_dcb_hw_pfc_config(struct i40e_hw *hw, + u8 pfc_en, u8 *prio_tc) +{ + u16 refresh_time = (u16)i40e_default_pause_time / 2; + u32 link_speed = hw->phy.link_info.link_speed; + u8 first_pfc_prio = 0; + u8 num_pfc_tc = 0; + u8 tc2pfc = 0; + u32 reg; + u8 i; + + /* get number of pfc tcs and tc2pfc map */ + for (i = 0; i < i40e_max_user_priority; i++) { + if (pfc_en & bit(i)) { + if (!first_pfc_prio) + first_pfc_prio = i; + /* set bit for the pfc tc */ + tc2pfc |= bit(prio_tc[i]); + num_pfc_tc++; + } + } + + switch (link_speed) { + case i40e_link_speed_10gb: + reg = rd32(hw, i40e_prtdcb_mflcn); + reg |= bit(i40e_prtdcb_mflcn_dpf_shift) & + i40e_prtdcb_mflcn_dpf_mask; + reg &= ~i40e_prtdcb_mflcn_rfce_mask; + reg &= ~i40e_prtdcb_mflcn_rpfce_mask; + if (pfc_en) { + reg |= bit(i40e_prtdcb_mflcn_rpfcm_shift) & + i40e_prtdcb_mflcn_rpfcm_mask; + reg |= ((u32)pfc_en << i40e_prtdcb_mflcn_rpfce_shift) & + i40e_prtdcb_mflcn_rpfce_mask; + } + wr32(hw, i40e_prtdcb_mflcn, reg); + + reg = rd32(hw, i40e_prtdcb_fccfg); + reg &= ~i40e_prtdcb_fccfg_tfce_mask; + if (pfc_en) + reg |= (i40e_dcb_pfc_enabled << + i40e_prtdcb_fccfg_tfce_shift) & + i40e_prtdcb_fccfg_tfce_mask; + wr32(hw, i40e_prtdcb_fccfg, reg); + + /* fcttv and fcrtv to be set by default */ + break; + case i40e_link_speed_40gb: + reg = rd32(hw, i40e_prtmac_hsec_ctl_rx_enable_gpp); + reg &= ~i40e_prtmac_hsec_ctl_rx_enable_gpp_mask; + wr32(hw, i40e_prtmac_hsec_ctl_rx_enable_gpp, reg); + + reg = rd32(hw, i40e_prtmac_hsec_ctl_rx_enable_ppp); + reg &= ~i40e_prtmac_hsec_ctl_rx_enable_gpp_mask; + reg |= bit(i40e_prtmac_hsec_ctl_rx_enable_ppp_shift) & + i40e_prtmac_hsec_ctl_rx_enable_ppp_mask; + wr32(hw, i40e_prtmac_hsec_ctl_rx_enable_ppp, reg); + + reg = rd32(hw, i40e_prtmac_hsec_ctl_rx_pause_enable); + reg &= ~i40e_prtmac_hsec_ctl_rx_pause_enable_mask; + reg |= ((u32)pfc_en << + i40e_prtmac_hsec_ctl_rx_pause_enable_shift) & + i40e_prtmac_hsec_ctl_rx_pause_enable_mask; + wr32(hw, i40e_prtmac_hsec_ctl_rx_pause_enable, reg); + + reg = rd32(hw, i40e_prtmac_hsec_ctl_tx_pause_enable); + reg &= ~i40e_prtmac_hsec_ctl_tx_pause_enable_mask; + reg |= ((u32)pfc_en << + i40e_prtmac_hsec_ctl_tx_pause_enable_shift) & + i40e_prtmac_hsec_ctl_tx_pause_enable_mask; + wr32(hw, i40e_prtmac_hsec_ctl_tx_pause_enable, reg); + + for (i = 0; i < i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_max_index; i++) { + reg = rd32(hw, i40e_prtmac_hsec_ctl_tx_pause_refresh_timer(i)); + reg &= ~i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_mask; + if (pfc_en) { + reg |= ((u32)refresh_time << + i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_shift) & + i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_mask; + } + wr32(hw, i40e_prtmac_hsec_ctl_tx_pause_refresh_timer(i), reg); + } + /* prtmac_hsec_ctl_tx_pause_quanta default value is 0xffff + * for all user priorities + */ + break; + } + + reg = rd32(hw, i40e_prtdcb_tc2pfc); + reg &= ~i40e_prtdcb_tc2pfc_tc2pfc_mask; + reg |= ((u32)tc2pfc << i40e_prtdcb_tc2pfc_tc2pfc_shift) & + i40e_prtdcb_tc2pfc_tc2pfc_mask; + wr32(hw, i40e_prtdcb_tc2pfc, reg); + + reg = rd32(hw, i40e_prtdcb_rup); + reg &= ~i40e_prtdcb_rup_novlanup_mask; + reg |= ((u32)first_pfc_prio << i40e_prtdcb_rup_novlanup_shift) & + i40e_prtdcb_rup_novlanup_mask; + wr32(hw, i40e_prtdcb_rup, reg); + + reg = rd32(hw, i40e_prtdcb_tdpmc); + reg &= ~i40e_prtdcb_tdpmc_tcpm_mode_mask; + if (num_pfc_tc > i40e_dcb_pfc_forced_num_tc) { + reg |= bit(i40e_prtdcb_tdpmc_tcpm_mode_shift) & + i40e_prtdcb_tdpmc_tcpm_mode_mask; + } + wr32(hw, i40e_prtdcb_tdpmc, reg); + + reg = rd32(hw, i40e_prtdcb_tcpmc); + reg &= ~i40e_prtdcb_tcpmc_tcpm_mode_mask; + if (num_pfc_tc > i40e_dcb_pfc_forced_num_tc) { + reg |= bit(i40e_prtdcb_tcpmc_tcpm_mode_shift) & + i40e_prtdcb_tcpmc_tcpm_mode_mask; + } + wr32(hw, i40e_prtdcb_tcpmc, reg); +} + +/** + * i40e_dcb_hw_set_num_tc + * @hw: pointer to the hw struct + * @num_tc: number of traffic classes + * + * configure number of traffic classes in hw + **/ +void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc) +{ + u32 reg = rd32(hw, i40e_prtdcb_genc); + + reg &= ~i40e_prtdcb_genc_numtc_mask; + reg |= ((u32)num_tc << i40e_prtdcb_genc_numtc_shift) & + i40e_prtdcb_genc_numtc_mask; + wr32(hw, i40e_prtdcb_genc, reg); +} + +/** + * i40e_dcb_hw_get_num_tc + * @hw: pointer to the hw struct + * + * returns number of traffic classes configured in hw + **/ +u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw) +{ + u32 reg = rd32(hw, i40e_prtdcb_genc); + + return (u8)((reg & i40e_prtdcb_genc_numtc_mask) >> + i40e_prtdcb_genc_numtc_shift); +} + +/** + * i40e_dcb_hw_rx_ets_bw_config + * @hw: pointer to the hw struct + * @bw_share: bandwidth share indexed per traffic class + * @mode: strict priority or round robin mode between up sharing same + * traffic class + * @prio_type: tc is ets enabled or strict priority + * + * configure hw rx ets bandwidth as part of dcb configuration. + **/ +void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share, + u8 *mode, u8 *prio_type) +{ + u32 reg; + u8 i; + + for (i = 0; i <= i40e_prtdcb_retstcc_max_index; i++) { + reg = rd32(hw, i40e_prtdcb_retstcc(i)); + reg &= ~(i40e_prtdcb_retstcc_bwshare_mask | + i40e_prtdcb_retstcc_upintc_mode_mask | + i40e_prtdcb_retstcc_etstc_shift); + reg |= ((u32)bw_share[i] << i40e_prtdcb_retstcc_bwshare_shift) & + i40e_prtdcb_retstcc_bwshare_mask; + reg |= ((u32)mode[i] << i40e_prtdcb_retstcc_upintc_mode_shift) & + i40e_prtdcb_retstcc_upintc_mode_mask; + reg |= ((u32)prio_type[i] << i40e_prtdcb_retstcc_etstc_shift) & + i40e_prtdcb_retstcc_etstc_mask; + wr32(hw, i40e_prtdcb_retstcc(i), reg); + } +} + +/** + * i40e_dcb_hw_rx_ets_bw_config + * @hw: pointer to the hw struct + * @prio_tc: priority to tc assignment indexed by priority + * + * configure hw rx up2tc map as part of dcb configuration. + **/ +void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc) +{ + u32 reg = rd32(hw, i40e_prtdcb_rup2tc); +#define i40e_up2tc_reg(val, i) \ + (((val) << i40e_prtdcb_rup2tc_up##i##tc_shift) & \ + i40e_prtdcb_rup2tc_up##i##tc_mask) + + reg |= i40e_up2tc_reg(prio_tc[0], 0); + reg |= i40e_up2tc_reg(prio_tc[1], 1); + reg |= i40e_up2tc_reg(prio_tc[2], 2); + reg |= i40e_up2tc_reg(prio_tc[3], 3); + reg |= i40e_up2tc_reg(prio_tc[4], 4); + reg |= i40e_up2tc_reg(prio_tc[5], 5); + reg |= i40e_up2tc_reg(prio_tc[6], 6); + reg |= i40e_up2tc_reg(prio_tc[7], 7); + + wr32(hw, i40e_prtdcb_rup2tc, reg); +} + +/** + * i40e_dcb_hw_calculate_pool_sizes - configure dcb pool sizes + * @hw: pointer to the hw struct + * @num_ports: number of available ports on the device + * @eee_enabled: eee enabled for the given port + * @pfc_en: bit map of pfc enabled traffic classes + * @mfs_tc: array of max frame size for each traffic class + * @pb_cfg: pointer to packet buffer configuration + * + * calculate the shared and dedicated per tc pool sizes, + * watermarks and threshold values. + **/ +void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw, + u8 num_ports, bool eee_enabled, + u8 pfc_en, u32 *mfs_tc, + struct i40e_rx_pb_config *pb_cfg) +{ + u32 pool_size[i40e_max_traffic_class]; + u32 high_wm[i40e_max_traffic_class]; + u32 low_wm[i40e_max_traffic_class]; + u32 total_pool_size = 0; + int shared_pool_size; /* need signed variable */ + u32 port_pb_size; + u32 mfs_max; + u32 pcirtt; + u8 i; + + /* get the mfs(max) for the port */ + for (i = 0; i < i40e_max_traffic_class; i++) { + if (mfs_tc[i] > mfs_max) + mfs_max = mfs_tc[i]; + } + + pcirtt = i40e_bt2b(i40e_pcirtt_link_speed_10g); + + /* calculate effective rx pb size per port */ + port_pb_size = i40e_device_rpb_size / num_ports; + if (eee_enabled) + port_pb_size -= i40e_bt2b(i40e_eee_tx_lpi_exit_time); + port_pb_size -= mfs_max; + + /* step 1 calculating tc pool/shared pool sizes and watermarks */ + for (i = 0; i < i40e_max_traffic_class; i++) { + if (pfc_en & bit(i)) { + low_wm[i] = (i40e_dcb_watermark_start_factor * + mfs_tc[i]) + pcirtt; + high_wm[i] = low_wm[i]; + high_wm[i] += ((mfs_max > i40e_max_frame_size) + ? mfs_max : i40e_max_frame_size); + pool_size[i] = high_wm[i]; + pool_size[i] += i40e_bt2b(i40e_std_dv_tc(mfs_max, + mfs_tc[i])); + } else { + low_wm[i] = 0; + pool_size[i] = (i40e_dcb_watermark_start_factor * + mfs_tc[i]) + pcirtt; + high_wm[i] = pool_size[i]; + } + total_pool_size += pool_size[i]; + } + + shared_pool_size = port_pb_size - total_pool_size; + if (shared_pool_size > 0) { + pb_cfg->shared_pool_size = shared_pool_size; + pb_cfg->shared_pool_high_wm = shared_pool_size; + pb_cfg->shared_pool_low_wm = 0; + for (i = 0; i < i40e_max_traffic_class; i++) { + pb_cfg->shared_pool_low_thresh[i] = 0; + pb_cfg->shared_pool_high_thresh[i] = shared_pool_size; + pb_cfg->tc_pool_size[i] = pool_size[i]; + pb_cfg->tc_pool_high_wm[i] = high_wm[i]; + pb_cfg->tc_pool_low_wm[i] = low_wm[i]; + } + + } else { + i40e_debug(hw, i40e_debug_dcb, + "the shared pool size for the port is negative %d. ", + shared_pool_size); + } +} + +/** + * i40e_dcb_hw_rx_pb_config + * @hw: pointer to the hw struct + * @old_pb_cfg: existing rx packet buffer configuration + * @new_pb_cfg: new rx packet buffer configuration + * + * program the rx packet buffer registers. + **/ +void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw, + struct i40e_rx_pb_config *old_pb_cfg, + struct i40e_rx_pb_config *new_pb_cfg) +{ + u32 old_val; + u32 new_val; + u32 reg; + u8 i; + + /* the rx packet buffer register programming needs to be done in a + * certain order and the following code is based on that + * requirement. + */ + + /* program the shared pool low water mark per port if decreasing */ + old_val = old_pb_cfg->shared_pool_low_wm; + new_val = new_pb_cfg->shared_pool_low_wm; + if (new_val < old_val) { + reg = rd32(hw, i40e_prtrpb_slw); + reg &= ~i40e_prtrpb_slw_slw_mask; + reg |= (new_val << i40e_prtrpb_slw_slw_shift) & + i40e_prtrpb_slw_slw_mask; + wr32(hw, i40e_prtrpb_slw, reg); + } + + /* program the shared pool low threshold and tc pool + * low water mark per tc that are decreasing. + */ + for (i = 0; i < i40e_max_traffic_class; i++) { + old_val = old_pb_cfg->shared_pool_low_thresh[i]; + new_val = new_pb_cfg->shared_pool_low_thresh[i]; + if (new_val < old_val) { + reg = rd32(hw, i40e_prtrpb_slt(i)); + reg &= ~i40e_prtrpb_slt_slt_tcn_mask; + reg |= (new_val << i40e_prtrpb_slt_slt_tcn_shift) & + i40e_prtrpb_slt_slt_tcn_mask; + wr32(hw, i40e_prtrpb_slt(i), reg); + } + + old_val = old_pb_cfg->tc_pool_low_wm[i]; + new_val = new_pb_cfg->tc_pool_low_wm[i]; + if (new_val < old_val) { + reg = rd32(hw, i40e_prtrpb_dlw(i)); + reg &= ~i40e_prtrpb_dlw_dlw_tcn_mask; + reg |= (new_val << i40e_prtrpb_dlw_dlw_tcn_shift) & + i40e_prtrpb_dlw_dlw_tcn_mask; + wr32(hw, i40e_prtrpb_dlw(i), reg); + } + } + + /* program the shared pool high water mark per port if decreasing */ + old_val = old_pb_cfg->shared_pool_high_wm; + new_val = new_pb_cfg->shared_pool_high_wm; + if (new_val < old_val) { + reg = rd32(hw, i40e_prtrpb_shw); + reg &= ~i40e_prtrpb_shw_shw_mask; + reg |= (new_val << i40e_prtrpb_shw_shw_shift) & + i40e_prtrpb_shw_shw_mask; + wr32(hw, i40e_prtrpb_shw, reg); + } + + /* program the shared pool high threshold and tc pool + * high water mark per tc that are decreasing. + */ + for (i = 0; i < i40e_max_traffic_class; i++) { + old_val = old_pb_cfg->shared_pool_high_thresh[i]; + new_val = new_pb_cfg->shared_pool_high_thresh[i]; + if (new_val < old_val) { + reg = rd32(hw, i40e_prtrpb_sht(i)); + reg &= ~i40e_prtrpb_sht_sht_tcn_mask; + reg |= (new_val << i40e_prtrpb_sht_sht_tcn_shift) & + i40e_prtrpb_sht_sht_tcn_mask; + wr32(hw, i40e_prtrpb_sht(i), reg); + } + + old_val = old_pb_cfg->tc_pool_high_wm[i]; + new_val = new_pb_cfg->tc_pool_high_wm[i]; + if (new_val < old_val) { + reg = rd32(hw, i40e_prtrpb_dhw(i)); + reg &= ~i40e_prtrpb_dhw_dhw_tcn_mask; + reg |= (new_val << i40e_prtrpb_dhw_dhw_tcn_shift) & + i40e_prtrpb_dhw_dhw_tcn_mask; + wr32(hw, i40e_prtrpb_dhw(i), reg); + } + } + + /* write dedicated pool sizes per tc */ + for (i = 0; i < i40e_max_traffic_class; i++) { + new_val = new_pb_cfg->tc_pool_size[i]; + reg = rd32(hw, i40e_prtrpb_dps(i)); + reg &= ~i40e_prtrpb_dps_dps_tcn_mask; + reg |= (new_val << i40e_prtrpb_dps_dps_tcn_shift) & + i40e_prtrpb_dps_dps_tcn_mask; + wr32(hw, i40e_prtrpb_dps(i), reg); + } + + /* write shared pool size per port */ + new_val = new_pb_cfg->shared_pool_size; + reg = rd32(hw, i40e_prtrpb_sps); + reg &= ~i40e_prtrpb_sps_sps_mask; + reg |= (new_val << i40e_prtrpb_sps_sps_shift) & + i40e_prtrpb_sps_sps_mask; + wr32(hw, i40e_prtrpb_sps, reg); + + /* program the shared pool low water mark per port if increasing */ + old_val = old_pb_cfg->shared_pool_low_wm; + new_val = new_pb_cfg->shared_pool_low_wm; + if (new_val > old_val) { + reg = rd32(hw, i40e_prtrpb_slw); + reg &= ~i40e_prtrpb_slw_slw_mask; + reg |= (new_val << i40e_prtrpb_slw_slw_shift) & + i40e_prtrpb_slw_slw_mask; + wr32(hw, i40e_prtrpb_slw, reg); + } + + /* program the shared pool low threshold and tc pool + * low water mark per tc that are increasing. + */ + for (i = 0; i < i40e_max_traffic_class; i++) { + old_val = old_pb_cfg->shared_pool_low_thresh[i]; + new_val = new_pb_cfg->shared_pool_low_thresh[i]; + if (new_val > old_val) { + reg = rd32(hw, i40e_prtrpb_slt(i)); + reg &= ~i40e_prtrpb_slt_slt_tcn_mask; + reg |= (new_val << i40e_prtrpb_slt_slt_tcn_shift) & + i40e_prtrpb_slt_slt_tcn_mask; + wr32(hw, i40e_prtrpb_slt(i), reg); + } + + old_val = old_pb_cfg->tc_pool_low_wm[i]; + new_val = new_pb_cfg->tc_pool_low_wm[i]; + if (new_val > old_val) { + reg = rd32(hw, i40e_prtrpb_dlw(i)); + reg &= ~i40e_prtrpb_dlw_dlw_tcn_mask; + reg |= (new_val << i40e_prtrpb_dlw_dlw_tcn_shift) & + i40e_prtrpb_dlw_dlw_tcn_mask; + wr32(hw, i40e_prtrpb_dlw(i), reg); + } + } + + /* program the shared pool high water mark per port if increasing */ + old_val = old_pb_cfg->shared_pool_high_wm; + new_val = new_pb_cfg->shared_pool_high_wm; + if (new_val > old_val) { + reg = rd32(hw, i40e_prtrpb_shw); + reg &= ~i40e_prtrpb_shw_shw_mask; + reg |= (new_val << i40e_prtrpb_shw_shw_shift) & + i40e_prtrpb_shw_shw_mask; + wr32(hw, i40e_prtrpb_shw, reg); + } + + /* program the shared pool high threshold and tc pool + * high water mark per tc that are increasing. + */ + for (i = 0; i < i40e_max_traffic_class; i++) { + old_val = old_pb_cfg->shared_pool_high_thresh[i]; + new_val = new_pb_cfg->shared_pool_high_thresh[i]; + if (new_val > old_val) { + reg = rd32(hw, i40e_prtrpb_sht(i)); + reg &= ~i40e_prtrpb_sht_sht_tcn_mask; + reg |= (new_val << i40e_prtrpb_sht_sht_tcn_shift) & + i40e_prtrpb_sht_sht_tcn_mask; + wr32(hw, i40e_prtrpb_sht(i), reg); + } + + old_val = old_pb_cfg->tc_pool_high_wm[i]; + new_val = new_pb_cfg->tc_pool_high_wm[i]; + if (new_val > old_val) { + reg = rd32(hw, i40e_prtrpb_dhw(i)); + reg &= ~i40e_prtrpb_dhw_dhw_tcn_mask; + reg |= (new_val << i40e_prtrpb_dhw_dhw_tcn_shift) & + i40e_prtrpb_dhw_dhw_tcn_mask; + wr32(hw, i40e_prtrpb_dhw(i), reg); + } + } +} + diff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb.h b/drivers/net/ethernet/intel/i40e/i40e_dcb.h --- a/drivers/net/ethernet/intel/i40e/i40e_dcb.h +++ b/drivers/net/ethernet/intel/i40e/i40e_dcb.h -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +#define i40e_dcbx_status_not_started 0 +#define i40e_dcbx_status_multiple_peers 3 +#define i40e_cee_subtype_ctrl 1 +#define i40e_dcb_pfc_enabled 2 +#define i40e_dcb_pfc_forced_num_tc 2 +/* tlv definitions for preparing mib */ +#define i40e_tlv_id_chassis_id 0 +#define i40e_tlv_id_port_id 1 +#define i40e_tlv_id_time_to_live 2 +#define i40e_ieee_tlv_id_ets_cfg 3 +#define i40e_ieee_tlv_id_ets_rec 4 +#define i40e_ieee_tlv_id_pfc_cfg 5 +#define i40e_ieee_tlv_id_app_pri 6 +#define i40e_tlv_id_end_of_lldppdu 7 +#define i40e_tlv_id_start i40e_ieee_tlv_id_ets_cfg -#pragma pack(1) +#define i40e_ieee_tlv_header_length 2 +#define i40e_ieee_ets_tlv_length 25 +#define i40e_ieee_pfc_tlv_length 6 +#define i40e_ieee_app_tlv_length 11 + +/* defines for default sw dcb config */ +#define i40e_ieee_default_ets_tcbw 100 +#define i40e_ieee_default_ets_willing 1 +#define i40e_ieee_default_pfc_willing 1 +#define i40e_ieee_default_num_apps 1 +#define i40e_ieee_default_app_prio 3 +#pragma pack(1) +#define i40e_cee_feat_tlv_enable_mask 0x80 +#define i40e_cee_feat_tlv_err_mask 0x20 +enum i40e_get_fw_lldp_status_resp { + i40e_get_fw_lldp_status_disabled = 0, + i40e_get_fw_lldp_status_enabled = 1 +}; + +/* data structures to pass for sw dcbx */ +struct i40e_rx_pb_config { + u32 shared_pool_size; + u32 shared_pool_high_wm; + u32 shared_pool_low_wm; + u32 shared_pool_high_thresh[i40e_max_traffic_class]; + u32 shared_pool_low_thresh[i40e_max_traffic_class]; + u32 tc_pool_size[i40e_max_traffic_class]; + u32 tc_pool_high_wm[i40e_max_traffic_class]; + u32 tc_pool_low_wm[i40e_max_traffic_class]; +}; + +enum i40e_dcb_arbiter_mode { + i40e_dcb_arb_mode_strict_priority = 0, + i40e_dcb_arb_mode_round_robin = 1 +}; + +#define i40e_dcb_default_max_exponent 0xb +#define i40e_default_pause_time 0xffff +#define i40e_max_frame_size 4608 /* 4.5 kb */ + +#define i40e_device_rpb_size 968000 /* 968 kb */ + +/* bittimes (bt) conversion */ +#define i40e_bt2kb(bt) (((bt) + (8 * 1024 - 1)) / (8 * 1024)) +#define i40e_b2bt(bt) ((bt) * 8) +#define i40e_bt2b(bt) (((bt) + (8 - 1)) / 8) + +/* max frame(tc) = mfs(max) + mfs(tc) */ +#define i40e_max_frame_tc(mfs_max, mfs_tc) i40e_b2bt((mfs_max) + (mfs_tc)) + +/* eee tx lpi exit time in bit times */ +#define i40e_eee_tx_lpi_exit_time 142500 + +/* pci round trip time in bit times */ +#define i40e_pcirtt_link_speed_10g 20000 +#define i40e_pcirtt_byte_link_speed_20g 40000 +#define i40e_pcirtt_byte_link_speed_40g 80000 + +/* pfc frame delay bit times */ +#define i40e_pfc_frame_delay 672 + +/* worst case cable (10gbase-t) delay bit times */ +#define i40e_cable_delay 5556 + +/* higher layer delay @10g bit times */ +#define i40e_higher_layer_delay_10g 6144 + +/* interface delays in bit times */ +/* todo: add for other link speeds 20g/40g/etc. */ +#define i40e_interface_delay_10g_mac_control 8192 +#define i40e_interface_delay_10g_mac 8192 +#define i40e_interface_delay_10g_rs 8192 + +#define i40e_interface_delay_xgxs 2048 +#define i40e_interface_delay_xaui 2048 + +#define i40e_interface_delay_10g_basex_pcs 2048 +#define i40e_interface_delay_10g_baser_pcs 3584 +#define i40e_interface_delay_lx4_pmd 512 +#define i40e_interface_delay_cx4_pmd 512 +#define i40e_interface_delay_serial_pma 512 +#define i40e_interface_delay_pmd 512 + +#define i40e_interface_delay_10g_baset 25600 + +/* hardware rx dcb config related defines */ +#define i40e_dcb_1_port_threshold 0xf +#define i40e_dcb_1_port_fifo_size 0x10 +#define i40e_dcb_2_port_threshold_low_num_tc 0xf +#define i40e_dcb_2_port_fifo_size_low_num_tc 0x10 +#define i40e_dcb_2_port_threshold_high_num_tc 0xc +#define i40e_dcb_2_port_fifo_size_high_num_tc 0x8 +#define i40e_dcb_4_port_threshold_low_num_tc 0x9 +#define i40e_dcb_4_port_fifo_size_low_num_tc 0x8 +#define i40e_dcb_4_port_threshold_high_num_tc 0x6 +#define i40e_dcb_4_port_fifo_size_high_num_tc 0x4 +#define i40e_dcb_watermark_start_factor 0x2 + +/* delay values for with 10g baset in bit times */ +#define i40e_interface_delay_10g_copper \ + (i40e_interface_delay_10g_mac + (2 * i40e_interface_delay_xaui) \ + + i40e_interface_delay_10g_baset) +#define i40e_dv_tc(mfs_max, mfs_tc) \ + ((2 * i40e_max_frame_tc(mfs_max, mfs_tc)) \ + + i40e_pfc_frame_delay \ + + (2 * i40e_cable_delay) \ + + (2 * i40e_interface_delay_10g_copper) \ + + i40e_higher_layer_delay_10g) +static inline u32 i40e_std_dv_tc(u32 mfs_max, u32 mfs_tc) +{ + return i40e_dv_tc(mfs_max, mfs_tc) + i40e_b2bt(mfs_max); +} + +/* apis for sw dcbx */ +void i40e_dcb_hw_rx_fifo_config(struct i40e_hw *hw, + enum i40e_dcb_arbiter_mode ets_mode, + enum i40e_dcb_arbiter_mode non_ets_mode, + u32 max_exponent, u8 lltc_map); +void i40e_dcb_hw_rx_cmd_monitor_config(struct i40e_hw *hw, + u8 num_tc, u8 num_ports); +void i40e_dcb_hw_pfc_config(struct i40e_hw *hw, + u8 pfc_en, u8 *prio_tc); +void i40e_dcb_hw_set_num_tc(struct i40e_hw *hw, u8 num_tc); +u8 i40e_dcb_hw_get_num_tc(struct i40e_hw *hw); +void i40e_dcb_hw_rx_ets_bw_config(struct i40e_hw *hw, u8 *bw_share, + u8 *mode, u8 *prio_type); +void i40e_dcb_hw_rx_up2tc_config(struct i40e_hw *hw, u8 *prio_tc); +void i40e_dcb_hw_calculate_pool_sizes(struct i40e_hw *hw, + u8 num_ports, bool eee_enabled, + u8 pfc_en, u32 *mfs_tc, + struct i40e_rx_pb_config *pb_cfg); +void i40e_dcb_hw_rx_pb_config(struct i40e_hw *hw, + struct i40e_rx_pb_config *old_pb_cfg, + struct i40e_rx_pb_config *new_pb_cfg); - u16 *status); + u16 *status); - struct i40e_dcbx_config *dcbcfg); + struct i40e_dcbx_config *dcbcfg); - u8 bridgetype, - struct i40e_dcbx_config *dcbcfg); + u8 bridgetype, + struct i40e_dcbx_config *dcbcfg); -i40e_status i40e_init_dcb(struct i40e_hw *hw, bool enable_mib_change); +i40e_status i40e_init_dcb(struct i40e_hw *hw, + bool enable_mib_change); +enum i40e_status_code +i40e_get_fw_lldp_status(struct i40e_hw *hw, + enum i40e_get_fw_lldp_status_resp *lldp_status); +i40e_status i40e_set_dcb_config(struct i40e_hw *hw); +i40e_status i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen, + struct i40e_dcbx_config *dcbcfg); diff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h --- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h +++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +enum i40e_status_code +i40e_aq_set_lldp_mib(struct i40e_hw *hw, + u8 mib_type, void *buff, u16 buff_size, + struct i40e_asq_cmd_details *cmd_details); +enum i40e_status_code +i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid, + struct i40e_asq_cmd_details *cmd_details); diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h --- a/drivers/net/ethernet/intel/i40e/i40e_register.h +++ b/drivers/net/ethernet/intel/i40e/i40e_register.h -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +#define i40e_prt_swr_pm_thr 0x0026cd00 /* reset: corer */ +#define i40e_prt_swr_pm_thr_threshold_shift 0 +#define i40e_prt_swr_pm_thr_threshold_mask i40e_mask(0xff, i40e_prt_swr_pm_thr_threshold_shift) +#define i40e_prtdcb_fccfg 0x001e4640 /* reset: globr */ +#define i40e_prtdcb_fccfg_tfce_shift 3 +#define i40e_prtdcb_fccfg_tfce_mask i40e_mask(0x3, i40e_prtdcb_fccfg_tfce_shift) +#define i40e_prtdcb_genc_numtc_shift 2 +#define i40e_prtdcb_genc_numtc_mask i40e_mask(0xf, i40e_prtdcb_genc_numtc_shift) +#define i40e_prtdcb_mflcn 0x001e2400 /* reset: globr */ +#define i40e_prtdcb_mflcn_pmcf_shift 0 +#define i40e_prtdcb_mflcn_pmcf_mask i40e_mask(0x1, i40e_prtdcb_mflcn_pmcf_shift) +#define i40e_prtdcb_mflcn_dpf_shift 1 +#define i40e_prtdcb_mflcn_dpf_mask i40e_mask(0x1, i40e_prtdcb_mflcn_dpf_shift) +#define i40e_prtdcb_mflcn_rpfcm_shift 2 +#define i40e_prtdcb_mflcn_rpfcm_mask i40e_mask(0x1, i40e_prtdcb_mflcn_rpfcm_shift) +#define i40e_prtdcb_mflcn_rfce_shift 3 +#define i40e_prtdcb_mflcn_rfce_mask i40e_mask(0x1, i40e_prtdcb_mflcn_rfce_shift) +#define i40e_prtdcb_mflcn_rpfce_shift 4 +#define i40e_prtdcb_mflcn_rpfce_mask i40e_mask(0xff, i40e_prtdcb_mflcn_rpfce_shift) +#define i40e_prtdcb_retsc 0x001223e0 /* reset: corer */ +#define i40e_prtdcb_retsc_ets_mode_shift 0 +#define i40e_prtdcb_retsc_ets_mode_mask i40e_mask(0x1, i40e_prtdcb_retsc_ets_mode_shift) +#define i40e_prtdcb_retsc_non_ets_mode_shift 1 +#define i40e_prtdcb_retsc_non_ets_mode_mask i40e_mask(0x1, i40e_prtdcb_retsc_non_ets_mode_shift) +#define i40e_prtdcb_retsc_ets_max_exp_shift 2 +#define i40e_prtdcb_retsc_ets_max_exp_mask i40e_mask(0xf, i40e_prtdcb_retsc_ets_max_exp_shift) +#define i40e_prtdcb_retsc_lltc_shift 8 +#define i40e_prtdcb_retsc_lltc_mask i40e_mask(0xff, i40e_prtdcb_retsc_lltc_shift) +#define i40e_prtdcb_retstcc(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtdcb_retstcc_max_index 7 +#define i40e_prtdcb_retstcc_bwshare_shift 0 +#define i40e_prtdcb_retstcc_bwshare_mask i40e_mask(0x7f, i40e_prtdcb_retstcc_bwshare_shift) +#define i40e_prtdcb_retstcc_upintc_mode_shift 30 +#define i40e_prtdcb_retstcc_upintc_mode_mask i40e_mask(0x1, i40e_prtdcb_retstcc_upintc_mode_shift) +#define i40e_prtdcb_retstcc_etstc_shift 31 +#define i40e_prtdcb_retstcc_etstc_mask i40e_mask(0x1u, i40e_prtdcb_retstcc_etstc_shift) +#define i40e_prtdcb_rppmc 0x001223a0 /* reset: corer */ +#define i40e_prtdcb_rppmc_lanrppm_shift 0 +#define i40e_prtdcb_rppmc_lanrppm_mask i40e_mask(0xff, i40e_prtdcb_rppmc_lanrppm_shift) +#define i40e_prtdcb_rppmc_rdmarppm_shift 8 +#define i40e_prtdcb_rppmc_rdmarppm_mask i40e_mask(0xff, i40e_prtdcb_rppmc_rdmarppm_shift) +#define i40e_prtdcb_rppmc_rx_fifo_size_shift 16 +#define i40e_prtdcb_rppmc_rx_fifo_size_mask i40e_mask(0xff, i40e_prtdcb_rppmc_rx_fifo_size_shift) +#define i40e_prtdcb_rup 0x001c0b00 /* reset: corer */ +#define i40e_prtdcb_rup_novlanup_shift 0 +#define i40e_prtdcb_rup_novlanup_mask i40e_mask(0x7, i40e_prtdcb_rup_novlanup_shift) +#define i40e_prtdcb_rup2tc 0x001c09a0 /* reset: corer */ +#define i40e_prtdcb_rup2tc_up0tc_shift 0 +#define i40e_prtdcb_rup2tc_up0tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up0tc_shift) +#define i40e_prtdcb_rup2tc_up1tc_shift 3 +#define i40e_prtdcb_rup2tc_up1tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up1tc_shift) +#define i40e_prtdcb_rup2tc_up2tc_shift 6 +#define i40e_prtdcb_rup2tc_up2tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up2tc_shift) +#define i40e_prtdcb_rup2tc_up3tc_shift 9 +#define i40e_prtdcb_rup2tc_up3tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up3tc_shift) +#define i40e_prtdcb_rup2tc_up4tc_shift 12 +#define i40e_prtdcb_rup2tc_up4tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up4tc_shift) +#define i40e_prtdcb_rup2tc_up5tc_shift 15 +#define i40e_prtdcb_rup2tc_up5tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up5tc_shift) +#define i40e_prtdcb_rup2tc_up6tc_shift 18 +#define i40e_prtdcb_rup2tc_up6tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up6tc_shift) +#define i40e_prtdcb_rup2tc_up7tc_shift 21 +#define i40e_prtdcb_rup2tc_up7tc_mask i40e_mask(0x7, i40e_prtdcb_rup2tc_up7tc_shift) +#define i40e_prtdcb_ruptq(_i) (0x00122400 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtdcb_ruptq_max_index 7 +#define i40e_prtdcb_ruptq_rxqnum_shift 0 +#define i40e_prtdcb_ruptq_rxqnum_mask i40e_mask(0x3fff, i40e_prtdcb_ruptq_rxqnum_shift) +#define i40e_prtdcb_tc2pfc 0x001c0980 /* reset: corer */ +#define i40e_prtdcb_tc2pfc_tc2pfc_shift 0 +#define i40e_prtdcb_tc2pfc_tc2pfc_mask i40e_mask(0xff, i40e_prtdcb_tc2pfc_tc2pfc_shift) +#define i40e_prtdcb_tcmstc(_i) (0x000a0040 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtdcb_tcmstc_max_index 7 +#define i40e_prtdcb_tcmstc_mstc_shift 0 +#define i40e_prtdcb_tcmstc_mstc_mask i40e_mask(0xfffff, i40e_prtdcb_tcmstc_mstc_shift) +#define i40e_prtdcb_tcpmc 0x000a21a0 /* reset: corer */ +#define i40e_prtdcb_tcpmc_cpm_shift 0 +#define i40e_prtdcb_tcpmc_cpm_mask i40e_mask(0x1fff, i40e_prtdcb_tcpmc_cpm_shift) +#define i40e_prtdcb_tcpmc_lltc_shift 13 +#define i40e_prtdcb_tcpmc_lltc_mask i40e_mask(0xff, i40e_prtdcb_tcpmc_lltc_shift) +#define i40e_prtdcb_tcpmc_tcpm_mode_shift 30 +#define i40e_prtdcb_tcpmc_tcpm_mode_mask i40e_mask(0x1, i40e_prtdcb_tcpmc_tcpm_mode_shift) +#define i40e_prtdcb_tcwstc(_i) (0x000a2040 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtdcb_tcwstc_max_index 7 +#define i40e_prtdcb_tcwstc_mstc_shift 0 +#define i40e_prtdcb_tcwstc_mstc_mask i40e_mask(0xfffff, i40e_prtdcb_tcwstc_mstc_shift) +#define i40e_prtdcb_tdpmc 0x000a0180 /* reset: corer */ +#define i40e_prtdcb_tdpmc_dpm_shift 0 +#define i40e_prtdcb_tdpmc_dpm_mask i40e_mask(0xff, i40e_prtdcb_tdpmc_dpm_shift) +#define i40e_prtdcb_tdpmc_tcpm_mode_shift 30 +#define i40e_prtdcb_tdpmc_tcpm_mode_mask i40e_mask(0x1, i40e_prtdcb_tdpmc_tcpm_mode_shift) +#define i40e_prtdcb_tetsc_tcb 0x000ae060 /* reset: corer */ +#define i40e_prtdcb_tetsc_tcb_en_ll_strict_priority_shift 0 +#define i40e_prtdcb_tetsc_tcb_en_ll_strict_priority_mask i40e_mask(0x1, \ + i40e_prtdcb_tetsc_tcb_en_ll_strict_priority_shift) +#define i40e_prtdcb_tetsc_tcb_lltc_shift 8 +#define i40e_prtdcb_tetsc_tcb_lltc_mask i40e_mask(0xff, i40e_prtdcb_tetsc_tcb_lltc_shift) +#define i40e_prtdcb_tetsc_tpb 0x00098060 /* reset: corer */ +#define i40e_prtdcb_tetsc_tpb_en_ll_strict_priority_shift 0 +#define i40e_prtdcb_tetsc_tpb_en_ll_strict_priority_mask i40e_mask(0x1, \ + i40e_prtdcb_tetsc_tpb_en_ll_strict_priority_shift) +#define i40e_prtdcb_tetsc_tpb_lltc_shift 8 +#define i40e_prtdcb_tetsc_tpb_lltc_mask i40e_mask(0xff, i40e_prtdcb_tetsc_tpb_lltc_shift) +#define i40e_prtdcb_tfcs 0x001e4560 /* reset: globr */ +#define i40e_prtdcb_tfcs_txoff_shift 0 +#define i40e_prtdcb_tfcs_txoff_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff_shift) +#define i40e_prtdcb_tfcs_txoff0_shift 8 +#define i40e_prtdcb_tfcs_txoff0_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff0_shift) +#define i40e_prtdcb_tfcs_txoff1_shift 9 +#define i40e_prtdcb_tfcs_txoff1_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff1_shift) +#define i40e_prtdcb_tfcs_txoff2_shift 10 +#define i40e_prtdcb_tfcs_txoff2_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff2_shift) +#define i40e_prtdcb_tfcs_txoff3_shift 11 +#define i40e_prtdcb_tfcs_txoff3_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff3_shift) +#define i40e_prtdcb_tfcs_txoff4_shift 12 +#define i40e_prtdcb_tfcs_txoff4_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff4_shift) +#define i40e_prtdcb_tfcs_txoff5_shift 13 +#define i40e_prtdcb_tfcs_txoff5_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff5_shift) +#define i40e_prtdcb_tfcs_txoff6_shift 14 +#define i40e_prtdcb_tfcs_txoff6_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff6_shift) +#define i40e_prtdcb_tfcs_txoff7_shift 15 +#define i40e_prtdcb_tfcs_txoff7_mask i40e_mask(0x1, i40e_prtdcb_tfcs_txoff7_shift) +#define i40e_prtdcb_tpfcts(_i) (0x001e4660 + ((_i) * 32)) /* _i=0...7 */ /* reset: globr */ +#define i40e_prtdcb_tpfcts_max_index 7 +#define i40e_prtdcb_tpfcts_pfctimer_shift 0 +#define i40e_prtdcb_tpfcts_pfctimer_mask i40e_mask(0x3fff, i40e_prtdcb_tpfcts_pfctimer_shift) +#define i40e_prtmac_hsec_ctl_rx_enable_gpp 0x001e3260 /* reset: globr */ +#define i40e_prtmac_hsec_ctl_rx_enable_gpp_shift 0 +#define i40e_prtmac_hsec_ctl_rx_enable_gpp_mask i40e_mask(0x1, \ + i40e_prtmac_hsec_ctl_rx_enable_gpp_shift) +#define i40e_prtmac_hsec_ctl_rx_enable_ppp 0x001e32e0 /* reset: globr */ +#define i40e_prtmac_hsec_ctl_rx_enable_ppp_shift 0 +#define i40e_prtmac_hsec_ctl_rx_enable_ppp_mask i40e_mask(0x1, \ + i40e_prtmac_hsec_ctl_rx_enable_ppp_shift) +#define i40e_prtmac_hsec_ctl_rx_pause_enable 0x001e30c0 /* reset: globr */ +#define i40e_prtmac_hsec_ctl_rx_pause_enable_shift 0 +#define i40e_prtmac_hsec_ctl_rx_pause_enable_mask i40e_mask(0x1ff, \ + i40e_prtmac_hsec_ctl_rx_pause_enable_shift) +#define i40e_prtmac_hsec_ctl_tx_pause_enable 0x001e30d0 /* reset: globr */ +#define i40e_prtmac_hsec_ctl_tx_pause_enable_shift 0 +#define i40e_prtmac_hsec_ctl_tx_pause_enable_mask i40e_mask(0x1ff, \ + i40e_prtmac_hsec_ctl_tx_pause_enable_shift) +#define i40e_prtmac_hsec_ctl_tx_pause_refresh_timer(_i) (0x001e3400 + ((_i) * 16)) /* _i=0...8 */ +#define i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_max_index 8 +#define i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_shift 0 +#define i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_mask i40e_mask(0xffff, \ + i40e_prtmac_hsec_ctl_tx_pause_refresh_timer_shift) +#define i40e_prtrpb_dhw(_i) (0x000ac100 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtrpb_dhw_dhw_tcn_shift 0 +#define i40e_prtrpb_dhw_dhw_tcn_mask i40e_mask(0xfffff, i40e_prtrpb_dhw_dhw_tcn_shift) +#define i40e_prtrpb_dlw(_i) (0x000ac220 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtrpb_dlw_dlw_tcn_shift 0 +#define i40e_prtrpb_dlw_dlw_tcn_mask i40e_mask(0xfffff, i40e_prtrpb_dlw_dlw_tcn_shift) +#define i40e_prtrpb_dps(_i) (0x000ac320 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtrpb_dps_dps_tcn_shift 0 +#define i40e_prtrpb_dps_dps_tcn_mask i40e_mask(0xfffff, i40e_prtrpb_dps_dps_tcn_shift) +#define i40e_prtrpb_sht(_i) (0x000ac480 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtrpb_sht_sht_tcn_shift 0 +#define i40e_prtrpb_sht_sht_tcn_mask i40e_mask(0xfffff, i40e_prtrpb_sht_sht_tcn_shift) +#define i40e_prtrpb_shw 0x000ac580 /* reset: corer */ +#define i40e_prtrpb_shw_shw_shift 0 +#define i40e_prtrpb_shw_shw_mask i40e_mask(0xfffff, i40e_prtrpb_shw_shw_shift) +#define i40e_prtrpb_slt(_i) (0x000ac5a0 + ((_i) * 32)) /* _i=0...7 */ /* reset: corer */ +#define i40e_prtrpb_slt_slt_tcn_shift 0 +#define i40e_prtrpb_slt_slt_tcn_mask i40e_mask(0xfffff, i40e_prtrpb_slt_slt_tcn_shift) +#define i40e_prtrpb_slw 0x000ac6a0 /* reset: corer */ +#define i40e_prtrpb_slw_slw_shift 0 +#define i40e_prtrpb_slw_slw_mask i40e_mask(0xfffff, i40e_prtrpb_slw_slw_shift) +#define i40e_prtrpb_sps 0x000ac7c0 /* reset: corer */ +#define i40e_prtrpb_sps_sps_shift 0 +#define i40e_prtrpb_sps_sps_mask i40e_mask(0xfffff, i40e_prtrpb_sps_sps_shift) diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h --- a/drivers/net/ethernet/intel/i40e/i40e_type.h +++ b/drivers/net/ethernet/intel/i40e/i40e_type.h -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +#define i40e_dcbx_apps_non_willing 0x1
|
Networking
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90bc8e003be2bf00a1d3223ee9259c1d4d8751f3
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arkadiusz kubalewski
|
drivers
|
net
|
ethernet, i40e, intel
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i40e: add init and default config of software based dcb
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add extra handling on changing the "disable-fw-lldp" private flag to properly initialize software based dcb feature.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add support for software controlled dcb
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['i40e ']
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['h', 'c']
| 3
| 497
| 58
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--- diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h --- a/drivers/net/ethernet/intel/i40e/i40e.h +++ b/drivers/net/ethernet/intel/i40e/i40e.h -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +#define i40e_dcb_prio_type_strict 0 +#define i40e_dcb_prio_type_ets 1 +#define i40e_dcb_strict_prio_credits 127 + struct i40e_rx_pb_config pb_cfg; /* current rx packet buffer config */ + struct i40e_dcbx_config tmp_cfg; +static inline bool i40e_is_sw_dcb(struct i40e_pf *pf) +{ + return !!(pf->flags & i40e_flag_disable_fw_lldp); +} + +void i40e_set_lldp_forwarding(struct i40e_pf *pf, bool enable); +int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg); +int i40e_dcb_sw_default_config(struct i40e_pf *pf); diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c --- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c +++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c - struct i40e_dcbx_config *dcbcfg; - +#ifdef config_i40e_dcb + i40e_dcb_sw_default_config(pf); +#endif /* config_i40e_dcb */ + i40e_aq_cfg_lldp_mib_change_event(&pf->hw, false, null); - i40e_aq_set_dcb_parameters(&pf->hw, true, null); - /* reset local_dcbx_config to default */ - dcbcfg = &pf->hw.local_dcbx_config; - dcbcfg->etscfg.willing = 1; - dcbcfg->etscfg.maxtcs = 0; - dcbcfg->etscfg.tcbwtable[0] = 100; - for (i = 1; i < i40e_max_traffic_class; i++) - dcbcfg->etscfg.tcbwtable[i] = 0; - for (i = 0; i < i40e_max_user_priority; i++) - dcbcfg->etscfg.prioritytable[i] = 0; - dcbcfg->etscfg.tsatable[0] = i40e_ieee_tsa_ets; - dcbcfg->pfc.willing = 1; - dcbcfg->pfc.pfccap = i40e_max_traffic_class; + i40e_set_lldp_forwarding(pf, false); diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c --- a/drivers/net/ethernet/intel/i40e/i40e_main.c +++ b/drivers/net/ethernet/intel/i40e/i40e_main.c -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ -static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired); +static void i40e_prep_for_reset(struct i40e_pf *pf); + memset(&bw_data, 0, sizeof(bw_data)); + memset(&bw_data, 0, sizeof(bw_data)); + if (tc_map == i40e_default_traffic_class) + return; + +/** + * i40e_suspend_port_tx - suspend port tx + * @pf: pf struct + * + * suspend a port's tx and issue a pf reset in case of failure. + **/ +static int i40e_suspend_port_tx(struct i40e_pf *pf) +{ + struct i40e_hw *hw = &pf->hw; + int ret; + + ret = i40e_aq_suspend_port_tx(hw, pf->mac_seid, null); + if (ret) { + dev_info(&pf->pdev->dev, + "suspend port tx failed, err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + /* schedule pf reset to recover */ + set_bit(__i40e_pf_reset_requested, pf->state); + i40e_service_event_schedule(pf); + } + + return ret; +} + +/** + * i40e_hw_set_dcb_config - program new dcbx settings into hw + * @pf: pf being configured + * @new_cfg: new dcbx configuration + * + * program dcb settings into hw and reconfigure veb/vsis on + * given pf. uses "set lldp mib" aqc to program the hardware. + **/ +static int i40e_hw_set_dcb_config(struct i40e_pf *pf, + struct i40e_dcbx_config *new_cfg) +{ + struct i40e_dcbx_config *old_cfg = &pf->hw.local_dcbx_config; + int ret; + + /* check if need reconfiguration */ + if (!memcmp(&new_cfg, &old_cfg, sizeof(new_cfg))) { + dev_dbg(&pf->pdev->dev, "no change in dcb config required. "); + return 0; + } + + /* config change disable all vsis */ + i40e_pf_quiesce_all_vsi(pf); + + /* copy the new config to the current config */ + *old_cfg = *new_cfg; + old_cfg->etsrec = old_cfg->etscfg; + ret = i40e_set_dcb_config(&pf->hw); + if (ret) { + dev_info(&pf->pdev->dev, + "set dcb config failed, err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + goto out; + } + + /* changes in configuration update veb/vsi */ + i40e_dcb_reconfigure(pf); +out: + /* in case of reset do not try to resume anything */ + if (!test_bit(__i40e_reset_recovery_pending, pf->state)) { + /* re-start the vsis if disabled */ + ret = i40e_resume_port_tx(pf); + /* in case of error no point in resuming vsis */ + if (ret) + goto err; + i40e_pf_unquiesce_all_vsi(pf); + } +err: + return ret; +} + +/** + * i40e_hw_dcb_config - program new dcbx settings into hw + * @pf: pf being configured + * @new_cfg: new dcbx configuration + * + * program dcb settings into hw and reconfigure veb/vsis on + * given pf + **/ +int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg) +{ + struct i40e_aqc_configure_switching_comp_ets_data ets_data; + u8 prio_type[i40e_max_traffic_class] = {0}; + u32 mfs_tc[i40e_max_traffic_class]; + struct i40e_dcbx_config *old_cfg; + u8 mode[i40e_max_traffic_class]; + struct i40e_rx_pb_config pb_cfg; + struct i40e_hw *hw = &pf->hw; + u8 num_ports = hw->num_ports; + bool need_reconfig; + int ret = -einval; + u8 lltc_map = 0; + u8 tc_map = 0; + u8 new_numtc; + u8 i; + + dev_dbg(&pf->pdev->dev, "configuring dcb registers directly "); + /* un-pack information to program ets hw via shared api + * numtc, tcmap + * lltc map + * ets/non-ets arbiter mode + * max exponent (credit refills) + * total number of ports + * pfc priority bit-map + * priority table + * bw % per tc + * arbiter mode between ups sharing same tc + * tsa table (ets or non-ets) + * eee enabled or not + * mfs tc table + */ + + new_numtc = i40e_dcb_get_num_tc(new_cfg); + + memset(&ets_data, 0, sizeof(ets_data)); + for (i = 0; i < new_numtc; i++) { + tc_map |= bit(i); + switch (new_cfg->etscfg.tsatable[i]) { + case i40e_ieee_tsa_ets: + prio_type[i] = i40e_dcb_prio_type_ets; + ets_data.tc_bw_share_credits[i] = + new_cfg->etscfg.tcbwtable[i]; + break; + case i40e_ieee_tsa_strict: + prio_type[i] = i40e_dcb_prio_type_strict; + lltc_map |= bit(i); + ets_data.tc_bw_share_credits[i] = + i40e_dcb_strict_prio_credits; + break; + default: + /* invalid tsa type */ + need_reconfig = false; + goto out; + } + } + + old_cfg = &hw->local_dcbx_config; + /* check if need reconfiguration */ + need_reconfig = i40e_dcb_need_reconfig(pf, old_cfg, new_cfg); + + /* if needed, enable/disable frame tagging, disable all vsis + * and suspend port tx + */ + if (need_reconfig) { + /* enable dcb tagging only when more than one tc */ + if (new_numtc > 1) + pf->flags |= i40e_flag_dcb_enabled; + else + pf->flags &= ~i40e_flag_dcb_enabled; + + set_bit(__i40e_port_suspended, pf->state); + /* reconfiguration needed quiesce all vsis */ + i40e_pf_quiesce_all_vsi(pf); + ret = i40e_suspend_port_tx(pf); + if (ret) + goto err; + } + + /* configure port ets tx scheduler */ + ets_data.tc_valid_bits = tc_map; + ets_data.tc_strict_priority_flags = lltc_map; + ret = i40e_aq_config_switch_comp_ets + (hw, pf->mac_seid, &ets_data, + i40e_aqc_opc_modify_switching_comp_ets, null); + if (ret) { + dev_info(&pf->pdev->dev, + "modify port ets failed, err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + goto out; + } + + /* configure rx ets hw */ + memset(&mode, i40e_dcb_arb_mode_round_robin, sizeof(mode)); + i40e_dcb_hw_set_num_tc(hw, new_numtc); + i40e_dcb_hw_rx_fifo_config(hw, i40e_dcb_arb_mode_round_robin, + i40e_dcb_arb_mode_strict_priority, + i40e_dcb_default_max_exponent, + lltc_map); + i40e_dcb_hw_rx_cmd_monitor_config(hw, new_numtc, num_ports); + i40e_dcb_hw_rx_ets_bw_config(hw, new_cfg->etscfg.tcbwtable, mode, + prio_type); + i40e_dcb_hw_pfc_config(hw, new_cfg->pfc.pfcenable, + new_cfg->etscfg.prioritytable); + i40e_dcb_hw_rx_up2tc_config(hw, new_cfg->etscfg.prioritytable); + + /* configure rx packet buffers in hw */ + for (i = 0; i < i40e_max_traffic_class; i++) { + mfs_tc[i] = pf->vsi[pf->lan_vsi]->netdev->mtu; + mfs_tc[i] += i40e_packet_hdr_pad; + } + + i40e_dcb_hw_calculate_pool_sizes(hw, num_ports, + false, new_cfg->pfc.pfcenable, + mfs_tc, &pb_cfg); + i40e_dcb_hw_rx_pb_config(hw, &pf->pb_cfg, &pb_cfg); + + /* update the local rx packet buffer config */ + pf->pb_cfg = pb_cfg; + + /* inform the fw about changes to dcb configuration */ + ret = i40e_aq_dcb_updated(&pf->hw, null); + if (ret) { + dev_info(&pf->pdev->dev, + "dcb updated failed, err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + goto out; + } + + /* update the port dcbx configuration */ + *old_cfg = *new_cfg; + + /* changes in configuration update veb/vsi */ + i40e_dcb_reconfigure(pf); +out: + /* re-start the vsis if disabled */ + if (need_reconfig) { + ret = i40e_resume_port_tx(pf); + + clear_bit(__i40e_port_suspended, pf->state); + /* in case of error no point in resuming vsis */ + if (ret) + goto err; + + /* wait for the pf's queues to be disabled */ + ret = i40e_pf_wait_queues_disabled(pf); + if (ret) { + /* schedule pf reset to recover */ + set_bit(__i40e_pf_reset_requested, pf->state); + i40e_service_event_schedule(pf); + goto err; + } else { + i40e_pf_unquiesce_all_vsi(pf); + set_bit(__i40e_client_service_requested, pf->state); + set_bit(__i40e_client_l2_change, pf->state); + } + /* registers are set, lets apply */ + if (pf->hw_features & i40e_hw_use_set_lldp_mib) + ret = i40e_hw_set_dcb_config(pf, new_cfg); + } + +err: + return ret; +} + +/** + * i40e_dcb_sw_default_config - set default dcb configuration when dcb in sw + * @pf: pf being queried + * + * set default dcb configuration in case dcb is to be done in sw. + **/ +int i40e_dcb_sw_default_config(struct i40e_pf *pf) +{ + struct i40e_dcbx_config *dcb_cfg = &pf->hw.local_dcbx_config; + struct i40e_aqc_configure_switching_comp_ets_data ets_data; + struct i40e_hw *hw = &pf->hw; + int err; + + if (pf->hw_features & i40e_hw_use_set_lldp_mib) { + /* update the local cached instance with tc0 ets */ + memset(&pf->tmp_cfg, 0, sizeof(struct i40e_dcbx_config)); + pf->tmp_cfg.etscfg.willing = i40e_ieee_default_ets_willing; + pf->tmp_cfg.etscfg.maxtcs = 0; + pf->tmp_cfg.etscfg.tcbwtable[0] = i40e_ieee_default_ets_tcbw; + pf->tmp_cfg.etscfg.tsatable[0] = i40e_ieee_tsa_ets; + pf->tmp_cfg.pfc.willing = i40e_ieee_default_pfc_willing; + pf->tmp_cfg.pfc.pfccap = i40e_max_traffic_class; + /* fw needs one app to configure hw */ + pf->tmp_cfg.numapps = i40e_ieee_default_num_apps; + pf->tmp_cfg.app[0].selector = i40e_app_sel_ethtype; + pf->tmp_cfg.app[0].priority = i40e_ieee_default_app_prio; + pf->tmp_cfg.app[0].protocolid = i40e_app_protoid_fcoe; + + return i40e_hw_set_dcb_config(pf, &pf->tmp_cfg); + } + + memset(&ets_data, 0, sizeof(ets_data)); + ets_data.tc_valid_bits = i40e_default_traffic_class; /* tc0 only */ + ets_data.tc_strict_priority_flags = 0; /* ets */ + ets_data.tc_bw_share_credits[0] = i40e_ieee_default_ets_tcbw; /* 100% to tc0 */ + + /* enable ets on the physical port */ + err = i40e_aq_config_switch_comp_ets + (hw, pf->mac_seid, &ets_data, + i40e_aqc_opc_enable_switching_comp_ets, null); + if (err) { + dev_info(&pf->pdev->dev, + "enable port ets failed, err %s aq_err %s ", + i40e_stat_str(&pf->hw, err), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + err = -enoent; + goto out; + } + + /* update the local cached instance with tc0 ets */ + dcb_cfg->etscfg.willing = i40e_ieee_default_ets_willing; + dcb_cfg->etscfg.cbs = 0; + dcb_cfg->etscfg.maxtcs = i40e_max_traffic_class; + dcb_cfg->etscfg.tcbwtable[0] = i40e_ieee_default_ets_tcbw; + +out: + return err; +} + - int err = 0; + int err; - if ((pf->hw_features & i40e_hw_no_dcb_support) || - (pf->flags & i40e_flag_disable_fw_lldp)) { - dev_info(&pf->pdev->dev, "dcb is not supported or fw lldp is disabled "); + if (pf->hw_features & i40e_hw_no_dcb_support) { + dev_info(&pf->pdev->dev, "dcb is not supported. "); - + if (pf->flags & i40e_flag_disable_fw_lldp) { + dev_info(&pf->pdev->dev, "fw lldp is disabled, attempting sw dcb "); + err = i40e_dcb_sw_default_config(pf); + if (err) { + dev_info(&pf->pdev->dev, "could not initialize sw dcb "); + goto out; + } + dev_info(&pf->pdev->dev, "sw dcb initialization succeeded. "); + pf->dcbx_cap = dcb_cap_dcbx_host | + dcb_cap_dcbx_ver_ieee; + /* at init capable but disabled */ + pf->flags |= i40e_flag_dcb_capable; + pf->flags &= ~i40e_flag_dcb_enabled; + goto out; + } +/** + * i40e_set_lldp_forwarding - set forwarding of lldp frames + * @pf: pf being configured + * @enable: if forwarding to os shall be enabled + * + * toggle forwarding of lldp frames behavior, + * when passing dcb control from firmware to software + * lldp frames must be forwarded to the software based + * lldp agent. + */ +void i40e_set_lldp_forwarding(struct i40e_pf *pf, bool enable) +{ + if (pf->lan_vsi == i40e_no_vsi) + return; + + if (!pf->vsi[pf->lan_vsi]) + return; + + /* no need to check the outcome, commands may fail + * if desired value is already set + */ + i40e_aq_add_rem_control_packet_filter(&pf->hw, null, eth_p_lldp, + i40e_aqc_add_control_packet_flags_tx | + i40e_aqc_add_control_packet_flags_ignore_mac, + pf->vsi[pf->lan_vsi]->seid, 0, + enable, null, null); + + i40e_aq_add_rem_control_packet_filter(&pf->hw, null, eth_p_lldp, + i40e_aqc_add_control_packet_flags_rx | + i40e_aqc_add_control_packet_flags_ignore_mac, + pf->vsi[pf->lan_vsi]->seid, 0, + enable, null, null); +} + - - i40e_prep_for_reset(pf, lock_acquired); + i40e_prep_for_reset(pf); + /* x710-t*l 2.5g and 5g speeds don't support dcb */ + if (i40e_is_x710tl_device(hw->device_id) && + (hw->phy.link_info.link_speed & + ~(i40e_link_speed_2_5gb | i40e_link_speed_5gb)) && + !(pf->flags & i40e_flag_dcb_capable)) + /* let firmware decide if the dcb should be disabled */ + pf->flags |= i40e_flag_dcb_capable; + - dev_info(&pf->pdev->dev, - "failed querying dcb configuration data from firmware, err %s aq_err %s ", - i40e_stat_str(&pf->hw, ret), - i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + /* x710-t*l 2.5g and 5g speeds don't support dcb */ + if (i40e_is_x710tl_device(hw->device_id) && + (hw->phy.link_info.link_speed & + (i40e_link_speed_2_5gb | i40e_link_speed_5gb))) { + dev_warn(&pf->pdev->dev, + "dcb is not supported for x710-t*l 2.5/5g speeds "); + pf->flags &= ~i40e_flag_dcb_capable; + } else { + dev_info(&pf->pdev->dev, + "failed querying dcb configuration data from firmware, err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, + pf->hw.aq.asq_last_status)); + } +#ifdef config_i40e_dcb + int err; +#endif /* config_i40e_dcb */ +#ifdef config_i40e_dcb + if (new_link == old_link) + return; + /* not sw dcb so firmware will take care of default settings */ + if (pf->dcbx_cap & dcb_cap_dcbx_lld_managed) + return; + + /* we cover here only link down, as after link up in case of sw dcb + * sw lldp agent will take care of setting it up + */ + if (!new_link) { + dev_dbg(&pf->pdev->dev, "reconfig dcb to single tc as result of link down "); + memset(&pf->tmp_cfg, 0, sizeof(pf->tmp_cfg)); + err = i40e_dcb_sw_default_config(pf); + if (err) { + pf->flags &= ~(i40e_flag_dcb_capable | + i40e_flag_dcb_enabled); + } else { + pf->dcbx_cap = dcb_cap_dcbx_host | + dcb_cap_dcbx_ver_ieee; + pf->flags |= i40e_flag_dcb_capable; + pf->flags &= ~i40e_flag_dcb_enabled; + } + } +#endif /* config_i40e_dcb */ - i40e_prep_for_reset(pf, false); + i40e_prep_for_reset(pf); + rtnl_lock(); + rtnl_unlock(); - * @lock_acquired: indicates whether or not the lock has been acquired - * before this function was called. -static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired) +static void i40e_prep_for_reset(struct i40e_pf *pf) - /* pf_quiesce_all_vsi modifies netdev structures -rtnl_lock needed */ - if (!lock_acquired) - rtnl_lock(); - if (!lock_acquired) - rtnl_unlock(); - /* enable fw to write a default dcb config on link-up */ - i40e_aq_set_dcb_parameters(hw, true, null); - -#ifdef config_i40e_dcb - ret = i40e_init_pf_dcb(pf); - if (ret) { - dev_info(&pf->pdev->dev, "dcb init failed %d, disabled ", ret); - pf->flags &= ~i40e_flag_dcb_capable; - /* continue without dcb enabled */ - } -#endif /* config_i40e_dcb */ - /* do basic switch setup */ +#ifdef config_i40e_dcb + /* enable fw to write a default dcb config on link-up + * unless i40e_flag_tc_mqprio was enabled or dcb + * is not supported with new link speed + */ + if (pf->flags & i40e_flag_tc_mqprio) { + i40e_aq_set_dcb_parameters(hw, false, null); + } else { + if (i40e_is_x710tl_device(hw->device_id) && + (hw->phy.link_info.link_speed & + (i40e_link_speed_2_5gb | i40e_link_speed_5gb))) { + i40e_aq_set_dcb_parameters(hw, false, null); + dev_warn(&pf->pdev->dev, + "dcb is not supported for x710-t*l 2.5/5g speeds "); + pf->flags &= ~i40e_flag_dcb_capable; + } else { + i40e_aq_set_dcb_parameters(hw, true, null); + ret = i40e_init_pf_dcb(pf); + if (ret) { + dev_info(&pf->pdev->dev, "dcb init failed %d, disabled ", + ret); + pf->flags &= ~i40e_flag_dcb_capable; + /* continue without dcb enabled */ + } + } + } + +#endif /* config_i40e_dcb */ + +#ifdef config_i40e_dcb + if (pf->flags & i40e_flag_disable_fw_lldp) + i40e_set_lldp_forwarding(pf, true); +#endif /* config_i40e_dcb */ - i40e_prep_for_reset(pf, lock_acquired); + i40e_prep_for_reset(pf); - i40e_prep_for_reset(pf, true); + i40e_prep_for_reset(pf); - i40e_prep_for_reset(pf, true); + i40e_prep_for_reset(pf); +#ifdef config_i40e_dcb + enum i40e_get_fw_lldp_status_resp lldp_status; + i40e_status status; +#endif /* config_i40e_dcb */ +#ifdef config_i40e_dcb + status = i40e_get_fw_lldp_status(&pf->hw, &lldp_status); + (!status && + lldp_status == i40e_get_fw_lldp_status_enabled) ? + (pf->flags &= ~i40e_flag_disable_fw_lldp) : + (pf->flags |= i40e_flag_disable_fw_lldp); -#ifdef config_i40e_dcb +#ifdef config_i40e_dcb + if (pf->flags & i40e_flag_disable_fw_lldp) + i40e_set_lldp_forwarding(pf, true); +#endif /* config_i40e_dcb */ - i40e_prep_for_reset(pf, false); + i40e_prep_for_reset(pf); - i40e_prep_for_reset(pf, false); + i40e_prep_for_reset(pf); - i40e_prep_for_reset(pf, false); + i40e_prep_for_reset(pf); - i40e_prep_for_reset(pf, true); + i40e_prep_for_reset(pf);
|
Networking
|
4b208eaa8078113ed3f6ba7ecad1ac0a2bad4608
|
arkadiusz kubalewski
|
drivers
|
net
|
ethernet, i40e, intel
|
i40e: add netlink callbacks support for software based dcb
|
add callbacks used by software based lldp agent, which allows to configure dcb feature from userspace.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for software controlled dcb
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['i40e ']
|
['c']
| 1
| 745
| 7
|
--- diff --git a/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c b/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c --- a/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c +++ b/drivers/net/ethernet/intel/i40e/i40e_dcb_nl.c -/* copyright(c) 2013 - 2018 intel corporation. */ +/* copyright(c) 2013 - 2021 intel corporation. */ +#define i40e_dcbnl_status_success 0 +#define i40e_dcbnl_status_error 1 +static bool i40e_dcbnl_find_app(struct i40e_dcbx_config *cfg, + struct i40e_dcb_app_priority_table *app); - struct i40e_hw *hw = &pf->hw; - dcbxcfg = &hw->local_dcbx_config; + dcbxcfg = &pf->hw.local_dcbx_config; - ets->ets_cap = dcbxcfg->etscfg.maxtcs; + ets->ets_cap = i40e_max_traffic_class; - /* get requests/indicatiosn */ + /* get requests/indications */ +/** + * i40e_dcbnl_ieee_setets - set ieee ets configuration + * @netdev: the corresponding netdev + * @ets: structure to hold the ets information + * + * set ieee ets configuration + **/ +static int i40e_dcbnl_ieee_setets(struct net_device *netdev, + struct ieee_ets *ets) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + struct i40e_dcbx_config *old_cfg; + int i, ret; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_ieee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return -einval; + + old_cfg = &pf->hw.local_dcbx_config; + /* copy current config into temp */ + pf->tmp_cfg = *old_cfg; + + /* update the ets configuration for temp */ + pf->tmp_cfg.etscfg.willing = ets->willing; + pf->tmp_cfg.etscfg.maxtcs = i40e_max_traffic_class; + pf->tmp_cfg.etscfg.cbs = ets->cbs; + for (i = 0; i < i40e_max_traffic_class; i++) { + pf->tmp_cfg.etscfg.tcbwtable[i] = ets->tc_tx_bw[i]; + pf->tmp_cfg.etscfg.tsatable[i] = ets->tc_tsa[i]; + pf->tmp_cfg.etscfg.prioritytable[i] = ets->prio_tc[i]; + pf->tmp_cfg.etsrec.tcbwtable[i] = ets->tc_reco_bw[i]; + pf->tmp_cfg.etsrec.tsatable[i] = ets->tc_reco_tsa[i]; + pf->tmp_cfg.etsrec.prioritytable[i] = ets->reco_prio_tc[i]; + } + + /* commit changes to hw */ + ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg); + if (ret) { + dev_info(&pf->pdev->dev, + "failed setting dcb ets configuration err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + return -einval; + } + + return 0; +} + +/** + * i40e_dcbnl_ieee_setpfc - set local ieee pfc configuration + * @netdev: the corresponding netdev + * @pfc: structure to hold the pfc information + * + * sets local ieee pfc configuration + **/ +static int i40e_dcbnl_ieee_setpfc(struct net_device *netdev, + struct ieee_pfc *pfc) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + struct i40e_dcbx_config *old_cfg; + int ret; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_ieee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return -einval; + + old_cfg = &pf->hw.local_dcbx_config; + /* copy current config into temp */ + pf->tmp_cfg = *old_cfg; + if (pfc->pfc_cap) + pf->tmp_cfg.pfc.pfccap = pfc->pfc_cap; + else + pf->tmp_cfg.pfc.pfccap = i40e_max_traffic_class; + pf->tmp_cfg.pfc.pfcenable = pfc->pfc_en; + + ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg); + if (ret) { + dev_info(&pf->pdev->dev, + "failed setting dcb pfc configuration err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + return -einval; + } + + return 0; +} + +/** + * i40e_dcbnl_ieee_setapp - set local ieee app configuration + * @netdev: the corresponding netdev + * @app: structure to hold the application information + * + * sets local ieee app configuration + **/ +static int i40e_dcbnl_ieee_setapp(struct net_device *netdev, + struct dcb_app *app) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + struct i40e_dcb_app_priority_table new_app; + struct i40e_dcbx_config *old_cfg; + int ret; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_ieee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return -einval; + + old_cfg = &pf->hw.local_dcbx_config; + if (old_cfg->numapps == i40e_dcbx_max_apps) + return -einval; + + ret = dcb_ieee_setapp(netdev, app); + if (ret) + return ret; + + new_app.selector = app->selector; + new_app.protocolid = app->protocol; + new_app.priority = app->priority; + /* already internally available */ + if (i40e_dcbnl_find_app(old_cfg, &new_app)) + return 0; + + /* copy current config into temp */ + pf->tmp_cfg = *old_cfg; + /* add the app */ + pf->tmp_cfg.app[pf->tmp_cfg.numapps++] = new_app; + + ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg); + if (ret) { + dev_info(&pf->pdev->dev, + "failed setting dcb configuration err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + return -einval; + } + + return 0; +} + +/** + * i40e_dcbnl_ieee_delapp - delete local ieee app configuration + * @netdev: the corresponding netdev + * @app: structure to hold the application information + * + * deletes local ieee app configuration other than the first application + * required by firmware + **/ +static int i40e_dcbnl_ieee_delapp(struct net_device *netdev, + struct dcb_app *app) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + struct i40e_dcbx_config *old_cfg; + int i, j, ret; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_ieee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return -einval; + + ret = dcb_ieee_delapp(netdev, app); + if (ret) + return ret; + + old_cfg = &pf->hw.local_dcbx_config; + /* need one app for fw so keep it */ + if (old_cfg->numapps == 1) + return 0; + + /* copy current config into temp */ + pf->tmp_cfg = *old_cfg; + + /* find and reset the app */ + for (i = 1; i < pf->tmp_cfg.numapps; i++) { + if (app->selector == pf->tmp_cfg.app[i].selector && + app->protocol == pf->tmp_cfg.app[i].protocolid && + app->priority == pf->tmp_cfg.app[i].priority) { + /* reset the app data */ + pf->tmp_cfg.app[i].selector = 0; + pf->tmp_cfg.app[i].protocolid = 0; + pf->tmp_cfg.app[i].priority = 0; + break; + } + } + + /* if the specific dcb app not found */ + if (i == pf->tmp_cfg.numapps) + return -einval; + + pf->tmp_cfg.numapps--; + /* overwrite the tmp_cfg app */ + for (j = i; j < pf->tmp_cfg.numapps; j++) + pf->tmp_cfg.app[j] = old_cfg->app[j + 1]; + + ret = i40e_hw_dcb_config(pf, &pf->tmp_cfg); + if (ret) { + dev_info(&pf->pdev->dev, + "failed setting dcb configuration err %s aq_err %s ", + i40e_stat_str(&pf->hw, ret), + i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); + return -einval; + } + + return 0; +} + +/** + * i40e_dcbnl_getstate - get dcb enabled state + * @netdev: the corresponding netdev + * + * get the current dcb enabled state + **/ +static u8 i40e_dcbnl_getstate(struct net_device *netdev) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + dev_dbg(&pf->pdev->dev, "dcb state=%d ", + !!(pf->flags & i40e_flag_dcb_enabled)); + return !!(pf->flags & i40e_flag_dcb_enabled); +} + +/** + * i40e_dcbnl_setstate - set dcb state + * @netdev: the corresponding netdev + * @state: enable or disable + * + * set the dcb state + **/ +static u8 i40e_dcbnl_setstate(struct net_device *netdev, u8 state) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + int ret = i40e_dcbnl_status_success; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return ret; + + dev_dbg(&pf->pdev->dev, "new state=%d current state=%d ", + state, (pf->flags & i40e_flag_dcb_enabled) ? 1 : 0); + /* nothing to do */ + if (!state == !(pf->flags & i40e_flag_dcb_enabled)) + return ret; + + if (i40e_is_sw_dcb(pf)) { + if (state) { + pf->flags |= i40e_flag_dcb_enabled; + memcpy(&pf->hw.desired_dcbx_config, + &pf->hw.local_dcbx_config, + sizeof(struct i40e_dcbx_config)); + } else { + pf->flags &= ~i40e_flag_dcb_enabled; + } + } else { + /* cannot directly manipulate fw lldp agent */ + ret = i40e_dcbnl_status_error; + } + return ret; +} + +/** + * i40e_dcbnl_set_pg_tc_cfg_tx - set cee pg tx config + * @netdev: the corresponding netdev + * @tc: the corresponding traffic class + * @prio_type: the traffic priority type + * @bwg_id: the bw group id the traffic class belongs to + * @bw_pct: the bw percentage for the corresponding bwg + * @up_map: prio mapped to corresponding tc + * + * set tx pg settings for cee mode + **/ +static void i40e_dcbnl_set_pg_tc_cfg_tx(struct net_device *netdev, int tc, + u8 prio_type, u8 bwg_id, u8 bw_pct, + u8 up_map) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + int i; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + /* lltc not supported yet */ + if (tc >= i40e_max_traffic_class) + return; + + /* prio_type, bwg_id and bw_pct per up are not supported */ + + /* use only up_map to map tc */ + for (i = 0; i < i40e_max_traffic_class; i++) { + if (up_map & bit(i)) + pf->tmp_cfg.etscfg.prioritytable[i] = tc; + } + pf->tmp_cfg.etscfg.tsatable[tc] = i40e_ieee_tsa_ets; + dev_dbg(&pf->pdev->dev, + "set pg config tc=%d bwg_id=%d prio_type=%d bw_pct=%d up_map=%d ", + tc, bwg_id, prio_type, bw_pct, up_map); +} + +/** + * i40e_dcbnl_set_pg_tc_cfg_tx - set cee pg tx bw config + * @netdev: the corresponding netdev + * @pgid: the corresponding traffic class + * @bw_pct: the bw percentage for the specified traffic class + * + * set tx bw settings for cee mode + **/ +static void i40e_dcbnl_set_pg_bwg_cfg_tx(struct net_device *netdev, int pgid, + u8 bw_pct) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + /* lltc not supported yet */ + if (pgid >= i40e_max_traffic_class) + return; + + pf->tmp_cfg.etscfg.tcbwtable[pgid] = bw_pct; + dev_dbg(&pf->pdev->dev, "set pg bw config tc=%d bw_pct=%d ", + pgid, bw_pct); +} + +/** + * i40e_dcbnl_set_pg_tc_cfg_rx - set cee pg rx config + * @netdev: the corresponding netdev + * @prio: the corresponding traffic class + * @prio_type: the traffic priority type + * @pgid: the bw group id the traffic class belongs to + * @bw_pct: the bw percentage for the corresponding bwg + * @up_map: prio mapped to corresponding tc + * + * set rx bw settings for cee mode. the hardware does not support this + * so we won't allow setting of this parameter. + **/ +static void i40e_dcbnl_set_pg_tc_cfg_rx(struct net_device *netdev, + int __always_unused prio, + u8 __always_unused prio_type, + u8 __always_unused pgid, + u8 __always_unused bw_pct, + u8 __always_unused up_map) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + dev_dbg(&pf->pdev->dev, "rx tc pg config not supported. "); +} + +/** + * i40e_dcbnl_set_pg_bwg_cfg_rx - set cee pg rx config + * @netdev: the corresponding netdev + * @pgid: the corresponding traffic class + * @bw_pct: the bw percentage for the specified traffic class + * + * set rx bw settings for cee mode. the hardware does not support this + * so we won't allow setting of this parameter. + **/ +static void i40e_dcbnl_set_pg_bwg_cfg_rx(struct net_device *netdev, int pgid, + u8 bw_pct) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + dev_dbg(&pf->pdev->dev, "rx bwg pg config not supported. "); +} + +/** + * i40e_dcbnl_get_pg_tc_cfg_tx - get cee pg tx config + * @netdev: the corresponding netdev + * @prio: the corresponding user priority + * @prio_type: traffic priority type + * @pgid: the bw group id the traffic class belongs to + * @bw_pct: bw percentage for the corresponding bwg + * @up_map: prio mapped to corresponding tc + * + * get tx pg settings for cee mode + **/ +static void i40e_dcbnl_get_pg_tc_cfg_tx(struct net_device *netdev, int prio, + u8 __always_unused *prio_type, + u8 *pgid, + u8 __always_unused *bw_pct, + u8 __always_unused *up_map) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + if (prio >= i40e_max_user_priority) + return; + + *pgid = pf->hw.local_dcbx_config.etscfg.prioritytable[prio]; + dev_dbg(&pf->pdev->dev, "get pg config prio=%d tc=%d ", + prio, *pgid); +} + +/** + * i40e_dcbnl_get_pg_bwg_cfg_tx - get cee pg bw config + * @netdev: the corresponding netdev + * @pgid: the corresponding traffic class + * @bw_pct: the bw percentage for the corresponding tc + * + * get tx bw settings for given tc in cee mode + **/ +static void i40e_dcbnl_get_pg_bwg_cfg_tx(struct net_device *netdev, int pgid, + u8 *bw_pct) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + if (pgid >= i40e_max_traffic_class) + return; + + *bw_pct = pf->hw.local_dcbx_config.etscfg.tcbwtable[pgid]; + dev_dbg(&pf->pdev->dev, "get pg bw config tc=%d bw_pct=%d ", + pgid, *bw_pct); +} + +/** + * i40e_dcbnl_get_pg_tc_cfg_rx - get cee pg rx config + * @netdev: the corresponding netdev + * @prio: the corresponding user priority + * @prio_type: the traffic priority type + * @pgid: the pg id + * @bw_pct: the bw percentage for the corresponding bwg + * @up_map: prio mapped to corresponding tc + * + * get rx pg settings for cee mode. the up2tc map is applied in same + * manner for tx and rx (symmetrical) so return the tc information for + * given priority accordingly. + **/ +static void i40e_dcbnl_get_pg_tc_cfg_rx(struct net_device *netdev, int prio, + u8 *prio_type, u8 *pgid, u8 *bw_pct, + u8 *up_map) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + if (prio >= i40e_max_user_priority) + return; + + *pgid = pf->hw.local_dcbx_config.etscfg.prioritytable[prio]; +} + +/** + * i40e_dcbnl_get_pg_bwg_cfg_rx - get cee pg bw rx config + * @netdev: the corresponding netdev + * @pgid: the corresponding traffic class + * @bw_pct: the bw percentage for the corresponding tc + * + * get rx bw settings for given tc in cee mode + * the adapter doesn't support rx ets and runs in strict priority + * mode in rx path and hence just return 0. + **/ +static void i40e_dcbnl_get_pg_bwg_cfg_rx(struct net_device *netdev, int pgid, + u8 *bw_pct) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + *bw_pct = 0; +} + +/** + * i40e_dcbnl_set_pfc_cfg - set cee pfc configuration + * @netdev: the corresponding netdev + * @prio: the corresponding user priority + * @setting: the pfc setting for given priority + * + * set the pfc enabled/disabled setting for given user priority + **/ +static void i40e_dcbnl_set_pfc_cfg(struct net_device *netdev, int prio, + u8 setting) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + if (prio >= i40e_max_user_priority) + return; + + pf->tmp_cfg.pfc.pfccap = i40e_max_traffic_class; + if (setting) + pf->tmp_cfg.pfc.pfcenable |= bit(prio); + else + pf->tmp_cfg.pfc.pfcenable &= ~bit(prio); + dev_dbg(&pf->pdev->dev, + "set pfc config up=%d setting=%d pfcenable=0x%x ", + prio, setting, pf->tmp_cfg.pfc.pfcenable); +} + +/** + * i40e_dcbnl_get_pfc_cfg - get cee pfc configuration + * @netdev: the corresponding netdev + * @prio: the corresponding user priority + * @setting: the pfc setting for given priority + * + * get the pfc enabled/disabled setting for given user priority + **/ +static void i40e_dcbnl_get_pfc_cfg(struct net_device *netdev, int prio, + u8 *setting) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return; + + if (prio >= i40e_max_user_priority) + return; + + *setting = (pf->hw.local_dcbx_config.pfc.pfcenable >> prio) & 0x1; + dev_dbg(&pf->pdev->dev, + "get pfc config up=%d setting=%d pfcenable=0x%x ", + prio, *setting, pf->hw.local_dcbx_config.pfc.pfcenable); +} + +/** + * i40e_dcbnl_cee_set_all - commit cee dcb settings to hardware + * @netdev: the corresponding netdev + * + * commit the current dcb configuration to hardware + **/ +static u8 i40e_dcbnl_cee_set_all(struct net_device *netdev) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + int err; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return i40e_dcbnl_status_error; + + dev_dbg(&pf->pdev->dev, "commit dcb configuration to the hardware "); + err = i40e_hw_dcb_config(pf, &pf->tmp_cfg); + + return err ? i40e_dcbnl_status_error : i40e_dcbnl_status_success; +} + +/** + * i40e_dcbnl_get_cap - get dcbx capabilities of adapter + * @netdev: the corresponding netdev + * @capid: the capability type + * @cap: the capability value + * + * return the capability value for a given capability type + **/ +static u8 i40e_dcbnl_get_cap(struct net_device *netdev, int capid, u8 *cap) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->flags & i40e_flag_dcb_capable)) + return i40e_dcbnl_status_error; + + switch (capid) { + case dcb_cap_attr_pg: + case dcb_cap_attr_pfc: + *cap = true; + break; + case dcb_cap_attr_pg_tcs: + case dcb_cap_attr_pfc_tcs: + *cap = 0x80; + break; + case dcb_cap_attr_dcbx: + *cap = pf->dcbx_cap; + break; + case dcb_cap_attr_up2tc: + case dcb_cap_attr_gsp: + case dcb_cap_attr_bcn: + default: + *cap = false; + break; + } + + dev_dbg(&pf->pdev->dev, "get capability cap=%d capval=0x%x ", + capid, *cap); + return i40e_dcbnl_status_success; +} + +/** + * i40e_dcbnl_getnumtcs - get max number of traffic classes supported + * @netdev: the corresponding netdev + * @tcid: the tc id + * @num: total number of tcs supported by the device + * + * return the total number of tcs supported by the adapter + **/ +static int i40e_dcbnl_getnumtcs(struct net_device *netdev, int tcid, u8 *num) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + if (!(pf->flags & i40e_flag_dcb_capable)) + return -einval; + + *num = i40e_max_traffic_class; + return 0; +} + +/** + * i40e_dcbnl_setnumtcs - set cee number of traffic classes + * @netdev: the corresponding netdev + * @tcid: the tc id + * @num: total number of tcs + * + * set the total number of tcs (unsupported) + **/ +static int i40e_dcbnl_setnumtcs(struct net_device *netdev, int tcid, u8 num) +{ + return -einval; +} + +/** + * i40e_dcbnl_getpfcstate - get cee pfc mode + * @netdev: the corresponding netdev + * + * get the current pfc enabled state + **/ +static u8 i40e_dcbnl_getpfcstate(struct net_device *netdev) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + /* return enabled if any pfc enabled up */ + if (pf->hw.local_dcbx_config.pfc.pfcenable) + return 1; + else + return 0; +} + +/** + * i40e_dcbnl_setpfcstate - set cee pfc mode + * @netdev: the corresponding netdev + * @state: required state + * + * the pfc state to be set; this is enabled/disabled based on the pfc + * priority settings and not via this call for i40e driver + **/ +static void i40e_dcbnl_setpfcstate(struct net_device *netdev, u8 state) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + dev_dbg(&pf->pdev->dev, "pfc state is modified via pfc config. "); +} + +/** + * i40e_dcbnl_getapp - get cee app + * @netdev: the corresponding netdev + * @idtype: the app selector + * @id: the app ethtype or port number + * + * return the cee mode app for the given idtype and id + **/ +static int i40e_dcbnl_getapp(struct net_device *netdev, u8 idtype, u16 id) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + struct dcb_app app = { + .selector = idtype, + .protocol = id, + }; + + if (!(pf->dcbx_cap & dcb_cap_dcbx_ver_cee) || + (pf->dcbx_cap & dcb_cap_dcbx_lld_managed)) + return -einval; + + return dcb_getapp(netdev, &app); +} + +/** + * i40e_dcbnl_setdcbx - set required dcbx capability + * @netdev: the corresponding netdev + * @mode: new dcb mode managed or cee+ieee + * + * set dcbx capability features + **/ +static u8 i40e_dcbnl_setdcbx(struct net_device *netdev, u8 mode) +{ + struct i40e_pf *pf = i40e_netdev_to_pf(netdev); + + /* do not allow to set mode if managed by firmware */ + if (pf->dcbx_cap & dcb_cap_dcbx_lld_managed) + return i40e_dcbnl_status_error; + + /* no support for lld_managed modes or cee+ieee */ + if ((mode & dcb_cap_dcbx_lld_managed) || + ((mode & dcb_cap_dcbx_ver_ieee) && (mode & dcb_cap_dcbx_ver_cee)) || + !(mode & dcb_cap_dcbx_host)) + return i40e_dcbnl_status_error; + + /* already set to the given mode no change */ + if (mode == pf->dcbx_cap) + return i40e_dcbnl_status_success; + + pf->dcbx_cap = mode; + if (mode & dcb_cap_dcbx_ver_cee) + pf->hw.local_dcbx_config.dcbx_mode = i40e_dcbx_mode_cee; + else + pf->hw.local_dcbx_config.dcbx_mode = i40e_dcbx_mode_ieee; + + dev_dbg(&pf->pdev->dev, "mode=%d ", mode); + return i40e_dcbnl_status_success; +} + - .getpermhwaddr = i40e_dcbnl_get_perm_hw_addr, + .getpermhwaddr = i40e_dcbnl_get_perm_hw_addr, + .ieee_setets = i40e_dcbnl_ieee_setets, + .ieee_setpfc = i40e_dcbnl_ieee_setpfc, + .ieee_setapp = i40e_dcbnl_ieee_setapp, + .ieee_delapp = i40e_dcbnl_ieee_delapp, + .getstate = i40e_dcbnl_getstate, + .setstate = i40e_dcbnl_setstate, + .setpgtccfgtx = i40e_dcbnl_set_pg_tc_cfg_tx, + .setpgbwgcfgtx = i40e_dcbnl_set_pg_bwg_cfg_tx, + .setpgtccfgrx = i40e_dcbnl_set_pg_tc_cfg_rx, + .setpgbwgcfgrx = i40e_dcbnl_set_pg_bwg_cfg_rx, + .getpgtccfgtx = i40e_dcbnl_get_pg_tc_cfg_tx, + .getpgbwgcfgtx = i40e_dcbnl_get_pg_bwg_cfg_tx, + .getpgtccfgrx = i40e_dcbnl_get_pg_tc_cfg_rx, + .getpgbwgcfgrx = i40e_dcbnl_get_pg_bwg_cfg_rx, + .setpfccfg = i40e_dcbnl_set_pfc_cfg, + .getpfccfg = i40e_dcbnl_get_pfc_cfg, + .setall = i40e_dcbnl_cee_set_all, + .getcap = i40e_dcbnl_get_cap, + .getnumtcs = i40e_dcbnl_getnumtcs, + .setnumtcs = i40e_dcbnl_setnumtcs, + .getpfcstate = i40e_dcbnl_getpfcstate, + .setpfcstate = i40e_dcbnl_setpfcstate, + .getapp = i40e_dcbnl_getapp, + .setdcbx = i40e_dcbnl_setdcbx, + /* sw dcb taken care by dcbnl set calls */ + if (pf->dcbx_cap & dcb_cap_dcbx_host) + return; + - if ((pf->flags & i40e_flag_mfp_enabled) && !(pf->hw.func_caps.iscsi)) + if ((pf->flags & i40e_flag_mfp_enabled) && !(hw->func_caps.iscsi))
|
Networking
|
5effa78e7c94e66b81659526f5149cb3f6256854
|
arkadiusz kubalewski
|
drivers
|
net
|
ethernet, i40e, intel
|
ice: implement new lldp filter command
|
there is an issue with some nvms where an already existent lldp filter is blocking the creation of a filter to allow lldp packets to be redirected to the default vsi for the interface. this is blocking all lldp functionality based in the kernel when the fw lldp agent is disabled (e.g. software based dcbx).
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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implement a new lldp command that allows adding vsi destinations to existing filters and adds support for netdev bonding event
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ice ']
|
['h', 'c']
| 6
| 82
| 8
|
--- diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +/* lldp filter control (direct 0x0a0a) */ +struct ice_aqc_lldp_filter_ctrl { + u8 cmd_flags; +#define ice_aqc_lldp_filter_action_add 0x0 +#define ice_aqc_lldp_filter_action_delete 0x1 + u8 reserved1; + __le16 vsi_num; + u8 reserved2[12]; +}; + + struct ice_aqc_lldp_filter_ctrl lldp_filter_ctrl; + ice_aqc_opc_lldp_filter_ctrl = 0x0a0a, diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c + +/** + * ice_fw_supports_lldp_fltr - check nvm version supports lldp_fltr_ctrl + * @hw: pointer to hw struct + */ +bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw) +{ + if (hw->mac_type != ice_mac_e810) + return false; + + if (hw->api_maj_ver == ice_fw_api_lldp_fltr_maj) { + if (hw->api_min_ver > ice_fw_api_lldp_fltr_min) + return true; + if (hw->api_min_ver == ice_fw_api_lldp_fltr_min && + hw->api_patch >= ice_fw_api_lldp_fltr_patch) + return true; + } else if (hw->api_maj_ver > ice_fw_api_lldp_fltr_maj) { + return true; + } + return false; +} + +/** + * ice_lldp_fltr_add_remove - add or remove a lldp rx switch filter + * @hw: pointer to hw struct + * @vsi_num: absolute hw index for vsi + * @add: boolean for if adding or removing a filter + */ +enum ice_status +ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add) +{ + struct ice_aqc_lldp_filter_ctrl *cmd; + struct ice_aq_desc desc; + + cmd = &desc.params.lldp_filter_ctrl; + + ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_lldp_filter_ctrl); + + if (add) + cmd->cmd_flags = ice_aqc_lldp_filter_action_add; + else + cmd->cmd_flags = ice_aqc_lldp_filter_action_delete; + + cmd->vsi_num = cpu_to_le16(vsi_num); + + return ice_aq_send_cmd(hw, &desc, null, 0, null); +} diff --git a/drivers/net/ethernet/intel/ice/ice_common.h b/drivers/net/ethernet/intel/ice/ice_common.h --- a/drivers/net/ethernet/intel/ice/ice_common.h +++ b/drivers/net/ethernet/intel/ice/ice_common.h +bool ice_fw_supports_lldp_fltr_ctrl(struct ice_hw *hw); +enum ice_status +ice_lldp_fltr_add_remove(struct ice_hw *hw, u16 vsi_num, bool add); diff --git a/drivers/net/ethernet/intel/ice/ice_ethtool.c b/drivers/net/ethernet/intel/ice/ice_ethtool.c --- a/drivers/net/ethernet/intel/ice/ice_ethtool.c +++ b/drivers/net/ethernet/intel/ice/ice_ethtool.c + /* remove rule to direct lldp packets to default vsi. + * the fw lldp engine will now be consuming them. + */ + ice_cfg_sw_lldp(vsi, false, false); + - /* remove rule to direct lldp packets to default vsi. - * the fw lldp engine will now be consuming them. - */ - ice_cfg_sw_lldp(vsi, false, false); - diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c --- a/drivers/net/ethernet/intel/ice/ice_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_lib.c - if (tx) + if (tx) { - else - status = eth_fltr(vsi, eth_p_lldp, ice_fltr_rx, ice_fwd_to_vsi); + } else { + if (ice_fw_supports_lldp_fltr_ctrl(&pf->hw)) { + status = ice_lldp_fltr_add_remove(&pf->hw, vsi->vsi_num, + create); + } else { + status = eth_fltr(vsi, eth_p_lldp, ice_fltr_rx, + ice_fwd_to_vsi); + } + } diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h +/* aq api version for lldp_filter_control */ +#define ice_fw_api_lldp_fltr_maj 1 +#define ice_fw_api_lldp_fltr_min 7 +#define ice_fw_api_lldp_fltr_patch 1 +
|
Networking
|
34295a3696fbd0d90ee7c62b3162ffdb112b3497
|
dave ertman
|
drivers
|
net
|
ethernet, ice, intel
|
ice: add initial support framework for lag
|
add the framework and initial implementation for receiving and processing netdev bonding events. this is only the software support and the implementation of the hw offload for bonding support will be coming at a later time. there are some architectural gaps that need to be closed before that happens.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement a new lldp command that allows adding vsi destinations to existing filters and adds support for netdev bonding event
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ice ']
|
['h', 'c', 'makefile']
| 7
| 570
| 0
|
--- diff --git a/drivers/net/ethernet/intel/ice/makefile b/drivers/net/ethernet/intel/ice/makefile --- a/drivers/net/ethernet/intel/ice/makefile +++ b/drivers/net/ethernet/intel/ice/makefile + ice_lag.o \ diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h --- a/drivers/net/ethernet/intel/ice/ice.h +++ b/drivers/net/ethernet/intel/ice/ice.h +#include "ice_lag.h" + struct ice_lag *lag; /* link aggregation information */ +/** + * ice_set_sriov_cap - enable sriov in pf flags + * @pf: pf struct + */ +static inline void ice_set_sriov_cap(struct ice_pf *pf) +{ + if (pf->hw.func_caps.common_cap.sr_iov_1_1) + set_bit(ice_flag_sriov_capable, pf->flags); +} + +/** + * ice_clear_sriov_cap - disable sriov in pf flags + * @pf: pf struct + */ +static inline void ice_clear_sriov_cap(struct ice_pf *pf) +{ + clear_bit(ice_flag_sriov_capable, pf->flags); +} + +bool netif_is_ice(struct net_device *dev); diff --git a/drivers/net/ethernet/intel/ice/ice_lag.c b/drivers/net/ethernet/intel/ice/ice_lag.c --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_lag.c +// spdx-license-identifier: gpl-2.0 +/* copyright (c) 2018-2021, intel corporation. */ + +/* link aggregation code */ + +#include "ice.h" +#include "ice_lag.h" + +/** + * ice_lag_nop_handler - no-op rx handler to disable lag + * @pskb: pointer to skb pointer + */ +rx_handler_result_t ice_lag_nop_handler(struct sk_buff __always_unused **pskb) +{ + return rx_handler_pass; +} + +/** + * ice_lag_set_primary - set pf lag state as primary + * @lag: lag info struct + */ +static void ice_lag_set_primary(struct ice_lag *lag) +{ + struct ice_pf *pf = lag->pf; + + if (!pf) + return; + + if (lag->role != ice_lag_unset && lag->role != ice_lag_backup) { + dev_warn(ice_pf_to_dev(pf), "%s: attempt to be primary, but incompatible state. ", + netdev_name(lag->netdev)); + return; + } + + lag->role = ice_lag_primary; +} + +/** + * ice_lag_set_backup - set pf lag state to backup + * @lag: lag info struct + */ +static void ice_lag_set_backup(struct ice_lag *lag) +{ + struct ice_pf *pf = lag->pf; + + if (!pf) + return; + + if (lag->role != ice_lag_unset && lag->role != ice_lag_primary) { + dev_dbg(ice_pf_to_dev(pf), "%s: attempt to be backup, but incompatible state ", + netdev_name(lag->netdev)); + return; + } + + lag->role = ice_lag_backup; +} + +/** + * ice_display_lag_info - print lag info + * @lag: lag info struct + */ +static void ice_display_lag_info(struct ice_lag *lag) +{ + const char *name, *peer, *upper, *role, *bonded, *master; + struct device *dev = &lag->pf->pdev->dev; + + name = lag->netdev ? netdev_name(lag->netdev) : "unset"; + peer = lag->peer_netdev ? netdev_name(lag->peer_netdev) : "unset"; + upper = lag->upper_netdev ? netdev_name(lag->upper_netdev) : "unset"; + master = lag->master ? "true" : "false"; + bonded = lag->bonded ? "bonded" : "unbonded"; + + switch (lag->role) { + case ice_lag_none: + role = "none"; + break; + case ice_lag_primary: + role = "primary"; + break; + case ice_lag_backup: + role = "backup"; + break; + case ice_lag_unset: + role = "unset"; + break; + default: + role = "error"; + } + + dev_dbg(dev, "%s %s, peer:%s, upper:%s, role:%s, master:%s ", name, + bonded, peer, upper, role, master); +} + +/** + * ice_lag_info_event - handle netdev_bonding_info event + * @lag: lag info struct + * @ptr: opaque data pointer + * + * ptr is to be cast to (netdev_notifier_bonding_info *) + */ +static void ice_lag_info_event(struct ice_lag *lag, void *ptr) +{ + struct net_device *event_netdev, *netdev_tmp; + struct netdev_notifier_bonding_info *info; + struct netdev_bonding_info *bonding_info; + const char *lag_netdev_name; + + event_netdev = netdev_notifier_info_to_dev(ptr); + info = ptr; + lag_netdev_name = netdev_name(lag->netdev); + bonding_info = &info->bonding_info; + + if (event_netdev != lag->netdev || !lag->bonded || !lag->upper_netdev) + return; + + if (bonding_info->master.bond_mode != bond_mode_activebackup) { + netdev_dbg(lag->netdev, "bonding event recv, but mode not active/backup "); + goto lag_out; + } + + if (strcmp(bonding_info->slave.slave_name, lag_netdev_name)) { + netdev_dbg(lag->netdev, "bonding event recv, but slave info not for us "); + goto lag_out; + } + + rcu_read_lock(); + for_each_netdev_in_bond_rcu(lag->upper_netdev, netdev_tmp) { + if (!netif_is_ice(netdev_tmp)) + continue; + + if (netdev_tmp && netdev_tmp != lag->netdev && + lag->peer_netdev != netdev_tmp) { + dev_hold(netdev_tmp); + lag->peer_netdev = netdev_tmp; + } + } + rcu_read_unlock(); + + if (bonding_info->slave.state) + ice_lag_set_backup(lag); + else + ice_lag_set_primary(lag); + +lag_out: + ice_display_lag_info(lag); +} + +/** + * ice_lag_link - handle lag link event + * @lag: lag info struct + * @info: info from the netdev notifier + */ +static void +ice_lag_link(struct ice_lag *lag, struct netdev_notifier_changeupper_info *info) +{ + struct net_device *netdev_tmp, *upper = info->upper_dev; + struct ice_pf *pf = lag->pf; + int peers = 0; + + if (lag->bonded) + dev_warn(ice_pf_to_dev(pf), "%s already part of a bond ", + netdev_name(lag->netdev)); + + rcu_read_lock(); + for_each_netdev_in_bond_rcu(upper, netdev_tmp) + peers++; + rcu_read_unlock(); + + if (lag->upper_netdev != upper) { + dev_hold(upper); + lag->upper_netdev = upper; + } + + ice_clear_sriov_cap(pf); + + lag->bonded = true; + lag->role = ice_lag_unset; + + /* if this is the first element in an lag mark as master */ + lag->master = !!(peers == 1); +} + +/** + * ice_lag_unlink - handle unlink event + * @lag: lag info struct + * @info: info from netdev notification + */ +static void +ice_lag_unlink(struct ice_lag *lag, + struct netdev_notifier_changeupper_info *info) +{ + struct net_device *netdev_tmp, *upper = info->upper_dev; + struct ice_pf *pf = lag->pf; + bool found = false; + + if (!lag->bonded) { + netdev_dbg(lag->netdev, "bonding unlink event on non-lag netdev "); + return; + } + + /* determine if we are in the new lag config or not */ + rcu_read_lock(); + for_each_netdev_in_bond_rcu(upper, netdev_tmp) { + if (netdev_tmp == lag->netdev) { + found = true; + break; + } + } + rcu_read_unlock(); + + if (found) + return; + + if (lag->upper_netdev) { + dev_put(lag->upper_netdev); + lag->upper_netdev = null; + } + + if (lag->peer_netdev) { + dev_put(lag->peer_netdev); + lag->peer_netdev = null; + } + + ice_set_sriov_cap(pf); + lag->bonded = false; + lag->role = ice_lag_none; +} + +/** + * ice_lag_changeupper_event - handle lag changeupper event + * @lag: lag info struct + * @ptr: opaque pointer data + * + * ptr is to be cast into netdev_notifier_changeupper_info + */ +static void ice_lag_changeupper_event(struct ice_lag *lag, void *ptr) +{ + struct netdev_notifier_changeupper_info *info; + struct net_device *netdev; + + info = ptr; + netdev = netdev_notifier_info_to_dev(ptr); + + /* not for this netdev */ + if (netdev != lag->netdev) + return; + + if (!info->upper_dev) { + netdev_dbg(netdev, "changeupper rcvd, but no upper defined "); + return; + } + + netdev_dbg(netdev, "bonding %s ", info->linking ? "link" : "unlink"); + + if (!netif_is_lag_master(info->upper_dev)) { + netdev_dbg(netdev, "changeupper rcvd, but not master. bail "); + return; + } + + if (info->linking) + ice_lag_link(lag, info); + else + ice_lag_unlink(lag, info); + + ice_display_lag_info(lag); +} + +/** + * ice_lag_changelower_event - handle lag changelower event + * @lag: lag info struct + * @ptr: opaque data pointer + * + * ptr to be cast to netdev_notifier_changelowerstate_info + */ +static void ice_lag_changelower_event(struct ice_lag *lag, void *ptr) +{ + struct net_device *netdev = netdev_notifier_info_to_dev(ptr); + + if (netdev != lag->netdev) + return; + + netdev_dbg(netdev, "bonding info "); + + if (!netif_is_lag_port(netdev)) + netdev_dbg(netdev, "changelower rcvd, but netdev not in lag. bail "); +} + +/** + * ice_lag_event_handler - handle lag events from netdev + * @notif_blk: notifier block registered by this netdev + * @event: event type + * @ptr: opaque data containing notifier event + */ +static int +ice_lag_event_handler(struct notifier_block *notif_blk, unsigned long event, + void *ptr) +{ + struct net_device *netdev = netdev_notifier_info_to_dev(ptr); + struct ice_lag *lag; + + lag = container_of(notif_blk, struct ice_lag, notif_block); + + if (!lag->netdev) + return notify_done; + + /* check that the netdev is in the working namespace */ + if (!net_eq(dev_net(netdev), &init_net)) + return notify_done; + + switch (event) { + case netdev_changeupper: + ice_lag_changeupper_event(lag, ptr); + break; + case netdev_changelowerstate: + ice_lag_changelower_event(lag, ptr); + break; + case netdev_bonding_info: + ice_lag_info_event(lag, ptr); + break; + default: + break; + } + + return notify_done; +} + +/** + * ice_register_lag_handler - register lag handler on netdev + * @lag: lag struct + */ +static int ice_register_lag_handler(struct ice_lag *lag) +{ + struct device *dev = ice_pf_to_dev(lag->pf); + struct notifier_block *notif_blk; + + notif_blk = &lag->notif_block; + + if (!notif_blk->notifier_call) { + notif_blk->notifier_call = ice_lag_event_handler; + if (register_netdevice_notifier(notif_blk)) { + notif_blk->notifier_call = null; + dev_err(dev, "fail register lag event handler! "); + return -einval; + } + dev_dbg(dev, "lag event handler registered "); + } + return 0; +} + +/** + * ice_unregister_lag_handler - unregister lag handler on netdev + * @lag: lag struct + */ +static void ice_unregister_lag_handler(struct ice_lag *lag) +{ + struct device *dev = ice_pf_to_dev(lag->pf); + struct notifier_block *notif_blk; + + notif_blk = &lag->notif_block; + if (notif_blk->notifier_call) { + unregister_netdevice_notifier(notif_blk); + dev_dbg(dev, "lag event handler unregistered "); + } +} + +/** + * ice_init_lag - initialize support for lag + * @pf: pf struct + * + * alloc memory for lag structs and initialize the elements. + * memory will be freed in ice_deinit_lag + */ +int ice_init_lag(struct ice_pf *pf) +{ + struct device *dev = ice_pf_to_dev(pf); + struct ice_lag *lag; + struct ice_vsi *vsi; + int err; + + pf->lag = kzalloc(sizeof(*lag), gfp_kernel); + if (!pf->lag) + return -enomem; + lag = pf->lag; + + vsi = ice_get_main_vsi(pf); + if (!vsi) { + dev_err(dev, "couldn't get main vsi, link aggregation init fail "); + err = -eio; + goto lag_error; + } + + lag->pf = pf; + lag->netdev = vsi->netdev; + lag->role = ice_lag_none; + lag->bonded = false; + lag->peer_netdev = null; + lag->upper_netdev = null; + lag->notif_block.notifier_call = null; + + err = ice_register_lag_handler(lag); + if (err) { + dev_warn(dev, "init lag: failed to register event handler "); + goto lag_error; + } + + ice_display_lag_info(lag); + + dev_dbg(dev, "init lag complete "); + return 0; + +lag_error: + kfree(lag); + pf->lag = null; + return err; +} + +/** + * ice_deinit_lag - clean up lag + * @pf: pf struct + * + * clean up kernel lag info and free memory + * this function is meant to only be called on driver remove/shutdown + */ +void ice_deinit_lag(struct ice_pf *pf) +{ + struct ice_lag *lag; + + lag = pf->lag; + + if (!lag) + return; + + if (lag->pf) + ice_unregister_lag_handler(lag); + + if (lag->upper_netdev) + dev_put(lag->upper_netdev); + + if (lag->peer_netdev) + dev_put(lag->peer_netdev); + + kfree(lag); + + pf->lag = null; +} diff --git a/drivers/net/ethernet/intel/ice/ice_lag.h b/drivers/net/ethernet/intel/ice/ice_lag.h --- /dev/null +++ b/drivers/net/ethernet/intel/ice/ice_lag.h +/* spdx-license-identifier: gpl-2.0 */ +/* copyright (c) 2018-2021, intel corporation. */ + +#ifndef _ice_lag_h_ +#define _ice_lag_h_ + +#include <linux/netdevice.h> + +/* lag roles for netdev */ +enum ice_lag_role { + ice_lag_none, + ice_lag_primary, + ice_lag_backup, + ice_lag_unset +}; + +struct ice_pf; + +/* lag info struct */ +struct ice_lag { + struct ice_pf *pf; /* backlink to pf struct */ + struct net_device *netdev; /* this pf's netdev */ + struct net_device *peer_netdev; + struct net_device *upper_netdev; /* upper bonding netdev */ + struct notifier_block notif_block; + u8 bonded:1; /* currently bonded */ + u8 master:1; /* this is a master */ + u8 handler:1; /* did we register a rx_netdev_handler */ + /* each thing blocking bonding will increment this value by one. + * if this value is zero, then bonding is allowed. + */ + u16 dis_lag; + u8 role; +}; + +int ice_init_lag(struct ice_pf *pf); +void ice_deinit_lag(struct ice_pf *pf); +rx_handler_result_t ice_lag_nop_handler(struct sk_buff **pskb); + +/** + * ice_disable_lag - increment lag disable count + * @lag: lag struct + */ +static inline void ice_disable_lag(struct ice_lag *lag) +{ + /* if lag this pf is not already disabled, disable it */ + rtnl_lock(); + if (!netdev_is_rx_handler_busy(lag->netdev)) { + if (!netdev_rx_handler_register(lag->netdev, + ice_lag_nop_handler, + null)) + lag->handler = true; + } + rtnl_unlock(); + lag->dis_lag++; +} + +/** + * ice_enable_lag - decrement disable count for a pf + * @lag: lag struct + * + * decrement the disable counter for a port, and if that count reaches + * zero, then remove the no-op rx handler from that netdev + */ +static inline void ice_enable_lag(struct ice_lag *lag) +{ + if (lag->dis_lag) + lag->dis_lag--; + if (!lag->dis_lag && lag->handler) { + rtnl_lock(); + netdev_rx_handler_unregister(lag->netdev); + rtnl_unlock(); + lag->handler = false; + } +} + +/** + * ice_is_lag_dis - is lag disabled + * @lag: lag struct + * + * return true if bonding is disabled + */ +static inline bool ice_is_lag_dis(struct ice_lag *lag) +{ + return !!(lag->dis_lag); +} +#endif /* _ice_lag_h_ */ diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c --- a/drivers/net/ethernet/intel/ice/ice_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_lib.c + if (vsi_type == ice_vsi_vf) + ice_enable_lag(pf->lag); diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c +bool netif_is_ice(struct net_device *dev) +{ + return dev && (dev->netdev_ops == &ice_netdev_ops); +} + + if (ice_init_lag(pf)) + dev_warn(dev, "failed to init link aggregation support "); + + ice_deinit_lag(pf); diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c --- a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c +++ b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c + if (pf->lag) + ice_enable_lag(pf->lag); + if (pf->lag) + ice_disable_lag(pf->lag);
|
Networking
|
df006dd4b1dca8c486f73ae76fb77c06afae83f2
|
dave ertman
|
drivers
|
net
|
ethernet, ice, intel
|
ice: create scheduler aggregator node config and move vsis
|
create set scheduler aggregator node and move for vsis into respective scheduler node. max children per aggregator node is 64.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement the creation scheduler aggregator nodes and distributing vsis within the nodes
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ice ']
|
['h', 'c']
| 9
| 1,207
| 20
|
--- diff --git a/drivers/net/ethernet/intel/ice/ice.h b/drivers/net/ethernet/intel/ice/ice.h --- a/drivers/net/ethernet/intel/ice/ice.h +++ b/drivers/net/ethernet/intel/ice/ice.h + + /* setup back reference, to which aggregator node this vsi + * corresponds to + */ + struct ice_agg_node *agg_node; +struct ice_agg_node { + u32 agg_id; +#define ice_max_vsis_in_agg_node 64 + u32 num_vsis; + u8 valid; +}; + + +#define ice_invalid_agg_node_id 0 +#define ice_pf_agg_node_id_start 1 +#define ice_max_pf_agg_nodes 32 + struct ice_agg_node pf_agg_node[ice_max_pf_agg_nodes]; +#define ice_vf_agg_node_id_start 65 +#define ice_max_vf_agg_nodes 32 + struct ice_agg_node vf_agg_node[ice_max_vf_agg_nodes]; diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +struct ice_aqc_txsched_move_grp_info_hdr { + __le32 src_parent_teid; + __le32 dest_parent_teid; + __le16 num_elems; + __le16 reserved; +}; + +struct ice_aqc_move_elem { + struct ice_aqc_txsched_move_grp_info_hdr hdr; + __le32 teid[]; +}; + + ice_aqc_opc_move_sched_elems = 0x0408, diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c --- a/drivers/net/ethernet/intel/ice/ice_common.c +++ b/drivers/net/ethernet/intel/ice/ice_common.c + ice_sched_replay_agg_vsi_preinit(hw); + if (!status) + status = ice_replay_vsi_agg(hw, vsi_handle); + ice_sched_replay_agg(hw); diff --git a/drivers/net/ethernet/intel/ice/ice_lib.c b/drivers/net/ethernet/intel/ice/ice_lib.c --- a/drivers/net/ethernet/intel/ice/ice_lib.c +++ b/drivers/net/ethernet/intel/ice/ice_lib.c +/** + * ice_set_agg_vsi - sets up scheduler aggregator node and move vsi into it + * @vsi: pointer to the vsi + * + * this function will allocate new scheduler aggregator now if needed and will + * move specified vsi into it. + */ +static void ice_set_agg_vsi(struct ice_vsi *vsi) +{ + struct device *dev = ice_pf_to_dev(vsi->back); + struct ice_agg_node *agg_node_iter = null; + u32 agg_id = ice_invalid_agg_node_id; + struct ice_agg_node *agg_node = null; + int node_offset, max_agg_nodes = 0; + struct ice_port_info *port_info; + struct ice_pf *pf = vsi->back; + u32 agg_node_id_start = 0; + enum ice_status status; + + /* create (as needed) scheduler aggregator node and move vsi into + * corresponding aggregator node + * - pf aggregator node to contains vsis of type _pf and _ctrl + * - vf aggregator nodes will contain vf vsi + */ + port_info = pf->hw.port_info; + if (!port_info) + return; + + switch (vsi->type) { + case ice_vsi_ctrl: + case ice_vsi_lb: + case ice_vsi_pf: + max_agg_nodes = ice_max_pf_agg_nodes; + agg_node_id_start = ice_pf_agg_node_id_start; + agg_node_iter = &pf->pf_agg_node[0]; + break; + case ice_vsi_vf: + /* user can create 'n' vfs on a given pf, but since max children + * per aggregator node can be only 64. following code handles + * aggregator(s) for vf vsis, either selects a agg_node which + * was already created provided num_vsis < 64, otherwise + * select next available node, which will be created + */ + max_agg_nodes = ice_max_vf_agg_nodes; + agg_node_id_start = ice_vf_agg_node_id_start; + agg_node_iter = &pf->vf_agg_node[0]; + break; + default: + /* other vsi type, handle later if needed */ + dev_dbg(dev, "unexpected vsi type %s ", + ice_vsi_type_str(vsi->type)); + return; + } + + /* find the appropriate aggregator node */ + for (node_offset = 0; node_offset < max_agg_nodes; node_offset++) { + /* see if we can find space in previously created + * node if num_vsis < 64, otherwise skip + */ + if (agg_node_iter->num_vsis && + agg_node_iter->num_vsis == ice_max_vsis_in_agg_node) { + agg_node_iter++; + continue; + } + + if (agg_node_iter->valid && + agg_node_iter->agg_id != ice_invalid_agg_node_id) { + agg_id = agg_node_iter->agg_id; + agg_node = agg_node_iter; + break; + } + + /* find unclaimed agg_id */ + if (agg_node_iter->agg_id == ice_invalid_agg_node_id) { + agg_id = node_offset + agg_node_id_start; + agg_node = agg_node_iter; + break; + } + /* move to next agg_node */ + agg_node_iter++; + } + + if (!agg_node) + return; + + /* if selected aggregator node was not created, create it */ + if (!agg_node->valid) { + status = ice_cfg_agg(port_info, agg_id, ice_agg_type_agg, + (u8)vsi->tc_cfg.ena_tc); + if (status) { + dev_err(dev, "unable to create aggregator node with agg_id %u ", + agg_id); + return; + } + /* aggregator node is created, store the neeeded info */ + agg_node->valid = true; + agg_node->agg_id = agg_id; + } + + /* move vsi to corresponding aggregator node */ + status = ice_move_vsi_to_agg(port_info, agg_id, vsi->idx, + (u8)vsi->tc_cfg.ena_tc); + if (status) { + dev_err(dev, "unable to move vsi idx %u into aggregator %u node", + vsi->idx, agg_id); + return; + } + + /* keep active children count for aggregator node */ + agg_node->num_vsis++; + + /* cache the 'agg_id' in vsi, so that after reset - vsi will be moved + * to aggregator node + */ + vsi->agg_node = agg_node; + dev_dbg(dev, "successfully moved vsi idx %u tc_bitmap 0x%x) into aggregator node %d which has num_vsis %u ", + vsi->idx, vsi->tc_cfg.ena_tc, vsi->agg_node->agg_id, + vsi->agg_node->num_vsis); +} + + if (!vsi->agg_node) + ice_set_agg_vsi(vsi); + if (vsi->type == ice_vsi_vf && + vsi->agg_node && vsi->agg_node->valid) + vsi->agg_node->num_vsis--; diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c + int node; + + for (node = 0; node < ice_max_pf_agg_nodes; node++) + pf->pf_agg_node[node].num_vsis = 0; + + for (node = 0; node < ice_max_vf_agg_nodes; node++) + pf->vf_agg_node[node].num_vsis = 0; + diff --git a/drivers/net/ethernet/intel/ice/ice_sched.c b/drivers/net/ethernet/intel/ice/ice_sched.c --- a/drivers/net/ethernet/intel/ice/ice_sched.c +++ b/drivers/net/ethernet/intel/ice/ice_sched.c +/** + * ice_aq_move_sched_elems - move scheduler elements + * @hw: pointer to the hw struct + * @grps_req: number of groups to move + * @buf: pointer to buffer + * @buf_size: buffer size in bytes + * @grps_movd: returns total number of groups moved + * @cd: pointer to command details structure or null + * + * move scheduling elements (0x0408) + */ +static enum ice_status +ice_aq_move_sched_elems(struct ice_hw *hw, u16 grps_req, + struct ice_aqc_move_elem *buf, u16 buf_size, + u16 *grps_movd, struct ice_sq_cd *cd) +{ + return ice_aqc_send_sched_elem_cmd(hw, ice_aqc_opc_move_sched_elems, + grps_req, (void *)buf, buf_size, + grps_movd, cd); +} + +/** + * ice_sched_get_agg_layer - get the current aggregator layer number + * @hw: pointer to the hw struct + * + * this function returns the current aggregator layer number + */ +static u8 ice_sched_get_agg_layer(struct ice_hw *hw) +{ + /* num layers aggregator layer + * 9 4 + * 7 or less sw_entry_point_layer + */ + /* calculate the aggregator layer based on number of layers. */ + if (hw->num_tx_sched_layers > ice_agg_layer_offset + 1) { + u8 layer = hw->num_tx_sched_layers - ice_agg_layer_offset; + + if (layer > hw->sw_entry_point_layer) + return layer; + } + return hw->sw_entry_point_layer; +} + - * @hw: pointer to the hw struct + * @pi: pointer to the port information structure -ice_sched_get_vsi_node(struct ice_hw *hw, struct ice_sched_node *tc_node, +ice_sched_get_vsi_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, - vsi_layer = ice_sched_get_vsi_layer(hw); - node = ice_sched_get_first_node(hw->port_info, tc_node, vsi_layer); + vsi_layer = ice_sched_get_vsi_layer(pi->hw); + node = ice_sched_get_first_node(pi, tc_node, vsi_layer); +/** + * ice_sched_get_agg_node - get an aggregator node based on aggregator id + * @pi: pointer to the port information structure + * @tc_node: pointer to the tc node + * @agg_id: aggregator id + * + * this function retrieves an aggregator node for a given aggregator id from + * a given tc branch + */ +static struct ice_sched_node * +ice_sched_get_agg_node(struct ice_port_info *pi, struct ice_sched_node *tc_node, + u32 agg_id) +{ + struct ice_sched_node *node; + struct ice_hw *hw = pi->hw; + u8 agg_layer; + + if (!hw) + return null; + agg_layer = ice_sched_get_agg_layer(hw); + node = ice_sched_get_first_node(pi, tc_node, agg_layer); + + /* check whether it already exists */ + while (node) { + if (node->agg_id == agg_id) + return node; + node = node->sibling; + } + + return node; +} + - parent = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); + parent = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); - * @hw: pointer to the hw struct + * @pi: pointer to the port info structure -ice_sched_calc_vsi_support_nodes(struct ice_hw *hw, +ice_sched_calc_vsi_support_nodes(struct ice_port_info *pi, - vsil = ice_sched_get_vsi_layer(hw); - for (i = vsil; i >= hw->sw_entry_point_layer; i--) + vsil = ice_sched_get_vsi_layer(pi->hw); + for (i = vsil; i >= pi->hw->sw_entry_point_layer; i--) - node = ice_sched_get_first_node(hw->port_info, tc_node, - (u8)i); + node = ice_sched_get_first_node(pi, tc_node, (u8)i); - if (node->num_children < hw->max_children[i]) + if (node->num_children < pi->hw->max_children[i]) - struct ice_hw *hw = pi->hw; - ice_sched_calc_vsi_support_nodes(hw, tc_node, num_nodes); + ice_sched_calc_vsi_support_nodes(pi, tc_node, num_nodes); - vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); + vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); - vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); + vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); - vsi_node = ice_sched_get_vsi_node(hw, tc_node, vsi_handle); + vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); - vsi_node = ice_sched_get_vsi_node(pi->hw, tc_node, vsi_handle); + vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); +/** + * ice_get_agg_info - get the aggregator id + * @hw: pointer to the hardware structure + * @agg_id: aggregator id + * + * this function validates aggregator id. the function returns info if + * aggregator id is present in list otherwise it returns null. + */ +static struct ice_sched_agg_info * +ice_get_agg_info(struct ice_hw *hw, u32 agg_id) +{ + struct ice_sched_agg_info *agg_info; + + list_for_each_entry(agg_info, &hw->agg_list, list_entry) + if (agg_info->agg_id == agg_id) + return agg_info; + + return null; +} + +/** + * ice_sched_get_free_vsi_parent - find a free parent node in aggregator subtree + * @hw: pointer to the hw struct + * @node: pointer to a child node + * @num_nodes: num nodes count array + * + * this function walks through the aggregator subtree to find a free parent + * node + */ +static struct ice_sched_node * +ice_sched_get_free_vsi_parent(struct ice_hw *hw, struct ice_sched_node *node, + u16 *num_nodes) +{ + u8 l = node->tx_sched_layer; + u8 vsil, i; + + vsil = ice_sched_get_vsi_layer(hw); + + /* is it vsi parent layer ? */ + if (l == vsil - 1) + return (node->num_children < hw->max_children[l]) ? node : null; + + /* we have intermediate nodes. let's walk through the subtree. if the + * intermediate node has space to add a new node then clear the count + */ + if (node->num_children < hw->max_children[l]) + num_nodes[l] = 0; + /* the below recursive call is intentional and wouldn't go more than + * 2 or 3 iterations. + */ + + for (i = 0; i < node->num_children; i++) { + struct ice_sched_node *parent; + + parent = ice_sched_get_free_vsi_parent(hw, node->children[i], + num_nodes); + if (parent) + return parent; + } + + return null; +} + +/** + * ice_sched_update_parent - update the new parent in sw db + * @new_parent: pointer to a new parent node + * @node: pointer to a child node + * + * this function removes the child from the old parent and adds it to a new + * parent + */ +static void +ice_sched_update_parent(struct ice_sched_node *new_parent, + struct ice_sched_node *node) +{ + struct ice_sched_node *old_parent; + u8 i, j; + + old_parent = node->parent; + + /* update the old parent children */ + for (i = 0; i < old_parent->num_children; i++) + if (old_parent->children[i] == node) { + for (j = i + 1; j < old_parent->num_children; j++) + old_parent->children[j - 1] = + old_parent->children[j]; + old_parent->num_children--; + break; + } + + /* now move the node to a new parent */ + new_parent->children[new_parent->num_children++] = node; + node->parent = new_parent; + node->info.parent_teid = new_parent->info.node_teid; +} + +/** + * ice_sched_move_nodes - move child nodes to a given parent + * @pi: port information structure + * @parent: pointer to parent node + * @num_items: number of child nodes to be moved + * @list: pointer to child node teids + * + * this function move the child nodes to a given parent. + */ +static enum ice_status +ice_sched_move_nodes(struct ice_port_info *pi, struct ice_sched_node *parent, + u16 num_items, u32 *list) +{ + struct ice_aqc_move_elem *buf; + struct ice_sched_node *node; + enum ice_status status = 0; + u16 i, grps_movd = 0; + struct ice_hw *hw; + u16 buf_len; + + hw = pi->hw; + + if (!parent || !num_items) + return ice_err_param; + + /* does parent have enough space */ + if (parent->num_children + num_items > + hw->max_children[parent->tx_sched_layer]) + return ice_err_aq_full; + + buf_len = struct_size(buf, teid, 1); + buf = kzalloc(buf_len, gfp_kernel); + if (!buf) + return ice_err_no_memory; + + for (i = 0; i < num_items; i++) { + node = ice_sched_find_node_by_teid(pi->root, list[i]); + if (!node) { + status = ice_err_param; + goto move_err_exit; + } + + buf->hdr.src_parent_teid = node->info.parent_teid; + buf->hdr.dest_parent_teid = parent->info.node_teid; + buf->teid[0] = node->info.node_teid; + buf->hdr.num_elems = cpu_to_le16(1); + status = ice_aq_move_sched_elems(hw, 1, buf, buf_len, + &grps_movd, null); + if (status && grps_movd != 1) { + status = ice_err_cfg; + goto move_err_exit; + } + + /* update the sw db */ + ice_sched_update_parent(parent, node); + } + +move_err_exit: + kfree(buf); + return status; +} + +/** + * ice_sched_move_vsi_to_agg - move vsi to aggregator node + * @pi: port information structure + * @vsi_handle: software vsi handle + * @agg_id: aggregator id + * @tc: tc number + * + * this function moves a vsi to an aggregator node or its subtree. + * intermediate nodes may be created if required. + */ +static enum ice_status +ice_sched_move_vsi_to_agg(struct ice_port_info *pi, u16 vsi_handle, u32 agg_id, + u8 tc) +{ + struct ice_sched_node *vsi_node, *agg_node, *tc_node, *parent; + u16 num_nodes[ice_aqc_topo_max_level_num] = { 0 }; + u32 first_node_teid, vsi_teid; + enum ice_status status; + u16 num_nodes_added; + u8 aggl, vsil, i; + + tc_node = ice_sched_get_tc_node(pi, tc); + if (!tc_node) + return ice_err_cfg; + + agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); + if (!agg_node) + return ice_err_does_not_exist; + + vsi_node = ice_sched_get_vsi_node(pi, tc_node, vsi_handle); + if (!vsi_node) + return ice_err_does_not_exist; + + /* is this vsi already part of given aggregator? */ + if (ice_sched_find_node_in_subtree(pi->hw, agg_node, vsi_node)) + return 0; + + aggl = ice_sched_get_agg_layer(pi->hw); + vsil = ice_sched_get_vsi_layer(pi->hw); + + /* set intermediate node count to 1 between aggregator and vsi layers */ + for (i = aggl + 1; i < vsil; i++) + num_nodes[i] = 1; + + /* check if the aggregator subtree has any free node to add the vsi */ + for (i = 0; i < agg_node->num_children; i++) { + parent = ice_sched_get_free_vsi_parent(pi->hw, + agg_node->children[i], + num_nodes); + if (parent) + goto move_nodes; + } + + /* add new nodes */ + parent = agg_node; + for (i = aggl + 1; i < vsil; i++) { + status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, + num_nodes[i], + &first_node_teid, + &num_nodes_added); + if (status || num_nodes[i] != num_nodes_added) + return ice_err_cfg; + + /* the newly added node can be a new parent for the next + * layer nodes + */ + if (num_nodes_added) + parent = ice_sched_find_node_by_teid(tc_node, + first_node_teid); + else + parent = parent->children[0]; + + if (!parent) + return ice_err_cfg; + } + +move_nodes: + vsi_teid = le32_to_cpu(vsi_node->info.node_teid); + return ice_sched_move_nodes(pi, parent, 1, &vsi_teid); +} + +/** + * ice_move_all_vsi_to_dflt_agg - move all vsi(s) to default aggregator + * @pi: port information structure + * @agg_info: aggregator info + * @tc: traffic class number + * @rm_vsi_info: true or false + * + * this function move all the vsi(s) to the default aggregator and delete + * aggregator vsi info based on passed in boolean parameter rm_vsi_info. the + * caller holds the scheduler lock. + */ +static enum ice_status +ice_move_all_vsi_to_dflt_agg(struct ice_port_info *pi, + struct ice_sched_agg_info *agg_info, u8 tc, + bool rm_vsi_info) +{ + struct ice_sched_agg_vsi_info *agg_vsi_info; + struct ice_sched_agg_vsi_info *tmp; + enum ice_status status = 0; + + list_for_each_entry_safe(agg_vsi_info, tmp, &agg_info->agg_vsi_list, + list_entry) { + u16 vsi_handle = agg_vsi_info->vsi_handle; + + /* move vsi to default aggregator */ + if (!ice_is_tc_ena(agg_vsi_info->tc_bitmap[0], tc)) + continue; + + status = ice_sched_move_vsi_to_agg(pi, vsi_handle, + ice_dflt_agg_id, tc); + if (status) + break; + + clear_bit(tc, agg_vsi_info->tc_bitmap); + if (rm_vsi_info && !agg_vsi_info->tc_bitmap[0]) { + list_del(&agg_vsi_info->list_entry); + devm_kfree(ice_hw_to_dev(pi->hw), agg_vsi_info); + } + } + + return status; +} + +/** + * ice_sched_is_agg_inuse - check whether the aggregator is in use or not + * @pi: port information structure + * @node: node pointer + * + * this function checks whether the aggregator is attached with any vsi or not. + */ +static bool +ice_sched_is_agg_inuse(struct ice_port_info *pi, struct ice_sched_node *node) +{ + u8 vsil, i; + + vsil = ice_sched_get_vsi_layer(pi->hw); + if (node->tx_sched_layer < vsil - 1) { + for (i = 0; i < node->num_children; i++) + if (ice_sched_is_agg_inuse(pi, node->children[i])) + return true; + return false; + } else { + return node->num_children ? true : false; + } +} + +/** + * ice_sched_rm_agg_cfg - remove the aggregator node + * @pi: port information structure + * @agg_id: aggregator id + * @tc: tc number + * + * this function removes the aggregator node and intermediate nodes if any + * from the given tc + */ +static enum ice_status +ice_sched_rm_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) +{ + struct ice_sched_node *tc_node, *agg_node; + struct ice_hw *hw = pi->hw; + + tc_node = ice_sched_get_tc_node(pi, tc); + if (!tc_node) + return ice_err_cfg; + + agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); + if (!agg_node) + return ice_err_does_not_exist; + + /* can't remove the aggregator node if it has children */ + if (ice_sched_is_agg_inuse(pi, agg_node)) + return ice_err_in_use; + + /* need to remove the whole subtree if aggregator node is the + * only child. + */ + while (agg_node->tx_sched_layer > hw->sw_entry_point_layer) { + struct ice_sched_node *parent = agg_node->parent; + + if (!parent) + return ice_err_cfg; + + if (parent->num_children > 1) + break; + + agg_node = parent; + } + + ice_free_sched_node(pi, agg_node); + return 0; +} + +/** + * ice_rm_agg_cfg_tc - remove aggregator configuration for tc + * @pi: port information structure + * @agg_info: aggregator id + * @tc: tc number + * @rm_vsi_info: bool value true or false + * + * this function removes aggregator reference to vsi of given tc. it removes + * the aggregator configuration completely for requested tc. the caller needs + * to hold the scheduler lock. + */ +static enum ice_status +ice_rm_agg_cfg_tc(struct ice_port_info *pi, struct ice_sched_agg_info *agg_info, + u8 tc, bool rm_vsi_info) +{ + enum ice_status status = 0; + + /* if nothing to remove - return success */ + if (!ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) + goto exit_rm_agg_cfg_tc; + + status = ice_move_all_vsi_to_dflt_agg(pi, agg_info, tc, rm_vsi_info); + if (status) + goto exit_rm_agg_cfg_tc; + + /* delete aggregator node(s) */ + status = ice_sched_rm_agg_cfg(pi, agg_info->agg_id, tc); + if (status) + goto exit_rm_agg_cfg_tc; + + clear_bit(tc, agg_info->tc_bitmap); +exit_rm_agg_cfg_tc: + return status; +} + +/** + * ice_save_agg_tc_bitmap - save aggregator tc bitmap + * @pi: port information structure + * @agg_id: aggregator id + * @tc_bitmap: 8 bits tc bitmap + * + * save aggregator tc bitmap. this function needs to be called with scheduler + * lock held. + */ +static enum ice_status +ice_save_agg_tc_bitmap(struct ice_port_info *pi, u32 agg_id, + unsigned long *tc_bitmap) +{ + struct ice_sched_agg_info *agg_info; + + agg_info = ice_get_agg_info(pi->hw, agg_id); + if (!agg_info) + return ice_err_param; + bitmap_copy(agg_info->replay_tc_bitmap, tc_bitmap, + ice_max_traffic_class); + return 0; +} + +/** + * ice_sched_add_agg_cfg - create an aggregator node + * @pi: port information structure + * @agg_id: aggregator id + * @tc: tc number + * + * this function creates an aggregator node and intermediate nodes if required + * for the given tc + */ +static enum ice_status +ice_sched_add_agg_cfg(struct ice_port_info *pi, u32 agg_id, u8 tc) +{ + struct ice_sched_node *parent, *agg_node, *tc_node; + u16 num_nodes[ice_aqc_topo_max_level_num] = { 0 }; + enum ice_status status = 0; + struct ice_hw *hw = pi->hw; + u32 first_node_teid; + u16 num_nodes_added; + u8 i, aggl; + + tc_node = ice_sched_get_tc_node(pi, tc); + if (!tc_node) + return ice_err_cfg; + + agg_node = ice_sched_get_agg_node(pi, tc_node, agg_id); + /* does agg node already exist ? */ + if (agg_node) + return status; + + aggl = ice_sched_get_agg_layer(hw); + + /* need one node in agg layer */ + num_nodes[aggl] = 1; + + /* check whether the intermediate nodes have space to add the + * new aggregator. if they are full, then sw needs to allocate a new + * intermediate node on those layers + */ + for (i = hw->sw_entry_point_layer; i < aggl; i++) { + parent = ice_sched_get_first_node(pi, tc_node, i); + + /* scan all the siblings */ + while (parent) { + if (parent->num_children < hw->max_children[i]) + break; + parent = parent->sibling; + } + + /* all the nodes are full, reserve one for this layer */ + if (!parent) + num_nodes[i]++; + } + + /* add the aggregator node */ + parent = tc_node; + for (i = hw->sw_entry_point_layer; i <= aggl; i++) { + if (!parent) + return ice_err_cfg; + + status = ice_sched_add_nodes_to_layer(pi, tc_node, parent, i, + num_nodes[i], + &first_node_teid, + &num_nodes_added); + if (status || num_nodes[i] != num_nodes_added) + return ice_err_cfg; + + /* the newly added node can be a new parent for the next + * layer nodes + */ + if (num_nodes_added) { + parent = ice_sched_find_node_by_teid(tc_node, + first_node_teid); + /* register aggregator id with the aggregator node */ + if (parent && i == aggl) + parent->agg_id = agg_id; + } else { + parent = parent->children[0]; + } + } + + return 0; +} + +/** + * ice_sched_cfg_agg - configure aggregator node + * @pi: port information structure + * @agg_id: aggregator id + * @agg_type: aggregator type queue, vsi, or aggregator group + * @tc_bitmap: bits tc bitmap + * + * it registers a unique aggregator node into scheduler services. it + * allows a user to register with a unique id to track it's resources. + * the aggregator type determines if this is a queue group, vsi group + * or aggregator group. it then creates the aggregator node(s) for requested + * tc(s) or removes an existing aggregator node including its configuration + * if indicated via tc_bitmap. call ice_rm_agg_cfg to release aggregator + * resources and remove aggregator id. + * this function needs to be called with scheduler lock held. + */ +static enum ice_status +ice_sched_cfg_agg(struct ice_port_info *pi, u32 agg_id, + enum ice_agg_type agg_type, unsigned long *tc_bitmap) +{ + struct ice_sched_agg_info *agg_info; + enum ice_status status = 0; + struct ice_hw *hw = pi->hw; + u8 tc; + + agg_info = ice_get_agg_info(hw, agg_id); + if (!agg_info) { + /* create new entry for new aggregator id */ + agg_info = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*agg_info), + gfp_kernel); + if (!agg_info) + return ice_err_no_memory; + + agg_info->agg_id = agg_id; + agg_info->agg_type = agg_type; + agg_info->tc_bitmap[0] = 0; + + /* initialize the aggregator vsi list head */ + init_list_head(&agg_info->agg_vsi_list); + + /* add new entry in aggregator list */ + list_add(&agg_info->list_entry, &hw->agg_list); + } + /* create aggregator node(s) for requested tc(s) */ + ice_for_each_traffic_class(tc) { + if (!ice_is_tc_ena(*tc_bitmap, tc)) { + /* delete aggregator cfg tc if it exists previously */ + status = ice_rm_agg_cfg_tc(pi, agg_info, tc, false); + if (status) + break; + continue; + } + + /* check if aggregator node for tc already exists */ + if (ice_is_tc_ena(agg_info->tc_bitmap[0], tc)) + continue; + + /* create new aggregator node for tc */ + status = ice_sched_add_agg_cfg(pi, agg_id, tc); + if (status) + break; + + /* save aggregator node's tc information */ + set_bit(tc, agg_info->tc_bitmap); + } + + return status; +} + +/** + * ice_cfg_agg - config aggregator node + * @pi: port information structure + * @agg_id: aggregator id + * @agg_type: aggregator type queue, vsi, or aggregator group + * @tc_bitmap: bits tc bitmap + * + * this function configures aggregator node(s). + */ +enum ice_status +ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, enum ice_agg_type agg_type, + u8 tc_bitmap) +{ + unsigned long bitmap = tc_bitmap; + enum ice_status status; + + mutex_lock(&pi->sched_lock); + status = ice_sched_cfg_agg(pi, agg_id, agg_type, + (unsigned long *)&bitmap); + if (!status) + status = ice_save_agg_tc_bitmap(pi, agg_id, + (unsigned long *)&bitmap); + mutex_unlock(&pi->sched_lock); + return status; +} + +/** + * ice_get_agg_vsi_info - get the aggregator id + * @agg_info: aggregator info + * @vsi_handle: software vsi handle + * + * the function returns aggregator vsi info based on vsi handle. this function + * needs to be called with scheduler lock held. + */ +static struct ice_sched_agg_vsi_info * +ice_get_agg_vsi_info(struct ice_sched_agg_info *agg_info, u16 vsi_handle) +{ + struct ice_sched_agg_vsi_info *agg_vsi_info; + + list_for_each_entry(agg_vsi_info, &agg_info->agg_vsi_list, list_entry) + if (agg_vsi_info->vsi_handle == vsi_handle) + return agg_vsi_info; + + return null; +} + +/** + * ice_get_vsi_agg_info - get the aggregator info of vsi + * @hw: pointer to the hardware structure + * @vsi_handle: sw vsi handle + * + * the function returns aggregator info of vsi represented via vsi_handle. the + * vsi has in this case a different aggregator than the default one. this + * function needs to be called with scheduler lock held. + */ +static struct ice_sched_agg_info * +ice_get_vsi_agg_info(struct ice_hw *hw, u16 vsi_handle) +{ + struct ice_sched_agg_info *agg_info; + + list_for_each_entry(agg_info, &hw->agg_list, list_entry) { + struct ice_sched_agg_vsi_info *agg_vsi_info; + + agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); + if (agg_vsi_info) + return agg_info; + } + return null; +} + +/** + * ice_save_agg_vsi_tc_bitmap - save aggregator vsi tc bitmap + * @pi: port information structure + * @agg_id: aggregator id + * @vsi_handle: software vsi handle + * @tc_bitmap: tc bitmap of enabled tc(s) + * + * save vsi to aggregator tc bitmap. this function needs to call with scheduler + * lock held. + */ +static enum ice_status +ice_save_agg_vsi_tc_bitmap(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, + unsigned long *tc_bitmap) +{ + struct ice_sched_agg_vsi_info *agg_vsi_info; + struct ice_sched_agg_info *agg_info; + + agg_info = ice_get_agg_info(pi->hw, agg_id); + if (!agg_info) + return ice_err_param; + /* check if entry already exist */ + agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); + if (!agg_vsi_info) + return ice_err_param; + bitmap_copy(agg_vsi_info->replay_tc_bitmap, tc_bitmap, + ice_max_traffic_class); + return 0; +} + +/** + * ice_sched_assoc_vsi_to_agg - associate/move vsi to new/default aggregator + * @pi: port information structure + * @agg_id: aggregator id + * @vsi_handle: software vsi handle + * @tc_bitmap: tc bitmap of enabled tc(s) + * + * this function moves vsi to a new or default aggregator node. if vsi is + * already associated to the aggregator node then no operation is performed on + * the tree. this function needs to be called with scheduler lock held. + */ +static enum ice_status +ice_sched_assoc_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, + u16 vsi_handle, unsigned long *tc_bitmap) +{ + struct ice_sched_agg_vsi_info *agg_vsi_info; + struct ice_sched_agg_info *agg_info; + enum ice_status status = 0; + struct ice_hw *hw = pi->hw; + u8 tc; + + if (!ice_is_vsi_valid(pi->hw, vsi_handle)) + return ice_err_param; + agg_info = ice_get_agg_info(hw, agg_id); + if (!agg_info) + return ice_err_param; + /* check if entry already exist */ + agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); + if (!agg_vsi_info) { + /* create new entry for vsi under aggregator list */ + agg_vsi_info = devm_kzalloc(ice_hw_to_dev(hw), + sizeof(*agg_vsi_info), gfp_kernel); + if (!agg_vsi_info) + return ice_err_param; + + /* add vsi id into the aggregator list */ + agg_vsi_info->vsi_handle = vsi_handle; + list_add(&agg_vsi_info->list_entry, &agg_info->agg_vsi_list); + } + /* move vsi node to new aggregator node for requested tc(s) */ + ice_for_each_traffic_class(tc) { + if (!ice_is_tc_ena(*tc_bitmap, tc)) + continue; + + /* move vsi to new aggregator */ + status = ice_sched_move_vsi_to_agg(pi, vsi_handle, agg_id, tc); + if (status) + break; + + set_bit(tc, agg_vsi_info->tc_bitmap); + } + return status; +} + - enum ice_status status; - status = ice_sched_update_elem(hw, node, &buf); + return ice_sched_update_elem(hw, node, &buf); +} + +/** + * ice_move_vsi_to_agg - moves vsi to new or default aggregator + * @pi: port information structure + * @agg_id: aggregator id + * @vsi_handle: software vsi handle + * @tc_bitmap: tc bitmap of enabled tc(s) + * + * move or associate vsi to a new or default aggregator node. + */ +enum ice_status +ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, + u8 tc_bitmap) +{ + unsigned long bitmap = tc_bitmap; + enum ice_status status; + + mutex_lock(&pi->sched_lock); + status = ice_sched_assoc_vsi_to_agg(pi, agg_id, vsi_handle, + (unsigned long *)&bitmap); + if (!status) + status = ice_save_agg_vsi_tc_bitmap(pi, agg_id, vsi_handle, + (unsigned long *)&bitmap); + mutex_unlock(&pi->sched_lock); +/** + * ice_sched_get_ena_tc_bitmap - get enabled tc bitmap + * @pi: port info struct + * @tc_bitmap: 8 bits tc bitmap to check + * @ena_tc_bitmap: 8 bits enabled tc bitmap to return + * + * this function returns enabled tc bitmap in variable ena_tc_bitmap. some tcs + * may be missing, it returns enabled tcs. this function needs to be called with + * scheduler lock held. + */ +static void +ice_sched_get_ena_tc_bitmap(struct ice_port_info *pi, + unsigned long *tc_bitmap, + unsigned long *ena_tc_bitmap) +{ + u8 tc; + + /* some tc(s) may be missing after reset, adjust for replay */ + ice_for_each_traffic_class(tc) + if (ice_is_tc_ena(*tc_bitmap, tc) && + (ice_sched_get_tc_node(pi, tc))) + set_bit(tc, ena_tc_bitmap); +} + +/** + * ice_sched_replay_agg - recreate aggregator node(s) + * @hw: pointer to the hw struct + * + * this function recreate aggregator type nodes which are not replayed earlier. + * it also replay aggregator bw information. these aggregator nodes are not + * associated with vsi type node yet. + */ +void ice_sched_replay_agg(struct ice_hw *hw) +{ + struct ice_port_info *pi = hw->port_info; + struct ice_sched_agg_info *agg_info; + + mutex_lock(&pi->sched_lock); + list_for_each_entry(agg_info, &hw->agg_list, list_entry) + /* replay aggregator (re-create aggregator node) */ + if (!bitmap_equal(agg_info->tc_bitmap, agg_info->replay_tc_bitmap, + ice_max_traffic_class)) { + declare_bitmap(replay_bitmap, ice_max_traffic_class); + enum ice_status status; + + bitmap_zero(replay_bitmap, ice_max_traffic_class); + ice_sched_get_ena_tc_bitmap(pi, + agg_info->replay_tc_bitmap, + replay_bitmap); + status = ice_sched_cfg_agg(hw->port_info, + agg_info->agg_id, + ice_agg_type_agg, + replay_bitmap); + if (status) { + dev_info(ice_hw_to_dev(hw), + "replay agg id[%d] failed ", + agg_info->agg_id); + /* move on to next one */ + continue; + } + } + mutex_unlock(&pi->sched_lock); +} + +/** + * ice_sched_replay_agg_vsi_preinit - agg/vsi replay pre initialization + * @hw: pointer to the hw struct + * + * this function initialize aggregator(s) tc bitmap to zero. a required + * preinit step for replaying aggregators. + */ +void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw) +{ + struct ice_port_info *pi = hw->port_info; + struct ice_sched_agg_info *agg_info; + + mutex_lock(&pi->sched_lock); + list_for_each_entry(agg_info, &hw->agg_list, list_entry) { + struct ice_sched_agg_vsi_info *agg_vsi_info; + + agg_info->tc_bitmap[0] = 0; + list_for_each_entry(agg_vsi_info, &agg_info->agg_vsi_list, + list_entry) + agg_vsi_info->tc_bitmap[0] = 0; + } + mutex_unlock(&pi->sched_lock); +} + +/** + * ice_sched_replay_vsi_agg - replay aggregator & vsi to aggregator node(s) + * @hw: pointer to the hw struct + * @vsi_handle: software vsi handle + * + * this function replays aggregator node, vsi to aggregator type nodes, and + * their node bandwidth information. this function needs to be called with + * scheduler lock held. + */ +static enum ice_status +ice_sched_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) +{ + declare_bitmap(replay_bitmap, ice_max_traffic_class); + struct ice_sched_agg_vsi_info *agg_vsi_info; + struct ice_port_info *pi = hw->port_info; + struct ice_sched_agg_info *agg_info; + enum ice_status status; + + bitmap_zero(replay_bitmap, ice_max_traffic_class); + if (!ice_is_vsi_valid(hw, vsi_handle)) + return ice_err_param; + agg_info = ice_get_vsi_agg_info(hw, vsi_handle); + if (!agg_info) + return 0; /* not present in list - default agg case */ + agg_vsi_info = ice_get_agg_vsi_info(agg_info, vsi_handle); + if (!agg_vsi_info) + return 0; /* not present in list - default agg case */ + ice_sched_get_ena_tc_bitmap(pi, agg_info->replay_tc_bitmap, + replay_bitmap); + /* replay aggregator node associated to vsi_handle */ + status = ice_sched_cfg_agg(hw->port_info, agg_info->agg_id, + ice_agg_type_agg, replay_bitmap); + if (status) + return status; + + bitmap_zero(replay_bitmap, ice_max_traffic_class); + ice_sched_get_ena_tc_bitmap(pi, agg_vsi_info->replay_tc_bitmap, + replay_bitmap); + /* move this vsi (vsi_handle) to above aggregator */ + return ice_sched_assoc_vsi_to_agg(pi, agg_info->agg_id, vsi_handle, + replay_bitmap); +} + +/** + * ice_replay_vsi_agg - replay vsi to aggregator node + * @hw: pointer to the hw struct + * @vsi_handle: software vsi handle + * + * this function replays association of vsi to aggregator type nodes, and + * node bandwidth information. + */ +enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle) +{ + struct ice_port_info *pi = hw->port_info; + enum ice_status status; + + mutex_lock(&pi->sched_lock); + status = ice_sched_replay_vsi_agg(hw, vsi_handle); + mutex_unlock(&pi->sched_lock); + return status; +} + diff --git a/drivers/net/ethernet/intel/ice/ice_sched.h b/drivers/net/ethernet/intel/ice/ice_sched.h --- a/drivers/net/ethernet/intel/ice/ice_sched.h +++ b/drivers/net/ethernet/intel/ice/ice_sched.h +#define ice_agg_layer_offset 6 + /* save aggregator vsi tc bitmap */ + declare_bitmap(replay_tc_bitmap, ice_max_traffic_class); + /* save aggregator tc bitmap */ + declare_bitmap(replay_tc_bitmap, ice_max_traffic_class); + +/* tx scheduler rate limiter functions */ +enum ice_status +ice_cfg_agg(struct ice_port_info *pi, u32 agg_id, + enum ice_agg_type agg_type, u8 tc_bitmap); +enum ice_status +ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle, + u8 tc_bitmap); +void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw); +void ice_sched_replay_agg(struct ice_hw *hw); +enum ice_status ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle); diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h +/* ice_dflt_agg_id means that all new vm(s)/vsi node connects + * to driver defined policy for default aggregator + */ +#define ice_dflt_agg_id 0 diff --git a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c --- a/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c +++ b/drivers/net/ethernet/intel/ice/ice_virtchnl_pf.c +/** + * ice_vf_rebuild_aggregator_node_cfg - rebuild aggregator node config + * @vsi: pointer to vsi + * + * this function moves vsi into corresponding scheduler aggregator node + * based on cached value of "aggregator node info" per vsi + */ +static void ice_vf_rebuild_aggregator_node_cfg(struct ice_vsi *vsi) +{ + struct ice_pf *pf = vsi->back; + enum ice_status status; + struct device *dev; + + if (!vsi->agg_node) + return; + + dev = ice_pf_to_dev(pf); + if (vsi->agg_node->num_vsis == ice_max_vsis_in_agg_node) { + dev_dbg(dev, + "agg_id %u already has reached max_num_vsis %u ", + vsi->agg_node->agg_id, vsi->agg_node->num_vsis); + return; + } + + status = ice_move_vsi_to_agg(pf->hw.port_info, vsi->agg_node->agg_id, + vsi->idx, vsi->tc_cfg.ena_tc); + if (status) + dev_dbg(dev, "unable to move vsi idx %u into aggregator %u node", + vsi->idx, vsi->agg_node->agg_id); + else + vsi->agg_node->num_vsis++; +} + + struct ice_vsi *vsi = vf->pf->vsi[vf->lan_vsi_idx]; + /* rebuild aggregator node config for main vf vsi */ + ice_vf_rebuild_aggregator_node_cfg(vsi);
|
Networking
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b126bd6bcd6710aa984104e979a5c930f44561b4
|
kiran patil
|
drivers
|
net
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ethernet, ice, intel
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ice: display some stored nvm versions via devlink info
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the devlink info interface supports drivers reporting "stored" versions. these versions indicate the version of an update that has been downloaded to the device, but is not yet active.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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display some stored nvm versions via devlink info
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['ice ']
|
['h', 'c']
| 3
| 94
| 4
|
--- diff --git a/drivers/net/ethernet/intel/ice/ice_devlink.c b/drivers/net/ethernet/intel/ice/ice_devlink.c --- a/drivers/net/ethernet/intel/ice/ice_devlink.c +++ b/drivers/net/ethernet/intel/ice/ice_devlink.c + struct ice_nvm_info pending_nvm; + struct ice_hw_dev_caps dev_caps; +static int +ice_info_pending_nvm_ver(struct ice_pf __always_unused *pf, struct ice_info_ctx *ctx) +{ + struct ice_nvm_info *nvm = &ctx->pending_nvm; + + if (ctx->dev_caps.common_cap.nvm_update_pending_nvm) + snprintf(ctx->buf, sizeof(ctx->buf), "%x.%02x", nvm->major, nvm->minor); + + return 0; +} + +static int +ice_info_pending_eetrack(struct ice_pf __always_unused *pf, struct ice_info_ctx *ctx) +{ + struct ice_nvm_info *nvm = &ctx->pending_nvm; + + if (ctx->dev_caps.common_cap.nvm_update_pending_nvm) + snprintf(ctx->buf, sizeof(ctx->buf), "0x%08x", nvm->eetrack); + + return 0; +} + -#define fixed(key, getter) { ice_version_fixed, key, getter } -#define running(key, getter) { ice_version_running, key, getter } +#define fixed(key, getter) { ice_version_fixed, key, getter, null } +#define running(key, getter) { ice_version_running, key, getter, null } +#define stored(key, getter, fallback) { ice_version_stored, key, getter, fallback } + +/* the combined() macro inserts both the running entry as well as a stored + * entry. the running entry will always report the version from the active + * handler. the stored entry will first try the pending handler, and fallback + * to the active handler if the pending function does not report a version. + * the pending handler should check the status of a pending update for the + * relevant flash component. it should only fill in the buffer in the case + * where a valid pending version is available. this ensures that the related + * stored and running versions remain in sync, and that stored versions are + * correctly reported as expected. + */ +#define combined(key, active, pending) \ + running(key, active), \ + stored(key, pending, active) + int (*fallback)(struct ice_pf *pf, struct ice_info_ctx *ctx); - running("fw.psid.api", ice_info_nvm_ver), - running(devlink_info_version_generic_fw_bundle_id, ice_info_eetrack), + combined("fw.psid.api", ice_info_nvm_ver, ice_info_pending_nvm_ver), + combined(devlink_info_version_generic_fw_bundle_id, ice_info_eetrack, ice_info_pending_eetrack), + struct device *dev = ice_pf_to_dev(pf); + struct ice_hw *hw = &pf->hw; + enum ice_status status; + /* discover capabilities first */ + status = ice_discover_dev_caps(hw, &ctx->dev_caps); + if (status) { + err = -eio; + goto out_free_ctx; + } + + if (ctx->dev_caps.common_cap.nvm_update_pending_nvm) { + status = ice_get_inactive_nvm_ver(hw, &ctx->pending_nvm); + if (status) { + dev_dbg(dev, "unable to read inactive nvm version data, status %s aq_err %s ", + ice_stat_str(status), ice_aq_str(hw->adminq.sq_last_status)); + + /* disable display of pending option rom */ + ctx->dev_caps.common_cap.nvm_update_pending_nvm = false; + } + } + + /* if the default getter doesn't report a version, use the + * fallback function. this is primarily useful in the case of + * "stored" versions that want to report the same value as the + * running version in the normal case of no pending update. + */ + if (ctx->buf[0] == '' && ice_devlink_versions[i].fallback) { + err = ice_devlink_versions[i].fallback(pf, ctx); + if (err) { + nl_set_err_msg_mod(extack, "unable to obtain version info"); + goto out_free_ctx; + } + } + diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c --- a/drivers/net/ethernet/intel/ice/ice_nvm.c +++ b/drivers/net/ethernet/intel/ice/ice_nvm.c +/** + * ice_get_inactive_nvm_ver - read option rom version from the inactive bank + * @hw: pointer to the hw structure + * @nvm: storage for option rom version information + * + * reads the nvm eetrack id, map version, and security revision of the + * inactive nvm bank. used to access version data for a pending update that + * has not yet been activated. + */ +enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm) +{ + return ice_get_nvm_ver_info(hw, ice_inactive_flash_bank, nvm); +} + diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.h b/drivers/net/ethernet/intel/ice/ice_nvm.h --- a/drivers/net/ethernet/intel/ice/ice_nvm.h +++ b/drivers/net/ethernet/intel/ice/ice_nvm.h +ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm); +enum ice_status
|
Networking
|
2c4fe41d727f230df59ba053f8ade36b24d22520
|
jacob keller
|
drivers
|
net
|
ethernet, ice, intel
|
ice: display stored undi firmware version via devlink info
|
just as we recently added support for other stored firmware flash versions, support display of the stored undi option rom version via devlink info.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
display stored undi firmware version via devlink info
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ice ']
|
['h', 'c']
| 3
| 113
| 38
|
--- diff --git a/drivers/net/ethernet/intel/ice/ice_devlink.c b/drivers/net/ethernet/intel/ice/ice_devlink.c --- a/drivers/net/ethernet/intel/ice/ice_devlink.c +++ b/drivers/net/ethernet/intel/ice/ice_devlink.c + struct ice_orom_info pending_orom; +static int +ice_info_pending_orom_ver(struct ice_pf __always_unused *pf, struct ice_info_ctx *ctx) +{ + struct ice_orom_info *orom = &ctx->pending_orom; + + if (ctx->dev_caps.common_cap.nvm_update_pending_orom) + snprintf(ctx->buf, sizeof(ctx->buf), "%u.%u.%u", + orom->major, orom->build, orom->patch); + + return 0; +} + - running(devlink_info_version_generic_fw_undi, ice_info_orom_ver), + combined(devlink_info_version_generic_fw_undi, ice_info_orom_ver, ice_info_pending_orom_ver), + if (ctx->dev_caps.common_cap.nvm_update_pending_orom) { + status = ice_get_inactive_orom_ver(hw, &ctx->pending_orom); + if (status) { + dev_dbg(dev, "unable to read inactive option rom version data, status %s aq_err %s ", + ice_stat_str(status), ice_aq_str(hw->adminq.sq_last_status)); + + /* disable display of pending option rom */ + ctx->dev_caps.common_cap.nvm_update_pending_orom = false; + } + } + diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c --- a/drivers/net/ethernet/intel/ice/ice_nvm.c +++ b/drivers/net/ethernet/intel/ice/ice_nvm.c - * ice_get_orom_ver_info - read option rom version information + * ice_get_orom_civd_data - get the combo version information from option rom - * @orom: pointer to option rom info structure + * @bank: whether to read from the active or inactive flash module + * @civd: storage for the option rom civd data. - * read the combo image version data from the boot configuration tlv and fill - * in the option rom version data. + * searches through the option rom flash contents to locate the civd data for + * the image. -ice_get_orom_ver_info(struct ice_hw *hw, struct ice_orom_info *orom) +ice_get_orom_civd_data(struct ice_hw *hw, enum ice_bank_select bank, + struct ice_orom_civd_info *civd) - u16 combo_hi, combo_lo, boot_cfg_tlv, boot_cfg_tlv_len; + struct ice_orom_civd_info tmp; - u32 combo_ver; + u32 offset; - status = ice_get_pfa_module_tlv(hw, &boot_cfg_tlv, &boot_cfg_tlv_len, - ice_sr_boot_cfg_ptr); - if (status) { - ice_debug(hw, ice_dbg_init, "failed to read boot configuration block tlv. "); - return status; - } - - /* boot configuration block must have length at least 2 words - * (combo image version high and combo image version low) + /* the civd section is located in the option rom aligned to 512 bytes. + * the first 4 bytes must contain the ascii characters "$civ". + * a simple modulo 256 sum of all of the bytes of the structure must + * equal 0. - if (boot_cfg_tlv_len < 2) { - ice_debug(hw, ice_dbg_init, "invalid boot configuration block tlv size. "); - return ice_err_inval_size; - } + for (offset = 0; (offset + 512) <= hw->flash.banks.orom_size; offset += 512) { + u8 sum = 0, i; - status = ice_read_sr_word(hw, (boot_cfg_tlv + ice_nvm_orom_ver_off), - &combo_hi); - if (status) { - ice_debug(hw, ice_dbg_init, "failed to read orom_ver hi. "); - return status; + status = ice_read_flash_module(hw, bank, ice_sr_1st_orom_bank_ptr, + offset, (u8 *)&tmp, sizeof(tmp)); + if (status) { + ice_debug(hw, ice_dbg_nvm, "unable to read option rom civd data "); + return status; + } + + /* skip forward until we find a matching signature */ + if (memcmp("$civ", tmp.signature, sizeof(tmp.signature)) != 0) + continue; + + /* verify that the simple checksum is zero */ + for (i = 0; i < sizeof(tmp); i++) + sum += ((u8 *)&tmp)[i]; + + if (sum) { + ice_debug(hw, ice_dbg_nvm, "found civd data with invalid checksum of %u ", + sum); + return ice_err_nvm; + } + + *civd = tmp; + return 0; - status = ice_read_sr_word(hw, (boot_cfg_tlv + ice_nvm_orom_ver_off + 1), - &combo_lo); + return ice_err_nvm; +} + +/** + * ice_get_orom_ver_info - read option rom version information + * @hw: pointer to the hw struct + * @bank: whether to read from the active or inactive flash module + * @orom: pointer to option rom info structure + * + * read option rom version and security revision from the option rom flash + * section. + */ +static enum ice_status +ice_get_orom_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_orom_info *orom) +{ + struct ice_orom_civd_info civd; + enum ice_status status; + u32 combo_ver; + + status = ice_get_orom_civd_data(hw, bank, &civd); - ice_debug(hw, ice_dbg_init, "failed to read orom_ver lo. "); + ice_debug(hw, ice_dbg_nvm, "failed to locate valid option rom civd data "); - combo_ver = ((u32)combo_hi << 16) | combo_lo; + combo_ver = le32_to_cpu(civd.combo_ver); - orom->major = (u8)((combo_ver & ice_orom_ver_mask) >> - ice_orom_ver_shift); + orom->major = (u8)((combo_ver & ice_orom_ver_mask) >> ice_orom_ver_shift); - orom->build = (u16)((combo_ver & ice_orom_ver_build_mask) >> - ice_orom_ver_build_shift); + orom->build = (u16)((combo_ver & ice_orom_ver_build_mask) >> ice_orom_ver_build_shift); +/** + * ice_get_inactive_orom_ver - read option rom version from the inactive bank + * @hw: pointer to the hw structure + * @orom: storage for option rom version information + * + * reads the option rom version and security revision data for the inactive + * section of flash. used to access version data for a pending update that has + * not yet been activated. + */ +enum ice_status ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom) +{ + return ice_get_orom_ver_info(hw, ice_inactive_flash_bank, orom); +} + - status = ice_get_orom_ver_info(hw, &flash->orom); - if (status) { + status = ice_get_orom_ver_info(hw, ice_active_flash_bank, &flash->orom); + if (status) - return status; - } diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.h b/drivers/net/ethernet/intel/ice/ice_nvm.h --- a/drivers/net/ethernet/intel/ice/ice_nvm.h +++ b/drivers/net/ethernet/intel/ice/ice_nvm.h +struct ice_orom_civd_info { + u8 signature[4]; /* must match ascii '$civ' characters */ + u8 checksum; /* simple modulo 256 sum of all structure bytes must equal 0 */ + __le32 combo_ver; /* combo image version number */ + u8 combo_name_len; /* length of the unicode combo image version string, max of 32 */ + __le16 combo_name[32]; /* unicode string representing the combo image version */ +} __packed; + +ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom); +enum ice_status
|
Networking
|
e67fbcfbb4ef0d0bbd978594707381efcadf0c55
|
jacob keller
|
drivers
|
net
|
ethernet, ice, intel
|
ice: display stored netlist versions via devlink info
|
add a function to read the inactive netlist bank for version information. to support this, refactor how we read the netlist version data. instead of using the firmware aq interface with a module id, read from the flash as a flat nvm, using ice_read_flash_module.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
display stored netlist versions via devlink info
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ice ']
|
['h', 'c']
| 7
| 176
| 93
|
--- diff --git a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h --- a/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h +++ b/drivers/net/ethernet/intel/ice/ice_adminq_cmd.h -/* the result of netlist nvm read comes in a tlv format. the actual data - * (netlist header) starts from word offset 1 (byte 2). the fw strips - * out the type field from the tlv header so all the netlist fields - * should adjust their offset value by 1 word (2 bytes) in order to map - * their correct location. - */ -#define ice_aqc_nvm_link_topo_netlist_mod_id 0x11b -#define ice_aqc_nvm_link_topo_netlist_len_offset 1 -#define ice_aqc_nvm_link_topo_netlist_len 2 /* in bytes */ -#define ice_aqc_nvm_netlist_node_count_offset 2 -#define ice_aqc_nvm_netlist_node_count_len 2 /* in bytes */ -#define ice_aqc_nvm_netlist_node_count_m ice_m(0x3ff, 0) -#define ice_aqc_nvm_netlist_id_blk_start_offset 5 -#define ice_aqc_nvm_netlist_id_blk_len 0x30 /* in words */ - -/* netlist id block field offsets (word offsets) */ -#define ice_aqc_nvm_netlist_id_blk_major_ver_low 2 -#define ice_aqc_nvm_netlist_id_blk_major_ver_high 3 -#define ice_aqc_nvm_netlist_id_blk_minor_ver_low 4 -#define ice_aqc_nvm_netlist_id_blk_minor_ver_high 5 -#define ice_aqc_nvm_netlist_id_blk_type_low 6 -#define ice_aqc_nvm_netlist_id_blk_type_high 7 -#define ice_aqc_nvm_netlist_id_blk_rev_low 8 -#define ice_aqc_nvm_netlist_id_blk_rev_high 9 -#define ice_aqc_nvm_netlist_id_blk_sha_hash 0xa -#define ice_aqc_nvm_netlist_id_blk_cust_ver 0x2f - diff --git a/drivers/net/ethernet/intel/ice/ice_devlink.c b/drivers/net/ethernet/intel/ice/ice_devlink.c --- a/drivers/net/ethernet/intel/ice/ice_devlink.c +++ b/drivers/net/ethernet/intel/ice/ice_devlink.c + struct ice_netlist_info pending_netlist; +static int +ice_info_pending_netlist_ver(struct ice_pf __always_unused *pf, struct ice_info_ctx *ctx) +{ + struct ice_netlist_info *netlist = &ctx->pending_netlist; + + /* the netlist version fields are bcd formatted */ + if (ctx->dev_caps.common_cap.nvm_update_pending_netlist) + snprintf(ctx->buf, sizeof(ctx->buf), "%x.%x.%x-%x.%x.%x", + netlist->major, netlist->minor, + netlist->type >> 16, netlist->type & 0xffff, netlist->rev, + netlist->cust_ver); + + return 0; +} + +static int +ice_info_pending_netlist_build(struct ice_pf __always_unused *pf, struct ice_info_ctx *ctx) +{ + struct ice_netlist_info *netlist = &ctx->pending_netlist; + + if (ctx->dev_caps.common_cap.nvm_update_pending_netlist) + snprintf(ctx->buf, sizeof(ctx->buf), "0x%08x", netlist->hash); + + return 0; +} + - running("fw.netlist", ice_info_netlist_ver), - running("fw.netlist.build", ice_info_netlist_build), + combined("fw.netlist", ice_info_netlist_ver, ice_info_pending_netlist_ver), + combined("fw.netlist.build", ice_info_netlist_build, ice_info_pending_netlist_build), + if (ctx->dev_caps.common_cap.nvm_update_pending_netlist) { + status = ice_get_inactive_netlist_ver(hw, &ctx->pending_netlist); + if (status) { + dev_dbg(dev, "unable to read inactive netlist version data, status %s aq_err %s ", + ice_stat_str(status), ice_aq_str(hw->adminq.sq_last_status)); + + /* disable display of pending option rom */ + ctx->dev_caps.common_cap.nvm_update_pending_netlist = false; + } + } + diff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c --- a/drivers/net/ethernet/intel/ice/ice_main.c +++ b/drivers/net/ethernet/intel/ice/ice_main.c + case ice_err_nvm: + return "ice_err_nvm"; diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c --- a/drivers/net/ethernet/intel/ice/ice_nvm.c +++ b/drivers/net/ethernet/intel/ice/ice_nvm.c +/** + * ice_read_netlist_module - read data from the netlist module area + * @hw: pointer to the hw structure + * @bank: whether to read from the active or inactive module + * @offset: offset into the netlist to read from + * @data: storage for returned word value + * + * read a word from the specified netlist bank. + */ +static enum ice_status +ice_read_netlist_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) +{ + enum ice_status status; + __le16 data_local; + + status = ice_read_flash_module(hw, bank, ice_sr_netlist_bank_ptr, offset * sizeof(u16), + (__force u8 *)&data_local, sizeof(u16)); + if (!status) + *data = le16_to_cpu(data_local); + + return status; +} + - * ice_get_netlist_ver_info + * ice_get_netlist_info - * @ver: pointer to netlist version info structure + * @bank: whether to read from the active or inactive flash bank + * @netlist: pointer to netlist version info structure - * get the netlist version information + * get the netlist version information from the requested bank. reads the link + * topology section to find the netlist id block and extract the relevant + * information into the netlist version structure. -ice_get_netlist_ver_info(struct ice_hw *hw, struct ice_netlist_info *ver) +ice_get_netlist_info(struct ice_hw *hw, enum ice_bank_select bank, + struct ice_netlist_info *netlist) - enum ice_status ret; - u32 id_blk_start; - __le16 raw_data; - u16 data, i; - u16 *buff; - - ret = ice_acquire_nvm(hw, ice_res_read); - if (ret) - return ret; - buff = kcalloc(ice_aqc_nvm_netlist_id_blk_len, sizeof(*buff), - gfp_kernel); - if (!buff) { - ret = ice_err_no_memory; - goto exit_no_mem; + u16 module_id, length, node_count, i; + enum ice_status status; + u16 *id_blk; + + status = ice_read_netlist_module(hw, bank, ice_netlist_type_offset, &module_id); + if (status) + return status; + + if (module_id != ice_netlist_link_topo_mod_id) { + ice_debug(hw, ice_dbg_nvm, "expected netlist module_id id of 0x%04x, but got 0x%04x ", + ice_netlist_link_topo_mod_id, module_id); + return ice_err_nvm; - /* read module length */ - ret = ice_aq_read_nvm(hw, ice_aqc_nvm_link_topo_netlist_mod_id, - ice_aqc_nvm_link_topo_netlist_len_offset * 2, - ice_aqc_nvm_link_topo_netlist_len, &raw_data, - false, false, null); - if (ret) - goto exit_error; + status = ice_read_netlist_module(hw, bank, ice_link_topo_module_len, &length); + if (status) + return status; - data = le16_to_cpu(raw_data); - /* exit if length is = 0 */ - if (!data) - goto exit_error; + /* sanity check that we have at least enough words to store the netlist id block */ + if (length < ice_netlist_id_blk_size) { + ice_debug(hw, ice_dbg_nvm, "netlist link topology module too small. expected at least %u words, but got %u words. ", + ice_netlist_id_blk_size, length); + return ice_err_nvm; + } - /* read node count */ - ret = ice_aq_read_nvm(hw, ice_aqc_nvm_link_topo_netlist_mod_id, - ice_aqc_nvm_netlist_node_count_offset * 2, - ice_aqc_nvm_netlist_node_count_len, &raw_data, - false, false, null); - if (ret) - goto exit_error; - data = le16_to_cpu(raw_data) & ice_aqc_nvm_netlist_node_count_m; + status = ice_read_netlist_module(hw, bank, ice_link_topo_node_count, &node_count); + if (status) + return status; + node_count &= ice_link_topo_node_count_m; - /* netlist id block starts from offset 4 + node count * 2 */ - id_blk_start = ice_aqc_nvm_netlist_id_blk_start_offset + data * 2; + id_blk = kcalloc(ice_netlist_id_blk_size, sizeof(*id_blk), gfp_kernel); + if (!id_blk) + return ice_err_no_memory; - /* read the entire netlist id block */ - ret = ice_aq_read_nvm(hw, ice_aqc_nvm_link_topo_netlist_mod_id, - id_blk_start * 2, - ice_aqc_nvm_netlist_id_blk_len * 2, buff, false, - false, null); - if (ret) + /* read out the entire netlist id block at once. */ + status = ice_read_flash_module(hw, bank, ice_sr_netlist_bank_ptr, + ice_netlist_id_blk_offset(node_count) * sizeof(u16), + (u8 *)id_blk, ice_netlist_id_blk_size * sizeof(u16)); + if (status) - for (i = 0; i < ice_aqc_nvm_netlist_id_blk_len; i++) - buff[i] = le16_to_cpu(((__force __le16 *)buff)[i]); - - ver->major = (buff[ice_aqc_nvm_netlist_id_blk_major_ver_high] << 16) | - buff[ice_aqc_nvm_netlist_id_blk_major_ver_low]; - ver->minor = (buff[ice_aqc_nvm_netlist_id_blk_minor_ver_high] << 16) | - buff[ice_aqc_nvm_netlist_id_blk_minor_ver_low]; - ver->type = (buff[ice_aqc_nvm_netlist_id_blk_type_high] << 16) | - buff[ice_aqc_nvm_netlist_id_blk_type_low]; - ver->rev = (buff[ice_aqc_nvm_netlist_id_blk_rev_high] << 16) | - buff[ice_aqc_nvm_netlist_id_blk_rev_low]; - ver->cust_ver = buff[ice_aqc_nvm_netlist_id_blk_cust_ver]; + for (i = 0; i < ice_netlist_id_blk_size; i++) + id_blk[i] = le16_to_cpu(((__force __le16 *)id_blk)[i]); + + netlist->major = id_blk[ice_netlist_id_blk_major_ver_high] << 16 | + id_blk[ice_netlist_id_blk_major_ver_low]; + netlist->minor = id_blk[ice_netlist_id_blk_minor_ver_high] << 16 | + id_blk[ice_netlist_id_blk_minor_ver_low]; + netlist->type = id_blk[ice_netlist_id_blk_type_high] << 16 | + id_blk[ice_netlist_id_blk_type_low]; + netlist->rev = id_blk[ice_netlist_id_blk_rev_high] << 16 | + id_blk[ice_netlist_id_blk_rev_low]; + netlist->cust_ver = id_blk[ice_netlist_id_blk_cust_ver]; - ver->hash = buff[ice_aqc_nvm_netlist_id_blk_sha_hash + 15] << 16 | - buff[ice_aqc_nvm_netlist_id_blk_sha_hash + 14]; + netlist->hash = id_blk[ice_netlist_id_blk_sha_hash_word(15)] << 16 | + id_blk[ice_netlist_id_blk_sha_hash_word(14)]; - kfree(buff); -exit_no_mem: - ice_release_nvm(hw); - return ret; + kfree(id_blk); + + return status; +} + +/** + * ice_get_inactive_netlist_ver + * @hw: pointer to the hw struct + * @netlist: pointer to netlist version info structure + * + * read the netlist version data from the inactive netlist bank. used to + * extract version data of a pending flash update in order to display the + * version data. + */ +enum ice_status ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist) +{ + return ice_get_netlist_info(hw, ice_inactive_flash_bank, netlist); - status = ice_get_netlist_ver_info(hw, &flash->netlist); + status = ice_get_netlist_info(hw, ice_active_flash_bank, &flash->netlist); diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.h b/drivers/net/ethernet/intel/ice/ice_nvm.h --- a/drivers/net/ethernet/intel/ice/ice_nvm.h +++ b/drivers/net/ethernet/intel/ice/ice_nvm.h +ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist); +enum ice_status diff --git a/drivers/net/ethernet/intel/ice/ice_status.h b/drivers/net/ethernet/intel/ice/ice_status.h --- a/drivers/net/ethernet/intel/ice/ice_status.h +++ b/drivers/net/ethernet/intel/ice/ice_status.h + ice_err_nvm = -50, diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h +/* the link topology netlist section is stored as a series of words. it is + * stored in the nvm as a tlv, with the first two words containing the type + * and length. + */ +#define ice_netlist_link_topo_mod_id 0x011b +#define ice_netlist_type_offset 0x0000 +#define ice_netlist_len_offset 0x0001 + +/* the link topology section follows the tlv header. when reading the netlist + * using ice_read_netlist_module, we need to account for the 2-word tlv + * header. + */ +#define ice_netlist_link_topo_offset(n) ((n) + 2) + +#define ice_link_topo_module_len ice_netlist_link_topo_offset(0x0000) +#define ice_link_topo_node_count ice_netlist_link_topo_offset(0x0001) + +#define ice_link_topo_node_count_m ice_m(0x3ff, 0) + +/* the netlist id block is located after all of the link topology nodes. */ +#define ice_netlist_id_blk_size 0x30 +#define ice_netlist_id_blk_offset(n) ice_netlist_link_topo_offset(0x0004 + 2 * (n)) + +/* netlist id block field offsets (word offsets) */ +#define ice_netlist_id_blk_major_ver_low 0x02 +#define ice_netlist_id_blk_major_ver_high 0x03 +#define ice_netlist_id_blk_minor_ver_low 0x04 +#define ice_netlist_id_blk_minor_ver_high 0x05 +#define ice_netlist_id_blk_type_low 0x06 +#define ice_netlist_id_blk_type_high 0x07 +#define ice_netlist_id_blk_rev_low 0x08 +#define ice_netlist_id_blk_rev_high 0x09 +#define ice_netlist_id_blk_sha_hash_word(n) (0x0a + (n)) +#define ice_netlist_id_blk_cust_ver 0x2f +
|
Networking
|
e120a9ab45d31dfc5f5fd3eb39c2d5b7986320d9
|
jacob keller
|
drivers
|
net
|
ethernet, ice, intel
|
ice: introduce function for reading from flash modules
|
when reading from the flash memory of the device, the ice driver has two interfaces available to it. first, it can use a mediated interface via firmware that allows specifying a module id. this allows reading from specific modules of the active flash bank.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce function for reading from flash modules
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['ice ']
|
['h', 'c']
| 2
| 179
| 5
|
--- diff --git a/drivers/net/ethernet/intel/ice/ice_nvm.c b/drivers/net/ethernet/intel/ice/ice_nvm.c --- a/drivers/net/ethernet/intel/ice/ice_nvm.c +++ b/drivers/net/ethernet/intel/ice/ice_nvm.c +/** + * ice_get_flash_bank_offset - get offset into requested flash bank + * @hw: pointer to the hw structure + * @bank: whether to read from the active or inactive flash bank + * @module: the module to read from + * + * based on the module, lookup the module offset from the beginning of the + * flash. + * + * returns the flash offset. note that a value of zero is invalid and must be + * treated as an error. + */ +static u32 ice_get_flash_bank_offset(struct ice_hw *hw, enum ice_bank_select bank, u16 module) +{ + struct ice_bank_info *banks = &hw->flash.banks; + enum ice_flash_bank active_bank; + bool second_bank_active; + u32 offset, size; + + switch (module) { + case ice_sr_1st_nvm_bank_ptr: + offset = banks->nvm_ptr; + size = banks->nvm_size; + active_bank = banks->nvm_bank; + break; + case ice_sr_1st_orom_bank_ptr: + offset = banks->orom_ptr; + size = banks->orom_size; + active_bank = banks->orom_bank; + break; + case ice_sr_netlist_bank_ptr: + offset = banks->netlist_ptr; + size = banks->netlist_size; + active_bank = banks->netlist_bank; + break; + default: + ice_debug(hw, ice_dbg_nvm, "unexpected value for flash module: 0x%04x ", module); + return 0; + } + + switch (active_bank) { + case ice_1st_flash_bank: + second_bank_active = false; + break; + case ice_2nd_flash_bank: + second_bank_active = true; + break; + default: + ice_debug(hw, ice_dbg_nvm, "unexpected value for active flash bank: %u ", + active_bank); + return 0; + } + + /* the second flash bank is stored immediately following the first + * bank. based on whether the 1st or 2nd bank is active, and whether + * we want the active or inactive bank, calculate the desired offset. + */ + switch (bank) { + case ice_active_flash_bank: + return offset + (second_bank_active ? size : 0); + case ice_inactive_flash_bank: + return offset + (second_bank_active ? 0 : size); + } + + ice_debug(hw, ice_dbg_nvm, "unexpected value for flash bank selection: %u ", bank); + return 0; +} + +/** + * ice_read_flash_module - read a word from one of the main nvm modules + * @hw: pointer to the hw structure + * @bank: which bank of the module to read + * @module: the module to read + * @offset: the offset into the module in bytes + * @data: storage for the word read from the flash + * @length: bytes of data to read + * + * read data from the specified flash module. the bank parameter indicates + * whether or not to read from the active bank or the inactive bank of that + * module. + * + * the word will be read using flat nvm access, and relies on the + * hw->flash.banks data being setup by ice_determine_active_flash_banks() + * during initialization. + */ +static enum ice_status +ice_read_flash_module(struct ice_hw *hw, enum ice_bank_select bank, u16 module, + u32 offset, u8 *data, u32 length) +{ + enum ice_status status; + u32 start; + + start = ice_get_flash_bank_offset(hw, bank, module); + if (!start) { + ice_debug(hw, ice_dbg_nvm, "unable to calculate flash bank offset for module 0x%04x ", + module); + return ice_err_param; + } + + status = ice_acquire_nvm(hw, ice_res_read); + if (status) + return status; + + status = ice_read_flat_nvm(hw, start + offset, &length, data, false); + + ice_release_nvm(hw); + + return status; +} + +/** + * ice_read_nvm_module - read from the active main nvm module + * @hw: pointer to the hw structure + * @bank: whether to read from active or inactive nvm module + * @offset: offset into the nvm module to read, in words + * @data: storage for returned word value + * + * read the specified word from the active nvm module. this includes the css + * header at the start of the nvm module. + */ +static enum ice_status +ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) +{ + enum ice_status status; + __le16 data_local; + + status = ice_read_flash_module(hw, bank, ice_sr_1st_nvm_bank_ptr, offset * sizeof(u16), + (__force u8 *)&data_local, sizeof(u16)); + if (!status) + *data = le16_to_cpu(data_local); + + return status; +} + +/** + * ice_read_nvm_sr_copy - read a word from the shadow ram copy in the nvm bank + * @hw: pointer to the hw structure + * @bank: whether to read from the active or inactive nvm module + * @offset: offset into the shadow ram copy to read, in words + * @data: storage for returned word value + * + * read the specified word from the copy of the shadow ram found in the + * specified nvm module. + */ +static enum ice_status +ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data) +{ + return ice_read_nvm_module(hw, bank, ice_nvm_sr_copy_word_offset + offset, data); +} + + * @bank: whether to read from the active or inactive flash bank -ice_get_nvm_ver_info(struct ice_hw *hw, struct ice_nvm_info *nvm) +ice_get_nvm_ver_info(struct ice_hw *hw, enum ice_bank_select bank, struct ice_nvm_info *nvm) - status = ice_read_sr_word(hw, ice_sr_nvm_dev_starter_ver, &ver); + status = ice_read_nvm_sr_copy(hw, bank, ice_sr_nvm_dev_starter_ver, &ver); + - status = ice_read_sr_word(hw, ice_sr_nvm_eetrack_lo, &eetrack_lo); + status = ice_read_nvm_sr_copy(hw, bank, ice_sr_nvm_eetrack_lo, &eetrack_lo); - status = ice_read_sr_word(hw, ice_sr_nvm_eetrack_hi, &eetrack_hi); + status = ice_read_nvm_sr_copy(hw, bank, ice_sr_nvm_eetrack_hi, &eetrack_hi); - status = ice_get_nvm_ver_info(hw, &flash->nvm); + status = ice_get_nvm_ver_info(hw, ice_active_flash_bank, &flash->nvm); diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h +/* enumeration of which flash bank is desired to read from, either the active + * bank or the inactive bank. used to abstract 1st and 2nd bank notion from + * code which just wants to read the active or inactive flash bank. + */ +enum ice_bank_select { + ice_active_flash_bank, + ice_inactive_flash_bank, +}; + +/* css header words */ +#define ice_nvm_css_srev_l 0x14 +#define ice_nvm_css_srev_h 0x15 + +/* length of css header section in words */ +#define ice_css_header_length 330 + +/* offset of shadow ram copy in the nvm bank area. */ +#define ice_nvm_sr_copy_word_offset roundup(ice_css_header_length, 32) + +/* size in bytes of option rom trailer */ +#define ice_nvm_orom_trailer_length (2 * ice_css_header_length) +
|
Networking
|
0ce50c7066e214545ea4543d73946073725c4421
|
jacob keller
|
drivers
|
net
|
ethernet, ice, intel
|
igb: enable rss for intel i211 ethernet controller
|
the intel i211 ethernet controller supports 2 receive side scaling (rss) queues. it should not be excluded from having this feature enabled.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
enable rss for intel i211 ethernet controller
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['igb ']
|
['c']
| 1
| 1
| 2
|
--- diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c - if (hw->mac.type != e1000_i211) - mrqc |= e1000_mrqc_enable_rss_mq; + mrqc |= e1000_mrqc_enable_rss_mq;
|
Networking
|
6e6026f2dd2005844fb35c3911e8083c09952c6c
|
nick lowe
|
drivers
|
net
|
ethernet, igb, intel
|
igc: expose the nvm version
|
expose the nvm map version via drvinfo in ethtool nvm image version is reported as firmware version for i225 device minor typo fix - remove space
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
expose the nvm version
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['igb ']
|
['h', 'c']
| 3
| 17
| 2
|
--- diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h + + char fw_version[16]; diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h +#define igc_nvm_dev_starter 5 /* dev_starter version */ diff --git a/drivers/net/ethernet/intel/igc/igc_ethtool.c b/drivers/net/ethernet/intel/igc/igc_ethtool.c --- a/drivers/net/ethernet/intel/igc/igc_ethtool.c +++ b/drivers/net/ethernet/intel/igc/igc_ethtool.c + struct igc_hw *hw = &adapter->hw; + u16 nvm_version = 0; + + strscpy(drvinfo->driver, igc_driver_name, sizeof(drvinfo->driver)); + + /* nvm image version is reported as firmware version for i225 device */ + hw->nvm.ops.read(hw, igc_nvm_dev_starter, 1, &nvm_version); + + scnprintf(adapter->fw_version, + sizeof(adapter->fw_version), + "%x", + nvm_version); - strlcpy(drvinfo->driver, igc_driver_name, sizeof(drvinfo->driver)); + strscpy(drvinfo->fw_version, adapter->fw_version, + sizeof(drvinfo->fw_version)); - /* add fw_version here */
|
Networking
|
01bb6129c641030a40931c1a8c60ce4098c23dc9
|
sasha neftin
|
drivers
|
net
|
ethernet, igc, intel
|
igc: expose the gphy firmware version
|
extend reporting of nvm image version to include the gphy (i225 phy) firmware version.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
expose the gphy firmware version
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['igb ']
|
['h', 'c']
| 5
| 28
| 3
|
--- diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h --- a/drivers/net/ethernet/intel/igc/igc.h +++ b/drivers/net/ethernet/intel/igc/igc.h - char fw_version[16]; + char fw_version[32]; diff --git a/drivers/net/ethernet/intel/igc/igc_ethtool.c b/drivers/net/ethernet/intel/igc/igc_ethtool.c --- a/drivers/net/ethernet/intel/igc/igc_ethtool.c +++ b/drivers/net/ethernet/intel/igc/igc_ethtool.c + u16 gphy_version; + /* gphy firmware version is reported as phy fw version */ + gphy_version = igc_read_phy_fw_version(hw); + - "%x", - nvm_version); + "%x:%x", + nvm_version, + gphy_version); diff --git a/drivers/net/ethernet/intel/igc/igc_phy.c b/drivers/net/ethernet/intel/igc/igc_phy.c --- a/drivers/net/ethernet/intel/igc/igc_phy.c +++ b/drivers/net/ethernet/intel/igc/igc_phy.c + +/** + * igc_read_phy_fw_version - read gphy firmware version + * @hw: pointer to the hw structure + */ +u16 igc_read_phy_fw_version(struct igc_hw *hw) +{ + struct igc_phy_info *phy = &hw->phy; + u16 gphy_version = 0; + u16 ret_val; + + /* nvm image version is reported as firmware version for i225 device */ + ret_val = phy->ops.read_reg(hw, igc_gphy_version, &gphy_version); + if (ret_val) + hw_dbg("igc_phy: read wrong gphy version "); + + return gphy_version; +} diff --git a/drivers/net/ethernet/intel/igc/igc_phy.h b/drivers/net/ethernet/intel/igc/igc_phy.h --- a/drivers/net/ethernet/intel/igc/igc_phy.h +++ b/drivers/net/ethernet/intel/igc/igc_phy.h +u16 igc_read_phy_fw_version(struct igc_hw *hw); diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h --- a/drivers/net/ethernet/intel/igc/igc_regs.h +++ b/drivers/net/ethernet/intel/igc/igc_regs.h +#define igc_gphy_version 0x0001e /* i225 gphy firmware version */
|
Networking
|
94f794d15a5ea902aabf148f17f5310a2f6ccd67
|
sasha neftin
|
drivers
|
net
|
ethernet, igc, intel
|
iwlwifi: mvm: add rfi-m support
|
rf interference mitigation is a new feature targeted to handle the problem of interference between ddr memory and wifi. the role of the driver is to configure fw with the table holding a mapping between problematic channels/bands and the corresponding frequencies.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support for rf interference mitigation (rfi)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c', 'makefile']
| 8
| 261
| 1
|
- send rfi configuration command (currently with a default table) which - read the table, used by the fw (which can be a subset of the table --- diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h b/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h --- a/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/commands.h + + /** + * @rfi_config_cmd: &struct iwl_rfi_config_cmd + */ + rfi_config_cmd = 0xb, + + /** + * @rfi_get_freq_table_cmd: &struct iwl_rfi_config_cmd + */ + rfi_get_freq_table_cmd = 0xc, diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/rfi.h b/drivers/net/wireless/intel/iwlwifi/fw/api/rfi.h --- /dev/null +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/rfi.h +/* spdx-license-identifier: gpl-2.0 or bsd-3-clause */ +/* + * copyright (c) 2020 intel corporation + */ +#ifndef __iwl_fw_api_rfi_h__ +#define __iwl_fw_api_rfi_h__ + +#define iwl_rfi_lut_entry_channels_num 15 +#define iwl_rfi_lut_size 24 +#define iwl_rfi_lut_installed_size 4 + +/** + * struct iwl_rfi_lut_entry - an entry in the rfi frequency lut. + * + * @freq: frequency + * @channels: channels that can be interfered at frequency freq (at most 15) + * @bands: the corresponding bands + */ +struct iwl_rfi_lut_entry { + __le16 freq; + u8 channels[iwl_rfi_lut_entry_channels_num]; + u8 bands[iwl_rfi_lut_entry_channels_num]; +} __packed; + +/** + * struct iwl_rfi_config_cmd - rfi configuration table + * + * @entry: a table can have 24 frequency/channel mappings + * @oem: specifies if this is the default table or set by oem + */ +struct iwl_rfi_config_cmd { + struct iwl_rfi_lut_entry table[iwl_rfi_lut_size]; + u8 oem; + u8 reserved[3]; +} __packed; /* rfi_config_cmd_api_s_ver_1 */ + +/** + * iwl_rfi_freq_table_status - status of the frequency table query + * @rfi_freq_table_ok: can be used + * @rfi_freq_table_dvfs_not_ready: dvfs is not ready yet, should try later + * @rfi_freq_table_disabled: the feature is disabled in fw + */ +enum iwl_rfi_freq_table_status { + rfi_freq_table_ok, + rfi_freq_table_dvfs_not_ready, + rfi_freq_table_disabled, +}; + +/** + * struct iwl_rfi_freq_table_resp_cmd - get the rfi freq table used by fw + * + * @table: table used by fw + * @status: see &iwl_rfi_freq_table_status + */ +struct iwl_rfi_freq_table_resp_cmd { + struct iwl_rfi_lut_entry table[iwl_rfi_lut_installed_size]; + __le32 status; +} __packed; /* rfi_config_cmd_api_s_ver_1 */ + +#endif /* __iwl_fw_api_rfi_h__ */ diff --git a/drivers/net/wireless/intel/iwlwifi/fw/file.h b/drivers/net/wireless/intel/iwlwifi/fw/file.h --- a/drivers/net/wireless/intel/iwlwifi/fw/file.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/file.h + iwl_ucode_tlv_capa_rfim_support = (__force iwl_ucode_tlv_capa_t)102, diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/makefile b/drivers/net/wireless/intel/iwlwifi/mvm/makefile --- a/drivers/net/wireless/intel/iwlwifi/mvm/makefile +++ b/drivers/net/wireless/intel/iwlwifi/mvm/makefile +iwlmvm-y += rfi.o diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +static ssize_t iwl_dbgfs_rfi_freq_table_write(struct iwl_mvm *mvm, char *buf, + size_t count, loff_t *ppos) +{ + int ret = 0; + u16 op_id; + + if (kstrtou16(buf, 10, &op_id)) + return -einval; + + /* value zero triggers re-sending the default table to the device */ + if (!op_id) + ret = iwl_rfi_send_config_cmd(mvm, null); + else + ret = -eopnotsupp; /* in the future a new table will be added */ + + return ret ?: count; +} + +/* the size computation is as follows: + * each number needs at most 3 characters, number of rows is the size of + * the table; so, need 5 chars for the "freq: " part and each tuple afterwards + * needs 6 characters for numbers and 5 for the punctuation around. + */ +#define iwl_rfi_buf_size (iwl_rfi_lut_installed_size *\ + (5 + iwl_rfi_lut_entry_channels_num * (6 + 5))) + +static ssize_t iwl_dbgfs_rfi_freq_table_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct iwl_mvm *mvm = file->private_data; + struct iwl_rfi_freq_table_resp_cmd *resp; + u32 status; + char buf[iwl_rfi_buf_size]; + int i, j, pos = 0; + + resp = iwl_rfi_get_freq_table(mvm); + if (is_err(resp)) + return ptr_err(resp); + + status = le32_to_cpu(resp->status); + if (status != rfi_freq_table_ok) { + scnprintf(buf, iwl_rfi_buf_size, "status = %d ", status); + goto out; + } + + for (i = 0; i < array_size(resp->table); i++) { + pos += scnprintf(buf + pos, iwl_rfi_buf_size - pos, "%d: ", + resp->table[i].freq); + + for (j = 0; j < array_size(resp->table[i].channels); j++) + pos += scnprintf(buf + pos, iwl_rfi_buf_size - pos, + "(%d, %d) ", + resp->table[i].channels[j], + resp->table[i].bands[j]); + pos += scnprintf(buf + pos, iwl_rfi_buf_size - pos, " "); + } + +out: + kfree(resp); + return simple_read_from_buffer(user_buf, count, ppos, buf, pos); +} + +mvm_debugfs_read_write_file_ops(rfi_freq_table, 16); + mvm_debugfs_add_file(rfi_freq_table, mvm->debugfs_dir, 0600); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw-api.h b/drivers/net/wireless/intel/iwlwifi/mvm/fw-api.h --- a/drivers/net/wireless/intel/iwlwifi/mvm/fw-api.h +++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw-api.h - * copyright (c) 2012-2014, 2018 intel corporation + * copyright (c) 2012-2014, 2018, 2020 intel corporation +#include "fw/api/rfi.h" diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h --- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm, + struct iwl_rfi_lut_entry *rfi_table); +struct iwl_rfi_freq_table_resp_cmd *iwl_rfi_get_freq_table(struct iwl_mvm *mvm); + diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/rfi.c b/drivers/net/wireless/intel/iwlwifi/mvm/rfi.c --- /dev/null +++ b/drivers/net/wireless/intel/iwlwifi/mvm/rfi.c +// spdx-license-identifier: gpl-2.0 or bsd-3-clause +/* + * copyright (c) 2020 intel corporation + */ + +#include "mvm.h" +#include "fw/api/commands.h" +#include "fw/api/phy-ctxt.h" + +/** + * ddr needs frequency in units of 16.666mhz, so provide fw with the + * frequency values in the adjusted format. + */ +const static struct iwl_rfi_lut_entry iwl_rfi_table[iwl_rfi_lut_size] = { + /* lpddr4 */ + + /* frequency 3733mhz */ + {cpu_to_le16(223), {114, 116, 118, 120, 122,}, + {phy_band_5, phy_band_5, phy_band_5, phy_band_5, phy_band_5,}}, + + /* frequency 4267mhz */ + {cpu_to_le16(256), {79, 83, 85, 87, 89, 91, 93,}, + {phy_band_6, phy_band_6, phy_band_6, phy_band_6, phy_band_6, + phy_band_6, phy_band_6,}}, + + /* ddr5epor */ + + /* frequency 4000mhz */ + {cpu_to_le16(240), {3, 5, 7, 9, 11, 13, 15,}, + {phy_band_6, phy_band_6, phy_band_6, phy_band_6, phy_band_6, + phy_band_6, phy_band_6,}}, + + /* frequency 4400mhz */ + {cpu_to_le16(264), {111, 119, 123, 125, 129, 131, 133, 135, 143,}, + {phy_band_6, phy_band_6, phy_band_6, phy_band_6, phy_band_6, + phy_band_6, phy_band_6, phy_band_6, phy_band_6,}}, + + /* lpddr5ipor */ + + /* frequency 5200mhz */ + {cpu_to_le16(312), {36, 38, 40, 42, 50,}, + {phy_band_5, phy_band_5, phy_band_5, phy_band_5, phy_band_5,}}, + + /* frequency 6000mhz */ + {cpu_to_le16(360), {3, 5, 7, 9, 11, 13, 15,}, + {phy_band_6, phy_band_6, phy_band_6, phy_band_6, phy_band_6, + phy_band_6, phy_band_6,}}, + + /* frequency 6400mhz */ + {cpu_to_le16(384), {79, 83, 85, 87, 89, 91, 93,}, + {phy_band_6, phy_band_6, phy_band_6, phy_band_6, phy_band_6, + phy_band_6, phy_band_6,}}, +}; + +int iwl_rfi_send_config_cmd(struct iwl_mvm *mvm, struct iwl_rfi_lut_entry *rfi_table) +{ + int ret; + struct iwl_rfi_config_cmd cmd; + struct iwl_host_cmd hcmd = { + .id = wide_id(system_group, rfi_config_cmd), + .dataflags[0] = iwl_hcmd_dfl_dup, + .data[0] = &cmd, + .len[0] = sizeof(cmd), + }; + + if (!fw_has_capa(&mvm->fw->ucode_capa, iwl_ucode_tlv_capa_rfim_support)) + return -eopnotsupp; + + /* in case no table is passed, use the default one */ + if (!rfi_table) { + memcpy(cmd.table, iwl_rfi_table, sizeof(cmd.table)); + } else { + memcpy(cmd.table, rfi_table, sizeof(cmd.table)); + /* notify fw the table is not the default one */ + cmd.oem = 1; + } + + mutex_lock(&mvm->mutex); + ret = iwl_mvm_send_cmd(mvm, &hcmd); + mutex_unlock(&mvm->mutex); + + if (ret) + iwl_err(mvm, "failed to send rfi config cmd %d ", ret); + + return ret; +} + +struct iwl_rfi_freq_table_resp_cmd *iwl_rfi_get_freq_table(struct iwl_mvm *mvm) +{ + struct iwl_rfi_freq_table_resp_cmd *resp; + int resp_size = sizeof(*resp); + int ret; + struct iwl_host_cmd cmd = { + .id = wide_id(system_group, rfi_get_freq_table_cmd), + .flags = cmd_want_skb, + }; + + if (!fw_has_capa(&mvm->fw->ucode_capa, iwl_ucode_tlv_capa_rfim_support)) + return err_ptr(-eopnotsupp); + + mutex_lock(&mvm->mutex); + ret = iwl_mvm_send_cmd(mvm, &cmd); + mutex_unlock(&mvm->mutex); + if (ret) + return err_ptr(ret); + + if (warn_on_once(iwl_rx_packet_payload_len(cmd.resp_pkt) != resp_size)) + return err_ptr(-eio); + + resp = kzalloc(resp_size, gfp_kernel); + if (!resp) + return err_ptr(-enomem); + + memcpy(resp, cmd.resp_pkt->data, resp_size); + + iwl_free_resp(&cmd); + return resp; +}
|
Networking
|
21254908cbe995a3982a23da32c30d1b43467043
|
gregory greenman
|
drivers
|
net
|
api, fw, intel, iwlwifi, mvm, wireless
|
iwlwifi: acpi: add support for dsm rfi
|
bios provides rfi feature enable/disable state via wifi dsm acpi object. by default the feature should be disabled. the guid for this feature is different from the one driver currently uses, so need to provide a set of new definitions.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support for rf interference mitigation (rfi)
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 3
| 75
| 14
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c --- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.c -static const guid_t intel_wifi_guid = guid_init(0xf21202bf, 0x8f78, 0x4dc6, - 0xa5, 0xb3, 0x1f, 0x73, - 0x8e, 0x28, 0x5a, 0xde); +const guid_t iwl_guid = guid_init(0xf21202bf, 0x8f78, 0x4dc6, + 0xa5, 0xb3, 0x1f, 0x73, + 0x8e, 0x28, 0x5a, 0xde); +iwl_export_symbol(iwl_guid); + +const guid_t iwl_rfi_guid = guid_init(0x7266172c, 0x220b, 0x4b29, + 0x81, 0x4f, 0x75, 0xe4, + 0xdd, 0x26, 0xb5, 0xfd); +iwl_export_symbol(iwl_rfi_guid); - union acpi_object *args) + union acpi_object *args, + const guid_t *guid) - obj = acpi_evaluate_dsm(acpi_handle(dev), &intel_wifi_guid, rev, func, + obj = acpi_evaluate_dsm(acpi_handle(dev), guid, rev, func, - u64 *value, size_t expected_size) + const guid_t *guid, u64 *value, + size_t expected_size) - obj = iwl_acpi_get_dsm_object(dev, rev, func, null); + obj = iwl_acpi_get_dsm_object(dev, rev, func, null, guid); -int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, u8 *value) +int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, + const guid_t *guid, u8 *value) - ret = iwl_acpi_get_dsm_integer(dev, rev, func, &val, sizeof(u8)); + ret = iwl_acpi_get_dsm_integer(dev, rev, func, + guid, &val, sizeof(u8)); diff --git a/drivers/net/wireless/intel/iwlwifi/fw/acpi.h b/drivers/net/wireless/intel/iwlwifi/fw/acpi.h --- a/drivers/net/wireless/intel/iwlwifi/fw/acpi.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/acpi.h +/* dsm rfi uses a different guid, so need separate definitions */ + +#define dsm_rfi_func_enable 3 + +enum iwl_dsm_values_rfi { + dsm_value_rfi_enable, + dsm_value_rfi_disable, + dsm_value_rfi_max +}; + +extern const guid_t iwl_guid; +extern const guid_t iwl_rfi_guid; + -int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, u8 *value); +int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, + const guid_t *guid, u8 *value); -static inline -int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, u8 *value) +static inline int iwl_acpi_get_dsm_u8(struct device *dev, int rev, int func, + const guid_t *guid, u8 *value) diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c - dsm_func_enable_indonesia_5g2, &value); + dsm_func_enable_indonesia_5g2, + &iwl_guid, &value); +static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm) +{ + u8 value; + int ret = iwl_acpi_get_dsm_u8((&mvm->fwrt)->dev, 0, dsm_rfi_func_enable, + &iwl_rfi_guid, &value); + + if (ret < 0) { + iwl_debug_radio(mvm, "failed to get dsm rfi, ret=%d ", ret); + + } else if (value >= dsm_value_rfi_max) { + iwl_debug_radio(mvm, "dsm rfi got invalid value, ret=%d ", + value); + + } else if (value == dsm_value_rfi_enable) { + iwl_debug_radio(mvm, "dsm rfi is evaluated to enable "); + return dsm_value_rfi_enable; + } + + iwl_debug_radio(mvm, "dsm rfi is disabled "); + + /* default behaviour is disabled */ + return dsm_value_rfi_disable; +} + - dsm_func_disable_srd, &value); + dsm_func_disable_srd, + &iwl_guid, &value); + +static u8 iwl_mvm_eval_dsm_rfi(struct iwl_mvm *mvm) +{ + return dsm_value_rfi_disable; +} + if (fw_has_capa(&mvm->fw->ucode_capa, + iwl_ucode_tlv_capa_rfim_support)) { + if (iwl_mvm_eval_dsm_rfi(mvm) == dsm_value_rfi_enable) + iwl_rfi_send_config_cmd(mvm, null); + } +
|
Networking
|
4e8fe214f7c0ca75f512dd573f944221ecdf053e
|
gregory greenman
|
drivers
|
net
|
fw, intel, iwlwifi, mvm, wireless
|
iwlwifi: add new cards for so and qu family
|
add few pci id's for so with hr and qu with hr in ax family.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add new cards for so and qu family
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 3
| 46
| 0
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c --- a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c +++ b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c +const struct iwl_cfg iwl_cfg_so_a0_hr_a0 = { + .fw_name_pre = iwl_so_a_hr_b_fw_pre, + iwl_device_ax210, + .num_rbds = iwl_num_rbds_ax210_he, +}; + +const struct iwl_cfg iwl_cfg_quz_a0_hr_b0 = { + .fw_name_pre = iwl_quz_a_hr_b_fw_pre, + iwl_device_22500, + /* + * this device doesn't support receiving blockack with a large bitmap + * so we need to restrict the size of transmitted aggregation to the + * ht size; mac80211 would otherwise pick the he max (256) by default. + */ + .max_tx_agg_size = ieee80211_max_ampdu_buf_ht, + .num_rbds = iwl_num_rbds_22000_he, +}; + diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-config.h b/drivers/net/wireless/intel/iwlwifi/iwl-config.h --- a/drivers/net/wireless/intel/iwlwifi/iwl-config.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-config.h +extern const struct iwl_cfg iwl_cfg_so_a0_hr_a0; +extern const struct iwl_cfg iwl_cfg_quz_a0_hr_b0; diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_quz, silicon_b_step, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_no_160, iwl_cfg_any, + iwl_cfg_quz_a0_hr_b0, iwl_ax203_name), +/* so with hr */ + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_so, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_no_160, iwl_cfg_any, + iwl_cfg_so_a0_hr_a0, iwl_ax203_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_so, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_no_160, iwl_cfg_any, + iwl_cfg_so_a0_hr_a0, iwl_ax203_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_so, iwl_cfg_any, + iwl_cfg_rf_type_hr1, iwl_cfg_any, + iwl_cfg_160, iwl_cfg_any, + iwl_cfg_so_a0_hr_a0, iwl_ax101_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_so, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_160, iwl_cfg_any, + iwl_cfg_so_a0_hr_a0, iwl_ax201_name)
|
Networking
|
410f758529bc227b186ba0846bcc75ac0700ffb2
|
ihab zhaika
|
drivers
|
net
|
cfg, intel, iwlwifi, pcie, wireless
|
iwlwifi: add support for qu with ax201 device
|
add this specific samsung ax201 sku to driver so it can be detected and initialized successfully.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for qu with ax201 device
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['c']
| 1
| 1
| 0
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c + iwl_dev_info(0x4df0, 0x6074, iwl_ax201_cfg_qu_hr, null),
|
Networking
|
97195d3cad852063208a1cd4f4d073459547a415
|
matt chen
|
drivers
|
net
|
intel, iwlwifi, pcie, wireless
|
iwlwifi: add support for snj with jf devices
|
add support for snj devices with jf and a workaround for some cases where the devices erroneously show as qnj devices.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for snj with jf devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 3
| 75
| 18
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c --- a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c +++ b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c +#define iwl_snj_a_jf_b_fw_pre "iwlwifi-sosnj-a0-jf-b0-" -#define iwl_ma_a_gf_a_fw_module_firmware(api) \ +#define iwl_snj_a_jf_b_module_firmware(api) \ + iwl_snj_a_jf_b_fw_pre __stringify(api) ".ucode" +#define iwl_ma_a_gf_a_fw_module_firmware(api) \ -const struct iwl_cfg iwlax201_cfg_snj_hr_b0 = { - .name = iwl_ax201_name, - .fw_name_pre = iwl_qu_b_hr_b_fw_pre, +const struct iwl_cfg iwl_cfg_snj_hr_b0 = { + .fw_name_pre = iwl_snj_a_hr_b_fw_pre, + .uhb_supported = true, + iwl_device_ax210, + .num_rbds = iwl_num_rbds_ax210_he, +}; + +const struct iwl_cfg iwl_cfg_snj_a0_jf_b0 = { + .fw_name_pre = iwl_snj_a_jf_b_fw_pre, +module_firmware(iwl_snj_a_jf_b_module_firmware(iwl_22000_ucode_api_max)); diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-config.h b/drivers/net/wireless/intel/iwlwifi/iwl-config.h --- a/drivers/net/wireless/intel/iwlwifi/iwl-config.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-config.h -extern const struct iwl_cfg iwlax201_cfg_snj_hr_b0; +extern const struct iwl_cfg iwl_cfg_snj_hr_b0; +extern const struct iwl_cfg iwl_cfg_snj_a0_jf_b0; diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c - /* qnj with hr */ - iwl_dev_info(0x2720, iwl_cfg_any, iwl_qnj_b0_hr_b0_cfg, iwl_ax201_name), - - iwl_dev_info(0x2726, 0x0070, iwlax201_cfg_snj_hr_b0, null), - iwl_dev_info(0x2726, 0x0074, iwlax201_cfg_snj_hr_b0, null), - iwl_dev_info(0x2726, 0x0078, iwlax201_cfg_snj_hr_b0, null), - iwl_dev_info(0x2726, 0x007c, iwlax201_cfg_snj_hr_b0, null), - iwl_dev_info(0x2726, 0x2074, iwlax201_cfg_snj_hr_b0, null), - iwl_dev_info(0x2726, 0x4070, iwlax201_cfg_snj_hr_b0, null), - iwl_dev_info(0x2726, 0x0244, iwlax201_cfg_snj_hr_b0, iwl_ax101_name), - iwl_dev_info(0x2726, 0x1651, iwlax201_cfg_snj_hr_b0, iwl_ax201_killer_1650s_name), - iwl_dev_info(0x2726, 0x1652, iwlax201_cfg_snj_hr_b0, iwl_ax201_killer_1650i_name), - iwl_dev_info(0x2726, 0x4244, iwlax201_cfg_snj_hr_b0, iwl_ax101_name), + iwl_dev_info(0x2726, 0x1651, iwl_cfg_snj_hr_b0, iwl_ax201_killer_1650s_name), + iwl_dev_info(0x2726, 0x1652, iwl_cfg_snj_hr_b0, iwl_ax201_killer_1650i_name), +/* qnj with hr */ + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_qnj, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_any, iwl_cfg_any, + iwl_qnj_b0_hr_b0_cfg, iwl_ax201_name), + +/* snj with jf */ + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_jf1, iwl_cfg_rf_id_jf1, + iwl_cfg_160, iwl_cfg_cores_bt, + iwl_cfg_snj_a0_jf_b0, iwl9461_160_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_jf1, iwl_cfg_rf_id_jf1, + iwl_cfg_no_160, iwl_cfg_cores_bt, + iwl_cfg_snj_a0_jf_b0, iwl9461_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_jf1, iwl_cfg_rf_id_jf1_div, + iwl_cfg_160, iwl_cfg_cores_bt, + iwl_cfg_snj_a0_jf_b0, iwl9462_160_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_jf1, iwl_cfg_rf_id_jf1_div, + iwl_cfg_no_160, iwl_cfg_cores_bt, + iwl_cfg_snj_a0_jf_b0, iwl9462_name), + + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_jf2, iwl_cfg_rf_id_jf, + iwl_cfg_160, iwl_cfg_cores_bt, + iwl_cfg_snj_a0_jf_b0, iwl9560_160_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_jf2, iwl_cfg_rf_id_jf, + iwl_cfg_no_160, iwl_cfg_cores_bt, + iwl_cfg_snj_a0_jf_b0, iwl9560_name), + +/* snj with hr */ + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_any, iwl_cfg_any, + iwl_cfg_snj_hr_b0, iwl_ax201_name), + + /* + * workaround for problematic snj device: sometimes when + * certain rf modules are connected to snj, the device id + * changes to qnj's id. so we are using qnj's trans_cfg until + * here. but if we detect that the mac type is actually snj, + * we should switch to it here to avoid problems later. + */ + if (csr_hw_rev_type(iwl_trans->hw_rev) == iwl_cfg_mac_type_snj) + iwl_trans->trans_cfg = &iwl_so_trans_cfg; +
|
Networking
|
930be4e76f262ede9927fb7d1ca525736cdc3669
|
luca coelho
|
drivers
|
net
|
cfg, intel, iwlwifi, pcie, wireless
|
iwlwifi: mvm: support scan_cfg_cmd version 5
|
since the firmware support for internal station for auxiliary activities, there is no need to configure an auxiliary station as part of scan_cfg_cmd. thus, this configuration was removed from the corresponding structure.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support new scan config fw api
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 2
| 11
| 8
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h b/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h --- a/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/scan.h - * @bcast_sta_id: the index of the station in the fw + * @bcast_sta_id: the index of the station in the fw. deprecated starting with + * api version 5. -} __packed; /* scan_config_db_cmd_api_s_3 */ +} __packed; /* scan_config_db_cmd_api_s_5 */ diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/scan.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/scan.c - add_sta, 0) < 12) + add_sta, 0) < 12) { - /* - * fw doesn't use this sta anymore, pending deprecation via host api - * change. - */ - else + } else if (iwl_fw_lookup_cmd_ver(mvm->fw, long_group, + scan_cfg_cmd, 0) < 5) { + /* + * fw doesn't use this sta anymore. deprecated on scan_cfg_cmd + * version 5. + */ + }
|
Networking
|
e1900bceab6af27989d71b067760cf9de0f81598
|
ilan peer
|
drivers
|
net
|
api, fw, intel, iwlwifi, mvm, wireless
|
iwlwifi: mvm: add debugfs entry to trigger a dump as any time-point
|
this is used for different tests collecting different types of debug data from fw (e.g latency issues, hw issues etc).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add debugfs entry to trigger a dump as any time-point
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['c']
| 1
| 19
| 0
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +static ssize_t iwl_dbgfs_dbg_time_point_write(struct iwl_mvm *mvm, + char *buf, size_t count, + loff_t *ppos) +{ + u32 timepoint; + + if (kstrtou32(buf, 0, &timepoint)) + return -einval; + + if (timepoint == iwl_fw_ini_time_point_invalid || + timepoint >= iwl_fw_ini_time_point_num) + return -einval; + + iwl_dbg_tlv_time_point(&mvm->fwrt, timepoint, null); + + return count; +} + +mvm_debugfs_write_file_ops(dbg_time_point, 64);
|
Networking
|
9dbb62a29042e543ab6671dc12c1473c3cbc58c2
|
mordechay goodstein
|
drivers
|
net
|
intel, iwlwifi, mvm, wireless
|
iwlwifi: mvm: debugfs for phy-integration-ver
|
add debugfs file to print the phy integration version. file name is: phy_integration_ver
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add debugfs for phy-integration-ver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['c']
| 1
| 28
| 0
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/debugfs.c +static ssize_t iwl_dbgfs_phy_integration_ver_read(struct file *file, + char __user *user_buf, + size_t count, loff_t *ppos) +{ + struct iwl_mvm *mvm = file->private_data; + char *buf; + size_t bufsz; + int pos; + ssize_t ret; + + bufsz = mvm->fw->phy_integration_ver_len + 2; + buf = kmalloc(bufsz, gfp_kernel); + if (!buf) + return -enomem; + + pos = scnprintf(buf, bufsz, "%.*s ", mvm->fw->phy_integration_ver_len, + mvm->fw->phy_integration_ver); + + ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); + + kfree(buf); + return ret; +} + +mvm_debugfs_read_file_ops(phy_integration_ver); + + if (mvm->fw->phy_integration_ver) + mvm_debugfs_add_file(phy_integration_ver, mvm->debugfs_dir, 0400);
|
Networking
|
33fa519ac6184a73704dab877483daf2b5f8a279
|
dror moshe
|
drivers
|
net
|
intel, iwlwifi, mvm, wireless
|
iwlwifi: mvm: handle cca-ext delay firmware notification
|
if there are frequent cca delays due to the extension channel as detected by the firmware, and we're on 2.4 ghz, then handle this by disconnecting (with a reconnect hint).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
handle cca-ext delay firmware notification
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 5
| 157
| 1
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h b/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h --- a/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/datapath.h - * copyright (c) 2012-2014, 2018-2019 intel corporation + * copyright (c) 2012-2014, 2018-2020 intel corporation + /** + * @monitor_notif: datapath monitoring notification, using + * &struct iwl_datapath_monitor_notif + */ + monitor_notif = 0xf4, + +enum iwl_datapath_monitor_notif_type { + iwl_dp_mon_notif_type_ext_cca, +}; + +struct iwl_datapath_monitor_notif { + __le32 type; + u8 mac_id; + u8 reserved[3]; +} __packed; /* monitor_ntf_api_s_ver_1 */ + diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mac80211.c +static void iwl_mvm_reset_cca_40mhz_workaround(struct iwl_mvm *mvm, + struct ieee80211_vif *vif) +{ + struct ieee80211_supported_band *sband; + const struct ieee80211_sta_he_cap *he_cap; + + if (vif->type != nl80211_iftype_station) + return; + + if (!mvm->cca_40mhz_workaround) + return; + + /* decrement and check that we reached zero */ + mvm->cca_40mhz_workaround--; + if (mvm->cca_40mhz_workaround) + return; + + sband = mvm->hw->wiphy->bands[nl80211_band_2ghz]; + + sband->ht_cap.cap |= ieee80211_ht_cap_sup_width_20_40; + + he_cap = ieee80211_get_he_iftype_cap(sband, + ieee80211_vif_type_p2p(vif)); + + if (he_cap) { + /* we know that ours is writable */ + struct ieee80211_sta_he_cap *he = (void *)he_cap; + + he->he_cap_elem.phy_cap_info[0] |= + ieee80211_he_phy_cap0_channel_width_set_40mhz_in_2g; + } +} + + + /* + * additionally, reset the 40 mhz capability if we disconnected + * from the ap now. + */ + iwl_mvm_reset_cca_40mhz_workaround(mvm, vif); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h --- a/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h +++ b/drivers/net/wireless/intel/iwlwifi/mvm/mvm.h + u8 cca_40mhz_workaround; + +struct ieee80211_vif *iwl_mvm_get_vif_by_macid(struct iwl_mvm *mvm, u32 macid); diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/ops.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/ops.c +static void iwl_mvm_rx_monitor_notif(struct iwl_mvm *mvm, + struct iwl_rx_cmd_buffer *rxb) +{ + struct iwl_rx_packet *pkt = rxb_addr(rxb); + struct iwl_datapath_monitor_notif *notif = (void *)pkt->data; + struct ieee80211_supported_band *sband; + const struct ieee80211_sta_he_cap *he_cap; + struct ieee80211_vif *vif; + + if (notif->type != cpu_to_le32(iwl_dp_mon_notif_type_ext_cca)) + return; + + vif = iwl_mvm_get_vif_by_macid(mvm, notif->mac_id); + if (!vif || vif->type != nl80211_iftype_station) + return; + + if (!vif->bss_conf.chandef.chan || + vif->bss_conf.chandef.chan->band != nl80211_band_2ghz || + vif->bss_conf.chandef.width < nl80211_chan_width_40) + return; + + if (!vif->bss_conf.assoc) + return; + + /* this shouldn't happen *again*, ignore it */ + if (mvm->cca_40mhz_workaround) + return; + + /* + * we'll decrement this on disconnect - so set to 2 since we'll + * still have to disconnect from the current ap first. + */ + mvm->cca_40mhz_workaround = 2; + + /* + * this capability manipulation isn't really ideal, but it's the + * easiest choice - otherwise we'd have to do some major changes + * in mac80211 to support this, which isn't worth it. this does + * mean that userspace may have outdated information, but that's + * actually not an issue at all. + */ + sband = mvm->hw->wiphy->bands[nl80211_band_2ghz]; + + warn_on(!sband->ht_cap.ht_supported); + warn_on(!(sband->ht_cap.cap & ieee80211_ht_cap_sup_width_20_40)); + sband->ht_cap.cap &= ~ieee80211_ht_cap_sup_width_20_40; + + he_cap = ieee80211_get_he_iftype_cap(sband, + ieee80211_vif_type_p2p(vif)); + + if (he_cap) { + /* we know that ours is writable */ + struct ieee80211_sta_he_cap *he = (void *)he_cap; + + warn_on(!he->has_he); + warn_on(!(he->he_cap_elem.phy_cap_info[0] & + ieee80211_he_phy_cap0_channel_width_set_40mhz_in_2g)); + he->he_cap_elem.phy_cap_info[0] &= + ~ieee80211_he_phy_cap0_channel_width_set_40mhz_in_2g; + } + + ieee80211_disconnect(vif, true); +} + + rx_handler_grp(data_path_group, monitor_notif, + iwl_mvm_rx_monitor_notif, rx_handler_async_locked, + struct iwl_datapath_monitor_notif), + hcmd_name(monitor_notif), diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/utils.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/utils.c +struct iwl_bss_find_iter_data { + struct ieee80211_vif *vif; + u32 macid; +}; + +static void iwl_mvm_bss_find_iface_iterator(void *_data, u8 *mac, + struct ieee80211_vif *vif) +{ + struct iwl_bss_find_iter_data *data = _data; + struct iwl_mvm_vif *mvmvif = iwl_mvm_vif_from_mac80211(vif); + + if (mvmvif->id == data->macid) + data->vif = vif; +} + +struct ieee80211_vif *iwl_mvm_get_vif_by_macid(struct iwl_mvm *mvm, u32 macid) +{ + struct iwl_bss_find_iter_data data = { + .macid = macid, + }; + + lockdep_assert_held(&mvm->mutex); + + ieee80211_iterate_active_interfaces_atomic( + mvm->hw, ieee80211_iface_iter_normal, + iwl_mvm_bss_find_iface_iterator, &data); + + return data.vif; +} +
|
Networking
|
f7d6ef33a779c866721eea2b980f51bda1994a04
|
johannes berg
|
drivers
|
net
|
api, fw, intel, iwlwifi, mvm, wireless
|
iwlwifi: pcie: add ax201 and ax211 radio modules for ma devices
|
add support for ax201 and ax211 radio modules, which we call hr2 and gf, respectively. these modules can be used with the ma family of devices and above.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add ax201 and ax211 radio modules for ma devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 3
| 34
| 0
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c --- a/drivers/net/wireless/intel/iwlwifi/cfg/22000.c +++ b/drivers/net/wireless/intel/iwlwifi/cfg/22000.c +#define iwl_ma_a_hr_b_fw_pre "iwlwifi-ma-a0-hr-b0-" +#define iwl_ma_a_gf4_a_fw_pre "iwlwifi-ma-a0-gf4-a0-" +#define iwl_ma_a_hr_b_fw_module_firmware(api) \ + iwl_ma_a_hr_b_fw_pre __stringify(api) ".ucode" +#define iwl_ma_a_gf4_a_fw_module_firmware(api) \ + iwl_ma_a_gf4_a_fw_pre __stringify(api) ".ucode" +const struct iwl_cfg iwl_cfg_ma_a0_hr_b0 = { + .fw_name_pre = iwl_ma_a_hr_b_fw_pre, + .uhb_supported = true, + iwl_device_ax210, + .num_rbds = iwl_num_rbds_ax210_he, +}; + +const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0 = { + .fw_name_pre = iwl_ma_a_gf4_a_fw_pre, + .uhb_supported = true, + iwl_device_ax210, + .num_rbds = iwl_num_rbds_ax210_he, +}; + +module_firmware(iwl_ma_a_hr_b_fw_module_firmware(iwl_22000_ucode_api_max)); +module_firmware(iwl_ma_a_gf4_a_fw_module_firmware(iwl_22000_ucode_api_max)); diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-config.h b/drivers/net/wireless/intel/iwlwifi/iwl-config.h --- a/drivers/net/wireless/intel/iwlwifi/iwl-config.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-config.h +extern const struct iwl_cfg iwl_cfg_ma_a0_hr_b0; +extern const struct iwl_cfg iwl_cfg_ma_a0_gf4_a0; diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_ma, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_any, iwl_cfg_any, iwl_cfg_no_cdb, + iwl_cfg_ma_a0_hr_b0, iwl_ax201_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_ma, iwl_cfg_any, + iwl_cfg_rf_type_gf, iwl_cfg_any, + iwl_cfg_any, iwl_cfg_any, iwl_cfg_cdb, + iwl_cfg_ma_a0_gf4_a0, iwl_ax211_name),
|
Networking
|
1205d7f7ffb18dd96347d8a2a35dba859510e2d7
|
matti gottlieb
|
drivers
|
net
|
cfg, intel, iwlwifi, pcie, wireless
|
iwlwifi: pcie: add support for snj with hr1
|
add an entry for snj with hr1. this device should use the tx_with_siso_diversity option, but that doesn't work at the moment. so we leave it disabled for now (and use the same struct as hr2).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
aadd support for snj with hr1
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['c']
| 1
| 6
| 0
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_snj, iwl_cfg_any, + iwl_cfg_rf_type_hr1, iwl_cfg_any, + iwl_cfg_any, iwl_cfg_any, + iwl_cfg_snj_hr_b0, iwl_ax101_name), +
|
Networking
|
7f9c3bc465b20245c11a2455ed2770d02b0adf4c
|
luca coelho
|
drivers
|
net
|
intel, iwlwifi, pcie, wireless
|
iwlwifi: pcie: add support for so-f devices
|
we have a new type of device that has a different mac id, but is otherwise identical to so devices. add rules to match this new id accordingly.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for so-f devices
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 2
| 26
| 1
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/iwl-config.h b/drivers/net/wireless/intel/iwlwifi/iwl-config.h --- a/drivers/net/wireless/intel/iwlwifi/iwl-config.h +++ b/drivers/net/wireless/intel/iwlwifi/iwl-config.h +#define iwl_cfg_mac_type_sof 0x43 diff --git a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c --- a/drivers/net/wireless/intel/iwlwifi/pcie/drv.c +++ b/drivers/net/wireless/intel/iwlwifi/pcie/drv.c - iwl_cfg_so_a0_hr_a0, iwl_ax201_name) + iwl_cfg_so_a0_hr_a0, iwl_ax201_name), + +/* so-f with hr */ + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_sof, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_no_160, iwl_cfg_any, iwl_cfg_no_cdb, + iwl_cfg_so_a0_hr_a0, iwl_ax203_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_sof, iwl_cfg_any, + iwl_cfg_rf_type_hr1, iwl_cfg_any, + iwl_cfg_160, iwl_cfg_any, iwl_cfg_no_cdb, + iwl_cfg_so_a0_hr_a0, iwl_ax101_name), + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_sof, iwl_cfg_any, + iwl_cfg_rf_type_hr2, iwl_cfg_any, + iwl_cfg_160, iwl_cfg_any, iwl_cfg_no_cdb, + iwl_cfg_so_a0_hr_a0, iwl_ax201_name), + +/* so-f with gf */ + _iwl_dev_info(iwl_cfg_any, iwl_cfg_any, + iwl_cfg_mac_type_sof, iwl_cfg_any, + iwl_cfg_rf_type_gf, iwl_cfg_any, + iwl_cfg_160, iwl_cfg_any, iwl_cfg_no_cdb, + iwlax211_2ax_cfg_so_gf_a0, iwl_ax211_name),
|
Networking
|
08f4b0b1c07bcb70247931d81233fb9c59f50c35
|
luca coelho
|
drivers
|
net
|
intel, iwlwifi, pcie, wireless
|
iwlwifi: pnvm: implement reading pnvm from uefi
|
we now support fetching the pnvm data from a uefi variable. add the code to read this variable first and use it. if it's not available, we fall back to reading the data from the filesystem, as before.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
implement support for pnvm from bios
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['c']
| 1
| 90
| 1
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c --- a/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c +++ b/drivers/net/wireless/intel/iwlwifi/fw/pnvm.c +#include <linux/efi.h> +/* + * this is known to be broken on v4.19 and to work on v5.4. until we + * figure out why this is the case and how to make it work, simply + * disable the feature in old kernels. + */ +#if defined(config_efi) + +#define iwl_efi_var_guid efi_guid(0x92daaf2f, 0xc02b, 0x455b, \ + 0xb2, 0xec, 0xf5, 0xa3, \ + 0x59, 0x4f, 0x4a, 0xea) + +#define iwl_uefi_oem_pnvm_name l"ueficnvwlanoemsignedpnvm" + +#define iwl_hardcoded_pnvm_size 4096 + +struct pnvm_sku_package { + u8 rev; + u8 reserved1[3]; + u32 total_size; + u8 n_skus; + u8 reserved2[11]; + u8 data[]; +}; + +static int iwl_pnvm_get_from_efi(struct iwl_trans *trans, + u8 **data, size_t *len) +{ + struct efivar_entry *pnvm_efivar; + struct pnvm_sku_package *package; + unsigned long package_size; + int err; + + pnvm_efivar = kzalloc(sizeof(*pnvm_efivar), gfp_kernel); + if (!pnvm_efivar) + return -enomem; + + memcpy(&pnvm_efivar->var.variablename, iwl_uefi_oem_pnvm_name, + sizeof(iwl_uefi_oem_pnvm_name)); + pnvm_efivar->var.vendorguid = iwl_efi_var_guid; + + /* + * todo: we hardcode a maximum length here, because reading + * from the uefi is not working. to implement this properly, + * we have to call efivar_entry_size(). + */ + package_size = iwl_hardcoded_pnvm_size; + + package = kmalloc(package_size, gfp_kernel); + if (!package) { + err = -enomem; + goto out; + } + + err = efivar_entry_get(pnvm_efivar, null, &package_size, package); + if (err) { + iwl_debug_fw(trans, + "pnvm uefi variable not found %d (len %zd) ", + err, package_size); + goto out; + } + + iwl_debug_fw(trans, "read pnvm fro uefi with size %zd ", package_size); + + *data = kmemdup(package->data, *len, gfp_kernel); + if (!*data) + err = -enomem; + *len = package_size - sizeof(*package); + +out: + kfree(package); + kfree(pnvm_efivar); + + return err; +} +#else /* config_efi */ +static inline int iwl_pnvm_get_from_efi(struct iwl_trans *trans, + u8 **data, size_t *len) +{ + return -eopnotsupp; +} +#endif /* config_efi */ + - /* try to load the pnvm from the filesystem */ + /* first attempt to get the pnvm from bios */ + ret = iwl_pnvm_get_from_efi(trans, &data, &len); + if (!ret) + goto parse; + + /* if it's not available, try from the filesystem */ +parse:
|
Networking
|
a1a6a4cf49eceb3fde0f1abaaf3cb24e73fdc417
|
luca coelho
|
drivers
|
net
|
fw, intel, iwlwifi, wireless
|
iwlwifi:mvm: add support for version 2 of the lari_config_change command.
|
add support for version 2 of the lari_config_change command. this is needed to support uhb enable/disable from bios
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add support for version 2 of the lari_config_change command
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['iwlwifi ']
|
['h', 'c']
| 2
| 23
| 5
|
--- diff --git a/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h b/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h --- a/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h +++ b/drivers/net/wireless/intel/iwlwifi/fw/api/nvm-reg.h - * struct iwl_lari_config_change_cmd - change lari configuration + * struct iwl_lari_config_change_cmd_v1 - change lari configuration -struct iwl_lari_config_change_cmd { +struct iwl_lari_config_change_cmd_v1 { +/** + * struct iwl_lari_config_change_cmd_v2 - change lari configuration + * @config_bitmap: bit map of the config commands. each bit will trigger a + * different predefined fw config operation + * @oem_uhb_allow_bitmap: bitmap of uhb enabled mcc sets + */ +struct iwl_lari_config_change_cmd_v2 { + __le32 config_bitmap; + __le32 oem_uhb_allow_bitmap; +} __packed; /* lari_change_conf_cmd_s_ver_2 */ + diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c --- a/drivers/net/wireless/intel/iwlwifi/mvm/fw.c +++ b/drivers/net/wireless/intel/iwlwifi/mvm/fw.c - struct iwl_lari_config_change_cmd cmd = {}; + struct iwl_lari_config_change_cmd_v2 cmd = {}; - iwl_debug_radio(mvm, "sending lari_config_change "); + size_t cmd_size = iwl_fw_lookup_cmd_ver(mvm->fw, + regulatory_and_nvm_group, + lari_config_change, 1) == 2 ? + sizeof(struct iwl_lari_config_change_cmd_v2) : + sizeof(struct iwl_lari_config_change_cmd_v1); + iwl_debug_radio(mvm, + "sending lari_config_change, config_bitmap=0x%x ", + le32_to_cpu(cmd.config_bitmap)); - 0, sizeof(cmd), &cmd); + 0, cmd_size, &cmd);
|
Networking
|
3ce882473ec4321c8b14ea30f36bfeaa18335413
|
miri korenblit
|
drivers
|
net
|
api, fw, intel, iwlwifi, mvm, wireless
|
lan743x: boost performance on cpu archs w/o dma cache snooping
|
the buffers in the lan743x driver's receive ring are always 9k, even when the largest packet that can be received (the mtu) is much smaller. this performs particularly badly on cpu archs without dma cache snooping (such as arm): each received packet results in a 9k dma_{map|unmap} operation, which is very expensive because cpu caches need to be invalidated.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
lan743x speed boost
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['lan743x']
|
['h', 'c']
| 2
| 148
| 181
|
--- diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c --- a/drivers/net/ethernet/microchip/lan743x_main.c +++ b/drivers/net/ethernet/microchip/lan743x_main.c -static struct sk_buff *lan743x_rx_allocate_skb(struct lan743x_rx *rx) -{ - int length = 0; - - length = (lan743x_max_frame_size + eth_hlen + 4 + rx_head_padding); - return __netdev_alloc_skb(rx->adapter->netdev, - length, gfp_atomic | gfp_dma); -} - -static int lan743x_rx_init_ring_element(struct lan743x_rx *rx, int index, - struct sk_buff *skb) +static int lan743x_rx_init_ring_element(struct lan743x_rx *rx, int index) + struct net_device *netdev = rx->adapter->netdev; + struct device *dev = &rx->adapter->pdev->dev; - int length = 0; + struct sk_buff *skb; + dma_addr_t dma_ptr; + int length; + + length = netdev->mtu + eth_hlen + 4 + rx_head_padding; - length = (lan743x_max_frame_size + eth_hlen + 4 + rx_head_padding); - buffer_info->skb = skb; - if (!(buffer_info->skb)) + skb = __netdev_alloc_skb(netdev, length, gfp_atomic | gfp_dma); + if (!skb) - buffer_info->dma_ptr = dma_map_single(&rx->adapter->pdev->dev, - buffer_info->skb->data, - length, - dma_from_device); - if (dma_mapping_error(&rx->adapter->pdev->dev, - buffer_info->dma_ptr)) { - buffer_info->dma_ptr = 0; + dma_ptr = dma_map_single(dev, skb->data, length, dma_from_device); + if (dma_mapping_error(dev, dma_ptr)) { + dev_kfree_skb_any(skb); + if (buffer_info->dma_ptr) + dma_unmap_single(dev, buffer_info->dma_ptr, + buffer_info->buffer_length, dma_from_device); + buffer_info->skb = skb; + buffer_info->dma_ptr = dma_ptr; - skb_reserve(buffer_info->skb, rx_head_padding); -static int lan743x_rx_process_packet(struct lan743x_rx *rx) +static struct sk_buff * +lan743x_rx_trim_skb(struct sk_buff *skb, int frame_length) +{ + if (skb_linearize(skb)) { + dev_kfree_skb_irq(skb); + return null; + } + frame_length = max_t(int, 0, frame_length - rx_head_padding - 2); + if (skb->len > frame_length) { + skb->tail -= skb->len - frame_length; + skb->len = frame_length; + } + return skb; +} + +static int lan743x_rx_process_buffer(struct lan743x_rx *rx) - struct skb_shared_hwtstamps *hwtstamps = null; - int result = rx_process_result_nothing_to_do; + struct lan743x_rx_descriptor *descriptor, *desc_ext; + struct net_device *netdev = rx->adapter->netdev; + int result = rx_process_result_nothing_to_do; - struct lan743x_rx_descriptor *descriptor; + int frame_length, buffer_length; - int first_index = -1; - int last_index = -1; + bool is_last, is_first; + struct sk_buff *skb; - if (rx->last_head != current_head_index) { - descriptor = &rx->ring_cpu_ptr[rx->last_head]; - if (le32_to_cpu(descriptor->data0) & rx_desc_data0_own_) - goto done; + if (rx->last_head == current_head_index) + goto done; - if (!(le32_to_cpu(descriptor->data0) & rx_desc_data0_fs_)) - goto done; + descriptor = &rx->ring_cpu_ptr[rx->last_head]; + if (le32_to_cpu(descriptor->data0) & rx_desc_data0_own_) + goto done; + buffer_info = &rx->buffer_info[rx->last_head]; - first_index = rx->last_head; - if (le32_to_cpu(descriptor->data0) & rx_desc_data0_ls_) { - last_index = rx->last_head; - } else { - int index; - - index = lan743x_rx_next_index(rx, first_index); - while (index != current_head_index) { - descriptor = &rx->ring_cpu_ptr[index]; - if (le32_to_cpu(descriptor->data0) & rx_desc_data0_own_) - goto done; - - if (le32_to_cpu(descriptor->data0) & rx_desc_data0_ls_) { - last_index = index; - break; - } - index = lan743x_rx_next_index(rx, index); - } - } - if (last_index >= 0) { - descriptor = &rx->ring_cpu_ptr[last_index]; - if (le32_to_cpu(descriptor->data0) & rx_desc_data0_ext_) { - /* extension is expected to follow */ - int index = lan743x_rx_next_index(rx, - last_index); - if (index != current_head_index) { - descriptor = &rx->ring_cpu_ptr[index]; - if (le32_to_cpu(descriptor->data0) & - rx_desc_data0_own_) { - goto done; - } - if (le32_to_cpu(descriptor->data0) & - rx_desc_data0_ext_) { - extension_index = index; - } else { - goto done; - } - } else { - /* extension is not yet available */ - /* prevent processing of this packet */ - first_index = -1; - last_index = -1; - } - } - } - } - if (first_index >= 0 && last_index >= 0) { - int real_last_index = last_index; - struct sk_buff *skb = null; - u32 ts_sec = 0; - u32 ts_nsec = 0; - - /* packet is available */ - if (first_index == last_index) { - /* single buffer packet */ - struct sk_buff *new_skb = null; - int packet_length; - - new_skb = lan743x_rx_allocate_skb(rx); - if (!new_skb) { - /* failed to allocate next skb. - * memory is very low. - * drop this packet and reuse buffer. - */ - lan743x_rx_reuse_ring_element(rx, first_index); - goto process_extension; - } + is_last = le32_to_cpu(descriptor->data0) & rx_desc_data0_ls_; + is_first = le32_to_cpu(descriptor->data0) & rx_desc_data0_fs_; - buffer_info = &rx->buffer_info[first_index]; - skb = buffer_info->skb; - descriptor = &rx->ring_cpu_ptr[first_index]; - - /* unmap from dma */ - if (buffer_info->dma_ptr) { - dma_unmap_single(&rx->adapter->pdev->dev, - buffer_info->dma_ptr, - buffer_info->buffer_length, - dma_from_device); - buffer_info->dma_ptr = 0; - buffer_info->buffer_length = 0; - } - buffer_info->skb = null; - packet_length = rx_desc_data0_frame_length_get_ - (le32_to_cpu(descriptor->data0)); - skb_put(skb, packet_length - 4); - skb->protocol = eth_type_trans(skb, - rx->adapter->netdev); - lan743x_rx_init_ring_element(rx, first_index, new_skb); - } else { - int index = first_index; + if (is_last && le32_to_cpu(descriptor->data0) & rx_desc_data0_ext_) { + /* extension is expected to follow */ + int index = lan743x_rx_next_index(rx, rx->last_head); - /* multi buffer packet not supported */ - /* this should not happen since - * buffers are allocated to be at least jumbo size - */ + if (index == current_head_index) + /* extension not yet available */ + goto done; + desc_ext = &rx->ring_cpu_ptr[index]; + if (le32_to_cpu(desc_ext->data0) & rx_desc_data0_own_) + /* extension not yet available */ + goto done; + if (!(le32_to_cpu(desc_ext->data0) & rx_desc_data0_ext_)) + goto move_forward; + extension_index = index; + } - /* clean up buffers */ - if (first_index <= last_index) { - while ((index >= first_index) && - (index <= last_index)) { - lan743x_rx_reuse_ring_element(rx, - index); - index = lan743x_rx_next_index(rx, - index); - } - } else { - while ((index >= first_index) || - (index <= last_index)) { - lan743x_rx_reuse_ring_element(rx, - index); - index = lan743x_rx_next_index(rx, - index); - } - } - } + /* only the last buffer in a multi-buffer frame contains the total frame + * length. the chip occasionally sends more buffers than strictly + * required to reach the total frame length. + * handle this by adding all buffers to the skb in their entirety. + * once the real frame length is known, trim the skb. + */ + frame_length = + rx_desc_data0_frame_length_get_(le32_to_cpu(descriptor->data0)); + buffer_length = buffer_info->buffer_length; + + netdev_dbg(netdev, "%s%schunk: %d/%d", + is_first ? "first " : " ", + is_last ? "last " : " ", + frame_length, buffer_length); + + /* save existing skb, allocate new skb and map to dma */ + skb = buffer_info->skb; + if (lan743x_rx_init_ring_element(rx, rx->last_head)) { + /* failed to allocate next skb. + * memory is very low. + * drop this packet and reuse buffer. + */ + lan743x_rx_reuse_ring_element(rx, rx->last_head); + /* drop packet that was being assembled */ + dev_kfree_skb_irq(rx->skb_head); + rx->skb_head = null; + goto process_extension; + } + + /* add buffers to skb via skb->frag_list */ + if (is_first) { + skb_reserve(skb, rx_head_padding); + skb_put(skb, buffer_length - rx_head_padding); + if (rx->skb_head) + dev_kfree_skb_irq(rx->skb_head); + rx->skb_head = skb; + } else if (rx->skb_head) { + skb_put(skb, buffer_length); + if (skb_shinfo(rx->skb_head)->frag_list) + rx->skb_tail->next = skb; + else + skb_shinfo(rx->skb_head)->frag_list = skb; + rx->skb_tail = skb; + rx->skb_head->len += skb->len; + rx->skb_head->data_len += skb->len; + rx->skb_head->truesize += skb->truesize; + } else { + /* packet to assemble has already been dropped because one or + * more of its buffers could not be allocated + */ + netdev_dbg(netdev, "drop buffer intended for dropped packet"); + dev_kfree_skb_irq(skb); + } - if (extension_index >= 0) { - descriptor = &rx->ring_cpu_ptr[extension_index]; - buffer_info = &rx->buffer_info[extension_index]; - - ts_sec = le32_to_cpu(descriptor->data1); - ts_nsec = (le32_to_cpu(descriptor->data2) & - rx_desc_data2_ts_ns_mask_); - lan743x_rx_reuse_ring_element(rx, extension_index); - real_last_index = extension_index; - } + if (extension_index >= 0) { + u32 ts_sec; + u32 ts_nsec; - if (!skb) { - result = rx_process_result_packet_dropped; - goto move_forward; - } + ts_sec = le32_to_cpu(desc_ext->data1); + ts_nsec = (le32_to_cpu(desc_ext->data2) & + rx_desc_data2_ts_ns_mask_); + if (rx->skb_head) + skb_hwtstamps(rx->skb_head)->hwtstamp = + ktime_set(ts_sec, ts_nsec); + lan743x_rx_reuse_ring_element(rx, extension_index); + rx->last_head = extension_index; + netdev_dbg(netdev, "process extension"); + } - if (extension_index < 0) - goto pass_packet_to_os; - hwtstamps = skb_hwtstamps(skb); - if (hwtstamps) - hwtstamps->hwtstamp = ktime_set(ts_sec, ts_nsec); + if (is_last && rx->skb_head) + rx->skb_head = lan743x_rx_trim_skb(rx->skb_head, frame_length); -pass_packet_to_os: - /* pass packet to os */ - napi_gro_receive(&rx->napi, skb); - result = rx_process_result_packet_received; + if (is_last && rx->skb_head) { + rx->skb_head->protocol = eth_type_trans(rx->skb_head, + rx->adapter->netdev); + netdev_dbg(netdev, "sending %d byte frame to os", + rx->skb_head->len); + napi_gro_receive(&rx->napi, rx->skb_head); + rx->skb_head = null; + } - /* push tail and head forward */ - rx->last_tail = real_last_index; - rx->last_head = lan743x_rx_next_index(rx, real_last_index); - } + /* push tail and head forward */ + rx->last_tail = rx->last_head; + rx->last_head = lan743x_rx_next_index(rx, rx->last_head); + result = rx_process_result_buffer_received; - result = lan743x_rx_process_packet(rx); + result = lan743x_rx_process_buffer(rx); - if (count == weight || result == rx_process_result_packet_received) + if (count == weight || result == rx_process_result_buffer_received) - struct sk_buff *new_skb = lan743x_rx_allocate_skb(rx); - - ret = lan743x_rx_init_ring_element(rx, index, new_skb); + ret = lan743x_rx_init_ring_element(rx, index); diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h --- a/drivers/net/ethernet/microchip/lan743x_main.h +++ b/drivers/net/ethernet/microchip/lan743x_main.h + + struct sk_buff *skb_head, *skb_tail; -#define rx_process_result_packet_received (1) -#define rx_process_result_packet_dropped (2) +#define rx_process_result_buffer_received (1)
|
Networking
|
a8db76d40e4d568a9e9cc9fb8d81352b5ff530ee
|
sven van asbroeck
|
drivers
|
net
|
ethernet, microchip
|
lan743x: sync only the received area of an rx ring buffer
|
on cpu architectures w/o dma cache snooping, dma_unmap() is a is a very expensive operation, because its resulting sync needs to invalidate cpu caches.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
lan743x speed boost
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['lan743x']
|
['c']
| 1
| 26
| 9
|
--- diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c --- a/drivers/net/ethernet/microchip/lan743x_main.c +++ b/drivers/net/ethernet/microchip/lan743x_main.c + unsigned int buffer_length, used_length; - int length; - length = netdev->mtu + eth_hlen + 4 + rx_head_padding; + buffer_length = netdev->mtu + eth_hlen + 4 + rx_head_padding; - skb = __netdev_alloc_skb(netdev, length, gfp_atomic | gfp_dma); + skb = __netdev_alloc_skb(netdev, buffer_length, gfp_atomic | gfp_dma); - dma_ptr = dma_map_single(dev, skb->data, length, dma_from_device); + dma_ptr = dma_map_single(dev, skb->data, buffer_length, dma_from_device); - if (buffer_info->dma_ptr) - dma_unmap_single(dev, buffer_info->dma_ptr, - buffer_info->buffer_length, dma_from_device); + if (buffer_info->dma_ptr) { + /* sync used area of buffer only */ + if (le32_to_cpu(descriptor->data0) & rx_desc_data0_ls_) + /* frame length is valid only if ls bit is set. + * it's a safe upper bound for the used area in this + * buffer. + */ + used_length = min(rx_desc_data0_frame_length_get_ + (le32_to_cpu(descriptor->data0)), + buffer_info->buffer_length); + else + used_length = buffer_info->buffer_length; + dma_sync_single_for_cpu(dev, buffer_info->dma_ptr, + used_length, + dma_from_device); + dma_unmap_single_attrs(dev, buffer_info->dma_ptr, + buffer_info->buffer_length, + dma_from_device, + dma_attr_skip_cpu_sync); + } - buffer_info->buffer_length = length; + buffer_info->buffer_length = buffer_length; - (length & rx_desc_data0_buf_length_mask_))); + (buffer_length & rx_desc_data0_buf_length_mask_)));
|
Networking
|
966df6ded24d537834402a421d46ef31b3647a78
|
sven van asbroeck
|
drivers
|
net
|
ethernet, microchip
|
mac80211_hwsim: add 6ghz channels
|
advertise 6ghz channels to mac80211.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add 6ghz channels
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mac80211_hwsim']
|
['c']
| 1
| 73
| 1
|
--- diff --git a/drivers/net/wireless/mac80211_hwsim.c b/drivers/net/wireless/mac80211_hwsim.c --- a/drivers/net/wireless/mac80211_hwsim.c +++ b/drivers/net/wireless/mac80211_hwsim.c +#define chan6g(_freq) { \ + .band = nl80211_band_6ghz, \ + .center_freq = (_freq), \ + .hw_value = (_freq), \ +} + +static const struct ieee80211_channel hwsim_channels_6ghz[] = { + chan6g(5955), /* channel 1 */ + chan6g(5975), /* channel 5 */ + chan6g(5995), /* channel 9 */ + chan6g(6015), /* channel 13 */ + chan6g(6035), /* channel 17 */ + chan6g(6055), /* channel 21 */ + chan6g(6075), /* channel 25 */ + chan6g(6095), /* channel 29 */ + chan6g(6115), /* channel 33 */ + chan6g(6135), /* channel 37 */ + chan6g(6155), /* channel 41 */ + chan6g(6175), /* channel 45 */ + chan6g(6195), /* channel 49 */ + chan6g(6215), /* channel 53 */ + chan6g(6235), /* channel 57 */ + chan6g(6255), /* channel 61 */ + chan6g(6275), /* channel 65 */ + chan6g(6295), /* channel 69 */ + chan6g(6315), /* channel 73 */ + chan6g(6335), /* channel 77 */ + chan6g(6355), /* channel 81 */ + chan6g(6375), /* channel 85 */ + chan6g(6395), /* channel 89 */ + chan6g(6415), /* channel 93 */ + chan6g(6435), /* channel 97 */ + chan6g(6455), /* channel 181 */ + chan6g(6475), /* channel 105 */ + chan6g(6495), /* channel 109 */ + chan6g(6515), /* channel 113 */ + chan6g(6535), /* channel 117 */ + chan6g(6555), /* channel 121 */ + chan6g(6575), /* channel 125 */ + chan6g(6595), /* channel 129 */ + chan6g(6615), /* channel 133 */ + chan6g(6635), /* channel 137 */ + chan6g(6655), /* channel 141 */ + chan6g(6675), /* channel 145 */ + chan6g(6695), /* channel 149 */ + chan6g(6715), /* channel 153 */ + chan6g(6735), /* channel 157 */ + chan6g(6755), /* channel 161 */ + chan6g(6775), /* channel 165 */ + chan6g(6795), /* channel 169 */ + chan6g(6815), /* channel 173 */ + chan6g(6835), /* channel 177 */ + chan6g(6855), /* channel 181 */ + chan6g(6875), /* channel 185 */ + chan6g(6895), /* channel 189 */ + chan6g(6915), /* channel 193 */ + chan6g(6935), /* channel 197 */ + chan6g(6955), /* channel 201 */ + chan6g(6975), /* channel 205 */ + chan6g(6995), /* channel 209 */ + chan6g(7015), /* channel 213 */ + chan6g(7035), /* channel 217 */ + chan6g(7055), /* channel 221 */ + chan6g(7075), /* channel 225 */ + chan6g(7095), /* channel 229 */ + chan6g(7115), /* channel 233 */ +}; + + struct ieee80211_channel channels_6ghz[array_size(hwsim_channels_6ghz)]; - array_size(hwsim_channels_5ghz)]; + array_size(hwsim_channels_5ghz) + + array_size(hwsim_channels_6ghz)]; + memcpy(data->channels_6ghz, hwsim_channels_6ghz, + sizeof(hwsim_channels_6ghz));
|
Networking
|
28881922abd786a1e62a4ca77394a84373dd5279
|
ramon fontes
|
drivers
|
net
|
wireless
|
net: mhi: add protocol support
|
mhi can transport different protocols, some are handled at upper level, like ip and qmap(rmnet/netlink), but others will need to be inside mhi net driver, like mbim. this change adds support for protocol rx and tx_fixup callbacks registration, that can be used to encode/decode the targeted protocol.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mbim over mhi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mhi']
|
['c']
| 1
| 57
| 12
|
--- diff --git a/drivers/net/mhi_net.c b/drivers/net/mhi_net.c --- a/drivers/net/mhi_net.c +++ b/drivers/net/mhi_net.c + const struct mhi_net_proto *proto; + void *proto_data; +struct mhi_net_proto { + int (*init)(struct mhi_net_dev *mhi_netdev); + struct sk_buff * (*tx_fixup)(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb); + void (*rx)(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb); +}; + +struct mhi_device_info { + const char *netname; + const struct mhi_net_proto *proto; +}; + + const struct mhi_net_proto *proto = mhi_netdev->proto; + if (proto && proto->tx_fixup) { + skb = proto->tx_fixup(mhi_netdev, skb); + if (unlikely(!skb)) + goto exit_drop; + } + - - u64_stats_update_begin(&mhi_netdev->stats.tx_syncp); - u64_stats_inc(&mhi_netdev->stats.tx_dropped); - u64_stats_update_end(&mhi_netdev->stats.tx_syncp); - - /* drop the packet */ + goto exit_drop; + +exit_drop: + u64_stats_update_begin(&mhi_netdev->stats.tx_syncp); + u64_stats_inc(&mhi_netdev->stats.tx_dropped); + u64_stats_update_end(&mhi_netdev->stats.tx_syncp); + + return netdev_tx_ok; + const struct mhi_net_proto *proto = mhi_netdev->proto; - netif_rx(skb); + if (proto && proto->rx) + proto->rx(mhi_netdev, skb); + else + netif_rx(skb); - const char *netname = (char *)id->driver_data; + const struct mhi_device_info *info = (struct mhi_device_info *)id->driver_data; - ndev = alloc_netdev(sizeof(*mhi_netdev), netname, net_name_predictable, - mhi_net_setup); + ndev = alloc_netdev(sizeof(*mhi_netdev), info->netname, + net_name_predictable, mhi_net_setup); + mhi_netdev->proto = info->proto; + if (mhi_netdev->proto) { + err = mhi_netdev->proto->init(mhi_netdev); + if (err) + goto out_err_proto; + } + +out_err_proto: + unregister_netdev(ndev); +static const struct mhi_device_info mhi_hwip0 = { + .netname = "mhi_hwip%d", +}; + +static const struct mhi_device_info mhi_swip0 = { + .netname = "mhi_swip%d", +}; + - { .chan = "ip_hw0", .driver_data = (kernel_ulong_t)"mhi_hwip%d" }, - { .chan = "ip_sw0", .driver_data = (kernel_ulong_t)"mhi_swip%d" }, + /* hardware accelerated data path (to modem ipa), protocol agnostic */ + { .chan = "ip_hw0", .driver_data = (kernel_ulong_t)&mhi_hwip0 }, + /* software data path (to modem cpu) */ + { .chan = "ip_sw0", .driver_data = (kernel_ulong_t)&mhi_swip0 },
|
Networking
|
ddeb9bfa59c711ccbddec1c9fb9ec190caab1a4c
|
loic poulain
|
drivers
|
net
| |
net: mhi: add dedicated folder
|
create a dedicated mhi directory for mhi-net, mhi-net is going to be split into differente files (for additional protocol support).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mbim over mhi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mhi']
|
['c', 'makefile']
| 3
| 4
| 1
|
--- diff --git a/drivers/net/makefile b/drivers/net/makefile --- a/drivers/net/makefile +++ b/drivers/net/makefile -obj-$(config_mhi_net) += mhi_net.o +obj-$(config_mhi_net) += mhi/ diff --git a/drivers/net/mhi/makefile b/drivers/net/mhi/makefile --- /dev/null +++ b/drivers/net/mhi/makefile +obj-$(config_mhi_net) += mhi_net.o + +mhi_net-y := net.o diff --git a/drivers/net/mhi_net.c b/drivers/net/mhi/net.c
|
Networking
|
b6ec6b8942700e855aa1a42e04ca9e1f89162de0
|
loic poulain
|
drivers
|
net
|
mhi
|
net: mhi: create mhi.h
|
move mhi-net shared structures to mhi header, that will be used by upcoming proto(s).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mbim over mhi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mhi']
|
['h', 'c']
| 2
| 38
| 31
|
--- diff --git a/drivers/net/mhi/mhi.h b/drivers/net/mhi/mhi.h --- /dev/null +++ b/drivers/net/mhi/mhi.h +/* spdx-license-identifier: gpl-2.0-or-later */ +/* mhi network driver - network over mhi bus + * + * copyright (c) 2021 linaro ltd <loic.poulain@linaro.org> + */ + +struct mhi_net_stats { + u64_stats_t rx_packets; + u64_stats_t rx_bytes; + u64_stats_t rx_errors; + u64_stats_t rx_dropped; + u64_stats_t tx_packets; + u64_stats_t tx_bytes; + u64_stats_t tx_errors; + u64_stats_t tx_dropped; + struct u64_stats_sync tx_syncp; + struct u64_stats_sync rx_syncp; +}; + +struct mhi_net_dev { + struct mhi_device *mdev; + struct net_device *ndev; + struct sk_buff *skbagg_head; + struct sk_buff *skbagg_tail; + const struct mhi_net_proto *proto; + void *proto_data; + struct delayed_work rx_refill; + struct mhi_net_stats stats; + u32 rx_queue_sz; +}; + +struct mhi_net_proto { + int (*init)(struct mhi_net_dev *mhi_netdev); + struct sk_buff * (*tx_fixup)(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb); + void (*rx)(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb); +}; diff --git a/drivers/net/mhi/net.c b/drivers/net/mhi/net.c --- a/drivers/net/mhi/net.c +++ b/drivers/net/mhi/net.c +#include "mhi.h" + -struct mhi_net_stats { - u64_stats_t rx_packets; - u64_stats_t rx_bytes; - u64_stats_t rx_errors; - u64_stats_t rx_dropped; - u64_stats_t tx_packets; - u64_stats_t tx_bytes; - u64_stats_t tx_errors; - u64_stats_t tx_dropped; - struct u64_stats_sync tx_syncp; - struct u64_stats_sync rx_syncp; -}; - -struct mhi_net_dev { - struct mhi_device *mdev; - struct net_device *ndev; - struct sk_buff *skbagg_head; - struct sk_buff *skbagg_tail; - const struct mhi_net_proto *proto; - void *proto_data; - struct delayed_work rx_refill; - struct mhi_net_stats stats; - u32 rx_queue_sz; -}; - -struct mhi_net_proto { - int (*init)(struct mhi_net_dev *mhi_netdev); - struct sk_buff * (*tx_fixup)(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb); - void (*rx)(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb); -}; -
|
Networking
|
77e8080e12721c9206aa592aa34985c897ee1a32
|
loic poulain
|
drivers
|
net
|
mhi
|
net: mhi: add rx_length_errors stat
|
this can be used by proto when packet len is incorrect.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mbim over mhi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mhi']
|
['h', 'c']
| 2
| 2
| 0
|
--- diff --git a/drivers/net/mhi/mhi.h b/drivers/net/mhi/mhi.h --- a/drivers/net/mhi/mhi.h +++ b/drivers/net/mhi/mhi.h + u64_stats_t rx_length_errors; diff --git a/drivers/net/mhi/net.c b/drivers/net/mhi/net.c --- a/drivers/net/mhi/net.c +++ b/drivers/net/mhi/net.c + stats->rx_length_errors = u64_stats_read(&mhi_netdev->stats.rx_length_errors);
|
Networking
|
84c55f16dcd74af5be525aa9c1878bfaec4e8a7a
|
loic poulain
|
drivers
|
net
|
mhi
|
net: mhi: add mbim proto
|
mbim has initially been specified by usb-if for transporting data (ip) between a modem and a host over usb. however some modern modems also support mbim over pcie (via mhi). in the same way as qmap(rmnet), it allows to aggregate ip packets and to perform context multiplexing.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mbim over mhi support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mhi']
|
['h', 'c', 'makefile']
| 4
| 304
| 1
|
--- diff --git a/drivers/net/mhi/makefile b/drivers/net/mhi/makefile --- a/drivers/net/mhi/makefile +++ b/drivers/net/mhi/makefile -mhi_net-y := net.o +mhi_net-y := net.o proto_mbim.o diff --git a/drivers/net/mhi/mhi.h b/drivers/net/mhi/mhi.h --- a/drivers/net/mhi/mhi.h +++ b/drivers/net/mhi/mhi.h + int msg_enable; + +extern const struct mhi_net_proto proto_mbim; diff --git a/drivers/net/mhi/net.c b/drivers/net/mhi/net.c --- a/drivers/net/mhi/net.c +++ b/drivers/net/mhi/net.c +static const struct mhi_device_info mhi_hwip0_mbim = { + .netname = "mhi_mbim%d", + .proto = &proto_mbim, +}; + + /* hardware accelerated data path (to modem ipa), mbim protocol */ + { .chan = "ip_hw0_mbim", .driver_data = (kernel_ulong_t)&mhi_hwip0_mbim }, diff --git a/drivers/net/mhi/proto_mbim.c b/drivers/net/mhi/proto_mbim.c --- /dev/null +++ b/drivers/net/mhi/proto_mbim.c +// spdx-license-identifier: gpl-2.0-or-later +/* mhi network driver - network over mhi bus + * + * copyright (c) 2021 linaro ltd <loic.poulain@linaro.org> + * + * this driver copy some code from cdc_ncm, which is: + * copyright (c) st-ericsson 2010-2012 + * and cdc_mbim, which is: + * copyright (c) 2012 smith micro software, inc. + * copyright (c) 2012 bjrn mork <bjorn@mork.no> + * + */ + +#include <linux/ethtool.h> +#include <linux/if_vlan.h> +#include <linux/ip.h> +#include <linux/mii.h> +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/usb.h> +#include <linux/usb/cdc.h> +#include <linux/usb/usbnet.h> +#include <linux/usb/cdc_ncm.h> + +#include "mhi.h" + +#define mbim_ndp16_sign_mask 0x00ffffff + +struct mbim_context { + u16 rx_seq; + u16 tx_seq; +}; + +static void __mbim_length_errors_inc(struct mhi_net_dev *dev) +{ + u64_stats_update_begin(&dev->stats.rx_syncp); + u64_stats_inc(&dev->stats.rx_length_errors); + u64_stats_update_end(&dev->stats.rx_syncp); +} + +static void __mbim_errors_inc(struct mhi_net_dev *dev) +{ + u64_stats_update_begin(&dev->stats.rx_syncp); + u64_stats_inc(&dev->stats.rx_errors); + u64_stats_update_end(&dev->stats.rx_syncp); +} + +static int mbim_rx_verify_nth16(struct sk_buff *skb) +{ + struct mhi_net_dev *dev = netdev_priv(skb->dev); + struct mbim_context *ctx = dev->proto_data; + struct usb_cdc_ncm_nth16 *nth16; + int len; + + if (skb->len < sizeof(struct usb_cdc_ncm_nth16) + + sizeof(struct usb_cdc_ncm_ndp16)) { + netif_dbg(dev, rx_err, dev->ndev, "frame too short "); + __mbim_length_errors_inc(dev); + return -einval; + } + + nth16 = (struct usb_cdc_ncm_nth16 *)skb->data; + + if (nth16->dwsignature != cpu_to_le32(usb_cdc_ncm_nth16_sign)) { + netif_dbg(dev, rx_err, dev->ndev, + "invalid nth16 signature <%#010x> ", + le32_to_cpu(nth16->dwsignature)); + __mbim_errors_inc(dev); + return -einval; + } + + /* no limit on the block length, except the size of the data pkt */ + len = le16_to_cpu(nth16->wblocklength); + if (len > skb->len) { + netif_dbg(dev, rx_err, dev->ndev, + "ntb does not fit into the skb %u/%u ", len, + skb->len); + __mbim_length_errors_inc(dev); + return -einval; + } + + if (ctx->rx_seq + 1 != le16_to_cpu(nth16->wsequence) && + (ctx->rx_seq || le16_to_cpu(nth16->wsequence)) && + !(ctx->rx_seq == 0xffff && !le16_to_cpu(nth16->wsequence))) { + netif_dbg(dev, rx_err, dev->ndev, + "sequence number glitch prev=%d curr=%d ", + ctx->rx_seq, le16_to_cpu(nth16->wsequence)); + } + ctx->rx_seq = le16_to_cpu(nth16->wsequence); + + return le16_to_cpu(nth16->wndpindex); +} + +static int mbim_rx_verify_ndp16(struct sk_buff *skb, int ndpoffset) +{ + struct mhi_net_dev *dev = netdev_priv(skb->dev); + struct usb_cdc_ncm_ndp16 *ndp16; + int ret; + + if (ndpoffset + sizeof(struct usb_cdc_ncm_ndp16) > skb->len) { + netif_dbg(dev, rx_err, dev->ndev, "invalid ndp offset <%u> ", + ndpoffset); + return -einval; + } + + ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb->data + ndpoffset); + + if (le16_to_cpu(ndp16->wlength) < usb_cdc_ncm_ndp16_length_min) { + netif_dbg(dev, rx_err, dev->ndev, "invalid dpt16 length <%u> ", + le16_to_cpu(ndp16->wlength)); + return -einval; + } + + ret = ((le16_to_cpu(ndp16->wlength) - sizeof(struct usb_cdc_ncm_ndp16)) + / sizeof(struct usb_cdc_ncm_dpe16)); + ret--; /* last entry is always a null terminator */ + + if (sizeof(struct usb_cdc_ncm_ndp16) + + ret * sizeof(struct usb_cdc_ncm_dpe16) > skb->len) { + netif_dbg(dev, rx_err, dev->ndev, + "invalid nframes = %d ", ret); + return -einval; + } + + return ret; +} + +static void mbim_rx(struct mhi_net_dev *mhi_netdev, struct sk_buff *skb) +{ + struct net_device *ndev = mhi_netdev->ndev; + int ndpoffset; + + if (skb_linearize(skb)) + goto error; + + /* check ntb header and retrieve first ndp offset */ + ndpoffset = mbim_rx_verify_nth16(skb); + if (ndpoffset < 0) { + net_err_ratelimited("%s: incorrect ntb header ", ndev->name); + goto error; + } + + /* process each ndp */ + while (1) { + struct usb_cdc_ncm_ndp16 *ndp16; + struct usb_cdc_ncm_dpe16 *dpe16; + int nframes, n; + + /* check ndp header and retrieve number of datagrams */ + nframes = mbim_rx_verify_ndp16(skb, ndpoffset); + if (nframes < 0) { + net_err_ratelimited("%s: incorrect ndp16 ", ndev->name); + __mbim_length_errors_inc(mhi_netdev); + goto error; + } + + /* only ip data type supported, no dss in mhi context */ + ndp16 = (struct usb_cdc_ncm_ndp16 *)(skb->data + ndpoffset); + if ((ndp16->dwsignature & cpu_to_le32(mbim_ndp16_sign_mask)) + != cpu_to_le32(usb_cdc_mbim_ndp16_ips_sign)) { + net_err_ratelimited("%s: unsupported ndp type ", ndev->name); + __mbim_errors_inc(mhi_netdev); + goto next_ndp; + } + + /* only primary ip session 0 (0x00) supported for now */ + if (ndp16->dwsignature & ~cpu_to_le32(mbim_ndp16_sign_mask)) { + net_err_ratelimited("%s: bad packet session ", ndev->name); + __mbim_errors_inc(mhi_netdev); + goto next_ndp; + } + + /* de-aggregate and deliver ip packets */ + dpe16 = ndp16->dpe16; + for (n = 0; n < nframes; n++, dpe16++) { + u16 dgram_offset = le16_to_cpu(dpe16->wdatagramindex); + u16 dgram_len = le16_to_cpu(dpe16->wdatagramlength); + struct sk_buff *skbn; + + if (!dgram_offset || !dgram_len) + break; /* null terminator */ + + skbn = netdev_alloc_skb(ndev, dgram_len); + if (!skbn) + continue; + + skb_put(skbn, dgram_len); + memcpy(skbn->data, skb->data + dgram_offset, dgram_len); + + switch (skbn->data[0] & 0xf0) { + case 0x40: + skbn->protocol = htons(eth_p_ip); + break; + case 0x60: + skbn->protocol = htons(eth_p_ipv6); + break; + default: + net_err_ratelimited("%s: unknown protocol ", + ndev->name); + __mbim_errors_inc(mhi_netdev); + dev_kfree_skb_any(skbn); + continue; + } + + netif_rx(skbn); + } +next_ndp: + /* other ndp to process? */ + ndpoffset = (int)le16_to_cpu(ndp16->wnextndpindex); + if (!ndpoffset) + break; + } + + /* free skb */ + dev_consume_skb_any(skb); + return; +error: + dev_kfree_skb_any(skb); +} + +struct mbim_tx_hdr { + struct usb_cdc_ncm_nth16 nth16; + struct usb_cdc_ncm_ndp16 ndp16; + struct usb_cdc_ncm_dpe16 dpe16[2]; +} __packed; + +static struct sk_buff *mbim_tx_fixup(struct mhi_net_dev *mhi_netdev, + struct sk_buff *skb) +{ + struct mbim_context *ctx = mhi_netdev->proto_data; + unsigned int dgram_size = skb->len; + struct usb_cdc_ncm_nth16 *nth16; + struct usb_cdc_ncm_ndp16 *ndp16; + struct mbim_tx_hdr *mbim_hdr; + + /* for now, this is a partial implementation of cdc mbim, only one ndp + * is sent, containing the ip packet (no aggregation). + */ + + /* ensure we have enough headroom for crafting mbim header */ + if (skb_cow_head(skb, sizeof(struct mbim_tx_hdr))) { + dev_kfree_skb_any(skb); + return null; + } + + mbim_hdr = skb_push(skb, sizeof(struct mbim_tx_hdr)); + + /* fill ntb header */ + nth16 = &mbim_hdr->nth16; + nth16->dwsignature = cpu_to_le32(usb_cdc_ncm_nth16_sign); + nth16->wheaderlength = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); + nth16->wsequence = cpu_to_le16(ctx->tx_seq++); + nth16->wblocklength = cpu_to_le16(skb->len); + nth16->wndpindex = cpu_to_le16(sizeof(struct usb_cdc_ncm_nth16)); + + /* fill the unique ndp */ + ndp16 = &mbim_hdr->ndp16; + ndp16->dwsignature = cpu_to_le32(usb_cdc_mbim_ndp16_ips_sign); + ndp16->wlength = cpu_to_le16(sizeof(struct usb_cdc_ncm_ndp16) + + sizeof(struct usb_cdc_ncm_dpe16) * 2); + ndp16->wnextndpindex = 0; + + /* datagram follows the mbim header */ + ndp16->dpe16[0].wdatagramindex = cpu_to_le16(sizeof(struct mbim_tx_hdr)); + ndp16->dpe16[0].wdatagramlength = cpu_to_le16(dgram_size); + + /* null termination */ + ndp16->dpe16[1].wdatagramindex = 0; + ndp16->dpe16[1].wdatagramlength = 0; + + return skb; +} + +static int mbim_init(struct mhi_net_dev *mhi_netdev) +{ + struct net_device *ndev = mhi_netdev->ndev; + + mhi_netdev->proto_data = devm_kzalloc(&ndev->dev, + sizeof(struct mbim_context), + gfp_kernel); + if (!mhi_netdev->proto_data) + return -enomem; + + ndev->needed_headroom = sizeof(struct mbim_tx_hdr); + + return 0; +} + +const struct mhi_net_proto proto_mbim = { + .init = mbim_init, + .rx = mbim_rx, + .tx_fixup = mbim_tx_fixup, +};
|
Networking
|
163c5e6262ae5d7347801964dbd3d48490490a3d
|
loic poulain
|
drivers
|
net
|
mhi
|
net: mhi: add raw ip mode support
|
mhi net is protocol agnostic, the payload protocol depends on the modem configuration, which can be either rmnet (ip muxing and aggregation) or raw ip. this patch adds support for incomming ipv4/ipv6 packets, that was previously unconditionnaly reported as rmnet packets.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add raw ip mode support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mhi']
|
['c']
| 1
| 13
| 2
|
--- diff --git a/drivers/net/mhi_net.c b/drivers/net/mhi_net.c --- a/drivers/net/mhi_net.c +++ b/drivers/net/mhi_net.c - ndev->type = arphrd_none; /* qmap... */ + ndev->type = arphrd_rawip; - skb->protocol = htons(eth_p_map); + switch (skb->data[0] & 0xf0) { + case 0x40: + skb->protocol = htons(eth_p_ip); + break; + case 0x60: + skb->protocol = htons(eth_p_ipv6); + break; + default: + skb->protocol = htons(eth_p_map); + break; + } +
|
Networking
|
c134db89a44bdc86c7b0451095d6ba328a7c1748
|
loic poulain
|
drivers
|
net
| |
rdma/mlx5: support 400gbps ib rate in mlx5 driver
|
support 400gbps ib rate in mlx5 driver.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support 400gbps ib rate in mlx5 driver
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 2
| 0
|
--- diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c --- a/drivers/infiniband/hw/mlx5/qp.c +++ b/drivers/infiniband/hw/mlx5/qp.c + case ib_rate_400_gbps: + return 6;
|
Networking
|
c70f51de85302e76a59f6c6ce3dcd27b6411d23b
|
patrisious haddad maor gottlieb maorg nvidia com
|
drivers
|
infiniband
|
hw, mlx5
|
ib/mlx5: support default partition key for representor port
|
representor port has only one default pkey. hence have simpler query pkey callback or it.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
support default partition key for representor port
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 11
| 0
|
--- diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c +static int mlx5_ib_rep_query_pkey(struct ib_device *ibdev, u8 port, u16 index, + u16 *pkey) +{ + /* default special pkey for representor device port as per the + * ib specification 1.3 section 10.9.1.2. + */ + *pkey = 0xffff; + return 0; +} + + .query_pkey = mlx5_ib_rep_query_pkey,
|
Networking
|
d6fd59e14ed2975d9b372876c45a09d76d1e70c9
|
parav pandit
|
drivers
|
infiniband
|
hw, mlx5
|
net/mlx5: add new timestamp mode bits
|
these fields declare which timestamp mode is supported by the device per rq/sq/qp.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mlx5 real time clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h']
| 1
| 49
| 5
|
--- diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h +enum { + mlx5_qp_timestamp_format_cap_free_running = 0x0, + mlx5_qp_timestamp_format_cap_real_time = 0x1, + mlx5_qp_timestamp_format_cap_free_running_and_real_time = 0x2, +}; + - u8 reserved_at_5[0x1b]; + u8 reserved_at_5[0x19]; + u8 qp_ts_format[0x2]; +enum { + mlx5_sq_timestamp_format_cap_free_running = 0x0, + mlx5_sq_timestamp_format_cap_real_time = 0x1, + mlx5_sq_timestamp_format_cap_free_running_and_real_time = 0x2, +}; + +enum { + mlx5_rq_timestamp_format_cap_free_running = 0x0, + mlx5_rq_timestamp_format_cap_real_time = 0x1, + mlx5_rq_timestamp_format_cap_free_running_and_real_time = 0x2, +}; + - u8 reserved_at_440[0x4]; + u8 sq_ts_format[0x2]; + u8 rq_ts_format[0x2]; +enum { + mlx5_qpc_timestamp_format_free_running = 0x0, + mlx5_qpc_timestamp_format_default = 0x1, + mlx5_qpc_timestamp_format_real_time = 0x2, +}; + - u8 reserved_at_55[0x6]; + u8 reserved_at_55[0x3]; + u8 ts_format[0x2]; + u8 reserved_at_5a[0x1]; +enum { + mlx5_sqc_timestamp_format_free_running = 0x0, + mlx5_sqc_timestamp_format_default = 0x1, + mlx5_sqc_timestamp_format_real_time = 0x2, +}; + - u8 reserved_at_f[0x11]; + u8 reserved_at_f[0xb]; + u8 ts_format[0x2]; + u8 reserved_at_1c[0x4]; +enum { + mlx5_rqc_timestamp_format_free_running = 0x0, + mlx5_rqc_timestamp_format_default = 0x1, + mlx5_rqc_timestamp_format_real_time = 0x2, +}; + - u8 reserved_at_f[0x11]; + u8 reserved_at_f[0xb]; + u8 ts_format[0x2]; + u8 reserved_at_1c[0x4];
|
Networking
|
a6a217dddcd544f6b75f0e2a60b6e84c1d494b7e
|
aharon landau
|
include
|
linux
|
mlx5
|
net/mlx5: add register layout to support real-time time-stamp
|
add needed structure layouts and defines for mtutc (management utc) register. mtutc will be used for cyc2time hw translation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mlx5 real time clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h']
| 3
| 33
| 3
|
--- diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h --- a/include/linux/mlx5/device.h +++ b/include/linux/mlx5/device.h - __be32 rsvd4[1019]; + __be32 rsvd4[11]; + __be32 real_time_h; + __be32 real_time_l; + __be32 rsvd5[1006]; diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h + mlx5_reg_mtutc = 0x9055, diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h --- a/include/linux/mlx5/mlx5_ifc.h +++ b/include/linux/mlx5/mlx5_ifc.h +enum { + mlx5_mtutc_operation_set_time_immediate = 0x1, + mlx5_mtutc_operation_adjust_time = 0x2, + mlx5_mtutc_operation_adjust_freq_utc = 0x3, +}; + +struct mlx5_ifc_mtutc_reg_bits { + u8 reserved_at_0[0x1c]; + u8 operation[0x4]; + + u8 freq_adjustment[0x20]; + + u8 reserved_at_40[0x40]; + + u8 utc_sec[0x20]; + + u8 reserved_at_a0[0x2]; + u8 utc_nsec[0x1e]; + + u8 time_adjustment[0x20]; +}; + - u8 reserved_at_0[0x6e]; + u8 reserved_at_0[0x6b]; + u8 ptpcyc2realtime_modify[0x1]; + u8 reserved_at_6c[0x2]; - u8 regs_85_to_68[0x12]; + u8 mtutc[0x1]; + u8 regs_84_to_68[0x11]; + struct mlx5_ifc_mtutc_reg_bits mtutc_reg;
|
Networking
|
ae02d41551d6f2a035d3e63ce4415e1b2ba3a7e6
|
eran ben elisha
|
include
|
linux
|
mlx5
|
net/mlx5: refactor init clock function
|
function mlx5_init_clock() is responsible for internal ptp related metadata initializations. break mlx5_init_clock() to sub functions, each takes care of its own logic.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mlx5 real time clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 53
| 23
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c -void mlx5_init_clock(struct mlx5_core_dev *mdev) +static void mlx5_timecounter_init(struct mlx5_core_dev *mdev) - u64 overflow_cycles; - u64 ns; - u64 frac = 0; - if (!dev_freq) { - mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting hw clock init "); - return; - } - seqlock_init(&clock->lock); +} + +static void mlx5_init_overflow_period(struct mlx5_clock *clock) +{ + struct mlx5_core_dev *mdev = container_of(clock, struct mlx5_core_dev, clock); + struct mlx5_ib_clock_info *clock_info = mdev->clock_info; + u64 overflow_cycles; + u64 frac = 0; + u64 ns; - mdev->clock_info = - (struct mlx5_ib_clock_info *)get_zeroed_page(gfp_kernel); - if (mdev->clock_info) { - mdev->clock_info->nsec = clock->tc.nsec; - mdev->clock_info->cycles = clock->tc.cycle_last; - mdev->clock_info->mask = clock->cycles.mask; - mdev->clock_info->mult = clock->nominal_c_mult; - mdev->clock_info->shift = clock->cycles.shift; - mdev->clock_info->frac = clock->tc.frac; - mdev->clock_info->overflow_period = clock->overflow_period; - } - - init_work(&clock->pps_info.out_work, mlx5_pps_out); - mlx5_core_warn(mdev, "invalid overflow period, overflow_work is not scheduled "); + mlx5_core_warn(mdev, + "invalid overflow period, overflow_work is not scheduled "); + + if (clock_info) + clock_info->overflow_period = clock->overflow_period; +} + +static void mlx5_init_clock_info(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = &mdev->clock; + struct mlx5_ib_clock_info *info; + + mdev->clock_info = (struct mlx5_ib_clock_info *)get_zeroed_page(gfp_kernel); + if (!mdev->clock_info) { + mlx5_core_warn(mdev, "failed to allocate ib clock info page "); + return; + } + + info = mdev->clock_info; + + info->nsec = clock->tc.nsec; + info->cycles = clock->tc.cycle_last; + info->mask = clock->cycles.mask; + info->mult = clock->nominal_c_mult; + info->shift = clock->cycles.shift; + info->frac = clock->tc.frac; +} + +void mlx5_init_clock(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = &mdev->clock; + + if (!mlx5_cap_gen(mdev, device_frequency_khz)) { + mlx5_core_warn(mdev, "invalid device_frequency_khz, aborting hw clock init "); + return; + } + + seqlock_init(&clock->lock); + + mlx5_timecounter_init(mdev); + mlx5_init_clock_info(mdev); + mlx5_init_overflow_period(clock); + init_work(&clock->pps_info.out_work, mlx5_pps_out);
|
Networking
|
1436de0b991548fd859a00c889b8c4dcbbb5f463
|
eran ben elisha moshe shemesh moshe mellanox com
|
drivers
|
net
|
core, ethernet, lib, mellanox, mlx5
|
net/mlx5: move all internal timer metadata into a dedicated struct
|
internal timer mode (sw clock) requires some ptp clock related metadata structs. real time mode (hw clock) will not need these metadata structs. this separation emphasize the different interfaces for hw clock and sw clock.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mlx5 real time clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 3
| 71
| 51
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c - struct mlx5_clock *clock = container_of(cc, struct mlx5_clock, cycles); + struct mlx5_timer *timer = container_of(cc, struct mlx5_timer, cycles); + struct mlx5_clock *clock = container_of(timer, struct mlx5_clock, timer); + struct mlx5_timer *timer; - clock_info->cycles = clock->tc.cycle_last; - clock_info->mult = clock->cycles.mult; - clock_info->nsec = clock->tc.nsec; - clock_info->frac = clock->tc.frac; + timer = &clock->timer; + clock_info->cycles = timer->tc.cycle_last; + clock_info->mult = timer->cycles.mult; + clock_info->nsec = timer->tc.nsec; + clock_info->frac = timer->tc.frac; + struct mlx5_timer *timer; - clock = container_of(dwork, struct mlx5_clock, overflow_work); + timer = container_of(dwork, struct mlx5_timer, overflow_work); + clock = container_of(timer, struct mlx5_clock, timer); + - timecounter_read(&clock->tc); + timecounter_read(&timer->tc); - schedule_delayed_work(&clock->overflow_work, clock->overflow_period); + schedule_delayed_work(&timer->overflow_work, timer->overflow_period); + struct mlx5_timer *timer = &clock->timer; - timecounter_init(&clock->tc, &clock->cycles, ns); + timecounter_init(&timer->tc, &timer->cycles, ns); + struct mlx5_timer *timer = &clock->timer; - ns = timecounter_cyc2time(&clock->tc, cycles); + ns = timecounter_cyc2time(&timer->tc, cycles); + struct mlx5_timer *timer = &clock->timer; - timecounter_adjtime(&clock->tc, delta); + timecounter_adjtime(&timer->tc, delta); + struct mlx5_timer *timer = &clock->timer; - - adj = clock->nominal_c_mult; + adj = timer->nominal_c_mult; - timecounter_read(&clock->tc); - clock->cycles.mult = neg_adj ? clock->nominal_c_mult - diff : - clock->nominal_c_mult + diff; + timecounter_read(&timer->tc); + timer->cycles.mult = neg_adj ? timer->nominal_c_mult - diff : + timer->nominal_c_mult + diff; + struct mlx5_timer *timer = &clock->timer; - nsec_now = timecounter_cyc2time(&clock->tc, cycles_now); + nsec_now = timecounter_cyc2time(&timer->tc, cycles_now); - cycles_delta = div64_u64(nsec_delta << clock->cycles.shift, - clock->cycles.mult); + cycles_delta = div64_u64(nsec_delta << timer->cycles.shift, + timer->cycles.mult); + struct mlx5_timer *timer = &clock->timer; - nsec_now = timecounter_cyc2time(&clock->tc, cycles_now); + nsec_now = timecounter_cyc2time(&timer->tc, cycles_now); - cycles_delta = div64_u64(nsec_delta << clock->cycles.shift, - clock->cycles.mult); + cycles_delta = div64_u64(nsec_delta << timer->cycles.shift, + timer->cycles.mult); + struct mlx5_timer *timer = &clock->timer; - clock->cycles.read = read_internal_timer; - clock->cycles.shift = mlx5_cycles_shift; - clock->cycles.mult = clocksource_khz2mult(dev_freq, - clock->cycles.shift); - clock->nominal_c_mult = clock->cycles.mult; - clock->cycles.mask = clocksource_mask(41); - - timecounter_init(&clock->tc, &clock->cycles, + timer->cycles.read = read_internal_timer; + timer->cycles.shift = mlx5_cycles_shift; + timer->cycles.mult = clocksource_khz2mult(dev_freq, + timer->cycles.shift); + timer->nominal_c_mult = timer->cycles.mult; + timer->cycles.mask = clocksource_mask(41); + + timecounter_init(&timer->tc, &timer->cycles, + struct mlx5_timer *timer = &clock->timer; - overflow_cycles = div64_u64(~0ull >> 1, clock->cycles.mult); - overflow_cycles = min(overflow_cycles, div_u64(clock->cycles.mask, 3)); + overflow_cycles = div64_u64(~0ull >> 1, timer->cycles.mult); + overflow_cycles = min(overflow_cycles, div_u64(timer->cycles.mask, 3)); - ns = cyclecounter_cyc2ns(&clock->cycles, overflow_cycles, + ns = cyclecounter_cyc2ns(&timer->cycles, overflow_cycles, - clock->overflow_period = ns; + timer->overflow_period = ns; - init_delayed_work(&clock->overflow_work, mlx5_timestamp_overflow); - if (clock->overflow_period) - schedule_delayed_work(&clock->overflow_work, 0); + init_delayed_work(&timer->overflow_work, mlx5_timestamp_overflow); + if (timer->overflow_period) + schedule_delayed_work(&timer->overflow_work, 0); - clock_info->overflow_period = clock->overflow_period; + clock_info->overflow_period = timer->overflow_period; + struct mlx5_timer *timer; - - info->nsec = clock->tc.nsec; - info->cycles = clock->tc.cycle_last; - info->mask = clock->cycles.mask; - info->mult = clock->nominal_c_mult; - info->shift = clock->cycles.shift; - info->frac = clock->tc.frac; + timer = &clock->timer; + + info->nsec = timer->tc.nsec; + info->cycles = timer->tc.cycle_last; + info->mask = timer->cycles.mask; + info->mult = timer->nominal_c_mult; + info->shift = timer->cycles.shift; + info->frac = timer->tc.frac; - cancel_delayed_work_sync(&clock->overflow_work); + cancel_delayed_work_sync(&clock->timer.overflow_work); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h + struct mlx5_timer *timer = &clock->timer; - nsec = timecounter_cyc2time(&clock->tc, timestamp); + nsec = timecounter_cyc2time(&timer->tc, timestamp); diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h -struct mlx5_clock { - struct mlx5_nb pps_nb; - seqlock_t lock; +struct mlx5_timer { - struct hwtstamp_config hwtstamp_config; +}; + +struct mlx5_clock { + struct mlx5_nb pps_nb; + seqlock_t lock; + struct hwtstamp_config hwtstamp_config; + struct mlx5_timer timer;
|
Networking
|
d6f3dc8f509ce6288e2537eb4b0614ef444fd84a
|
eran ben elisha
|
drivers
|
net
|
core, ethernet, lib, mellanox, mlx5
|
net/mlx5: move some pps logic into helper functions
|
some of pps logic (timestamp calculations) fits only internal timer timestamp mode. move these logics into helper functions. later in the patchset cyc2time hw translation mode will expose its own pps timestamp calculations.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mlx5 real time clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 73
| 40
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +static u64 find_target_cycles(struct mlx5_core_dev *mdev, s64 target_ns) +{ + struct mlx5_clock *clock = &mdev->clock; + u64 cycles_now, cycles_delta; + u64 nsec_now, nsec_delta; + struct mlx5_timer *timer; + unsigned long flags; + + timer = &clock->timer; + + cycles_now = mlx5_read_internal_timer(mdev, null); + write_seqlock_irqsave(&clock->lock, flags); + nsec_now = timecounter_cyc2time(&timer->tc, cycles_now); + nsec_delta = target_ns - nsec_now; + cycles_delta = div64_u64(nsec_delta << timer->cycles.shift, + timer->cycles.mult); + write_sequnlock_irqrestore(&clock->lock, flags); + + return cycles_now + cycles_delta; +} + +static u64 perout_conf_internal_timer(struct mlx5_core_dev *mdev, + s64 sec, u32 nsec) +{ + struct timespec64 ts; + s64 target_ns; + + ts.tv_sec = sec; + ts.tv_nsec = nsec; + target_ns = timespec64_to_ns(&ts); + + return find_target_cycles(mdev, target_ns); +} + - struct mlx5_timer *timer = &clock->timer; - u64 nsec_now, nsec_delta, time_stamp = 0; - u64 cycles_now, cycles_delta; - unsigned long flags; + u64 time_stamp = 0; - pin = ptp_find_pin(clock->ptp, ptp_pf_perout, - rq->perout.index); - if (pin < 0) - return -ebusy; - + field_select = mlx5_mtpps_fs_enable; + u32 nsec; + s64 sec; + + pin = ptp_find_pin(clock->ptp, ptp_pf_perout, rq->perout.index); + if (pin < 0) + return -ebusy; + - ts.tv_sec = rq->perout.start.sec; - ts.tv_nsec = rq->perout.start.nsec; - ns = timespec64_to_ns(&ts); - cycles_now = mlx5_read_internal_timer(mdev, null); - write_seqlock_irqsave(&clock->lock, flags); - nsec_now = timecounter_cyc2time(&timer->tc, cycles_now); - nsec_delta = ns - nsec_now; - cycles_delta = div64_u64(nsec_delta << timer->cycles.shift, - timer->cycles.mult); - write_sequnlock_irqrestore(&clock->lock, flags); - time_stamp = cycles_now + cycles_delta; - field_select = mlx5_mtpps_fs_pin_mode | - mlx5_mtpps_fs_pattern | - mlx5_mtpps_fs_enable | - mlx5_mtpps_fs_time_stamp; - } else { - field_select = mlx5_mtpps_fs_enable; + nsec = rq->perout.start.nsec; + sec = rq->perout.start.sec; + + time_stamp = perout_conf_internal_timer(mdev, sec, nsec); + + field_select |= mlx5_mtpps_fs_pin_mode | + mlx5_mtpps_fs_pattern | + mlx5_mtpps_fs_time_stamp; +static void ts_next_sec(struct timespec64 *ts) +{ + ts->tv_sec += 1; + ts->tv_nsec = 0; +} + +static u64 perout_conf_next_event_inernal_timer(struct mlx5_core_dev *mdev, + struct mlx5_clock *clock) +{ + struct timespec64 ts; + s64 target_ns; + + mlx5_ptp_gettimex(&clock->ptp_info, &ts, null); + ts_next_sec(&ts); + target_ns = timespec64_to_ns(&ts); + + return find_target_cycles(mdev, target_ns); +} + - struct mlx5_timer *timer = &clock->timer; - u64 cycles_now, cycles_delta; - u64 nsec_now, nsec_delta, ns; - struct timespec64 ts; + u64 ns; - mlx5_ptp_gettimex(&clock->ptp_info, &ts, null); - cycles_now = mlx5_read_internal_timer(mdev, null); - ts.tv_sec += 1; - ts.tv_nsec = 0; - ns = timespec64_to_ns(&ts); + ns = perout_conf_next_event_inernal_timer(mdev, clock); - nsec_now = timecounter_cyc2time(&timer->tc, cycles_now); - nsec_delta = ns - nsec_now; - cycles_delta = div64_u64(nsec_delta << timer->cycles.shift, - timer->cycles.mult); - clock->pps_info.start[pin] = cycles_now + cycles_delta; + clock->pps_info.start[pin] = ns;
|
Networking
|
de19cd6cc9777e258de853c3ddf5d5a7bbadf165
|
eran ben elisha
|
drivers
|
net
|
core, ethernet, lib, mellanox, mlx5
|
net/mlx5: add cyc2time hw translation mode support
|
device timestamp can be in real time mode (cycles to time translation is offloaded into the hardware). with real time mode, hw provides timestamp which is already translated into nanoseconds.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
mlx5 real time clock
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 8
| 241
| 38
|
- improve mtae (max time absolute error) for hw ts by up to 160 ns over a - faster data-path timestamp to nanoseconds, as translation is --- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h --- a/drivers/net/ethernet/mellanox/mlx5/core/en.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h +#include "lib/clock.h" + cqe_ts_to_ns ptp_cyc2time; + cqe_ts_to_ns ptp_cyc2time; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c --- a/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/ptp.c -#include "lib/clock.h" + struct mlx5e_txqsq *sq = &ptpsq->txqsq; - hwtstamp = mlx5_timecounter_cyc2time(ptpsq->txqsq.clock, get_cqe_ts(cqe)); + hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, get_cqe_ts(cqe)); + sq->ptp_cyc2time = mlx5_is_real_time_sq(mdev) ? + mlx5_real_time_cyc2time : + mlx5_timecounter_cyc2time; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h --- a/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/txrx.h +static inline +ktime_t mlx5e_cqe_ts_to_ns(cqe_ts_to_ns func, struct mlx5_clock *clock, u64 cqe_ts) +{ + return indirect_call_2(func, mlx5_real_time_cyc2time, mlx5_timecounter_cyc2time, + clock, cqe_ts); +} + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c + rq->ptp_cyc2time = mlx5_is_real_time_rq(mdev) ? + mlx5_real_time_cyc2time : + mlx5_timecounter_cyc2time; - + u8 ts_format; + ts_format = mlx5_is_real_time_rq(mdev) ? + mlx5_rqc_timestamp_format_real_time : + mlx5_rqc_timestamp_format_free_running; + mlx5_set(rqc, rqc, ts_format, ts_format); + sq->ptp_cyc2time = mlx5_is_real_time_sq(mdev) ? + mlx5_real_time_cyc2time : + mlx5_timecounter_cyc2time; + u8 ts_format; + ts_format = mlx5_is_real_time_sq(mdev) ? + mlx5_sqc_timestamp_format_real_time : + mlx5_sqc_timestamp_format_free_running; + mlx5_set(sqc, sqc, ts_format, ts_format); + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c --- a/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_rx.c -#include "lib/clock.h" - skb_hwtstamps(skb)->hwtstamp = - mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); - + skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time, + rq->clock, get_cqe_ts(cqe)); - skb_hwtstamps(skb)->hwtstamp = - mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe)); - + skb_hwtstamps(skb)->hwtstamp = mlx5e_cqe_ts_to_ns(rq->ptp_cyc2time, + rq->clock, get_cqe_ts(cqe)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c --- a/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tx.c -#include "lib/clock.h" - hwts.hwtstamp = mlx5_timecounter_cyc2time(sq->clock, ts); + hwts.hwtstamp = mlx5e_cqe_ts_to_ns(sq->ptp_cyc2time, sq->clock, ts); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c -static u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev, - struct ptp_system_timestamp *sts) +static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev) +{ + return (mlx5_is_real_time_rq(mdev) || mlx5_is_real_time_sq(mdev)); +} + +static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev) +{ + return mlx5_cap_mcam_feature(mdev, ptpcyc2realtime_modify); +} + +static int mlx5_set_mtutc(struct mlx5_core_dev *dev, u32 *mtutc, u32 size) +{ + u32 out[mlx5_st_sz_dw(mtutc_reg)] = {}; + + if (!mlx5_cap_mcam_reg(dev, mtutc)) + return -eopnotsupp; + + return mlx5_core_access_reg(dev, mtutc, size, out, sizeof(out), + mlx5_reg_mtutc, 0, 1); +} + +static u64 mlx5_read_time(struct mlx5_core_dev *dev, + struct ptp_system_timestamp *sts, + bool real_time) - timer_h = ioread32be(&dev->iseg->internal_timer_h); + timer_h = ioread32be(real_time ? &dev->iseg->real_time_h : + &dev->iseg->internal_timer_h); - timer_l = ioread32be(&dev->iseg->internal_timer_l); + timer_l = ioread32be(real_time ? &dev->iseg->real_time_l : + &dev->iseg->internal_timer_l); - timer_h1 = ioread32be(&dev->iseg->internal_timer_h); + timer_h1 = ioread32be(real_time ? &dev->iseg->real_time_h : + &dev->iseg->internal_timer_h); - timer_l = ioread32be(&dev->iseg->internal_timer_l); + timer_l = ioread32be(real_time ? &dev->iseg->real_time_l : + &dev->iseg->internal_timer_l); - return (u64)timer_l | (u64)timer_h1 << 32; + return real_time ? real_time_to_ns(timer_h1, timer_l) : + (u64)timer_l | (u64)timer_h1 << 32; - return mlx5_read_internal_timer(mdev, null) & cc->mask; + return mlx5_read_time(mdev, null, false) & cc->mask; +static int mlx5_ptp_settime_real_time(struct mlx5_core_dev *mdev, + const struct timespec64 *ts) +{ + u32 in[mlx5_st_sz_dw(mtutc_reg)] = {}; + + if (!mlx5_modify_mtutc_allowed(mdev)) + return 0; + + if (ts->tv_sec < 0 || ts->tv_sec > u32_max || + ts->tv_nsec < 0 || ts->tv_nsec > nsec_per_sec) + return -einval; + + mlx5_set(mtutc_reg, in, operation, mlx5_mtutc_operation_set_time_immediate); + mlx5_set(mtutc_reg, in, utc_sec, ts->tv_sec); + mlx5_set(mtutc_reg, in, utc_nsec, ts->tv_nsec); + + return mlx5_set_mtutc(mdev, in, sizeof(in)); +} + - u64 ns = timespec64_to_ns(ts); + int err; + err = mlx5_ptp_settime_real_time(mdev, ts); + if (err) + return err; + - timecounter_init(&timer->tc, &timer->cycles, ns); + timecounter_init(&timer->tc, &timer->cycles, timespec64_to_ns(ts)); +static +struct timespec64 mlx5_ptp_gettimex_real_time(struct mlx5_core_dev *mdev, + struct ptp_system_timestamp *sts) +{ + struct timespec64 ts; + u64 time; + + time = mlx5_read_time(mdev, sts, true); + ts = ns_to_timespec64(time); + return ts; +} + + if (mlx5_real_time_mode(mdev)) { + *ts = mlx5_ptp_gettimex_real_time(mdev, sts); + goto out; + } + - cycles = mlx5_read_internal_timer(mdev, sts); + cycles = mlx5_read_time(mdev, sts, false); - - +out: +static int mlx5_ptp_adjtime_real_time(struct mlx5_core_dev *mdev, s64 delta) +{ + u32 in[mlx5_st_sz_dw(mtutc_reg)] = {}; + + if (!mlx5_modify_mtutc_allowed(mdev)) + return 0; + + /* hw time adjustment range is s16. if out of range, settime instead */ + if (delta < s16_min || delta > s16_max) { + struct timespec64 ts; + s64 ns; + + ts = mlx5_ptp_gettimex_real_time(mdev, null); + ns = timespec64_to_ns(&ts) + delta; + ts = ns_to_timespec64(ns); + return mlx5_ptp_settime_real_time(mdev, &ts); + } + + mlx5_set(mtutc_reg, in, operation, mlx5_mtutc_operation_adjust_time); + mlx5_set(mtutc_reg, in, time_adjustment, delta); + + return mlx5_set_mtutc(mdev, in, sizeof(in)); +} + + int err; + + err = mlx5_ptp_adjtime_real_time(mdev, delta); + if (err) + return err; +static int mlx5_ptp_adjfreq_real_time(struct mlx5_core_dev *mdev, s32 freq) +{ + u32 in[mlx5_st_sz_dw(mtutc_reg)] = {}; + + if (!mlx5_modify_mtutc_allowed(mdev)) + return 0; + + mlx5_set(mtutc_reg, in, operation, mlx5_mtutc_operation_adjust_freq_utc); + mlx5_set(mtutc_reg, in, freq_adjustment, freq); + + return mlx5_set_mtutc(mdev, in, sizeof(in)); +} + + int err; + + mdev = container_of(clock, struct mlx5_core_dev, clock); + err = mlx5_ptp_adjfreq_real_time(mdev, delta); + if (err) + return err; - mdev = container_of(clock, struct mlx5_core_dev, clock); - cycles_now = mlx5_read_internal_timer(mdev, null); + cycles_now = mlx5_read_time(mdev, null, false); +static u64 perout_conf_real_time(s64 sec, u32 nsec) +{ + return (u64)nsec | (u64)sec << 32; +} + + bool rt_mode = mlx5_real_time_mode(mdev); - time_stamp = perout_conf_internal_timer(mdev, sec, nsec); + if (rt_mode && sec > u32_max) + return -einval; + + time_stamp = rt_mode ? perout_conf_real_time(sec, nsec) : + perout_conf_internal_timer(mdev, sec, nsec); -static u64 perout_conf_next_event_inernal_timer(struct mlx5_core_dev *mdev, - struct mlx5_clock *clock) +static u64 perout_conf_next_event_timer(struct mlx5_core_dev *mdev, + struct mlx5_clock *clock) + bool rt_mode = mlx5_real_time_mode(mdev); - mlx5_ptp_gettimex(&clock->ptp_info, &ts, null); + if (rt_mode) + ts = mlx5_ptp_gettimex_real_time(mdev, null); + else + mlx5_ptp_gettimex(&clock->ptp_info, &ts, null); + - return find_target_cycles(mdev, target_ns); + return rt_mode ? perout_conf_real_time(ts.tv_sec, ts.tv_nsec) : + find_target_cycles(mdev, target_ns); - ptp_event.timestamp = + ptp_event.timestamp = mlx5_real_time_mode(mdev) ? + mlx5_real_time_cyc2time(clock, + be64_to_cpu(eqe->data.pps.time_stamp)) : - ns = perout_conf_next_event_inernal_timer(mdev, clock); + ns = perout_conf_next_event_timer(mdev, clock); +static void mlx5_init_timer_clock(struct mlx5_core_dev *mdev) +{ + struct mlx5_clock *clock = &mdev->clock; + + mlx5_timecounter_init(mdev); + mlx5_init_clock_info(mdev); + mlx5_init_overflow_period(clock); + clock->ptp_info = mlx5_ptp_clock_info; + + if (mlx5_real_time_mode(mdev)) { + struct timespec64 ts; + + ktime_get_real_ts64(&ts); + mlx5_ptp_settime(&clock->ptp_info, &ts); + } +} + - - mlx5_timecounter_init(mdev); - mlx5_init_clock_info(mdev); - mlx5_init_overflow_period(clock); + mlx5_init_timer_clock(mdev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.h +static inline bool mlx5_is_real_time_rq(struct mlx5_core_dev *mdev) +{ + u8 rq_ts_format_cap = mlx5_cap_gen(mdev, rq_ts_format); + + return (rq_ts_format_cap == mlx5_rq_timestamp_format_cap_real_time || + rq_ts_format_cap == mlx5_rq_timestamp_format_cap_free_running_and_real_time); +} + +static inline bool mlx5_is_real_time_sq(struct mlx5_core_dev *mdev) +{ + u8 sq_ts_format_cap = mlx5_cap_gen(mdev, sq_ts_format); + + return (sq_ts_format_cap == mlx5_sq_timestamp_format_cap_real_time || + sq_ts_format_cap == mlx5_sq_timestamp_format_cap_free_running_and_real_time); +} + +typedef ktime_t (*cqe_ts_to_ns)(struct mlx5_clock *, u64); + +#define real_time_to_ns(hi, low) (((u64)hi) * nsec_per_sec + ((u64)low)) + +static inline ktime_t mlx5_real_time_cyc2time(struct mlx5_clock *clock, + u64 timestamp) +{ + u64 time = real_time_to_ns(timestamp >> 32, timestamp & 0xffffffff); + + return ns_to_ktime(time); +} + +static inline ktime_t mlx5_real_time_cyc2time(struct mlx5_clock *clock, + u64 timestamp) +{ + return 0; +}
|
Networking
|
432119de33d9013467371fc85238d623f64ff67e
|
aya levin
|
drivers
|
net
|
core, en, ethernet, lib, mellanox, mlx5
|
net/mlx5: dr, add infrastructure for supporting several steering formats
|
add a struct of device specific callbacks for ste layer below dr_ste. each device will implement its hw-specific function, and a comon logic from the dr code will access these functions through the new ste_ctx api.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 37
| 1
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -#include "dr_types.h" +#include "dr_ste.h" diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +/* spdx-license-identifier: gpl-2.0 or linux-openib */ +/* copyright (c) 2020 nvidia corporation. all rights reserved. */ + +#ifndef _dr_ste_ +#define _dr_ste_ + +#include "dr_types.h" + +#define dr_ste_ctx_builder(fname) \ + ((*build_##fname##_init)(struct mlx5dr_ste_build *sb, \ + struct mlx5dr_match_param *mask)) + +struct mlx5dr_ste_ctx { + void dr_ste_ctx_builder(eth_l2_src_dst); + void dr_ste_ctx_builder(eth_l3_ipv6_src); + void dr_ste_ctx_builder(eth_l3_ipv6_dst); + void dr_ste_ctx_builder(eth_l3_ipv4_5_tuple); + void dr_ste_ctx_builder(eth_l2_src); + void dr_ste_ctx_builder(eth_l2_dst); + void dr_ste_ctx_builder(eth_l2_tnl); + void dr_ste_ctx_builder(eth_l3_ipv4_misc); + void dr_ste_ctx_builder(eth_ipv6_l3_l4); + void dr_ste_ctx_builder(mpls); + void dr_ste_ctx_builder(tnl_gre); + void dr_ste_ctx_builder(tnl_mpls); + int dr_ste_ctx_builder(icmp); + void dr_ste_ctx_builder(general_purpose); + void dr_ste_ctx_builder(eth_l4_misc); + void dr_ste_ctx_builder(tnl_vxlan_gpe); + void dr_ste_ctx_builder(tnl_geneve); + void dr_ste_ctx_builder(register_0); + void dr_ste_ctx_builder(register_1); + void dr_ste_ctx_builder(src_gvmi_qpn); +}; + +#endif /* _dr_ste_ */
|
Networking
|
4bdba39b703acbe5d0094675a71f736d386fbe96
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, move macros from dr_ste.c to header
|
move some macros from dr_ste.c to header - these macros will be used by all the format-specific functions.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 76
| 74
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -#define ste_ipv4 0x1 -#define ste_ipv6 0x2 -#define ste_tcp 0x1 -#define ste_udp 0x2 -#define ste_spi 0x3 -#define ip_version_ipv4 0x4 -#define ip_version_ipv6 0x6 -#define ste_svlan 0x1 -#define ste_cvlan 0x2 -/* set to ste a specific value using dr_ste_set */ -#define dr_ste_set_val(lookup_type, tag, t_fname, spec, s_fname, value) do { \ - if ((spec)->s_fname) { \ - mlx5_set(ste_##lookup_type, tag, t_fname, value); \ - (spec)->s_fname = 0; \ - } \ -} while (0) - -/* set to ste spec->s_fname to tag->t_fname */ -#define dr_ste_set_tag(lookup_type, tag, t_fname, spec, s_fname) \ - dr_ste_set_val(lookup_type, tag, t_fname, spec, s_fname, spec->s_fname) - -/* set to ste -1 to bit_mask->bm_fname and set spec->s_fname as used */ -#define dr_ste_set_mask(lookup_type, bit_mask, bm_fname, spec, s_fname) \ - dr_ste_set_val(lookup_type, bit_mask, bm_fname, spec, s_fname, -1) - -/* set to ste spec->s_fname to bit_mask->bm_fname and set spec->s_fname as used */ -#define dr_ste_set_mask_v(lookup_type, bit_mask, bm_fname, spec, s_fname) \ - dr_ste_set_val(lookup_type, bit_mask, bm_fname, spec, s_fname, (spec)->s_fname) - -#define dr_ste_set_tcp_flags(lookup_type, tag, spec) do { \ - mlx5_set(ste_##lookup_type, tag, tcp_ns, !!((spec)->tcp_flags & (1 << 8))); \ - mlx5_set(ste_##lookup_type, tag, tcp_cwr, !!((spec)->tcp_flags & (1 << 7))); \ - mlx5_set(ste_##lookup_type, tag, tcp_ece, !!((spec)->tcp_flags & (1 << 6))); \ - mlx5_set(ste_##lookup_type, tag, tcp_urg, !!((spec)->tcp_flags & (1 << 5))); \ - mlx5_set(ste_##lookup_type, tag, tcp_ack, !!((spec)->tcp_flags & (1 << 4))); \ - mlx5_set(ste_##lookup_type, tag, tcp_psh, !!((spec)->tcp_flags & (1 << 3))); \ - mlx5_set(ste_##lookup_type, tag, tcp_rst, !!((spec)->tcp_flags & (1 << 2))); \ - mlx5_set(ste_##lookup_type, tag, tcp_syn, !!((spec)->tcp_flags & (1 << 1))); \ - mlx5_set(ste_##lookup_type, tag, tcp_fin, !!((spec)->tcp_flags & (1 << 0))); \ -} while (0) - -#define dr_ste_set_mpls_mask(lookup_type, mask, in_out, bit_mask) do { \ - dr_ste_set_mask_v(lookup_type, mask, mpls0_label, mask, \ - in_out##_first_mpls_label);\ - dr_ste_set_mask_v(lookup_type, mask, mpls0_s_bos, mask, \ - in_out##_first_mpls_s_bos); \ - dr_ste_set_mask_v(lookup_type, mask, mpls0_exp, mask, \ - in_out##_first_mpls_exp); \ - dr_ste_set_mask_v(lookup_type, mask, mpls0_ttl, mask, \ - in_out##_first_mpls_ttl); \ -} while (0) - -#define dr_ste_set_mpls_tag(lookup_type, mask, in_out, tag) do { \ - dr_ste_set_tag(lookup_type, tag, mpls0_label, mask, \ - in_out##_first_mpls_label);\ - dr_ste_set_tag(lookup_type, tag, mpls0_s_bos, mask, \ - in_out##_first_mpls_s_bos); \ - dr_ste_set_tag(lookup_type, tag, mpls0_exp, mask, \ - in_out##_first_mpls_exp); \ - dr_ste_set_tag(lookup_type, tag, mpls0_ttl, mask, \ - in_out##_first_mpls_ttl); \ -} while (0) - -#define dr_ste_is_outer_mpls_over_gre_set(_misc) (\ - (_misc)->outer_first_mpls_over_gre_label || \ - (_misc)->outer_first_mpls_over_gre_exp || \ - (_misc)->outer_first_mpls_over_gre_s_bos || \ - (_misc)->outer_first_mpls_over_gre_ttl) -#define dr_ste_is_outer_mpls_over_udp_set(_misc) (\ - (_misc)->outer_first_mpls_over_udp_label || \ - (_misc)->outer_first_mpls_over_udp_exp || \ - (_misc)->outer_first_mpls_over_udp_s_bos || \ - (_misc)->outer_first_mpls_over_udp_ttl) - diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +#define ste_ipv4 0x1 +#define ste_ipv6 0x2 +#define ste_tcp 0x1 +#define ste_udp 0x2 +#define ste_spi 0x3 +#define ip_version_ipv4 0x4 +#define ip_version_ipv6 0x6 +#define ste_svlan 0x1 +#define ste_cvlan 0x2 + +/* set to ste a specific value using dr_ste_set */ +#define dr_ste_set_val(lookup_type, tag, t_fname, spec, s_fname, value) do { \ + if ((spec)->s_fname) { \ + mlx5_set(ste_##lookup_type, tag, t_fname, value); \ + (spec)->s_fname = 0; \ + } \ +} while (0) + +/* set to ste spec->s_fname to tag->t_fname */ +#define dr_ste_set_tag(lookup_type, tag, t_fname, spec, s_fname) \ + dr_ste_set_val(lookup_type, tag, t_fname, spec, s_fname, spec->s_fname) + +/* set to ste -1 to bit_mask->bm_fname and set spec->s_fname as used */ +#define dr_ste_set_mask(lookup_type, bit_mask, bm_fname, spec, s_fname) \ + dr_ste_set_val(lookup_type, bit_mask, bm_fname, spec, s_fname, -1) + +/* set to ste spec->s_fname to bit_mask->bm_fname and set spec->s_fname as used */ +#define dr_ste_set_mask_v(lookup_type, bit_mask, bm_fname, spec, s_fname) \ + dr_ste_set_val(lookup_type, bit_mask, bm_fname, spec, s_fname, (spec)->s_fname) + +#define dr_ste_set_tcp_flags(lookup_type, tag, spec) do { \ + mlx5_set(ste_##lookup_type, tag, tcp_ns, !!((spec)->tcp_flags & (1 << 8))); \ + mlx5_set(ste_##lookup_type, tag, tcp_cwr, !!((spec)->tcp_flags & (1 << 7))); \ + mlx5_set(ste_##lookup_type, tag, tcp_ece, !!((spec)->tcp_flags & (1 << 6))); \ + mlx5_set(ste_##lookup_type, tag, tcp_urg, !!((spec)->tcp_flags & (1 << 5))); \ + mlx5_set(ste_##lookup_type, tag, tcp_ack, !!((spec)->tcp_flags & (1 << 4))); \ + mlx5_set(ste_##lookup_type, tag, tcp_psh, !!((spec)->tcp_flags & (1 << 3))); \ + mlx5_set(ste_##lookup_type, tag, tcp_rst, !!((spec)->tcp_flags & (1 << 2))); \ + mlx5_set(ste_##lookup_type, tag, tcp_syn, !!((spec)->tcp_flags & (1 << 1))); \ + mlx5_set(ste_##lookup_type, tag, tcp_fin, !!((spec)->tcp_flags & (1 << 0))); \ +} while (0) + +#define dr_ste_set_mpls_mask(lookup_type, mask, in_out, bit_mask) do { \ + dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_label, mask, \ + in_out##_first_mpls_label);\ + dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_s_bos, mask, \ + in_out##_first_mpls_s_bos); \ + dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_exp, mask, \ + in_out##_first_mpls_exp); \ + dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_ttl, mask, \ + in_out##_first_mpls_ttl); \ +} while (0) + +#define dr_ste_set_mpls_tag(lookup_type, mask, in_out, tag) do { \ + dr_ste_set_tag(lookup_type, tag, mpls0_label, mask, \ + in_out##_first_mpls_label);\ + dr_ste_set_tag(lookup_type, tag, mpls0_s_bos, mask, \ + in_out##_first_mpls_s_bos); \ + dr_ste_set_tag(lookup_type, tag, mpls0_exp, mask, \ + in_out##_first_mpls_exp); \ + dr_ste_set_tag(lookup_type, tag, mpls0_ttl, mask, \ + in_out##_first_mpls_ttl); \ +} while (0) + +#define dr_ste_is_outer_mpls_over_gre_set(_misc) (\ + (_misc)->outer_first_mpls_over_gre_label || \ + (_misc)->outer_first_mpls_over_gre_exp || \ + (_misc)->outer_first_mpls_over_gre_s_bos || \ + (_misc)->outer_first_mpls_over_gre_ttl) + +#define dr_ste_is_outer_mpls_over_udp_set(_misc) (\ + (_misc)->outer_first_mpls_over_udp_label || \ + (_misc)->outer_first_mpls_over_udp_exp || \ + (_misc)->outer_first_mpls_over_udp_s_bos || \ + (_misc)->outer_first_mpls_over_udp_ttl) +
|
Networking
|
75699246a01fa90587a8fc83ff0dffe3288cb91c
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
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net/mlx5: dr, use the new hw specific ste infrastructure
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split the ste builders functionality into the common part and device-specific part. all the device-specific part (with 'v0' in the function names) is accessed through the ste context structure.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['mlx5/mlx5e ']
|
['h', 'c']
| 5
| 613
| 330
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c + dmn->ste_ctx = mlx5dr_ste_get_ctx(dmn->info.caps.sw_format_ver); + if (!dmn->ste_ctx) { + mlx5dr_err(dmn, "sw steering on this device is unsupported "); + return -eopnotsupp; + } + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - mlx5dr_ste_build_general_purpose(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_general_purpose(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_register_0(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_register_0(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_register_1(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_register_1(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_src_gvmi_qpn(&sb[idx++], &mask, - dmn, inner, rx); + mlx5dr_ste_build_src_gvmi_qpn(ste_ctx, &sb[idx++], + &mask, dmn, inner, rx); - mlx5dr_ste_build_eth_l2_src_dst(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l2_src_dst(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l2_src(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l2_src(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l2_dst(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l2_dst(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv6_dst(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv6_dst(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv6_src(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv6_src(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_ipv6_l3_l4(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_ipv6_l3_l4(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv4_5_tuple(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv4_5_tuple(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv4_misc(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv4_misc(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_tnl_vxlan_gpe(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_tnl_vxlan_gpe(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_tnl_geneve(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_tnl_geneve(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l4_misc(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l4_misc(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_mpls(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_mpls(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_tnl_mpls(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_tnl_mpls(ste_ctx, &sb[idx++], + &mask, inner, rx); - ret = mlx5dr_ste_build_icmp(&sb[idx++], + ret = mlx5dr_ste_build_icmp(ste_ctx, &sb[idx++], - mlx5dr_ste_build_tnl_gre(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_tnl_gre(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l2_tnl(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l2_tnl(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l2_src_dst(&sb[idx++], + mlx5dr_ste_build_eth_l2_src_dst(ste_ctx, &sb[idx++], - mlx5dr_ste_build_eth_l2_src(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l2_src(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l2_dst(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l2_dst(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv6_dst(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv6_dst(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv6_src(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv6_src(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_ipv6_l3_l4(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_ipv6_l3_l4(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv4_5_tuple(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv4_5_tuple(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l3_ipv4_misc(&sb[idx++], &mask, - inner, rx); + mlx5dr_ste_build_eth_l3_ipv4_misc(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_eth_l4_misc(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_eth_l4_misc(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_mpls(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_mpls(ste_ctx, &sb[idx++], + &mask, inner, rx); - mlx5dr_ste_build_tnl_mpls(&sb[idx++], &mask, inner, rx); + mlx5dr_ste_build_tnl_mpls(ste_ctx, &sb[idx++], + &mask, inner, rx); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -static u16 dr_ste_conv_bit_to_byte_mask(u8 *bit_mask) +u16 mlx5dr_ste_conv_bit_to_byte_mask(u8 *bit_mask) -static void dr_ste_build_eth_l2_src_des_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); - - if (mask->smac_47_16 || mask->smac_15_0) { - mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_47_32, - mask->smac_47_16 >> 16); - mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_31_0, - mask->smac_47_16 << 16 | mask->smac_15_0); - mask->smac_47_16 = 0; - mask->smac_15_0 = 0; - } - - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); - - if (mask->cvlan_tag) { - mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); - mask->cvlan_tag = 0; - } else if (mask->svlan_tag) { - mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); - mask->svlan_tag = 0; - } -} - -static int dr_ste_build_eth_l2_src_des_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static void +dr_ste_v0_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); + + if (mask->smac_47_16 || mask->smac_15_0) { + mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_47_32, + mask->smac_47_16 >> 16); + mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_31_0, + mask->smac_47_16 << 16 | mask->smac_15_0); + mask->smac_47_16 = 0; + mask->smac_15_0 = 0; + } + + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); + dr_ste_set_mask(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); + + if (mask->cvlan_tag) { + mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + } else if (mask->svlan_tag) { + mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); + mask->svlan_tag = 0; + } +} + +static int +dr_ste_v0_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl2_src_dst, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_src_dst_tag; +} + +void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l2_src_des_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl2_src_dst, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l2_src_des_tag; + ste_ctx->build_eth_l2_src_dst_init(sb, mask); -static void dr_ste_build_eth_l3_ipv6_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_dst, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv6_dst_tag; +} + +void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l3_ipv6_dst_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_dst, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l3_ipv6_dst_tag; + ste_ctx->build_eth_l3_ipv6_dst_init(sb, mask); -static void dr_ste_build_eth_l3_ipv6_src_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_src, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv6_src_tag; +} + +void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l3_ipv6_src_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_src, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l3_ipv6_src_tag; + ste_ctx->build_eth_l3_ipv6_src_init(sb, mask); -static void dr_ste_build_eth_l3_ipv4_5_tuple_bit_mask(struct mlx5dr_match_param *value, - bool inner, - u8 *bit_mask) +static void +dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(struct mlx5dr_match_param *value, + bool inner, + u8 *bit_mask) -static int dr_ste_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_5_tuple, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag; +} + +void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l3_ipv4_5_tuple_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_5_tuple, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l3_ipv4_5_tuple_tag; + ste_ctx->build_eth_l3_ipv4_5_tuple_init(sb, mask); -dr_ste_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value, - bool inner, u8 *tag) +static int +dr_ste_v0_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value, + bool inner, u8 *tag) -static void dr_ste_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) - dr_ste_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); + dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); -static int dr_ste_build_eth_l2_src_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l2_src_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) - return dr_ste_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); + return dr_ste_v0_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); +} + +static void +dr_ste_v0_build_eth_l2_src_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask); + sb->lu_type = dr_ste_calc_lu_type(ethl2_src, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_src_tag; -void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l2_src_bit_mask(mask, inner, sb->bit_mask); - sb->lu_type = dr_ste_calc_lu_type(ethl2_src, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l2_src_tag; + ste_ctx->build_eth_l2_src_init(sb, mask); -static void dr_ste_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) - dr_ste_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); + dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); -static int dr_ste_build_eth_l2_dst_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l2_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) - return dr_ste_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); + return dr_ste_v0_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); -void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl2_dst, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_dst_tag; +} + +void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l2_dst_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl2_dst, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l2_dst_tag; + ste_ctx->build_eth_l2_dst_init(sb, mask); -static void dr_ste_build_eth_l2_tnl_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l2_tnl_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask, bool inner, bool rx) +static void +dr_ste_v0_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) - dr_ste_build_eth_l2_tnl_bit_mask(mask, inner, sb->bit_mask); + dr_ste_v0_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask); + sb->lu_type = mlx5dr_ste_lu_type_ethl2_tunneling_i; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_tnl_tag; +} + +void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask, bool inner, bool rx) +{ - sb->lu_type = mlx5dr_ste_lu_type_ethl2_tunneling_i; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l2_tnl_tag; + ste_ctx->build_eth_l2_tnl_init(sb, mask); -static void dr_ste_build_eth_l3_ipv4_misc_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_misc, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv4_misc_tag; +} + +void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l3_ipv4_misc_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_misc, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l3_ipv4_misc_tag; + ste_ctx->build_eth_l3_ipv4_misc_init(sb, mask); -static void dr_ste_build_ipv6_l3_l4_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_ipv6_l3_l4_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_ipv6_l3_l4_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl4, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_ipv6_l3_l4_tag; +} + +void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_ipv6_l3_l4_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl4, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_ipv6_l3_l4_tag; + ste_ctx->build_eth_ipv6_l3_l4_init(sb, mask); -static void dr_ste_build_mpls_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_mpls_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_mpls_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_mpls_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_mpls(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_mpls_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_mpls_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(mpls_first, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_mpls_tag; +} + +void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_mpls_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(mpls_first, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_mpls_tag; + ste_ctx->build_mpls_init(sb, mask); -static void dr_ste_build_gre_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_tnl_gre_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_gre_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_tnl_gre_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask, bool inner, bool rx) +static void +dr_ste_v0_build_tnl_gre_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) - dr_ste_build_gre_bit_mask(mask, inner, sb->bit_mask); + dr_ste_v0_build_tnl_gre_bit_mask(mask, sb->inner, sb->bit_mask); + sb->lu_type = mlx5dr_ste_lu_type_gre; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_tnl_gre_tag; +} + +void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask, + bool inner, bool rx) +{ - sb->lu_type = mlx5dr_ste_lu_type_gre; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_gre_tag; + ste_ctx->build_tnl_gre_init(sb, mask); -static void dr_ste_build_flex_parser_0_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_tnl_mpls_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_flex_parser_0_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_tnl_mpls_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_tnl_mpls_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_tnl_mpls_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_0; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_tnl_mpls_tag; +} + +void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_flex_parser_0_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_0; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_flex_parser_0_tag; + ste_ctx->build_tnl_mpls_init(sb, mask); -static int dr_ste_build_flex_parser_1_bit_mask(struct mlx5dr_match_param *mask, - struct mlx5dr_cmd_caps *caps, - u8 *bit_mask) +static int +dr_ste_v0_build_icmp_bit_mask(struct mlx5dr_match_param *mask, + struct mlx5dr_cmd_caps *caps, + u8 *bit_mask) - bool is_ipv4_mask = dr_mask_is_icmpv4_set(&mask->misc3); + bool is_ipv4_mask = dr_mask_is_icmpv4_set(misc_3_mask); -static int dr_ste_build_flex_parser_1_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_icmp_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -int mlx5dr_ste_build_icmp(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask, - struct mlx5dr_cmd_caps *caps, - bool inner, bool rx) +static int +dr_ste_v0_build_icmp_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) - ret = dr_ste_build_flex_parser_1_bit_mask(mask, caps, sb->bit_mask); + ret = dr_ste_v0_build_icmp_bit_mask(mask, sb->caps, sb->bit_mask); - sb->rx = rx; - sb->inner = inner; - sb->caps = caps; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_flex_parser_1_tag; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_icmp_tag; -static void dr_ste_build_general_purpose_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +int mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask, + struct mlx5dr_cmd_caps *caps, + bool inner, bool rx) +{ + sb->rx = rx; + sb->inner = inner; + sb->caps = caps; + return ste_ctx->build_icmp_init(sb, mask); +} + +static void +dr_ste_v0_build_general_purpose_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_general_purpose_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_general_purpose_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_general_purpose_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_general_purpose_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_general_purpose; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_general_purpose_tag; +} + +void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_general_purpose_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_general_purpose; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_general_purpose_tag; + ste_ctx->build_general_purpose_init(sb, mask); -static void dr_ste_build_eth_l4_misc_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +static void +dr_ste_v0_build_eth_l4_misc_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -static int dr_ste_build_eth_l4_misc_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_eth_l4_misc_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l4_misc_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl4_misc, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l4_misc_tag; +} + +void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_eth_l4_misc_bit_mask(mask, inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl4_misc, rx, inner); - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_eth_l4_misc_tag; + ste_ctx->build_eth_l4_misc_init(sb, mask); -dr_ste_build_flex_parser_tnl_vxlan_gpe_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) +dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) -dr_ste_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(mask, sb->inner, + sb->bit_mask); + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag; +} + +void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_flex_parser_tnl_vxlan_gpe_bit_mask(mask, inner, - sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_flex_parser_tnl_vxlan_gpe_tag; + ste_ctx->build_tnl_vxlan_gpe_init(sb, mask); -dr_ste_build_flex_parser_tnl_geneve_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) +dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) -dr_ste_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +dr_ste_v0_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(mask, sb->bit_mask); + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_geneve_tag; +} + +void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_flex_parser_tnl_geneve_bit_mask(mask, sb->bit_mask); - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_flex_parser_tnl_geneve_tag; + ste_ctx->build_tnl_geneve_init(sb, mask); -static void dr_ste_build_register_0_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) +static void +dr_ste_v0_build_register_0_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) -static int dr_ste_build_register_0_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_register_0_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_register_0(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_register_0_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_register_0_bit_mask(mask, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_steering_registers_0; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_register_0_tag; +} + +void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_register_0_bit_mask(mask, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_steering_registers_0; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_register_0_tag; + ste_ctx->build_register_0_init(sb, mask); -static void dr_ste_build_register_1_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) +static void +dr_ste_v0_build_register_1_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) -static int dr_ste_build_register_1_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_register_1_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) -void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_register_1_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_register_1_bit_mask(mask, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_steering_registers_1; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_register_1_tag; +} + +void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_register_1_bit_mask(mask, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_steering_registers_1; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_register_1_tag; + ste_ctx->build_register_1_init(sb, mask); -static void dr_ste_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) +static void +dr_ste_v0_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) -static int dr_ste_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) +static int +dr_ste_v0_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) - if (!vport_cap) + if (!vport_cap) { + mlx5dr_err(dmn, "vport 0x%x is invalid ", + misc->source_port); + } -void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb, +static void +dr_ste_v0_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_src_gvmi_and_qp; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_src_gvmi_qpn_tag; +} + +void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, - dr_ste_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_src_gvmi_and_qp; - sb->byte_mask = dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_build_src_gvmi_qpn_tag; + ste_ctx->build_src_gvmi_qpn_init(sb, mask); +} + +static struct mlx5dr_ste_ctx ste_ctx_v0 = { + .build_eth_l2_src_dst_init = &dr_ste_v0_build_eth_l2_src_dst_init, + .build_eth_l3_ipv6_src_init = &dr_ste_v0_build_eth_l3_ipv6_src_init, + .build_eth_l3_ipv6_dst_init = &dr_ste_v0_build_eth_l3_ipv6_dst_init, + .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v0_build_eth_l3_ipv4_5_tuple_init, + .build_eth_l2_src_init = &dr_ste_v0_build_eth_l2_src_init, + .build_eth_l2_dst_init = &dr_ste_v0_build_eth_l2_dst_init, + .build_eth_l2_tnl_init = &dr_ste_v0_build_eth_l2_tnl_init, + .build_eth_l3_ipv4_misc_init = &dr_ste_v0_build_eth_l3_ipv4_misc_init, + .build_eth_ipv6_l3_l4_init = &dr_ste_v0_build_eth_ipv6_l3_l4_init, + .build_mpls_init = &dr_ste_v0_build_mpls_init, + .build_tnl_gre_init = &dr_ste_v0_build_tnl_gre_init, + .build_tnl_mpls_init = &dr_ste_v0_build_tnl_mpls_init, + .build_icmp_init = &dr_ste_v0_build_icmp_init, + .build_general_purpose_init = &dr_ste_v0_build_general_purpose_init, + .build_eth_l4_misc_init = &dr_ste_v0_build_eth_l4_misc_init, + .build_tnl_vxlan_gpe_init = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init, + .build_tnl_geneve_init = &dr_ste_v0_build_flex_parser_tnl_geneve_init, + .build_register_0_init = &dr_ste_v0_build_register_0_init, + .build_register_1_init = &dr_ste_v0_build_register_1_init, + .build_src_gvmi_qpn_init = &dr_ste_v0_build_src_gvmi_qpn_init, +}; + +static struct mlx5dr_ste_ctx *mlx5dr_ste_ctx_arr[] = { + [mlx5_steering_format_connectx_5] = &ste_ctx_v0, + [mlx5_steering_format_connectx_6dx] = null, +}; + +struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version) +{ + if (version > mlx5_steering_format_connectx_6dx) + return null; + + return mlx5dr_ste_ctx_arr[version]; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +u16 mlx5dr_ste_conv_bit_to_byte_mask(u8 *bit_mask); + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +struct mlx5dr_ste_ctx; +struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version); -void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_build *builder, +void mlx5dr_ste_build_eth_l2_src_dst(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *builder, -void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l3_ipv4_5_tuple(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l3_ipv4_misc(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l3_ipv6_dst(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l3_ipv6_src(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l2_src(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l2_dst(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l2_tnl(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_ipv6_l3_l4(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_eth_l4_misc(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_tnl_gre(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_mpls(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_mpls(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_tnl_mpls(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -int mlx5dr_ste_build_icmp(struct mlx5dr_ste_build *sb, +int mlx5dr_ste_build_icmp(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_tnl_vxlan_gpe(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_tnl_geneve(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_general_purpose(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_register_0(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_register_0(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_register_1(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_register_1(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, -void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_build *sb, +void mlx5dr_ste_build_src_gvmi_qpn(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste_build *sb, + struct mlx5dr_ste_ctx *ste_ctx;
|
Networking
|
5212f9c65a472b549db98ac5d45c851f60b9b357
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, move hw stev0 match logic to a separate file
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move current ste match logic to a seprate file. this file will be used for hw specific stev0.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c', 'makefile']
| 4
| 1,286
| 1,279
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/makefile b/drivers/net/ethernet/mellanox/mlx5/core/makefile --- a/drivers/net/ethernet/mellanox/mlx5/core/makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/makefile + steering/dr_ste_v0.o \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -#define dr_ste_calc_lu_type(lookup_type, rx, inner) \ - ((inner) ? mlx5dr_ste_lu_type_##lookup_type##_i : \ - (rx) ? mlx5dr_ste_lu_type_##lookup_type##_d : \ - mlx5dr_ste_lu_type_##lookup_type##_o) - -static void -dr_ste_v0_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); - - if (mask->smac_47_16 || mask->smac_15_0) { - mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_47_32, - mask->smac_47_16 >> 16); - mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_31_0, - mask->smac_47_16 << 16 | mask->smac_15_0); - mask->smac_47_16 = 0; - mask->smac_15_0 = 0; - } - - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); - - if (mask->cvlan_tag) { - mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); - mask->cvlan_tag = 0; - } else if (mask->svlan_tag) { - mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); - mask->svlan_tag = 0; - } -} - -static int -dr_ste_v0_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l2_src_dst, tag, dmac_47_16, spec, dmac_47_16); - dr_ste_set_tag(eth_l2_src_dst, tag, dmac_15_0, spec, dmac_15_0); - - if (spec->smac_47_16 || spec->smac_15_0) { - mlx5_set(ste_eth_l2_src_dst, tag, smac_47_32, - spec->smac_47_16 >> 16); - mlx5_set(ste_eth_l2_src_dst, tag, smac_31_0, - spec->smac_47_16 << 16 | spec->smac_15_0); - spec->smac_47_16 = 0; - spec->smac_15_0 = 0; - } - - if (spec->ip_version) { - if (spec->ip_version == ip_version_ipv4) { - mlx5_set(ste_eth_l2_src_dst, tag, l3_type, ste_ipv4); - spec->ip_version = 0; - } else if (spec->ip_version == ip_version_ipv6) { - mlx5_set(ste_eth_l2_src_dst, tag, l3_type, ste_ipv6); - spec->ip_version = 0; - } else { - pr_info("unsupported ip_version value "); - return -einval; - } - } - - dr_ste_set_tag(eth_l2_src_dst, tag, first_vlan_id, spec, first_vid); - dr_ste_set_tag(eth_l2_src_dst, tag, first_cfi, spec, first_cfi); - dr_ste_set_tag(eth_l2_src_dst, tag, first_priority, spec, first_prio); - - if (spec->cvlan_tag) { - mlx5_set(ste_eth_l2_src_dst, tag, first_vlan_qualifier, dr_ste_cvlan); - spec->cvlan_tag = 0; - } else if (spec->svlan_tag) { - mlx5_set(ste_eth_l2_src_dst, tag, first_vlan_qualifier, dr_ste_svlan); - spec->svlan_tag = 0; - } - return 0; -} - -static void -dr_ste_v0_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl2_src_dst, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_src_dst_tag; -} - -static void -dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_127_96, mask, dst_ip_127_96); - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_95_64, mask, dst_ip_95_64); - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_63_32, mask, dst_ip_63_32); - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_31_0, mask, dst_ip_31_0); -} - -static int -dr_ste_v0_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_127_96, spec, dst_ip_127_96); - dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_95_64, spec, dst_ip_95_64); - dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_63_32, spec, dst_ip_63_32); - dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_31_0, spec, dst_ip_31_0); - - return 0; -} - -static void -dr_ste_v0_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_dst, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv6_dst_tag; -} - -static void -dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_127_96, mask, src_ip_127_96); - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_95_64, mask, src_ip_95_64); - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_63_32, mask, src_ip_63_32); - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_31_0, mask, src_ip_31_0); -} - -static int -dr_ste_v0_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_127_96, spec, src_ip_127_96); - dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_95_64, spec, src_ip_95_64); - dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_63_32, spec, src_ip_63_32); - dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_31_0, spec, src_ip_31_0); - - return 0; -} - -static void -dr_ste_v0_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_src, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv6_src_tag; -} - -static void -dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(struct mlx5dr_match_param *value, - bool inner, - u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - destination_address, mask, dst_ip_31_0); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - source_address, mask, src_ip_31_0); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - destination_port, mask, tcp_dport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - destination_port, mask, udp_dport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - source_port, mask, tcp_sport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - source_port, mask, udp_sport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - protocol, mask, ip_protocol); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - fragmented, mask, frag); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - dscp, mask, ip_dscp); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - ecn, mask, ip_ecn); - - if (mask->tcp_flags) { - dr_ste_set_tcp_flags(eth_l3_ipv4_5_tuple, bit_mask, mask); - mask->tcp_flags = 0; - } -} - -static int -dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, destination_address, spec, dst_ip_31_0); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, source_address, spec, src_ip_31_0); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, destination_port, spec, tcp_dport); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, destination_port, spec, udp_dport); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, source_port, spec, tcp_sport); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, source_port, spec, udp_sport); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, protocol, spec, ip_protocol); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, fragmented, spec, frag); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, dscp, spec, ip_dscp); - dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, ecn, spec, ip_ecn); - - if (spec->tcp_flags) { - dr_ste_set_tcp_flags(eth_l3_ipv4_5_tuple, tag, spec); - spec->tcp_flags = 0; - } - - return 0; -} - -static void -dr_ste_v0_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_5_tuple, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag; -} - -static void -dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - struct mlx5dr_match_misc *misc_mask = &value->misc; - - dr_ste_set_mask_v(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_src, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_src, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask_v(eth_l2_src, bit_mask, ip_fragmented, mask, frag); - dr_ste_set_mask_v(eth_l2_src, bit_mask, l3_ethertype, mask, ethertype); - dr_ste_set_mask(eth_l2_src, bit_mask, l3_type, mask, ip_version); - - if (mask->svlan_tag || mask->cvlan_tag) { - mlx5_set(ste_eth_l2_src, bit_mask, first_vlan_qualifier, -1); - mask->cvlan_tag = 0; - mask->svlan_tag = 0; - } - - if (inner) { - if (misc_mask->inner_second_cvlan_tag || - misc_mask->inner_second_svlan_tag) { - mlx5_set(ste_eth_l2_src, bit_mask, second_vlan_qualifier, -1); - misc_mask->inner_second_cvlan_tag = 0; - misc_mask->inner_second_svlan_tag = 0; - } - - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_vlan_id, misc_mask, inner_second_vid); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_cfi, misc_mask, inner_second_cfi); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_priority, misc_mask, inner_second_prio); - } else { - if (misc_mask->outer_second_cvlan_tag || - misc_mask->outer_second_svlan_tag) { - mlx5_set(ste_eth_l2_src, bit_mask, second_vlan_qualifier, -1); - misc_mask->outer_second_cvlan_tag = 0; - misc_mask->outer_second_svlan_tag = 0; - } - - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_vlan_id, misc_mask, outer_second_vid); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_cfi, misc_mask, outer_second_cfi); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_priority, misc_mask, outer_second_prio); - } -} - -static int -dr_ste_v0_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value, - bool inner, u8 *tag) -{ - struct mlx5dr_match_spec *spec = inner ? &value->inner : &value->outer; - struct mlx5dr_match_misc *misc_spec = &value->misc; - - dr_ste_set_tag(eth_l2_src, tag, first_vlan_id, spec, first_vid); - dr_ste_set_tag(eth_l2_src, tag, first_cfi, spec, first_cfi); - dr_ste_set_tag(eth_l2_src, tag, first_priority, spec, first_prio); - dr_ste_set_tag(eth_l2_src, tag, ip_fragmented, spec, frag); - dr_ste_set_tag(eth_l2_src, tag, l3_ethertype, spec, ethertype); - - if (spec->ip_version) { - if (spec->ip_version == ip_version_ipv4) { - mlx5_set(ste_eth_l2_src, tag, l3_type, ste_ipv4); - spec->ip_version = 0; - } else if (spec->ip_version == ip_version_ipv6) { - mlx5_set(ste_eth_l2_src, tag, l3_type, ste_ipv6); - spec->ip_version = 0; - } else { - pr_info("unsupported ip_version value "); - return -einval; - } - } - - if (spec->cvlan_tag) { - mlx5_set(ste_eth_l2_src, tag, first_vlan_qualifier, dr_ste_cvlan); - spec->cvlan_tag = 0; - } else if (spec->svlan_tag) { - mlx5_set(ste_eth_l2_src, tag, first_vlan_qualifier, dr_ste_svlan); - spec->svlan_tag = 0; - } - - if (inner) { - if (misc_spec->inner_second_cvlan_tag) { - mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_cvlan); - misc_spec->inner_second_cvlan_tag = 0; - } else if (misc_spec->inner_second_svlan_tag) { - mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_svlan); - misc_spec->inner_second_svlan_tag = 0; - } - - dr_ste_set_tag(eth_l2_src, tag, second_vlan_id, misc_spec, inner_second_vid); - dr_ste_set_tag(eth_l2_src, tag, second_cfi, misc_spec, inner_second_cfi); - dr_ste_set_tag(eth_l2_src, tag, second_priority, misc_spec, inner_second_prio); - } else { - if (misc_spec->outer_second_cvlan_tag) { - mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_cvlan); - misc_spec->outer_second_cvlan_tag = 0; - } else if (misc_spec->outer_second_svlan_tag) { - mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_svlan); - misc_spec->outer_second_svlan_tag = 0; - } - dr_ste_set_tag(eth_l2_src, tag, second_vlan_id, misc_spec, outer_second_vid); - dr_ste_set_tag(eth_l2_src, tag, second_cfi, misc_spec, outer_second_cfi); - dr_ste_set_tag(eth_l2_src, tag, second_priority, misc_spec, outer_second_prio); - } - - return 0; -} - -static void -dr_ste_v0_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l2_src, bit_mask, smac_47_16, mask, smac_47_16); - dr_ste_set_mask_v(eth_l2_src, bit_mask, smac_15_0, mask, smac_15_0); - - dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); -} - -static int -dr_ste_v0_build_eth_l2_src_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l2_src, tag, smac_47_16, spec, smac_47_16); - dr_ste_set_tag(eth_l2_src, tag, smac_15_0, spec, smac_15_0); - - return dr_ste_v0_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); -} - -static void -dr_ste_v0_build_eth_l2_src_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask); - sb->lu_type = dr_ste_calc_lu_type(ethl2_src, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_src_tag; -} - -static void -dr_ste_v0_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l2_dst, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_dst, bit_mask, dmac_15_0, mask, dmac_15_0); - - dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); -} - -static int -dr_ste_v0_build_eth_l2_dst_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l2_dst, tag, dmac_47_16, spec, dmac_47_16); - dr_ste_set_tag(eth_l2_dst, tag, dmac_15_0, spec, dmac_15_0); - - return dr_ste_v0_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); -} - -static void -dr_ste_v0_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl2_dst, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_dst_tag; -} - -static void -dr_ste_v0_build_eth_l2_tnl_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - struct mlx5dr_match_misc *misc = &value->misc; - - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, dmac_15_0, mask, dmac_15_0); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, ip_fragmented, mask, frag); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, l3_ethertype, mask, ethertype); - dr_ste_set_mask(eth_l2_tnl, bit_mask, l3_type, mask, ip_version); - - if (misc->vxlan_vni) { - mlx5_set(ste_eth_l2_tnl, bit_mask, - l2_tunneling_network_id, (misc->vxlan_vni << 8)); - misc->vxlan_vni = 0; - } - - if (mask->svlan_tag || mask->cvlan_tag) { - mlx5_set(ste_eth_l2_tnl, bit_mask, first_vlan_qualifier, -1); - mask->cvlan_tag = 0; - mask->svlan_tag = 0; - } -} - -static int -dr_ste_v0_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - struct mlx5dr_match_misc *misc = &value->misc; - - dr_ste_set_tag(eth_l2_tnl, tag, dmac_47_16, spec, dmac_47_16); - dr_ste_set_tag(eth_l2_tnl, tag, dmac_15_0, spec, dmac_15_0); - dr_ste_set_tag(eth_l2_tnl, tag, first_vlan_id, spec, first_vid); - dr_ste_set_tag(eth_l2_tnl, tag, first_cfi, spec, first_cfi); - dr_ste_set_tag(eth_l2_tnl, tag, ip_fragmented, spec, frag); - dr_ste_set_tag(eth_l2_tnl, tag, first_priority, spec, first_prio); - dr_ste_set_tag(eth_l2_tnl, tag, l3_ethertype, spec, ethertype); - - if (misc->vxlan_vni) { - mlx5_set(ste_eth_l2_tnl, tag, l2_tunneling_network_id, - (misc->vxlan_vni << 8)); - misc->vxlan_vni = 0; - } - - if (spec->cvlan_tag) { - mlx5_set(ste_eth_l2_tnl, tag, first_vlan_qualifier, dr_ste_cvlan); - spec->cvlan_tag = 0; - } else if (spec->svlan_tag) { - mlx5_set(ste_eth_l2_tnl, tag, first_vlan_qualifier, dr_ste_svlan); - spec->svlan_tag = 0; - } - - if (spec->ip_version) { - if (spec->ip_version == ip_version_ipv4) { - mlx5_set(ste_eth_l2_tnl, tag, l3_type, ste_ipv4); - spec->ip_version = 0; - } else if (spec->ip_version == ip_version_ipv6) { - mlx5_set(ste_eth_l2_tnl, tag, l3_type, ste_ipv6); - spec->ip_version = 0; - } else { - return -einval; - } - } - - return 0; -} - -static void -dr_ste_v0_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_ethl2_tunneling_i; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_tnl_tag; -} - -static void -dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv4_misc, bit_mask, time_to_live, mask, ttl_hoplimit); -} - -static int -dr_ste_v0_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l3_ipv4_misc, tag, time_to_live, spec, ttl_hoplimit); - - return 0; -} - -static void -dr_ste_v0_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_misc, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv4_misc_tag; -} - -static void -dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l4, bit_mask, dst_port, mask, tcp_dport); - dr_ste_set_mask_v(eth_l4, bit_mask, src_port, mask, tcp_sport); - dr_ste_set_mask_v(eth_l4, bit_mask, dst_port, mask, udp_dport); - dr_ste_set_mask_v(eth_l4, bit_mask, src_port, mask, udp_sport); - dr_ste_set_mask_v(eth_l4, bit_mask, protocol, mask, ip_protocol); - dr_ste_set_mask_v(eth_l4, bit_mask, fragmented, mask, frag); - dr_ste_set_mask_v(eth_l4, bit_mask, dscp, mask, ip_dscp); - dr_ste_set_mask_v(eth_l4, bit_mask, ecn, mask, ip_ecn); - dr_ste_set_mask_v(eth_l4, bit_mask, ipv6_hop_limit, mask, ttl_hoplimit); - - if (mask->tcp_flags) { - dr_ste_set_tcp_flags(eth_l4, bit_mask, mask); - mask->tcp_flags = 0; - } -} - -static int -dr_ste_v0_build_eth_ipv6_l3_l4_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; - - dr_ste_set_tag(eth_l4, tag, dst_port, spec, tcp_dport); - dr_ste_set_tag(eth_l4, tag, src_port, spec, tcp_sport); - dr_ste_set_tag(eth_l4, tag, dst_port, spec, udp_dport); - dr_ste_set_tag(eth_l4, tag, src_port, spec, udp_sport); - dr_ste_set_tag(eth_l4, tag, protocol, spec, ip_protocol); - dr_ste_set_tag(eth_l4, tag, fragmented, spec, frag); - dr_ste_set_tag(eth_l4, tag, dscp, spec, ip_dscp); - dr_ste_set_tag(eth_l4, tag, ecn, spec, ip_ecn); - dr_ste_set_tag(eth_l4, tag, ipv6_hop_limit, spec, ttl_hoplimit); - - if (spec->tcp_flags) { - dr_ste_set_tcp_flags(eth_l4, tag, spec); - spec->tcp_flags = 0; - } - - return 0; -} - -static void -dr_ste_v0_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl4, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_ipv6_l3_l4_tag; -} - -static void -dr_ste_v0_build_mpls_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc2_mask = &value->misc2; - - if (inner) - dr_ste_set_mpls_mask(mpls, misc2_mask, inner, bit_mask); - else - dr_ste_set_mpls_mask(mpls, misc2_mask, outer, bit_mask); -} - -static int -dr_ste_v0_build_mpls_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc2 *misc2_mask = &value->misc2; - - if (sb->inner) - dr_ste_set_mpls_tag(mpls, misc2_mask, inner, tag); - else - dr_ste_set_mpls_tag(mpls, misc2_mask, outer, tag); - - return 0; -} - -static void -dr_ste_v0_build_mpls_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_mpls_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(mpls_first, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_mpls_tag; -} - -static void -dr_ste_v0_build_tnl_gre_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc *misc_mask = &value->misc; - - dr_ste_set_mask_v(gre, bit_mask, gre_protocol, misc_mask, gre_protocol); - dr_ste_set_mask_v(gre, bit_mask, gre_k_present, misc_mask, gre_k_present); - dr_ste_set_mask_v(gre, bit_mask, gre_key_h, misc_mask, gre_key_h); - dr_ste_set_mask_v(gre, bit_mask, gre_key_l, misc_mask, gre_key_l); - - dr_ste_set_mask_v(gre, bit_mask, gre_c_present, misc_mask, gre_c_present); - dr_ste_set_mask_v(gre, bit_mask, gre_s_present, misc_mask, gre_s_present); -} - -static int -dr_ste_v0_build_tnl_gre_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc *misc = &value->misc; - - dr_ste_set_tag(gre, tag, gre_protocol, misc, gre_protocol); - - dr_ste_set_tag(gre, tag, gre_k_present, misc, gre_k_present); - dr_ste_set_tag(gre, tag, gre_key_h, misc, gre_key_h); - dr_ste_set_tag(gre, tag, gre_key_l, misc, gre_key_l); - - dr_ste_set_tag(gre, tag, gre_c_present, misc, gre_c_present); - - dr_ste_set_tag(gre, tag, gre_s_present, misc, gre_s_present); - - return 0; -} - -static void -dr_ste_v0_build_tnl_gre_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_tnl_gre_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_gre; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_tnl_gre_tag; -} - -static void -dr_ste_v0_build_tnl_mpls_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - if (dr_ste_is_outer_mpls_over_gre_set(misc_2_mask)) { - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_label, - misc_2_mask, outer_first_mpls_over_gre_label); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_exp, - misc_2_mask, outer_first_mpls_over_gre_exp); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_s_bos, - misc_2_mask, outer_first_mpls_over_gre_s_bos); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_ttl, - misc_2_mask, outer_first_mpls_over_gre_ttl); - } else { - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_label, - misc_2_mask, outer_first_mpls_over_udp_label); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_exp, - misc_2_mask, outer_first_mpls_over_udp_exp); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_s_bos, - misc_2_mask, outer_first_mpls_over_udp_s_bos); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_ttl, - misc_2_mask, outer_first_mpls_over_udp_ttl); - } -} - -static int -dr_ste_v0_build_tnl_mpls_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - if (dr_ste_is_outer_mpls_over_gre_set(misc_2_mask)) { - dr_ste_set_tag(flex_parser_0, tag, parser_3_label, - misc_2_mask, outer_first_mpls_over_gre_label); - - dr_ste_set_tag(flex_parser_0, tag, parser_3_exp, - misc_2_mask, outer_first_mpls_over_gre_exp); - - dr_ste_set_tag(flex_parser_0, tag, parser_3_s_bos, - misc_2_mask, outer_first_mpls_over_gre_s_bos); - - dr_ste_set_tag(flex_parser_0, tag, parser_3_ttl, - misc_2_mask, outer_first_mpls_over_gre_ttl); - } else { - dr_ste_set_tag(flex_parser_0, tag, parser_3_label, - misc_2_mask, outer_first_mpls_over_udp_label); - - dr_ste_set_tag(flex_parser_0, tag, parser_3_exp, - misc_2_mask, outer_first_mpls_over_udp_exp); - - dr_ste_set_tag(flex_parser_0, tag, parser_3_s_bos, - misc_2_mask, outer_first_mpls_over_udp_s_bos); - - dr_ste_set_tag(flex_parser_0, tag, parser_3_ttl, - misc_2_mask, outer_first_mpls_over_udp_ttl); - } - return 0; -} - -static void -dr_ste_v0_build_tnl_mpls_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_tnl_mpls_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_0; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_tnl_mpls_tag; -} - -#define icmp_type_offset_first_dw 24 -#define icmp_code_offset_first_dw 16 -#define icmp_header_data_offset_second_dw 0 - -static int -dr_ste_v0_build_icmp_bit_mask(struct mlx5dr_match_param *mask, - struct mlx5dr_cmd_caps *caps, - u8 *bit_mask) -{ - struct mlx5dr_match_misc3 *misc_3_mask = &mask->misc3; - bool is_ipv4_mask = dr_mask_is_icmpv4_set(misc_3_mask); - u32 icmp_header_data_mask; - u32 icmp_type_mask; - u32 icmp_code_mask; - int dw0_location; - int dw1_location; - - if (is_ipv4_mask) { - icmp_header_data_mask = misc_3_mask->icmpv4_header_data; - icmp_type_mask = misc_3_mask->icmpv4_type; - icmp_code_mask = misc_3_mask->icmpv4_code; - dw0_location = caps->flex_parser_id_icmp_dw0; - dw1_location = caps->flex_parser_id_icmp_dw1; - } else { - icmp_header_data_mask = misc_3_mask->icmpv6_header_data; - icmp_type_mask = misc_3_mask->icmpv6_type; - icmp_code_mask = misc_3_mask->icmpv6_code; - dw0_location = caps->flex_parser_id_icmpv6_dw0; - dw1_location = caps->flex_parser_id_icmpv6_dw1; - } - - switch (dw0_location) { - case 4: - if (icmp_type_mask) { - mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_4, - (icmp_type_mask << icmp_type_offset_first_dw)); - if (is_ipv4_mask) - misc_3_mask->icmpv4_type = 0; - else - misc_3_mask->icmpv6_type = 0; - } - if (icmp_code_mask) { - u32 cur_val = mlx5_get(ste_flex_parser_1, bit_mask, - flex_parser_4); - mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_4, - cur_val | (icmp_code_mask << icmp_code_offset_first_dw)); - if (is_ipv4_mask) - misc_3_mask->icmpv4_code = 0; - else - misc_3_mask->icmpv6_code = 0; - } - break; - default: - return -einval; - } - - switch (dw1_location) { - case 5: - if (icmp_header_data_mask) { - mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_5, - (icmp_header_data_mask << icmp_header_data_offset_second_dw)); - if (is_ipv4_mask) - misc_3_mask->icmpv4_header_data = 0; - else - misc_3_mask->icmpv6_header_data = 0; - } - break; - default: - return -einval; - } - - return 0; -} - -static int -dr_ste_v0_build_icmp_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc3 *misc_3 = &value->misc3; - u32 icmp_header_data; - int dw0_location; - int dw1_location; - u32 icmp_type; - u32 icmp_code; - bool is_ipv4; - - is_ipv4 = dr_mask_is_icmpv4_set(misc_3); - if (is_ipv4) { - icmp_header_data = misc_3->icmpv4_header_data; - icmp_type = misc_3->icmpv4_type; - icmp_code = misc_3->icmpv4_code; - dw0_location = sb->caps->flex_parser_id_icmp_dw0; - dw1_location = sb->caps->flex_parser_id_icmp_dw1; - } else { - icmp_header_data = misc_3->icmpv6_header_data; - icmp_type = misc_3->icmpv6_type; - icmp_code = misc_3->icmpv6_code; - dw0_location = sb->caps->flex_parser_id_icmpv6_dw0; - dw1_location = sb->caps->flex_parser_id_icmpv6_dw1; - } - - switch (dw0_location) { - case 4: - if (icmp_type) { - mlx5_set(ste_flex_parser_1, tag, flex_parser_4, - (icmp_type << icmp_type_offset_first_dw)); - if (is_ipv4) - misc_3->icmpv4_type = 0; - else - misc_3->icmpv6_type = 0; - } - - if (icmp_code) { - u32 cur_val = mlx5_get(ste_flex_parser_1, tag, - flex_parser_4); - mlx5_set(ste_flex_parser_1, tag, flex_parser_4, - cur_val | (icmp_code << icmp_code_offset_first_dw)); - if (is_ipv4) - misc_3->icmpv4_code = 0; - else - misc_3->icmpv6_code = 0; - } - break; - default: - return -einval; - } - - switch (dw1_location) { - case 5: - if (icmp_header_data) { - mlx5_set(ste_flex_parser_1, tag, flex_parser_5, - (icmp_header_data << icmp_header_data_offset_second_dw)); - if (is_ipv4) - misc_3->icmpv4_header_data = 0; - else - misc_3->icmpv6_header_data = 0; - } - break; - default: - return -einval; - } - - return 0; -} - -static int -dr_ste_v0_build_icmp_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - int ret; - - ret = dr_ste_v0_build_icmp_bit_mask(mask, sb->caps, sb->bit_mask); - if (ret) - return ret; - - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_1; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_icmp_tag; - - return 0; -} - -static void -dr_ste_v0_build_general_purpose_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_mask_v(general_purpose, bit_mask, - general_purpose_lookup_field, misc_2_mask, - metadata_reg_a); -} - -static int -dr_ste_v0_build_general_purpose_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_tag(general_purpose, tag, general_purpose_lookup_field, - misc_2_mask, metadata_reg_a); - - return 0; -} - -static void -dr_ste_v0_build_general_purpose_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_general_purpose_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_general_purpose; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_general_purpose_tag; -} - -static void -dr_ste_v0_build_eth_l4_misc_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc3 *misc_3_mask = &value->misc3; - - if (inner) { - dr_ste_set_mask_v(eth_l4_misc, bit_mask, seq_num, misc_3_mask, - inner_tcp_seq_num); - dr_ste_set_mask_v(eth_l4_misc, bit_mask, ack_num, misc_3_mask, - inner_tcp_ack_num); - } else { - dr_ste_set_mask_v(eth_l4_misc, bit_mask, seq_num, misc_3_mask, - outer_tcp_seq_num); - dr_ste_set_mask_v(eth_l4_misc, bit_mask, ack_num, misc_3_mask, - outer_tcp_ack_num); - } -} - -static int -dr_ste_v0_build_eth_l4_misc_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc3 *misc3 = &value->misc3; - - if (sb->inner) { - dr_ste_set_tag(eth_l4_misc, tag, seq_num, misc3, inner_tcp_seq_num); - dr_ste_set_tag(eth_l4_misc, tag, ack_num, misc3, inner_tcp_ack_num); - } else { - dr_ste_set_tag(eth_l4_misc, tag, seq_num, misc3, outer_tcp_seq_num); - dr_ste_set_tag(eth_l4_misc, tag, ack_num, misc3, outer_tcp_ack_num); - } - - return 0; -} - -static void -dr_ste_v0_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_eth_l4_misc_bit_mask(mask, sb->inner, sb->bit_mask); - - sb->lu_type = dr_ste_calc_lu_type(ethl4_misc, sb->rx, sb->inner); - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_eth_l4_misc_tag; -} - -static void -dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc3 *misc_3_mask = &value->misc3; - - dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, - outer_vxlan_gpe_flags, - misc_3_mask, outer_vxlan_gpe_flags); - dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, - outer_vxlan_gpe_next_protocol, - misc_3_mask, outer_vxlan_gpe_next_protocol); - dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, - outer_vxlan_gpe_vni, - misc_3_mask, outer_vxlan_gpe_vni); -} - -static int -dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc3 *misc3 = &value->misc3; - - dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, - outer_vxlan_gpe_flags, misc3, - outer_vxlan_gpe_flags); - dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, - outer_vxlan_gpe_next_protocol, misc3, - outer_vxlan_gpe_next_protocol); - dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, - outer_vxlan_gpe_vni, misc3, - outer_vxlan_gpe_vni); - - return 0; -} - -static void -dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(mask, sb->inner, - sb->bit_mask); - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag; -} - -static void -dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc *misc_mask = &value->misc; - - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_protocol_type, - misc_mask, geneve_protocol_type); - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_oam, - misc_mask, geneve_oam); - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_opt_len, - misc_mask, geneve_opt_len); - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_vni, - misc_mask, geneve_vni); -} - -static int -dr_ste_v0_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc *misc = &value->misc; - - dr_ste_set_tag(flex_parser_tnl_geneve, tag, - geneve_protocol_type, misc, geneve_protocol_type); - dr_ste_set_tag(flex_parser_tnl_geneve, tag, - geneve_oam, misc, geneve_oam); - dr_ste_set_tag(flex_parser_tnl_geneve, tag, - geneve_opt_len, misc, geneve_opt_len); - dr_ste_set_tag(flex_parser_tnl_geneve, tag, - geneve_vni, misc, geneve_vni); - - return 0; -} - -static void -dr_ste_v0_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(mask, sb->bit_mask); - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_geneve_tag; -} - -static void -dr_ste_v0_build_register_0_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_mask_v(register_0, bit_mask, register_0_h, - misc_2_mask, metadata_reg_c_0); - dr_ste_set_mask_v(register_0, bit_mask, register_0_l, - misc_2_mask, metadata_reg_c_1); - dr_ste_set_mask_v(register_0, bit_mask, register_1_h, - misc_2_mask, metadata_reg_c_2); - dr_ste_set_mask_v(register_0, bit_mask, register_1_l, - misc_2_mask, metadata_reg_c_3); -} - -static int -dr_ste_v0_build_register_0_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc2 *misc2 = &value->misc2; - - dr_ste_set_tag(register_0, tag, register_0_h, misc2, metadata_reg_c_0); - dr_ste_set_tag(register_0, tag, register_0_l, misc2, metadata_reg_c_1); - dr_ste_set_tag(register_0, tag, register_1_h, misc2, metadata_reg_c_2); - dr_ste_set_tag(register_0, tag, register_1_l, misc2, metadata_reg_c_3); - - return 0; -} - -static void -dr_ste_v0_build_register_0_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_register_0_bit_mask(mask, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_steering_registers_0; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_register_0_tag; -} - -static void -dr_ste_v0_build_register_1_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_mask_v(register_1, bit_mask, register_2_h, - misc_2_mask, metadata_reg_c_4); - dr_ste_set_mask_v(register_1, bit_mask, register_2_l, - misc_2_mask, metadata_reg_c_5); - dr_ste_set_mask_v(register_1, bit_mask, register_3_h, - misc_2_mask, metadata_reg_c_6); - dr_ste_set_mask_v(register_1, bit_mask, register_3_l, - misc_2_mask, metadata_reg_c_7); -} - -static int -dr_ste_v0_build_register_1_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc2 *misc2 = &value->misc2; - - dr_ste_set_tag(register_1, tag, register_2_h, misc2, metadata_reg_c_4); - dr_ste_set_tag(register_1, tag, register_2_l, misc2, metadata_reg_c_5); - dr_ste_set_tag(register_1, tag, register_3_h, misc2, metadata_reg_c_6); - dr_ste_set_tag(register_1, tag, register_3_l, misc2, metadata_reg_c_7); - - return 0; -} - -static void -dr_ste_v0_build_register_1_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_register_1_bit_mask(mask, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_steering_registers_1; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_register_1_tag; -} - -static void -dr_ste_v0_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc *misc_mask = &value->misc; - - dr_ste_set_mask(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port); - dr_ste_set_mask(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn); - misc_mask->source_eswitch_owner_vhca_id = 0; -} - -static int -dr_ste_v0_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, - struct mlx5dr_ste_build *sb, - u8 *tag) -{ - struct mlx5dr_match_misc *misc = &value->misc; - struct mlx5dr_cmd_vport_cap *vport_cap; - struct mlx5dr_domain *dmn = sb->dmn; - struct mlx5dr_cmd_caps *caps; - u8 *bit_mask = sb->bit_mask; - bool source_gvmi_set; - - dr_ste_set_tag(src_gvmi_qp, tag, source_qp, misc, source_sqn); - - if (sb->vhca_id_valid) { - /* find port gvmi based on the eswitch_owner_vhca_id */ - if (misc->source_eswitch_owner_vhca_id == dmn->info.caps.gvmi) - caps = &dmn->info.caps; - else if (dmn->peer_dmn && (misc->source_eswitch_owner_vhca_id == - dmn->peer_dmn->info.caps.gvmi)) - caps = &dmn->peer_dmn->info.caps; - else - return -einval; - } else { - caps = &dmn->info.caps; - } - - vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port); - if (!vport_cap) { - mlx5dr_err(dmn, "vport 0x%x is invalid ", - misc->source_port); - return -einval; - } - - source_gvmi_set = mlx5_get(ste_src_gvmi_qp, bit_mask, source_gvmi); - if (vport_cap->vport_gvmi && source_gvmi_set) - mlx5_set(ste_src_gvmi_qp, tag, source_gvmi, vport_cap->vport_gvmi); - - misc->source_eswitch_owner_vhca_id = 0; - misc->source_port = 0; - - return 0; -} - -static void -dr_ste_v0_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb, - struct mlx5dr_match_param *mask) -{ - dr_ste_v0_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask); - - sb->lu_type = mlx5dr_ste_lu_type_src_gvmi_and_qp; - sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); - sb->ste_build_tag_func = &dr_ste_v0_build_src_gvmi_qpn_tag; -} - -static struct mlx5dr_ste_ctx ste_ctx_v0 = { - .build_eth_l2_src_dst_init = &dr_ste_v0_build_eth_l2_src_dst_init, - .build_eth_l3_ipv6_src_init = &dr_ste_v0_build_eth_l3_ipv6_src_init, - .build_eth_l3_ipv6_dst_init = &dr_ste_v0_build_eth_l3_ipv6_dst_init, - .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v0_build_eth_l3_ipv4_5_tuple_init, - .build_eth_l2_src_init = &dr_ste_v0_build_eth_l2_src_init, - .build_eth_l2_dst_init = &dr_ste_v0_build_eth_l2_dst_init, - .build_eth_l2_tnl_init = &dr_ste_v0_build_eth_l2_tnl_init, - .build_eth_l3_ipv4_misc_init = &dr_ste_v0_build_eth_l3_ipv4_misc_init, - .build_eth_ipv6_l3_l4_init = &dr_ste_v0_build_eth_ipv6_l3_l4_init, - .build_mpls_init = &dr_ste_v0_build_mpls_init, - .build_tnl_gre_init = &dr_ste_v0_build_tnl_gre_init, - .build_tnl_mpls_init = &dr_ste_v0_build_tnl_mpls_init, - .build_icmp_init = &dr_ste_v0_build_icmp_init, - .build_general_purpose_init = &dr_ste_v0_build_general_purpose_init, - .build_eth_l4_misc_init = &dr_ste_v0_build_eth_l4_misc_init, - .build_tnl_vxlan_gpe_init = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init, - .build_tnl_geneve_init = &dr_ste_v0_build_flex_parser_tnl_geneve_init, - .build_register_0_init = &dr_ste_v0_build_register_0_init, - .build_register_1_init = &dr_ste_v0_build_register_1_init, - .build_src_gvmi_qpn_init = &dr_ste_v0_build_src_gvmi_qpn_init, -}; - diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +extern struct mlx5dr_ste_ctx ste_ctx_v0; + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +// spdx-license-identifier: gpl-2.0 or linux-openib +/* copyright (c) 2020 nvidia corporation. all rights reserved. */ + +#include <linux/types.h> +#include <linux/crc32.h> +#include "dr_ste.h" + +#define dr_ste_calc_lu_type(lookup_type, rx, inner) \ + ((inner) ? mlx5dr_ste_lu_type_##lookup_type##_i : \ + (rx) ? mlx5dr_ste_lu_type_##lookup_type##_d : \ + mlx5dr_ste_lu_type_##lookup_type##_o) + +static void +dr_ste_v0_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); + + if (mask->smac_47_16 || mask->smac_15_0) { + mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_47_32, + mask->smac_47_16 >> 16); + mlx5_set(ste_eth_l2_src_dst, bit_mask, smac_31_0, + mask->smac_47_16 << 16 | mask->smac_15_0); + mask->smac_47_16 = 0; + mask->smac_15_0 = 0; + } + + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); + dr_ste_set_mask(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); + + if (mask->cvlan_tag) { + mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + } else if (mask->svlan_tag) { + mlx5_set(ste_eth_l2_src_dst, bit_mask, first_vlan_qualifier, -1); + mask->svlan_tag = 0; + } +} + +static int +dr_ste_v0_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_src_dst, tag, dmac_47_16, spec, dmac_47_16); + dr_ste_set_tag(eth_l2_src_dst, tag, dmac_15_0, spec, dmac_15_0); + + if (spec->smac_47_16 || spec->smac_15_0) { + mlx5_set(ste_eth_l2_src_dst, tag, smac_47_32, + spec->smac_47_16 >> 16); + mlx5_set(ste_eth_l2_src_dst, tag, smac_31_0, + spec->smac_47_16 << 16 | spec->smac_15_0); + spec->smac_47_16 = 0; + spec->smac_15_0 = 0; + } + + if (spec->ip_version) { + if (spec->ip_version == ip_version_ipv4) { + mlx5_set(ste_eth_l2_src_dst, tag, l3_type, ste_ipv4); + spec->ip_version = 0; + } else if (spec->ip_version == ip_version_ipv6) { + mlx5_set(ste_eth_l2_src_dst, tag, l3_type, ste_ipv6); + spec->ip_version = 0; + } else { + return -einval; + } + } + + dr_ste_set_tag(eth_l2_src_dst, tag, first_vlan_id, spec, first_vid); + dr_ste_set_tag(eth_l2_src_dst, tag, first_cfi, spec, first_cfi); + dr_ste_set_tag(eth_l2_src_dst, tag, first_priority, spec, first_prio); + + if (spec->cvlan_tag) { + mlx5_set(ste_eth_l2_src_dst, tag, first_vlan_qualifier, dr_ste_cvlan); + spec->cvlan_tag = 0; + } else if (spec->svlan_tag) { + mlx5_set(ste_eth_l2_src_dst, tag, first_vlan_qualifier, dr_ste_svlan); + spec->svlan_tag = 0; + } + return 0; +} + +static void +dr_ste_v0_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl2_src_dst, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_src_dst_tag; +} + +static void +dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_127_96, mask, dst_ip_127_96); + dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_95_64, mask, dst_ip_95_64); + dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_63_32, mask, dst_ip_63_32); + dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_31_0, mask, dst_ip_31_0); +} + +static int +dr_ste_v0_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_127_96, spec, dst_ip_127_96); + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_95_64, spec, dst_ip_95_64); + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_63_32, spec, dst_ip_63_32); + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_31_0, spec, dst_ip_31_0); + + return 0; +} + +static void +dr_ste_v0_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_dst, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv6_dst_tag; +} + +static void +dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_127_96, mask, src_ip_127_96); + dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_95_64, mask, src_ip_95_64); + dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_63_32, mask, src_ip_63_32); + dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_31_0, mask, src_ip_31_0); +} + +static int +dr_ste_v0_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_127_96, spec, src_ip_127_96); + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_95_64, spec, src_ip_95_64); + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_63_32, spec, src_ip_63_32); + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_31_0, spec, src_ip_31_0); + + return 0; +} + +static void +dr_ste_v0_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv6_src, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv6_src_tag; +} + +static void +dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(struct mlx5dr_match_param *value, + bool inner, + u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + destination_address, mask, dst_ip_31_0); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + source_address, mask, src_ip_31_0); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + destination_port, mask, tcp_dport); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + destination_port, mask, udp_dport); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + source_port, mask, tcp_sport); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + source_port, mask, udp_sport); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + protocol, mask, ip_protocol); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + fragmented, mask, frag); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + dscp, mask, ip_dscp); + dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, + ecn, mask, ip_ecn); + + if (mask->tcp_flags) { + dr_ste_set_tcp_flags(eth_l3_ipv4_5_tuple, bit_mask, mask); + mask->tcp_flags = 0; + } +} + +static int +dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, destination_address, spec, dst_ip_31_0); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, source_address, spec, src_ip_31_0); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, destination_port, spec, tcp_dport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, destination_port, spec, udp_dport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, source_port, spec, tcp_sport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, source_port, spec, udp_sport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, protocol, spec, ip_protocol); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, fragmented, spec, frag); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, dscp, spec, ip_dscp); + dr_ste_set_tag(eth_l3_ipv4_5_tuple, tag, ecn, spec, ip_ecn); + + if (spec->tcp_flags) { + dr_ste_set_tcp_flags(eth_l3_ipv4_5_tuple, tag, spec); + spec->tcp_flags = 0; + } + + return 0; +} + +static void +dr_ste_v0_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_5_tuple, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag; +} + +static void +dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc_mask = &value->misc; + + dr_ste_set_mask_v(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_mask_v(eth_l2_src, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_mask_v(eth_l2_src, bit_mask, first_priority, mask, first_prio); + dr_ste_set_mask_v(eth_l2_src, bit_mask, ip_fragmented, mask, frag); + dr_ste_set_mask_v(eth_l2_src, bit_mask, l3_ethertype, mask, ethertype); + dr_ste_set_mask(eth_l2_src, bit_mask, l3_type, mask, ip_version); + + if (mask->svlan_tag || mask->cvlan_tag) { + mlx5_set(ste_eth_l2_src, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + mask->svlan_tag = 0; + } + + if (inner) { + if (misc_mask->inner_second_cvlan_tag || + misc_mask->inner_second_svlan_tag) { + mlx5_set(ste_eth_l2_src, bit_mask, second_vlan_qualifier, -1); + misc_mask->inner_second_cvlan_tag = 0; + misc_mask->inner_second_svlan_tag = 0; + } + + dr_ste_set_mask_v(eth_l2_src, bit_mask, + second_vlan_id, misc_mask, inner_second_vid); + dr_ste_set_mask_v(eth_l2_src, bit_mask, + second_cfi, misc_mask, inner_second_cfi); + dr_ste_set_mask_v(eth_l2_src, bit_mask, + second_priority, misc_mask, inner_second_prio); + } else { + if (misc_mask->outer_second_cvlan_tag || + misc_mask->outer_second_svlan_tag) { + mlx5_set(ste_eth_l2_src, bit_mask, second_vlan_qualifier, -1); + misc_mask->outer_second_cvlan_tag = 0; + misc_mask->outer_second_svlan_tag = 0; + } + + dr_ste_set_mask_v(eth_l2_src, bit_mask, + second_vlan_id, misc_mask, outer_second_vid); + dr_ste_set_mask_v(eth_l2_src, bit_mask, + second_cfi, misc_mask, outer_second_cfi); + dr_ste_set_mask_v(eth_l2_src, bit_mask, + second_priority, misc_mask, outer_second_prio); + } +} + +static int +dr_ste_v0_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value, + bool inner, u8 *tag) +{ + struct mlx5dr_match_spec *spec = inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc_spec = &value->misc; + + dr_ste_set_tag(eth_l2_src, tag, first_vlan_id, spec, first_vid); + dr_ste_set_tag(eth_l2_src, tag, first_cfi, spec, first_cfi); + dr_ste_set_tag(eth_l2_src, tag, first_priority, spec, first_prio); + dr_ste_set_tag(eth_l2_src, tag, ip_fragmented, spec, frag); + dr_ste_set_tag(eth_l2_src, tag, l3_ethertype, spec, ethertype); + + if (spec->ip_version) { + if (spec->ip_version == ip_version_ipv4) { + mlx5_set(ste_eth_l2_src, tag, l3_type, ste_ipv4); + spec->ip_version = 0; + } else if (spec->ip_version == ip_version_ipv6) { + mlx5_set(ste_eth_l2_src, tag, l3_type, ste_ipv6); + spec->ip_version = 0; + } else { + return -einval; + } + } + + if (spec->cvlan_tag) { + mlx5_set(ste_eth_l2_src, tag, first_vlan_qualifier, dr_ste_cvlan); + spec->cvlan_tag = 0; + } else if (spec->svlan_tag) { + mlx5_set(ste_eth_l2_src, tag, first_vlan_qualifier, dr_ste_svlan); + spec->svlan_tag = 0; + } + + if (inner) { + if (misc_spec->inner_second_cvlan_tag) { + mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_cvlan); + misc_spec->inner_second_cvlan_tag = 0; + } else if (misc_spec->inner_second_svlan_tag) { + mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_svlan); + misc_spec->inner_second_svlan_tag = 0; + } + + dr_ste_set_tag(eth_l2_src, tag, second_vlan_id, misc_spec, inner_second_vid); + dr_ste_set_tag(eth_l2_src, tag, second_cfi, misc_spec, inner_second_cfi); + dr_ste_set_tag(eth_l2_src, tag, second_priority, misc_spec, inner_second_prio); + } else { + if (misc_spec->outer_second_cvlan_tag) { + mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_cvlan); + misc_spec->outer_second_cvlan_tag = 0; + } else if (misc_spec->outer_second_svlan_tag) { + mlx5_set(ste_eth_l2_src, tag, second_vlan_qualifier, dr_ste_svlan); + misc_spec->outer_second_svlan_tag = 0; + } + dr_ste_set_tag(eth_l2_src, tag, second_vlan_id, misc_spec, outer_second_vid); + dr_ste_set_tag(eth_l2_src, tag, second_cfi, misc_spec, outer_second_cfi); + dr_ste_set_tag(eth_l2_src, tag, second_priority, misc_spec, outer_second_prio); + } + + return 0; +} + +static void +dr_ste_v0_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l2_src, bit_mask, smac_47_16, mask, smac_47_16); + dr_ste_set_mask_v(eth_l2_src, bit_mask, smac_15_0, mask, smac_15_0); + + dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); +} + +static int +dr_ste_v0_build_eth_l2_src_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_src, tag, smac_47_16, spec, smac_47_16); + dr_ste_set_tag(eth_l2_src, tag, smac_15_0, spec, smac_15_0); + + return dr_ste_v0_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); +} + +static void +dr_ste_v0_build_eth_l2_src_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask); + sb->lu_type = dr_ste_calc_lu_type(ethl2_src, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_src_tag; +} + +static void +dr_ste_v0_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l2_dst, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_mask_v(eth_l2_dst, bit_mask, dmac_15_0, mask, dmac_15_0); + + dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); +} + +static int +dr_ste_v0_build_eth_l2_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_dst, tag, dmac_47_16, spec, dmac_47_16); + dr_ste_set_tag(eth_l2_dst, tag, dmac_15_0, spec, dmac_15_0); + + return dr_ste_v0_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); +} + +static void +dr_ste_v0_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl2_dst, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_dst_tag; +} + +static void +dr_ste_v0_build_eth_l2_tnl_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, dmac_15_0, mask, dmac_15_0); + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_priority, mask, first_prio); + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, ip_fragmented, mask, frag); + dr_ste_set_mask_v(eth_l2_tnl, bit_mask, l3_ethertype, mask, ethertype); + dr_ste_set_mask(eth_l2_tnl, bit_mask, l3_type, mask, ip_version); + + if (misc->vxlan_vni) { + mlx5_set(ste_eth_l2_tnl, bit_mask, + l2_tunneling_network_id, (misc->vxlan_vni << 8)); + misc->vxlan_vni = 0; + } + + if (mask->svlan_tag || mask->cvlan_tag) { + mlx5_set(ste_eth_l2_tnl, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + mask->svlan_tag = 0; + } +} + +static int +dr_ste_v0_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(eth_l2_tnl, tag, dmac_47_16, spec, dmac_47_16); + dr_ste_set_tag(eth_l2_tnl, tag, dmac_15_0, spec, dmac_15_0); + dr_ste_set_tag(eth_l2_tnl, tag, first_vlan_id, spec, first_vid); + dr_ste_set_tag(eth_l2_tnl, tag, first_cfi, spec, first_cfi); + dr_ste_set_tag(eth_l2_tnl, tag, ip_fragmented, spec, frag); + dr_ste_set_tag(eth_l2_tnl, tag, first_priority, spec, first_prio); + dr_ste_set_tag(eth_l2_tnl, tag, l3_ethertype, spec, ethertype); + + if (misc->vxlan_vni) { + mlx5_set(ste_eth_l2_tnl, tag, l2_tunneling_network_id, + (misc->vxlan_vni << 8)); + misc->vxlan_vni = 0; + } + + if (spec->cvlan_tag) { + mlx5_set(ste_eth_l2_tnl, tag, first_vlan_qualifier, dr_ste_cvlan); + spec->cvlan_tag = 0; + } else if (spec->svlan_tag) { + mlx5_set(ste_eth_l2_tnl, tag, first_vlan_qualifier, dr_ste_svlan); + spec->svlan_tag = 0; + } + + if (spec->ip_version) { + if (spec->ip_version == ip_version_ipv4) { + mlx5_set(ste_eth_l2_tnl, tag, l3_type, ste_ipv4); + spec->ip_version = 0; + } else if (spec->ip_version == ip_version_ipv6) { + mlx5_set(ste_eth_l2_tnl, tag, l3_type, ste_ipv6); + spec->ip_version = 0; + } else { + return -einval; + } + } + + return 0; +} + +static void +dr_ste_v0_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_ethl2_tunneling_i; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l2_tnl_tag; +} + +static void +dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l3_ipv4_misc, bit_mask, time_to_live, mask, ttl_hoplimit); +} + +static int +dr_ste_v0_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv4_misc, tag, time_to_live, spec, ttl_hoplimit); + + return 0; +} + +static void +dr_ste_v0_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl3_ipv4_misc, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l3_ipv4_misc_tag; +} + +static void +dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_mask_v(eth_l4, bit_mask, dst_port, mask, tcp_dport); + dr_ste_set_mask_v(eth_l4, bit_mask, src_port, mask, tcp_sport); + dr_ste_set_mask_v(eth_l4, bit_mask, dst_port, mask, udp_dport); + dr_ste_set_mask_v(eth_l4, bit_mask, src_port, mask, udp_sport); + dr_ste_set_mask_v(eth_l4, bit_mask, protocol, mask, ip_protocol); + dr_ste_set_mask_v(eth_l4, bit_mask, fragmented, mask, frag); + dr_ste_set_mask_v(eth_l4, bit_mask, dscp, mask, ip_dscp); + dr_ste_set_mask_v(eth_l4, bit_mask, ecn, mask, ip_ecn); + dr_ste_set_mask_v(eth_l4, bit_mask, ipv6_hop_limit, mask, ttl_hoplimit); + + if (mask->tcp_flags) { + dr_ste_set_tcp_flags(eth_l4, bit_mask, mask); + mask->tcp_flags = 0; + } +} + +static int +dr_ste_v0_build_eth_ipv6_l3_l4_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l4, tag, dst_port, spec, tcp_dport); + dr_ste_set_tag(eth_l4, tag, src_port, spec, tcp_sport); + dr_ste_set_tag(eth_l4, tag, dst_port, spec, udp_dport); + dr_ste_set_tag(eth_l4, tag, src_port, spec, udp_sport); + dr_ste_set_tag(eth_l4, tag, protocol, spec, ip_protocol); + dr_ste_set_tag(eth_l4, tag, fragmented, spec, frag); + dr_ste_set_tag(eth_l4, tag, dscp, spec, ip_dscp); + dr_ste_set_tag(eth_l4, tag, ecn, spec, ip_ecn); + dr_ste_set_tag(eth_l4, tag, ipv6_hop_limit, spec, ttl_hoplimit); + + if (spec->tcp_flags) { + dr_ste_set_tcp_flags(eth_l4, tag, spec); + spec->tcp_flags = 0; + } + + return 0; +} + +static void +dr_ste_v0_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl4, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_ipv6_l3_l4_tag; +} + +static void +dr_ste_v0_build_mpls_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_misc2 *misc2_mask = &value->misc2; + + if (inner) + dr_ste_set_mpls_mask(mpls, misc2_mask, inner, bit_mask); + else + dr_ste_set_mpls_mask(mpls, misc2_mask, outer, bit_mask); +} + +static int +dr_ste_v0_build_mpls_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2_mask = &value->misc2; + + if (sb->inner) + dr_ste_set_mpls_tag(mpls, misc2_mask, inner, tag); + else + dr_ste_set_mpls_tag(mpls, misc2_mask, outer, tag); + + return 0; +} + +static void +dr_ste_v0_build_mpls_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_mpls_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(mpls_first, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_mpls_tag; +} + +static void +dr_ste_v0_build_tnl_gre_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_misc *misc_mask = &value->misc; + + dr_ste_set_mask_v(gre, bit_mask, gre_protocol, misc_mask, gre_protocol); + dr_ste_set_mask_v(gre, bit_mask, gre_k_present, misc_mask, gre_k_present); + dr_ste_set_mask_v(gre, bit_mask, gre_key_h, misc_mask, gre_key_h); + dr_ste_set_mask_v(gre, bit_mask, gre_key_l, misc_mask, gre_key_l); + + dr_ste_set_mask_v(gre, bit_mask, gre_c_present, misc_mask, gre_c_present); + dr_ste_set_mask_v(gre, bit_mask, gre_s_present, misc_mask, gre_s_present); +} + +static int +dr_ste_v0_build_tnl_gre_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(gre, tag, gre_protocol, misc, gre_protocol); + + dr_ste_set_tag(gre, tag, gre_k_present, misc, gre_k_present); + dr_ste_set_tag(gre, tag, gre_key_h, misc, gre_key_h); + dr_ste_set_tag(gre, tag, gre_key_l, misc, gre_key_l); + + dr_ste_set_tag(gre, tag, gre_c_present, misc, gre_c_present); + + dr_ste_set_tag(gre, tag, gre_s_present, misc, gre_s_present); + + return 0; +} + +static void +dr_ste_v0_build_tnl_gre_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_tnl_gre_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_gre; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_tnl_gre_tag; +} + +static void +dr_ste_v0_build_tnl_mpls_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + + if (dr_ste_is_outer_mpls_over_gre_set(misc_2_mask)) { + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_label, + misc_2_mask, outer_first_mpls_over_gre_label); + + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_exp, + misc_2_mask, outer_first_mpls_over_gre_exp); + + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_s_bos, + misc_2_mask, outer_first_mpls_over_gre_s_bos); + + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_ttl, + misc_2_mask, outer_first_mpls_over_gre_ttl); + } else { + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_label, + misc_2_mask, outer_first_mpls_over_udp_label); + + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_exp, + misc_2_mask, outer_first_mpls_over_udp_exp); + + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_s_bos, + misc_2_mask, outer_first_mpls_over_udp_s_bos); + + dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_ttl, + misc_2_mask, outer_first_mpls_over_udp_ttl); + } +} + +static int +dr_ste_v0_build_tnl_mpls_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + + if (dr_ste_is_outer_mpls_over_gre_set(misc_2_mask)) { + dr_ste_set_tag(flex_parser_0, tag, parser_3_label, + misc_2_mask, outer_first_mpls_over_gre_label); + + dr_ste_set_tag(flex_parser_0, tag, parser_3_exp, + misc_2_mask, outer_first_mpls_over_gre_exp); + + dr_ste_set_tag(flex_parser_0, tag, parser_3_s_bos, + misc_2_mask, outer_first_mpls_over_gre_s_bos); + + dr_ste_set_tag(flex_parser_0, tag, parser_3_ttl, + misc_2_mask, outer_first_mpls_over_gre_ttl); + } else { + dr_ste_set_tag(flex_parser_0, tag, parser_3_label, + misc_2_mask, outer_first_mpls_over_udp_label); + + dr_ste_set_tag(flex_parser_0, tag, parser_3_exp, + misc_2_mask, outer_first_mpls_over_udp_exp); + + dr_ste_set_tag(flex_parser_0, tag, parser_3_s_bos, + misc_2_mask, outer_first_mpls_over_udp_s_bos); + + dr_ste_set_tag(flex_parser_0, tag, parser_3_ttl, + misc_2_mask, outer_first_mpls_over_udp_ttl); + } + return 0; +} + +static void +dr_ste_v0_build_tnl_mpls_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_tnl_mpls_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_0; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_tnl_mpls_tag; +} + +#define icmp_type_offset_first_dw 24 +#define icmp_code_offset_first_dw 16 +#define icmp_header_data_offset_second_dw 0 + +static int +dr_ste_v0_build_icmp_bit_mask(struct mlx5dr_match_param *mask, + struct mlx5dr_cmd_caps *caps, + u8 *bit_mask) +{ + struct mlx5dr_match_misc3 *misc_3_mask = &mask->misc3; + bool is_ipv4_mask = dr_mask_is_icmpv4_set(misc_3_mask); + u32 icmp_header_data_mask; + u32 icmp_type_mask; + u32 icmp_code_mask; + int dw0_location; + int dw1_location; + + if (is_ipv4_mask) { + icmp_header_data_mask = misc_3_mask->icmpv4_header_data; + icmp_type_mask = misc_3_mask->icmpv4_type; + icmp_code_mask = misc_3_mask->icmpv4_code; + dw0_location = caps->flex_parser_id_icmp_dw0; + dw1_location = caps->flex_parser_id_icmp_dw1; + } else { + icmp_header_data_mask = misc_3_mask->icmpv6_header_data; + icmp_type_mask = misc_3_mask->icmpv6_type; + icmp_code_mask = misc_3_mask->icmpv6_code; + dw0_location = caps->flex_parser_id_icmpv6_dw0; + dw1_location = caps->flex_parser_id_icmpv6_dw1; + } + + switch (dw0_location) { + case 4: + if (icmp_type_mask) { + mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_4, + (icmp_type_mask << icmp_type_offset_first_dw)); + if (is_ipv4_mask) + misc_3_mask->icmpv4_type = 0; + else + misc_3_mask->icmpv6_type = 0; + } + if (icmp_code_mask) { + u32 cur_val = mlx5_get(ste_flex_parser_1, bit_mask, + flex_parser_4); + mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_4, + cur_val | (icmp_code_mask << icmp_code_offset_first_dw)); + if (is_ipv4_mask) + misc_3_mask->icmpv4_code = 0; + else + misc_3_mask->icmpv6_code = 0; + } + break; + default: + return -einval; + } + + switch (dw1_location) { + case 5: + if (icmp_header_data_mask) { + mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_5, + (icmp_header_data_mask << icmp_header_data_offset_second_dw)); + if (is_ipv4_mask) + misc_3_mask->icmpv4_header_data = 0; + else + misc_3_mask->icmpv6_header_data = 0; + } + break; + default: + return -einval; + } + + return 0; +} + +static int +dr_ste_v0_build_icmp_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc3 *misc_3 = &value->misc3; + u32 icmp_header_data; + int dw0_location; + int dw1_location; + u32 icmp_type; + u32 icmp_code; + bool is_ipv4; + + is_ipv4 = dr_mask_is_icmpv4_set(misc_3); + if (is_ipv4) { + icmp_header_data = misc_3->icmpv4_header_data; + icmp_type = misc_3->icmpv4_type; + icmp_code = misc_3->icmpv4_code; + dw0_location = sb->caps->flex_parser_id_icmp_dw0; + dw1_location = sb->caps->flex_parser_id_icmp_dw1; + } else { + icmp_header_data = misc_3->icmpv6_header_data; + icmp_type = misc_3->icmpv6_type; + icmp_code = misc_3->icmpv6_code; + dw0_location = sb->caps->flex_parser_id_icmpv6_dw0; + dw1_location = sb->caps->flex_parser_id_icmpv6_dw1; + } + + switch (dw0_location) { + case 4: + if (icmp_type) { + mlx5_set(ste_flex_parser_1, tag, flex_parser_4, + (icmp_type << icmp_type_offset_first_dw)); + if (is_ipv4) + misc_3->icmpv4_type = 0; + else + misc_3->icmpv6_type = 0; + } + + if (icmp_code) { + u32 cur_val = mlx5_get(ste_flex_parser_1, tag, + flex_parser_4); + mlx5_set(ste_flex_parser_1, tag, flex_parser_4, + cur_val | (icmp_code << icmp_code_offset_first_dw)); + if (is_ipv4) + misc_3->icmpv4_code = 0; + else + misc_3->icmpv6_code = 0; + } + break; + default: + return -einval; + } + + switch (dw1_location) { + case 5: + if (icmp_header_data) { + mlx5_set(ste_flex_parser_1, tag, flex_parser_5, + (icmp_header_data << icmp_header_data_offset_second_dw)); + if (is_ipv4) + misc_3->icmpv4_header_data = 0; + else + misc_3->icmpv6_header_data = 0; + } + break; + default: + return -einval; + } + + return 0; +} + +static int +dr_ste_v0_build_icmp_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + int ret; + + ret = dr_ste_v0_build_icmp_bit_mask(mask, sb->caps, sb->bit_mask); + if (ret) + return ret; + + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_1; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_icmp_tag; + + return 0; +} + +static void +dr_ste_v0_build_general_purpose_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + + dr_ste_set_mask_v(general_purpose, bit_mask, + general_purpose_lookup_field, misc_2_mask, + metadata_reg_a); +} + +static int +dr_ste_v0_build_general_purpose_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + + dr_ste_set_tag(general_purpose, tag, general_purpose_lookup_field, + misc_2_mask, metadata_reg_a); + + return 0; +} + +static void +dr_ste_v0_build_general_purpose_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_general_purpose_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_general_purpose; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_general_purpose_tag; +} + +static void +dr_ste_v0_build_eth_l4_misc_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_misc3 *misc_3_mask = &value->misc3; + + if (inner) { + dr_ste_set_mask_v(eth_l4_misc, bit_mask, seq_num, misc_3_mask, + inner_tcp_seq_num); + dr_ste_set_mask_v(eth_l4_misc, bit_mask, ack_num, misc_3_mask, + inner_tcp_ack_num); + } else { + dr_ste_set_mask_v(eth_l4_misc, bit_mask, seq_num, misc_3_mask, + outer_tcp_seq_num); + dr_ste_set_mask_v(eth_l4_misc, bit_mask, ack_num, misc_3_mask, + outer_tcp_ack_num); + } +} + +static int +dr_ste_v0_build_eth_l4_misc_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc3 *misc3 = &value->misc3; + + if (sb->inner) { + dr_ste_set_tag(eth_l4_misc, tag, seq_num, misc3, inner_tcp_seq_num); + dr_ste_set_tag(eth_l4_misc, tag, ack_num, misc3, inner_tcp_ack_num); + } else { + dr_ste_set_tag(eth_l4_misc, tag, seq_num, misc3, outer_tcp_seq_num); + dr_ste_set_tag(eth_l4_misc, tag, ack_num, misc3, outer_tcp_ack_num); + } + + return 0; +} + +static void +dr_ste_v0_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_eth_l4_misc_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_lu_type(ethl4_misc, sb->rx, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_eth_l4_misc_tag; +} + +static void +dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_misc3 *misc_3_mask = &value->misc3; + + dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, + outer_vxlan_gpe_flags, + misc_3_mask, outer_vxlan_gpe_flags); + dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, + outer_vxlan_gpe_next_protocol, + misc_3_mask, outer_vxlan_gpe_next_protocol); + dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, + outer_vxlan_gpe_vni, + misc_3_mask, outer_vxlan_gpe_vni); +} + +static int +dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc3 *misc3 = &value->misc3; + + dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, + outer_vxlan_gpe_flags, misc3, + outer_vxlan_gpe_flags); + dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, + outer_vxlan_gpe_next_protocol, misc3, + outer_vxlan_gpe_next_protocol); + dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, + outer_vxlan_gpe_vni, misc3, + outer_vxlan_gpe_vni); + + return 0; +} + +static void +dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(mask, sb->inner, + sb->bit_mask); + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag; +} + +static void +dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) +{ + struct mlx5dr_match_misc *misc_mask = &value->misc; + + dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, + geneve_protocol_type, + misc_mask, geneve_protocol_type); + dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, + geneve_oam, + misc_mask, geneve_oam); + dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, + geneve_opt_len, + misc_mask, geneve_opt_len); + dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, + geneve_vni, + misc_mask, geneve_vni); +} + +static int +dr_ste_v0_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_protocol_type, misc, geneve_protocol_type); + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_oam, misc, geneve_oam); + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_opt_len, misc, geneve_opt_len); + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_vni, misc, geneve_vni); + + return 0; +} + +static void +dr_ste_v0_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(mask, sb->bit_mask); + sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_flex_parser_tnl_geneve_tag; +} + +static void +dr_ste_v0_build_register_0_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) +{ + struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + + dr_ste_set_mask_v(register_0, bit_mask, register_0_h, + misc_2_mask, metadata_reg_c_0); + dr_ste_set_mask_v(register_0, bit_mask, register_0_l, + misc_2_mask, metadata_reg_c_1); + dr_ste_set_mask_v(register_0, bit_mask, register_1_h, + misc_2_mask, metadata_reg_c_2); + dr_ste_set_mask_v(register_0, bit_mask, register_1_l, + misc_2_mask, metadata_reg_c_3); +} + +static int +dr_ste_v0_build_register_0_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + dr_ste_set_tag(register_0, tag, register_0_h, misc2, metadata_reg_c_0); + dr_ste_set_tag(register_0, tag, register_0_l, misc2, metadata_reg_c_1); + dr_ste_set_tag(register_0, tag, register_1_h, misc2, metadata_reg_c_2); + dr_ste_set_tag(register_0, tag, register_1_l, misc2, metadata_reg_c_3); + + return 0; +} + +static void +dr_ste_v0_build_register_0_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_register_0_bit_mask(mask, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_steering_registers_0; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_register_0_tag; +} + +static void +dr_ste_v0_build_register_1_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) +{ + struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + + dr_ste_set_mask_v(register_1, bit_mask, register_2_h, + misc_2_mask, metadata_reg_c_4); + dr_ste_set_mask_v(register_1, bit_mask, register_2_l, + misc_2_mask, metadata_reg_c_5); + dr_ste_set_mask_v(register_1, bit_mask, register_3_h, + misc_2_mask, metadata_reg_c_6); + dr_ste_set_mask_v(register_1, bit_mask, register_3_l, + misc_2_mask, metadata_reg_c_7); +} + +static int +dr_ste_v0_build_register_1_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + dr_ste_set_tag(register_1, tag, register_2_h, misc2, metadata_reg_c_4); + dr_ste_set_tag(register_1, tag, register_2_l, misc2, metadata_reg_c_5); + dr_ste_set_tag(register_1, tag, register_3_h, misc2, metadata_reg_c_6); + dr_ste_set_tag(register_1, tag, register_3_l, misc2, metadata_reg_c_7); + + return 0; +} + +static void +dr_ste_v0_build_register_1_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_register_1_bit_mask(mask, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_steering_registers_1; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_register_1_tag; +} + +static void +dr_ste_v0_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) +{ + struct mlx5dr_match_misc *misc_mask = &value->misc; + + dr_ste_set_mask(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port); + dr_ste_set_mask(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn); + misc_mask->source_eswitch_owner_vhca_id = 0; +} + +static int +dr_ste_v0_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc *misc = &value->misc; + struct mlx5dr_cmd_vport_cap *vport_cap; + struct mlx5dr_domain *dmn = sb->dmn; + struct mlx5dr_cmd_caps *caps; + u8 *bit_mask = sb->bit_mask; + bool source_gvmi_set; + + dr_ste_set_tag(src_gvmi_qp, tag, source_qp, misc, source_sqn); + + if (sb->vhca_id_valid) { + /* find port gvmi based on the eswitch_owner_vhca_id */ + if (misc->source_eswitch_owner_vhca_id == dmn->info.caps.gvmi) + caps = &dmn->info.caps; + else if (dmn->peer_dmn && (misc->source_eswitch_owner_vhca_id == + dmn->peer_dmn->info.caps.gvmi)) + caps = &dmn->peer_dmn->info.caps; + else + return -einval; + } else { + caps = &dmn->info.caps; + } + + vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port); + if (!vport_cap) { + mlx5dr_err(dmn, "vport 0x%x is invalid ", + misc->source_port); + return -einval; + } + + source_gvmi_set = mlx5_get(ste_src_gvmi_qp, bit_mask, source_gvmi); + if (vport_cap->vport_gvmi && source_gvmi_set) + mlx5_set(ste_src_gvmi_qp, tag, source_gvmi, vport_cap->vport_gvmi); + + misc->source_eswitch_owner_vhca_id = 0; + misc->source_port = 0; + + return 0; +} + +static void +dr_ste_v0_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v0_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask); + + sb->lu_type = mlx5dr_ste_lu_type_src_gvmi_and_qp; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v0_build_src_gvmi_qpn_tag; +} + +struct mlx5dr_ste_ctx ste_ctx_v0 = { + .build_eth_l2_src_dst_init = &dr_ste_v0_build_eth_l2_src_dst_init, + .build_eth_l3_ipv6_src_init = &dr_ste_v0_build_eth_l3_ipv6_src_init, + .build_eth_l3_ipv6_dst_init = &dr_ste_v0_build_eth_l3_ipv6_dst_init, + .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v0_build_eth_l3_ipv4_5_tuple_init, + .build_eth_l2_src_init = &dr_ste_v0_build_eth_l2_src_init, + .build_eth_l2_dst_init = &dr_ste_v0_build_eth_l2_dst_init, + .build_eth_l2_tnl_init = &dr_ste_v0_build_eth_l2_tnl_init, + .build_eth_l3_ipv4_misc_init = &dr_ste_v0_build_eth_l3_ipv4_misc_init, + .build_eth_ipv6_l3_l4_init = &dr_ste_v0_build_eth_ipv6_l3_l4_init, + .build_mpls_init = &dr_ste_v0_build_mpls_init, + .build_tnl_gre_init = &dr_ste_v0_build_tnl_gre_init, + .build_tnl_mpls_init = &dr_ste_v0_build_tnl_mpls_init, + .build_icmp_init = &dr_ste_v0_build_icmp_init, + .build_general_purpose_init = &dr_ste_v0_build_general_purpose_init, + .build_eth_l4_misc_init = &dr_ste_v0_build_eth_l4_misc_init, + .build_tnl_vxlan_gpe_init = &dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_init, + .build_tnl_geneve_init = &dr_ste_v0_build_flex_parser_tnl_geneve_init, + .build_register_0_init = &dr_ste_v0_build_register_0_init, + .build_register_1_init = &dr_ste_v0_build_register_1_init, + .build_src_gvmi_qpn_init = &dr_ste_v0_build_src_gvmi_qpn_init, +};
|
Networking
|
d65e841de80375372f9842ed71756d3b90d96dc4
|
yevgeny kliteynik
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drivers
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net
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core, ethernet, mellanox, mlx5, steering
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net/mlx5: dr, remove unused macro definition from dr_ste
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signed-off-by: yevgeny kliteynik <kliteyn@nvidia.com> reviewed-by: saeed mahameed <saeedm@nvidia.com> signed-off-by: saeed mahameed <saeedm@nvidia.com>
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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introduce some refactoring to sw steering to support different formats of different hardware
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['mlx5/mlx5e ']
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['c']
| 1
| 0
| 2
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -#define dr_ste_crc_poly 0xedb88320l -
|
Networking
|
b7f7ad1846f699c757a9fad915de97cf9a4008af
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, fix stev0 source_eswitch_owner_vhca_id support
|
check vport_cap only if match on source gvmi is required.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 14
| 11
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c + + misc->source_eswitch_owner_vhca_id = 0; - vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port); - if (!vport_cap) { - mlx5dr_err(dmn, "vport 0x%x is invalid ", - misc->source_port); - return -einval; - } - - if (vport_cap->vport_gvmi && source_gvmi_set) - mlx5_set(ste_src_gvmi_qp, tag, source_gvmi, vport_cap->vport_gvmi); + if (source_gvmi_set) { + vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port); + if (!vport_cap) { + mlx5dr_err(dmn, "vport 0x%x is invalid ", + misc->source_port); + return -einval; + } - misc->source_eswitch_owner_vhca_id = 0; - misc->source_port = 0; + if (vport_cap->vport_gvmi) + mlx5_set(ste_src_gvmi_qp, tag, source_gvmi, vport_cap->vport_gvmi); + + misc->source_port = 0; + }
|
Networking
|
7863c912e8a07b9431fd6d9a9e371da47cb0f308
|
yevgeny kliteynik alex vesker valex nvidia com saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, merge similar dr ste set macros
|
merge dr_ste_ste macros for better code reuse, the macro dr_ste_set_mask_v and dr_ste_set_tag are merged to avoid tag and bit_mask function creation which are usually the same.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 84
| 415
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h -/* set to ste spec->s_fname to tag->t_fname */ +/* set to ste spec->s_fname to tag->t_fname set spec->s_fname as used */ -/* set to ste -1 to bit_mask->bm_fname and set spec->s_fname as used */ -#define dr_ste_set_mask(lookup_type, bit_mask, bm_fname, spec, s_fname) \ - dr_ste_set_val(lookup_type, bit_mask, bm_fname, spec, s_fname, -1) - -/* set to ste spec->s_fname to bit_mask->bm_fname and set spec->s_fname as used */ -#define dr_ste_set_mask_v(lookup_type, bit_mask, bm_fname, spec, s_fname) \ - dr_ste_set_val(lookup_type, bit_mask, bm_fname, spec, s_fname, (spec)->s_fname) +/* set to ste -1 to tag->t_fname and set spec->s_fname as used */ +#define dr_ste_set_ones(lookup_type, tag, t_fname, spec, s_fname) \ + dr_ste_set_val(lookup_type, tag, t_fname, spec, s_fname, -1) -#define dr_ste_set_mpls_mask(lookup_type, mask, in_out, bit_mask) do { \ - dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_label, mask, \ - in_out##_first_mpls_label);\ - dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_s_bos, mask, \ - in_out##_first_mpls_s_bos); \ - dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_exp, mask, \ - in_out##_first_mpls_exp); \ - dr_ste_set_mask_v(lookup_type, bit_mask, mpls0_ttl, mask, \ - in_out##_first_mpls_ttl); \ -} while (0) - -#define dr_ste_set_mpls_tag(lookup_type, mask, in_out, tag) do { \ - dr_ste_set_tag(lookup_type, tag, mpls0_label, mask, \ +#define dr_ste_set_mpls(lookup_type, mask, in_out, tag) do { \ + struct mlx5dr_match_misc2 *_mask = mask; \ + u8 *_tag = tag; \ + dr_ste_set_tag(lookup_type, _tag, mpls0_label, _mask, \ - dr_ste_set_tag(lookup_type, tag, mpls0_s_bos, mask, \ + dr_ste_set_tag(lookup_type, _tag, mpls0_s_bos, _mask, \ - dr_ste_set_tag(lookup_type, tag, mpls0_exp, mask, \ + dr_ste_set_tag(lookup_type, _tag, mpls0_exp, _mask, \ - dr_ste_set_tag(lookup_type, tag, mpls0_ttl, mask, \ + dr_ste_set_tag(lookup_type, _tag, mpls0_ttl, _mask, \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); + dr_ste_set_tag(eth_l2_src_dst, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_tag(eth_l2_src_dst, bit_mask, dmac_15_0, mask, dmac_15_0); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); + dr_ste_set_tag(eth_l2_src_dst, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_tag(eth_l2_src_dst, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_tag(eth_l2_src_dst, bit_mask, first_priority, mask, first_prio); + dr_ste_set_ones(eth_l2_src_dst, bit_mask, l3_type, mask, ip_version); -static void -dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_127_96, mask, dst_ip_127_96); - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_95_64, mask, dst_ip_95_64); - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_63_32, mask, dst_ip_63_32); - dr_ste_set_mask_v(eth_l3_ipv6_dst, bit_mask, dst_ip_31_0, mask, dst_ip_31_0); -} - - dr_ste_v0_build_eth_l3_ipv6_dst_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_l3_ipv6_dst_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_127_96, mask, src_ip_127_96); - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_95_64, mask, src_ip_95_64); - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_63_32, mask, src_ip_63_32); - dr_ste_set_mask_v(eth_l3_ipv6_src, bit_mask, src_ip_31_0, mask, src_ip_31_0); -} - - dr_ste_v0_build_eth_l3_ipv6_src_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_l3_ipv6_src_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(struct mlx5dr_match_param *value, - bool inner, - u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - destination_address, mask, dst_ip_31_0); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - source_address, mask, src_ip_31_0); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - destination_port, mask, tcp_dport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - destination_port, mask, udp_dport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - source_port, mask, tcp_sport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - source_port, mask, udp_sport); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - protocol, mask, ip_protocol); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - fragmented, mask, frag); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - dscp, mask, ip_dscp); - dr_ste_set_mask_v(eth_l3_ipv4_5_tuple, bit_mask, - ecn, mask, ip_ecn); - - if (mask->tcp_flags) { - dr_ste_set_tcp_flags(eth_l3_ipv4_5_tuple, bit_mask, mask); - mask->tcp_flags = 0; - } -} - - dr_ste_v0_build_eth_l3_ipv4_5_tuple_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_l3_ipv4_5_tuple_tag(mask, sb, sb->bit_mask); - dr_ste_set_mask_v(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_src, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_src, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask_v(eth_l2_src, bit_mask, ip_fragmented, mask, frag); - dr_ste_set_mask_v(eth_l2_src, bit_mask, l3_ethertype, mask, ethertype); - dr_ste_set_mask(eth_l2_src, bit_mask, l3_type, mask, ip_version); + dr_ste_set_tag(eth_l2_src, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_tag(eth_l2_src, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_tag(eth_l2_src, bit_mask, first_priority, mask, first_prio); + dr_ste_set_tag(eth_l2_src, bit_mask, ip_fragmented, mask, frag); + dr_ste_set_tag(eth_l2_src, bit_mask, l3_ethertype, mask, ethertype); + dr_ste_set_ones(eth_l2_src, bit_mask, l3_type, mask, ip_version); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_vlan_id, misc_mask, inner_second_vid); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_cfi, misc_mask, inner_second_cfi); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_priority, misc_mask, inner_second_prio); + dr_ste_set_tag(eth_l2_src, bit_mask, + second_vlan_id, misc_mask, inner_second_vid); + dr_ste_set_tag(eth_l2_src, bit_mask, + second_cfi, misc_mask, inner_second_cfi); + dr_ste_set_tag(eth_l2_src, bit_mask, + second_priority, misc_mask, inner_second_prio); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_vlan_id, misc_mask, outer_second_vid); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_cfi, misc_mask, outer_second_cfi); - dr_ste_set_mask_v(eth_l2_src, bit_mask, - second_priority, misc_mask, outer_second_prio); + dr_ste_set_tag(eth_l2_src, bit_mask, + second_vlan_id, misc_mask, outer_second_vid); + dr_ste_set_tag(eth_l2_src, bit_mask, + second_cfi, misc_mask, outer_second_cfi); + dr_ste_set_tag(eth_l2_src, bit_mask, + second_priority, misc_mask, outer_second_prio); - dr_ste_set_mask_v(eth_l2_src, bit_mask, smac_47_16, mask, smac_47_16); - dr_ste_set_mask_v(eth_l2_src, bit_mask, smac_15_0, mask, smac_15_0); + dr_ste_set_tag(eth_l2_src, bit_mask, smac_47_16, mask, smac_47_16); + dr_ste_set_tag(eth_l2_src, bit_mask, smac_15_0, mask, smac_15_0); - bool inner, u8 *bit_mask) + struct mlx5dr_ste_build *sb, + u8 *bit_mask) - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + struct mlx5dr_match_spec *mask = sb->inner ? &value->inner : &value->outer; - dr_ste_set_mask_v(eth_l2_dst, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_dst, bit_mask, dmac_15_0, mask, dmac_15_0); + dr_ste_set_tag(eth_l2_dst, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_tag(eth_l2_dst, bit_mask, dmac_15_0, mask, dmac_15_0); - dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); + dr_ste_v0_build_eth_l2_src_or_dst_bit_mask(value, sb->inner, bit_mask); - dr_ste_v0_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_l2_dst_bit_mask(mask, sb, sb->bit_mask); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, dmac_47_16, mask, dmac_47_16); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, dmac_15_0, mask, dmac_15_0); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_cfi, mask, first_cfi); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, first_priority, mask, first_prio); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, ip_fragmented, mask, frag); - dr_ste_set_mask_v(eth_l2_tnl, bit_mask, l3_ethertype, mask, ethertype); - dr_ste_set_mask(eth_l2_tnl, bit_mask, l3_type, mask, ip_version); + dr_ste_set_tag(eth_l2_tnl, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_tag(eth_l2_tnl, bit_mask, dmac_15_0, mask, dmac_15_0); + dr_ste_set_tag(eth_l2_tnl, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_tag(eth_l2_tnl, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_tag(eth_l2_tnl, bit_mask, first_priority, mask, first_prio); + dr_ste_set_tag(eth_l2_tnl, bit_mask, ip_fragmented, mask, frag); + dr_ste_set_tag(eth_l2_tnl, bit_mask, l3_ethertype, mask, ethertype); + dr_ste_set_ones(eth_l2_tnl, bit_mask, l3_type, mask, ip_version); -static void -dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l3_ipv4_misc, bit_mask, time_to_live, mask, ttl_hoplimit); -} - - dr_ste_v0_build_eth_l3_ipv4_misc_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_l3_ipv4_misc_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; - - dr_ste_set_mask_v(eth_l4, bit_mask, dst_port, mask, tcp_dport); - dr_ste_set_mask_v(eth_l4, bit_mask, src_port, mask, tcp_sport); - dr_ste_set_mask_v(eth_l4, bit_mask, dst_port, mask, udp_dport); - dr_ste_set_mask_v(eth_l4, bit_mask, src_port, mask, udp_sport); - dr_ste_set_mask_v(eth_l4, bit_mask, protocol, mask, ip_protocol); - dr_ste_set_mask_v(eth_l4, bit_mask, fragmented, mask, frag); - dr_ste_set_mask_v(eth_l4, bit_mask, dscp, mask, ip_dscp); - dr_ste_set_mask_v(eth_l4, bit_mask, ecn, mask, ip_ecn); - dr_ste_set_mask_v(eth_l4, bit_mask, ipv6_hop_limit, mask, ttl_hoplimit); - - if (mask->tcp_flags) { - dr_ste_set_tcp_flags(eth_l4, bit_mask, mask); - mask->tcp_flags = 0; - } -} - - dr_ste_v0_build_eth_ipv6_l3_l4_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_ipv6_l3_l4_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_mpls_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc2_mask = &value->misc2; - - if (inner) - dr_ste_set_mpls_mask(mpls, misc2_mask, inner, bit_mask); - else - dr_ste_set_mpls_mask(mpls, misc2_mask, outer, bit_mask); -} - - struct mlx5dr_match_misc2 *misc2_mask = &value->misc2; + struct mlx5dr_match_misc2 *misc2 = &value->misc2; - dr_ste_set_mpls_tag(mpls, misc2_mask, inner, tag); + dr_ste_set_mpls(mpls, misc2, inner, tag); - dr_ste_set_mpls_tag(mpls, misc2_mask, outer, tag); + dr_ste_set_mpls(mpls, misc2, outer, tag); - dr_ste_v0_build_mpls_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_mpls_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_tnl_gre_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc *misc_mask = &value->misc; - - dr_ste_set_mask_v(gre, bit_mask, gre_protocol, misc_mask, gre_protocol); - dr_ste_set_mask_v(gre, bit_mask, gre_k_present, misc_mask, gre_k_present); - dr_ste_set_mask_v(gre, bit_mask, gre_key_h, misc_mask, gre_key_h); - dr_ste_set_mask_v(gre, bit_mask, gre_key_l, misc_mask, gre_key_l); - - dr_ste_set_mask_v(gre, bit_mask, gre_c_present, misc_mask, gre_c_present); - dr_ste_set_mask_v(gre, bit_mask, gre_s_present, misc_mask, gre_s_present); -} - - dr_ste_v0_build_tnl_gre_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_tnl_gre_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_tnl_mpls_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - if (dr_ste_is_outer_mpls_over_gre_set(misc_2_mask)) { - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_label, - misc_2_mask, outer_first_mpls_over_gre_label); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_exp, - misc_2_mask, outer_first_mpls_over_gre_exp); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_s_bos, - misc_2_mask, outer_first_mpls_over_gre_s_bos); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_ttl, - misc_2_mask, outer_first_mpls_over_gre_ttl); - } else { - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_label, - misc_2_mask, outer_first_mpls_over_udp_label); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_exp, - misc_2_mask, outer_first_mpls_over_udp_exp); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_s_bos, - misc_2_mask, outer_first_mpls_over_udp_s_bos); - - dr_ste_set_mask_v(flex_parser_0, bit_mask, parser_3_ttl, - misc_2_mask, outer_first_mpls_over_udp_ttl); - } -} - - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + struct mlx5dr_match_misc2 *misc_2 = &value->misc2; - if (dr_ste_is_outer_mpls_over_gre_set(misc_2_mask)) { + if (dr_ste_is_outer_mpls_over_gre_set(misc_2)) { - misc_2_mask, outer_first_mpls_over_gre_label); + misc_2, outer_first_mpls_over_gre_label); - misc_2_mask, outer_first_mpls_over_gre_exp); + misc_2, outer_first_mpls_over_gre_exp); - misc_2_mask, outer_first_mpls_over_gre_s_bos); + misc_2, outer_first_mpls_over_gre_s_bos); - misc_2_mask, outer_first_mpls_over_gre_ttl); + misc_2, outer_first_mpls_over_gre_ttl); - misc_2_mask, outer_first_mpls_over_udp_label); + misc_2, outer_first_mpls_over_udp_label); - misc_2_mask, outer_first_mpls_over_udp_exp); + misc_2, outer_first_mpls_over_udp_exp); - misc_2_mask, outer_first_mpls_over_udp_s_bos); + misc_2, outer_first_mpls_over_udp_s_bos); - misc_2_mask, outer_first_mpls_over_udp_ttl); + misc_2, outer_first_mpls_over_udp_ttl); - dr_ste_v0_build_tnl_mpls_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_tnl_mpls_tag(mask, sb, sb->bit_mask); -static int -dr_ste_v0_build_icmp_bit_mask(struct mlx5dr_match_param *mask, - struct mlx5dr_cmd_caps *caps, - u8 *bit_mask) -{ - struct mlx5dr_match_misc3 *misc_3_mask = &mask->misc3; - bool is_ipv4_mask = dr_mask_is_icmpv4_set(misc_3_mask); - u32 icmp_header_data_mask; - u32 icmp_type_mask; - u32 icmp_code_mask; - int dw0_location; - int dw1_location; - - if (is_ipv4_mask) { - icmp_header_data_mask = misc_3_mask->icmpv4_header_data; - icmp_type_mask = misc_3_mask->icmpv4_type; - icmp_code_mask = misc_3_mask->icmpv4_code; - dw0_location = caps->flex_parser_id_icmp_dw0; - dw1_location = caps->flex_parser_id_icmp_dw1; - } else { - icmp_header_data_mask = misc_3_mask->icmpv6_header_data; - icmp_type_mask = misc_3_mask->icmpv6_type; - icmp_code_mask = misc_3_mask->icmpv6_code; - dw0_location = caps->flex_parser_id_icmpv6_dw0; - dw1_location = caps->flex_parser_id_icmpv6_dw1; - } - - switch (dw0_location) { - case 4: - if (icmp_type_mask) { - mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_4, - (icmp_type_mask << icmp_type_offset_first_dw)); - if (is_ipv4_mask) - misc_3_mask->icmpv4_type = 0; - else - misc_3_mask->icmpv6_type = 0; - } - if (icmp_code_mask) { - u32 cur_val = mlx5_get(ste_flex_parser_1, bit_mask, - flex_parser_4); - mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_4, - cur_val | (icmp_code_mask << icmp_code_offset_first_dw)); - if (is_ipv4_mask) - misc_3_mask->icmpv4_code = 0; - else - misc_3_mask->icmpv6_code = 0; - } - break; - default: - return -einval; - } - - switch (dw1_location) { - case 5: - if (icmp_header_data_mask) { - mlx5_set(ste_flex_parser_1, bit_mask, flex_parser_5, - (icmp_header_data_mask << icmp_header_data_offset_second_dw)); - if (is_ipv4_mask) - misc_3_mask->icmpv4_header_data = 0; - else - misc_3_mask->icmpv6_header_data = 0; - } - break; - default: - return -einval; - } - - return 0; -} - - ret = dr_ste_v0_build_icmp_bit_mask(mask, sb->caps, sb->bit_mask); + ret = dr_ste_v0_build_icmp_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_general_purpose_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_mask_v(general_purpose, bit_mask, - general_purpose_lookup_field, misc_2_mask, - metadata_reg_a); -} - - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; + struct mlx5dr_match_misc2 *misc_2 = &value->misc2; - misc_2_mask, metadata_reg_a); + misc_2, metadata_reg_a); - dr_ste_v0_build_general_purpose_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_general_purpose_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_eth_l4_misc_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc3 *misc_3_mask = &value->misc3; - - if (inner) { - dr_ste_set_mask_v(eth_l4_misc, bit_mask, seq_num, misc_3_mask, - inner_tcp_seq_num); - dr_ste_set_mask_v(eth_l4_misc, bit_mask, ack_num, misc_3_mask, - inner_tcp_ack_num); - } else { - dr_ste_set_mask_v(eth_l4_misc, bit_mask, seq_num, misc_3_mask, - outer_tcp_seq_num); - dr_ste_set_mask_v(eth_l4_misc, bit_mask, ack_num, misc_3_mask, - outer_tcp_ack_num); - } -} - - dr_ste_v0_build_eth_l4_misc_bit_mask(mask, sb->inner, sb->bit_mask); + dr_ste_v0_build_eth_l4_misc_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(struct mlx5dr_match_param *value, - bool inner, u8 *bit_mask) -{ - struct mlx5dr_match_misc3 *misc_3_mask = &value->misc3; - - dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, - outer_vxlan_gpe_flags, - misc_3_mask, outer_vxlan_gpe_flags); - dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, - outer_vxlan_gpe_next_protocol, - misc_3_mask, outer_vxlan_gpe_next_protocol); - dr_ste_set_mask_v(flex_parser_tnl_vxlan_gpe, bit_mask, - outer_vxlan_gpe_vni, - misc_3_mask, outer_vxlan_gpe_vni); -} - - dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_bit_mask(mask, sb->inner, - sb->bit_mask); + dr_ste_v0_build_flex_parser_tnl_vxlan_gpe_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc *misc_mask = &value->misc; - - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_protocol_type, - misc_mask, geneve_protocol_type); - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_oam, - misc_mask, geneve_oam); - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_opt_len, - misc_mask, geneve_opt_len); - dr_ste_set_mask_v(flex_parser_tnl_geneve, bit_mask, - geneve_vni, - misc_mask, geneve_vni); -} - - dr_ste_v0_build_flex_parser_tnl_geneve_bit_mask(mask, sb->bit_mask); + dr_ste_v0_build_flex_parser_tnl_geneve_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_register_0_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_mask_v(register_0, bit_mask, register_0_h, - misc_2_mask, metadata_reg_c_0); - dr_ste_set_mask_v(register_0, bit_mask, register_0_l, - misc_2_mask, metadata_reg_c_1); - dr_ste_set_mask_v(register_0, bit_mask, register_1_h, - misc_2_mask, metadata_reg_c_2); - dr_ste_set_mask_v(register_0, bit_mask, register_1_l, - misc_2_mask, metadata_reg_c_3); -} - - dr_ste_v0_build_register_0_bit_mask(mask, sb->bit_mask); + dr_ste_v0_build_register_0_tag(mask, sb, sb->bit_mask); -static void -dr_ste_v0_build_register_1_bit_mask(struct mlx5dr_match_param *value, - u8 *bit_mask) -{ - struct mlx5dr_match_misc2 *misc_2_mask = &value->misc2; - - dr_ste_set_mask_v(register_1, bit_mask, register_2_h, - misc_2_mask, metadata_reg_c_4); - dr_ste_set_mask_v(register_1, bit_mask, register_2_l, - misc_2_mask, metadata_reg_c_5); - dr_ste_set_mask_v(register_1, bit_mask, register_3_h, - misc_2_mask, metadata_reg_c_6); - dr_ste_set_mask_v(register_1, bit_mask, register_3_l, - misc_2_mask, metadata_reg_c_7); -} - - dr_ste_v0_build_register_1_bit_mask(mask, sb->bit_mask); + dr_ste_v0_build_register_1_tag(mask, sb, sb->bit_mask); - dr_ste_set_mask(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port); - dr_ste_set_mask(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn); + dr_ste_set_ones(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port); + dr_ste_set_ones(src_gvmi_qp, bit_mask, source_qp, misc_mask, source_sqn);
|
Networking
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467790985d2d7fd16a64a262578c2575d905e648
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yevgeny kliteynik saeed mahameed saeedm nvidia com
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drivers
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net
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core, ethernet, mellanox, mlx5, steering
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net/mlx5: dr, move stev0 look up types from mlx5_ifc_dr header
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the lookup types are device specific and should not be exposed to dr upper layers, matchers/tables. each hw ste version should keep them internal. the lu_type size is updated to support larger lu_types as required for stev1.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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introduce some refactoring to sw steering to support different formats of different hardware
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['mlx5/mlx5e ']
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['h', 'c']
| 4
| 64
| 60
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--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type, +void mlx5dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, - u8 next_lu_type; + u16 next_lu_type; - u8 lu_type, u16 byte_mask) + u16 lu_type, u16 byte_mask) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c - ((inner) ? mlx5dr_ste_lu_type_##lookup_type##_i : \ - (rx) ? mlx5dr_ste_lu_type_##lookup_type##_d : \ - mlx5dr_ste_lu_type_##lookup_type##_o) + ((inner) ? dr_ste_v0_lu_type_##lookup_type##_i : \ + (rx) ? dr_ste_v0_lu_type_##lookup_type##_d : \ + dr_ste_v0_lu_type_##lookup_type##_o) + +enum { + dr_ste_v0_lu_type_nop = 0x00, + dr_ste_v0_lu_type_src_gvmi_and_qp = 0x05, + dr_ste_v0_lu_type_ethl2_tunneling_i = 0x0a, + dr_ste_v0_lu_type_ethl2_dst_o = 0x06, + dr_ste_v0_lu_type_ethl2_dst_i = 0x07, + dr_ste_v0_lu_type_ethl2_dst_d = 0x1b, + dr_ste_v0_lu_type_ethl2_src_o = 0x08, + dr_ste_v0_lu_type_ethl2_src_i = 0x09, + dr_ste_v0_lu_type_ethl2_src_d = 0x1c, + dr_ste_v0_lu_type_ethl2_src_dst_o = 0x36, + dr_ste_v0_lu_type_ethl2_src_dst_i = 0x37, + dr_ste_v0_lu_type_ethl2_src_dst_d = 0x38, + dr_ste_v0_lu_type_ethl3_ipv6_dst_o = 0x0d, + dr_ste_v0_lu_type_ethl3_ipv6_dst_i = 0x0e, + dr_ste_v0_lu_type_ethl3_ipv6_dst_d = 0x1e, + dr_ste_v0_lu_type_ethl3_ipv6_src_o = 0x0f, + dr_ste_v0_lu_type_ethl3_ipv6_src_i = 0x10, + dr_ste_v0_lu_type_ethl3_ipv6_src_d = 0x1f, + dr_ste_v0_lu_type_ethl3_ipv4_5_tuple_o = 0x11, + dr_ste_v0_lu_type_ethl3_ipv4_5_tuple_i = 0x12, + dr_ste_v0_lu_type_ethl3_ipv4_5_tuple_d = 0x20, + dr_ste_v0_lu_type_ethl3_ipv4_misc_o = 0x29, + dr_ste_v0_lu_type_ethl3_ipv4_misc_i = 0x2a, + dr_ste_v0_lu_type_ethl3_ipv4_misc_d = 0x2b, + dr_ste_v0_lu_type_ethl4_o = 0x13, + dr_ste_v0_lu_type_ethl4_i = 0x14, + dr_ste_v0_lu_type_ethl4_d = 0x21, + dr_ste_v0_lu_type_ethl4_misc_o = 0x2c, + dr_ste_v0_lu_type_ethl4_misc_i = 0x2d, + dr_ste_v0_lu_type_ethl4_misc_d = 0x2e, + dr_ste_v0_lu_type_mpls_first_o = 0x15, + dr_ste_v0_lu_type_mpls_first_i = 0x24, + dr_ste_v0_lu_type_mpls_first_d = 0x25, + dr_ste_v0_lu_type_gre = 0x16, + dr_ste_v0_lu_type_flex_parser_0 = 0x22, + dr_ste_v0_lu_type_flex_parser_1 = 0x23, + dr_ste_v0_lu_type_flex_parser_tnl_header = 0x19, + dr_ste_v0_lu_type_general_purpose = 0x18, + dr_ste_v0_lu_type_steering_registers_0 = 0x2f, + dr_ste_v0_lu_type_steering_registers_1 = 0x30, + dr_ste_v0_lu_type_dont_care = mlx5dr_ste_lu_type_dont_care, +}; - sb->lu_type = mlx5dr_ste_lu_type_ethl2_tunneling_i; + sb->lu_type = dr_ste_v0_lu_type_ethl2_tunneling_i; - sb->lu_type = mlx5dr_ste_lu_type_gre; + sb->lu_type = dr_ste_v0_lu_type_gre; - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_0; + sb->lu_type = dr_ste_v0_lu_type_flex_parser_0; - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_1; + sb->lu_type = dr_ste_v0_lu_type_flex_parser_1; - sb->lu_type = mlx5dr_ste_lu_type_general_purpose; + sb->lu_type = dr_ste_v0_lu_type_general_purpose; - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; + sb->lu_type = dr_ste_v0_lu_type_flex_parser_tnl_header; - sb->lu_type = mlx5dr_ste_lu_type_flex_parser_tnl_header; + sb->lu_type = dr_ste_v0_lu_type_flex_parser_tnl_header; - sb->lu_type = mlx5dr_ste_lu_type_steering_registers_0; + sb->lu_type = dr_ste_v0_lu_type_steering_registers_0; - sb->lu_type = mlx5dr_ste_lu_type_steering_registers_1; + sb->lu_type = dr_ste_v0_lu_type_steering_registers_1; - sb->lu_type = mlx5dr_ste_lu_type_src_gvmi_and_qp; + sb->lu_type = dr_ste_v0_lu_type_src_gvmi_and_qp; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h - u8 lu_type; + u16 lu_type; - u8 lu_type; + u16 lu_type; - u8 lu_type, u16 byte_mask); + u16 lu_type, u16 byte_mask); -void mlx5dr_ste_init(u8 *hw_ste_p, u8 lu_type, u8 entry_type, u16 gvmi); +void mlx5dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, u16 gvmi); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h - mlx5dr_ste_lu_type_nop = 0x00, - mlx5dr_ste_lu_type_src_gvmi_and_qp = 0x05, - mlx5dr_ste_lu_type_ethl2_tunneling_i = 0x0a, - mlx5dr_ste_lu_type_ethl2_dst_o = 0x06, - mlx5dr_ste_lu_type_ethl2_dst_i = 0x07, - mlx5dr_ste_lu_type_ethl2_dst_d = 0x1b, - mlx5dr_ste_lu_type_ethl2_src_o = 0x08, - mlx5dr_ste_lu_type_ethl2_src_i = 0x09, - mlx5dr_ste_lu_type_ethl2_src_d = 0x1c, - mlx5dr_ste_lu_type_ethl2_src_dst_o = 0x36, - mlx5dr_ste_lu_type_ethl2_src_dst_i = 0x37, - mlx5dr_ste_lu_type_ethl2_src_dst_d = 0x38, - mlx5dr_ste_lu_type_ethl3_ipv6_dst_o = 0x0d, - mlx5dr_ste_lu_type_ethl3_ipv6_dst_i = 0x0e, - mlx5dr_ste_lu_type_ethl3_ipv6_dst_d = 0x1e, - mlx5dr_ste_lu_type_ethl3_ipv6_src_o = 0x0f, - mlx5dr_ste_lu_type_ethl3_ipv6_src_i = 0x10, - mlx5dr_ste_lu_type_ethl3_ipv6_src_d = 0x1f, - mlx5dr_ste_lu_type_ethl3_ipv4_5_tuple_o = 0x11, - mlx5dr_ste_lu_type_ethl3_ipv4_5_tuple_i = 0x12, - mlx5dr_ste_lu_type_ethl3_ipv4_5_tuple_d = 0x20, - mlx5dr_ste_lu_type_ethl3_ipv4_misc_o = 0x29, - mlx5dr_ste_lu_type_ethl3_ipv4_misc_i = 0x2a, - mlx5dr_ste_lu_type_ethl3_ipv4_misc_d = 0x2b, - mlx5dr_ste_lu_type_ethl4_o = 0x13, - mlx5dr_ste_lu_type_ethl4_i = 0x14, - mlx5dr_ste_lu_type_ethl4_d = 0x21, - mlx5dr_ste_lu_type_ethl4_misc_o = 0x2c, - mlx5dr_ste_lu_type_ethl4_misc_i = 0x2d, - mlx5dr_ste_lu_type_ethl4_misc_d = 0x2e, - mlx5dr_ste_lu_type_mpls_first_o = 0x15, - mlx5dr_ste_lu_type_mpls_first_i = 0x24, - mlx5dr_ste_lu_type_mpls_first_d = 0x25, - mlx5dr_ste_lu_type_gre = 0x16, - mlx5dr_ste_lu_type_flex_parser_0 = 0x22, - mlx5dr_ste_lu_type_flex_parser_1 = 0x23, - mlx5dr_ste_lu_type_flex_parser_tnl_header = 0x19, - mlx5dr_ste_lu_type_general_purpose = 0x18, - mlx5dr_ste_lu_type_steering_registers_0 = 0x2f, - mlx5dr_ste_lu_type_steering_registers_1 = 0x30,
|
Networking
|
dd2d3c8d206e1796b384e438d1219f44f4cbd5c2
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, refactor icmp ste builder
|
reworked icmp tag builder to better handle icmp v4/6 fields and avoid unneeded code duplication and 'if' statements, removed unused macro, changed bitfield of len 8 to u8.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 23
| 42
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c -#define icmp_type_offset_first_dw 24 -#define icmp_code_offset_first_dw 16 -#define icmp_header_data_offset_second_dw 0 +#define icmp_type_offset_first_dw 24 +#define icmp_code_offset_first_dw 16 - u32 icmp_header_data; + u32 *icmp_header_data; - u32 icmp_type; - u32 icmp_code; + u8 *icmp_type; + u8 *icmp_code; - icmp_header_data = misc_3->icmpv4_header_data; - icmp_type = misc_3->icmpv4_type; - icmp_code = misc_3->icmpv4_code; + icmp_header_data = &misc_3->icmpv4_header_data; + icmp_type = &misc_3->icmpv4_type; + icmp_code = &misc_3->icmpv4_code; - icmp_header_data = misc_3->icmpv6_header_data; - icmp_type = misc_3->icmpv6_type; - icmp_code = misc_3->icmpv6_code; + icmp_header_data = &misc_3->icmpv6_header_data; + icmp_type = &misc_3->icmpv6_type; + icmp_code = &misc_3->icmpv6_code; - if (icmp_type) { - mlx5_set(ste_flex_parser_1, tag, flex_parser_4, - (icmp_type << icmp_type_offset_first_dw)); - if (is_ipv4) - misc_3->icmpv4_type = 0; - else - misc_3->icmpv6_type = 0; - } + mlx5_set(ste_flex_parser_1, tag, flex_parser_4, + (*icmp_type << icmp_type_offset_first_dw) | + (*icmp_code << icmp_type_offset_first_dw)); - if (icmp_code) { - u32 cur_val = mlx5_get(ste_flex_parser_1, tag, - flex_parser_4); - mlx5_set(ste_flex_parser_1, tag, flex_parser_4, - cur_val | (icmp_code << icmp_code_offset_first_dw)); - if (is_ipv4) - misc_3->icmpv4_code = 0; - else - misc_3->icmpv6_code = 0; - } + *icmp_type = 0; + *icmp_code = 0; - if (icmp_header_data) { - mlx5_set(ste_flex_parser_1, tag, flex_parser_5, - (icmp_header_data << icmp_header_data_offset_second_dw)); - if (is_ipv4) - misc_3->icmpv4_header_data = 0; - else - misc_3->icmpv6_header_data = 0; - } + mlx5_set(ste_flex_parser_1, tag, flex_parser_5, + *icmp_header_data); + *icmp_header_data = 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h - u32 icmpv6_code:8; - u32 icmpv6_type:8; - u32 icmpv4_code:8; - u32 icmpv4_type:8; + u8 icmpv6_code; + u8 icmpv6_type; + u8 icmpv4_code; + u8 icmpv4_type;
|
Networking
|
40ca842c2b5bd08cf089c9f5e617968c5a0a001c
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, move action apply logic to dr_ste
|
the action apply logic is device specific per ste version, moving to the ste layer will allow implementing it for both devices while keeping dr upper layers the same.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 3
| 231
| 234
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c -#define max_vlans 2 -struct dr_action_vlan_info { - int count; - u32 headers[max_vlans]; -}; - -struct dr_action_apply_attr { - u32 modify_index; - u16 modify_actions; - u32 decap_index; - u16 decap_actions; - u8 decap_with_vlan:1; - u64 final_icm_addr; - u32 flow_tag; - u32 ctr_id; - u16 gvmi; - u16 hit_gvmi; - u32 reformat_id; - u32 reformat_size; - struct dr_action_vlan_info vlans; -}; - -static void dr_actions_init_next_ste(u8 **last_ste, - u32 *added_stes, - enum mlx5dr_ste_entry_type entry_type, - u16 gvmi) -{ - (*added_stes)++; - *last_ste += dr_ste_size; - mlx5dr_ste_init(*last_ste, mlx5dr_ste_lu_type_dont_care, entry_type, gvmi); -} - -static void dr_actions_apply_tx(struct mlx5dr_domain *dmn, - u8 *action_type_set, - u8 *last_ste, - struct dr_action_apply_attr *attr, - u32 *added_stes) -{ - bool encap = action_type_set[dr_action_typ_l2_to_tnl_l2] || - action_type_set[dr_action_typ_l2_to_tnl_l3]; - - /* we want to make sure the modify header comes before l2 - * encapsulation. the reason for that is that we support - * modify headers for outer headers only - */ - if (action_type_set[dr_action_typ_modify_hdr]) { - mlx5dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); - mlx5dr_ste_set_rewrite_actions(last_ste, - attr->modify_actions, - attr->modify_index); - } - - if (action_type_set[dr_action_typ_push_vlan]) { - int i; - - for (i = 0; i < attr->vlans.count; i++) { - if (i || action_type_set[dr_action_typ_modify_hdr]) - dr_actions_init_next_ste(&last_ste, - added_stes, - mlx5dr_ste_type_tx, - attr->gvmi); - - mlx5dr_ste_set_tx_push_vlan(last_ste, - attr->vlans.headers[i], - encap); - } - } - - if (encap) { - /* modify header and encapsulation require a different stes. - * since modify header ste format doesn't support encapsulation - * tunneling_action. - */ - if (action_type_set[dr_action_typ_modify_hdr] || - action_type_set[dr_action_typ_push_vlan]) - dr_actions_init_next_ste(&last_ste, - added_stes, - mlx5dr_ste_type_tx, - attr->gvmi); - - mlx5dr_ste_set_tx_encap(last_ste, - attr->reformat_id, - attr->reformat_size, - action_type_set[dr_action_typ_l2_to_tnl_l3]); - /* whenever prio_tag_required enabled, we can be sure that the - * previous table (acl) already push vlan to our packet, - * and due to hw limitation we need to set this bit, otherwise - * push vlan + reformat will not work. - */ - if (mlx5_cap_gen(dmn->mdev, prio_tag_required)) - mlx5dr_ste_set_go_back_bit(last_ste); - } - - if (action_type_set[dr_action_typ_ctr]) - mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id); -} - -static void dr_actions_apply_rx(u8 *action_type_set, - u8 *last_ste, - struct dr_action_apply_attr *attr, - u32 *added_stes) -{ - if (action_type_set[dr_action_typ_ctr]) - mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id); - - if (action_type_set[dr_action_typ_tnl_l3_to_l2]) { - mlx5dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); - mlx5dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan); - mlx5dr_ste_set_rewrite_actions(last_ste, - attr->decap_actions, - attr->decap_index); - } - - if (action_type_set[dr_action_typ_tnl_l2_to_l2]) - mlx5dr_ste_set_rx_decap(last_ste); - - if (action_type_set[dr_action_typ_pop_vlan]) { - int i; - - for (i = 0; i < attr->vlans.count; i++) { - if (i || - action_type_set[dr_action_typ_tnl_l2_to_l2] || - action_type_set[dr_action_typ_tnl_l3_to_l2]) - dr_actions_init_next_ste(&last_ste, - added_stes, - mlx5dr_ste_type_rx, - attr->gvmi); - - mlx5dr_ste_set_rx_pop_vlan(last_ste); - } - } - - if (action_type_set[dr_action_typ_modify_hdr]) { - if (mlx5dr_ste_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) - dr_actions_init_next_ste(&last_ste, - added_stes, - mlx5dr_ste_type_modify_pkt, - attr->gvmi); - else - mlx5dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); - - mlx5dr_ste_set_rewrite_actions(last_ste, - attr->modify_actions, - attr->modify_index); - } - - if (action_type_set[dr_action_typ_tag]) { - if (mlx5dr_ste_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) - dr_actions_init_next_ste(&last_ste, - added_stes, - mlx5dr_ste_type_rx, - attr->gvmi); - - mlx5dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag); - } -} - - struct dr_action_apply_attr *attr, + struct mlx5dr_ste_actions_attr *attr, - dr_actions_apply_rx(action_type_set, last_ste, attr, &added_stes); + mlx5dr_ste_set_actions_rx(dmn, action_type_set, + last_ste, attr, &added_stes); - dr_actions_apply_tx(dmn, action_type_set, last_ste, attr, &added_stes); + mlx5dr_ste_set_actions_tx(dmn, action_type_set, + last_ste, attr, &added_stes); - last_ste += added_stes * dr_ste_size; - - mlx5dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi); - mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1); + struct mlx5dr_ste_actions_attr attr = {}; - struct dr_action_apply_attr attr = {}; - max_actions_type = max_vlans; + max_actions_type = mlx5dr_max_vlans; - max_actions_type = max_vlans; - if (attr.vlans.count == max_vlans) + max_actions_type = mlx5dr_max_vlans; + if (attr.vlans.count == mlx5dr_max_vlans) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -static u8 *mlx5dr_ste_get_tag(u8 *hw_ste_p) +static u8 *dr_ste_get_tag(u8 *hw_ste_p) -void mlx5dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag) +static void dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag) -void mlx5dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id) +static void dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id) -void mlx5dr_ste_set_go_back_bit(u8 *hw_ste_p) +static void dr_ste_set_go_back_bit(u8 *hw_ste_p) -void mlx5dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_hdr, - bool go_back) +static void dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_hdr, + bool go_back) - mlx5dr_ste_set_go_back_bit(hw_ste_p); + dr_ste_set_go_back_bit(hw_ste_p); -void mlx5dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id, int size, bool encap_l3) +static void dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id, + int size, bool encap_l3) -void mlx5dr_ste_set_rx_decap(u8 *hw_ste_p) +static void dr_ste_set_rx_decap(u8 *hw_ste_p) -void mlx5dr_ste_set_rx_pop_vlan(u8 *hw_ste_p) +static void dr_ste_set_rx_pop_vlan(u8 *hw_ste_p) -void mlx5dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan) +static void dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan) -void mlx5dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type) +static void dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type) -u8 mlx5dr_ste_get_entry_type(u8 *hw_ste_p) +static u8 dr_ste_get_entry_type(u8 *hw_ste_p) -void mlx5dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, - u32 re_write_index) +static void dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, + u32 re_write_index) -void mlx5dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) +static void dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) -void mlx5dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, - u16 gvmi) +static void dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, + u16 gvmi) -u64 mlx5dr_ste_get_miss_addr(u8 *hw_ste) +void mlx5dr_ste_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) +{ + u64 index = miss_addr >> 6; + + /* miss address for tx and rx stes located in the same offsets */ + mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_39_32, index >> 26); + mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_31_6, index); +} + +static u64 dr_ste_get_miss_addr(u8 *hw_ste) +static void dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr) +{ + u8 *hw_ste_p = ste->hw_ste; + + mlx5_set(ste_rx_steering_mult, hw_ste_p, next_lu_type, + mlx5dr_ste_lu_type_dont_care); + mlx5dr_ste_set_miss_addr(hw_ste_p, miss_addr); + dr_ste_set_always_miss((struct dr_hw_ste_format *)ste->hw_ste); +} + - mlx5dr_ste_always_miss_addr(&tmp_ste, miss_addr); + dr_ste_always_miss_addr(&tmp_ste, miss_addr); - miss_addr = mlx5dr_ste_get_miss_addr(ste->hw_ste); + miss_addr = dr_ste_get_miss_addr(ste->hw_ste); -void mlx5dr_ste_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) -{ - u64 index = miss_addr >> 6; - - /* miss address for tx and rx stes located in the same offsets */ - mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_39_32, index >> 26); - mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_31_6, index); -} - -void mlx5dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr) -{ - u8 *hw_ste = ste->hw_ste; - - mlx5_set(ste_rx_steering_mult, hw_ste, next_lu_type, mlx5dr_ste_lu_type_dont_care); - mlx5dr_ste_set_miss_addr(hw_ste, miss_addr); - dr_ste_set_always_miss((struct dr_hw_ste_format *)ste->hw_ste); -} - - mlx5dr_ste_init(formatted_ste, htbl->lu_type, nic_dmn->ste_type, gvmi); + dr_ste_init(formatted_ste, htbl->lu_type, nic_dmn->ste_type, gvmi); - mlx5dr_ste_always_miss_addr(&ste, connect_info->miss_icm_addr); + dr_ste_always_miss_addr(&ste, connect_info->miss_icm_addr); +static void dr_ste_arr_init_next_ste(u8 **last_ste, + u32 *added_stes, + enum mlx5dr_ste_entry_type entry_type, + u16 gvmi) +{ + (*added_stes)++; + *last_ste += dr_ste_size; + dr_ste_init(*last_ste, mlx5dr_ste_lu_type_dont_care, entry_type, gvmi); +} + +void mlx5dr_ste_set_actions_tx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes) +{ + bool encap = action_type_set[dr_action_typ_l2_to_tnl_l2] || + action_type_set[dr_action_typ_l2_to_tnl_l3]; + + /* we want to make sure the modify header comes before l2 + * encapsulation. the reason for that is that we support + * modify headers for outer headers only + */ + if (action_type_set[dr_action_typ_modify_hdr]) { + dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); + dr_ste_set_rewrite_actions(last_ste, + attr->modify_actions, + attr->modify_index); + } + + if (action_type_set[dr_action_typ_push_vlan]) { + int i; + + for (i = 0; i < attr->vlans.count; i++) { + if (i || action_type_set[dr_action_typ_modify_hdr]) + dr_ste_arr_init_next_ste(&last_ste, + added_stes, + mlx5dr_ste_type_tx, + attr->gvmi); + + dr_ste_set_tx_push_vlan(last_ste, + attr->vlans.headers[i], + encap); + } + } + + if (encap) { + /* modify header and encapsulation require a different stes. + * since modify header ste format doesn't support encapsulation + * tunneling_action. + */ + if (action_type_set[dr_action_typ_modify_hdr] || + action_type_set[dr_action_typ_push_vlan]) + dr_ste_arr_init_next_ste(&last_ste, + added_stes, + mlx5dr_ste_type_tx, + attr->gvmi); + + dr_ste_set_tx_encap(last_ste, + attr->reformat_id, + attr->reformat_size, + action_type_set[dr_action_typ_l2_to_tnl_l3]); + /* whenever prio_tag_required enabled, we can be sure that the + * previous table (acl) already push vlan to our packet, + * and due to hw limitation we need to set this bit, otherwise + * push vlan + reformat will not work. + */ + if (mlx5_cap_gen(dmn->mdev, prio_tag_required)) + dr_ste_set_go_back_bit(last_ste); + } + + if (action_type_set[dr_action_typ_ctr]) + dr_ste_set_counter_id(last_ste, attr->ctr_id); + + dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi); + mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1); +} + +void mlx5dr_ste_set_actions_rx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes) +{ + if (action_type_set[dr_action_typ_ctr]) + dr_ste_set_counter_id(last_ste, attr->ctr_id); + + if (action_type_set[dr_action_typ_tnl_l3_to_l2]) { + dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); + dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan); + dr_ste_set_rewrite_actions(last_ste, + attr->decap_actions, + attr->decap_index); + } + + if (action_type_set[dr_action_typ_tnl_l2_to_l2]) + dr_ste_set_rx_decap(last_ste); + + if (action_type_set[dr_action_typ_pop_vlan]) { + int i; + + for (i = 0; i < attr->vlans.count; i++) { + if (i || + action_type_set[dr_action_typ_tnl_l2_to_l2] || + action_type_set[dr_action_typ_tnl_l3_to_l2]) + dr_ste_arr_init_next_ste(&last_ste, + added_stes, + mlx5dr_ste_type_rx, + attr->gvmi); + + dr_ste_set_rx_pop_vlan(last_ste); + } + } + + if (action_type_set[dr_action_typ_modify_hdr]) { + if (dr_ste_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) + dr_ste_arr_init_next_ste(&last_ste, + added_stes, + mlx5dr_ste_type_modify_pkt, + attr->gvmi); + else + dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); + + dr_ste_set_rewrite_actions(last_ste, + attr->modify_actions, + attr->modify_index); + } + + if (action_type_set[dr_action_typ_tag]) { + if (dr_ste_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) + dr_ste_arr_init_next_ste(&last_ste, + added_stes, + mlx5dr_ste_type_rx, + attr->gvmi); + + dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag); + } + + dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi); + mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1); +} + - mlx5dr_ste_init(ste_arr, - sb->lu_type, - nic_dmn->ste_type, - dmn->info.caps.gvmi); + dr_ste_init(ste_arr, + sb->lu_type, + nic_dmn->ste_type, + dmn->info.caps.gvmi); - ret = sb->ste_build_tag_func(value, sb, mlx5dr_ste_get_tag(ste_arr)); + ret = sb->ste_build_tag_func(value, sb, dr_ste_get_tag(ste_arr)); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h -void mlx5dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, u16 gvmi); -void mlx5dr_ste_always_hit_htbl(struct mlx5dr_ste *ste, - struct mlx5dr_ste_htbl *next_htbl); -u64 mlx5dr_ste_get_miss_addr(u8 *hw_ste); -void mlx5dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi); -void mlx5dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr); -void mlx5dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag); -void mlx5dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id); -void mlx5dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id, - int size, bool encap_l3); -void mlx5dr_ste_set_rx_decap(u8 *hw_ste_p); -void mlx5dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan); -void mlx5dr_ste_set_rx_pop_vlan(u8 *hw_ste_p); -void mlx5dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_tpid_pcp_dei_vid, - bool go_back); -void mlx5dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type); -u8 mlx5dr_ste_get_entry_type(u8 *hw_ste_p); -void mlx5dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, - u32 re_write_index); -void mlx5dr_ste_set_go_back_bit(u8 *hw_ste_p); +#define mlx5dr_max_vlans 2 + +struct mlx5dr_ste_actions_attr { + u32 modify_index; + u16 modify_actions; + u32 decap_index; + u16 decap_actions; + u8 decap_with_vlan:1; + u64 final_icm_addr; + u32 flow_tag; + u32 ctr_id; + u16 gvmi; + u16 hit_gvmi; + u32 reformat_id; + u32 reformat_size; + struct { + int count; + u32 headers[mlx5dr_max_vlans]; + } vlans; +}; + +void mlx5dr_ste_set_actions_rx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes); +void mlx5dr_ste_set_actions_tx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes); +
|
Networking
|
64c7894218b9e7b0dcb93478f035c4178e5b348f
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add ste setters and getters per-device api
|
extend the ste context struct with various per-device setters and getters.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h']
| 1
| 12
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h + /* builders */ + + /* getters and setters */ + void (*ste_init)(u8 *hw_ste_p, u16 lu_type, + u8 entry_type, u16 gvmi); + void (*set_next_lu_type)(u8 *hw_ste_p, u16 lu_type); + u16 (*get_next_lu_type)(u8 *hw_ste_p); + void (*set_miss_addr)(u8 *hw_ste_p, u64 miss_addr); + u64 (*get_miss_addr)(u8 *hw_ste_p); + void (*set_hit_addr)(u8 *hw_ste_p, u64 icm_addr, u32 ht_size); + void (*set_byte_mask)(u8 *hw_ste_p, u16 byte_mask); + u16 (*get_byte_mask)(u8 *hw_ste_p);
|
Networking
|
6c1f0e4df858dbdfac93ffdfbc50f66d3950a50d
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, move stev0 setters and getters
|
use the new setters and getters api for stev0: move hw specific setter and getters from dr_ste to stev0 file. since stev0 and stev1 format are different each version should implemented different setters and getters. rename remaining static functions w/o mlx5 prefix.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 5
| 195
| 103
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - mlx5dr_ste_set_actions_rx(dmn, action_type_set, + mlx5dr_ste_set_actions_rx(ste_ctx, dmn, action_type_set, - mlx5dr_ste_set_actions_tx(dmn, action_type_set, + mlx5dr_ste_set_actions_tx(ste_ctx, dmn, action_type_set, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c -static int dr_rule_append_to_miss_list(struct mlx5dr_ste *new_last_ste, +static int dr_rule_append_to_miss_list(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste *new_last_ste, - mlx5dr_ste_set_miss_addr(last_ste->hw_ste, + mlx5dr_ste_set_miss_addr(ste_ctx, last_ste->hw_ste, + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - mlx5dr_ste_set_miss_addr(hw_ste, nic_matcher->e_anchor->chunk->icm_addr); + mlx5dr_ste_set_miss_addr(ste_ctx, hw_ste, + nic_matcher->e_anchor->chunk->icm_addr); + struct mlx5dr_domain *dmn = matcher->tbl->dmn; - ret = dr_rule_append_to_miss_list(new_ste, + ret = dr_rule_append_to_miss_list(dmn->ste_ctx, new_ste, - mlx5dr_dbg(matcher->tbl->dmn, "failed update dup entry "); + mlx5dr_dbg(dmn, "failed update dup entry "); + struct mlx5dr_domain *dmn = matcher->tbl->dmn; - mlx5dr_ste_set_miss_addr(hw_ste, nic_matcher->e_anchor->chunk->icm_addr); + mlx5dr_ste_set_miss_addr(dmn->ste_ctx, hw_ste, + nic_matcher->e_anchor->chunk->icm_addr); - mlx5dr_dbg(matcher->tbl->dmn, "failed adding collision entry, index: %d ", + mlx5dr_dbg(dmn, "failed adding collision entry, index: %d ", - mlx5dr_ste_set_formatted_ste(dmn->info.caps.gvmi, + mlx5dr_ste_set_formatted_ste(dmn->ste_ctx, + dmn->info.caps.gvmi, - mlx5dr_ste_set_hit_addr(prev_htbl->ste_arr[0].hw_ste, + mlx5dr_ste_set_hit_addr(dmn->ste_ctx, + prev_htbl->ste_arr[0].hw_ste, - mlx5dr_ste_set_hit_addr_by_next_htbl(cur_htbl->pointing_ste->hw_ste, + mlx5dr_ste_set_hit_addr_by_next_htbl(dmn->ste_ctx, + cur_htbl->pointing_ste->hw_ste, + struct mlx5dr_domain *dmn = matcher->tbl->dmn; + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - if (dr_rule_append_to_miss_list(new_ste, miss_list, send_list)) { - mlx5dr_dbg(matcher->tbl->dmn, "failed to update prev miss_list "); + if (dr_rule_append_to_miss_list(ste_ctx, new_ste, + miss_list, send_list)) { + mlx5dr_dbg(dmn, "failed to update prev miss_list "); + struct mlx5dr_domain *dmn = matcher->tbl->dmn; - mlx5dr_ste_set_hit_addr_by_next_htbl(prev_hw_ste, action_ste->htbl); + mlx5dr_ste_set_hit_addr_by_next_htbl(dmn->ste_ctx, + prev_hw_ste, + action_ste->htbl); - mlx5dr_dbg(matcher->tbl->dmn, "failed adding rule member "); + mlx5dr_dbg(dmn, "failed adding rule member "); + struct mlx5dr_domain *dmn = matcher->tbl->dmn; - mlx5dr_ste_set_miss_addr(hw_ste, nic_matcher->e_anchor->chunk->icm_addr); + mlx5dr_ste_set_miss_addr(dmn->ste_ctx, hw_ste, + nic_matcher->e_anchor->chunk->icm_addr); - mlx5dr_dbg(matcher->tbl->dmn, "failed allocating table "); + mlx5dr_dbg(dmn, "failed allocating table "); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -static void dr_ste_init(u8 *hw_ste_p, u16 lu_type, u8 entry_type, - u16 gvmi) -{ - mlx5_set(ste_general, hw_ste_p, entry_type, entry_type); - mlx5_set(ste_general, hw_ste_p, entry_sub_type, lu_type); - mlx5_set(ste_general, hw_ste_p, next_lu_type, mlx5dr_ste_lu_type_dont_care); - - /* set gvmi once, this is the same for rx/tx - * bits 63_48 of next table base / miss address encode the next gvmi - */ - mlx5_set(ste_rx_steering_mult, hw_ste_p, gvmi, gvmi); - mlx5_set(ste_rx_steering_mult, hw_ste_p, next_table_base_63_48, gvmi); - mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_63_48, gvmi); -} - -void mlx5dr_ste_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) +void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste_p, u64 miss_addr) - u64 index = miss_addr >> 6; - - /* miss address for tx and rx stes located in the same offsets */ - mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_39_32, index >> 26); - mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_31_6, index); -} - -static u64 dr_ste_get_miss_addr(u8 *hw_ste) -{ - u64 index = - (mlx5_get(ste_rx_steering_mult, hw_ste, miss_address_31_6) | - mlx5_get(ste_rx_steering_mult, hw_ste, miss_address_39_32) << 26); - - return index << 6; + ste_ctx->set_miss_addr(hw_ste_p, miss_addr); -static void dr_ste_always_miss_addr(struct mlx5dr_ste *ste, u64 miss_addr) +static void dr_ste_always_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste *ste, u64 miss_addr) - mlx5_set(ste_rx_steering_mult, hw_ste_p, next_lu_type, - mlx5dr_ste_lu_type_dont_care); - mlx5dr_ste_set_miss_addr(hw_ste_p, miss_addr); + ste_ctx->set_next_lu_type(hw_ste_p, mlx5dr_ste_lu_type_dont_care); + ste_ctx->set_miss_addr(hw_ste_p, miss_addr); -void mlx5dr_ste_set_hit_addr(u8 *hw_ste, u64 icm_addr, u32 ht_size) +void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste, u64 icm_addr, u32 ht_size) - u64 index = (icm_addr >> 5) | ht_size; - - mlx5_set(ste_general, hw_ste, next_table_base_39_32_size, index >> 27); - mlx5_set(ste_general, hw_ste, next_table_base_31_5_size, index); + ste_ctx->set_hit_addr(hw_ste, icm_addr, ht_size); -static void dr_ste_always_hit_htbl(struct mlx5dr_ste *ste, +static void dr_ste_always_hit_htbl(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste *ste, - mlx5_set(ste_general, hw_ste, byte_mask, next_htbl->byte_mask); - mlx5_set(ste_general, hw_ste, next_lu_type, next_htbl->lu_type); - mlx5dr_ste_set_hit_addr(hw_ste, chunk->icm_addr, chunk->num_of_entries); + ste_ctx->set_byte_mask(hw_ste, next_htbl->byte_mask); + ste_ctx->set_next_lu_type(hw_ste, next_htbl->lu_type); + ste_ctx->set_hit_addr(hw_ste, chunk->icm_addr, chunk->num_of_entries); -dr_ste_remove_head_ste(struct mlx5dr_ste *ste, +dr_ste_remove_head_ste(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste *ste, - dr_ste_always_miss_addr(&tmp_ste, miss_addr); + dr_ste_always_miss_addr(ste_ctx, &tmp_ste, miss_addr); -static void dr_ste_remove_middle_ste(struct mlx5dr_ste *ste, +static void dr_ste_remove_middle_ste(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_ste *ste, - miss_addr = dr_ste_get_miss_addr(ste->hw_ste); - mlx5dr_ste_set_miss_addr(prev_ste->hw_ste, miss_addr); + miss_addr = ste_ctx->get_miss_addr(ste->hw_ste); + ste_ctx->set_miss_addr(prev_ste->hw_ste, miss_addr); + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - dr_ste_remove_head_ste(ste, nic_matcher, + dr_ste_remove_head_ste(ste_ctx, ste, + nic_matcher, - dr_ste_remove_middle_ste(ste, &ste_info_head, &send_ste_list, stats_tbl); + dr_ste_remove_middle_ste(ste_ctx, ste, + &ste_info_head, &send_ste_list, + stats_tbl); -void mlx5dr_ste_set_hit_addr_by_next_htbl(u8 *hw_ste, +void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste, - mlx5dr_ste_set_hit_addr(hw_ste, chunk->icm_addr, chunk->num_of_entries); + ste_ctx->set_hit_addr(hw_ste, chunk->icm_addr, chunk->num_of_entries); -void mlx5dr_ste_set_formatted_ste(u16 gvmi, +void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, + u16 gvmi, - dr_ste_init(formatted_ste, htbl->lu_type, nic_dmn->ste_type, gvmi); + ste_ctx->ste_init(formatted_ste, htbl->lu_type, nic_dmn->ste_type, gvmi); - dr_ste_always_hit_htbl(&ste, connect_info->hit_next_htbl); + dr_ste_always_hit_htbl(ste_ctx, &ste, connect_info->hit_next_htbl); - dr_ste_always_miss_addr(&ste, connect_info->miss_icm_addr); + dr_ste_always_miss_addr(ste_ctx, &ste, connect_info->miss_icm_addr); - mlx5dr_ste_set_formatted_ste(dmn->info.caps.gvmi, + mlx5dr_ste_set_formatted_ste(dmn->ste_ctx, + dmn->info.caps.gvmi, - struct dr_hw_ste_format *hw_ste = (struct dr_hw_ste_format *)cur_hw_ste; + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - next_lu_type = mlx5_get(ste_general, hw_ste, next_lu_type); - byte_mask = mlx5_get(ste_general, hw_ste, byte_mask); + next_lu_type = ste_ctx->get_next_lu_type(cur_hw_ste); + byte_mask = ste_ctx->get_byte_mask(cur_hw_ste); - mlx5dr_ste_set_hit_addr_by_next_htbl(cur_hw_ste, next_htbl); + mlx5dr_ste_set_hit_addr_by_next_htbl(ste_ctx, + cur_hw_ste, next_htbl); -static void dr_ste_arr_init_next_ste(u8 **last_ste, +static void dr_ste_arr_init_next_ste(struct mlx5dr_ste_ctx *ste_ctx, + u8 **last_ste, - dr_ste_init(*last_ste, mlx5dr_ste_lu_type_dont_care, entry_type, gvmi); + ste_ctx->ste_init(*last_ste, mlx5dr_ste_lu_type_dont_care, entry_type, gvmi); -void mlx5dr_ste_set_actions_tx(struct mlx5dr_domain *dmn, +void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_domain *dmn, - dr_ste_arr_init_next_ste(&last_ste, + dr_ste_arr_init_next_ste(ste_ctx, + &last_ste, - dr_ste_arr_init_next_ste(&last_ste, + dr_ste_arr_init_next_ste(ste_ctx, + &last_ste, - mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1); + mlx5dr_ste_set_hit_addr(ste_ctx, last_ste, attr->final_icm_addr, 1); -void mlx5dr_ste_set_actions_rx(struct mlx5dr_domain *dmn, +void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_domain *dmn, - dr_ste_arr_init_next_ste(&last_ste, + dr_ste_arr_init_next_ste(ste_ctx, + &last_ste, - dr_ste_arr_init_next_ste(&last_ste, + dr_ste_arr_init_next_ste(ste_ctx, + &last_ste, - dr_ste_arr_init_next_ste(&last_ste, + dr_ste_arr_init_next_ste(ste_ctx, + &last_ste, - mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1); + mlx5dr_ste_set_hit_addr(ste_ctx, last_ste, attr->final_icm_addr, 1); + struct mlx5dr_ste_ctx *ste_ctx = dmn->ste_ctx; - dr_ste_init(ste_arr, - sb->lu_type, - nic_dmn->ste_type, - dmn->info.caps.gvmi); + ste_ctx->ste_init(ste_arr, + sb->lu_type, + nic_dmn->ste_type, + dmn->info.caps.gvmi); - mlx5_set(ste_general, ste_arr, next_lu_type, sb->lu_type); - mlx5_set(ste_general, ste_arr, byte_mask, sb->byte_mask); + ste_ctx->set_next_lu_type(ste_arr, sb->lu_type); + ste_ctx->set_byte_mask(ste_arr, sb->byte_mask); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +static void dr_ste_v0_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) +{ + u64 index = miss_addr >> 6; + + /* miss address for tx and rx stes located in the same offsets */ + mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_39_32, index >> 26); + mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_31_6, index); +} + +static u64 dr_ste_v0_get_miss_addr(u8 *hw_ste_p) +{ + u64 index = + (mlx5_get(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) | + mlx5_get(ste_rx_steering_mult, hw_ste_p, miss_address_39_32) << 26); + + return index << 6; +} + +static void dr_ste_v0_set_byte_mask(u8 *hw_ste_p, u16 byte_mask) +{ + mlx5_set(ste_general, hw_ste_p, byte_mask, byte_mask); +} + +static u16 dr_ste_v0_get_byte_mask(u8 *hw_ste_p) +{ + return mlx5_get(ste_general, hw_ste_p, byte_mask); +} + +static void dr_ste_v0_set_lu_type(u8 *hw_ste_p, u16 lu_type) +{ + mlx5_set(ste_general, hw_ste_p, entry_sub_type, lu_type); +} + +static void dr_ste_v0_set_next_lu_type(u8 *hw_ste_p, u16 lu_type) +{ + mlx5_set(ste_general, hw_ste_p, next_lu_type, lu_type); +} + +static u16 dr_ste_v0_get_next_lu_type(u8 *hw_ste_p) +{ + return mlx5_get(ste_general, hw_ste_p, next_lu_type); +} + +static void dr_ste_v0_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size) +{ + u64 index = (icm_addr >> 5) | ht_size; + + mlx5_set(ste_general, hw_ste_p, next_table_base_39_32_size, index >> 27); + mlx5_set(ste_general, hw_ste_p, next_table_base_31_5_size, index); +} + +static void dr_ste_v0_init(u8 *hw_ste_p, u16 lu_type, + u8 entry_type, u16 gvmi) +{ + mlx5_set(ste_general, hw_ste_p, entry_type, entry_type); + dr_ste_v0_set_lu_type(hw_ste_p, lu_type); + dr_ste_v0_set_next_lu_type(hw_ste_p, mlx5dr_ste_lu_type_dont_care); + + /* set gvmi once, this is the same for rx/tx + * bits 63_48 of next table base / miss address encode the next gvmi + */ + mlx5_set(ste_rx_steering_mult, hw_ste_p, gvmi, gvmi); + mlx5_set(ste_rx_steering_mult, hw_ste_p, next_table_base_63_48, gvmi); + mlx5_set(ste_rx_steering_mult, hw_ste_p, miss_address_63_48, gvmi); +} + + /* builders */ + + /* getters and setters */ + .ste_init = &dr_ste_v0_init, + .set_next_lu_type = &dr_ste_v0_set_next_lu_type, + .get_next_lu_type = &dr_ste_v0_get_next_lu_type, + .set_miss_addr = &dr_ste_v0_set_miss_addr, + .get_miss_addr = &dr_ste_v0_get_miss_addr, + .set_hit_addr = &dr_ste_v0_set_hit_addr, + .set_byte_mask = &dr_ste_v0_set_byte_mask, + .get_byte_mask = &dr_ste_v0_get_byte_mask, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h -void mlx5dr_ste_set_miss_addr(u8 *hw_ste, u64 miss_addr); -void mlx5dr_ste_set_hit_addr(u8 *hw_ste, u64 icm_addr, u32 ht_size); +void mlx5dr_ste_set_miss_addr(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste, u64 miss_addr); +void mlx5dr_ste_set_hit_addr(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste, u64 icm_addr, u32 ht_size); +void mlx5dr_ste_set_hit_addr_by_next_htbl(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste, + struct mlx5dr_ste_htbl *next_htbl); -void mlx5dr_ste_set_actions_rx(struct mlx5dr_domain *dmn, +void mlx5dr_ste_set_actions_rx(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_domain *dmn, -void mlx5dr_ste_set_actions_tx(struct mlx5dr_domain *dmn, +void mlx5dr_ste_set_actions_tx(struct mlx5dr_ste_ctx *ste_ctx, + struct mlx5dr_domain *dmn, -void mlx5dr_ste_set_hit_addr_by_next_htbl(u8 *hw_ste, - struct mlx5dr_ste_htbl *next_htbl); -void mlx5dr_ste_set_formatted_ste(u16 gvmi, +void mlx5dr_ste_set_formatted_ste(struct mlx5dr_ste_ctx *ste_ctx, + u16 gvmi,
|
Networking
|
6b93b400aa88e94f253f03e6095cd560854a5268
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add ste tx/rx actions per-device api
|
extend the ste context struct with per-device tx/rx actions.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h']
| 1
| 12
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h + + /* actions */ + void (*set_actions_rx)(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *hw_ste_arr, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes); + void (*set_actions_tx)(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *hw_ste_arr, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes);
|
Networking
|
8f9a822e596013c1c37d24d010d1b39012d3e1d2
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, move stev0 action apply logic
|
use ste tx/rx actions per-device api: move hw specific action apply logic from dr_ste to stev0 file - stev0 and stev1 actions format is different, each version should have its own implementation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 2
| 256
| 235
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -#define dr_ste_enable_flow_tag bit(31) - -enum dr_ste_tunl_action { - dr_ste_tunl_action_none = 0, - dr_ste_tunl_action_enable = 1, - dr_ste_tunl_action_decap = 2, - dr_ste_tunl_action_l3_decap = 3, - dr_ste_tunl_action_pop_vlan = 4, -}; - -enum dr_ste_action_type { - dr_ste_action_type_push_vlan = 1, - dr_ste_action_type_encap_l3 = 3, - dr_ste_action_type_encap = 4, -}; - -static void dr_ste_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag) -{ - mlx5_set(ste_rx_steering_mult, hw_ste_p, qp_list_pointer, - dr_ste_enable_flow_tag | flow_tag); -} - -static void dr_ste_set_counter_id(u8 *hw_ste_p, u32 ctr_id) -{ - /* this can be used for both rx_steering_mult and for sx_transmit */ - mlx5_set(ste_rx_steering_mult, hw_ste_p, counter_trigger_15_0, ctr_id); - mlx5_set(ste_rx_steering_mult, hw_ste_p, counter_trigger_23_16, ctr_id >> 16); -} - -static void dr_ste_set_go_back_bit(u8 *hw_ste_p) -{ - mlx5_set(ste_sx_transmit, hw_ste_p, go_back, 1); -} - -static void dr_ste_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_hdr, - bool go_back) -{ - mlx5_set(ste_sx_transmit, hw_ste_p, action_type, - dr_ste_action_type_push_vlan); - mlx5_set(ste_sx_transmit, hw_ste_p, encap_pointer_vlan_data, vlan_hdr); - /* due to hw limitation we need to set this bit, otherwise reforamt + - * push vlan will not work. - */ - if (go_back) - dr_ste_set_go_back_bit(hw_ste_p); -} - -static void dr_ste_set_tx_encap(void *hw_ste_p, u32 reformat_id, - int size, bool encap_l3) -{ - mlx5_set(ste_sx_transmit, hw_ste_p, action_type, - encap_l3 ? dr_ste_action_type_encap_l3 : dr_ste_action_type_encap); - /* the hardware expects here size in words (2 byte) */ - mlx5_set(ste_sx_transmit, hw_ste_p, action_description, size / 2); - mlx5_set(ste_sx_transmit, hw_ste_p, encap_pointer_vlan_data, reformat_id); -} - -static void dr_ste_set_rx_decap(u8 *hw_ste_p) -{ - mlx5_set(ste_rx_steering_mult, hw_ste_p, tunneling_action, - dr_ste_tunl_action_decap); -} - -static void dr_ste_set_rx_pop_vlan(u8 *hw_ste_p) -{ - mlx5_set(ste_rx_steering_mult, hw_ste_p, tunneling_action, - dr_ste_tunl_action_pop_vlan); -} - -static void dr_ste_set_rx_decap_l3(u8 *hw_ste_p, bool vlan) -{ - mlx5_set(ste_rx_steering_mult, hw_ste_p, tunneling_action, - dr_ste_tunl_action_l3_decap); - mlx5_set(ste_modify_packet, hw_ste_p, action_description, vlan ? 1 : 0); -} - -static void dr_ste_set_entry_type(u8 *hw_ste_p, u8 entry_type) -{ - mlx5_set(ste_general, hw_ste_p, entry_type, entry_type); -} - -static u8 dr_ste_get_entry_type(u8 *hw_ste_p) -{ - return mlx5_get(ste_general, hw_ste_p, entry_type); -} - -static void dr_ste_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, - u32 re_write_index) -{ - mlx5_set(ste_modify_packet, hw_ste_p, number_of_re_write_actions, - num_of_actions); - mlx5_set(ste_modify_packet, hw_ste_p, header_re_write_actions_pointer, - re_write_index); -} - -static void dr_ste_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) -{ - mlx5_set(ste_general, hw_ste_p, next_table_base_63_48, gvmi); -} - -static void dr_ste_arr_init_next_ste(struct mlx5dr_ste_ctx *ste_ctx, - u8 **last_ste, - u32 *added_stes, - enum mlx5dr_ste_entry_type entry_type, - u16 gvmi) -{ - (*added_stes)++; - *last_ste += dr_ste_size; - ste_ctx->ste_init(*last_ste, mlx5dr_ste_lu_type_dont_care, entry_type, gvmi); -} - - u8 *last_ste, + u8 *hw_ste_arr, - bool encap = action_type_set[dr_action_typ_l2_to_tnl_l2] || - action_type_set[dr_action_typ_l2_to_tnl_l3]; - - /* we want to make sure the modify header comes before l2 - * encapsulation. the reason for that is that we support - * modify headers for outer headers only - */ - if (action_type_set[dr_action_typ_modify_hdr]) { - dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); - dr_ste_set_rewrite_actions(last_ste, - attr->modify_actions, - attr->modify_index); - } - - if (action_type_set[dr_action_typ_push_vlan]) { - int i; - - for (i = 0; i < attr->vlans.count; i++) { - if (i || action_type_set[dr_action_typ_modify_hdr]) - dr_ste_arr_init_next_ste(ste_ctx, - &last_ste, - added_stes, - mlx5dr_ste_type_tx, - attr->gvmi); - - dr_ste_set_tx_push_vlan(last_ste, - attr->vlans.headers[i], - encap); - } - } - - if (encap) { - /* modify header and encapsulation require a different stes. - * since modify header ste format doesn't support encapsulation - * tunneling_action. - */ - if (action_type_set[dr_action_typ_modify_hdr] || - action_type_set[dr_action_typ_push_vlan]) - dr_ste_arr_init_next_ste(ste_ctx, - &last_ste, - added_stes, - mlx5dr_ste_type_tx, - attr->gvmi); - - dr_ste_set_tx_encap(last_ste, - attr->reformat_id, - attr->reformat_size, - action_type_set[dr_action_typ_l2_to_tnl_l3]); - /* whenever prio_tag_required enabled, we can be sure that the - * previous table (acl) already push vlan to our packet, - * and due to hw limitation we need to set this bit, otherwise - * push vlan + reformat will not work. - */ - if (mlx5_cap_gen(dmn->mdev, prio_tag_required)) - dr_ste_set_go_back_bit(last_ste); - } - - if (action_type_set[dr_action_typ_ctr]) - dr_ste_set_counter_id(last_ste, attr->ctr_id); - - dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi); - mlx5dr_ste_set_hit_addr(ste_ctx, last_ste, attr->final_icm_addr, 1); + ste_ctx->set_actions_tx(dmn, action_type_set, hw_ste_arr, + attr, added_stes); - u8 *last_ste, + u8 *hw_ste_arr, - if (action_type_set[dr_action_typ_ctr]) - dr_ste_set_counter_id(last_ste, attr->ctr_id); - - if (action_type_set[dr_action_typ_tnl_l3_to_l2]) { - dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); - dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan); - dr_ste_set_rewrite_actions(last_ste, - attr->decap_actions, - attr->decap_index); - } - - if (action_type_set[dr_action_typ_tnl_l2_to_l2]) - dr_ste_set_rx_decap(last_ste); - - if (action_type_set[dr_action_typ_pop_vlan]) { - int i; - - for (i = 0; i < attr->vlans.count; i++) { - if (i || - action_type_set[dr_action_typ_tnl_l2_to_l2] || - action_type_set[dr_action_typ_tnl_l3_to_l2]) - dr_ste_arr_init_next_ste(ste_ctx, - &last_ste, - added_stes, - mlx5dr_ste_type_rx, - attr->gvmi); - - dr_ste_set_rx_pop_vlan(last_ste); - } - } - - if (action_type_set[dr_action_typ_modify_hdr]) { - if (dr_ste_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) - dr_ste_arr_init_next_ste(ste_ctx, - &last_ste, - added_stes, - mlx5dr_ste_type_modify_pkt, - attr->gvmi); - else - dr_ste_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); - - dr_ste_set_rewrite_actions(last_ste, - attr->modify_actions, - attr->modify_index); - } - - if (action_type_set[dr_action_typ_tag]) { - if (dr_ste_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) - dr_ste_arr_init_next_ste(ste_ctx, - &last_ste, - added_stes, - mlx5dr_ste_type_rx, - attr->gvmi); - - dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag); - } - - dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi); - mlx5dr_ste_set_hit_addr(ste_ctx, last_ste, attr->final_icm_addr, 1); + ste_ctx->set_actions_rx(dmn, action_type_set, hw_ste_arr, + attr, added_stes); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +#define dr_ste_enable_flow_tag bit(31) + +enum dr_ste_tunl_action { + dr_ste_tunl_action_none = 0, + dr_ste_tunl_action_enable = 1, + dr_ste_tunl_action_decap = 2, + dr_ste_tunl_action_l3_decap = 3, + dr_ste_tunl_action_pop_vlan = 4, +}; + +enum dr_ste_action_type { + dr_ste_action_type_push_vlan = 1, + dr_ste_action_type_encap_l3 = 3, + dr_ste_action_type_encap = 4, +}; + +static void dr_ste_v0_set_entry_type(u8 *hw_ste_p, u8 entry_type) +{ + mlx5_set(ste_general, hw_ste_p, entry_type, entry_type); +} + +static u8 dr_ste_v0_get_entry_type(u8 *hw_ste_p) +{ + return mlx5_get(ste_general, hw_ste_p, entry_type); +} + +static void dr_ste_v0_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) +{ + mlx5_set(ste_general, hw_ste_p, next_table_base_63_48, gvmi); +} + - mlx5_set(ste_general, hw_ste_p, entry_type, entry_type); + dr_ste_v0_set_entry_type(hw_ste_p, entry_type); +static void dr_ste_v0_rx_set_flow_tag(u8 *hw_ste_p, u32 flow_tag) +{ + mlx5_set(ste_rx_steering_mult, hw_ste_p, qp_list_pointer, + dr_ste_enable_flow_tag | flow_tag); +} + +static void dr_ste_v0_set_counter_id(u8 *hw_ste_p, u32 ctr_id) +{ + /* this can be used for both rx_steering_mult and for sx_transmit */ + mlx5_set(ste_rx_steering_mult, hw_ste_p, counter_trigger_15_0, ctr_id); + mlx5_set(ste_rx_steering_mult, hw_ste_p, counter_trigger_23_16, ctr_id >> 16); +} + +static void dr_ste_v0_set_go_back_bit(u8 *hw_ste_p) +{ + mlx5_set(ste_sx_transmit, hw_ste_p, go_back, 1); +} + +static void dr_ste_v0_set_tx_push_vlan(u8 *hw_ste_p, u32 vlan_hdr, + bool go_back) +{ + mlx5_set(ste_sx_transmit, hw_ste_p, action_type, + dr_ste_action_type_push_vlan); + mlx5_set(ste_sx_transmit, hw_ste_p, encap_pointer_vlan_data, vlan_hdr); + /* due to hw limitation we need to set this bit, otherwise reforamt + + * push vlan will not work. + */ + if (go_back) + dr_ste_v0_set_go_back_bit(hw_ste_p); +} + +static void dr_ste_v0_set_tx_encap(void *hw_ste_p, u32 reformat_id, + int size, bool encap_l3) +{ + mlx5_set(ste_sx_transmit, hw_ste_p, action_type, + encap_l3 ? dr_ste_action_type_encap_l3 : dr_ste_action_type_encap); + /* the hardware expects here size in words (2 byte) */ + mlx5_set(ste_sx_transmit, hw_ste_p, action_description, size / 2); + mlx5_set(ste_sx_transmit, hw_ste_p, encap_pointer_vlan_data, reformat_id); +} + +static void dr_ste_v0_set_rx_decap(u8 *hw_ste_p) +{ + mlx5_set(ste_rx_steering_mult, hw_ste_p, tunneling_action, + dr_ste_tunl_action_decap); +} + +static void dr_ste_v0_set_rx_pop_vlan(u8 *hw_ste_p) +{ + mlx5_set(ste_rx_steering_mult, hw_ste_p, tunneling_action, + dr_ste_tunl_action_pop_vlan); +} + +static void dr_ste_v0_set_rx_decap_l3(u8 *hw_ste_p, bool vlan) +{ + mlx5_set(ste_rx_steering_mult, hw_ste_p, tunneling_action, + dr_ste_tunl_action_l3_decap); + mlx5_set(ste_modify_packet, hw_ste_p, action_description, vlan ? 1 : 0); +} + +static void dr_ste_v0_set_rewrite_actions(u8 *hw_ste_p, u16 num_of_actions, + u32 re_write_index) +{ + mlx5_set(ste_modify_packet, hw_ste_p, number_of_re_write_actions, + num_of_actions); + mlx5_set(ste_modify_packet, hw_ste_p, header_re_write_actions_pointer, + re_write_index); +} + +static void dr_ste_v0_arr_init_next(u8 **last_ste, + u32 *added_stes, + enum mlx5dr_ste_entry_type entry_type, + u16 gvmi) +{ + (*added_stes)++; + *last_ste += dr_ste_size; + dr_ste_v0_init(*last_ste, mlx5dr_ste_lu_type_dont_care, + entry_type, gvmi); +} + +static void +dr_ste_v0_set_actions_tx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes) +{ + bool encap = action_type_set[dr_action_typ_l2_to_tnl_l2] || + action_type_set[dr_action_typ_l2_to_tnl_l3]; + + /* we want to make sure the modify header comes before l2 + * encapsulation. the reason for that is that we support + * modify headers for outer headers only + */ + if (action_type_set[dr_action_typ_modify_hdr]) { + dr_ste_v0_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); + dr_ste_v0_set_rewrite_actions(last_ste, + attr->modify_actions, + attr->modify_index); + } + + if (action_type_set[dr_action_typ_push_vlan]) { + int i; + + for (i = 0; i < attr->vlans.count; i++) { + if (i || action_type_set[dr_action_typ_modify_hdr]) + dr_ste_v0_arr_init_next(&last_ste, + added_stes, + mlx5dr_ste_type_tx, + attr->gvmi); + + dr_ste_v0_set_tx_push_vlan(last_ste, + attr->vlans.headers[i], + encap); + } + } + + if (encap) { + /* modify header and encapsulation require a different stes. + * since modify header ste format doesn't support encapsulation + * tunneling_action. + */ + if (action_type_set[dr_action_typ_modify_hdr] || + action_type_set[dr_action_typ_push_vlan]) + dr_ste_v0_arr_init_next(&last_ste, + added_stes, + mlx5dr_ste_type_tx, + attr->gvmi); + + dr_ste_v0_set_tx_encap(last_ste, + attr->reformat_id, + attr->reformat_size, + action_type_set[dr_action_typ_l2_to_tnl_l3]); + /* whenever prio_tag_required enabled, we can be sure that the + * previous table (acl) already push vlan to our packet, + * and due to hw limitation we need to set this bit, otherwise + * push vlan + reformat will not work. + */ + if (mlx5_cap_gen(dmn->mdev, prio_tag_required)) + dr_ste_v0_set_go_back_bit(last_ste); + } + + if (action_type_set[dr_action_typ_ctr]) + dr_ste_v0_set_counter_id(last_ste, attr->ctr_id); + + dr_ste_v0_set_hit_gvmi(last_ste, attr->hit_gvmi); + dr_ste_v0_set_hit_addr(last_ste, attr->final_icm_addr, 1); +} + +static void +dr_ste_v0_set_actions_rx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes) +{ + if (action_type_set[dr_action_typ_ctr]) + dr_ste_v0_set_counter_id(last_ste, attr->ctr_id); + + if (action_type_set[dr_action_typ_tnl_l3_to_l2]) { + dr_ste_v0_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); + dr_ste_v0_set_rx_decap_l3(last_ste, attr->decap_with_vlan); + dr_ste_v0_set_rewrite_actions(last_ste, + attr->decap_actions, + attr->decap_index); + } + + if (action_type_set[dr_action_typ_tnl_l2_to_l2]) + dr_ste_v0_set_rx_decap(last_ste); + + if (action_type_set[dr_action_typ_pop_vlan]) { + int i; + + for (i = 0; i < attr->vlans.count; i++) { + if (i || + action_type_set[dr_action_typ_tnl_l2_to_l2] || + action_type_set[dr_action_typ_tnl_l3_to_l2]) + dr_ste_v0_arr_init_next(&last_ste, + added_stes, + mlx5dr_ste_type_rx, + attr->gvmi); + + dr_ste_v0_set_rx_pop_vlan(last_ste); + } + } + + if (action_type_set[dr_action_typ_modify_hdr]) { + if (dr_ste_v0_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) + dr_ste_v0_arr_init_next(&last_ste, + added_stes, + mlx5dr_ste_type_modify_pkt, + attr->gvmi); + else + dr_ste_v0_set_entry_type(last_ste, mlx5dr_ste_type_modify_pkt); + + dr_ste_v0_set_rewrite_actions(last_ste, + attr->modify_actions, + attr->modify_index); + } + + if (action_type_set[dr_action_typ_tag]) { + if (dr_ste_v0_get_entry_type(last_ste) == mlx5dr_ste_type_modify_pkt) + dr_ste_v0_arr_init_next(&last_ste, + added_stes, + mlx5dr_ste_type_rx, + attr->gvmi); + + dr_ste_v0_rx_set_flow_tag(last_ste, attr->flow_tag); + } + + dr_ste_v0_set_hit_gvmi(last_ste, attr->hit_gvmi); + dr_ste_v0_set_hit_addr(last_ste, attr->final_icm_addr, 1); +} + + + /* actions */ + .set_actions_rx = &dr_ste_v0_set_actions_rx, + .set_actions_tx = &dr_ste_v0_set_actions_tx,
|
Networking
|
ad17dc8cf9107e6513632fc61e34e0a1ab9a376f
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add ste modify header actions per-device api
|
extend the ste context struct with per-device modify header actions.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h']
| 1
| 23
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h + u32 modify_field_arr_sz; + const struct mlx5dr_ste_action_modify_field *modify_field_arr; + void (*set_action_set)(u8 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data); + void (*set_action_add)(u8 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data); + void (*set_action_copy)(u8 *hw_action, + u8 dst_hw_field, + u8 dst_shifter, + u8 dst_len, + u8 src_hw_field, + u8 src_shifter); + int (*set_action_decap_l3_list)(void *data, + u32 data_sz, + u8 *hw_action, + u32 hw_action_sz, + u16 *used_hw_action_num);
|
Networking
|
3ad5838ffb36004cdf30715ac23f7452f293fe96
|
yevgeny kliteynik saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, move stev0 modify header logic
|
move hw specific modify header fields and logic to stev0 file and use the new ste context callbacks. since stev0 and stev1 modify actions values are different, each version has its own implementation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
introduce some refactoring to sw steering to support different formats of different hardware
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 6
| 501
| 390
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--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c -struct dr_action_modify_field_conv { - u16 hw_field; - u8 start; - u8 end; - u8 l3_type; - u8 l4_type; -}; - -static const struct dr_action_modify_field_conv dr_action_conv_arr[] = { - [mlx5_action_in_field_out_smac_47_16] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l2_1, .start = 16, .end = 47, - }, - [mlx5_action_in_field_out_smac_15_0] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l2_1, .start = 0, .end = 15, - }, - [mlx5_action_in_field_out_ethertype] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l2_2, .start = 32, .end = 47, - }, - [mlx5_action_in_field_out_dmac_47_16] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l2_0, .start = 16, .end = 47, - }, - [mlx5_action_in_field_out_dmac_15_0] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l2_0, .start = 0, .end = 15, - }, - [mlx5_action_in_field_out_ip_dscp] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_1, .start = 0, .end = 5, - }, - [mlx5_action_in_field_out_tcp_flags] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_0, .start = 48, .end = 56, - .l4_type = mlx5dr_action_mdfy_hw_hdr_l4_tcp, - }, - [mlx5_action_in_field_out_tcp_sport] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_0, .start = 0, .end = 15, - .l4_type = mlx5dr_action_mdfy_hw_hdr_l4_tcp, - }, - [mlx5_action_in_field_out_tcp_dport] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_0, .start = 16, .end = 31, - .l4_type = mlx5dr_action_mdfy_hw_hdr_l4_tcp, - }, - [mlx5_action_in_field_out_ip_ttl] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_1, .start = 8, .end = 15, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv4, - }, - [mlx5_action_in_field_out_ipv6_hoplimit] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_1, .start = 8, .end = 15, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_udp_sport] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_0, .start = 0, .end = 15, - .l4_type = mlx5dr_action_mdfy_hw_hdr_l4_udp, - }, - [mlx5_action_in_field_out_udp_dport] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_0, .start = 16, .end = 31, - .l4_type = mlx5dr_action_mdfy_hw_hdr_l4_udp, - }, - [mlx5_action_in_field_out_sipv6_127_96] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_3, .start = 32, .end = 63, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_sipv6_95_64] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_3, .start = 0, .end = 31, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_sipv6_63_32] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_4, .start = 32, .end = 63, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_sipv6_31_0] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_4, .start = 0, .end = 31, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_dipv6_127_96] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_0, .start = 32, .end = 63, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_dipv6_95_64] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_0, .start = 0, .end = 31, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_dipv6_63_32] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_2, .start = 32, .end = 63, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_dipv6_31_0] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_2, .start = 0, .end = 31, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv6, - }, - [mlx5_action_in_field_out_sipv4] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_0, .start = 0, .end = 31, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv4, - }, - [mlx5_action_in_field_out_dipv4] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l3_0, .start = 32, .end = 63, - .l3_type = mlx5dr_action_mdfy_hw_hdr_l3_ipv4, - }, - [mlx5_action_in_field_metadata_reg_a] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_metadata, .start = 0, .end = 31, - }, - [mlx5_action_in_field_metadata_reg_b] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_metadata, .start = 32, .end = 63, - }, - [mlx5_action_in_field_metadata_reg_c_0] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_reg_0, .start = 32, .end = 63, - }, - [mlx5_action_in_field_metadata_reg_c_1] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_reg_0, .start = 0, .end = 31, - }, - [mlx5_action_in_field_metadata_reg_c_2] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_reg_1, .start = 32, .end = 63, - }, - [mlx5_action_in_field_metadata_reg_c_3] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_reg_1, .start = 0, .end = 31, - }, - [mlx5_action_in_field_metadata_reg_c_4] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_reg_2, .start = 32, .end = 63, - }, - [mlx5_action_in_field_metadata_reg_c_5] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_reg_2, .start = 0, .end = 31, - }, - [mlx5_action_in_field_out_tcp_seq_num] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_1, .start = 32, .end = 63, - }, - [mlx5_action_in_field_out_tcp_ack_num] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l4_1, .start = 0, .end = 31, - }, - [mlx5_action_in_field_out_first_vid] = { - .hw_field = mlx5dr_action_mdfy_hw_fld_l2_2, .start = 0, .end = 15, - }, -}; - -#define cvlan_ethertype 0x8100 -#define svlan_ethertype 0x88a8 -#define hdr_len_l2_only 14 -#define hdr_len_l2_vlan 18 -#define rewrite_hw_action_num 6 - -static int dr_actions_l2_rewrite(struct mlx5dr_domain *dmn, - struct mlx5dr_action *action, - void *data, size_t data_sz) -{ - struct mlx5_ifc_l2_hdr_bits *l2_hdr = data; - u64 ops[rewrite_hw_action_num] = {}; - u32 hdr_fld_4b; - u16 hdr_fld_2b; - u16 vlan_type; - bool vlan; - int i = 0; - int ret; - - vlan = (data_sz != hdr_len_l2_only); - - /* dmac_47_16 */ - mlx5_set(dr_action_hw_set, ops + i, - opcode, mlx5dr_action_mdfy_hw_op_set); - mlx5_set(dr_action_hw_set, ops + i, - destination_length, 0); - mlx5_set(dr_action_hw_set, ops + i, - destination_field_code, mlx5dr_action_mdfy_hw_fld_l2_0); - mlx5_set(dr_action_hw_set, ops + i, - destination_left_shifter, 16); - hdr_fld_4b = mlx5_get(l2_hdr, l2_hdr, dmac_47_16); - mlx5_set(dr_action_hw_set, ops + i, - inline_data, hdr_fld_4b); - i++; - - /* smac_47_16 */ - mlx5_set(dr_action_hw_set, ops + i, - opcode, mlx5dr_action_mdfy_hw_op_set); - mlx5_set(dr_action_hw_set, ops + i, - destination_length, 0); - mlx5_set(dr_action_hw_set, ops + i, - destination_field_code, mlx5dr_action_mdfy_hw_fld_l2_1); - mlx5_set(dr_action_hw_set, ops + i, - destination_left_shifter, 16); - hdr_fld_4b = (mlx5_get(l2_hdr, l2_hdr, smac_31_0) >> 16 | - mlx5_get(l2_hdr, l2_hdr, smac_47_32) << 16); - mlx5_set(dr_action_hw_set, ops + i, - inline_data, hdr_fld_4b); - i++; - - /* dmac_15_0 */ - mlx5_set(dr_action_hw_set, ops + i, - opcode, mlx5dr_action_mdfy_hw_op_set); - mlx5_set(dr_action_hw_set, ops + i, - destination_length, 16); - mlx5_set(dr_action_hw_set, ops + i, - destination_field_code, mlx5dr_action_mdfy_hw_fld_l2_0); - mlx5_set(dr_action_hw_set, ops + i, - destination_left_shifter, 0); - hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, dmac_15_0); - mlx5_set(dr_action_hw_set, ops + i, - inline_data, hdr_fld_2b); - i++; - - /* ethertype + (optional) vlan */ - mlx5_set(dr_action_hw_set, ops + i, - opcode, mlx5dr_action_mdfy_hw_op_set); - mlx5_set(dr_action_hw_set, ops + i, - destination_field_code, mlx5dr_action_mdfy_hw_fld_l2_2); - mlx5_set(dr_action_hw_set, ops + i, - destination_left_shifter, 32); - if (!vlan) { - hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, ethertype); - mlx5_set(dr_action_hw_set, ops + i, inline_data, hdr_fld_2b); - mlx5_set(dr_action_hw_set, ops + i, destination_length, 16); - } else { - hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, ethertype); - vlan_type = hdr_fld_2b == svlan_ethertype ? dr_ste_svlan : dr_ste_cvlan; - hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, vlan); - hdr_fld_4b = (vlan_type << 16) | hdr_fld_2b; - mlx5_set(dr_action_hw_set, ops + i, inline_data, hdr_fld_4b); - mlx5_set(dr_action_hw_set, ops + i, destination_length, 18); - } - i++; - - /* smac_15_0 */ - mlx5_set(dr_action_hw_set, ops + i, - opcode, mlx5dr_action_mdfy_hw_op_set); - mlx5_set(dr_action_hw_set, ops + i, - destination_length, 16); - mlx5_set(dr_action_hw_set, ops + i, - destination_field_code, mlx5dr_action_mdfy_hw_fld_l2_1); - mlx5_set(dr_action_hw_set, ops + i, - destination_left_shifter, 0); - hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, smac_31_0); - mlx5_set(dr_action_hw_set, ops + i, - inline_data, hdr_fld_2b); - i++; - - if (vlan) { - mlx5_set(dr_action_hw_set, ops + i, - opcode, mlx5dr_action_mdfy_hw_op_set); - hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, vlan_type); - mlx5_set(dr_action_hw_set, ops + i, - inline_data, hdr_fld_2b); - mlx5_set(dr_action_hw_set, ops + i, - destination_length, 16); - mlx5_set(dr_action_hw_set, ops + i, - destination_field_code, mlx5dr_action_mdfy_hw_fld_l2_2); - mlx5_set(dr_action_hw_set, ops + i, - destination_left_shifter, 0); - i++; - } - - action->rewrite.data = (void *)ops; - action->rewrite.num_of_actions = i; - - ret = mlx5dr_send_postsend_action(dmn, action); - if (ret) { - mlx5dr_dbg(dmn, "writing encapsulation action to icm failed "); - return ret; - } - - return 0; -} - - /* only ethernet frame is supported, with vlan (18) or without (14) */ - if (data_sz != hdr_len_l2_only && data_sz != hdr_len_l2_vlan) - return -einval; + u8 hw_actions[action_cache_line_size] = {}; + int ret; + + ret = mlx5dr_ste_set_action_decap_l3_list(dmn->ste_ctx, + data, data_sz, + hw_actions, + action_cache_line_size, + &action->rewrite.num_of_actions); + if (ret) { + mlx5dr_dbg(dmn, "failed creating decap l3 action list "); + return ret; + } - if (!action->rewrite.chunk) + if (!action->rewrite.chunk) { + mlx5dr_dbg(dmn, "failed allocating modify header chunk "); + } + action->rewrite.data = (void *)hw_actions; - ret = dr_actions_l2_rewrite(dmn, action, data, data_sz); + ret = mlx5dr_send_postsend_action(dmn, action); + mlx5dr_dbg(dmn, "writing decap l3 actions to icm failed "); +#define cvlan_ethertype 0x8100 +#define svlan_ethertype 0x88a8 + -static const struct dr_action_modify_field_conv * -dr_action_modify_get_hw_info(u16 sw_field) -{ - const struct dr_action_modify_field_conv *hw_action_info; - - if (sw_field >= array_size(dr_action_conv_arr)) - goto not_found; - - hw_action_info = &dr_action_conv_arr[sw_field]; - if (!hw_action_info->end && !hw_action_info->start) - goto not_found; - - return hw_action_info; - -not_found: - return null; -} - - const struct dr_action_modify_field_conv **ret_hw_info) + const struct mlx5dr_ste_action_modify_field **ret_hw_info) - const struct dr_action_modify_field_conv *hw_action_info; + const struct mlx5dr_ste_action_modify_field *hw_action_info; - hw_action_info = dr_action_modify_get_hw_info(sw_field); + hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); - mlx5_set(dr_action_hw_set, hw_action, - opcode, mlx5dr_action_mdfy_hw_op_add); - - mlx5_set(dr_action_hw_set, hw_action, destination_field_code, - hw_action_info->hw_field); - - mlx5_set(dr_action_hw_set, hw_action, destination_left_shifter, - hw_action_info->start); - - /* prm defines that length zero specific length of 32bits */ - mlx5_set(dr_action_hw_set, hw_action, destination_length, - max_length == 32 ? 0 : max_length); - - mlx5_set(dr_action_hw_set, hw_action, inline_data, data); + mlx5dr_ste_set_action_add(dmn->ste_ctx, + hw_action, + hw_action_info->hw_field, + hw_action_info->start, + max_length, + data); - const struct dr_action_modify_field_conv **ret_hw_info) + const struct mlx5dr_ste_action_modify_field **ret_hw_info) - const struct dr_action_modify_field_conv *hw_action_info; + const struct mlx5dr_ste_action_modify_field *hw_action_info; - hw_action_info = dr_action_modify_get_hw_info(sw_field); + hw_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, sw_field); - mlx5_set(dr_action_hw_set, hw_action, - opcode, mlx5dr_action_mdfy_hw_op_set); - - mlx5_set(dr_action_hw_set, hw_action, destination_field_code, - hw_action_info->hw_field); - - mlx5_set(dr_action_hw_set, hw_action, destination_left_shifter, - hw_action_info->start + offset); - - mlx5_set(dr_action_hw_set, hw_action, destination_length, - length == 32 ? 0 : length); - - mlx5_set(dr_action_hw_set, hw_action, inline_data, data); + mlx5dr_ste_set_action_set(dmn->ste_ctx, + hw_action, + hw_action_info->hw_field, + hw_action_info->start + offset, + length, + data); - const struct dr_action_modify_field_conv **ret_dst_hw_info, - const struct dr_action_modify_field_conv **ret_src_hw_info) + const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, + const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) - const struct dr_action_modify_field_conv *hw_dst_action_info; - const struct dr_action_modify_field_conv *hw_src_action_info; + const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; + const struct mlx5dr_ste_action_modify_field *hw_src_action_info; - hw_src_action_info = dr_action_modify_get_hw_info(src_field); - hw_dst_action_info = dr_action_modify_get_hw_info(dst_field); + hw_src_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, src_field); + hw_dst_action_info = mlx5dr_ste_conv_modify_hdr_sw_field(dmn->ste_ctx, dst_field); - mlx5_set(dr_action_hw_copy, hw_action, - opcode, mlx5dr_action_mdfy_hw_op_copy); - - mlx5_set(dr_action_hw_copy, hw_action, destination_field_code, - hw_dst_action_info->hw_field); - - mlx5_set(dr_action_hw_copy, hw_action, destination_left_shifter, - hw_dst_action_info->start + dst_offset); - - mlx5_set(dr_action_hw_copy, hw_action, destination_length, - length == 32 ? 0 : length); - - mlx5_set(dr_action_hw_copy, hw_action, source_field_code, - hw_src_action_info->hw_field); - - mlx5_set(dr_action_hw_copy, hw_action, source_left_shifter, - hw_src_action_info->start + dst_offset); + mlx5dr_ste_set_action_copy(dmn->ste_ctx, + hw_action, + hw_dst_action_info->hw_field, + hw_dst_action_info->start + dst_offset, + length, + hw_src_action_info->hw_field, + hw_src_action_info->start + src_offset); - const struct dr_action_modify_field_conv **ret_dst_hw_info, - const struct dr_action_modify_field_conv **ret_src_hw_info) + const struct mlx5dr_ste_action_modify_field **ret_dst_hw_info, + const struct mlx5dr_ste_action_modify_field **ret_src_hw_info) - const struct dr_action_modify_field_conv *hw_dst_action_info; - const struct dr_action_modify_field_conv *hw_src_action_info; - u16 hw_field = mlx5dr_action_mdfy_hw_fld_reserved; - u32 l3_type = mlx5dr_action_mdfy_hw_hdr_l3_none; - u32 l4_type = mlx5dr_action_mdfy_hw_hdr_l4_none; + const struct mlx5dr_ste_action_modify_field *hw_dst_action_info; + const struct mlx5dr_ste_action_modify_field *hw_src_action_info; + u16 hw_field = 0; + u32 l3_type = 0; + u32 l4_type = 0; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +const struct mlx5dr_ste_action_modify_field * +mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field) +{ + const struct mlx5dr_ste_action_modify_field *hw_field; + + if (sw_field >= ste_ctx->modify_field_arr_sz) + return null; + + hw_field = &ste_ctx->modify_field_arr[sw_field]; + if (!hw_field->end && !hw_field->start) + return null; + + return hw_field; +} + +void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, + __be64 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data) +{ + ste_ctx->set_action_set((u8 *)hw_action, + hw_field, shifter, length, data); +} + +void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, + __be64 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data) +{ + ste_ctx->set_action_add((u8 *)hw_action, + hw_field, shifter, length, data); +} + +void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, + __be64 *hw_action, + u8 dst_hw_field, + u8 dst_shifter, + u8 dst_len, + u8 src_hw_field, + u8 src_shifter) +{ + ste_ctx->set_action_copy((u8 *)hw_action, + dst_hw_field, dst_shifter, dst_len, + src_hw_field, src_shifter); +} + +int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, + void *data, u32 data_sz, + u8 *hw_action, u32 hw_action_sz, + u16 *used_hw_action_num) +{ + /* only ethernet frame is supported, with vlan (18) or without (14) */ + if (data_sz != hdr_len_l2 && data_sz != hdr_len_l2_w_vlan) + return -einval; + + return ste_ctx->set_action_decap_l3_list(data, data_sz, + hw_action, hw_action_sz, + used_hw_action_num); +} + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +#define hdr_len_l2_macs 0xc +#define hdr_len_l2_vlan 0x4 +#define hdr_len_l2_ether 0x2 +#define hdr_len_l2 (hdr_len_l2_macs + hdr_len_l2_ether) +#define hdr_len_l2_w_vlan (hdr_len_l2 + hdr_len_l2_vlan) +enum dr_ste_action_modify_type_l3 { + dr_ste_action_mdfy_type_l3_none = 0x0, + dr_ste_action_mdfy_type_l3_ipv4 = 0x1, + dr_ste_action_mdfy_type_l3_ipv6 = 0x2, +}; + +enum dr_ste_action_modify_type_l4 { + dr_ste_action_mdfy_type_l4_none = 0x0, + dr_ste_action_mdfy_type_l4_tcp = 0x1, + dr_ste_action_mdfy_type_l4_udp = 0x2, +}; + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c -#define dr_ste_enable_flow_tag bit(31) +#define svlan_ethertype 0x88a8 +#define dr_ste_enable_flow_tag bit(31) -enum dr_ste_tunl_action { +enum dr_ste_v0_action_tunl { -enum dr_ste_action_type { +enum dr_ste_v0_action_type { +enum dr_ste_v0_action_mdfy_op { + dr_ste_action_mdfy_op_copy = 0x1, + dr_ste_action_mdfy_op_set = 0x2, + dr_ste_action_mdfy_op_add = 0x3, +}; + +enum { + dr_ste_v0_action_mdfy_fld_l2_0 = 0, + dr_ste_v0_action_mdfy_fld_l2_1 = 1, + dr_ste_v0_action_mdfy_fld_l2_2 = 2, + dr_ste_v0_action_mdfy_fld_l3_0 = 3, + dr_ste_v0_action_mdfy_fld_l3_1 = 4, + dr_ste_v0_action_mdfy_fld_l3_2 = 5, + dr_ste_v0_action_mdfy_fld_l3_3 = 6, + dr_ste_v0_action_mdfy_fld_l3_4 = 7, + dr_ste_v0_action_mdfy_fld_l4_0 = 8, + dr_ste_v0_action_mdfy_fld_l4_1 = 9, + dr_ste_v0_action_mdfy_fld_mpls = 10, + dr_ste_v0_action_mdfy_fld_l2_tnl_0 = 11, + dr_ste_v0_action_mdfy_fld_reg_0 = 12, + dr_ste_v0_action_mdfy_fld_reg_1 = 13, + dr_ste_v0_action_mdfy_fld_reg_2 = 14, + dr_ste_v0_action_mdfy_fld_reg_3 = 15, + dr_ste_v0_action_mdfy_fld_l4_2 = 16, + dr_ste_v0_action_mdfy_fld_flex_0 = 17, + dr_ste_v0_action_mdfy_fld_flex_1 = 18, + dr_ste_v0_action_mdfy_fld_flex_2 = 19, + dr_ste_v0_action_mdfy_fld_flex_3 = 20, + dr_ste_v0_action_mdfy_fld_l2_tnl_1 = 21, + dr_ste_v0_action_mdfy_fld_metadata = 22, + dr_ste_v0_action_mdfy_fld_reserved = 23, +}; + +static const struct mlx5dr_ste_action_modify_field dr_ste_v0_action_modify_field_arr[] = { + [mlx5_action_in_field_out_smac_47_16] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l2_1, .start = 16, .end = 47, + }, + [mlx5_action_in_field_out_smac_15_0] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l2_1, .start = 0, .end = 15, + }, + [mlx5_action_in_field_out_ethertype] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l2_2, .start = 32, .end = 47, + }, + [mlx5_action_in_field_out_dmac_47_16] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l2_0, .start = 16, .end = 47, + }, + [mlx5_action_in_field_out_dmac_15_0] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l2_0, .start = 0, .end = 15, + }, + [mlx5_action_in_field_out_ip_dscp] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_1, .start = 0, .end = 5, + }, + [mlx5_action_in_field_out_tcp_flags] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_0, .start = 48, .end = 56, + .l4_type = dr_ste_action_mdfy_type_l4_tcp, + }, + [mlx5_action_in_field_out_tcp_sport] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_0, .start = 0, .end = 15, + .l4_type = dr_ste_action_mdfy_type_l4_tcp, + }, + [mlx5_action_in_field_out_tcp_dport] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_0, .start = 16, .end = 31, + .l4_type = dr_ste_action_mdfy_type_l4_tcp, + }, + [mlx5_action_in_field_out_ip_ttl] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_1, .start = 8, .end = 15, + .l3_type = dr_ste_action_mdfy_type_l3_ipv4, + }, + [mlx5_action_in_field_out_ipv6_hoplimit] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_1, .start = 8, .end = 15, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_udp_sport] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_0, .start = 0, .end = 15, + .l4_type = dr_ste_action_mdfy_type_l4_udp, + }, + [mlx5_action_in_field_out_udp_dport] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_0, .start = 16, .end = 31, + .l4_type = dr_ste_action_mdfy_type_l4_udp, + }, + [mlx5_action_in_field_out_sipv6_127_96] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_3, .start = 32, .end = 63, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv6_95_64] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_3, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv6_63_32] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_4, .start = 32, .end = 63, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv6_31_0] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_4, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_127_96] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_0, .start = 32, .end = 63, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_95_64] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_0, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_63_32] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_2, .start = 32, .end = 63, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_31_0] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_2, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv4] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_0, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv4, + }, + [mlx5_action_in_field_out_dipv4] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l3_0, .start = 32, .end = 63, + .l3_type = dr_ste_action_mdfy_type_l3_ipv4, + }, + [mlx5_action_in_field_metadata_reg_a] = { + .hw_field = dr_ste_v0_action_mdfy_fld_metadata, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_b] = { + .hw_field = dr_ste_v0_action_mdfy_fld_metadata, .start = 32, .end = 63, + }, + [mlx5_action_in_field_metadata_reg_c_0] = { + .hw_field = dr_ste_v0_action_mdfy_fld_reg_0, .start = 32, .end = 63, + }, + [mlx5_action_in_field_metadata_reg_c_1] = { + .hw_field = dr_ste_v0_action_mdfy_fld_reg_0, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_2] = { + .hw_field = dr_ste_v0_action_mdfy_fld_reg_1, .start = 32, .end = 63, + }, + [mlx5_action_in_field_metadata_reg_c_3] = { + .hw_field = dr_ste_v0_action_mdfy_fld_reg_1, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_4] = { + .hw_field = dr_ste_v0_action_mdfy_fld_reg_2, .start = 32, .end = 63, + }, + [mlx5_action_in_field_metadata_reg_c_5] = { + .hw_field = dr_ste_v0_action_mdfy_fld_reg_2, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_tcp_seq_num] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_1, .start = 32, .end = 63, + }, + [mlx5_action_in_field_out_tcp_ack_num] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l4_1, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_first_vid] = { + .hw_field = dr_ste_v0_action_mdfy_fld_l2_2, .start = 0, .end = 15, + }, +}; + +static void dr_ste_v0_set_action_set(u8 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data) +{ + length = (length == 32) ? 0 : length; + mlx5_set(dr_action_hw_set, hw_action, opcode, dr_ste_action_mdfy_op_set); + mlx5_set(dr_action_hw_set, hw_action, destination_field_code, hw_field); + mlx5_set(dr_action_hw_set, hw_action, destination_left_shifter, shifter); + mlx5_set(dr_action_hw_set, hw_action, destination_length, length); + mlx5_set(dr_action_hw_set, hw_action, inline_data, data); +} + +static void dr_ste_v0_set_action_add(u8 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data) +{ + length = (length == 32) ? 0 : length; + mlx5_set(dr_action_hw_set, hw_action, opcode, dr_ste_action_mdfy_op_add); + mlx5_set(dr_action_hw_set, hw_action, destination_field_code, hw_field); + mlx5_set(dr_action_hw_set, hw_action, destination_left_shifter, shifter); + mlx5_set(dr_action_hw_set, hw_action, destination_length, length); + mlx5_set(dr_action_hw_set, hw_action, inline_data, data); +} + +static void dr_ste_v0_set_action_copy(u8 *hw_action, + u8 dst_hw_field, + u8 dst_shifter, + u8 dst_len, + u8 src_hw_field, + u8 src_shifter) +{ + mlx5_set(dr_action_hw_copy, hw_action, opcode, dr_ste_action_mdfy_op_copy); + mlx5_set(dr_action_hw_copy, hw_action, destination_field_code, dst_hw_field); + mlx5_set(dr_action_hw_copy, hw_action, destination_left_shifter, dst_shifter); + mlx5_set(dr_action_hw_copy, hw_action, destination_length, dst_len); + mlx5_set(dr_action_hw_copy, hw_action, source_field_code, src_hw_field); + mlx5_set(dr_action_hw_copy, hw_action, source_left_shifter, src_shifter); +} + +#define dr_ste_decap_l3_min_action_num 5 + +static int +dr_ste_v0_set_action_decap_l3_list(void *data, u32 data_sz, + u8 *hw_action, u32 hw_action_sz, + u16 *used_hw_action_num) +{ + struct mlx5_ifc_l2_hdr_bits *l2_hdr = data; + u32 hw_action_num; + int required_actions; + u32 hdr_fld_4b; + u16 hdr_fld_2b; + u16 vlan_type; + bool vlan; + + vlan = (data_sz != hdr_len_l2); + hw_action_num = hw_action_sz / mlx5_st_sz_bytes(dr_action_hw_set); + required_actions = dr_ste_decap_l3_min_action_num + !!vlan; + + if (hw_action_num < required_actions) + return -enomem; + + /* dmac_47_16 */ + mlx5_set(dr_action_hw_set, hw_action, + opcode, dr_ste_action_mdfy_op_set); + mlx5_set(dr_action_hw_set, hw_action, + destination_length, 0); + mlx5_set(dr_action_hw_set, hw_action, + destination_field_code, dr_ste_v0_action_mdfy_fld_l2_0); + mlx5_set(dr_action_hw_set, hw_action, + destination_left_shifter, 16); + hdr_fld_4b = mlx5_get(l2_hdr, l2_hdr, dmac_47_16); + mlx5_set(dr_action_hw_set, hw_action, + inline_data, hdr_fld_4b); + hw_action += mlx5_st_sz_bytes(dr_action_hw_set); + + /* smac_47_16 */ + mlx5_set(dr_action_hw_set, hw_action, + opcode, dr_ste_action_mdfy_op_set); + mlx5_set(dr_action_hw_set, hw_action, + destination_length, 0); + mlx5_set(dr_action_hw_set, hw_action, + destination_field_code, dr_ste_v0_action_mdfy_fld_l2_1); + mlx5_set(dr_action_hw_set, hw_action, destination_left_shifter, 16); + hdr_fld_4b = (mlx5_get(l2_hdr, l2_hdr, smac_31_0) >> 16 | + mlx5_get(l2_hdr, l2_hdr, smac_47_32) << 16); + mlx5_set(dr_action_hw_set, hw_action, inline_data, hdr_fld_4b); + hw_action += mlx5_st_sz_bytes(dr_action_hw_set); + + /* dmac_15_0 */ + mlx5_set(dr_action_hw_set, hw_action, + opcode, dr_ste_action_mdfy_op_set); + mlx5_set(dr_action_hw_set, hw_action, + destination_length, 16); + mlx5_set(dr_action_hw_set, hw_action, + destination_field_code, dr_ste_v0_action_mdfy_fld_l2_0); + mlx5_set(dr_action_hw_set, hw_action, + destination_left_shifter, 0); + hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, dmac_15_0); + mlx5_set(dr_action_hw_set, hw_action, + inline_data, hdr_fld_2b); + hw_action += mlx5_st_sz_bytes(dr_action_hw_set); + + /* ethertype + (optional) vlan */ + mlx5_set(dr_action_hw_set, hw_action, + opcode, dr_ste_action_mdfy_op_set); + mlx5_set(dr_action_hw_set, hw_action, + destination_field_code, dr_ste_v0_action_mdfy_fld_l2_2); + mlx5_set(dr_action_hw_set, hw_action, + destination_left_shifter, 32); + if (!vlan) { + hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, ethertype); + mlx5_set(dr_action_hw_set, hw_action, inline_data, hdr_fld_2b); + mlx5_set(dr_action_hw_set, hw_action, destination_length, 16); + } else { + hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, ethertype); + vlan_type = hdr_fld_2b == svlan_ethertype ? dr_ste_svlan : dr_ste_cvlan; + hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, vlan); + hdr_fld_4b = (vlan_type << 16) | hdr_fld_2b; + mlx5_set(dr_action_hw_set, hw_action, inline_data, hdr_fld_4b); + mlx5_set(dr_action_hw_set, hw_action, destination_length, 18); + } + hw_action += mlx5_st_sz_bytes(dr_action_hw_set); + + /* smac_15_0 */ + mlx5_set(dr_action_hw_set, hw_action, + opcode, dr_ste_action_mdfy_op_set); + mlx5_set(dr_action_hw_set, hw_action, + destination_length, 16); + mlx5_set(dr_action_hw_set, hw_action, + destination_field_code, dr_ste_v0_action_mdfy_fld_l2_1); + mlx5_set(dr_action_hw_set, hw_action, + destination_left_shifter, 0); + hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, smac_31_0); + mlx5_set(dr_action_hw_set, hw_action, inline_data, hdr_fld_2b); + hw_action += mlx5_st_sz_bytes(dr_action_hw_set); + + if (vlan) { + mlx5_set(dr_action_hw_set, hw_action, + opcode, dr_ste_action_mdfy_op_set); + hdr_fld_2b = mlx5_get(l2_hdr, l2_hdr, vlan_type); + mlx5_set(dr_action_hw_set, hw_action, + inline_data, hdr_fld_2b); + mlx5_set(dr_action_hw_set, hw_action, + destination_length, 16); + mlx5_set(dr_action_hw_set, hw_action, + destination_field_code, dr_ste_v0_action_mdfy_fld_l2_2); + mlx5_set(dr_action_hw_set, hw_action, + destination_left_shifter, 0); + } + + *used_hw_action_num = required_actions; + + return 0; +} + + .modify_field_arr_sz = array_size(dr_ste_v0_action_modify_field_arr), + .modify_field_arr = dr_ste_v0_action_modify_field_arr, + .set_action_set = &dr_ste_v0_set_action_set, + .set_action_add = &dr_ste_v0_set_action_add, + .set_action_copy = &dr_ste_v0_set_action_copy, + .set_action_decap_l3_list = &dr_ste_v0_set_action_decap_l3_list, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +void mlx5dr_ste_set_action_set(struct mlx5dr_ste_ctx *ste_ctx, + __be64 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data); +void mlx5dr_ste_set_action_add(struct mlx5dr_ste_ctx *ste_ctx, + __be64 *hw_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data); +void mlx5dr_ste_set_action_copy(struct mlx5dr_ste_ctx *ste_ctx, + __be64 *hw_action, + u8 dst_hw_field, + u8 dst_shifter, + u8 dst_len, + u8 src_hw_field, + u8 src_shifter); +int mlx5dr_ste_set_action_decap_l3_list(struct mlx5dr_ste_ctx *ste_ctx, + void *data, + u32 data_sz, + u8 *hw_action, + u32 hw_action_sz, + u16 *used_hw_action_num); + +const struct mlx5dr_ste_action_modify_field * +mlx5dr_ste_conv_modify_hdr_sw_field(struct mlx5dr_ste_ctx *ste_ctx, u16 sw_field); + +struct mlx5dr_ste_action_modify_field { + u16 hw_field; + u8 start; + u8 end; + u8 l3_type; + u8 l4_type; +}; + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr.h -enum { - mlx5dr_action_mdfy_hw_fld_l2_0 = 0, - mlx5dr_action_mdfy_hw_fld_l2_1 = 1, - mlx5dr_action_mdfy_hw_fld_l2_2 = 2, - mlx5dr_action_mdfy_hw_fld_l3_0 = 3, - mlx5dr_action_mdfy_hw_fld_l3_1 = 4, - mlx5dr_action_mdfy_hw_fld_l3_2 = 5, - mlx5dr_action_mdfy_hw_fld_l3_3 = 6, - mlx5dr_action_mdfy_hw_fld_l3_4 = 7, - mlx5dr_action_mdfy_hw_fld_l4_0 = 8, - mlx5dr_action_mdfy_hw_fld_l4_1 = 9, - mlx5dr_action_mdfy_hw_fld_mpls = 10, - mlx5dr_action_mdfy_hw_fld_l2_tnl_0 = 11, - mlx5dr_action_mdfy_hw_fld_reg_0 = 12, - mlx5dr_action_mdfy_hw_fld_reg_1 = 13, - mlx5dr_action_mdfy_hw_fld_reg_2 = 14, - mlx5dr_action_mdfy_hw_fld_reg_3 = 15, - mlx5dr_action_mdfy_hw_fld_l4_2 = 16, - mlx5dr_action_mdfy_hw_fld_flex_0 = 17, - mlx5dr_action_mdfy_hw_fld_flex_1 = 18, - mlx5dr_action_mdfy_hw_fld_flex_2 = 19, - mlx5dr_action_mdfy_hw_fld_flex_3 = 20, - mlx5dr_action_mdfy_hw_fld_l2_tnl_1 = 21, - mlx5dr_action_mdfy_hw_fld_metadata = 22, - mlx5dr_action_mdfy_hw_fld_reserved = 23, -}; - -enum { - mlx5dr_action_mdfy_hw_op_copy = 0x1, - mlx5dr_action_mdfy_hw_op_set = 0x2, - mlx5dr_action_mdfy_hw_op_add = 0x3, -}; - -enum { - mlx5dr_action_mdfy_hw_hdr_l3_none = 0x0, - mlx5dr_action_mdfy_hw_hdr_l3_ipv4 = 0x1, - mlx5dr_action_mdfy_hw_hdr_l3_ipv6 = 0x2, -}; - -enum { - mlx5dr_action_mdfy_hw_hdr_l4_none = 0x0, - mlx5dr_action_mdfy_hw_hdr_l4_tcp = 0x1, - mlx5dr_action_mdfy_hw_hdr_l4_udp = 0x2, -}; -
|
Networking
|
4781df92f4dab5ca6928390c3cf4bfba9730a526
|
yevgeny kliteynik alex vesker valex nvidia com saeed mahameed saeedm nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, fix potential shift wrapping of 32-bit value
|
fix 32-bit variable shift wrapping in dr_ste_v0_get_miss_addr.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 2
| 2
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v0.c - (mlx5_get(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) | - mlx5_get(ste_rx_steering_mult, hw_ste_p, miss_address_39_32) << 26); + ((u64)mlx5_get(ste_rx_steering_mult, hw_ste_p, miss_address_31_6) | + ((u64)mlx5_get(ste_rx_steering_mult, hw_ste_p, miss_address_39_32)) << 26);
|
Networking
|
bdbc13c204ee3e742289730618002ff9f21109bf
|
yevgeny kliteynik alex vesker valex nvidia com
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add match stev1 structs to ifc
|
add mlx5_ifc_dr_ste_v1.h - a new header with hw specific ste structs for version 1.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h']
| 1
| 273
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +/* spdx-license-identifier: gpl-2.0 or linux-openib */ +/* copyright (c) 2020 nvidia corporation. all rights reserved. */ + +#ifndef mlx5_ifc_dr_ste_v1_h +#define mlx5_ifc_dr_ste_v1_h + +struct mlx5_ifc_ste_eth_l2_src_v1_bits { + u8 reserved_at_0[0x1]; + u8 sx_sniffer[0x1]; + u8 functional_loopback[0x1]; + u8 ip_fragmented[0x1]; + u8 qp_type[0x2]; + u8 encapsulation_type[0x2]; + u8 port[0x2]; + u8 l3_type[0x2]; + u8 l4_type[0x2]; + u8 first_vlan_qualifier[0x2]; + u8 first_priority[0x3]; + u8 first_cfi[0x1]; + u8 first_vlan_id[0xc]; + + u8 smac_47_16[0x20]; + + u8 smac_15_0[0x10]; + u8 l3_ethertype[0x10]; + + u8 reserved_at_60[0x6]; + u8 tcp_syn[0x1]; + u8 reserved_at_67[0x3]; + u8 force_loopback[0x1]; + u8 l2_ok[0x1]; + u8 l3_ok[0x1]; + u8 l4_ok[0x1]; + u8 second_vlan_qualifier[0x2]; + + u8 second_priority[0x3]; + u8 second_cfi[0x1]; + u8 second_vlan_id[0xc]; +}; + +struct mlx5_ifc_ste_eth_l2_dst_v1_bits { + u8 reserved_at_0[0x1]; + u8 sx_sniffer[0x1]; + u8 functional_lb[0x1]; + u8 ip_fragmented[0x1]; + u8 qp_type[0x2]; + u8 encapsulation_type[0x2]; + u8 port[0x2]; + u8 l3_type[0x2]; + u8 l4_type[0x2]; + u8 first_vlan_qualifier[0x2]; + u8 first_priority[0x3]; + u8 first_cfi[0x1]; + u8 first_vlan_id[0xc]; + + u8 dmac_47_16[0x20]; + + u8 dmac_15_0[0x10]; + u8 l3_ethertype[0x10]; + + u8 reserved_at_60[0x6]; + u8 tcp_syn[0x1]; + u8 reserved_at_67[0x3]; + u8 force_lb[0x1]; + u8 l2_ok[0x1]; + u8 l3_ok[0x1]; + u8 l4_ok[0x1]; + u8 second_vlan_qualifier[0x2]; + u8 second_priority[0x3]; + u8 second_cfi[0x1]; + u8 second_vlan_id[0xc]; +}; + +struct mlx5_ifc_ste_eth_l2_src_dst_v1_bits { + u8 dmac_47_16[0x20]; + + u8 smac_47_16[0x20]; + + u8 dmac_15_0[0x10]; + u8 reserved_at_50[0x2]; + u8 functional_lb[0x1]; + u8 reserved_at_53[0x5]; + u8 port[0x2]; + u8 l3_type[0x2]; + u8 reserved_at_5c[0x2]; + u8 first_vlan_qualifier[0x2]; + + u8 first_priority[0x3]; + u8 first_cfi[0x1]; + u8 first_vlan_id[0xc]; + u8 smac_15_0[0x10]; +}; + +struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_v1_bits { + u8 source_address[0x20]; + + u8 destination_address[0x20]; + + u8 source_port[0x10]; + u8 destination_port[0x10]; + + u8 reserved_at_60[0x4]; + u8 l4_ok[0x1]; + u8 l3_ok[0x1]; + u8 fragmented[0x1]; + u8 tcp_ns[0x1]; + u8 tcp_cwr[0x1]; + u8 tcp_ece[0x1]; + u8 tcp_urg[0x1]; + u8 tcp_ack[0x1]; + u8 tcp_psh[0x1]; + u8 tcp_rst[0x1]; + u8 tcp_syn[0x1]; + u8 tcp_fin[0x1]; + u8 dscp[0x6]; + u8 ecn[0x2]; + u8 protocol[0x8]; +}; + +struct mlx5_ifc_ste_eth_l2_tnl_v1_bits { + u8 l2_tunneling_network_id[0x20]; + + u8 dmac_47_16[0x20]; + + u8 dmac_15_0[0x10]; + u8 l3_ethertype[0x10]; + + u8 reserved_at_60[0x3]; + u8 ip_fragmented[0x1]; + u8 reserved_at_64[0x2]; + u8 encp_type[0x2]; + u8 reserved_at_68[0x2]; + u8 l3_type[0x2]; + u8 l4_type[0x2]; + u8 first_vlan_qualifier[0x2]; + u8 first_priority[0x3]; + u8 first_cfi[0x1]; + u8 first_vlan_id[0xc]; +}; + +struct mlx5_ifc_ste_eth_l3_ipv4_misc_v1_bits { + u8 identification[0x10]; + u8 flags[0x3]; + u8 fragment_offset[0xd]; + + u8 total_length[0x10]; + u8 checksum[0x10]; + + u8 version[0x4]; + u8 ihl[0x4]; + u8 time_to_live[0x8]; + u8 reserved_at_50[0x10]; + + u8 reserved_at_60[0x1c]; + u8 voq_internal_prio[0x4]; +}; + +struct mlx5_ifc_ste_eth_l4_v1_bits { + u8 ipv6_version[0x4]; + u8 reserved_at_4[0x4]; + u8 dscp[0x6]; + u8 ecn[0x2]; + u8 ipv6_hop_limit[0x8]; + u8 protocol[0x8]; + + u8 src_port[0x10]; + u8 dst_port[0x10]; + + u8 first_fragment[0x1]; + u8 reserved_at_41[0xb]; + u8 flow_label[0x14]; + + u8 tcp_data_offset[0x4]; + u8 l4_ok[0x1]; + u8 l3_ok[0x1]; + u8 fragmented[0x1]; + u8 tcp_ns[0x1]; + u8 tcp_cwr[0x1]; + u8 tcp_ece[0x1]; + u8 tcp_urg[0x1]; + u8 tcp_ack[0x1]; + u8 tcp_psh[0x1]; + u8 tcp_rst[0x1]; + u8 tcp_syn[0x1]; + u8 tcp_fin[0x1]; + u8 ipv6_paylen[0x10]; +}; + +struct mlx5_ifc_ste_eth_l4_misc_v1_bits { + u8 window_size[0x10]; + u8 urgent_pointer[0x10]; + + u8 ack_num[0x20]; + + u8 seq_num[0x20]; + + u8 length[0x10]; + u8 checksum[0x10]; +}; + +struct mlx5_ifc_ste_mpls_v1_bits { + u8 reserved_at_0[0x15]; + u8 mpls_ok[0x1]; + u8 mpls4_s_bit[0x1]; + u8 mpls4_qualifier[0x1]; + u8 mpls3_s_bit[0x1]; + u8 mpls3_qualifier[0x1]; + u8 mpls2_s_bit[0x1]; + u8 mpls2_qualifier[0x1]; + u8 mpls1_s_bit[0x1]; + u8 mpls1_qualifier[0x1]; + u8 mpls0_s_bit[0x1]; + u8 mpls0_qualifier[0x1]; + + u8 mpls0_label[0x14]; + u8 mpls0_exp[0x3]; + u8 mpls0_s_bos[0x1]; + u8 mpls0_ttl[0x8]; + + u8 mpls1_label[0x20]; + + u8 mpls2_label[0x20]; +}; + +struct mlx5_ifc_ste_gre_v1_bits { + u8 gre_c_present[0x1]; + u8 reserved_at_1[0x1]; + u8 gre_k_present[0x1]; + u8 gre_s_present[0x1]; + u8 strict_src_route[0x1]; + u8 recur[0x3]; + u8 flags[0x5]; + u8 version[0x3]; + u8 gre_protocol[0x10]; + + u8 reserved_at_20[0x20]; + + u8 gre_key_h[0x18]; + u8 gre_key_l[0x8]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_ste_src_gvmi_qp_v1_bits { + u8 loopback_synd[0x8]; + u8 reserved_at_8[0x7]; + u8 functional_lb[0x1]; + u8 source_gvmi[0x10]; + + u8 force_lb[0x1]; + u8 reserved_at_21[0x1]; + u8 source_is_requestor[0x1]; + u8 reserved_at_23[0x5]; + u8 source_qp[0x18]; + + u8 reserved_at_40[0x20]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_ste_icmp_v1_bits { + u8 icmp_payload_data[0x20]; + + u8 icmp_header_data[0x20]; + + u8 icmp_type[0x8]; + u8 icmp_code[0x8]; + u8 reserved_at_50[0x10]; + + u8 reserved_at_60[0x20]; +}; + +#endif /* mlx5_ifc_dr_ste_v1_h */
|
Networking
|
3a77c238909b354b25c8d58ea541c44e14030ba8
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add hw stev1 match logic
|
add stev1 match logic to a new file. this file will be used for hw specific stev1.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c', 'makefile']
| 4
| 911
| 2
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/makefile b/drivers/net/ethernet/mellanox/mlx5/core/makefile --- a/drivers/net/ethernet/mellanox/mlx5/core/makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/makefile - steering/dr_ste_v0.o \ + steering/dr_ste_v0.o steering/dr_ste_v1.o \ diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c - [mlx5_steering_format_connectx_6dx] = null, + [mlx5_steering_format_connectx_6dx] = &ste_ctx_v1, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +extern struct mlx5dr_ste_ctx ste_ctx_v1; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +// spdx-license-identifier: gpl-2.0 or linux-openib +/* copyright (c) 2020 nvidia corporation. all rights reserved. */ + +#include <linux/types.h> +#include "mlx5_ifc_dr_ste_v1.h" +#include "dr_ste.h" + +#define dr_ste_calc_dfnr_type(lookup_type, inner) \ + ((inner) ? dr_ste_v1_lu_type_##lookup_type##_i : \ + dr_ste_v1_lu_type_##lookup_type##_o) + +enum dr_ste_v1_entry_format { + dr_ste_v1_type_bwc_byte = 0x0, + dr_ste_v1_type_bwc_dw = 0x1, + dr_ste_v1_type_match = 0x2, +}; + +/* lookup type is built from 2b: [ definer mode 1b ][ definer index 1b ] */ +enum { + dr_ste_v1_lu_type_nop = 0x0000, + dr_ste_v1_lu_type_ethl2_tnl = 0x0002, + dr_ste_v1_lu_type_ibl3_ext = 0x0102, + dr_ste_v1_lu_type_ethl2_o = 0x0003, + dr_ste_v1_lu_type_ibl4 = 0x0103, + dr_ste_v1_lu_type_ethl2_i = 0x0004, + dr_ste_v1_lu_type_src_qp_gvmi = 0x0104, + dr_ste_v1_lu_type_ethl2_src_o = 0x0005, + dr_ste_v1_lu_type_ethl2_headers_o = 0x0105, + dr_ste_v1_lu_type_ethl2_src_i = 0x0006, + dr_ste_v1_lu_type_ethl2_headers_i = 0x0106, + dr_ste_v1_lu_type_ethl3_ipv4_5_tuple_o = 0x0007, + dr_ste_v1_lu_type_ipv6_des_o = 0x0107, + dr_ste_v1_lu_type_ethl3_ipv4_5_tuple_i = 0x0008, + dr_ste_v1_lu_type_ipv6_des_i = 0x0108, + dr_ste_v1_lu_type_ethl4_o = 0x0009, + dr_ste_v1_lu_type_ipv6_src_o = 0x0109, + dr_ste_v1_lu_type_ethl4_i = 0x000a, + dr_ste_v1_lu_type_ipv6_src_i = 0x010a, + dr_ste_v1_lu_type_ethl2_src_dst_o = 0x000b, + dr_ste_v1_lu_type_mpls_o = 0x010b, + dr_ste_v1_lu_type_ethl2_src_dst_i = 0x000c, + dr_ste_v1_lu_type_mpls_i = 0x010c, + dr_ste_v1_lu_type_ethl3_ipv4_misc_o = 0x000d, + dr_ste_v1_lu_type_gre = 0x010d, + dr_ste_v1_lu_type_flex_parser_tnl_header = 0x000e, + dr_ste_v1_lu_type_general_purpose = 0x010e, + dr_ste_v1_lu_type_ethl3_ipv4_misc_i = 0x000f, + dr_ste_v1_lu_type_steering_registers_0 = 0x010f, + dr_ste_v1_lu_type_steering_registers_1 = 0x0110, + dr_ste_v1_lu_type_flex_parser_0 = 0x0111, + dr_ste_v1_lu_type_flex_parser_1 = 0x0112, + dr_ste_v1_lu_type_ethl4_misc_o = 0x0113, + dr_ste_v1_lu_type_ethl4_misc_i = 0x0114, + dr_ste_v1_lu_type_invalid = 0x00ff, + dr_ste_v1_lu_type_dont_care = mlx5dr_ste_lu_type_dont_care, +}; + +static void dr_ste_v1_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, dmac_15_0, mask, dmac_15_0); + + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, smac_47_16, mask, smac_47_16); + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, smac_15_0, mask, smac_15_0); + + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_tag(eth_l2_src_dst_v1, bit_mask, first_priority, mask, first_prio); + dr_ste_set_ones(eth_l2_src_dst_v1, bit_mask, l3_type, mask, ip_version); + + if (mask->cvlan_tag) { + mlx5_set(ste_eth_l2_src_dst_v1, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + } else if (mask->svlan_tag) { + mlx5_set(ste_eth_l2_src_dst_v1, bit_mask, first_vlan_qualifier, -1); + mask->svlan_tag = 0; + } +} + +static int dr_ste_v1_build_eth_l2_src_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_src_dst_v1, tag, dmac_47_16, spec, dmac_47_16); + dr_ste_set_tag(eth_l2_src_dst_v1, tag, dmac_15_0, spec, dmac_15_0); + + dr_ste_set_tag(eth_l2_src_dst_v1, tag, smac_47_16, spec, smac_47_16); + dr_ste_set_tag(eth_l2_src_dst_v1, tag, smac_15_0, spec, smac_15_0); + + if (spec->ip_version == ip_version_ipv4) { + mlx5_set(ste_eth_l2_src_dst_v1, tag, l3_type, ste_ipv4); + spec->ip_version = 0; + } else if (spec->ip_version == ip_version_ipv6) { + mlx5_set(ste_eth_l2_src_dst_v1, tag, l3_type, ste_ipv6); + spec->ip_version = 0; + } else if (spec->ip_version) { + return -einval; + } + + dr_ste_set_tag(eth_l2_src_dst_v1, tag, first_vlan_id, spec, first_vid); + dr_ste_set_tag(eth_l2_src_dst_v1, tag, first_cfi, spec, first_cfi); + dr_ste_set_tag(eth_l2_src_dst_v1, tag, first_priority, spec, first_prio); + + if (spec->cvlan_tag) { + mlx5_set(ste_eth_l2_src_dst_v1, tag, first_vlan_qualifier, dr_ste_cvlan); + spec->cvlan_tag = 0; + } else if (spec->svlan_tag) { + mlx5_set(ste_eth_l2_src_dst_v1, tag, first_vlan_qualifier, dr_ste_svlan); + spec->svlan_tag = 0; + } + return 0; +} + +static void dr_ste_v1_build_eth_l2_src_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l2_src_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ethl2_src_dst, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_src_dst_tag; +} + +static int dr_ste_v1_build_eth_l3_ipv6_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_127_96, spec, dst_ip_127_96); + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_95_64, spec, dst_ip_95_64); + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_63_32, spec, dst_ip_63_32); + dr_ste_set_tag(eth_l3_ipv6_dst, tag, dst_ip_31_0, spec, dst_ip_31_0); + + return 0; +} + +static void dr_ste_v1_build_eth_l3_ipv6_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l3_ipv6_dst_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ipv6_des, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv6_dst_tag; +} + +static int dr_ste_v1_build_eth_l3_ipv6_src_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_127_96, spec, src_ip_127_96); + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_95_64, spec, src_ip_95_64); + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_63_32, spec, src_ip_63_32); + dr_ste_set_tag(eth_l3_ipv6_src, tag, src_ip_31_0, spec, src_ip_31_0); + + return 0; +} + +static void dr_ste_v1_build_eth_l3_ipv6_src_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l3_ipv6_src_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ipv6_src, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv6_src_tag; +} + +static int dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, destination_address, spec, dst_ip_31_0); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, source_address, spec, src_ip_31_0); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, destination_port, spec, tcp_dport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, destination_port, spec, udp_dport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, source_port, spec, tcp_sport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, source_port, spec, udp_sport); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, protocol, spec, ip_protocol); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, fragmented, spec, frag); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, dscp, spec, ip_dscp); + dr_ste_set_tag(eth_l3_ipv4_5_tuple_v1, tag, ecn, spec, ip_ecn); + + if (spec->tcp_flags) { + dr_ste_set_tcp_flags(eth_l3_ipv4_5_tuple_v1, tag, spec); + spec->tcp_flags = 0; + } + + return 0; +} + +static void dr_ste_v1_build_eth_l3_ipv4_5_tuple_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ethl3_ipv4_5_tuple, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_tag; +} + +static void dr_ste_v1_build_eth_l2_src_or_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc_mask = &value->misc; + + dr_ste_set_tag(eth_l2_src_v1, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, first_priority, mask, first_prio); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, ip_fragmented, mask, frag); // ? + dr_ste_set_tag(eth_l2_src_v1, bit_mask, l3_ethertype, mask, ethertype); // ? + dr_ste_set_ones(eth_l2_src_v1, bit_mask, l3_type, mask, ip_version); + + if (mask->svlan_tag || mask->cvlan_tag) { + mlx5_set(ste_eth_l2_src_v1, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + mask->svlan_tag = 0; + } + + if (inner) { + if (misc_mask->inner_second_cvlan_tag || + misc_mask->inner_second_svlan_tag) { + mlx5_set(ste_eth_l2_src_v1, bit_mask, second_vlan_qualifier, -1); + misc_mask->inner_second_cvlan_tag = 0; + misc_mask->inner_second_svlan_tag = 0; + } + + dr_ste_set_tag(eth_l2_src_v1, bit_mask, + second_vlan_id, misc_mask, inner_second_vid); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, + second_cfi, misc_mask, inner_second_cfi); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, + second_priority, misc_mask, inner_second_prio); + } else { + if (misc_mask->outer_second_cvlan_tag || + misc_mask->outer_second_svlan_tag) { + mlx5_set(ste_eth_l2_src_v1, bit_mask, second_vlan_qualifier, -1); + misc_mask->outer_second_cvlan_tag = 0; + misc_mask->outer_second_svlan_tag = 0; + } + + dr_ste_set_tag(eth_l2_src_v1, bit_mask, + second_vlan_id, misc_mask, outer_second_vid); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, + second_cfi, misc_mask, outer_second_cfi); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, + second_priority, misc_mask, outer_second_prio); + } +} + +static int dr_ste_v1_build_eth_l2_src_or_dst_tag(struct mlx5dr_match_param *value, + bool inner, u8 *tag) +{ + struct mlx5dr_match_spec *spec = inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc_spec = &value->misc; + + dr_ste_set_tag(eth_l2_src_v1, tag, first_vlan_id, spec, first_vid); + dr_ste_set_tag(eth_l2_src_v1, tag, first_cfi, spec, first_cfi); + dr_ste_set_tag(eth_l2_src_v1, tag, first_priority, spec, first_prio); + dr_ste_set_tag(eth_l2_src_v1, tag, ip_fragmented, spec, frag); + dr_ste_set_tag(eth_l2_src_v1, tag, l3_ethertype, spec, ethertype); + + if (spec->ip_version == ip_version_ipv4) { + mlx5_set(ste_eth_l2_src_v1, tag, l3_type, ste_ipv4); + spec->ip_version = 0; + } else if (spec->ip_version == ip_version_ipv6) { + mlx5_set(ste_eth_l2_src_v1, tag, l3_type, ste_ipv6); + spec->ip_version = 0; + } else if (spec->ip_version) { + return -einval; + } + + if (spec->cvlan_tag) { + mlx5_set(ste_eth_l2_src_v1, tag, first_vlan_qualifier, dr_ste_cvlan); + spec->cvlan_tag = 0; + } else if (spec->svlan_tag) { + mlx5_set(ste_eth_l2_src_v1, tag, first_vlan_qualifier, dr_ste_svlan); + spec->svlan_tag = 0; + } + + if (inner) { + if (misc_spec->inner_second_cvlan_tag) { + mlx5_set(ste_eth_l2_src_v1, tag, second_vlan_qualifier, dr_ste_cvlan); + misc_spec->inner_second_cvlan_tag = 0; + } else if (misc_spec->inner_second_svlan_tag) { + mlx5_set(ste_eth_l2_src_v1, tag, second_vlan_qualifier, dr_ste_svlan); + misc_spec->inner_second_svlan_tag = 0; + } + + dr_ste_set_tag(eth_l2_src_v1, tag, second_vlan_id, misc_spec, inner_second_vid); + dr_ste_set_tag(eth_l2_src_v1, tag, second_cfi, misc_spec, inner_second_cfi); + dr_ste_set_tag(eth_l2_src_v1, tag, second_priority, misc_spec, inner_second_prio); + } else { + if (misc_spec->outer_second_cvlan_tag) { + mlx5_set(ste_eth_l2_src_v1, tag, second_vlan_qualifier, dr_ste_cvlan); + misc_spec->outer_second_cvlan_tag = 0; + } else if (misc_spec->outer_second_svlan_tag) { + mlx5_set(ste_eth_l2_src_v1, tag, second_vlan_qualifier, dr_ste_svlan); + misc_spec->outer_second_svlan_tag = 0; + } + dr_ste_set_tag(eth_l2_src_v1, tag, second_vlan_id, misc_spec, outer_second_vid); + dr_ste_set_tag(eth_l2_src_v1, tag, second_cfi, misc_spec, outer_second_cfi); + dr_ste_set_tag(eth_l2_src_v1, tag, second_priority, misc_spec, outer_second_prio); + } + + return 0; +} + +static void dr_ste_v1_build_eth_l2_src_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_src_v1, bit_mask, smac_47_16, mask, smac_47_16); + dr_ste_set_tag(eth_l2_src_v1, bit_mask, smac_15_0, mask, smac_15_0); + + dr_ste_v1_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); +} + +static int dr_ste_v1_build_eth_l2_src_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_src_v1, tag, smac_47_16, spec, smac_47_16); + dr_ste_set_tag(eth_l2_src_v1, tag, smac_15_0, spec, smac_15_0); + + return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); +} + +static void dr_ste_v1_build_eth_l2_src_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l2_src_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ethl2_src, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_src_tag; +} + +static void dr_ste_v1_build_eth_l2_dst_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_dst_v1, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_tag(eth_l2_dst_v1, bit_mask, dmac_15_0, mask, dmac_15_0); + + dr_ste_v1_build_eth_l2_src_or_dst_bit_mask(value, inner, bit_mask); +} + +static int dr_ste_v1_build_eth_l2_dst_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l2_dst_v1, tag, dmac_47_16, spec, dmac_47_16); + dr_ste_set_tag(eth_l2_dst_v1, tag, dmac_15_0, spec, dmac_15_0); + + return dr_ste_v1_build_eth_l2_src_or_dst_tag(value, sb->inner, tag); +} + +static void dr_ste_v1_build_eth_l2_dst_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l2_dst_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ethl2, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_dst_tag; +} + +static void dr_ste_v1_build_eth_l2_tnl_bit_mask(struct mlx5dr_match_param *value, + bool inner, u8 *bit_mask) +{ + struct mlx5dr_match_spec *mask = inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, dmac_47_16, mask, dmac_47_16); + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, dmac_15_0, mask, dmac_15_0); + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, first_vlan_id, mask, first_vid); + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, first_cfi, mask, first_cfi); + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, first_priority, mask, first_prio); + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, ip_fragmented, mask, frag); + dr_ste_set_tag(eth_l2_tnl_v1, bit_mask, l3_ethertype, mask, ethertype); + dr_ste_set_ones(eth_l2_tnl_v1, bit_mask, l3_type, mask, ip_version); + + if (misc->vxlan_vni) { + mlx5_set(ste_eth_l2_tnl_v1, bit_mask, + l2_tunneling_network_id, (misc->vxlan_vni << 8)); + misc->vxlan_vni = 0; + } + + if (mask->svlan_tag || mask->cvlan_tag) { + mlx5_set(ste_eth_l2_tnl_v1, bit_mask, first_vlan_qualifier, -1); + mask->cvlan_tag = 0; + mask->svlan_tag = 0; + } +} + +static int dr_ste_v1_build_eth_l2_tnl_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(eth_l2_tnl_v1, tag, dmac_47_16, spec, dmac_47_16); + dr_ste_set_tag(eth_l2_tnl_v1, tag, dmac_15_0, spec, dmac_15_0); + dr_ste_set_tag(eth_l2_tnl_v1, tag, first_vlan_id, spec, first_vid); + dr_ste_set_tag(eth_l2_tnl_v1, tag, first_cfi, spec, first_cfi); + dr_ste_set_tag(eth_l2_tnl_v1, tag, ip_fragmented, spec, frag); + dr_ste_set_tag(eth_l2_tnl_v1, tag, first_priority, spec, first_prio); + dr_ste_set_tag(eth_l2_tnl_v1, tag, l3_ethertype, spec, ethertype); + + if (misc->vxlan_vni) { + mlx5_set(ste_eth_l2_tnl_v1, tag, l2_tunneling_network_id, + (misc->vxlan_vni << 8)); + misc->vxlan_vni = 0; + } + + if (spec->cvlan_tag) { + mlx5_set(ste_eth_l2_tnl_v1, tag, first_vlan_qualifier, dr_ste_cvlan); + spec->cvlan_tag = 0; + } else if (spec->svlan_tag) { + mlx5_set(ste_eth_l2_tnl_v1, tag, first_vlan_qualifier, dr_ste_svlan); + spec->svlan_tag = 0; + } + + if (spec->ip_version == ip_version_ipv4) { + mlx5_set(ste_eth_l2_tnl_v1, tag, l3_type, ste_ipv4); + spec->ip_version = 0; + } else if (spec->ip_version == ip_version_ipv6) { + mlx5_set(ste_eth_l2_tnl_v1, tag, l3_type, ste_ipv6); + spec->ip_version = 0; + } else if (spec->ip_version) { + return -einval; + } + + return 0; +} + +static void dr_ste_v1_build_eth_l2_tnl_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l2_tnl_bit_mask(mask, sb->inner, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_ethl2_tnl; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l2_tnl_tag; +} + +static int dr_ste_v1_build_eth_l3_ipv4_misc_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + + dr_ste_set_tag(eth_l3_ipv4_misc_v1, tag, time_to_live, spec, ttl_hoplimit); + + return 0; +} + +static void dr_ste_v1_build_eth_l3_ipv4_misc_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l3_ipv4_misc_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ethl3_ipv4_misc, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l3_ipv4_misc_tag; +} + +static int dr_ste_v1_build_eth_ipv6_l3_l4_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_spec *spec = sb->inner ? &value->inner : &value->outer; + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(eth_l4_v1, tag, dst_port, spec, tcp_dport); + dr_ste_set_tag(eth_l4_v1, tag, src_port, spec, tcp_sport); + dr_ste_set_tag(eth_l4_v1, tag, dst_port, spec, udp_dport); + dr_ste_set_tag(eth_l4_v1, tag, src_port, spec, udp_sport); + dr_ste_set_tag(eth_l4_v1, tag, protocol, spec, ip_protocol); + dr_ste_set_tag(eth_l4_v1, tag, fragmented, spec, frag); + dr_ste_set_tag(eth_l4_v1, tag, dscp, spec, ip_dscp); + dr_ste_set_tag(eth_l4_v1, tag, ecn, spec, ip_ecn); + dr_ste_set_tag(eth_l4_v1, tag, ipv6_hop_limit, spec, ttl_hoplimit); + + if (sb->inner) + dr_ste_set_tag(eth_l4_v1, tag, flow_label, misc, inner_ipv6_flow_label); + else + dr_ste_set_tag(eth_l4_v1, tag, flow_label, misc, outer_ipv6_flow_label); + + if (spec->tcp_flags) { + dr_ste_set_tcp_flags(eth_l4_v1, tag, spec); + spec->tcp_flags = 0; + } + + return 0; +} + +static void dr_ste_v1_build_eth_ipv6_l3_l4_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_ipv6_l3_l4_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(ethl4, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_ipv6_l3_l4_tag; +} + +static int dr_ste_v1_build_mpls_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + if (sb->inner) + dr_ste_set_mpls(mpls_v1, misc2, inner, tag); + else + dr_ste_set_mpls(mpls_v1, misc2, outer, tag); + + return 0; +} + +static void dr_ste_v1_build_mpls_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_mpls_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_calc_dfnr_type(mpls, sb->inner); + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_mpls_tag; +} + +static int dr_ste_v1_build_tnl_gre_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(gre_v1, tag, gre_protocol, misc, gre_protocol); + dr_ste_set_tag(gre_v1, tag, gre_k_present, misc, gre_k_present); + dr_ste_set_tag(gre_v1, tag, gre_key_h, misc, gre_key_h); + dr_ste_set_tag(gre_v1, tag, gre_key_l, misc, gre_key_l); + + dr_ste_set_tag(gre_v1, tag, gre_c_present, misc, gre_c_present); + dr_ste_set_tag(gre_v1, tag, gre_s_present, misc, gre_s_present); + + return 0; +} + +static void dr_ste_v1_build_tnl_gre_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_tnl_gre_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_gre; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_tnl_gre_tag; +} + +static int dr_ste_v1_build_tnl_mpls_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + if (dr_ste_is_outer_mpls_over_gre_set(misc2)) { + dr_ste_set_tag(mpls_v1, tag, mpls0_label, + misc2, outer_first_mpls_over_gre_label); + + dr_ste_set_tag(mpls_v1, tag, mpls0_exp, + misc2, outer_first_mpls_over_gre_exp); + + dr_ste_set_tag(mpls_v1, tag, mpls0_s_bos, + misc2, outer_first_mpls_over_gre_s_bos); + + dr_ste_set_tag(mpls_v1, tag, mpls0_ttl, + misc2, outer_first_mpls_over_gre_ttl); + } else { + dr_ste_set_tag(mpls_v1, tag, mpls0_label, + misc2, outer_first_mpls_over_udp_label); + + dr_ste_set_tag(mpls_v1, tag, mpls0_exp, + misc2, outer_first_mpls_over_udp_exp); + + dr_ste_set_tag(mpls_v1, tag, mpls0_s_bos, + misc2, outer_first_mpls_over_udp_s_bos); + + dr_ste_set_tag(mpls_v1, tag, mpls0_ttl, + misc2, outer_first_mpls_over_udp_ttl); + } + + return 0; +} + +static void dr_ste_v1_build_tnl_mpls_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_tnl_mpls_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_mpls_i; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_tnl_mpls_tag; +} + +static int dr_ste_v1_build_icmp_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc3 *misc3 = &value->misc3; + bool is_ipv4 = dr_mask_is_icmpv4_set(misc3); + u32 *icmp_header_data; + u8 *icmp_type; + u8 *icmp_code; + + if (is_ipv4) { + icmp_header_data = &misc3->icmpv4_header_data; + icmp_type = &misc3->icmpv4_type; + icmp_code = &misc3->icmpv4_code; + } else { + icmp_header_data = &misc3->icmpv6_header_data; + icmp_type = &misc3->icmpv6_type; + icmp_code = &misc3->icmpv6_code; + } + + mlx5_set(ste_icmp_v1, tag, icmp_header_data, *icmp_header_data); + mlx5_set(ste_icmp_v1, tag, icmp_type, *icmp_type); + mlx5_set(ste_icmp_v1, tag, icmp_code, *icmp_code); + + *icmp_header_data = 0; + *icmp_type = 0; + *icmp_code = 0; + + return 0; +} + +static int dr_ste_v1_build_icmp_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_icmp_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_ethl4_misc_o; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_icmp_tag; + + return 0; +} + +static int dr_ste_v1_build_general_purpose_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + dr_ste_set_tag(general_purpose, tag, general_purpose_lookup_field, + misc2, metadata_reg_a); + + return 0; +} + +static void dr_ste_v1_build_general_purpose_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_general_purpose_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_general_purpose; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_general_purpose_tag; +} + +static int dr_ste_v1_build_eth_l4_misc_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc3 *misc3 = &value->misc3; + + if (sb->inner) { + dr_ste_set_tag(eth_l4_misc_v1, tag, seq_num, misc3, inner_tcp_seq_num); + dr_ste_set_tag(eth_l4_misc_v1, tag, ack_num, misc3, inner_tcp_ack_num); + } else { + dr_ste_set_tag(eth_l4_misc_v1, tag, seq_num, misc3, outer_tcp_seq_num); + dr_ste_set_tag(eth_l4_misc_v1, tag, ack_num, misc3, outer_tcp_ack_num); + } + + return 0; +} + +static void dr_ste_v1_build_eth_l4_misc_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_eth_l4_misc_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_ethl4_misc_o; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_eth_l4_misc_tag; +} + +static int +dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc3 *misc3 = &value->misc3; + + dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, + outer_vxlan_gpe_flags, misc3, + outer_vxlan_gpe_flags); + dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, + outer_vxlan_gpe_next_protocol, misc3, + outer_vxlan_gpe_next_protocol); + dr_ste_set_tag(flex_parser_tnl_vxlan_gpe, tag, + outer_vxlan_gpe_vni, misc3, + outer_vxlan_gpe_vni); + + return 0; +} + +static void +dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_flex_parser_tnl_header; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_tag; +} + +static int +dr_ste_v1_build_flex_parser_tnl_geneve_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc *misc = &value->misc; + + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_protocol_type, misc, geneve_protocol_type); + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_oam, misc, geneve_oam); + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_opt_len, misc, geneve_opt_len); + dr_ste_set_tag(flex_parser_tnl_geneve, tag, + geneve_vni, misc, geneve_vni); + + return 0; +} + +static void +dr_ste_v1_build_flex_parser_tnl_geneve_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_flex_parser_tnl_geneve_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_flex_parser_tnl_header; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_flex_parser_tnl_geneve_tag; +} + +static int dr_ste_v1_build_register_0_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + dr_ste_set_tag(register_0, tag, register_0_h, misc2, metadata_reg_c_0); + dr_ste_set_tag(register_0, tag, register_0_l, misc2, metadata_reg_c_1); + dr_ste_set_tag(register_0, tag, register_1_h, misc2, metadata_reg_c_2); + dr_ste_set_tag(register_0, tag, register_1_l, misc2, metadata_reg_c_3); + + return 0; +} + +static void dr_ste_v1_build_register_0_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_register_0_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_steering_registers_0; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_register_0_tag; +} + +static int dr_ste_v1_build_register_1_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc2 *misc2 = &value->misc2; + + dr_ste_set_tag(register_1, tag, register_2_h, misc2, metadata_reg_c_4); + dr_ste_set_tag(register_1, tag, register_2_l, misc2, metadata_reg_c_5); + dr_ste_set_tag(register_1, tag, register_3_h, misc2, metadata_reg_c_6); + dr_ste_set_tag(register_1, tag, register_3_l, misc2, metadata_reg_c_7); + + return 0; +} + +static void dr_ste_v1_build_register_1_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_register_1_tag(mask, sb, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_steering_registers_1; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_register_1_tag; +} + +static void dr_ste_v1_build_src_gvmi_qpn_bit_mask(struct mlx5dr_match_param *value, + u8 *bit_mask) +{ + struct mlx5dr_match_misc *misc_mask = &value->misc; + + dr_ste_set_ones(src_gvmi_qp_v1, bit_mask, source_gvmi, misc_mask, source_port); + dr_ste_set_ones(src_gvmi_qp_v1, bit_mask, source_qp, misc_mask, source_sqn); +} + +static int dr_ste_v1_build_src_gvmi_qpn_tag(struct mlx5dr_match_param *value, + struct mlx5dr_ste_build *sb, + u8 *tag) +{ + struct mlx5dr_match_misc *misc = &value->misc; + struct mlx5dr_cmd_vport_cap *vport_cap; + struct mlx5dr_domain *dmn = sb->dmn; + struct mlx5dr_cmd_caps *caps; + u8 *bit_mask = sb->bit_mask; + + dr_ste_set_tag(src_gvmi_qp_v1, tag, source_qp, misc, source_sqn); + + if (sb->vhca_id_valid) { + /* find port gvmi based on the eswitch_owner_vhca_id */ + if (misc->source_eswitch_owner_vhca_id == dmn->info.caps.gvmi) + caps = &dmn->info.caps; + else if (dmn->peer_dmn && (misc->source_eswitch_owner_vhca_id == + dmn->peer_dmn->info.caps.gvmi)) + caps = &dmn->peer_dmn->info.caps; + else + return -einval; + + misc->source_eswitch_owner_vhca_id = 0; + } else { + caps = &dmn->info.caps; + } + + if (!mlx5_get(ste_src_gvmi_qp_v1, bit_mask, source_gvmi)) + return 0; + + vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port); + if (!vport_cap) { + mlx5dr_err(dmn, "vport 0x%x is disabled or invalid ", + misc->source_port); + return -einval; + } + + if (vport_cap->vport_gvmi) + mlx5_set(ste_src_gvmi_qp_v1, tag, source_gvmi, vport_cap->vport_gvmi); + + misc->source_port = 0; + return 0; +} + +static void dr_ste_v1_build_src_gvmi_qpn_init(struct mlx5dr_ste_build *sb, + struct mlx5dr_match_param *mask) +{ + dr_ste_v1_build_src_gvmi_qpn_bit_mask(mask, sb->bit_mask); + + sb->lu_type = dr_ste_v1_lu_type_src_qp_gvmi; + sb->byte_mask = mlx5dr_ste_conv_bit_to_byte_mask(sb->bit_mask); + sb->ste_build_tag_func = &dr_ste_v1_build_src_gvmi_qpn_tag; +} + +struct mlx5dr_ste_ctx ste_ctx_v1 = { + .build_eth_l2_src_dst_init = &dr_ste_v1_build_eth_l2_src_dst_init, + .build_eth_l3_ipv6_src_init = &dr_ste_v1_build_eth_l3_ipv6_src_init, + .build_eth_l3_ipv6_dst_init = &dr_ste_v1_build_eth_l3_ipv6_dst_init, + .build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init, + .build_eth_l2_src_init = &dr_ste_v1_build_eth_l2_src_init, + .build_eth_l2_dst_init = &dr_ste_v1_build_eth_l2_dst_init, + .build_eth_l2_tnl_init = &dr_ste_v1_build_eth_l2_tnl_init, + .build_eth_l3_ipv4_misc_init = &dr_ste_v1_build_eth_l3_ipv4_misc_init, + .build_eth_ipv6_l3_l4_init = &dr_ste_v1_build_eth_ipv6_l3_l4_init, + .build_mpls_init = &dr_ste_v1_build_mpls_init, + .build_tnl_gre_init = &dr_ste_v1_build_tnl_gre_init, + .build_tnl_mpls_init = &dr_ste_v1_build_tnl_mpls_init, + .build_icmp_init = &dr_ste_v1_build_icmp_init, + .build_general_purpose_init = &dr_ste_v1_build_general_purpose_init, + .build_eth_l4_misc_init = &dr_ste_v1_build_eth_l4_misc_init, + .build_tnl_vxlan_gpe_init = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init, + .build_tnl_geneve_init = &dr_ste_v1_build_flex_parser_tnl_geneve_init, + .build_register_0_init = &dr_ste_v1_build_register_0_init, + .build_register_1_init = &dr_ste_v1_build_register_1_init, + .build_src_gvmi_qpn_init = &dr_ste_v1_build_src_gvmi_qpn_init, +};
|
Networking
|
10b69418641062b4dc7fabe3c6f2e12432ec6987
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, allow native protocol support for hw stev1
|
some flex parser protocols are native as part of stev1. the check for supported protocols was modified to allow this.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 8
| 4
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_matcher.c - return caps->flex_protocols & mlx5_flex_parser_vxlan_gpe_enabled; + return (caps->sw_format_ver == mlx5_steering_format_connectx_6dx) || + (caps->flex_protocols & mlx5_flex_parser_vxlan_gpe_enabled); - return caps->flex_protocols & mlx5_flex_parser_geneve_enabled; + return (caps->sw_format_ver == mlx5_steering_format_connectx_6dx) || + (caps->flex_protocols & mlx5_flex_parser_geneve_enabled); - return caps->flex_protocols & mlx5_flex_parser_icmp_v4_enabled; + return (caps->sw_format_ver == mlx5_steering_format_connectx_6dx) || + (caps->flex_protocols & mlx5_flex_parser_icmp_v4_enabled); - return caps->flex_protocols & mlx5_flex_parser_icmp_v6_enabled; + return (caps->sw_format_ver == mlx5_steering_format_connectx_6dx) || + (caps->flex_protocols & mlx5_flex_parser_icmp_v6_enabled);
|
Networking
|
9f125ced1750ecf299dc52771410d823a36fbbfd
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add stev1 setters and getters
|
add hw specific setter and getters to stev1 file. since stev0 and stev1 format are different, each version should implemented different setters and getters.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 133
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +static void dr_ste_v1_set_miss_addr(u8 *hw_ste_p, u64 miss_addr) +{ + u64 index = miss_addr >> 6; + + mlx5_set(ste_match_bwc_v1, hw_ste_p, miss_address_39_32, index >> 26); + mlx5_set(ste_match_bwc_v1, hw_ste_p, miss_address_31_6, index); +} + +static u64 dr_ste_v1_get_miss_addr(u8 *hw_ste_p) +{ + u64 index = + (mlx5_get(ste_match_bwc_v1, hw_ste_p, miss_address_31_6) | + mlx5_get(ste_match_bwc_v1, hw_ste_p, miss_address_39_32) << 26); + + return index << 6; +} + +static void dr_ste_v1_set_byte_mask(u8 *hw_ste_p, u16 byte_mask) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, byte_mask, byte_mask); +} + +static u16 dr_ste_v1_get_byte_mask(u8 *hw_ste_p) +{ + return mlx5_get(ste_match_bwc_v1, hw_ste_p, byte_mask); +} + +static void dr_ste_v1_set_lu_type(u8 *hw_ste_p, u16 lu_type) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, entry_format, lu_type >> 8); + mlx5_set(ste_match_bwc_v1, hw_ste_p, match_definer_ctx_idx, lu_type & 0xff); +} + +static void dr_ste_v1_set_next_lu_type(u8 *hw_ste_p, u16 lu_type) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, next_entry_format, lu_type >> 8); + mlx5_set(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx, lu_type & 0xff); +} + +static u16 dr_ste_v1_get_next_lu_type(u8 *hw_ste_p) +{ + u8 mode = mlx5_get(ste_match_bwc_v1, hw_ste_p, next_entry_format); + u8 index = mlx5_get(ste_match_bwc_v1, hw_ste_p, hash_definer_ctx_idx); + + return (mode << 8 | index); +} + +static void dr_ste_v1_set_hit_addr(u8 *hw_ste_p, u64 icm_addr, u32 ht_size) +{ + u64 index = (icm_addr >> 5) | ht_size; + + mlx5_set(ste_match_bwc_v1, hw_ste_p, next_table_base_39_32_size, index >> 27); + mlx5_set(ste_match_bwc_v1, hw_ste_p, next_table_base_31_5_size, index); +} + +static void dr_ste_v1_init(u8 *hw_ste_p, u16 lu_type, + u8 entry_type, u16 gvmi) +{ + dr_ste_v1_set_lu_type(hw_ste_p, lu_type); + dr_ste_v1_set_next_lu_type(hw_ste_p, mlx5dr_ste_lu_type_dont_care); + + mlx5_set(ste_match_bwc_v1, hw_ste_p, gvmi, gvmi); + mlx5_set(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi); + mlx5_set(ste_match_bwc_v1, hw_ste_p, miss_address_63_48, gvmi); +} + + /* builders */ + /* getters and setters */ + .ste_init = &dr_ste_v1_init, + .set_next_lu_type = &dr_ste_v1_set_next_lu_type, + .get_next_lu_type = &dr_ste_v1_get_next_lu_type, + .set_miss_addr = &dr_ste_v1_set_miss_addr, + .get_miss_addr = &dr_ste_v1_get_miss_addr, + .set_hit_addr = &dr_ste_v1_set_hit_addr, + .set_byte_mask = &dr_ste_v1_set_byte_mask, + .get_byte_mask = &dr_ste_v1_get_byte_mask, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +struct mlx5_ifc_ste_match_bwc_v1_bits { + u8 entry_format[0x8]; + u8 counter_id[0x18]; + + u8 miss_address_63_48[0x10]; + u8 match_definer_ctx_idx[0x8]; + u8 miss_address_39_32[0x8]; + + u8 miss_address_31_6[0x1a]; + u8 reserved_at_5a[0x1]; + u8 match_polarity[0x1]; + u8 reparse[0x1]; + u8 reserved_at_5d[0x3]; + + u8 next_table_base_63_48[0x10]; + u8 hash_definer_ctx_idx[0x8]; + u8 next_table_base_39_32_size[0x8]; + + u8 next_table_base_31_5_size[0x1b]; + u8 hash_type[0x2]; + u8 hash_after_actions[0x1]; + u8 reserved_at_9e[0x2]; + + u8 byte_mask[0x10]; + u8 next_entry_format[0x1]; + u8 mask_mode[0x1]; + u8 gvmi[0xe]; + + u8 action[0x40]; +}; + +struct mlx5_ifc_ste_mask_and_match_v1_bits { + u8 entry_format[0x8]; + u8 counter_id[0x18]; + + u8 miss_address_63_48[0x10]; + u8 match_definer_ctx_idx[0x8]; + u8 miss_address_39_32[0x8]; + + u8 miss_address_31_6[0x1a]; + u8 reserved_at_5a[0x1]; + u8 match_polarity[0x1]; + u8 reparse[0x1]; + u8 reserved_at_5d[0x3]; + + u8 next_table_base_63_48[0x10]; + u8 hash_definer_ctx_idx[0x8]; + u8 next_table_base_39_32_size[0x8]; + + u8 next_table_base_31_5_size[0x1b]; + u8 hash_type[0x2]; + u8 hash_after_actions[0x1]; + u8 reserved_at_9e[0x2]; + + u8 action[0x60]; +}; +
|
Networking
|
a6098129c781a7b0fe0d518281bce99b60fe7203
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add stev1 action apply logic
|
add hw specific action apply logic to stev1. since stev0 and stev1 actions format is different, each version has its implementation.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 458
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +enum dr_ste_v1_header_anchors { + dr_ste_header_anchor_start_outer = 0x00, + dr_ste_header_anchor_1st_vlan = 0x02, + dr_ste_header_anchor_ipv6_ipv4 = 0x07, + dr_ste_header_anchor_inner_mac = 0x13, + dr_ste_header_anchor_inner_ipv6_ipv4 = 0x19, +}; + +enum dr_ste_v1_action_size { + dr_ste_action_single_sz = 4, + dr_ste_action_double_sz = 8, + dr_ste_action_triple_sz = 12, +}; + +enum dr_ste_v1_action_insert_ptr_attr { + dr_ste_v1_action_insert_ptr_attr_none = 0, /* regular push header (e.g. push vlan) */ + dr_ste_v1_action_insert_ptr_attr_encap = 1, /* encapsulation / tunneling */ + dr_ste_v1_action_insert_ptr_attr_esp = 2, /* ipsec */ +}; + +enum dr_ste_v1_action_id { + dr_ste_v1_action_id_nop = 0x00, + dr_ste_v1_action_id_copy = 0x05, + dr_ste_v1_action_id_set = 0x06, + dr_ste_v1_action_id_add = 0x07, + dr_ste_v1_action_id_remove_by_size = 0x08, + dr_ste_v1_action_id_remove_header_to_header = 0x09, + dr_ste_v1_action_id_insert_inline = 0x0a, + dr_ste_v1_action_id_insert_pointer = 0x0b, + dr_ste_v1_action_id_flow_tag = 0x0c, + dr_ste_v1_action_id_queue_id_sel = 0x0d, + dr_ste_v1_action_id_accelerated_list = 0x0e, + dr_ste_v1_action_id_modify_list = 0x0f, + dr_ste_v1_action_id_trailer = 0x13, + dr_ste_v1_action_id_counter_id = 0x14, + dr_ste_v1_action_id_max = 0x21, + /* use for special cases */ + dr_ste_v1_action_id_special_encap_l3 = 0x22, +}; + +static void dr_ste_v1_set_entry_type(u8 *hw_ste_p, u8 entry_type) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, entry_format, entry_type); +} + +static void dr_ste_v1_set_hit_gvmi(u8 *hw_ste_p, u16 gvmi) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, next_table_base_63_48, gvmi); +} + +static void dr_ste_v1_set_rx_flow_tag(u8 *s_action, u32 flow_tag) +{ + mlx5_set(ste_single_action_flow_tag_v1, s_action, action_id, + dr_ste_v1_action_id_flow_tag); + mlx5_set(ste_single_action_flow_tag_v1, s_action, flow_tag, flow_tag); +} + +static void dr_ste_v1_set_counter_id(u8 *hw_ste_p, u32 ctr_id) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, counter_id, ctr_id); +} + +static void dr_ste_v1_set_reparse(u8 *hw_ste_p) +{ + mlx5_set(ste_match_bwc_v1, hw_ste_p, reparse, 1); +} + +static void dr_ste_v1_set_tx_encap(u8 *hw_ste_p, u8 *d_action, + u32 reformat_id, int size) +{ + mlx5_set(ste_double_action_insert_with_ptr_v1, d_action, action_id, + dr_ste_v1_action_id_insert_pointer); + /* the hardware expects here size in words (2 byte) */ + mlx5_set(ste_double_action_insert_with_ptr_v1, d_action, size, size / 2); + mlx5_set(ste_double_action_insert_with_ptr_v1, d_action, pointer, reformat_id); + mlx5_set(ste_double_action_insert_with_ptr_v1, d_action, attributes, + dr_ste_v1_action_insert_ptr_attr_encap); + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_set_tx_push_vlan(u8 *hw_ste_p, u8 *d_action, + u32 vlan_hdr) +{ + mlx5_set(ste_double_action_insert_with_inline_v1, d_action, + action_id, dr_ste_v1_action_id_insert_inline); + /* the hardware expects offset to vlan header in words (2 byte) */ + mlx5_set(ste_double_action_insert_with_inline_v1, d_action, + start_offset, hdr_len_l2_macs >> 1); + mlx5_set(ste_double_action_insert_with_inline_v1, d_action, + inline_data, vlan_hdr); + + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_set_rx_pop_vlan(u8 *hw_ste_p, u8 *s_action, u8 vlans_num) +{ + mlx5_set(ste_single_action_remove_header_size_v1, s_action, + action_id, dr_ste_v1_action_id_remove_by_size); + mlx5_set(ste_single_action_remove_header_size_v1, s_action, + start_anchor, dr_ste_header_anchor_1st_vlan); + /* the hardware expects here size in words (2 byte) */ + mlx5_set(ste_single_action_remove_header_size_v1, s_action, + remove_size, (hdr_len_l2_vlan >> 1) * vlans_num); + + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_set_tx_encap_l3(u8 *hw_ste_p, + u8 *frst_s_action, + u8 *scnd_d_action, + u32 reformat_id, + int size) +{ + /* remove l2 headers */ + mlx5_set(ste_single_action_remove_header_v1, frst_s_action, action_id, + dr_ste_v1_action_id_remove_header_to_header); + mlx5_set(ste_single_action_remove_header_v1, frst_s_action, end_anchor, + dr_ste_header_anchor_ipv6_ipv4); + + /* encapsulate with given reformat id */ + mlx5_set(ste_double_action_insert_with_ptr_v1, scnd_d_action, action_id, + dr_ste_v1_action_id_insert_pointer); + /* the hardware expects here size in words (2 byte) */ + mlx5_set(ste_double_action_insert_with_ptr_v1, scnd_d_action, size, size / 2); + mlx5_set(ste_double_action_insert_with_ptr_v1, scnd_d_action, pointer, reformat_id); + mlx5_set(ste_double_action_insert_with_ptr_v1, scnd_d_action, attributes, + dr_ste_v1_action_insert_ptr_attr_encap); + + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_set_rx_decap(u8 *hw_ste_p, u8 *s_action) +{ + mlx5_set(ste_single_action_remove_header_v1, s_action, action_id, + dr_ste_v1_action_id_remove_header_to_header); + mlx5_set(ste_single_action_remove_header_v1, s_action, decap, 1); + mlx5_set(ste_single_action_remove_header_v1, s_action, vni_to_cqe, 1); + mlx5_set(ste_single_action_remove_header_v1, s_action, end_anchor, + dr_ste_header_anchor_inner_mac); + + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_set_rx_decap_l3(u8 *hw_ste_p, + u8 *s_action, + u16 decap_actions, + u32 decap_index) +{ + mlx5_set(ste_single_action_modify_list_v1, s_action, action_id, + dr_ste_v1_action_id_modify_list); + mlx5_set(ste_single_action_modify_list_v1, s_action, num_of_modify_actions, + decap_actions); + mlx5_set(ste_single_action_modify_list_v1, s_action, modify_actions_ptr, + decap_index); + + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_set_rewrite_actions(u8 *hw_ste_p, + u8 *s_action, + u16 num_of_actions, + u32 re_write_index) +{ + mlx5_set(ste_single_action_modify_list_v1, s_action, action_id, + dr_ste_v1_action_id_modify_list); + mlx5_set(ste_single_action_modify_list_v1, s_action, num_of_modify_actions, + num_of_actions); + mlx5_set(ste_single_action_modify_list_v1, s_action, modify_actions_ptr, + re_write_index); + + dr_ste_v1_set_reparse(hw_ste_p); +} + +static void dr_ste_v1_arr_init_next_match(u8 **last_ste, + u32 *added_stes, + u16 gvmi) +{ + u8 *action; + + (*added_stes)++; + *last_ste += dr_ste_size; + dr_ste_v1_init(*last_ste, mlx5dr_ste_lu_type_dont_care, 0, gvmi); + dr_ste_v1_set_entry_type(*last_ste, dr_ste_v1_type_match); + + action = mlx5_addr_of(ste_mask_and_match_v1, *last_ste, action); + memset(action, 0, mlx5_fld_sz_bytes(ste_mask_and_match_v1, action)); +} + +static void dr_ste_v1_set_actions_tx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes) +{ + u8 *action = mlx5_addr_of(ste_match_bwc_v1, last_ste, action); + u8 action_sz = dr_ste_action_double_sz; + bool allow_encap = true; + + if (action_type_set[dr_action_typ_ctr]) + dr_ste_v1_set_counter_id(last_ste, attr->ctr_id); + + if (action_type_set[dr_action_typ_modify_hdr]) { + if (action_sz < dr_ste_action_double_sz) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, + attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, + last_ste, action); + action_sz = dr_ste_action_triple_sz; + } + dr_ste_v1_set_rewrite_actions(last_ste, action, + attr->modify_actions, + attr->modify_index); + action_sz -= dr_ste_action_double_sz; + action += dr_ste_action_double_sz; + allow_encap = false; + } + + if (action_type_set[dr_action_typ_push_vlan]) { + int i; + + for (i = 0; i < attr->vlans.count; i++) { + if (action_sz < dr_ste_action_double_sz || !allow_encap) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + allow_encap = true; + } + dr_ste_v1_set_tx_push_vlan(last_ste, action, attr->vlans.headers[i]); + action_sz -= dr_ste_action_double_sz; + action += dr_ste_action_double_sz; + } + } + + if (action_type_set[dr_action_typ_l2_to_tnl_l2]) { + if (!allow_encap || action_sz < dr_ste_action_double_sz) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + allow_encap = true; + } + dr_ste_v1_set_tx_encap(last_ste, action, + attr->reformat_id, + attr->reformat_size); + action_sz -= dr_ste_action_double_sz; + action += dr_ste_action_double_sz; + } else if (action_type_set[dr_action_typ_l2_to_tnl_l3]) { + u8 *d_action; + + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + d_action = action + dr_ste_action_single_sz; + + dr_ste_v1_set_tx_encap_l3(last_ste, + action, d_action, + attr->reformat_id, + attr->reformat_size); + action_sz -= dr_ste_action_triple_sz; + action += dr_ste_action_triple_sz; + } + + dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi); + dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1); +} + +static void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn, + u8 *action_type_set, + u8 *last_ste, + struct mlx5dr_ste_actions_attr *attr, + u32 *added_stes) +{ + u8 *action = mlx5_addr_of(ste_match_bwc_v1, last_ste, action); + u8 action_sz = dr_ste_action_double_sz; + bool allow_modify_hdr = true; + bool allow_ctr = true; + + if (action_type_set[dr_action_typ_tnl_l3_to_l2]) { + dr_ste_v1_set_rx_decap_l3(last_ste, action, + attr->decap_actions, + attr->decap_index); + dr_ste_v1_set_rewrite_actions(last_ste, action, + attr->decap_actions, + attr->decap_index); + action_sz -= dr_ste_action_double_sz; + action += dr_ste_action_double_sz; + allow_modify_hdr = false; + allow_ctr = false; + } else if (action_type_set[dr_action_typ_tnl_l2_to_l2]) { + dr_ste_v1_set_rx_decap(last_ste, action); + action_sz -= dr_ste_action_single_sz; + action += dr_ste_action_single_sz; + allow_modify_hdr = false; + allow_ctr = false; + } + + if (action_type_set[dr_action_typ_tag]) { + if (action_sz < dr_ste_action_single_sz) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + allow_modify_hdr = true; + allow_ctr = true; + } + dr_ste_v1_set_rx_flow_tag(action, attr->flow_tag); + action_sz -= dr_ste_action_single_sz; + action += dr_ste_action_single_sz; + } + + if (action_type_set[dr_action_typ_pop_vlan]) { + if (action_sz < dr_ste_action_single_sz || + !allow_modify_hdr) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + allow_modify_hdr = false; + allow_ctr = false; + } + + dr_ste_v1_set_rx_pop_vlan(last_ste, action, attr->vlans.count); + action_sz -= dr_ste_action_single_sz; + action += dr_ste_action_single_sz; + } + + if (action_type_set[dr_action_typ_modify_hdr]) { + /* modify header and decapsulation must use different stes */ + if (!allow_modify_hdr || action_sz < dr_ste_action_double_sz) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + allow_modify_hdr = true; + allow_ctr = true; + } + dr_ste_v1_set_rewrite_actions(last_ste, action, + attr->modify_actions, + attr->modify_index); + action_sz -= dr_ste_action_double_sz; + action += dr_ste_action_double_sz; + } + + if (action_type_set[dr_action_typ_ctr]) { + /* counter action set after decap to exclude decaped header */ + if (!allow_ctr) { + dr_ste_v1_arr_init_next_match(&last_ste, added_stes, attr->gvmi); + action = mlx5_addr_of(ste_mask_and_match_v1, last_ste, action); + action_sz = dr_ste_action_triple_sz; + allow_modify_hdr = true; + allow_ctr = false; + } + dr_ste_v1_set_counter_id(last_ste, attr->ctr_id); + } + + dr_ste_v1_set_hit_gvmi(last_ste, attr->hit_gvmi); + dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1); +} + + /* actions */ + .set_actions_rx = &dr_ste_v1_set_actions_rx, + .set_actions_tx = &dr_ste_v1_set_actions_tx, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +struct mlx5_ifc_ste_single_action_flow_tag_v1_bits { + u8 action_id[0x8]; + u8 flow_tag[0x18]; +}; + +struct mlx5_ifc_ste_single_action_modify_list_v1_bits { + u8 action_id[0x8]; + u8 num_of_modify_actions[0x8]; + u8 modify_actions_ptr[0x10]; +}; + +struct mlx5_ifc_ste_single_action_remove_header_v1_bits { + u8 action_id[0x8]; + u8 reserved_at_8[0x2]; + u8 start_anchor[0x6]; + u8 reserved_at_10[0x2]; + u8 end_anchor[0x6]; + u8 reserved_at_18[0x4]; + u8 decap[0x1]; + u8 vni_to_cqe[0x1]; + u8 qos_profile[0x2]; +}; + +struct mlx5_ifc_ste_single_action_remove_header_size_v1_bits { + u8 action_id[0x8]; + u8 reserved_at_8[0x2]; + u8 start_anchor[0x6]; + u8 outer_l4_remove[0x1]; + u8 reserved_at_11[0x1]; + u8 start_offset[0x7]; + u8 reserved_at_18[0x1]; + u8 remove_size[0x6]; +}; + +struct mlx5_ifc_ste_double_action_copy_v1_bits { + u8 action_id[0x8]; + u8 destination_dw_offset[0x8]; + u8 reserved_at_10[0x2]; + u8 destination_left_shifter[0x6]; + u8 reserved_at_17[0x2]; + u8 destination_length[0x6]; + + u8 reserved_at_20[0x8]; + u8 source_dw_offset[0x8]; + u8 reserved_at_30[0x2]; + u8 source_right_shifter[0x6]; + u8 reserved_at_38[0x8]; +}; + +struct mlx5_ifc_ste_double_action_set_v1_bits { + u8 action_id[0x8]; + u8 destination_dw_offset[0x8]; + u8 reserved_at_10[0x2]; + u8 destination_left_shifter[0x6]; + u8 reserved_at_18[0x2]; + u8 destination_length[0x6]; + + u8 inline_data[0x20]; +}; + +struct mlx5_ifc_ste_double_action_add_v1_bits { + u8 action_id[0x8]; + u8 destination_dw_offset[0x8]; + u8 reserved_at_10[0x2]; + u8 destination_left_shifter[0x6]; + u8 reserved_at_18[0x2]; + u8 destination_length[0x6]; + + u8 add_value[0x20]; +}; + +struct mlx5_ifc_ste_double_action_insert_with_inline_v1_bits { + u8 action_id[0x8]; + u8 reserved_at_8[0x2]; + u8 start_anchor[0x6]; + u8 start_offset[0x7]; + u8 reserved_at_17[0x9]; + + u8 inline_data[0x20]; +}; + +struct mlx5_ifc_ste_double_action_insert_with_ptr_v1_bits { + u8 action_id[0x8]; + u8 reserved_at_8[0x2]; + u8 start_anchor[0x6]; + u8 start_offset[0x7]; + u8 size[0x6]; + u8 attributes[0x3]; + + u8 pointer[0x20]; +}; + +struct mlx5_ifc_ste_double_action_modify_action_list_v1_bits { + u8 action_id[0x8]; + u8 modify_actions_pattern_pointer[0x18]; + + u8 number_of_modify_actions[0x8]; + u8 modify_actions_argument_pointer[0x18]; +}; +
|
Networking
|
4e856c5db9b4d6601337dd5e3ea72a6931e2469b
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, add stev1 modify header logic
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add hw specific modify header fields and logic to stev1 file. since stev0 and stev1 modify actions values are different, each version has its own implementation.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 273
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +enum { + dr_ste_v1_action_mdfy_fld_l2_out_0 = 0x00, + dr_ste_v1_action_mdfy_fld_l2_out_1 = 0x01, + dr_ste_v1_action_mdfy_fld_l2_out_2 = 0x02, + dr_ste_v1_action_mdfy_fld_src_l2_out_0 = 0x08, + dr_ste_v1_action_mdfy_fld_src_l2_out_1 = 0x09, + dr_ste_v1_action_mdfy_fld_l3_out_0 = 0x0e, + dr_ste_v1_action_mdfy_fld_l4_out_0 = 0x18, + dr_ste_v1_action_mdfy_fld_l4_out_1 = 0x19, + dr_ste_v1_action_mdfy_fld_ipv4_out_0 = 0x40, + dr_ste_v1_action_mdfy_fld_ipv4_out_1 = 0x41, + dr_ste_v1_action_mdfy_fld_ipv6_dst_out_0 = 0x44, + dr_ste_v1_action_mdfy_fld_ipv6_dst_out_1 = 0x45, + dr_ste_v1_action_mdfy_fld_ipv6_dst_out_2 = 0x46, + dr_ste_v1_action_mdfy_fld_ipv6_dst_out_3 = 0x47, + dr_ste_v1_action_mdfy_fld_ipv6_src_out_0 = 0x4c, + dr_ste_v1_action_mdfy_fld_ipv6_src_out_1 = 0x4d, + dr_ste_v1_action_mdfy_fld_ipv6_src_out_2 = 0x4e, + dr_ste_v1_action_mdfy_fld_ipv6_src_out_3 = 0x4f, + dr_ste_v1_action_mdfy_fld_tcp_misc_0 = 0x5e, + dr_ste_v1_action_mdfy_fld_tcp_misc_1 = 0x5f, + dr_ste_v1_action_mdfy_fld_metadata_2_cqe = 0x7b, + dr_ste_v1_action_mdfy_fld_gnrl_purpose = 0x7c, + dr_ste_v1_action_mdfy_fld_register_2 = 0x8c, + dr_ste_v1_action_mdfy_fld_register_3 = 0x8d, + dr_ste_v1_action_mdfy_fld_register_4 = 0x8e, + dr_ste_v1_action_mdfy_fld_register_5 = 0x8f, + dr_ste_v1_action_mdfy_fld_register_6 = 0x90, + dr_ste_v1_action_mdfy_fld_register_7 = 0x91, +}; + +static const struct mlx5dr_ste_action_modify_field dr_ste_v1_action_modify_field_arr[] = { + [mlx5_action_in_field_out_smac_47_16] = { + .hw_field = dr_ste_v1_action_mdfy_fld_src_l2_out_0, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_smac_15_0] = { + .hw_field = dr_ste_v1_action_mdfy_fld_src_l2_out_1, .start = 16, .end = 31, + }, + [mlx5_action_in_field_out_ethertype] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l2_out_1, .start = 0, .end = 15, + }, + [mlx5_action_in_field_out_dmac_47_16] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l2_out_0, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_dmac_15_0] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l2_out_1, .start = 16, .end = 31, + }, + [mlx5_action_in_field_out_ip_dscp] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l3_out_0, .start = 18, .end = 23, + }, + [mlx5_action_in_field_out_tcp_flags] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l4_out_1, .start = 16, .end = 24, + .l4_type = dr_ste_action_mdfy_type_l4_tcp, + }, + [mlx5_action_in_field_out_tcp_sport] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l4_out_0, .start = 16, .end = 31, + .l4_type = dr_ste_action_mdfy_type_l4_tcp, + }, + [mlx5_action_in_field_out_tcp_dport] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l4_out_0, .start = 0, .end = 15, + .l4_type = dr_ste_action_mdfy_type_l4_tcp, + }, + [mlx5_action_in_field_out_ip_ttl] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l3_out_0, .start = 8, .end = 15, + .l3_type = dr_ste_action_mdfy_type_l3_ipv4, + }, + [mlx5_action_in_field_out_ipv6_hoplimit] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l3_out_0, .start = 8, .end = 15, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_udp_sport] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l4_out_0, .start = 16, .end = 31, + .l4_type = dr_ste_action_mdfy_type_l4_udp, + }, + [mlx5_action_in_field_out_udp_dport] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l4_out_0, .start = 0, .end = 15, + .l4_type = dr_ste_action_mdfy_type_l4_udp, + }, + [mlx5_action_in_field_out_sipv6_127_96] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_src_out_0, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv6_95_64] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_src_out_1, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv6_63_32] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_src_out_2, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv6_31_0] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_src_out_3, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_127_96] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_dst_out_0, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_95_64] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_dst_out_1, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_63_32] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_dst_out_2, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_dipv6_31_0] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv6_dst_out_3, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv6, + }, + [mlx5_action_in_field_out_sipv4] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv4_out_0, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv4, + }, + [mlx5_action_in_field_out_dipv4] = { + .hw_field = dr_ste_v1_action_mdfy_fld_ipv4_out_1, .start = 0, .end = 31, + .l3_type = dr_ste_action_mdfy_type_l3_ipv4, + }, + [mlx5_action_in_field_metadata_reg_a] = { + .hw_field = dr_ste_v1_action_mdfy_fld_gnrl_purpose, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_b] = { + .hw_field = dr_ste_v1_action_mdfy_fld_metadata_2_cqe, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_0] = { + .hw_field = dr_ste_v1_action_mdfy_fld_register_6, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_1] = { + .hw_field = dr_ste_v1_action_mdfy_fld_register_7, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_2] = { + .hw_field = dr_ste_v1_action_mdfy_fld_register_4, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_3] = { + .hw_field = dr_ste_v1_action_mdfy_fld_register_5, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_4] = { + .hw_field = dr_ste_v1_action_mdfy_fld_register_2, .start = 0, .end = 31, + }, + [mlx5_action_in_field_metadata_reg_c_5] = { + .hw_field = dr_ste_v1_action_mdfy_fld_register_3, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_tcp_seq_num] = { + .hw_field = dr_ste_v1_action_mdfy_fld_tcp_misc_0, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_tcp_ack_num] = { + .hw_field = dr_ste_v1_action_mdfy_fld_tcp_misc_1, .start = 0, .end = 31, + }, + [mlx5_action_in_field_out_first_vid] = { + .hw_field = dr_ste_v1_action_mdfy_fld_l2_out_2, .start = 0, .end = 15, + }, +}; + +static void dr_ste_v1_set_action_set(u8 *d_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data) +{ + shifter += mlx5_modify_header_v1_qw_offset; + mlx5_set(ste_double_action_set_v1, d_action, action_id, dr_ste_v1_action_id_set); + mlx5_set(ste_double_action_set_v1, d_action, destination_dw_offset, hw_field); + mlx5_set(ste_double_action_set_v1, d_action, destination_left_shifter, shifter); + mlx5_set(ste_double_action_set_v1, d_action, destination_length, length); + mlx5_set(ste_double_action_set_v1, d_action, inline_data, data); +} + +static void dr_ste_v1_set_action_add(u8 *d_action, + u8 hw_field, + u8 shifter, + u8 length, + u32 data) +{ + shifter += mlx5_modify_header_v1_qw_offset; + mlx5_set(ste_double_action_add_v1, d_action, action_id, dr_ste_v1_action_id_add); + mlx5_set(ste_double_action_add_v1, d_action, destination_dw_offset, hw_field); + mlx5_set(ste_double_action_add_v1, d_action, destination_left_shifter, shifter); + mlx5_set(ste_double_action_add_v1, d_action, destination_length, length); + mlx5_set(ste_double_action_add_v1, d_action, add_value, data); +} + +static void dr_ste_v1_set_action_copy(u8 *d_action, + u8 dst_hw_field, + u8 dst_shifter, + u8 dst_len, + u8 src_hw_field, + u8 src_shifter) +{ + dst_shifter += mlx5_modify_header_v1_qw_offset; + src_shifter += mlx5_modify_header_v1_qw_offset; + mlx5_set(ste_double_action_copy_v1, d_action, action_id, dr_ste_v1_action_id_copy); + mlx5_set(ste_double_action_copy_v1, d_action, destination_dw_offset, dst_hw_field); + mlx5_set(ste_double_action_copy_v1, d_action, destination_left_shifter, dst_shifter); + mlx5_set(ste_double_action_copy_v1, d_action, destination_length, dst_len); + mlx5_set(ste_double_action_copy_v1, d_action, source_dw_offset, src_hw_field); + mlx5_set(ste_double_action_copy_v1, d_action, source_right_shifter, src_shifter); +} + +#define dr_ste_decap_l3_action_num 8 +#define dr_ste_l2_hdr_max_sz 20 + +static int dr_ste_v1_set_action_decap_l3_list(void *data, + u32 data_sz, + u8 *hw_action, + u32 hw_action_sz, + u16 *used_hw_action_num) +{ + u8 padded_data[dr_ste_l2_hdr_max_sz] = {}; + void *data_ptr = padded_data; + u16 used_actions = 0; + u32 inline_data_sz; + u32 i; + + if (hw_action_sz / dr_ste_action_double_sz < dr_ste_decap_l3_action_num) + return -einval; + + memcpy(padded_data, data, data_sz); + + /* remove l2l3 outer headers */ + mlx5_set(ste_single_action_remove_header_v1, hw_action, action_id, + dr_ste_v1_action_id_remove_header_to_header); + mlx5_set(ste_single_action_remove_header_v1, hw_action, decap, 1); + mlx5_set(ste_single_action_remove_header_v1, hw_action, vni_to_cqe, 1); + mlx5_set(ste_single_action_remove_header_v1, hw_action, end_anchor, + dr_ste_header_anchor_inner_ipv6_ipv4); + hw_action += dr_ste_action_double_sz; + used_actions++; /* remove and nop are a single double action */ + + inline_data_sz = + mlx5_fld_sz_bytes(ste_double_action_insert_with_inline_v1, inline_data); + + /* add the new header inline + 2 extra bytes */ + for (i = 0; i < data_sz / inline_data_sz + 1; i++) { + void *addr_inline; + + mlx5_set(ste_double_action_insert_with_inline_v1, hw_action, action_id, + dr_ste_v1_action_id_insert_inline); + /* the hardware expects here offset to words (2 bytes) */ + mlx5_set(ste_double_action_insert_with_inline_v1, hw_action, start_offset, + i * 2); + + /* copy bytes one by one to avoid endianness problem */ + addr_inline = mlx5_addr_of(ste_double_action_insert_with_inline_v1, + hw_action, inline_data); + memcpy(addr_inline, data_ptr, inline_data_sz); + hw_action += dr_ste_action_double_sz; + data_ptr += inline_data_sz; + used_actions++; + } + + /* remove 2 extra bytes */ + mlx5_set(ste_single_action_remove_header_size_v1, hw_action, action_id, + dr_ste_v1_action_id_remove_by_size); + mlx5_set(ste_single_action_remove_header_size_v1, hw_action, start_offset, data_sz / 2); + /* the hardware expects here size in words (2 bytes) */ + mlx5_set(ste_single_action_remove_header_size_v1, hw_action, remove_size, 1); + used_actions++; + + *used_hw_action_num = used_actions; + + return 0; +} + + .modify_field_arr_sz = array_size(dr_ste_v1_action_modify_field_arr), + .modify_field_arr = dr_ste_v1_action_modify_field_arr, + .set_action_set = &dr_ste_v1_set_action_set, + .set_action_add = &dr_ste_v1_set_action_add, + .set_action_copy = &dr_ste_v1_set_action_copy, + .set_action_decap_l3_list = &dr_ste_v1_set_action_decap_l3_list, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5_ifc_dr_ste_v1.h +enum mlx5_ifc_ste_v1_modify_hdr_offset { + mlx5_modify_header_v1_qw_offset = 0x20, +}; +
|
Networking
|
c349b4137cfd9482f30dcd726748d0c4da1427f3
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, use the right size when writing partial ste into hw
|
in these cases we need to update only the ctrl area of the ste. so it is better to write only the control 32b and avoid copying the unneeded reduced 48b (control 32b + tag 16b).
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 2
| 9
| 5
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c - mlx5dr_send_fill_and_append_ste_send_info(last_ste, dr_ste_size_reduced, + mlx5dr_send_fill_and_append_ste_send_info(last_ste, dr_ste_size_ctrl, - /* copy data to ste, only reduced size, the last 16b (mask) + + /* copy data to ste, only reduced size or control, the last 16b (mask) - memcpy(ste_info->ste->hw_ste, ste_info->data, dr_ste_size_reduced); + if (ste_info->size == dr_ste_size_ctrl) + memcpy(ste_info->ste->hw_ste, ste_info->data, dr_ste_size_ctrl); + else + memcpy(ste_info->ste->hw_ste, ste_info->data, dr_ste_size_reduced); - mlx5dr_send_fill_and_append_ste_send_info(ste_to_update, dr_ste_size_reduced, + mlx5dr_send_fill_and_append_ste_send_info(ste_to_update, dr_ste_size_ctrl, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c - mlx5dr_send_fill_and_append_ste_send_info(prev_ste, dr_ste_size_reduced, 0, + mlx5dr_send_fill_and_append_ste_send_info(prev_ste, dr_ste_size_ctrl, 0,
|
Networking
|
f06d496985f49189dde4506d0ac15494d1a74607
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, use hw specific logic api when writing ste
|
stev0 format and stev1 hw format are different, each has a different order: stev0: ctrl 32b, tag 16b, bitmask 16b stev1: ctrl 32b, bitmask 16b, tag 16b
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 6
| 60
| 13
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_rule.c - ret = mlx5dr_send_postsend_ste(dmn, ste_info->ste, ste_info->data, - ste_info->size, ste_info->offset); - if (ret) - goto out; + ret = mlx5dr_send_postsend_ste(dmn, ste_info->ste, ste_info->data, + ste_info->size, ste_info->offset); + if (ret) + goto out; + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_send.c + mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, data, size); + + mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, formatted_ste, dr_ste_size); + + /* only when we have mask we need to re-arrange the ste */ + mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, + data + (j * dr_ste_size), + dr_ste_size); + u8 *copy_dst; - for (i = 0; i < num_stes; i++) { - u8 *copy_dst; - - /* copy the same ste on the data buffer */ - copy_dst = data + i * dr_ste_size; - memcpy(copy_dst, ste_init_data, dr_ste_size); - - if (update_hw_ste) { - /* copy the reduced ste to hash table ste_arr */ + if (update_hw_ste) { + /* copy the reduced ste to hash table ste_arr */ + for (i = 0; i < num_stes; i++) { + mlx5dr_ste_prepare_for_postsend(dmn->ste_ctx, ste_init_data, dr_ste_size); + + /* copy the same ste on the data buffer */ + for (i = 0; i < num_stes; i++) { + copy_dst = data + i * dr_ste_size; + memcpy(copy_dst, ste_init_data, dr_ste_size); + } + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste_p, u32 ste_size) +{ + if (ste_ctx->prepare_for_postsend) + ste_ctx->prepare_for_postsend(hw_ste_p, ste_size); +} + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h + + /* send */ + void (*prepare_for_postsend)(u8 *hw_ste_p, u32 ste_size); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c +static void dr_ste_v1_prepare_for_postsend(u8 *hw_ste_p, + u32 ste_size) +{ + u8 *tag = hw_ste_p + dr_ste_size_ctrl; + u8 *mask = tag + dr_ste_size_tag; + u8 tmp_tag[dr_ste_size_tag] = {}; + + if (ste_size == dr_ste_size_ctrl) + return; + + warn_on(ste_size != dr_ste_size); + + /* backup tag */ + memcpy(tmp_tag, tag, dr_ste_size_tag); + + /* swap mask and tag both are the same size */ + memcpy(tag, mask, dr_ste_size_mask); + memcpy(mask, tmp_tag, dr_ste_size_tag); +} + + /* send */ + .prepare_for_postsend = &dr_ste_v1_prepare_for_postsend, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h + +void mlx5dr_ste_prepare_for_postsend(struct mlx5dr_ste_ctx *ste_ctx, + u8 *hw_ste_p, u32 ste_size);
|
Networking
|
4fe45e1d31efb07bbf0c80a59c211109e389b8e3
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, copy all 64b whenever replacing ste in the head of miss-list
|
till now the code assumed that need to copy reduced size of the ste because the rest is the mask part which shouldn't be changed. this is not true for all types of hw (like stev1). take all 64b from the new ste and write them in the replaced ste place. this change will make it easier to handle all ste hw types because we have all the data that is about to be written into hw.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 15
| 4
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c -dr_ste_replace_head_ste(struct mlx5dr_ste *ste, struct mlx5dr_ste *next_ste, +dr_ste_replace_head_ste(struct mlx5dr_matcher_rx_tx *nic_matcher, + struct mlx5dr_ste *ste, + struct mlx5dr_ste *next_ste, + u8 hw_ste[dr_ste_size] = {}; + int sb_idx; + /* copy all 64 hw_ste bytes */ + memcpy(hw_ste, ste->hw_ste, dr_ste_size_reduced); + sb_idx = ste->ste_chain_location - 1; + mlx5dr_ste_set_bit_mask(hw_ste, + nic_matcher->ste_builder[sb_idx].bit_mask); + - mlx5dr_send_fill_and_append_ste_send_info(ste, dr_ste_size_reduced, - 0, ste->hw_ste, + mlx5dr_send_fill_and_append_ste_send_info(ste, dr_ste_size, + 0, hw_ste, - dr_ste_replace_head_ste(ste, next_ste, &ste_info_head, + dr_ste_replace_head_ste(nic_matcher, ste, + next_ste, &ste_info_head,
|
Networking
|
8fdac12acf32fa327c2da9ded8a460e606cb74ac
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
net/mlx5: dr, allow sw steering for sw_owner_v2 devices
|
allow sw_owner_v2 based on sw_format_version.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
sw steering for connectx-6dx
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 4
| 29
| 16
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_cmd.c - caps->sw_owner = - mlx5_cap_esw_flowtable_fdb(mdev, - sw_owner); + caps->sw_owner_v2 = mlx5_cap_esw_flowtable_fdb(mdev, sw_owner_v2); + if (!caps->sw_owner_v2) + caps->sw_owner = mlx5_cap_esw_flowtable_fdb(mdev, sw_owner); - caps->rx_sw_owner = mlx5_cap_flowtable_nic_rx(mdev, sw_owner); - caps->max_ft_level = mlx5_cap_flowtable_nic_rx(mdev, max_ft_level); + caps->rx_sw_owner_v2 = mlx5_cap_flowtable_nic_rx(mdev, sw_owner_v2); + caps->tx_sw_owner_v2 = mlx5_cap_flowtable_nic_tx(mdev, sw_owner_v2); + + if (!caps->rx_sw_owner_v2) + caps->rx_sw_owner = mlx5_cap_flowtable_nic_rx(mdev, sw_owner); + if (!caps->tx_sw_owner_v2) + caps->tx_sw_owner = mlx5_cap_flowtable_nic_tx(mdev, sw_owner); - caps->tx_sw_owner = mlx5_cap_flowtable_nic_tx(mdev, sw_owner); + caps->max_ft_level = mlx5_cap_flowtable_nic_rx(mdev, max_ft_level); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_domain.c +#define dr_domain_sw_steering_supported(dmn, dmn_type) \ + ((dmn)->info.caps.dmn_type##_sw_owner || \ + ((dmn)->info.caps.dmn_type##_sw_owner_v2 && \ + (dmn)->info.caps.sw_format_ver <= mlx5_steering_format_connectx_6dx)) + + dmn->info.caps.fdb_sw_owner_v2 = dmn->info.caps.esw_caps.sw_owner_v2; - if (dmn->info.caps.sw_format_ver != mlx5_steering_format_connectx_5) { - mlx5dr_err(dmn, "sw steering is not supported on this device "); - return -eopnotsupp; - } - - if (!dmn->info.caps.rx_sw_owner) + if (!dr_domain_sw_steering_supported(dmn, rx)) - if (!dmn->info.caps.tx_sw_owner) + if (!dr_domain_sw_steering_supported(dmn, tx)) - if (!dmn->info.caps.fdb_sw_owner) + if (!dr_domain_sw_steering_supported(dmn, fdb)) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_types.h - bool sw_owner; + u8 sw_owner:1; + u8 sw_owner_v2:1; + u8 rx_sw_owner_v2:1; + u8 tx_sw_owner_v2:1; + u8 fdb_sw_owner_v2:1; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/mlx5dr.h - return mlx5_cap_esw_flowtable_fdb(dev, sw_owner); + return mlx5_cap_esw_flowtable_fdb(dev, sw_owner) || + (mlx5_cap_esw_flowtable_fdb(dev, sw_owner_v2) && + (mlx5_cap_gen(dev, steering_format_version) <= + mlx5_steering_format_connectx_6dx));
|
Networking
|
64f45c0fc4c71f577506c5a7a7956ae3bc3388ea
|
yevgeny kliteynik
|
drivers
|
net
|
core, ethernet, mellanox, mlx5, steering
|
devlink: prepare code to fill multiple port function attributes
|
prepare code to fill zero or more port function optional attributes. subsequent patch makes use of this to fill more port function attributes.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mlx5 subfunction support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['c']
| 1
| 33
| 31
|
--- diff --git a/net/core/devlink.c b/net/core/devlink.c --- a/net/core/devlink.c +++ b/net/core/devlink.c +static int +devlink_port_fn_hw_addr_fill(struct devlink *devlink, const struct devlink_ops *ops, + struct devlink_port *port, struct sk_buff *msg, + struct netlink_ext_ack *extack, bool *msg_updated) +{ + u8 hw_addr[max_addr_len]; + int hw_addr_len; + int err; + + if (!ops->port_function_hw_addr_get) + return 0; + + err = ops->port_function_hw_addr_get(devlink, port, hw_addr, &hw_addr_len, extack); + if (err) { + if (err == -eopnotsupp) + return 0; + return err; + } + err = nla_put(msg, devlink_port_function_attr_hw_addr, hw_addr_len, hw_addr); + if (err) + return err; + *msg_updated = true; + return 0; +} + - bool empty_nest = true; - int err = 0; + bool msg_updated = false; + int err; - if (ops->port_function_hw_addr_get) { - int hw_addr_len; - u8 hw_addr[max_addr_len]; - - err = ops->port_function_hw_addr_get(devlink, port, hw_addr, &hw_addr_len, extack); - if (err == -eopnotsupp) { - /* port function attributes are optional for a port. if port doesn't - * support function attribute, returning -eopnotsupp is not an error. - */ - err = 0; - goto out; - } else if (err) { - goto out; - } - err = nla_put(msg, devlink_port_function_attr_hw_addr, hw_addr_len, hw_addr); - if (err) - goto out; - empty_nest = false; - } - -out: - if (err || empty_nest) + err = devlink_port_fn_hw_addr_fill(devlink, ops, port, msg, + extack, &msg_updated); + if (err || !msg_updated) - int err; - err = ops->port_function_hw_addr_set(devlink, port, hw_addr, hw_addr_len, extack); - if (err) - return err; - - devlink_port_notify(port, devlink_cmd_port_new); - return 0; + return ops->port_function_hw_addr_set(devlink, port, hw_addr, hw_addr_len, extack); + if (!err) + devlink_port_notify(port, devlink_cmd_port_new);
|
Networking
|
1230d94820c9cf74776eaac4ee45081e33ea1a30
|
parav pandit jiri pirko jiri nvidia com vu pham vuhuong nvidia com
|
net
|
core
| |
devlink: introduce pci sf port flavour and port attribute
|
a pci sub-function (sf) represents a portion of the device similar to pci vf.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mlx5 subfunction support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 3
| 60
| 0
|
--- diff --git a/include/net/devlink.h b/include/net/devlink.h --- a/include/net/devlink.h +++ b/include/net/devlink.h +/** + * struct devlink_port_pci_sf_attrs - devlink port's pci sf attributes + * @controller: associated controller number + * @sf: associated pci sf for of the pci pf for this port. + * @pf: associated pci pf number for this port. + */ +struct devlink_port_pci_sf_attrs { + u32 controller; + u32 sf; + u16 pf; +}; + + * @pci_sf: pci sf port attributes + struct devlink_port_pci_sf_attrs pci_sf; +void devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port, + u32 controller, u16 pf, u32 sf); diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h --- a/include/uapi/linux/devlink.h +++ b/include/uapi/linux/devlink.h + devlink_port_flavour_pci_sf, /* represents eswitch port + * for the pci sf. it is an internal + * port that faces the pci sf. + */ + devlink_attr_port_pci_sf_number, /* u32 */ diff --git a/net/core/devlink.c b/net/core/devlink.c --- a/net/core/devlink.c +++ b/net/core/devlink.c + case devlink_port_flavour_pci_sf: + if (nla_put_u32(msg, devlink_attr_port_controller_number, + attrs->pci_sf.controller) || + nla_put_u16(msg, devlink_attr_port_pci_pf_number, + attrs->pci_sf.pf) || + nla_put_u32(msg, devlink_attr_port_pci_sf_number, + attrs->pci_sf.sf)) + return -emsgsize; + break; +/** + * devlink_port_attrs_pci_sf_set - set pci sf port attributes + * + * @devlink_port: devlink port + * @controller: associated controller number for the devlink port instance + * @pf: associated pf for the devlink port instance + * @sf: associated sf of a pf for the devlink port instance + */ +void devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port, u32 controller, + u16 pf, u32 sf) +{ + struct devlink_port_attrs *attrs = &devlink_port->attrs; + int ret; + + if (warn_on(devlink_port->registered)) + return; + ret = __devlink_port_attrs_set(devlink_port, + devlink_port_flavour_pci_sf); + if (ret) + return; + attrs->pci_sf.controller = controller; + attrs->pci_sf.pf = pf; + attrs->pci_sf.sf = sf; +} +export_symbol_gpl(devlink_port_attrs_pci_sf_set); + + case devlink_port_flavour_pci_sf: + n = snprintf(name, len, "pf%usf%u", attrs->pci_sf.pf, + attrs->pci_sf.sf); + break;
|
Networking
|
b8288837ef6bdaac331752b401f5ca3b59b37430
|
parav pandit
|
include
|
uapi
|
linux
|
devlink: support add and delete devlink port
|
extended devlink interface for the user to add and delete a port. extend devlink to connect user requests to driver to add/delete a port in the device.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mlx5 subfunction support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 2
| 173
| 0
|
--- diff --git a/include/net/devlink.h b/include/net/devlink.h --- a/include/net/devlink.h +++ b/include/net/devlink.h +struct devlink_port_new_attrs { + enum devlink_port_flavour flavour; + unsigned int port_index; + u32 controller; + u32 sfnum; + u16 pfnum; + u8 port_index_valid:1, + controller_valid:1, + sfnum_valid:1; +}; + + /** + * port_new() - add a new port function of a specified flavor + * @devlink: devlink instance + * @attrs: attributes of the new port + * @extack: extack for reporting error messages + * @new_port_index: index of the new port + * + * devlink core will call this device driver function upon user request + * to create a new port function of a specified flavor and optional + * attributes + * + * notes: + * - called without devlink instance lock being held. drivers must + * implement own means of synchronization + * - on success, drivers must register a port with devlink core + * + * return: 0 on success, negative value otherwise. + */ + int (*port_new)(struct devlink *devlink, + const struct devlink_port_new_attrs *attrs, + struct netlink_ext_ack *extack, + unsigned int *new_port_index); + /** + * port_del() - delete a port function + * @devlink: devlink instance + * @port_index: port function index to delete + * @extack: extack for reporting error messages + * + * devlink core will call this device driver function upon user request + * to delete a previously created port function + * + * notes: + * - called without devlink instance lock being held. drivers must + * implement own means of synchronization + * - on success, drivers must unregister the corresponding devlink + * port + * + * return: 0 on success, negative value otherwise. + */ + int (*port_del)(struct devlink *devlink, unsigned int port_index, + struct netlink_ext_ack *extack); diff --git a/net/core/devlink.c b/net/core/devlink.c --- a/net/core/devlink.c +++ b/net/core/devlink.c +static int devlink_port_new_notifiy(struct devlink *devlink, + unsigned int port_index, + struct genl_info *info) +{ + struct devlink_port *devlink_port; + struct sk_buff *msg; + int err; + + msg = nlmsg_new(nlmsg_default_size, gfp_kernel); + if (!msg) + return -enomem; + + mutex_lock(&devlink->lock); + devlink_port = devlink_port_get_by_index(devlink, port_index); + if (!devlink_port) { + err = -enodev; + goto out; + } + + err = devlink_nl_port_fill(msg, devlink, devlink_port, + devlink_cmd_new, info->snd_portid, + info->snd_seq, 0, null); + if (err) + goto out; + + err = genlmsg_reply(msg, info); + mutex_unlock(&devlink->lock); + return err; + +out: + mutex_unlock(&devlink->lock); + nlmsg_free(msg); + return err; +} + +static int devlink_nl_cmd_port_new_doit(struct sk_buff *skb, + struct genl_info *info) +{ + struct netlink_ext_ack *extack = info->extack; + struct devlink_port_new_attrs new_attrs = {}; + struct devlink *devlink = info->user_ptr[0]; + unsigned int new_port_index; + int err; + + if (!devlink->ops->port_new || !devlink->ops->port_del) + return -eopnotsupp; + + if (!info->attrs[devlink_attr_port_flavour] || + !info->attrs[devlink_attr_port_pci_pf_number]) { + nl_set_err_msg_mod(extack, "port flavour or pci pf are not specified"); + return -einval; + } + new_attrs.flavour = nla_get_u16(info->attrs[devlink_attr_port_flavour]); + new_attrs.pfnum = + nla_get_u16(info->attrs[devlink_attr_port_pci_pf_number]); + + if (info->attrs[devlink_attr_port_index]) { + /* port index of the new port being created by driver. */ + new_attrs.port_index = + nla_get_u32(info->attrs[devlink_attr_port_index]); + new_attrs.port_index_valid = true; + } + if (info->attrs[devlink_attr_port_controller_number]) { + new_attrs.controller = + nla_get_u16(info->attrs[devlink_attr_port_controller_number]); + new_attrs.controller_valid = true; + } + if (new_attrs.flavour == devlink_port_flavour_pci_sf && + info->attrs[devlink_attr_port_pci_sf_number]) { + new_attrs.sfnum = nla_get_u32(info->attrs[devlink_attr_port_pci_sf_number]); + new_attrs.sfnum_valid = true; + } + + err = devlink->ops->port_new(devlink, &new_attrs, extack, + &new_port_index); + if (err) + return err; + + err = devlink_port_new_notifiy(devlink, new_port_index, info); + if (err && err != -enodev) { + /* fail to send the response; destroy newly created port. */ + devlink->ops->port_del(devlink, new_port_index, extack); + } + return err; +} + +static int devlink_nl_cmd_port_del_doit(struct sk_buff *skb, + struct genl_info *info) +{ + struct netlink_ext_ack *extack = info->extack; + struct devlink *devlink = info->user_ptr[0]; + unsigned int port_index; + + if (!devlink->ops->port_del) + return -eopnotsupp; + + if (!info->attrs[devlink_attr_port_index]) { + nl_set_err_msg_mod(extack, "port index is not specified"); + return -einval; + } + port_index = nla_get_u32(info->attrs[devlink_attr_port_index]); + + return devlink->ops->port_del(devlink, port_index, extack); +} + + [devlink_attr_port_flavour] = { .type = nla_u16 }, + [devlink_attr_port_pci_pf_number] = { .type = nla_u16 }, + [devlink_attr_port_pci_sf_number] = { .type = nla_u32 }, + [devlink_attr_port_controller_number] = { .type = nla_u32 }, + { + .cmd = devlink_cmd_port_new, + .doit = devlink_nl_cmd_port_new_doit, + .flags = genl_admin_perm, + .internal_flags = devlink_nl_flag_no_lock, + }, + { + .cmd = devlink_cmd_port_del, + .doit = devlink_nl_cmd_port_del_doit, + .flags = genl_admin_perm, + .internal_flags = devlink_nl_flag_no_lock, + },
|
Networking
|
cd76dcd68d96aa5bbc63b7ef25a87a1dbea3d73c
|
parav pandit
|
net
|
core
| |
devlink: support get and set state of port function
|
devlink port function can be in active or inactive state. allow users to get and set port function's state.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mlx5 subfunction support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'c']
| 3
| 141
| 1
|
--- diff --git a/include/net/devlink.h b/include/net/devlink.h --- a/include/net/devlink.h +++ b/include/net/devlink.h + /** + * port_fn_state_get() - get the state of a port function + * @devlink: devlink instance + * @port: the devlink port + * @state: admin configured state + * @opstate: current operational state + * @extack: extack for reporting error messages + * + * reports the admin and operational state of a devlink port function + * + * return: 0 on success, negative value otherwise. + */ + int (*port_fn_state_get)(struct devlink *devlink, + struct devlink_port *port, + enum devlink_port_fn_state *state, + enum devlink_port_fn_opstate *opstate, + struct netlink_ext_ack *extack); + /** + * port_fn_state_set() - set the admin state of a port function + * @devlink: devlink instance + * @port: the devlink port + * @state: admin state + * @extack: extack for reporting error messages + * + * set the admin state of a devlink port function + * + * return: 0 on success, negative value otherwise. + */ + int (*port_fn_state_set)(struct devlink *devlink, + struct devlink_port *port, + enum devlink_port_fn_state state, + struct netlink_ext_ack *extack); diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h --- a/include/uapi/linux/devlink.h +++ b/include/uapi/linux/devlink.h + devlink_port_fn_attr_state, /* u8 */ + devlink_port_fn_attr_opstate, /* u8 */ +enum devlink_port_fn_state { + devlink_port_fn_state_inactive, + devlink_port_fn_state_active, +}; + +/** + * enum devlink_port_fn_opstate - indicates operational state of the function + * @devlink_port_fn_opstate_attached: driver is attached to the function. + * for graceful tear down of the function, after inactivation of the + * function, user should wait for operational state to turn detached. + * @devlink_port_fn_opstate_detached: driver is detached from the function. + * it is safe to delete the port. + */ +enum devlink_port_fn_opstate { + devlink_port_fn_opstate_detached, + devlink_port_fn_opstate_attached, +}; + diff --git a/net/core/devlink.c b/net/core/devlink.c --- a/net/core/devlink.c +++ b/net/core/devlink.c + [devlink_port_fn_attr_state] = + nla_policy_range(nla_u8, devlink_port_fn_state_inactive, + devlink_port_fn_state_active), +static bool +devlink_port_fn_state_valid(enum devlink_port_fn_state state) +{ + return state == devlink_port_fn_state_inactive || + state == devlink_port_fn_state_active; +} + +static bool +devlink_port_fn_opstate_valid(enum devlink_port_fn_opstate opstate) +{ + return opstate == devlink_port_fn_opstate_detached || + opstate == devlink_port_fn_opstate_attached; +} + +static int +devlink_port_fn_state_fill(struct devlink *devlink, + const struct devlink_ops *ops, + struct devlink_port *port, struct sk_buff *msg, + struct netlink_ext_ack *extack, + bool *msg_updated) +{ + enum devlink_port_fn_opstate opstate; + enum devlink_port_fn_state state; + int err; + + if (!ops->port_fn_state_get) + return 0; + + err = ops->port_fn_state_get(devlink, port, &state, &opstate, extack); + if (err) { + if (err == -eopnotsupp) + return 0; + return err; + } + if (!devlink_port_fn_state_valid(state)) { + warn_on_once(1); + nl_set_err_msg_mod(extack, "invalid state read from driver"); + return -einval; + } + if (!devlink_port_fn_opstate_valid(opstate)) { + warn_on_once(1); + nl_set_err_msg_mod(extack, + "invalid operational state read from driver"); + return -einval; + } + if (nla_put_u8(msg, devlink_port_fn_attr_state, state) || + nla_put_u8(msg, devlink_port_fn_attr_opstate, opstate)) + return -emsgsize; + *msg_updated = true; + return 0; +} + + if (err) + goto out; + err = devlink_port_fn_state_fill(devlink, ops, port, msg, extack, + &msg_updated); +out: +static int devlink_port_fn_state_set(struct devlink *devlink, + struct devlink_port *port, + const struct nlattr *attr, + struct netlink_ext_ack *extack) +{ + enum devlink_port_fn_state state; + const struct devlink_ops *ops; + + state = nla_get_u8(attr); + ops = devlink->ops; + if (!ops->port_fn_state_set) { + nl_set_err_msg_mod(extack, + "function does not support state setting"); + return -eopnotsupp; + } + return ops->port_fn_state_set(devlink, port, state, extack); +} + - if (attr) + if (attr) { + if (err) + return err; + } + /* keep this as the last function attribute set, so that when + * multiple port function attributes are set along with state, + * those can be applied first before activating the state. + */ + attr = tb[devlink_port_fn_attr_state]; + if (attr) + err = devlink_port_fn_state_set(devlink, port, attr, extack);
|
Networking
|
a556dded9c23c51c82654f1ebe389cbc0bc22057
|
parav pandit
|
include
|
uapi
|
linux
|
net/mlx5: introduce vhca state event notifier
|
vhca state events indicates change in the state of the vhca that may occur due to a sf allocation, deallocation or enabling/disabling the sf hca.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mlx5 subfunction support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['h', 'kconfig', 'c', 'makefile']
| 12
| 422
| 0
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/kconfig b/drivers/net/ethernet/mellanox/mlx5/core/kconfig --- a/drivers/net/ethernet/mellanox/mlx5/core/kconfig +++ b/drivers/net/ethernet/mellanox/mlx5/core/kconfig + +config mlx5_sf + bool "mellanox technologies subfunction device support using auxiliary device" + depends on mlx5_core && mlx5_core_en + default n + help + build support for subfuction device in the nic. a mellanox subfunction + device can support rdma, netdevice and vdpa device. + it is similar to a sriov vf but it doesn't require sriov support. diff --git a/drivers/net/ethernet/mellanox/mlx5/core/makefile b/drivers/net/ethernet/mellanox/mlx5/core/makefile --- a/drivers/net/ethernet/mellanox/mlx5/core/makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/makefile +# +# sf device +# +mlx5_core-$(config_mlx5_sf) += sf/vhca_event.o diff --git a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c --- a/drivers/net/ethernet/mellanox/mlx5/core/cmd.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/cmd.c + case mlx5_cmd_op_query_vhca_state: + case mlx5_cmd_op_modify_vhca_state: + mlx5_command_str_case(query_vhca_state); + mlx5_command_str_case(modify_vhca_state); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c + if (mlx5_cap_gen_max(dev, vhca_state)) + async_event_mask |= (1ull << mlx5_event_type_vhca_state_change); + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/events.c b/drivers/net/ethernet/mellanox/mlx5/core/events.c --- a/drivers/net/ethernet/mellanox/mlx5/core/events.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/events.c + case mlx5_event_type_vhca_state_change: + return "mlx5_event_type_vhca_state_change"; + +void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work) +{ + queue_work(dev->priv.events->wq, work); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c +#include "sf/vhca_event.h" + mlx5_vhca_state_cap_handle(dev, set_hca_cap); + + err = mlx5_vhca_event_init(dev); + if (err) { + mlx5_core_err(dev, "failed to init vhca event notifier %d ", err); + goto err_fpga_cleanup; + } + +err_fpga_cleanup: + mlx5_fpga_cleanup(dev); + mlx5_vhca_event_cleanup(dev); + mlx5_vhca_event_start(dev); + + mlx5_vhca_event_stop(dev); + mlx5_vhca_event_stop(dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h + +void mlx5_events_work_enqueue(struct mlx5_core_dev *dev, struct work_struct *work); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event.h b/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event.h --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/mlx5_ifc_vhca_event.h +/* spdx-license-identifier: gpl-2.0 or linux-openib */ +/* copyright (c) 2020 mellanox technologies ltd */ + +#ifndef __mlx5_ifc_vhca_event_h__ +#define __mlx5_ifc_vhca_event_h__ + +enum mlx5_ifc_vhca_state { + mlx5_vhca_state_invalid = 0x0, + mlx5_vhca_state_allocated = 0x1, + mlx5_vhca_state_active = 0x2, + mlx5_vhca_state_in_use = 0x3, + mlx5_vhca_state_teardown_request = 0x4, +}; + +struct mlx5_ifc_vhca_state_context_bits { + u8 arm_change_event[0x1]; + u8 reserved_at_1[0xb]; + u8 vhca_state[0x4]; + u8 reserved_at_10[0x10]; + + u8 sw_function_id[0x20]; + + u8 reserved_at_40[0x80]; +}; + +struct mlx5_ifc_query_vhca_state_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; + + struct mlx5_ifc_vhca_state_context_bits vhca_state_context; +}; + +struct mlx5_ifc_query_vhca_state_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 embedded_cpu_function[0x1]; + u8 reserved_at_41[0xf]; + u8 function_id[0x10]; + + u8 reserved_at_60[0x20]; +}; + +struct mlx5_ifc_vhca_state_field_select_bits { + u8 reserved_at_0[0x1e]; + u8 sw_function_id[0x1]; + u8 arm_change_event[0x1]; +}; + +struct mlx5_ifc_modify_vhca_state_out_bits { + u8 status[0x8]; + u8 reserved_at_8[0x18]; + + u8 syndrome[0x20]; + + u8 reserved_at_40[0x40]; +}; + +struct mlx5_ifc_modify_vhca_state_in_bits { + u8 opcode[0x10]; + u8 uid[0x10]; + + u8 reserved_at_20[0x10]; + u8 op_mod[0x10]; + + u8 embedded_cpu_function[0x1]; + u8 reserved_at_41[0xf]; + u8 function_id[0x10]; + + struct mlx5_ifc_vhca_state_field_select_bits vhca_state_field_select; + + struct mlx5_ifc_vhca_state_context_bits vhca_state_context; +}; + +#endif diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h b/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h +/* spdx-license-identifier: gpl-2.0 or linux-openib */ +/* copyright (c) 2020 mellanox technologies ltd */ + +#ifndef __mlx5_sf_h__ +#define __mlx5_sf_h__ + +#include <linux/mlx5/driver.h> + +static inline u16 mlx5_sf_start_function_id(const struct mlx5_core_dev *dev) +{ + return mlx5_cap_gen(dev, sf_base_id); +} + +#ifdef config_mlx5_sf + +static inline bool mlx5_sf_supported(const struct mlx5_core_dev *dev) +{ + return mlx5_cap_gen(dev, sf); +} + +static inline u16 mlx5_sf_max_functions(const struct mlx5_core_dev *dev) +{ + if (!mlx5_sf_supported(dev)) + return 0; + if (mlx5_cap_gen(dev, max_num_sf)) + return mlx5_cap_gen(dev, max_num_sf); + else + return 1 << mlx5_cap_gen(dev, log_max_sf); +} + +#else + +static inline bool mlx5_sf_supported(const struct mlx5_core_dev *dev) +{ + return false; +} + +static inline u16 mlx5_sf_max_functions(const struct mlx5_core_dev *dev) +{ + return 0; +} + +#endif + +#endif diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/vhca_event.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/vhca_event.c --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/vhca_event.c +// spdx-license-identifier: gpl-2.0 or linux-openib +/* copyright (c) 2020 mellanox technologies ltd */ + +#include <linux/mlx5/driver.h> +#include "mlx5_ifc_vhca_event.h" +#include "mlx5_core.h" +#include "vhca_event.h" +#include "ecpf.h" + +struct mlx5_vhca_state_notifier { + struct mlx5_core_dev *dev; + struct mlx5_nb nb; + struct blocking_notifier_head n_head; +}; + +struct mlx5_vhca_event_work { + struct work_struct work; + struct mlx5_vhca_state_notifier *notifier; + struct mlx5_vhca_state_event event; +}; + +int mlx5_cmd_query_vhca_state(struct mlx5_core_dev *dev, u16 function_id, + bool ecpu, u32 *out, u32 outlen) +{ + u32 in[mlx5_st_sz_dw(query_vhca_state_in)] = {}; + + mlx5_set(query_vhca_state_in, in, opcode, mlx5_cmd_op_query_vhca_state); + mlx5_set(query_vhca_state_in, in, function_id, function_id); + mlx5_set(query_vhca_state_in, in, embedded_cpu_function, ecpu); + + return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen); +} + +static int mlx5_cmd_modify_vhca_state(struct mlx5_core_dev *dev, u16 function_id, + bool ecpu, u32 *in, u32 inlen) +{ + u32 out[mlx5_st_sz_dw(modify_vhca_state_out)] = {}; + + mlx5_set(modify_vhca_state_in, in, opcode, mlx5_cmd_op_modify_vhca_state); + mlx5_set(modify_vhca_state_in, in, function_id, function_id); + mlx5_set(modify_vhca_state_in, in, embedded_cpu_function, ecpu); + + return mlx5_cmd_exec(dev, in, inlen, out, sizeof(out)); +} + +int mlx5_modify_vhca_sw_id(struct mlx5_core_dev *dev, u16 function_id, bool ecpu, u32 sw_fn_id) +{ + u32 out[mlx5_st_sz_dw(modify_vhca_state_out)] = {}; + u32 in[mlx5_st_sz_dw(modify_vhca_state_in)] = {}; + + mlx5_set(modify_vhca_state_in, in, opcode, mlx5_cmd_op_modify_vhca_state); + mlx5_set(modify_vhca_state_in, in, function_id, function_id); + mlx5_set(modify_vhca_state_in, in, embedded_cpu_function, ecpu); + mlx5_set(modify_vhca_state_in, in, vhca_state_field_select.sw_function_id, 1); + mlx5_set(modify_vhca_state_in, in, vhca_state_context.sw_function_id, sw_fn_id); + + return mlx5_cmd_exec_inout(dev, modify_vhca_state, in, out); +} + +int mlx5_vhca_event_arm(struct mlx5_core_dev *dev, u16 function_id, bool ecpu) +{ + u32 in[mlx5_st_sz_dw(modify_vhca_state_in)] = {}; + + mlx5_set(modify_vhca_state_in, in, vhca_state_context.arm_change_event, 1); + mlx5_set(modify_vhca_state_in, in, vhca_state_field_select.arm_change_event, 1); + + return mlx5_cmd_modify_vhca_state(dev, function_id, ecpu, in, sizeof(in)); +} + +static void +mlx5_vhca_event_notify(struct mlx5_core_dev *dev, struct mlx5_vhca_state_event *event) +{ + u32 out[mlx5_st_sz_dw(query_vhca_state_out)] = {}; + int err; + + err = mlx5_cmd_query_vhca_state(dev, event->function_id, event->ecpu, out, sizeof(out)); + if (err) + return; + + event->sw_function_id = mlx5_get(query_vhca_state_out, out, + vhca_state_context.sw_function_id); + event->new_vhca_state = mlx5_get(query_vhca_state_out, out, + vhca_state_context.vhca_state); + + mlx5_vhca_event_arm(dev, event->function_id, event->ecpu); + + blocking_notifier_call_chain(&dev->priv.vhca_state_notifier->n_head, 0, event); +} + +static void mlx5_vhca_state_work_handler(struct work_struct *_work) +{ + struct mlx5_vhca_event_work *work = container_of(_work, struct mlx5_vhca_event_work, work); + struct mlx5_vhca_state_notifier *notifier = work->notifier; + struct mlx5_core_dev *dev = notifier->dev; + + mlx5_vhca_event_notify(dev, &work->event); +} + +static int +mlx5_vhca_state_change_notifier(struct notifier_block *nb, unsigned long type, void *data) +{ + struct mlx5_vhca_state_notifier *notifier = + mlx5_nb_cof(nb, struct mlx5_vhca_state_notifier, nb); + struct mlx5_vhca_event_work *work; + struct mlx5_eqe *eqe = data; + + work = kzalloc(sizeof(*work), gfp_atomic); + if (!work) + return notify_done; + init_work(&work->work, &mlx5_vhca_state_work_handler); + work->notifier = notifier; + work->event.function_id = be16_to_cpu(eqe->data.vhca_state.function_id); + work->event.ecpu = be16_to_cpu(eqe->data.vhca_state.ec_function); + mlx5_events_work_enqueue(notifier->dev, &work->work); + return notify_ok; +} + +void mlx5_vhca_state_cap_handle(struct mlx5_core_dev *dev, void *set_hca_cap) +{ + if (!mlx5_vhca_event_supported(dev)) + return; + + mlx5_set(cmd_hca_cap, set_hca_cap, vhca_state, 1); + mlx5_set(cmd_hca_cap, set_hca_cap, event_on_vhca_state_allocated, 1); + mlx5_set(cmd_hca_cap, set_hca_cap, event_on_vhca_state_active, 1); + mlx5_set(cmd_hca_cap, set_hca_cap, event_on_vhca_state_in_use, 1); + mlx5_set(cmd_hca_cap, set_hca_cap, event_on_vhca_state_teardown_request, 1); +} + +int mlx5_vhca_event_init(struct mlx5_core_dev *dev) +{ + struct mlx5_vhca_state_notifier *notifier; + + if (!mlx5_vhca_event_supported(dev)) + return 0; + + notifier = kzalloc(sizeof(*notifier), gfp_kernel); + if (!notifier) + return -enomem; + + dev->priv.vhca_state_notifier = notifier; + notifier->dev = dev; + blocking_init_notifier_head(¬ifier->n_head); + mlx5_nb_init(¬ifier->nb, mlx5_vhca_state_change_notifier, vhca_state_change); + return 0; +} + +void mlx5_vhca_event_cleanup(struct mlx5_core_dev *dev) +{ + if (!mlx5_vhca_event_supported(dev)) + return; + + kfree(dev->priv.vhca_state_notifier); + dev->priv.vhca_state_notifier = null; +} + +void mlx5_vhca_event_start(struct mlx5_core_dev *dev) +{ + struct mlx5_vhca_state_notifier *notifier; + + if (!dev->priv.vhca_state_notifier) + return; + + notifier = dev->priv.vhca_state_notifier; + mlx5_eq_notifier_register(dev, ¬ifier->nb); +} + +void mlx5_vhca_event_stop(struct mlx5_core_dev *dev) +{ + struct mlx5_vhca_state_notifier *notifier; + + if (!dev->priv.vhca_state_notifier) + return; + + notifier = dev->priv.vhca_state_notifier; + mlx5_eq_notifier_unregister(dev, ¬ifier->nb); +} + +int mlx5_vhca_event_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb) +{ + if (!dev->priv.vhca_state_notifier) + return -eopnotsupp; + return blocking_notifier_chain_register(&dev->priv.vhca_state_notifier->n_head, nb); +} + +void mlx5_vhca_event_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb) +{ + blocking_notifier_chain_unregister(&dev->priv.vhca_state_notifier->n_head, nb); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/vhca_event.h b/drivers/net/ethernet/mellanox/mlx5/core/sf/vhca_event.h --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/vhca_event.h +/* spdx-license-identifier: gpl-2.0 or linux-openib */ +/* copyright (c) 2020 mellanox technologies ltd */ + +#ifndef __mlx5_vhca_event_h__ +#define __mlx5_vhca_event_h__ + +#ifdef config_mlx5_sf + +struct mlx5_vhca_state_event { + u16 function_id; + u16 sw_function_id; + u8 new_vhca_state; + bool ecpu; +}; + +static inline bool mlx5_vhca_event_supported(const struct mlx5_core_dev *dev) +{ + return mlx5_cap_gen_max(dev, vhca_state); +} + +void mlx5_vhca_state_cap_handle(struct mlx5_core_dev *dev, void *set_hca_cap); +int mlx5_vhca_event_init(struct mlx5_core_dev *dev); +void mlx5_vhca_event_cleanup(struct mlx5_core_dev *dev); +void mlx5_vhca_event_start(struct mlx5_core_dev *dev); +void mlx5_vhca_event_stop(struct mlx5_core_dev *dev); +int mlx5_vhca_event_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); +void mlx5_vhca_event_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); +int mlx5_modify_vhca_sw_id(struct mlx5_core_dev *dev, u16 function_id, bool ecpu, u32 sw_fn_id); +int mlx5_vhca_event_arm(struct mlx5_core_dev *dev, u16 function_id, bool ecpu); +int mlx5_cmd_query_vhca_state(struct mlx5_core_dev *dev, u16 function_id, + bool ecpu, u32 *out, u32 outlen); +#else + +static inline void mlx5_vhca_state_cap_handle(struct mlx5_core_dev *dev, void *set_hca_cap) +{ +} + +static inline int mlx5_vhca_event_init(struct mlx5_core_dev *dev) +{ + return 0; +} + +static inline void mlx5_vhca_event_cleanup(struct mlx5_core_dev *dev) +{ +} + +static inline void mlx5_vhca_event_start(struct mlx5_core_dev *dev) +{ +} + +static inline void mlx5_vhca_event_stop(struct mlx5_core_dev *dev) +{ +} + +#endif + +#endif diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h +struct mlx5_vhca_state_notifier; +#ifdef config_mlx5_sf + struct mlx5_vhca_state_notifier *vhca_state_notifier; +#endif
|
Networking
|
f3196bb0f14c0ffb5089c15668bda196c98d3900
|
parav pandit
|
include
|
linux
|
core, ethernet, mellanox, mlx5, sf
|
net/mlx5: sf, add auxiliary device support
|
introduce api to add and delete an auxiliary device for an sf. each sf has its own dedicated window in the pci bar 2.
|
this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
|
add mlx5 subfunction support
|
['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
|
['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
|
['mlx5/mlx5e ']
|
['makefile', 'h', 'c', 'rst']
| 6
| 312
| 1
|
--- diff --git a/documentation/networking/device_drivers/ethernet/mellanox/mlx5.rst b/documentation/networking/device_drivers/ethernet/mellanox/mlx5.rst --- a/documentation/networking/device_drivers/ethernet/mellanox/mlx5.rst +++ b/documentation/networking/device_drivers/ethernet/mellanox/mlx5.rst +**config_mlx5_sf=(y/n)** + +| build support for subfunction. +| subfunctons are more light weight than pci sriov vfs. choosing this option +| will enable support for creating subfunction devices. diff --git a/drivers/net/ethernet/mellanox/mlx5/core/makefile b/drivers/net/ethernet/mellanox/mlx5/core/makefile --- a/drivers/net/ethernet/mellanox/mlx5/core/makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/makefile -mlx5_core-$(config_mlx5_sf) += sf/vhca_event.o +mlx5_core-$(config_mlx5_sf) += sf/vhca_event.o sf/dev/dev.o diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c +#include "sf/dev/dev.h" + mlx5_sf_dev_table_create(dev); + + mlx5_sf_dev_table_destroy(dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c +// spdx-license-identifier: gpl-2.0 or linux-openib +/* copyright (c) 2020 mellanox technologies ltd */ + +#include <linux/mlx5/driver.h> +#include <linux/mlx5/device.h> +#include "mlx5_core.h" +#include "dev.h" +#include "sf/vhca_event.h" +#include "sf/sf.h" +#include "sf/mlx5_ifc_vhca_event.h" +#include "ecpf.h" + +struct mlx5_sf_dev_table { + struct xarray devices; + unsigned int max_sfs; + phys_addr_t base_address; + u64 sf_bar_length; + struct notifier_block nb; + struct mlx5_core_dev *dev; +}; + +static bool mlx5_sf_dev_supported(const struct mlx5_core_dev *dev) +{ + return mlx5_cap_gen(dev, sf) && mlx5_vhca_event_supported(dev); +} + +static ssize_t sfnum_show(struct device *dev, struct device_attribute *attr, char *buf) +{ + struct auxiliary_device *adev = container_of(dev, struct auxiliary_device, dev); + struct mlx5_sf_dev *sf_dev = container_of(adev, struct mlx5_sf_dev, adev); + + return scnprintf(buf, page_size, "%u ", sf_dev->sfnum); +} +static device_attr_ro(sfnum); + +static struct attribute *sf_device_attrs[] = { + &dev_attr_sfnum.attr, + null, +}; + +static const struct attribute_group sf_attr_group = { + .attrs = sf_device_attrs, +}; + +static const struct attribute_group *sf_attr_groups[2] = { + &sf_attr_group, + null +}; + +static void mlx5_sf_dev_release(struct device *device) +{ + struct auxiliary_device *adev = container_of(device, struct auxiliary_device, dev); + struct mlx5_sf_dev *sf_dev = container_of(adev, struct mlx5_sf_dev, adev); + + mlx5_adev_idx_free(adev->id); + kfree(sf_dev); +} + +static void mlx5_sf_dev_remove(struct mlx5_sf_dev *sf_dev) +{ + auxiliary_device_delete(&sf_dev->adev); + auxiliary_device_uninit(&sf_dev->adev); +} + +static void mlx5_sf_dev_add(struct mlx5_core_dev *dev, u16 sf_index, u32 sfnum) +{ + struct mlx5_sf_dev_table *table = dev->priv.sf_dev_table; + struct mlx5_sf_dev *sf_dev; + struct pci_dev *pdev; + int err; + int id; + + id = mlx5_adev_idx_alloc(); + if (id < 0) { + err = id; + goto add_err; + } + + sf_dev = kzalloc(sizeof(*sf_dev), gfp_kernel); + if (!sf_dev) { + mlx5_adev_idx_free(id); + err = -enomem; + goto add_err; + } + pdev = dev->pdev; + sf_dev->adev.id = id; + sf_dev->adev.name = mlx5_sf_dev_id_name; + sf_dev->adev.dev.release = mlx5_sf_dev_release; + sf_dev->adev.dev.parent = &pdev->dev; + sf_dev->adev.dev.groups = sf_attr_groups; + sf_dev->sfnum = sfnum; + sf_dev->parent_mdev = dev; + + if (!table->max_sfs) { + mlx5_adev_idx_free(id); + kfree(sf_dev); + err = -eopnotsupp; + goto add_err; + } + sf_dev->bar_base_addr = table->base_address + (sf_index * table->sf_bar_length); + + err = auxiliary_device_init(&sf_dev->adev); + if (err) { + mlx5_adev_idx_free(id); + kfree(sf_dev); + goto add_err; + } + + err = auxiliary_device_add(&sf_dev->adev); + if (err) { + put_device(&sf_dev->adev.dev); + goto add_err; + } + + err = xa_insert(&table->devices, sf_index, sf_dev, gfp_kernel); + if (err) + goto xa_err; + return; + +xa_err: + mlx5_sf_dev_remove(sf_dev); +add_err: + mlx5_core_err(dev, "sf dev: fail device add for index=%d sfnum=%d err=%d ", + sf_index, sfnum, err); +} + +static void mlx5_sf_dev_del(struct mlx5_core_dev *dev, struct mlx5_sf_dev *sf_dev, u16 sf_index) +{ + struct mlx5_sf_dev_table *table = dev->priv.sf_dev_table; + + xa_erase(&table->devices, sf_index); + mlx5_sf_dev_remove(sf_dev); +} + +static int +mlx5_sf_dev_state_change_handler(struct notifier_block *nb, unsigned long event_code, void *data) +{ + struct mlx5_sf_dev_table *table = container_of(nb, struct mlx5_sf_dev_table, nb); + const struct mlx5_vhca_state_event *event = data; + struct mlx5_sf_dev *sf_dev; + u16 sf_index; + + sf_index = event->function_id - mlx5_cap_gen(table->dev, sf_base_id); + sf_dev = xa_load(&table->devices, sf_index); + switch (event->new_vhca_state) { + case mlx5_vhca_state_allocated: + if (sf_dev) + mlx5_sf_dev_del(table->dev, sf_dev, sf_index); + break; + case mlx5_vhca_state_teardown_request: + if (sf_dev) + mlx5_sf_dev_del(table->dev, sf_dev, sf_index); + else + mlx5_core_err(table->dev, + "sf dev: teardown state for invalid dev index=%d fn_id=0x%x ", + sf_index, event->sw_function_id); + break; + case mlx5_vhca_state_active: + if (!sf_dev) + mlx5_sf_dev_add(table->dev, sf_index, event->sw_function_id); + break; + default: + break; + } + return 0; +} + +static int mlx5_sf_dev_vhca_arm_all(struct mlx5_sf_dev_table *table) +{ + struct mlx5_core_dev *dev = table->dev; + u16 max_functions; + u16 function_id; + int err = 0; + bool ecpu; + int i; + + max_functions = mlx5_sf_max_functions(dev); + function_id = mlx5_cap_gen(dev, sf_base_id); + ecpu = mlx5_read_embedded_cpu(dev); + /* arm the vhca context as the vhca event notifier */ + for (i = 0; i < max_functions; i++) { + err = mlx5_vhca_event_arm(dev, function_id, ecpu); + if (err) + return err; + + function_id++; + } + return 0; +} + +void mlx5_sf_dev_table_create(struct mlx5_core_dev *dev) +{ + struct mlx5_sf_dev_table *table; + unsigned int max_sfs; + int err; + + if (!mlx5_sf_dev_supported(dev) || !mlx5_vhca_event_supported(dev)) + return; + + table = kzalloc(sizeof(*table), gfp_kernel); + if (!table) { + err = -enomem; + goto table_err; + } + + table->nb.notifier_call = mlx5_sf_dev_state_change_handler; + table->dev = dev; + if (mlx5_cap_gen(dev, max_num_sf)) + max_sfs = mlx5_cap_gen(dev, max_num_sf); + else + max_sfs = 1 << mlx5_cap_gen(dev, log_max_sf); + table->sf_bar_length = 1 << (mlx5_cap_gen(dev, log_min_sf_size) + 12); + table->base_address = pci_resource_start(dev->pdev, 2); + table->max_sfs = max_sfs; + xa_init(&table->devices); + dev->priv.sf_dev_table = table; + + err = mlx5_vhca_event_notifier_register(dev, &table->nb); + if (err) + goto vhca_err; + err = mlx5_sf_dev_vhca_arm_all(table); + if (err) + goto arm_err; + mlx5_core_dbg(dev, "sf dev: max sf devices=%d ", max_sfs); + return; + +arm_err: + mlx5_vhca_event_notifier_unregister(dev, &table->nb); +vhca_err: + table->max_sfs = 0; + kfree(table); + dev->priv.sf_dev_table = null; +table_err: + mlx5_core_err(dev, "sf dev table create err = %d ", err); +} + +static void mlx5_sf_dev_destroy_all(struct mlx5_sf_dev_table *table) +{ + struct mlx5_sf_dev *sf_dev; + unsigned long index; + + xa_for_each(&table->devices, index, sf_dev) { + xa_erase(&table->devices, index); + mlx5_sf_dev_remove(sf_dev); + } +} + +void mlx5_sf_dev_table_destroy(struct mlx5_core_dev *dev) +{ + struct mlx5_sf_dev_table *table = dev->priv.sf_dev_table; + + if (!table) + return; + + mlx5_vhca_event_notifier_unregister(dev, &table->nb); + + /* now that event handler is not running, it is safe to destroy + * the sf device without race. + */ + mlx5_sf_dev_destroy_all(table); + + warn_on(!xa_empty(&table->devices)); + kfree(table); + dev->priv.sf_dev_table = null; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h +/* spdx-license-identifier: gpl-2.0 or linux-openib */ +/* copyright (c) 2020 mellanox technologies ltd */ + +#ifndef __mlx5_sf_dev_h__ +#define __mlx5_sf_dev_h__ + +#ifdef config_mlx5_sf + +#include <linux/auxiliary_bus.h> + +#define mlx5_sf_dev_id_name "sf" + +struct mlx5_sf_dev { + struct auxiliary_device adev; + struct mlx5_core_dev *parent_mdev; + phys_addr_t bar_base_addr; + u32 sfnum; +}; + +void mlx5_sf_dev_table_create(struct mlx5_core_dev *dev); +void mlx5_sf_dev_table_destroy(struct mlx5_core_dev *dev); + +#else + +static inline void mlx5_sf_dev_table_create(struct mlx5_core_dev *dev) +{ +} + +static inline void mlx5_sf_dev_table_destroy(struct mlx5_core_dev *dev) +{ +} + +#endif + +#endif diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h +struct mlx5_sf_dev_table; + struct mlx5_sf_dev_table *sf_dev_table;
|
Networking
|
90d010b8634b89a97ca3b7aa6a88fd566fc77717
|
parav pandit
|
documentation
|
networking
|
core, dev, device_drivers, ethernet, mellanox, mlx5, sf
|
net/mlx5: sf, add auxiliary device driver
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add auxiliary device driver for mlx5 subfunction auxiliary device.
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this release allows to map an uid to a different one in a mount; it also adds support for selecting the preemption model at runtime; support for a low-overhead memory error detector designed to be used in production; support for the acrn hypervisor designed for embedded systems; btrfs initial support for zoned devices, subpage blocks sizes and performance improvements; support for eager nfs writes; support for a thermal power management to control the surface temperature of embedded devices in an unified way; the napi polling can be moved to a kernel thread; and support for non-blocking path lookups. as always, there are many other features, new drivers, improvements and fixes.
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add mlx5 subfunction support
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['core (various)', 'file systems', 'memory management', 'block layer', 'tracing, perf and bpf', 'virtualization', 'cryptography', 'security', 'networking', 'architectures x86 arm risc-v powerpc mips csky s390 pa-risc c6x']
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['graphics', 'power management', 'storage', 'drivers in the staging area', 'networking', 'audio', 'tablets, touch screens, keyboards, mouses', 'tv tuners, webcams, video capturers', 'universal serial bus', 'serial peripheral interface (spi)', 'watchdog', 'serial', 'cpu frequency scaling', 'device voltage and frequency scaling', 'voltage, current regulators, power capping, power supply', 'real time clock (rtc)', 'pin controllers (pinctrl)', 'multi media card (mmc)', 'memory technology devices (mtd)', 'industrial i/o (iio)', 'multi function devices (mfd)', 'pulse-width modulation (pwm)', 'inter-integrated circuit (i2c + i3c)', 'hardware monitoring (hwmon)', 'general purpose i/o (gpio)', 'leds', 'dma engines', 'cryptography hardware acceleration', 'pci', 'non-transparent bridge (ntb)', 'thunderbolt', 'clock', 'phy ("physical layer" framework)', 'cxl (compute express link)', 'various']
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['mlx5/mlx5e ']
|
['h', 'c', 'makefile']
| 10
| 187
| 6
|
--- diff --git a/drivers/net/ethernet/mellanox/mlx5/core/makefile b/drivers/net/ethernet/mellanox/mlx5/core/makefile --- a/drivers/net/ethernet/mellanox/mlx5/core/makefile +++ b/drivers/net/ethernet/mellanox/mlx5/core/makefile -mlx5_core-$(config_mlx5_sf) += sf/vhca_event.o sf/dev/dev.o +mlx5_core-$(config_mlx5_sf) += sf/vhca_event.o sf/dev/dev.o sf/dev/driver.o diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +#include "sf/dev/dev.h" + bool sf_dev_allocated; + + sf_dev_allocated = mlx5_sf_dev_allocated(dev); + if (sf_dev_allocated) { + /* reload results in deleting sf device which further results in + * unregistering devlink instance while holding devlink_mutext. + * hence, do not support reload. + */ + nl_set_err_msg_mod(extack, "reload is unsupported when sfs are allocated "); + return -eopnotsupp; + } diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c - eq_table->irq_table = dev->priv.irq_table; + eq_table->irq_table = mlx5_irq_table_get(dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/ethernet/mellanox/mlx5/core/main.c --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c -#define mlx5_default_prof 2 -static int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) +int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx) -static void mlx5_mdev_uninit(struct mlx5_core_dev *dev) +void mlx5_mdev_uninit(struct mlx5_core_dev *dev) + err = mlx5_sf_driver_register(); + if (err) + goto err_sf; + +err_sf: + pci_unregister_driver(&mlx5_core_driver); + mlx5_sf_driver_unregister(); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +#define mlx5_default_prof 2 + +struct mlx5_irq_table *mlx5_irq_table_get(struct mlx5_core_dev *dev); +static inline bool mlx5_core_is_sf(const struct mlx5_core_dev *dev) +{ + return dev->coredev_type == mlx5_coredev_sf; +} + +int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx); +void mlx5_mdev_uninit(struct mlx5_core_dev *dev); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c --- a/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c + if (mlx5_core_is_sf(dev)) + return 0; + + if (mlx5_core_is_sf(dev)) + return; + + if (mlx5_core_is_sf(dev)) + return 0; + + if (mlx5_core_is_sf(dev)) + return; + +struct mlx5_irq_table *mlx5_irq_table_get(struct mlx5_core_dev *dev) +{ +#ifdef config_mlx5_sf + if (mlx5_core_is_sf(dev)) + return dev->priv.parent_mdev->priv.irq_table; +#endif + return dev->priv.irq_table; +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.c +bool mlx5_sf_dev_allocated(const struct mlx5_core_dev *dev) +{ + struct mlx5_sf_dev_table *table = dev->priv.sf_dev_table; + + if (!mlx5_sf_dev_supported(dev)) + return false; + + return !xa_empty(&table->devices); +} + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/dev.h + struct mlx5_core_dev *mdev; +int mlx5_sf_driver_register(void); +void mlx5_sf_driver_unregister(void); + +bool mlx5_sf_dev_allocated(const struct mlx5_core_dev *dev); + +static inline int mlx5_sf_driver_register(void) +{ + return 0; +} + +static inline void mlx5_sf_driver_unregister(void) +{ +} + +static inline bool mlx5_sf_dev_allocated(const struct mlx5_core_dev *dev) +{ + return 0; +} + diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c --- /dev/null +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/driver.c +// spdx-license-identifier: gpl-2.0 or linux-openib +/* copyright (c) 2020 mellanox technologies ltd */ + +#include <linux/mlx5/driver.h> +#include <linux/mlx5/device.h> +#include "mlx5_core.h" +#include "dev.h" +#include "devlink.h" + +static int mlx5_sf_dev_probe(struct auxiliary_device *adev, const struct auxiliary_device_id *id) +{ + struct mlx5_sf_dev *sf_dev = container_of(adev, struct mlx5_sf_dev, adev); + struct mlx5_core_dev *mdev; + struct devlink *devlink; + int err; + + devlink = mlx5_devlink_alloc(); + if (!devlink) + return -enomem; + + mdev = devlink_priv(devlink); + mdev->device = &adev->dev; + mdev->pdev = sf_dev->parent_mdev->pdev; + mdev->bar_addr = sf_dev->bar_base_addr; + mdev->iseg_base = sf_dev->bar_base_addr; + mdev->coredev_type = mlx5_coredev_sf; + mdev->priv.parent_mdev = sf_dev->parent_mdev; + mdev->priv.adev_idx = adev->id; + sf_dev->mdev = mdev; + + err = mlx5_mdev_init(mdev, mlx5_default_prof); + if (err) { + mlx5_core_warn(mdev, "mlx5_mdev_init on err=%d ", err); + goto mdev_err; + } + + mdev->iseg = ioremap(mdev->iseg_base, sizeof(*mdev->iseg)); + if (!mdev->iseg) { + mlx5_core_warn(mdev, "remap error "); + goto remap_err; + } + + err = mlx5_load_one(mdev, true); + if (err) { + mlx5_core_warn(mdev, "mlx5_load_one err=%d ", err); + goto load_one_err; + } + return 0; + +load_one_err: + iounmap(mdev->iseg); +remap_err: + mlx5_mdev_uninit(mdev); +mdev_err: + mlx5_devlink_free(devlink); + return err; +} + +static void mlx5_sf_dev_remove(struct auxiliary_device *adev) +{ + struct mlx5_sf_dev *sf_dev = container_of(adev, struct mlx5_sf_dev, adev); + struct devlink *devlink; + + devlink = priv_to_devlink(sf_dev->mdev); + mlx5_unload_one(sf_dev->mdev, true); + iounmap(sf_dev->mdev->iseg); + mlx5_mdev_uninit(sf_dev->mdev); + mlx5_devlink_free(devlink); +} + +static void mlx5_sf_dev_shutdown(struct auxiliary_device *adev) +{ + struct mlx5_sf_dev *sf_dev = container_of(adev, struct mlx5_sf_dev, adev); + + mlx5_unload_one(sf_dev->mdev, false); +} + +static const struct auxiliary_device_id mlx5_sf_dev_id_table[] = { + { .name = mlx5_adev_name "." mlx5_sf_dev_id_name, }, + { }, +}; + +module_device_table(auxiliary, mlx5_sf_dev_id_table); + +static struct auxiliary_driver mlx5_sf_driver = { + .name = mlx5_sf_dev_id_name, + .probe = mlx5_sf_dev_probe, + .remove = mlx5_sf_dev_remove, + .shutdown = mlx5_sf_dev_shutdown, + .id_table = mlx5_sf_dev_id_table, +}; + +int mlx5_sf_driver_register(void) +{ + return auxiliary_driver_register(&mlx5_sf_driver); +} + +void mlx5_sf_driver_unregister(void) +{ + auxiliary_driver_unregister(&mlx5_sf_driver); +} diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h - mlx5_coredev_vf + mlx5_coredev_vf, + mlx5_coredev_sf, + struct mlx5_core_dev *parent_mdev;
|
Networking
|
1958fc2f0712ae771bfd2351b55e5a5b6b0bcfa4
|
parav pandit
|
include
|
linux
|
core, dev, ethernet, mellanox, mlx5, sf
|
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